# ! [doc = "Peripheral access API for MSPM0L130X microcontrollers (generated using svd2rust v0.30.2 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.30.2/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
# ! [deny (dead_code)]
# ! [deny (improper_ctypes)]
# ! [deny (missing_docs)]
# ! [deny (no_mangle_generic_items)]
# ! [deny (non_shorthand_field_patterns)]
# ! [deny (overflowing_literals)]
# ! [deny (path_statements)]
# ! [deny (patterns_in_fns_without_body)]
# ! [deny (private_bounds)]
# ! [deny (private_interfaces)]
# ! [deny (unconditional_recursion)]
# ! [deny (unused_allocation)]
# ! [deny (unused_comparisons)]
# ! [deny (unused_parens)]
# ! [deny (while_true)]
# ! [allow (non_camel_case_types)]
# ! [allow (non_snake_case)]
# ! [no_std]
use core :: ops :: Deref ; use core :: marker :: PhantomData ; # [doc = r"Number available in the NVIC for configuring priority"]
pub const NVIC_PRIO_BITS : u8 = 3 ; pub use cortex_m :: peripheral :: Peripherals as CorePeripherals ; # [cfg (feature = "rt")]
pub use cortex_m_rt :: interrupt ; # [cfg (feature = "rt")]
pub use self :: Interrupt as interrupt ; pub use cortex_m :: peripheral :: { CBP , CPUID , DCB , DWT , FPB , ITM , MPU , NVIC , SCB , SYST , TPIU , } ; # [allow (unused_imports)]
use generic :: * ; # [doc = r"Common register and bit access and modify traits"]
pub mod generic { use core :: marker ; # [doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
pub trait RawReg : Copy + Default + From < bool > + core :: ops :: BitOr < Output = Self > + core :: ops :: BitAnd < Output = Self > + core :: ops :: BitOrAssign + core :: ops :: BitAndAssign + core :: ops :: Not < Output = Self > + core :: ops :: Shl < u8 , Output = Self > { # [doc = " Mask for bits of width `WI`"]
fn mask < const WI : u8 > () -> Self ; # [doc = " Mask for bits of width 1"]
fn one () -> Self ; } macro_rules ! raw_reg { ($ U : ty , $ size : literal , $ mask : ident) => { impl RawReg for $ U { # [inline (always)]
fn mask < const WI : u8 > () -> Self { $ mask ::< WI > () } # [inline (always)]
fn one () -> Self { 1 } } const fn $ mask < const WI : u8 > () -> $ U { <$ U >:: MAX >> ($ size - WI) } impl FieldSpec for $ U { type Ux = $ U ; } } ; } raw_reg ! (u8 , 8 , mask_u8) ; raw_reg ! (u16 , 16 , mask_u16) ; raw_reg ! (u32 , 32 , mask_u32) ; raw_reg ! (u64 , 64 , mask_u64) ; # [doc = " Raw register type"]
pub trait RegisterSpec { # [doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
type Ux : RawReg ; } # [doc = " Raw field type"]
pub trait FieldSpec : Sized { # [doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
type Ux : Copy + PartialEq + From < Self > ; } # [doc = " Trait implemented by readable registers to enable the `read` method."]
# [doc = ""]
# [doc = " Registers marked with `Writable` can be also be `modify`'ed."]
pub trait Readable : RegisterSpec { } # [doc = " Trait implemented by writeable registers."]
# [doc = ""]
# [doc = " This enables the  `write`, `write_with_zero` and `reset` methods."]
# [doc = ""]
# [doc = " Registers marked with `Readable` can be also be `modify`'ed."]
pub trait Writable : RegisterSpec { # [doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux ; # [doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux ; } # [doc = " Reset value of the register."]
# [doc = ""]
# [doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
# [doc = " register by using the `reset` method."]
pub trait Resettable : RegisterSpec { # [doc = " Reset value of the register."]
const RESET_VALUE : Self :: Ux ; # [doc = " Reset value of the register."]
# [inline (always)]
fn reset_value () -> Self :: Ux { Self :: RESET_VALUE } } # [doc = " This structure provides volatile access to registers."]
# [repr (transparent)]
pub struct Reg < REG : RegisterSpec > { register : vcell :: VolatileCell < REG :: Ux > , _marker : marker :: PhantomData < REG > , } unsafe impl < REG : RegisterSpec > Send for Reg < REG > where REG :: Ux : Send { } impl < REG : RegisterSpec > Reg < REG > { # [doc = " Returns the underlying memory address of register."]
# [doc = ""]
# [doc = " ```ignore"]
# [doc = " let reg_ptr = periph.reg.as_ptr();"]
# [doc = " ```"]
# [inline (always)]
pub fn as_ptr (& self) -> * mut REG :: Ux { self . register . as_ptr () } } impl < REG : Readable > Reg < REG > { # [doc = " Reads the contents of a `Readable` register."]
# [doc = ""]
# [doc = " You can read the raw contents of a register by using `bits`:"]
# [doc = " ```ignore"]
# [doc = " let bits = periph.reg.read().bits();"]
# [doc = " ```"]
# [doc = " or get the content of a particular field of a register:"]
# [doc = " ```ignore"]
# [doc = " let reader = periph.reg.read();"]
# [doc = " let bits = reader.field1().bits();"]
# [doc = " let flag = reader.field2().bit_is_set();"]
# [doc = " ```"]
# [inline (always)]
pub fn read (& self) -> R < REG > { R { bits : self . register . get () , _reg : marker :: PhantomData , } } } impl < REG : Resettable + Writable > Reg < REG > { # [doc = " Writes the reset value to `Writable` register."]
# [doc = ""]
# [doc = " Resets the register to its initial state."]
# [inline (always)]
pub fn reset (& self) { self . register . set (REG :: RESET_VALUE) } # [doc = " Writes bits to a `Writable` register."]
# [doc = ""]
# [doc = " You can write raw bits into a register:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
# [doc = " ```"]
# [doc = " or write only the fields you need:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| w"]
# [doc = "     .field1().bits(newfield1bits)"]
# [doc = "     .field2().set_bit()"]
# [doc = "     .field3().variant(VARIANT)"]
# [doc = " );"]
# [doc = " ```"]
# [doc = " or an alternative way of saying the same:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.write(|w| {"]
# [doc = "     w.field1().bits(newfield1bits);"]
# [doc = "     w.field2().set_bit();"]
# [doc = "     w.field3().variant(VARIANT)"]
# [doc = " });"]
# [doc = " ```"]
# [doc = " In the latter case, other fields will be set to their reset value."]
# [inline (always)]
pub fn write < F > (& self , f : F) where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { self . register . set (f (& mut W { bits : REG :: RESET_VALUE & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , }) . bits ,) ; } } impl < REG : Writable > Reg < REG > { # [doc = " Writes 0 to a `Writable` register."]
# [doc = ""]
# [doc = " Similar to `write`, but unused bits will contain 0."]
# [doc = ""]
# [doc = " # Safety"]
# [doc = ""]
# [doc = " Unsafe to use with registers which don't allow to write 0."]
# [inline (always)]
pub unsafe fn write_with_zero < F > (& self , f : F) where F : FnOnce (& mut W < REG >) -> & mut W < REG > , { self . register . set (f (& mut W { bits : REG :: Ux :: default () , _reg : marker :: PhantomData , }) . bits ,) ; } } impl < REG : Readable + Writable > Reg < REG > { # [doc = " Modifies the contents of the register by reading and then writing it."]
# [doc = ""]
# [doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
# [doc = "    r.bits() | 3"]
# [doc = " ) });"]
# [doc = " ```"]
# [doc = " or"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|_, w| w"]
# [doc = "     .field1().bits(newfield1bits)"]
# [doc = "     .field2().set_bit()"]
# [doc = "     .field3().variant(VARIANT)"]
# [doc = " );"]
# [doc = " ```"]
# [doc = " or an alternative way of saying the same:"]
# [doc = " ```ignore"]
# [doc = " periph.reg.modify(|_, w| {"]
# [doc = "     w.field1().bits(newfield1bits);"]
# [doc = "     w.field2().set_bit();"]
# [doc = "     w.field3().variant(VARIANT)"]
# [doc = " });"]
# [doc = " ```"]
# [doc = " Other fields will have the value they had before the call to `modify`."]
# [inline (always)]
pub fn modify < F > (& self , f : F) where for < 'w > F : FnOnce (& R < REG > , & 'w mut W < REG >) -> & 'w mut W < REG > , { let bits = self . register . get () ; self . register . set (f (& R { bits , _reg : marker :: PhantomData , } , & mut W { bits : bits & ! REG :: ONE_TO_MODIFY_FIELDS_BITMAP | REG :: ZERO_TO_MODIFY_FIELDS_BITMAP , _reg : marker :: PhantomData , } ,) . bits ,) ; } } # [doc (hidden)]
pub mod raw { use super :: { marker , BitM , FieldSpec , RegisterSpec , Unsafe , Writable } ; pub struct R < REG : RegisterSpec > { pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct W < REG : RegisterSpec > { # [doc = "Writable bits"]
pub (crate) bits : REG :: Ux , pub (super) _reg : marker :: PhantomData < REG > , } pub struct FieldReader < FI = u8 > where FI : FieldSpec , { pub (crate) bits : FI :: Ux , _reg : marker :: PhantomData < FI > , } impl < FI : FieldSpec > FieldReader < FI > { # [doc = " Creates a new instance of the reader."]
# [allow (unused)]
# [inline (always)]
pub (crate) const fn new (bits : FI :: Ux) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct BitReader < FI = bool > { pub (crate) bits : bool , _reg : marker :: PhantomData < FI > , } impl < FI > BitReader < FI > { # [doc = " Creates a new instance of the reader."]
# [allow (unused)]
# [inline (always)]
pub (crate) const fn new (bits : bool) -> Self { Self { bits , _reg : marker :: PhantomData , } } } pub struct FieldWriter < 'a , REG , const WI : u8 , const O : u8 , FI = u8 , Safety = Unsafe > where REG : Writable + RegisterSpec , FI : FieldSpec , { pub (crate) w : & 'a mut W < REG > , _field : marker :: PhantomData < (FI , Safety) > , } impl < 'a , REG , const WI : u8 , const O : u8 , FI , Safety > FieldWriter < 'a , REG , WI , O , FI , Safety > where REG : Writable + RegisterSpec , FI : FieldSpec , { # [doc = " Creates a new instance of the writer"]
# [allow (unused)]
# [inline (always)]
pub (crate) fn new (w : & 'a mut W < REG >) -> Self { Self { w , _field : marker :: PhantomData , } } } pub struct BitWriter < 'a , REG , const O : u8 , FI = bool , M = BitM > where REG : Writable + RegisterSpec , bool : From < FI > , { pub (crate) w : & 'a mut W < REG > , _field : marker :: PhantomData < (FI , M) > , } impl < 'a , REG , const O : u8 , FI , M > BitWriter < 'a , REG , O , FI , M > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Creates a new instance of the writer"]
# [allow (unused)]
# [inline (always)]
pub (crate) fn new (w : & 'a mut W < REG >) -> Self { Self { w , _field : marker :: PhantomData , } } } } # [doc = " Register reader."]
# [doc = ""]
# [doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
# [doc = " method."]
pub type R < REG > = raw :: R < REG > ; impl < REG : RegisterSpec > R < REG > { # [doc = " Reads raw bits from register."]
# [inline (always)]
pub const fn bits (& self) -> REG :: Ux { self . bits } } impl < REG : RegisterSpec , FI > PartialEq < FI > for R < REG > where REG :: Ux : PartialEq , FI : Copy , REG :: Ux : From < FI > , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& REG :: Ux :: from (* other)) } } # [doc = " Register writer."]
# [doc = ""]
# [doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
pub type W < REG > = raw :: W < REG > ; # [doc = " Field reader."]
# [doc = ""]
# [doc = " Result of the `read` methods of fields."]
pub type FieldReader < FI = u8 > = raw :: FieldReader < FI > ; # [doc = " Bit-wise field reader"]
pub type BitReader < FI = bool > = raw :: BitReader < FI > ; impl < FI : FieldSpec > FieldReader < FI > { # [doc = " Reads raw bits from field."]
# [inline (always)]
pub const fn bits (& self) -> FI :: Ux { self . bits } } impl < FI > PartialEq < FI > for FieldReader < FI > where FI : FieldSpec + Copy , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& FI :: Ux :: from (* other)) } } impl < FI > PartialEq < FI > for BitReader < FI > where FI : Copy , bool : From < FI > , { # [inline (always)]
fn eq (& self , other : & FI) -> bool { self . bits . eq (& bool :: from (* other)) } } impl < FI > BitReader < FI > { # [doc = " Value of the field as raw bits."]
# [inline (always)]
pub const fn bit (& self) -> bool { self . bits } # [doc = " Returns `true` if the bit is clear (0)."]
# [inline (always)]
pub const fn bit_is_clear (& self) -> bool { ! self . bit () } # [doc = " Returns `true` if the bit is set (1)."]
# [inline (always)]
pub const fn bit_is_set (& self) -> bool { self . bit () } } # [doc (hidden)]
pub struct Safe ; # [doc (hidden)]
pub struct Unsafe ; # [doc = " Write field Proxy with unsafe `bits`"]
pub type FieldWriter < 'a , REG , const WI : u8 , const O : u8 , FI = u8 > = raw :: FieldWriter < 'a , REG , WI , O , FI , Unsafe > ; # [doc = " Write field Proxy with safe `bits`"]
pub type FieldWriterSafe < 'a , REG , const WI : u8 , const O : u8 , FI = u8 > = raw :: FieldWriter < 'a , REG , WI , O , FI , Safe > ; impl < 'a , REG , const WI : u8 , const OF : u8 , FI > FieldWriter < 'a , REG , WI , OF , FI > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { # [doc = " Field width"]
pub const WIDTH : u8 = WI ; # [doc = " Writes raw bits to the field"]
# [doc = ""]
# [doc = " # Safety"]
# [doc = ""]
# [doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (self , value : FI :: Ux) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: mask :: < WI > () << OF) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: mask :: < WI > ()) << OF ; self . w } # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> & 'a mut W < REG > { unsafe { self . bits (FI :: Ux :: from (variant)) } } } impl < 'a , REG , const WI : u8 , const OF : u8 , FI > FieldWriterSafe < 'a , REG , WI , OF , FI > where REG : Writable + RegisterSpec , FI : FieldSpec , REG :: Ux : From < FI :: Ux > , { # [doc = " Field width"]
pub const WIDTH : u8 = WI ; # [doc = " Writes raw bits to the field"]
# [inline (always)]
pub fn bits (self , value : FI :: Ux) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: mask :: < WI > () << OF) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: mask :: < WI > ()) << OF ; self . w } # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> & 'a mut W < REG > { self . bits (FI :: Ux :: from (variant)) } } macro_rules ! bit_proxy { ($ writer : ident , $ mwv : ident) => { # [doc (hidden)]
pub struct $ mwv ; # [doc = " Bit-wise write field proxy"]
pub type $ writer <'a , REG , const O : u8 , FI = bool > = raw :: BitWriter <'a , REG , O , FI , $ mwv >; impl <'a , REG , const OF : u8 , FI > $ writer <'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI >, { # [doc = " Field width"]
pub const WIDTH : u8 = 1 ; # [doc = " Writes bit to the field"]
# [inline (always)]
pub fn bit (self , value : bool) -> &'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << OF) ; self . w . bits |= (REG :: Ux :: from (value) & REG :: Ux :: one ()) << OF ; self . w } # [doc = " Writes `variant` to the field"]
# [inline (always)]
pub fn variant (self , variant : FI) -> &'a mut W < REG > { self . bit (bool :: from (variant)) } } } ; } bit_proxy ! (BitWriter , BitM) ; bit_proxy ! (BitWriter1S , Bit1S) ; bit_proxy ! (BitWriter0C , Bit0C) ; bit_proxy ! (BitWriter1C , Bit1C) ; bit_proxy ! (BitWriter0S , Bit0S) ; bit_proxy ! (BitWriter1T , Bit1T) ; bit_proxy ! (BitWriter0T , Bit0T) ; impl < 'a , REG , const OF : u8 , FI > BitWriter < 'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Sets the field bit"]
# [inline (always)]
pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << OF ; self . w } # [doc = " Clears the field bit"]
# [inline (always)]
pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << OF) ; self . w } } impl < 'a , REG , const OF : u8 , FI > BitWriter1S < 'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Sets the field bit"]
# [inline (always)]
pub fn set_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << OF ; self . w } } impl < 'a , REG , const OF : u8 , FI > BitWriter0C < 'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = " Clears the field bit"]
# [inline (always)]
pub fn clear_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << OF) ; self . w } } impl < 'a , REG , const OF : u8 , FI > BitWriter1C < 'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Clears the field bit by passing one"]
# [inline (always)]
pub fn clear_bit_by_one (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << OF ; self . w } } impl < 'a , REG , const OF : u8 , FI > BitWriter0S < 'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Sets the field bit by passing zero"]
# [inline (always)]
pub fn set_bit_by_zero (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << OF) ; self . w } } impl < 'a , REG , const OF : u8 , FI > BitWriter1T < 'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Toggle the field bit by passing one"]
# [inline (always)]
pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits |= REG :: Ux :: one () << OF ; self . w } } impl < 'a , REG , const OF : u8 , FI > BitWriter0T < 'a , REG , OF , FI > where REG : Writable + RegisterSpec , bool : From < FI > , { # [doc = "Toggle the field bit by passing zero"]
# [inline (always)]
pub fn toggle_bit (self) -> & 'a mut W < REG > { self . w . bits &= ! (REG :: Ux :: one () << OF) ; self . w } } } # [cfg (feature = "rt")]
extern "C" { fn INT_GROUP0 () ; fn INT_GROUP1 () ; fn TIMG1 () ; fn ADC0 () ; fn SPI0 () ; fn UART1 () ; fn UART0 () ; fn TIMG0 () ; fn TIMG2 () ; fn TIMG4 () ; fn I2C0 () ; fn I2C1 () ; fn DMA () ; } # [doc (hidden)]
pub union Vector { _handler : unsafe extern "C" fn () , _reserved : u32 , } # [cfg (feature = "rt")]
# [doc (hidden)]
# [link_section = ".vector_table.interrupts"]
# [no_mangle]
pub static __INTERRUPTS : [Vector ; 32]
= [Vector { _handler : INT_GROUP0 } , Vector { _handler : INT_GROUP1 } , Vector { _handler : TIMG1 } , Vector { _reserved : 0 } , Vector { _handler : ADC0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _handler : SPI0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _handler : UART1 } , Vector { _reserved : 0 } , Vector { _handler : UART0 } , Vector { _handler : TIMG0 } , Vector { _reserved : 0 } , Vector { _handler : TIMG2 } , Vector { _reserved : 0 } , Vector { _handler : TIMG4 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _handler : I2C0 } , Vector { _handler : I2C1 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _reserved : 0 } , Vector { _handler : DMA } ,]
; # [doc = r"Enumeration of all the interrupts."]
# [derive (Copy , Clone , Debug , PartialEq , Eq)]
# [repr (u16)]
pub enum Interrupt { # [doc = "0 - 0x00000040"]
INT_GROUP0 = 0 , # [doc = "1 - 0x00000044"]
INT_GROUP1 = 1 , # [doc = "2 - 0x00000048"]
TIMG1 = 2 , # [doc = "4 - 0x00000050"]
ADC0 = 4 , # [doc = "9 - 0x00000064"]
SPI0 = 9 , # [doc = "13 - 0x00000074"]
UART1 = 13 , # [doc = "15 - 0x0000007C"]
UART0 = 15 , # [doc = "16 - 0x00000080"]
TIMG0 = 16 , # [doc = "18 - 0x00000088"]
TIMG2 = 18 , # [doc = "20 - 0x00000090"]
TIMG4 = 20 , # [doc = "24 - 0x000000A0"]
I2C0 = 24 , # [doc = "25 - 0x000000A4"]
I2C1 = 25 , # [doc = "31 - 0x000000BC"]
DMA = 31 , } unsafe impl cortex_m :: interrupt :: InterruptNumber for Interrupt { # [inline (always)]
fn number (self) -> u16 { self as u16 } } # [doc = "PERIPHERALREGION"]
pub struct UART0 { _marker : PhantomData < * const () > } unsafe impl Send for UART0 { } impl UART0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const uart0 :: RegisterBlock = 0x4010_8000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const uart0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for UART0 { type Target = uart0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for UART0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("UART0") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod uart0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , # [doc = "0x808 - Peripheral Clock Configuration Register"]
pub clkcfg : CLKCFG , _reserved3 : [u8 ; 0x08]
, # [doc = "0x814 - Status Register"]
pub gprcm_stat : GPRCM_STAT , _reserved4 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1008 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved6 : [u8 ; 0x0c]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub int_event0_iidx : INT_EVENT0_IIDX , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub int_event0_imask : INT_EVENT0_IMASK , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub int_event0_ris : INT_EVENT0_RIS , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub int_event0_mis : INT_EVENT0_MIS , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub int_event0_iset : INT_EVENT0_ISET , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub int_event0_iclr : INT_EVENT0_ICLR , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1050 - Interrupt index"]
pub int_event1_iidx : INT_EVENT1_IIDX , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1058 - Interrupt mask"]
pub int_event1_imask : INT_EVENT1_IMASK , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1060 - Raw interrupt status"]
pub int_event1_ris : INT_EVENT1_RIS , _reserved16 : [u8 ; 0x04]
, # [doc = "0x1068 - Masked interrupt status"]
pub int_event1_mis : INT_EVENT1_MIS , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1070 - Interrupt set"]
pub int_event1_iset : INT_EVENT1_ISET , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1078 - Interrupt clear"]
pub int_event1_iclr : INT_EVENT1_ICLR , _reserved19 : [u8 ; 0x04]
, # [doc = "0x1080 - Interrupt index"]
pub int_event2_iidx : INT_EVENT2_IIDX , _reserved20 : [u8 ; 0x04]
, # [doc = "0x1088 - Interrupt mask"]
pub int_event2_imask : INT_EVENT2_IMASK , _reserved21 : [u8 ; 0x04]
, # [doc = "0x1090 - Raw interrupt status"]
pub int_event2_ris : INT_EVENT2_RIS , _reserved22 : [u8 ; 0x04]
, # [doc = "0x1098 - Masked interrupt status"]
pub int_event2_mis : INT_EVENT2_MIS , _reserved23 : [u8 ; 0x04]
, # [doc = "0x10a0 - Interrupt set"]
pub int_event2_iset : INT_EVENT2_ISET , _reserved24 : [u8 ; 0x04]
, # [doc = "0x10a8 - Interrupt clear"]
pub int_event2_iclr : INT_EVENT2_ICLR , _reserved25 : [u8 ; 0x34]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved26 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - UART Control Register 0"]
pub ctl0 : CTL0 , # [doc = "0x1104 - UART Line Control Register"]
pub lcrh : LCRH , # [doc = "0x1108 - UART Status Register"]
pub stat : STAT , # [doc = "0x110c - UART Interrupt FIFO Level Select Register"]
pub ifls : IFLS , # [doc = "0x1110 - UART Integer Baud-Rate Divisor Register"]
pub ibrd : IBRD , # [doc = "0x1114 - UART Fractional Baud-Rate Divisor Register"]
pub fbrd : FBRD , # [doc = "0x1118 - Glitch Filter Control"]
pub gfctl : GFCTL , _reserved34 : [u8 ; 0x04]
, # [doc = "0x1120 - UART Transmit Data Register"]
pub txdata : TXDATA , # [doc = "0x1124 - UART Receive Data Register"]
pub rxdata : RXDATA , _reserved36 : [u8 ; 0x08]
, # [doc = "0x1130 - UART LIN Mode Counter Register"]
pub lincnt : LINCNT , # [doc = "0x1134 - UART LIN Mode Control Register"]
pub linctl : LINCTL , # [doc = "0x1138 - UART LIN Mode Capture 0 Register"]
pub linc0 : LINC0 , # [doc = "0x113c - UART LIN Mode Capture 1 Register"]
pub linc1 : LINC1 , # [doc = "0x1140 - eUSCI_Ax IrDA Control Word Register"]
pub irctl : IRCTL , _reserved41 : [u8 ; 0x04]
, # [doc = "0x1148 - Self Address Mask Register"]
pub amask : AMASK , # [doc = "0x114c - Self Address Register"]
pub addr : ADDR , _reserved43 : [u8 ; 0x10]
, # [doc = "0x1160 - Clock Divider"]
pub clkdiv2 : CLKDIV2 , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKCFG (rw) register accessor: Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkcfg`]
module"]
pub type CLKCFG = crate :: Reg < clkcfg :: CLKCFG_SPEC > ; # [doc = "Peripheral Clock Configuration Register"]
pub mod clkcfg { # [doc = "Register `CLKCFG` reader"]
pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"]
pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"]
CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"]
CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"]
pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"]
# [inline (always)]
pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
# [must_use]
pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"]
# [inline (always)]
# [must_use]
pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"]
impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"]
impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"]
impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GPRCM_STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gprcm_stat`]
module"]
pub type GPRCM_STAT = crate :: Reg < gprcm_stat :: GPRCM_STAT_SPEC > ; # [doc = "Status Register"]
pub mod gprcm_stat { # [doc = "Register `GPRCM_STAT` reader"]
pub type R = crate :: R < GPRCM_STAT_SPEC > ; # [doc = "Field `GPRCM_STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type GPRCM_STAT_RESETSTKY_R = crate :: BitReader < GPRCM_STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GPRCM_STAT_RESETSTKY_A { # [doc = "0: NORES"]
GPRCM_STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
GPRCM_STAT_RESETSTKY_RESET = 1 , } impl From < GPRCM_STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : GPRCM_STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl GPRCM_STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GPRCM_STAT_RESETSTKY_A { match self . bits { false => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES , true => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_nores (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_reset (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn gprcm_stat_resetstky (& self) -> GPRCM_STAT_RESETSTKY_R { GPRCM_STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GPRCM_STAT_SPEC ; impl crate :: RegisterSpec for GPRCM_STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gprcm_stat::R`](R) reader structure"]
impl crate :: Readable for GPRCM_STAT_SPEC { } # [doc = "`reset()` method sets GPRCM_STAT to value 0"]
impl crate :: Resettable for GPRCM_STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iidx`]
module"]
pub type INT_EVENT0_IIDX = crate :: Reg < int_event0_iidx :: INT_EVENT0_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event0_iidx { # [doc = "Register `INT_EVENT0_IIDX` reader"]
pub type R = crate :: R < INT_EVENT0_IIDX_SPEC > ; # [doc = "Field `INT_EVENT0_IIDX_STAT` reader - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
pub type INT_EVENT0_IIDX_STAT_R = crate :: FieldReader < INT_EVENT0_IIDX_STAT_A > ; # [doc = "UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: RTFG"]
INT_EVENT0_IIDX_STAT_RTFG = 1 , # [doc = "2: FEFG"]
INT_EVENT0_IIDX_STAT_FEFG = 2 , # [doc = "3: PEFG"]
INT_EVENT0_IIDX_STAT_PEFG = 3 , # [doc = "4: BEFG"]
INT_EVENT0_IIDX_STAT_BEFG = 4 , # [doc = "5: OEFG"]
INT_EVENT0_IIDX_STAT_OEFG = 5 , # [doc = "6: RXNE"]
INT_EVENT0_IIDX_STAT_RXNE = 6 , # [doc = "7: RXPE"]
INT_EVENT0_IIDX_STAT_RXPE = 7 , # [doc = "8: LINC0"]
INT_EVENT0_IIDX_STAT_LINC0 = 8 , # [doc = "9: LINC1"]
INT_EVENT0_IIDX_STAT_LINC1 = 9 , # [doc = "10: LINOVF"]
INT_EVENT0_IIDX_STAT_LINOVF = 10 , # [doc = "11: RXIFG"]
INT_EVENT0_IIDX_STAT_RXIFG = 11 , # [doc = "12: TXIFG"]
INT_EVENT0_IIDX_STAT_TXIFG = 12 , # [doc = "13: EOT"]
INT_EVENT0_IIDX_STAT_EOT = 13 , # [doc = "14: MODE_9B"]
INT_EVENT0_IIDX_STAT_MODE_9B = 14 , # [doc = "15: CTS"]
INT_EVENT0_IIDX_STAT_CTS = 15 , # [doc = "16: DMA_DONE_RX"]
INT_EVENT0_IIDX_STAT_DMA_DONE_RX = 16 , # [doc = "17: DMA_DONE_TX"]
INT_EVENT0_IIDX_STAT_DMA_DONE_TX = 17 , # [doc = "18: NERR_EVT"]
INT_EVENT0_IIDX_STAT_NERR_EVT = 18 , } impl From < INT_EVENT0_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT0_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RTFG) , 2 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_FEFG) , 3 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_PEFG) , 4 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_BEFG) , 5 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_OEFG) , 6 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXNE) , 7 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXPE) , 8 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC0) , 9 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC1) , 10 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINOVF) , 11 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXIFG) , 12 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TXIFG) , 13 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_EOT) , 14 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MODE_9B) , 15 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_CTS) , 16 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_RX) , 17 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_TX) , 18 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NERR_EVT) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR } # [doc = "RTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rtfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RTFG } # [doc = "FEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_fefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_FEFG } # [doc = "PEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_pefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_PEFG } # [doc = "BEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_befg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_BEFG } # [doc = "OEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_oefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_OEFG } # [doc = "RXNE"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxne (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXNE } # [doc = "RXPE"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxpe (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXPE } # [doc = "LINC0"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_linc0 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC0 } # [doc = "LINC1"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_linc1 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC1 } # [doc = "LINOVF"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_linovf (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINOVF } # [doc = "RXIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXIFG } # [doc = "TXIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_txifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TXIFG } # [doc = "EOT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_eot (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_EOT } # [doc = "MODE_9B"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mode_9b (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MODE_9B } # [doc = "CTS"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_cts (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_CTS } # [doc = "DMA_DONE_RX"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dma_done_rx (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_RX } # [doc = "DMA_DONE_TX"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dma_done_tx (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_TX } # [doc = "NERR_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_nerr_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NERR_EVT } } impl R { # [doc = "Bits 0:7 - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event0_iidx_stat (& self) -> INT_EVENT0_IIDX_STAT_R { INT_EVENT0_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_imask`]
module"]
pub type INT_EVENT0_IMASK = crate :: Reg < int_event0_imask :: INT_EVENT0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event0_imask { # [doc = "Register `INT_EVENT0_IMASK` reader"]
pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"]
pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."]
pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."]
pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."]
pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."]
pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."]
pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."]
pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` reader - Enable LIN Capture 0 / Match Interrupt ."]
pub type INT_EVENT0_IMASK_LINC0_R = crate :: BitReader < INT_EVENT0_IMASK_LINC0_A > ; # [doc = "Enable LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_LINC0_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_LINC0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_LINC0_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC0_A { match self . bits { false => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR , true => INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_linc0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_linc0_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC0` writer - Enable LIN Capture 0 / Match Interrupt ."]
pub type INT_EVENT0_IMASK_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC0_A :: INT_EVENT0_IMASK_LINC0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` reader - Enable LIN Capture 1 Interrupt."]
pub type INT_EVENT0_IMASK_LINC1_R = crate :: BitReader < INT_EVENT0_IMASK_LINC1_A > ; # [doc = "Enable LIN Capture 1 Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_LINC1_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_LINC1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_LINC1_SET = 1 , } impl From < INT_EVENT0_IMASK_LINC1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINC1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_LINC1_A { match self . bits { false => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR , true => INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_linc1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_linc1_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINC1` writer - Enable LIN Capture 1 Interrupt."]
pub type INT_EVENT0_IMASK_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINC1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINC1_A :: INT_EVENT0_IMASK_LINC1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` reader - Enable LIN Hardware Counter Overflow Interrupt."]
pub type INT_EVENT0_IMASK_LINOVF_R = crate :: BitReader < INT_EVENT0_IMASK_LINOVF_A > ; # [doc = "Enable LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_LINOVF_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_LINOVF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_LINOVF_SET = 1 , } impl From < INT_EVENT0_IMASK_LINOVF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LINOVF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_LINOVF_A { match self . bits { false => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR , true => INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_linovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_linovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_LINOVF` writer - Enable LIN Hardware Counter Overflow Interrupt."]
pub type INT_EVENT0_IMASK_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LINOVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LINOVF_A :: INT_EVENT0_IMASK_LINOVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."]
pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."]
pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."]
pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."]
pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."]
pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."]
pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."]
# [inline (always)]
pub fn int_event0_imask_linc0 (& self) -> INT_EVENT0_IMASK_LINC0_R { INT_EVENT0_IMASK_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."]
# [inline (always)]
pub fn int_event0_imask_linc1 (& self) -> INT_EVENT0_IMASK_LINC1_R { INT_EVENT0_IMASK_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."]
# [inline (always)]
pub fn int_event0_imask_linovf (& self) -> INT_EVENT0_IMASK_LINOVF_R { INT_EVENT0_IMASK_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."]
# [inline (always)]
pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 7 - Enable LIN Capture 0 / Match Interrupt ."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_linc0 (& mut self) -> INT_EVENT0_IMASK_LINC0_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_LINC0_W :: new (self) } # [doc = "Bit 8 - Enable LIN Capture 1 Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_linc1 (& mut self) -> INT_EVENT0_IMASK_LINC1_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_LINC1_W :: new (self) } # [doc = "Bit 9 - Enable LIN Hardware Counter Overflow Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_linovf (& mut self) -> INT_EVENT0_IMASK_LINOVF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_LINOVF_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_ris`]
module"]
pub type INT_EVENT0_RIS = crate :: Reg < int_event0_ris :: INT_EVENT0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event0_ris { # [doc = "Register `INT_EVENT0_RIS` reader"]
pub type R = crate :: R < INT_EVENT0_RIS_SPEC > ; # [doc = "Field `INT_EVENT0_RIS_RTOUT` reader - UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_RIS_RTOUT_R = crate :: BitReader < INT_EVENT0_RIS_RTOUT_A > ; # [doc = "UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RTOUT_SET = 1 , } impl From < INT_EVENT0_RIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RTOUT_A { match self . bits { false => INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_CLR , true => INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rtout_clr (& self) -> bool { * self == INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rtout_set (& self) -> bool { * self == INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_SET } } # [doc = "Field `INT_EVENT0_RIS_FRMERR` reader - UART Framing Error Interrupt."]
pub type INT_EVENT0_RIS_FRMERR_R = crate :: BitReader < INT_EVENT0_RIS_FRMERR_A > ; # [doc = "UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_FRMERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_FRMERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_FRMERR_SET = 1 , } impl From < INT_EVENT0_RIS_FRMERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_FRMERR_A { match self . bits { false => INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_CLR , true => INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_frmerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_frmerr_set (& self) -> bool { * self == INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_SET } } # [doc = "Field `INT_EVENT0_RIS_PARERR` reader - UART Parity Error Interrupt."]
pub type INT_EVENT0_RIS_PARERR_R = crate :: BitReader < INT_EVENT0_RIS_PARERR_A > ; # [doc = "UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_PARERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_PARERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_PARERR_SET = 1 , } impl From < INT_EVENT0_RIS_PARERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_PARERR_A { match self . bits { false => INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_CLR , true => INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_parerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_parerr_set (& self) -> bool { * self == INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_SET } } # [doc = "Field `INT_EVENT0_RIS_BRKERR` reader - UART Break Error Interrupt."]
pub type INT_EVENT0_RIS_BRKERR_R = crate :: BitReader < INT_EVENT0_RIS_BRKERR_A > ; # [doc = "UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_BRKERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_BRKERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_BRKERR_SET = 1 , } impl From < INT_EVENT0_RIS_BRKERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_BRKERR_A { match self . bits { false => INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_CLR , true => INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_brkerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_brkerr_set (& self) -> bool { * self == INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_SET } } # [doc = "Field `INT_EVENT0_RIS_OVRERR` reader - UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_RIS_OVRERR_R = crate :: BitReader < INT_EVENT0_RIS_OVRERR_A > ; # [doc = "UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_OVRERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_OVRERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_OVRERR_SET = 1 , } impl From < INT_EVENT0_RIS_OVRERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_OVRERR_A { match self . bits { false => INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_CLR , true => INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_ovrerr_set (& self) -> bool { * self == INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_SET } } # [doc = "Field `INT_EVENT0_RIS_RXNE` reader - Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_RIS_RXNE_R = crate :: BitReader < INT_EVENT0_RIS_RXNE_A > ; # [doc = "Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXNE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXNE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXNE_SET = 1 , } impl From < INT_EVENT0_RIS_RXNE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXNE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXNE_A { match self . bits { false => INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_CLR , true => INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxne_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxne_set (& self) -> bool { * self == INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_SET } } # [doc = "Field `INT_EVENT0_RIS_RXPE` reader - Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_RIS_RXPE_R = crate :: BitReader < INT_EVENT0_RIS_RXPE_A > ; # [doc = "Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXPE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXPE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXPE_SET = 1 , } impl From < INT_EVENT0_RIS_RXPE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXPE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXPE_A { match self . bits { false => INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_CLR , true => INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxpe_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxpe_set (& self) -> bool { * self == INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_SET } } # [doc = "Field `INT_EVENT0_RIS_LINC0` reader - LIN Capture 0 / Match Interrupt ."]
pub type INT_EVENT0_RIS_LINC0_R = crate :: BitReader < INT_EVENT0_RIS_LINC0_A > ; # [doc = "LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_LINC0_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_LINC0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_LINC0_SET = 1 , } impl From < INT_EVENT0_RIS_LINC0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_LINC0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_LINC0_A { match self . bits { false => INT_EVENT0_RIS_LINC0_A :: INT_EVENT0_RIS_LINC0_CLR , true => INT_EVENT0_RIS_LINC0_A :: INT_EVENT0_RIS_LINC0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_linc0_clr (& self) -> bool { * self == INT_EVENT0_RIS_LINC0_A :: INT_EVENT0_RIS_LINC0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_linc0_set (& self) -> bool { * self == INT_EVENT0_RIS_LINC0_A :: INT_EVENT0_RIS_LINC0_SET } } # [doc = "Field `INT_EVENT0_RIS_LINC1` reader - LIN Capture 1 Interrupt."]
pub type INT_EVENT0_RIS_LINC1_R = crate :: BitReader < INT_EVENT0_RIS_LINC1_A > ; # [doc = "LIN Capture 1 Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_LINC1_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_LINC1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_LINC1_SET = 1 , } impl From < INT_EVENT0_RIS_LINC1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_LINC1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_LINC1_A { match self . bits { false => INT_EVENT0_RIS_LINC1_A :: INT_EVENT0_RIS_LINC1_CLR , true => INT_EVENT0_RIS_LINC1_A :: INT_EVENT0_RIS_LINC1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_linc1_clr (& self) -> bool { * self == INT_EVENT0_RIS_LINC1_A :: INT_EVENT0_RIS_LINC1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_linc1_set (& self) -> bool { * self == INT_EVENT0_RIS_LINC1_A :: INT_EVENT0_RIS_LINC1_SET } } # [doc = "Field `INT_EVENT0_RIS_LINOVF` reader - LIN Hardware Counter Overflow Interrupt."]
pub type INT_EVENT0_RIS_LINOVF_R = crate :: BitReader < INT_EVENT0_RIS_LINOVF_A > ; # [doc = "LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_LINOVF_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_LINOVF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_LINOVF_SET = 1 , } impl From < INT_EVENT0_RIS_LINOVF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_LINOVF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_LINOVF_A { match self . bits { false => INT_EVENT0_RIS_LINOVF_A :: INT_EVENT0_RIS_LINOVF_CLR , true => INT_EVENT0_RIS_LINOVF_A :: INT_EVENT0_RIS_LINOVF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_linovf_clr (& self) -> bool { * self == INT_EVENT0_RIS_LINOVF_A :: INT_EVENT0_RIS_LINOVF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_linovf_set (& self) -> bool { * self == INT_EVENT0_RIS_LINOVF_A :: INT_EVENT0_RIS_LINOVF_SET } } # [doc = "Field `INT_EVENT0_RIS_RXINT` reader - UART Receive Interrupt."]
pub type INT_EVENT0_RIS_RXINT_R = crate :: BitReader < INT_EVENT0_RIS_RXINT_A > ; # [doc = "UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXINT_SET = 1 , } impl From < INT_EVENT0_RIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXINT_A { match self . bits { false => INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_CLR , true => INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxint_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxint_set (& self) -> bool { * self == INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_SET } } # [doc = "Field `INT_EVENT0_RIS_TXINT` reader - UART Transmit Interrupt."]
pub type INT_EVENT0_RIS_TXINT_R = crate :: BitReader < INT_EVENT0_RIS_TXINT_A > ; # [doc = "UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TXINT_SET = 1 , } impl From < INT_EVENT0_RIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TXINT_A { match self . bits { false => INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_CLR , true => INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_txint_clr (& self) -> bool { * self == INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_txint_set (& self) -> bool { * self == INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_SET } } # [doc = "Field `INT_EVENT0_RIS_EOT` reader - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_RIS_EOT_R = crate :: BitReader < INT_EVENT0_RIS_EOT_A > ; # [doc = "UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_EOT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_EOT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_EOT_SET = 1 , } impl From < INT_EVENT0_RIS_EOT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_EOT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_EOT_A { match self . bits { false => INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_CLR , true => INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_eot_clr (& self) -> bool { * self == INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_eot_set (& self) -> bool { * self == INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_SET } } # [doc = "Field `INT_EVENT0_RIS_ADDR_MATCH` reader - Address Match Interrupt."]
pub type INT_EVENT0_RIS_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_RIS_ADDR_MATCH_A > ; # [doc = "Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_ADDR_MATCH_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_RIS_ADDR_MATCH_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_ADDR_MATCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_CLR , true => INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_addr_match_clr (& self) -> bool { * self == INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_addr_match_set (& self) -> bool { * self == INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_RIS_CTS` reader - UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_RIS_CTS_R = crate :: BitReader < INT_EVENT0_RIS_CTS_A > ; # [doc = "UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_CTS_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_CTS_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_CTS_SET = 1 , } impl From < INT_EVENT0_RIS_CTS_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_CTS_A { match self . bits { false => INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_CLR , true => INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_cts_clr (& self) -> bool { * self == INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_cts_set (& self) -> bool { * self == INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_SET } } # [doc = "Field `INT_EVENT0_RIS_DMA_DONE_RX` reader - DMA Done on RX Event Channel"]
pub type INT_EVENT0_RIS_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_RIS_DMA_DONE_RX_A > ; # [doc = "DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_RIS_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_CLR , true => INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_RIS_DMA_DONE_TX` reader - DMA Done on TX Event Channel"]
pub type INT_EVENT0_RIS_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_RIS_DMA_DONE_TX_A > ; # [doc = "DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_RIS_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_CLR , true => INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_RIS_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_RIS_NERR_R = crate :: BitReader < INT_EVENT0_RIS_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_NERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_NERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_NERR_SET = 1 , } impl From < INT_EVENT0_RIS_NERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_NERR_A { match self . bits { false => INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_CLR , true => INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_nerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_nerr_set (& self) -> bool { * self == INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_SET } } impl R { # [doc = "Bit 0 - UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rtout (& self) -> INT_EVENT0_RIS_RTOUT_R { INT_EVENT0_RIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - UART Framing Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_frmerr (& self) -> INT_EVENT0_RIS_FRMERR_R { INT_EVENT0_RIS_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - UART Parity Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_parerr (& self) -> INT_EVENT0_RIS_PARERR_R { INT_EVENT0_RIS_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Break Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_brkerr (& self) -> INT_EVENT0_RIS_BRKERR_R { INT_EVENT0_RIS_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Receive Overrun Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_ovrerr (& self) -> INT_EVENT0_RIS_OVRERR_R { INT_EVENT0_RIS_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rxne (& self) -> INT_EVENT0_RIS_RXNE_R { INT_EVENT0_RIS_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rxpe (& self) -> INT_EVENT0_RIS_RXPE_R { INT_EVENT0_RIS_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - LIN Capture 0 / Match Interrupt ."]
# [inline (always)]
pub fn int_event0_ris_linc0 (& self) -> INT_EVENT0_RIS_LINC0_R { INT_EVENT0_RIS_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - LIN Capture 1 Interrupt."]
# [inline (always)]
pub fn int_event0_ris_linc1 (& self) -> INT_EVENT0_RIS_LINC1_R { INT_EVENT0_RIS_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - LIN Hardware Counter Overflow Interrupt."]
# [inline (always)]
pub fn int_event0_ris_linovf (& self) -> INT_EVENT0_RIS_LINOVF_R { INT_EVENT0_RIS_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - UART Receive Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rxint (& self) -> INT_EVENT0_RIS_RXINT_R { INT_EVENT0_RIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event0_ris_txint (& self) -> INT_EVENT0_RIS_TXINT_R { INT_EVENT0_RIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
pub fn int_event0_ris_eot (& self) -> INT_EVENT0_RIS_EOT_R { INT_EVENT0_RIS_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Address Match Interrupt."]
# [inline (always)]
pub fn int_event0_ris_addr_match (& self) -> INT_EVENT0_RIS_ADDR_MATCH_R { INT_EVENT0_RIS_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
pub fn int_event0_ris_cts (& self) -> INT_EVENT0_RIS_CTS_R { INT_EVENT0_RIS_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DMA Done on RX Event Channel"]
# [inline (always)]
pub fn int_event0_ris_dma_done_rx (& self) -> INT_EVENT0_RIS_DMA_DONE_RX_R { INT_EVENT0_RIS_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DMA Done on TX Event Channel"]
# [inline (always)]
pub fn int_event0_ris_dma_done_tx (& self) -> INT_EVENT0_RIS_DMA_DONE_TX_R { INT_EVENT0_RIS_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
pub fn int_event0_ris_nerr (& self) -> INT_EVENT0_RIS_NERR_R { INT_EVENT0_RIS_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_RIS to value 0"]
impl crate :: Resettable for INT_EVENT0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_mis`]
module"]
pub type INT_EVENT0_MIS = crate :: Reg < int_event0_mis :: INT_EVENT0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event0_mis { # [doc = "Register `INT_EVENT0_MIS` reader"]
pub type R = crate :: R < INT_EVENT0_MIS_SPEC > ; # [doc = "Field `INT_EVENT0_MIS_RTOUT` reader - Masked UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_MIS_RTOUT_R = crate :: BitReader < INT_EVENT0_MIS_RTOUT_A > ; # [doc = "Masked UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RTOUT_SET = 1 , } impl From < INT_EVENT0_MIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RTOUT_A { match self . bits { false => INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_CLR , true => INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rtout_clr (& self) -> bool { * self == INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rtout_set (& self) -> bool { * self == INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_SET } } # [doc = "Field `INT_EVENT0_MIS_FRMERR` reader - Masked UART Framing Error Interrupt."]
pub type INT_EVENT0_MIS_FRMERR_R = crate :: BitReader < INT_EVENT0_MIS_FRMERR_A > ; # [doc = "Masked UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_FRMERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_FRMERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_FRMERR_SET = 1 , } impl From < INT_EVENT0_MIS_FRMERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_FRMERR_A { match self . bits { false => INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_CLR , true => INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_frmerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_frmerr_set (& self) -> bool { * self == INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_SET } } # [doc = "Field `INT_EVENT0_MIS_PARERR` reader - Masked UART Parity Error Interrupt."]
pub type INT_EVENT0_MIS_PARERR_R = crate :: BitReader < INT_EVENT0_MIS_PARERR_A > ; # [doc = "Masked UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_PARERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_PARERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_PARERR_SET = 1 , } impl From < INT_EVENT0_MIS_PARERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_PARERR_A { match self . bits { false => INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_CLR , true => INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_parerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_parerr_set (& self) -> bool { * self == INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_SET } } # [doc = "Field `INT_EVENT0_MIS_BRKERR` reader - Masked UART Break Error Interrupt."]
pub type INT_EVENT0_MIS_BRKERR_R = crate :: BitReader < INT_EVENT0_MIS_BRKERR_A > ; # [doc = "Masked UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_BRKERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_BRKERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_BRKERR_SET = 1 , } impl From < INT_EVENT0_MIS_BRKERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_BRKERR_A { match self . bits { false => INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_CLR , true => INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_brkerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_brkerr_set (& self) -> bool { * self == INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_SET } } # [doc = "Field `INT_EVENT0_MIS_OVRERR` reader - Masked UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_MIS_OVRERR_R = crate :: BitReader < INT_EVENT0_MIS_OVRERR_A > ; # [doc = "Masked UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_OVRERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_OVRERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_OVRERR_SET = 1 , } impl From < INT_EVENT0_MIS_OVRERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_OVRERR_A { match self . bits { false => INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_CLR , true => INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_ovrerr_set (& self) -> bool { * self == INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_SET } } # [doc = "Field `INT_EVENT0_MIS_RXNE` reader - Masked Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_MIS_RXNE_R = crate :: BitReader < INT_EVENT0_MIS_RXNE_A > ; # [doc = "Masked Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXNE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXNE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXNE_SET = 1 , } impl From < INT_EVENT0_MIS_RXNE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXNE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXNE_A { match self . bits { false => INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_CLR , true => INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxne_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxne_set (& self) -> bool { * self == INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_SET } } # [doc = "Field `INT_EVENT0_MIS_RXPE` reader - Masked Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_MIS_RXPE_R = crate :: BitReader < INT_EVENT0_MIS_RXPE_A > ; # [doc = "Masked Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXPE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXPE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXPE_SET = 1 , } impl From < INT_EVENT0_MIS_RXPE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXPE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXPE_A { match self . bits { false => INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_CLR , true => INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxpe_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxpe_set (& self) -> bool { * self == INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_SET } } # [doc = "Field `INT_EVENT0_MIS_LINC0` reader - Masked LIN Capture 0 / Match Interrupt ."]
pub type INT_EVENT0_MIS_LINC0_R = crate :: BitReader < INT_EVENT0_MIS_LINC0_A > ; # [doc = "Masked LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_LINC0_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_LINC0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_LINC0_SET = 1 , } impl From < INT_EVENT0_MIS_LINC0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_LINC0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_LINC0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_LINC0_A { match self . bits { false => INT_EVENT0_MIS_LINC0_A :: INT_EVENT0_MIS_LINC0_CLR , true => INT_EVENT0_MIS_LINC0_A :: INT_EVENT0_MIS_LINC0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_linc0_clr (& self) -> bool { * self == INT_EVENT0_MIS_LINC0_A :: INT_EVENT0_MIS_LINC0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_linc0_set (& self) -> bool { * self == INT_EVENT0_MIS_LINC0_A :: INT_EVENT0_MIS_LINC0_SET } } # [doc = "Field `INT_EVENT0_MIS_LINC1` reader - Masked LIN Capture 1 Interrupt."]
pub type INT_EVENT0_MIS_LINC1_R = crate :: BitReader < INT_EVENT0_MIS_LINC1_A > ; # [doc = "Masked LIN Capture 1 Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_LINC1_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_LINC1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_LINC1_SET = 1 , } impl From < INT_EVENT0_MIS_LINC1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_LINC1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_LINC1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_LINC1_A { match self . bits { false => INT_EVENT0_MIS_LINC1_A :: INT_EVENT0_MIS_LINC1_CLR , true => INT_EVENT0_MIS_LINC1_A :: INT_EVENT0_MIS_LINC1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_linc1_clr (& self) -> bool { * self == INT_EVENT0_MIS_LINC1_A :: INT_EVENT0_MIS_LINC1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_linc1_set (& self) -> bool { * self == INT_EVENT0_MIS_LINC1_A :: INT_EVENT0_MIS_LINC1_SET } } # [doc = "Field `INT_EVENT0_MIS_LINOVF` reader - Masked LIN Hardware Counter Overflow Interrupt."]
pub type INT_EVENT0_MIS_LINOVF_R = crate :: BitReader < INT_EVENT0_MIS_LINOVF_A > ; # [doc = "Masked LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_LINOVF_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_LINOVF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_LINOVF_SET = 1 , } impl From < INT_EVENT0_MIS_LINOVF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_LINOVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_LINOVF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_LINOVF_A { match self . bits { false => INT_EVENT0_MIS_LINOVF_A :: INT_EVENT0_MIS_LINOVF_CLR , true => INT_EVENT0_MIS_LINOVF_A :: INT_EVENT0_MIS_LINOVF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_linovf_clr (& self) -> bool { * self == INT_EVENT0_MIS_LINOVF_A :: INT_EVENT0_MIS_LINOVF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_linovf_set (& self) -> bool { * self == INT_EVENT0_MIS_LINOVF_A :: INT_EVENT0_MIS_LINOVF_SET } } # [doc = "Field `INT_EVENT0_MIS_RXINT` reader - Masked UART Receive Interrupt."]
pub type INT_EVENT0_MIS_RXINT_R = crate :: BitReader < INT_EVENT0_MIS_RXINT_A > ; # [doc = "Masked UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXINT_SET = 1 , } impl From < INT_EVENT0_MIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXINT_A { match self . bits { false => INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_CLR , true => INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxint_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxint_set (& self) -> bool { * self == INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_SET } } # [doc = "Field `INT_EVENT0_MIS_TXINT` reader - Masked UART Transmit Interrupt."]
pub type INT_EVENT0_MIS_TXINT_R = crate :: BitReader < INT_EVENT0_MIS_TXINT_A > ; # [doc = "Masked UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TXINT_SET = 1 , } impl From < INT_EVENT0_MIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TXINT_A { match self . bits { false => INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_CLR , true => INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_txint_clr (& self) -> bool { * self == INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_txint_set (& self) -> bool { * self == INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_SET } } # [doc = "Field `INT_EVENT0_MIS_EOT` reader - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_MIS_EOT_R = crate :: BitReader < INT_EVENT0_MIS_EOT_A > ; # [doc = "UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_EOT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_EOT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_EOT_SET = 1 , } impl From < INT_EVENT0_MIS_EOT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_EOT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_EOT_A { match self . bits { false => INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_CLR , true => INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_eot_clr (& self) -> bool { * self == INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_eot_set (& self) -> bool { * self == INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_SET } } # [doc = "Field `INT_EVENT0_MIS_ADDR_MATCH` reader - Masked Address Match Interrupt."]
pub type INT_EVENT0_MIS_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_MIS_ADDR_MATCH_A > ; # [doc = "Masked Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_ADDR_MATCH_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_MIS_ADDR_MATCH_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_ADDR_MATCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_CLR , true => INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_addr_match_clr (& self) -> bool { * self == INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_addr_match_set (& self) -> bool { * self == INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_MIS_CTS` reader - Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_MIS_CTS_R = crate :: BitReader < INT_EVENT0_MIS_CTS_A > ; # [doc = "Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_CTS_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_CTS_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_CTS_SET = 1 , } impl From < INT_EVENT0_MIS_CTS_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_CTS_A { match self . bits { false => INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_CLR , true => INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_cts_clr (& self) -> bool { * self == INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_cts_set (& self) -> bool { * self == INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_SET } } # [doc = "Field `INT_EVENT0_MIS_DMA_DONE_RX` reader - Masked DMA Done on RX Event Channel"]
pub type INT_EVENT0_MIS_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_MIS_DMA_DONE_RX_A > ; # [doc = "Masked DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_MIS_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_CLR , true => INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_MIS_DMA_DONE_TX` reader - Masked DMA Done on TX Event Channel"]
pub type INT_EVENT0_MIS_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_MIS_DMA_DONE_TX_A > ; # [doc = "Masked DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_MIS_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_CLR , true => INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_MIS_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_MIS_NERR_R = crate :: BitReader < INT_EVENT0_MIS_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_NERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_NERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_NERR_SET = 1 , } impl From < INT_EVENT0_MIS_NERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_NERR_A { match self . bits { false => INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_CLR , true => INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_nerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_nerr_set (& self) -> bool { * self == INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_SET } } impl R { # [doc = "Bit 0 - Masked UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rtout (& self) -> INT_EVENT0_MIS_RTOUT_R { INT_EVENT0_MIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masked UART Framing Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_frmerr (& self) -> INT_EVENT0_MIS_FRMERR_R { INT_EVENT0_MIS_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masked UART Parity Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_parerr (& self) -> INT_EVENT0_MIS_PARERR_R { INT_EVENT0_MIS_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masked UART Break Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_brkerr (& self) -> INT_EVENT0_MIS_BRKERR_R { INT_EVENT0_MIS_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Masked UART Receive Overrun Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_ovrerr (& self) -> INT_EVENT0_MIS_OVRERR_R { INT_EVENT0_MIS_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Masked Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rxne (& self) -> INT_EVENT0_MIS_RXNE_R { INT_EVENT0_MIS_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Masked Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rxpe (& self) -> INT_EVENT0_MIS_RXPE_R { INT_EVENT0_MIS_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Masked LIN Capture 0 / Match Interrupt ."]
# [inline (always)]
pub fn int_event0_mis_linc0 (& self) -> INT_EVENT0_MIS_LINC0_R { INT_EVENT0_MIS_LINC0_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Masked LIN Capture 1 Interrupt."]
# [inline (always)]
pub fn int_event0_mis_linc1 (& self) -> INT_EVENT0_MIS_LINC1_R { INT_EVENT0_MIS_LINC1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Masked LIN Hardware Counter Overflow Interrupt."]
# [inline (always)]
pub fn int_event0_mis_linovf (& self) -> INT_EVENT0_MIS_LINOVF_R { INT_EVENT0_MIS_LINOVF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Masked UART Receive Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rxint (& self) -> INT_EVENT0_MIS_RXINT_R { INT_EVENT0_MIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Masked UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event0_mis_txint (& self) -> INT_EVENT0_MIS_TXINT_R { INT_EVENT0_MIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
pub fn int_event0_mis_eot (& self) -> INT_EVENT0_MIS_EOT_R { INT_EVENT0_MIS_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Masked Address Match Interrupt."]
# [inline (always)]
pub fn int_event0_mis_addr_match (& self) -> INT_EVENT0_MIS_ADDR_MATCH_R { INT_EVENT0_MIS_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
pub fn int_event0_mis_cts (& self) -> INT_EVENT0_MIS_CTS_R { INT_EVENT0_MIS_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Masked DMA Done on RX Event Channel"]
# [inline (always)]
pub fn int_event0_mis_dma_done_rx (& self) -> INT_EVENT0_MIS_DMA_DONE_RX_R { INT_EVENT0_MIS_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Masked DMA Done on TX Event Channel"]
# [inline (always)]
pub fn int_event0_mis_dma_done_tx (& self) -> INT_EVENT0_MIS_DMA_DONE_TX_R { INT_EVENT0_MIS_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
pub fn int_event0_mis_nerr (& self) -> INT_EVENT0_MIS_NERR_R { INT_EVENT0_MIS_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_MIS to value 0"]
impl crate :: Resettable for INT_EVENT0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iset`]
module"]
pub type INT_EVENT0_ISET = crate :: Reg < int_event0_iset :: INT_EVENT0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event0_iset { # [doc = "Register `INT_EVENT0_ISET` writer"]
pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."]
pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."]
pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."]
pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_LINC0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_LINC0_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_LINC0_SET = 1 , } impl From < INT_EVENT0_ISET_LINC0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC0` writer - Set LIN Capture 0 / Match Interrupt ."]
pub type INT_EVENT0_ISET_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_linc0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC0_AW :: INT_EVENT0_ISET_LINC0_SET) } } # [doc = "Set LIN Capture 1 Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_LINC1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_LINC1_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_LINC1_SET = 1 , } impl From < INT_EVENT0_ISET_LINC1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINC1` writer - Set LIN Capture 1 Interrupt."]
pub type INT_EVENT0_ISET_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_linc1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINC1_AW :: INT_EVENT0_ISET_LINC1_SET) } } # [doc = "Set LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_LINOVF_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_LINOVF_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_LINOVF_SET = 1 , } impl From < INT_EVENT0_ISET_LINOVF_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LINOVF` writer - Set LIN Hardware Counter Overflow Interrupt."]
pub type INT_EVENT0_ISET_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_linovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LINOVF_AW :: INT_EVENT0_ISET_LINOVF_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."]
pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."]
pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."]
pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"]
pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"]
pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 7 - Set LIN Capture 0 / Match Interrupt ."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_linc0 (& mut self) -> INT_EVENT0_ISET_LINC0_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_LINC0_W :: new (self) } # [doc = "Bit 8 - Set LIN Capture 1 Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_linc1 (& mut self) -> INT_EVENT0_ISET_LINC1_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_LINC1_W :: new (self) } # [doc = "Bit 9 - Set LIN Hardware Counter Overflow Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_linovf (& mut self) -> INT_EVENT0_ISET_LINOVF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_LINOVF_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"]
impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iclr`]
module"]
pub type INT_EVENT0_ICLR = crate :: Reg < int_event0_iclr :: INT_EVENT0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event0_iclr { # [doc = "Register `INT_EVENT0_ICLR` writer"]
pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."]
pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."]
pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."]
pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear LIN Capture 0 / Match Interrupt .\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_LINC0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_LINC0_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_LINC0_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_LINC0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC0` writer - Clear LIN Capture 0 / Match Interrupt ."]
pub type INT_EVENT0_ICLR_LINC0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_linc0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_linc0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC0_AW :: INT_EVENT0_ICLR_LINC0_CLR) } } # [doc = "Clear LIN Capture 1 Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_LINC1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_LINC1_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_LINC1_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINC1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_LINC1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINC1` writer - Clear LIN Capture 1 Interrupt."]
pub type INT_EVENT0_ICLR_LINC1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINC1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINC1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_linc1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_linc1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINC1_AW :: INT_EVENT0_ICLR_LINC1_CLR) } } # [doc = "Clear LIN Hardware Counter Overflow Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_LINOVF_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_LINOVF_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_LINOVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_LINOVF_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_LINOVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LINOVF` writer - Clear LIN Hardware Counter Overflow Interrupt."]
pub type INT_EVENT0_ICLR_LINOVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LINOVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LINOVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_linovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_linovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LINOVF_AW :: INT_EVENT0_ICLR_LINOVF_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."]
pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."]
pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."]
pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"]
pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"]
pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 7 - Clear LIN Capture 0 / Match Interrupt ."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_linc0 (& mut self) -> INT_EVENT0_ICLR_LINC0_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_LINC0_W :: new (self) } # [doc = "Bit 8 - Clear LIN Capture 1 Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_linc1 (& mut self) -> INT_EVENT0_ICLR_LINC1_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_LINC1_W :: new (self) } # [doc = "Bit 9 - Clear LIN Hardware Counter Overflow Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_linovf (& mut self) -> INT_EVENT0_ICLR_LINOVF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_LINOVF_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iidx`]
module"]
pub type INT_EVENT1_IIDX = crate :: Reg < int_event1_iidx :: INT_EVENT1_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event1_iidx { # [doc = "Register `INT_EVENT1_IIDX` reader"]
pub type R = crate :: R < INT_EVENT1_IIDX_SPEC > ; # [doc = "Field `INT_EVENT1_IIDX_STAT` reader - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
pub type INT_EVENT1_IIDX_STAT_R = crate :: FieldReader < INT_EVENT1_IIDX_STAT_A > ; # [doc = "UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT1_IIDX_STAT_NO_INTR = 0 , # [doc = "1: RTFG"]
INT_EVENT1_IIDX_STAT_RTFG = 1 , # [doc = "11: RXIFG"]
INT_EVENT1_IIDX_STAT_RXIFG = 11 , } impl From < INT_EVENT1_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT1_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RTFG) , 11 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RXIFG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR } # [doc = "RTFG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_rtfg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RTFG } # [doc = "RXIFG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_rxifg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RXIFG } } impl R { # [doc = "Bits 0:7 - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event1_iidx_stat (& self) -> INT_EVENT1_IIDX_STAT_R { INT_EVENT1_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_imask`]
module"]
pub type INT_EVENT1_IMASK = crate :: Reg < int_event1_imask :: INT_EVENT1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event1_imask { # [doc = "Register `INT_EVENT1_IMASK` reader"]
pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"]
pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT1_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT1_IMASK_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_RTOUT_A { match self . bits { false => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR , true => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_rtout_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_rtout_set (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` reader - Enable UART Receive Interrupt."]
pub type INT_EVENT1_IMASK_RXINT_R = crate :: BitReader < INT_EVENT1_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_RXINT_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT1_IMASK_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_RXINT_A { match self . bits { false => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR , true => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_rxint_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_rxint_set (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` writer - Enable UART Receive Interrupt."]
pub type INT_EVENT1_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event1_imask_rtout (& self) -> INT_EVENT1_IMASK_RTOUT_R { INT_EVENT1_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
pub fn int_event1_imask_rxint (& self) -> INT_EVENT1_IMASK_RXINT_R { INT_EVENT1_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_rtout (& mut self) -> INT_EVENT1_IMASK_RTOUT_W < INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_rxint (& mut self) -> INT_EVENT1_IMASK_RXINT_W < INT_EVENT1_IMASK_SPEC , 10 > { INT_EVENT1_IMASK_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_ris`]
module"]
pub type INT_EVENT1_RIS = crate :: Reg < int_event1_ris :: INT_EVENT1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event1_ris { # [doc = "Register `INT_EVENT1_RIS` reader"]
pub type R = crate :: R < INT_EVENT1_RIS_SPEC > ; # [doc = "Field `INT_EVENT1_RIS_RTOUT` reader - UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_RIS_RTOUT_R = crate :: BitReader < INT_EVENT1_RIS_RTOUT_A > ; # [doc = "UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_RTOUT_SET = 1 , } impl From < INT_EVENT1_RIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_RTOUT_A { match self . bits { false => INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_CLR , true => INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_rtout_clr (& self) -> bool { * self == INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_rtout_set (& self) -> bool { * self == INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_SET } } # [doc = "Field `INT_EVENT1_RIS_RXINT` reader - UART Receive Interrupt."]
pub type INT_EVENT1_RIS_RXINT_R = crate :: BitReader < INT_EVENT1_RIS_RXINT_A > ; # [doc = "UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_RXINT_SET = 1 , } impl From < INT_EVENT1_RIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_RXINT_A { match self . bits { false => INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_CLR , true => INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_rxint_clr (& self) -> bool { * self == INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_rxint_set (& self) -> bool { * self == INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_SET } } impl R { # [doc = "Bit 0 - UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event1_ris_rtout (& self) -> INT_EVENT1_RIS_RTOUT_R { INT_EVENT1_RIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - UART Receive Interrupt."]
# [inline (always)]
pub fn int_event1_ris_rxint (& self) -> INT_EVENT1_RIS_RXINT_R { INT_EVENT1_RIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_RIS to value 0"]
impl crate :: Resettable for INT_EVENT1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_mis`]
module"]
pub type INT_EVENT1_MIS = crate :: Reg < int_event1_mis :: INT_EVENT1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event1_mis { # [doc = "Register `INT_EVENT1_MIS` reader"]
pub type R = crate :: R < INT_EVENT1_MIS_SPEC > ; # [doc = "Field `INT_EVENT1_MIS_RTOUT` reader - Masked UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_MIS_RTOUT_R = crate :: BitReader < INT_EVENT1_MIS_RTOUT_A > ; # [doc = "Masked UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_RTOUT_SET = 1 , } impl From < INT_EVENT1_MIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_RTOUT_A { match self . bits { false => INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_CLR , true => INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_rtout_clr (& self) -> bool { * self == INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_rtout_set (& self) -> bool { * self == INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_SET } } # [doc = "Field `INT_EVENT1_MIS_RXINT` reader - Masked UART Receive Interrupt."]
pub type INT_EVENT1_MIS_RXINT_R = crate :: BitReader < INT_EVENT1_MIS_RXINT_A > ; # [doc = "Masked UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_RXINT_SET = 1 , } impl From < INT_EVENT1_MIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_RXINT_A { match self . bits { false => INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_CLR , true => INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_rxint_clr (& self) -> bool { * self == INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_rxint_set (& self) -> bool { * self == INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_SET } } impl R { # [doc = "Bit 0 - Masked UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event1_mis_rtout (& self) -> INT_EVENT1_MIS_RTOUT_R { INT_EVENT1_MIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - Masked UART Receive Interrupt."]
# [inline (always)]
pub fn int_event1_mis_rxint (& self) -> INT_EVENT1_MIS_RXINT_R { INT_EVENT1_MIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_MIS to value 0"]
impl crate :: Resettable for INT_EVENT1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iset`]
module"]
pub type INT_EVENT1_ISET = crate :: Reg < int_event1_iset :: INT_EVENT1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event1_iset { # [doc = "Register `INT_EVENT1_ISET` writer"]
pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT1_ISET_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_RXINT_SET = 1 , } impl From < INT_EVENT1_ISET_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RXINT` writer - Set UART Receive Interrupt."]
pub type INT_EVENT1_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_rtout (& mut self) -> INT_EVENT1_ISET_RTOUT_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_RTOUT_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_rxint (& mut self) -> INT_EVENT1_ISET_RXINT_W < INT_EVENT1_ISET_SPEC , 10 > { INT_EVENT1_ISET_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"]
impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iclr`]
module"]
pub type INT_EVENT1_ICLR = crate :: Reg < int_event1_iclr :: INT_EVENT1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event1_iclr { # [doc = "Register `INT_EVENT1_ICLR` writer"]
pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RXINT` writer - Clear UART Receive Interrupt."]
pub type INT_EVENT1_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_rtout (& mut self) -> INT_EVENT1_ICLR_RTOUT_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_rxint (& mut self) -> INT_EVENT1_ICLR_RXINT_W < INT_EVENT1_ICLR_SPEC , 10 > { INT_EVENT1_ICLR_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iidx`]
module"]
pub type INT_EVENT2_IIDX = crate :: Reg < int_event2_iidx :: INT_EVENT2_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event2_iidx { # [doc = "Register `INT_EVENT2_IIDX` reader"]
pub type R = crate :: R < INT_EVENT2_IIDX_SPEC > ; # [doc = "Field `INT_EVENT2_IIDX_STAT` reader - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
pub type INT_EVENT2_IIDX_STAT_R = crate :: FieldReader < INT_EVENT2_IIDX_STAT_A > ; # [doc = "UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT2_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT2_IIDX_STAT_NO_INTR = 0 , # [doc = "12: TXIFG"]
INT_EVENT2_IIDX_STAT_TXIFG = 12 , } impl From < INT_EVENT2_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT2_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT2_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT2_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT2_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR) , 12 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_TXIFG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR } # [doc = "TXIFG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_txifg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_TXIFG } } impl R { # [doc = "Bits 0:7 - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event2_iidx_stat (& self) -> INT_EVENT2_IIDX_STAT_R { INT_EVENT2_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT2_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_imask`]
module"]
pub type INT_EVENT2_IMASK = crate :: Reg < int_event2_imask :: INT_EVENT2_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event2_imask { # [doc = "Register `INT_EVENT2_IMASK` reader"]
pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"]
pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_TXINT` reader - Enable UART Transmit Interrupt."]
pub type INT_EVENT2_IMASK_TXINT_R = crate :: BitReader < INT_EVENT2_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_TXINT_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT2_IMASK_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_TXINT_A { match self . bits { false => INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR , true => INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_txint_clr (& self) -> bool { * self == INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_txint_set (& self) -> bool { * self == INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT2_IMASK_TXINT` writer - Enable UART Transmit Interrupt."]
pub type INT_EVENT2_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET) } } impl R { # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event2_imask_txint (& self) -> INT_EVENT2_IMASK_TXINT_R { INT_EVENT2_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_txint (& mut self) -> INT_EVENT2_IMASK_TXINT_W < INT_EVENT2_IMASK_SPEC , 11 > { INT_EVENT2_IMASK_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_ris`]
module"]
pub type INT_EVENT2_RIS = crate :: Reg < int_event2_ris :: INT_EVENT2_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event2_ris { # [doc = "Register `INT_EVENT2_RIS` reader"]
pub type R = crate :: R < INT_EVENT2_RIS_SPEC > ; # [doc = "Field `INT_EVENT2_RIS_TXINT` reader - UART Transmit Interrupt."]
pub type INT_EVENT2_RIS_TXINT_R = crate :: BitReader < INT_EVENT2_RIS_TXINT_A > ; # [doc = "UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_TXINT_SET = 1 , } impl From < INT_EVENT2_RIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_TXINT_A { match self . bits { false => INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_CLR , true => INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_txint_clr (& self) -> bool { * self == INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_txint_set (& self) -> bool { * self == INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_SET } } impl R { # [doc = "Bit 11 - UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event2_ris_txint (& self) -> INT_EVENT2_RIS_TXINT_R { INT_EVENT2_RIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_RIS to value 0"]
impl crate :: Resettable for INT_EVENT2_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_mis`]
module"]
pub type INT_EVENT2_MIS = crate :: Reg < int_event2_mis :: INT_EVENT2_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event2_mis { # [doc = "Register `INT_EVENT2_MIS` reader"]
pub type R = crate :: R < INT_EVENT2_MIS_SPEC > ; # [doc = "Field `INT_EVENT2_MIS_TXINT` reader - Masked UART Transmit Interrupt."]
pub type INT_EVENT2_MIS_TXINT_R = crate :: BitReader < INT_EVENT2_MIS_TXINT_A > ; # [doc = "Masked UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_TXINT_SET = 1 , } impl From < INT_EVENT2_MIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_TXINT_A { match self . bits { false => INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_CLR , true => INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_txint_clr (& self) -> bool { * self == INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_txint_set (& self) -> bool { * self == INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_SET } } impl R { # [doc = "Bit 11 - Masked UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event2_mis_txint (& self) -> INT_EVENT2_MIS_TXINT_R { INT_EVENT2_MIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_MIS to value 0"]
impl crate :: Resettable for INT_EVENT2_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iset`]
module"]
pub type INT_EVENT2_ISET = crate :: Reg < int_event2_iset :: INT_EVENT2_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event2_iset { # [doc = "Register `INT_EVENT2_ISET` writer"]
pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_TXINT_SET = 1 , } impl From < INT_EVENT2_ISET_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_TXINT` writer - Set UART Transmit Interrupt."]
pub type INT_EVENT2_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TXINT_AW :: INT_EVENT2_ISET_TXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TXINT_AW :: INT_EVENT2_ISET_TXINT_SET) } } impl W { # [doc = "Bit 11 - Set UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_txint (& mut self) -> INT_EVENT2_ISET_TXINT_W < INT_EVENT2_ISET_SPEC , 11 > { INT_EVENT2_ISET_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"]
impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iclr`]
module"]
pub type INT_EVENT2_ICLR = crate :: Reg < int_event2_iclr :: INT_EVENT2_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event2_iclr { # [doc = "Register `INT_EVENT2_ICLR` writer"]
pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT2_ICLR_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_TXINT` writer - Clear UART Transmit Interrupt."]
pub type INT_EVENT2_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TXINT_AW :: INT_EVENT2_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TXINT_AW :: INT_EVENT2_ICLR_TXINT_CLR) } } impl W { # [doc = "Bit 11 - Clear UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_txint (& mut self) -> INT_EVENT2_ICLR_TXINT_W < INT_EVENT2_ICLR_SPEC , 11 > { INT_EVENT2_ICLR_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL0 (rw) register accessor: UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl0`]
module"]
pub type CTL0 = crate :: Reg < ctl0 :: CTL0_SPEC > ; # [doc = "UART Control Register 0"]
pub mod ctl0 { # [doc = "Register `CTL0` reader"]
pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"]
pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"]
CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"]
pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_LBE_A { # [doc = "0: DISABLE"]
CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)]
fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"]
pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_RXE_A { # [doc = "0: DISABLE"]
CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)]
fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_TXE_A { # [doc = "0: DISABLE"]
CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)]
fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"]
CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)]
fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"]
CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"]
CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)]
fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"]
# [inline (always)]
pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"]
# [inline (always)]
pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MENC` reader - Manchester Encode enable"]
pub type CTL0_MENC_R = crate :: BitReader < CTL0_MENC_A > ; # [doc = "Manchester Encode enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_MENC_A { # [doc = "0: DISABLE"]
CTL0_MENC_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_MENC_ENABLE = 1 , } impl From < CTL0_MENC_A > for bool { # [inline (always)]
fn from (variant : CTL0_MENC_A) -> Self { variant as u8 != 0 } } impl CTL0_MENC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_MENC_A { match self . bits { false => CTL0_MENC_A :: CTL0_MENC_DISABLE , true => CTL0_MENC_A :: CTL0_MENC_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_menc_disable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_menc_enable (& self) -> bool { * self == CTL0_MENC_A :: CTL0_MENC_ENABLE } } # [doc = "Field `CTL0_MENC` writer - Manchester Encode enable"]
pub type CTL0_MENC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MENC_A > ; impl < 'a , REG , const O : u8 > CTL0_MENC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_menc_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_menc_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MENC_A :: CTL0_MENC_ENABLE) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_MODE_A { # [doc = "0: UART"]
CTL0_MODE_UART = 0 , # [doc = "1: RS485"]
CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"]
CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"]
CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"]
CTL0_MODE_SMART = 4 , # [doc = "5: DALI"]
CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)]
fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"]
# [inline (always)]
pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"]
# [inline (always)]
pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"]
# [inline (always)]
pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"]
# [inline (always)]
pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"]
# [inline (always)]
pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"]
# [inline (always)]
pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"]
# [inline (always)]
pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"]
# [inline (always)]
pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"]
# [inline (always)]
pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"]
# [inline (always)]
pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"]
# [inline (always)]
pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"]
# [inline (always)]
pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_RTS_A { # [doc = "0: CLR"]
CTL0_RTS_CLR = 0 , # [doc = "1: SET"]
CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)]
fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"]
pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"]
CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"]
pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"]
pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"]
CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"]
pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_HSE_A { # [doc = "0: OVS16"]
CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"]
CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"]
CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)]
fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"]
# [inline (always)]
pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"]
# [inline (always)]
pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"]
# [inline (always)]
pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"]
# [inline (always)]
pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"]
# [inline (always)]
pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"]
# [inline (always)]
pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"]
pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_FEN_A { # [doc = "0: DISABLE"]
CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"]
pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"]
CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)]
fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"]
CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)]
fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
# [inline (always)]
pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"]
# [inline (always)]
pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
# [inline (always)]
pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
# [inline (always)]
pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
# [inline (always)]
pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
# [inline (always)]
pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Manchester Encode enable"]
# [inline (always)]
pub fn ctl0_menc (& self) -> CTL0_MENC_R { CTL0_MENC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
# [inline (always)]
pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
# [inline (always)]
pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"]
# [inline (always)]
pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"]
# [inline (always)]
pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
# [inline (always)]
pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"]
# [inline (always)]
pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
# [inline (always)]
pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
# [inline (always)]
pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
# [inline (always)]
# [must_use]
pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"]
# [inline (always)]
# [must_use]
pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
# [inline (always)]
# [must_use]
pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
# [inline (always)]
# [must_use]
pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
# [inline (always)]
# [must_use]
pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
# [inline (always)]
# [must_use]
pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bit 7 - Manchester Encode enable"]
# [inline (always)]
# [must_use]
pub fn ctl0_menc (& mut self) -> CTL0_MENC_W < CTL0_SPEC , 7 > { CTL0_MENC_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
# [inline (always)]
# [must_use]
pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
# [inline (always)]
# [must_use]
pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"]
# [inline (always)]
# [must_use]
pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"]
# [inline (always)]
# [must_use]
pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
# [inline (always)]
# [must_use]
pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"]
# [inline (always)]
# [must_use]
pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
# [inline (always)]
# [must_use]
pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
# [inline (always)]
# [must_use]
pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"]
impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } } # [doc = "LCRH (rw) register accessor: UART Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcrh::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcrh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcrh`]
module"]
pub type LCRH = crate :: Reg < lcrh :: LCRH_SPEC > ; # [doc = "UART Line Control Register"]
pub mod lcrh { # [doc = "Register `LCRH` reader"]
pub type R = crate :: R < LCRH_SPEC > ; # [doc = "Register `LCRH` writer"]
pub type W = crate :: W < LCRH_SPEC > ; # [doc = "Field `LCRH_BRK` reader - UART Send Break (for LIN Protocol)"]
pub type LCRH_BRK_R = crate :: BitReader < LCRH_BRK_A > ; # [doc = "UART Send Break (for LIN Protocol)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_BRK_A { # [doc = "0: DISABLE"]
LCRH_BRK_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_BRK_ENABLE = 1 , } impl From < LCRH_BRK_A > for bool { # [inline (always)]
fn from (variant : LCRH_BRK_A) -> Self { variant as u8 != 0 } } impl LCRH_BRK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_BRK_A { match self . bits { false => LCRH_BRK_A :: LCRH_BRK_DISABLE , true => LCRH_BRK_A :: LCRH_BRK_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_brk_disable (& self) -> bool { * self == LCRH_BRK_A :: LCRH_BRK_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_brk_enable (& self) -> bool { * self == LCRH_BRK_A :: LCRH_BRK_ENABLE } } # [doc = "Field `LCRH_BRK` writer - UART Send Break (for LIN Protocol)"]
pub type LCRH_BRK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_BRK_A > ; impl < 'a , REG , const O : u8 > LCRH_BRK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_brk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_BRK_A :: LCRH_BRK_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_brk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_BRK_A :: LCRH_BRK_ENABLE) } } # [doc = "Field `LCRH_PEN` reader - UART Parity Enable"]
pub type LCRH_PEN_R = crate :: BitReader < LCRH_PEN_A > ; # [doc = "UART Parity Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_PEN_A { # [doc = "0: DISABLE"]
LCRH_PEN_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_PEN_ENABLE = 1 , } impl From < LCRH_PEN_A > for bool { # [inline (always)]
fn from (variant : LCRH_PEN_A) -> Self { variant as u8 != 0 } } impl LCRH_PEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_PEN_A { match self . bits { false => LCRH_PEN_A :: LCRH_PEN_DISABLE , true => LCRH_PEN_A :: LCRH_PEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_pen_disable (& self) -> bool { * self == LCRH_PEN_A :: LCRH_PEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_pen_enable (& self) -> bool { * self == LCRH_PEN_A :: LCRH_PEN_ENABLE } } # [doc = "Field `LCRH_PEN` writer - UART Parity Enable"]
pub type LCRH_PEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_PEN_A > ; impl < 'a , REG , const O : u8 > LCRH_PEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_pen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_PEN_A :: LCRH_PEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_pen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_PEN_A :: LCRH_PEN_ENABLE) } } # [doc = "Field `LCRH_EPS` reader - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
pub type LCRH_EPS_R = crate :: BitReader < LCRH_EPS_A > ; # [doc = "UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_EPS_A { # [doc = "0: ODD"]
LCRH_EPS_ODD = 0 , # [doc = "1: EVEN"]
LCRH_EPS_EVEN = 1 , } impl From < LCRH_EPS_A > for bool { # [inline (always)]
fn from (variant : LCRH_EPS_A) -> Self { variant as u8 != 0 } } impl LCRH_EPS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_EPS_A { match self . bits { false => LCRH_EPS_A :: LCRH_EPS_ODD , true => LCRH_EPS_A :: LCRH_EPS_EVEN , } } # [doc = "ODD"]
# [inline (always)]
pub fn is_lcrh_eps_odd (& self) -> bool { * self == LCRH_EPS_A :: LCRH_EPS_ODD } # [doc = "EVEN"]
# [inline (always)]
pub fn is_lcrh_eps_even (& self) -> bool { * self == LCRH_EPS_A :: LCRH_EPS_EVEN } } # [doc = "Field `LCRH_EPS` writer - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
pub type LCRH_EPS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_EPS_A > ; impl < 'a , REG , const O : u8 > LCRH_EPS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ODD"]
# [inline (always)]
pub fn lcrh_eps_odd (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_EPS_A :: LCRH_EPS_ODD) } # [doc = "EVEN"]
# [inline (always)]
pub fn lcrh_eps_even (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_EPS_A :: LCRH_EPS_EVEN) } } # [doc = "Field `LCRH_STP2` reader - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
pub type LCRH_STP2_R = crate :: BitReader < LCRH_STP2_A > ; # [doc = "UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_STP2_A { # [doc = "0: DISABLE"]
LCRH_STP2_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_STP2_ENABLE = 1 , } impl From < LCRH_STP2_A > for bool { # [inline (always)]
fn from (variant : LCRH_STP2_A) -> Self { variant as u8 != 0 } } impl LCRH_STP2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_STP2_A { match self . bits { false => LCRH_STP2_A :: LCRH_STP2_DISABLE , true => LCRH_STP2_A :: LCRH_STP2_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_stp2_disable (& self) -> bool { * self == LCRH_STP2_A :: LCRH_STP2_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_stp2_enable (& self) -> bool { * self == LCRH_STP2_A :: LCRH_STP2_ENABLE } } # [doc = "Field `LCRH_STP2` writer - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
pub type LCRH_STP2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_STP2_A > ; impl < 'a , REG , const O : u8 > LCRH_STP2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_stp2_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_STP2_A :: LCRH_STP2_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_stp2_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_STP2_A :: LCRH_STP2_ENABLE) } } # [doc = "Field `LCRH_WLEN` reader - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
pub type LCRH_WLEN_R = crate :: FieldReader < LCRH_WLEN_A > ; # [doc = "UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum LCRH_WLEN_A { # [doc = "0: DATABIT5"]
LCRH_WLEN_DATABIT5 = 0 , # [doc = "1: DATABIT6"]
LCRH_WLEN_DATABIT6 = 1 , # [doc = "2: DATABIT7"]
LCRH_WLEN_DATABIT7 = 2 , # [doc = "3: DATABIT8"]
LCRH_WLEN_DATABIT8 = 3 , } impl From < LCRH_WLEN_A > for u8 { # [inline (always)]
fn from (variant : LCRH_WLEN_A) -> Self { variant as _ } } impl crate :: FieldSpec for LCRH_WLEN_A { type Ux = u8 ; } impl LCRH_WLEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_WLEN_A { match self . bits { 0 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT5 , 1 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT6 , 2 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT7 , 3 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT8 , _ => unreachable ! () , } } # [doc = "DATABIT5"]
# [inline (always)]
pub fn is_lcrh_wlen_databit5 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT5 } # [doc = "DATABIT6"]
# [inline (always)]
pub fn is_lcrh_wlen_databit6 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT6 } # [doc = "DATABIT7"]
# [inline (always)]
pub fn is_lcrh_wlen_databit7 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT7 } # [doc = "DATABIT8"]
# [inline (always)]
pub fn is_lcrh_wlen_databit8 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT8 } } # [doc = "Field `LCRH_WLEN` writer - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
pub type LCRH_WLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , LCRH_WLEN_A > ; impl < 'a , REG , const O : u8 > LCRH_WLEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DATABIT5"]
# [inline (always)]
pub fn lcrh_wlen_databit5 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT5) } # [doc = "DATABIT6"]
# [inline (always)]
pub fn lcrh_wlen_databit6 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT6) } # [doc = "DATABIT7"]
# [inline (always)]
pub fn lcrh_wlen_databit7 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT7) } # [doc = "DATABIT8"]
# [inline (always)]
pub fn lcrh_wlen_databit8 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT8) } } # [doc = "Field `LCRH_SPS` reader - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
pub type LCRH_SPS_R = crate :: BitReader < LCRH_SPS_A > ; # [doc = "UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_SPS_A { # [doc = "0: DISABLE"]
LCRH_SPS_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_SPS_ENABLE = 1 , } impl From < LCRH_SPS_A > for bool { # [inline (always)]
fn from (variant : LCRH_SPS_A) -> Self { variant as u8 != 0 } } impl LCRH_SPS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_SPS_A { match self . bits { false => LCRH_SPS_A :: LCRH_SPS_DISABLE , true => LCRH_SPS_A :: LCRH_SPS_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_sps_disable (& self) -> bool { * self == LCRH_SPS_A :: LCRH_SPS_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_sps_enable (& self) -> bool { * self == LCRH_SPS_A :: LCRH_SPS_ENABLE } } # [doc = "Field `LCRH_SPS` writer - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
pub type LCRH_SPS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_SPS_A > ; impl < 'a , REG , const O : u8 > LCRH_SPS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_sps_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SPS_A :: LCRH_SPS_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_sps_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SPS_A :: LCRH_SPS_ENABLE) } } # [doc = "Field `LCRH_SENDIDLE` reader - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
pub type LCRH_SENDIDLE_R = crate :: BitReader < LCRH_SENDIDLE_A > ; # [doc = "UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_SENDIDLE_A { # [doc = "0: DISABLE"]
LCRH_SENDIDLE_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_SENDIDLE_ENABLE = 1 , } impl From < LCRH_SENDIDLE_A > for bool { # [inline (always)]
fn from (variant : LCRH_SENDIDLE_A) -> Self { variant as u8 != 0 } } impl LCRH_SENDIDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_SENDIDLE_A { match self . bits { false => LCRH_SENDIDLE_A :: LCRH_SENDIDLE_DISABLE , true => LCRH_SENDIDLE_A :: LCRH_SENDIDLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_sendidle_disable (& self) -> bool { * self == LCRH_SENDIDLE_A :: LCRH_SENDIDLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_sendidle_enable (& self) -> bool { * self == LCRH_SENDIDLE_A :: LCRH_SENDIDLE_ENABLE } } # [doc = "Field `LCRH_SENDIDLE` writer - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
pub type LCRH_SENDIDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_SENDIDLE_A > ; impl < 'a , REG , const O : u8 > LCRH_SENDIDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_sendidle_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SENDIDLE_A :: LCRH_SENDIDLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_sendidle_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SENDIDLE_A :: LCRH_SENDIDLE_ENABLE) } } # [doc = "Field `LCRH_EXTDIR_SETUP` reader - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
pub type LCRH_EXTDIR_SETUP_R = crate :: FieldReader ; # [doc = "Field `LCRH_EXTDIR_SETUP` writer - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
pub type LCRH_EXTDIR_SETUP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O > ; # [doc = "Field `LCRH_EXTDIR_HOLD` reader - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
pub type LCRH_EXTDIR_HOLD_R = crate :: FieldReader ; # [doc = "Field `LCRH_EXTDIR_HOLD` writer - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
pub type LCRH_EXTDIR_HOLD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O > ; impl R { # [doc = "Bit 0 - UART Send Break (for LIN Protocol)"]
# [inline (always)]
pub fn lcrh_brk (& self) -> LCRH_BRK_R { LCRH_BRK_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - UART Parity Enable"]
# [inline (always)]
pub fn lcrh_pen (& self) -> LCRH_PEN_R { LCRH_PEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
# [inline (always)]
pub fn lcrh_eps (& self) -> LCRH_EPS_R { LCRH_EPS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
# [inline (always)]
pub fn lcrh_stp2 (& self) -> LCRH_STP2_R { LCRH_STP2_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
# [inline (always)]
pub fn lcrh_wlen (& self) -> LCRH_WLEN_R { LCRH_WLEN_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
# [inline (always)]
pub fn lcrh_sps (& self) -> LCRH_SPS_R { LCRH_SPS_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
# [inline (always)]
pub fn lcrh_sendidle (& self) -> LCRH_SENDIDLE_R { LCRH_SENDIDLE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:20 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
# [inline (always)]
pub fn lcrh_extdir_setup (& self) -> LCRH_EXTDIR_SETUP_R { LCRH_EXTDIR_SETUP_R :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:25 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
# [inline (always)]
pub fn lcrh_extdir_hold (& self) -> LCRH_EXTDIR_HOLD_R { LCRH_EXTDIR_HOLD_R :: new (((self . bits >> 21) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - UART Send Break (for LIN Protocol)"]
# [inline (always)]
# [must_use]
pub fn lcrh_brk (& mut self) -> LCRH_BRK_W < LCRH_SPEC , 0 > { LCRH_BRK_W :: new (self) } # [doc = "Bit 1 - UART Parity Enable"]
# [inline (always)]
# [must_use]
pub fn lcrh_pen (& mut self) -> LCRH_PEN_W < LCRH_SPEC , 1 > { LCRH_PEN_W :: new (self) } # [doc = "Bit 2 - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
# [inline (always)]
# [must_use]
pub fn lcrh_eps (& mut self) -> LCRH_EPS_W < LCRH_SPEC , 2 > { LCRH_EPS_W :: new (self) } # [doc = "Bit 3 - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
# [inline (always)]
# [must_use]
pub fn lcrh_stp2 (& mut self) -> LCRH_STP2_W < LCRH_SPEC , 3 > { LCRH_STP2_W :: new (self) } # [doc = "Bits 4:5 - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
# [inline (always)]
# [must_use]
pub fn lcrh_wlen (& mut self) -> LCRH_WLEN_W < LCRH_SPEC , 4 > { LCRH_WLEN_W :: new (self) } # [doc = "Bit 6 - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
# [inline (always)]
# [must_use]
pub fn lcrh_sps (& mut self) -> LCRH_SPS_W < LCRH_SPEC , 6 > { LCRH_SPS_W :: new (self) } # [doc = "Bit 7 - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
# [inline (always)]
# [must_use]
pub fn lcrh_sendidle (& mut self) -> LCRH_SENDIDLE_W < LCRH_SPEC , 7 > { LCRH_SENDIDLE_W :: new (self) } # [doc = "Bits 16:20 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
# [inline (always)]
# [must_use]
pub fn lcrh_extdir_setup (& mut self) -> LCRH_EXTDIR_SETUP_W < LCRH_SPEC , 16 > { LCRH_EXTDIR_SETUP_W :: new (self) } # [doc = "Bits 21:25 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
# [inline (always)]
# [must_use]
pub fn lcrh_extdir_hold (& mut self) -> LCRH_EXTDIR_HOLD_W < LCRH_SPEC , 21 > { LCRH_EXTDIR_HOLD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcrh::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcrh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LCRH_SPEC ; impl crate :: RegisterSpec for LCRH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`lcrh::R`](R) reader structure"]
impl crate :: Readable for LCRH_SPEC { } # [doc = "`write(|w| ..)` method takes [`lcrh::W`](W) writer structure"]
impl crate :: Writable for LCRH_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LCRH to value 0"]
impl crate :: Resettable for LCRH_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "UART Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_BUSY` reader - UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation."]
pub type STAT_BUSY_R = crate :: BitReader < STAT_BUSY_A > ; # [doc = "UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_BUSY_A { # [doc = "0: CLEARED"]
STAT_BUSY_CLEARED = 0 , # [doc = "1: SET"]
STAT_BUSY_SET = 1 , } impl From < STAT_BUSY_A > for bool { # [inline (always)]
fn from (variant : STAT_BUSY_A) -> Self { variant as u8 != 0 } } impl STAT_BUSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_BUSY_A { match self . bits { false => STAT_BUSY_A :: STAT_BUSY_CLEARED , true => STAT_BUSY_A :: STAT_BUSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_busy_cleared (& self) -> bool { * self == STAT_BUSY_A :: STAT_BUSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_busy_set (& self) -> bool { * self == STAT_BUSY_A :: STAT_BUSY_SET } } # [doc = "Field `STAT_RXFE` reader - UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_RXFE_R = crate :: BitReader < STAT_RXFE_A > ; # [doc = "UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RXFE_A { # [doc = "0: CLEARED"]
STAT_RXFE_CLEARED = 0 , # [doc = "1: SET"]
STAT_RXFE_SET = 1 , } impl From < STAT_RXFE_A > for bool { # [inline (always)]
fn from (variant : STAT_RXFE_A) -> Self { variant as u8 != 0 } } impl STAT_RXFE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RXFE_A { match self . bits { false => STAT_RXFE_A :: STAT_RXFE_CLEARED , true => STAT_RXFE_A :: STAT_RXFE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_rxfe_cleared (& self) -> bool { * self == STAT_RXFE_A :: STAT_RXFE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_rxfe_set (& self) -> bool { * self == STAT_RXFE_A :: STAT_RXFE_SET } } # [doc = "Field `STAT_RXFF` reader - UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_RXFF_R = crate :: BitReader < STAT_RXFF_A > ; # [doc = "UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RXFF_A { # [doc = "0: CLEARED"]
STAT_RXFF_CLEARED = 0 , # [doc = "1: SET"]
STAT_RXFF_SET = 1 , } impl From < STAT_RXFF_A > for bool { # [inline (always)]
fn from (variant : STAT_RXFF_A) -> Self { variant as u8 != 0 } } impl STAT_RXFF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RXFF_A { match self . bits { false => STAT_RXFF_A :: STAT_RXFF_CLEARED , true => STAT_RXFF_A :: STAT_RXFF_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_rxff_cleared (& self) -> bool { * self == STAT_RXFF_A :: STAT_RXFF_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_rxff_set (& self) -> bool { * self == STAT_RXFF_A :: STAT_RXFF_SET } } # [doc = "Field `STAT_TXFE` reader - UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_TXFE_R = crate :: BitReader < STAT_TXFE_A > ; # [doc = "UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_TXFE_A { # [doc = "0: CLEARED"]
STAT_TXFE_CLEARED = 0 , # [doc = "1: SET"]
STAT_TXFE_SET = 1 , } impl From < STAT_TXFE_A > for bool { # [inline (always)]
fn from (variant : STAT_TXFE_A) -> Self { variant as u8 != 0 } } impl STAT_TXFE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_TXFE_A { match self . bits { false => STAT_TXFE_A :: STAT_TXFE_CLEARED , true => STAT_TXFE_A :: STAT_TXFE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_txfe_cleared (& self) -> bool { * self == STAT_TXFE_A :: STAT_TXFE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_txfe_set (& self) -> bool { * self == STAT_TXFE_A :: STAT_TXFE_SET } } # [doc = "Field `STAT_TXFF` reader - UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_TXFF_R = crate :: BitReader < STAT_TXFF_A > ; # [doc = "UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_TXFF_A { # [doc = "0: CLEARED"]
STAT_TXFF_CLEARED = 0 , # [doc = "1: SET"]
STAT_TXFF_SET = 1 , } impl From < STAT_TXFF_A > for bool { # [inline (always)]
fn from (variant : STAT_TXFF_A) -> Self { variant as u8 != 0 } } impl STAT_TXFF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_TXFF_A { match self . bits { false => STAT_TXFF_A :: STAT_TXFF_CLEARED , true => STAT_TXFF_A :: STAT_TXFF_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_txff_cleared (& self) -> bool { * self == STAT_TXFF_A :: STAT_TXFF_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_txff_set (& self) -> bool { * self == STAT_TXFF_A :: STAT_TXFF_SET } } # [doc = "Field `STAT_CTS` reader - Clear To Send"]
pub type STAT_CTS_R = crate :: BitReader < STAT_CTS_A > ; # [doc = "Clear To Send\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_CTS_A { # [doc = "0: CLEARED"]
STAT_CTS_CLEARED = 0 , # [doc = "1: SET"]
STAT_CTS_SET = 1 , } impl From < STAT_CTS_A > for bool { # [inline (always)]
fn from (variant : STAT_CTS_A) -> Self { variant as u8 != 0 } } impl STAT_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_CTS_A { match self . bits { false => STAT_CTS_A :: STAT_CTS_CLEARED , true => STAT_CTS_A :: STAT_CTS_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_cts_cleared (& self) -> bool { * self == STAT_CTS_A :: STAT_CTS_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_cts_set (& self) -> bool { * self == STAT_CTS_A :: STAT_CTS_SET } } # [doc = "Field `STAT_IDLE` reader - IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address."]
pub type STAT_IDLE_R = crate :: BitReader < STAT_IDLE_A > ; # [doc = "IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_IDLE_A { # [doc = "0: CLEARED"]
STAT_IDLE_CLEARED = 0 , # [doc = "1: SET"]
STAT_IDLE_SET = 1 , } impl From < STAT_IDLE_A > for bool { # [inline (always)]
fn from (variant : STAT_IDLE_A) -> Self { variant as u8 != 0 } } impl STAT_IDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_IDLE_A { match self . bits { false => STAT_IDLE_A :: STAT_IDLE_CLEARED , true => STAT_IDLE_A :: STAT_IDLE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_idle_cleared (& self) -> bool { * self == STAT_IDLE_A :: STAT_IDLE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_idle_set (& self) -> bool { * self == STAT_IDLE_A :: STAT_IDLE_SET } } impl R { # [doc = "Bit 0 - UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation."]
# [inline (always)]
pub fn stat_busy (& self) -> STAT_BUSY_R { STAT_BUSY_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_rxfe (& self) -> STAT_RXFE_R { STAT_RXFE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_rxff (& self) -> STAT_RXFF_R { STAT_RXFF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 6 - UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_txfe (& self) -> STAT_TXFE_R { STAT_TXFE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_txff (& self) -> STAT_TXFF_R { STAT_TXFF_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Clear To Send"]
# [inline (always)]
pub fn stat_cts (& self) -> STAT_CTS_R { STAT_CTS_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address."]
# [inline (always)]
pub fn stat_idle (& self) -> STAT_IDLE_R { STAT_IDLE_R :: new (((self . bits >> 9) & 1) != 0) } } # [doc = "UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IFLS (rw) register accessor: UART Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifls`]
module"]
pub type IFLS = crate :: Reg < ifls :: IFLS_SPEC > ; # [doc = "UART Interrupt FIFO Level Select Register"]
pub mod ifls { # [doc = "Register `IFLS` reader"]
pub type R = crate :: R < IFLS_SPEC > ; # [doc = "Register `IFLS` writer"]
pub type W = crate :: W < IFLS_SPEC > ; # [doc = "Field `IFLS_TXIFLSEL` reader - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
pub type IFLS_TXIFLSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_TXIFLSEL` writer - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
pub type IFLS_TXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `IFLS_RXIFLSEL` reader - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
pub type IFLS_RXIFLSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_RXIFLSEL` writer - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
pub type IFLS_RXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `IFLS_RXTOSEL` reader - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
pub type IFLS_RXTOSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_RXTOSEL` writer - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
pub type IFLS_RXTOSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bits 0:2 - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
# [inline (always)]
pub fn ifls_txiflsel (& self) -> IFLS_TXIFLSEL_R { IFLS_TXIFLSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
# [inline (always)]
pub fn ifls_rxiflsel (& self) -> IFLS_RXIFLSEL_R { IFLS_RXIFLSEL_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:11 - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
# [inline (always)]
pub fn ifls_rxtosel (& self) -> IFLS_RXTOSEL_R { IFLS_RXTOSEL_R :: new (((self . bits >> 8) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:2 - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
# [inline (always)]
# [must_use]
pub fn ifls_txiflsel (& mut self) -> IFLS_TXIFLSEL_W < IFLS_SPEC , 0 > { IFLS_TXIFLSEL_W :: new (self) } # [doc = "Bits 4:6 - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
# [inline (always)]
# [must_use]
pub fn ifls_rxiflsel (& mut self) -> IFLS_RXIFLSEL_W < IFLS_SPEC , 4 > { IFLS_RXIFLSEL_W :: new (self) } # [doc = "Bits 8:11 - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
# [inline (always)]
# [must_use]
pub fn ifls_rxtosel (& mut self) -> IFLS_RXTOSEL_W < IFLS_SPEC , 8 > { IFLS_RXTOSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IFLS_SPEC ; impl crate :: RegisterSpec for IFLS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifls::R`](R) reader structure"]
impl crate :: Readable for IFLS_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"]
impl crate :: Writable for IFLS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFLS to value 0x22"]
impl crate :: Resettable for IFLS_SPEC { const RESET_VALUE : Self :: Ux = 0x22 ; } } # [doc = "IBRD (rw) register accessor: UART Integer Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibrd`]
module"]
pub type IBRD = crate :: Reg < ibrd :: IBRD_SPEC > ; # [doc = "UART Integer Baud-Rate Divisor Register"]
pub mod ibrd { # [doc = "Register `IBRD` reader"]
pub type R = crate :: R < IBRD_SPEC > ; # [doc = "Register `IBRD` writer"]
pub type W = crate :: W < IBRD_SPEC > ; # [doc = "Field `IBRD_DIVINT` reader - Integer Baud-Rate Divisor"]
pub type IBRD_DIVINT_R = crate :: FieldReader < u16 > ; # [doc = "Field `IBRD_DIVINT` writer - Integer Baud-Rate Divisor"]
pub type IBRD_DIVINT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Integer Baud-Rate Divisor"]
# [inline (always)]
pub fn ibrd_divint (& self) -> IBRD_DIVINT_R { IBRD_DIVINT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Integer Baud-Rate Divisor"]
# [inline (always)]
# [must_use]
pub fn ibrd_divint (& mut self) -> IBRD_DIVINT_W < IBRD_SPEC , 0 > { IBRD_DIVINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Integer Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IBRD_SPEC ; impl crate :: RegisterSpec for IBRD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ibrd::R`](R) reader structure"]
impl crate :: Readable for IBRD_SPEC { } # [doc = "`write(|w| ..)` method takes [`ibrd::W`](W) writer structure"]
impl crate :: Writable for IBRD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IBRD to value 0"]
impl crate :: Resettable for IBRD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FBRD (rw) register accessor: UART Fractional Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fbrd`]
module"]
pub type FBRD = crate :: Reg < fbrd :: FBRD_SPEC > ; # [doc = "UART Fractional Baud-Rate Divisor Register"]
pub mod fbrd { # [doc = "Register `FBRD` reader"]
pub type R = crate :: R < FBRD_SPEC > ; # [doc = "Register `FBRD` writer"]
pub type W = crate :: W < FBRD_SPEC > ; # [doc = "Field `FBRD_DIVFRAC` reader - Fractional Baud-Rate Divisor"]
pub type FBRD_DIVFRAC_R = crate :: FieldReader ; # [doc = "Field `FBRD_DIVFRAC` writer - Fractional Baud-Rate Divisor"]
pub type FBRD_DIVFRAC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O > ; impl R { # [doc = "Bits 0:5 - Fractional Baud-Rate Divisor"]
# [inline (always)]
pub fn fbrd_divfrac (& self) -> FBRD_DIVFRAC_R { FBRD_DIVFRAC_R :: new ((self . bits & 0x3f) as u8) } } impl W { # [doc = "Bits 0:5 - Fractional Baud-Rate Divisor"]
# [inline (always)]
# [must_use]
pub fn fbrd_divfrac (& mut self) -> FBRD_DIVFRAC_W < FBRD_SPEC , 0 > { FBRD_DIVFRAC_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Fractional Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FBRD_SPEC ; impl crate :: RegisterSpec for FBRD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fbrd::R`](R) reader structure"]
impl crate :: Readable for FBRD_SPEC { } # [doc = "`write(|w| ..)` method takes [`fbrd::W`](W) writer structure"]
impl crate :: Writable for FBRD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FBRD to value 0"]
impl crate :: Resettable for FBRD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GFCTL (rw) register accessor: Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gfctl`]
module"]
pub type GFCTL = crate :: Reg < gfctl :: GFCTL_SPEC > ; # [doc = "Glitch Filter Control"]
pub mod gfctl { # [doc = "Register `GFCTL` reader"]
pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"]
pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_DGFSEL` reader - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The following values are the glitch suppression values in terms of functional clocks. In IRDA mode: Receive filter length. The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK)"]
pub type GFCTL_DGFSEL_R = crate :: FieldReader < GFCTL_DGFSEL_A > ; # [doc = "Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The following values are the glitch suppression values in terms of functional clocks. In IRDA mode: Receive filter length. The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GFCTL_DGFSEL_A { # [doc = "0: DISABLED"]
GFCTL_DGFSEL_DISABLED = 0 , } impl From < GFCTL_DGFSEL_A > for u8 { # [inline (always)]
fn from (variant : GFCTL_DGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_DGFSEL_A { type Ux = u8 ; } impl GFCTL_DGFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < GFCTL_DGFSEL_A > { match self . bits { 0 => Some (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) , _ => None , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_gfctl_dgfsel_disabled (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED } } # [doc = "Field `GFCTL_DGFSEL` writer - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The following values are the glitch suppression values in terms of functional clocks. In IRDA mode: Receive filter length. The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK)"]
pub type GFCTL_DGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O , GFCTL_DGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_DGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn gfctl_dgfsel_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) } } # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"]
GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"]
GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)]
fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"]
GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"]
GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"]
GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"]
GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)]
fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } # [doc = "Field `GFCTL_CHAIN` reader - Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling"]
pub type GFCTL_CHAIN_R = crate :: BitReader < GFCTL_CHAIN_A > ; # [doc = "Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GFCTL_CHAIN_A { # [doc = "0: DISABLED"]
GFCTL_CHAIN_DISABLED = 0 , # [doc = "1: ENABLED"]
GFCTL_CHAIN_ENABLED = 1 , } impl From < GFCTL_CHAIN_A > for bool { # [inline (always)]
fn from (variant : GFCTL_CHAIN_A) -> Self { variant as u8 != 0 } } impl GFCTL_CHAIN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_CHAIN_A { match self . bits { false => GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLED , true => GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_gfctl_chain_disabled (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_gfctl_chain_enabled (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLED } } # [doc = "Field `GFCTL_CHAIN` writer - Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling"]
pub type GFCTL_CHAIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_CHAIN_A > ; impl < 'a , REG , const O : u8 > GFCTL_CHAIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn gfctl_chain_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn gfctl_chain_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLED) } } impl R { # [doc = "Bits 0:5 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The following values are the glitch suppression values in terms of functional clocks. In IRDA mode: Receive filter length. The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK)"]
# [inline (always)]
pub fn gfctl_dgfsel (& self) -> GFCTL_DGFSEL_R { GFCTL_DGFSEL_R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
# [inline (always)]
pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling"]
# [inline (always)]
pub fn gfctl_chain (& self) -> GFCTL_CHAIN_R { GFCTL_CHAIN_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the RX line. The following values are the glitch suppression values in terms of functional clocks. In IRDA mode: Receive filter length. The minimum pulse length for receive is given by: t(MIN) = (DGFSEL) / f(IRTXCLK)"]
# [inline (always)]
# [must_use]
pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W < GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable. 0 DISABLE: When 0, chaining is disabled and only digital filter output is available to IP logic for sampling 1 ENABLE: When 1, analog and digital glitch filters are chained and the output of the combination is made available to IP logic for sampling"]
# [inline (always)]
# [must_use]
pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W < GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"]
impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"]
impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"]
impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TXDATA (rw) register accessor: UART Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdata::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txdata`]
module"]
pub type TXDATA = crate :: Reg < txdata :: TXDATA_SPEC > ; # [doc = "UART Transmit Data Register"]
pub mod txdata { # [doc = "Register `TXDATA` reader"]
pub type R = crate :: R < TXDATA_SPEC > ; # [doc = "Register `TXDATA` writer"]
pub type W = crate :: W < TXDATA_SPEC > ; # [doc = "Field `TXDATA_DATA` reader - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
pub type TXDATA_DATA_R = crate :: FieldReader ; # [doc = "Field `TXDATA_DATA` writer - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
pub type TXDATA_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
# [inline (always)]
pub fn txdata_data (& self) -> TXDATA_DATA_R { TXDATA_DATA_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
# [inline (always)]
# [must_use]
pub fn txdata_data (& mut self) -> TXDATA_DATA_W < TXDATA_SPEC , 0 > { TXDATA_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TXDATA_SPEC ; impl crate :: RegisterSpec for TXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`txdata::R`](R) reader structure"]
impl crate :: Readable for TXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`txdata::W`](W) writer structure"]
impl crate :: Writable for TXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TXDATA to value 0"]
impl crate :: Resettable for TXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RXDATA (r) register accessor: UART Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdata`]
module"]
pub type RXDATA = crate :: Reg < rxdata :: RXDATA_SPEC > ; # [doc = "UART Receive Data Register"]
pub mod rxdata { # [doc = "Register `RXDATA` reader"]
pub type R = crate :: R < RXDATA_SPEC > ; # [doc = "Field `RXDATA_DATA` reader - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
pub type RXDATA_DATA_R = crate :: FieldReader ; # [doc = "Field `RXDATA_FRMERR` reader - UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO."]
pub type RXDATA_FRMERR_R = crate :: BitReader < RXDATA_FRMERR_A > ; # [doc = "UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_FRMERR_A { # [doc = "0: CLR"]
RXDATA_FRMERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_FRMERR_SET = 1 , } impl From < RXDATA_FRMERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_FRMERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_FRMERR_A { match self . bits { false => RXDATA_FRMERR_A :: RXDATA_FRMERR_CLR , true => RXDATA_FRMERR_A :: RXDATA_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_frmerr_clr (& self) -> bool { * self == RXDATA_FRMERR_A :: RXDATA_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_frmerr_set (& self) -> bool { * self == RXDATA_FRMERR_A :: RXDATA_FRMERR_SET } } # [doc = "Field `RXDATA_PARERR` reader - UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register."]
pub type RXDATA_PARERR_R = crate :: BitReader < RXDATA_PARERR_A > ; # [doc = "UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_PARERR_A { # [doc = "0: CLR"]
RXDATA_PARERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_PARERR_SET = 1 , } impl From < RXDATA_PARERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_PARERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_PARERR_A { match self . bits { false => RXDATA_PARERR_A :: RXDATA_PARERR_CLR , true => RXDATA_PARERR_A :: RXDATA_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_parerr_clr (& self) -> bool { * self == RXDATA_PARERR_A :: RXDATA_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_parerr_set (& self) -> bool { * self == RXDATA_PARERR_A :: RXDATA_PARERR_SET } } # [doc = "Field `RXDATA_BRKERR` reader - UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
pub type RXDATA_BRKERR_R = crate :: BitReader < RXDATA_BRKERR_A > ; # [doc = "UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_BRKERR_A { # [doc = "0: CLR"]
RXDATA_BRKERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_BRKERR_SET = 1 , } impl From < RXDATA_BRKERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_BRKERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_BRKERR_A { match self . bits { false => RXDATA_BRKERR_A :: RXDATA_BRKERR_CLR , true => RXDATA_BRKERR_A :: RXDATA_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_brkerr_clr (& self) -> bool { * self == RXDATA_BRKERR_A :: RXDATA_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_brkerr_set (& self) -> bool { * self == RXDATA_BRKERR_A :: RXDATA_BRKERR_SET } } # [doc = "Field `RXDATA_OVRERR` reader - UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO."]
pub type RXDATA_OVRERR_R = crate :: BitReader < RXDATA_OVRERR_A > ; # [doc = "UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_OVRERR_A { # [doc = "0: CLR"]
RXDATA_OVRERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_OVRERR_SET = 1 , } impl From < RXDATA_OVRERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_OVRERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_OVRERR_A { match self . bits { false => RXDATA_OVRERR_A :: RXDATA_OVRERR_CLR , true => RXDATA_OVRERR_A :: RXDATA_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_ovrerr_clr (& self) -> bool { * self == RXDATA_OVRERR_A :: RXDATA_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_ovrerr_set (& self) -> bool { * self == RXDATA_OVRERR_A :: RXDATA_OVRERR_SET } } # [doc = "Field `RXDATA_NERR` reader - Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register."]
pub type RXDATA_NERR_R = crate :: BitReader < RXDATA_NERR_A > ; # [doc = "Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_NERR_A { # [doc = "0: CLR"]
RXDATA_NERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_NERR_SET = 1 , } impl From < RXDATA_NERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_NERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_NERR_A { match self . bits { false => RXDATA_NERR_A :: RXDATA_NERR_CLR , true => RXDATA_NERR_A :: RXDATA_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_nerr_clr (& self) -> bool { * self == RXDATA_NERR_A :: RXDATA_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_nerr_set (& self) -> bool { * self == RXDATA_NERR_A :: RXDATA_NERR_SET } } impl R { # [doc = "Bits 0:7 - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
# [inline (always)]
pub fn rxdata_data (& self) -> RXDATA_DATA_R { RXDATA_DATA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 8 - UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO."]
# [inline (always)]
pub fn rxdata_frmerr (& self) -> RXDATA_FRMERR_R { RXDATA_FRMERR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register."]
# [inline (always)]
pub fn rxdata_parerr (& self) -> RXDATA_PARERR_R { RXDATA_PARERR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
# [inline (always)]
pub fn rxdata_brkerr (& self) -> RXDATA_BRKERR_R { RXDATA_BRKERR_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO."]
# [inline (always)]
pub fn rxdata_ovrerr (& self) -> RXDATA_OVRERR_R { RXDATA_OVRERR_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register."]
# [inline (always)]
pub fn rxdata_nerr (& self) -> RXDATA_NERR_R { RXDATA_NERR_R :: new (((self . bits >> 12) & 1) != 0) } } # [doc = "UART Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RXDATA_SPEC ; impl crate :: RegisterSpec for RXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rxdata::R`](R) reader structure"]
impl crate :: Readable for RXDATA_SPEC { } # [doc = "`reset()` method sets RXDATA to value 0"]
impl crate :: Resettable for RXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "LINCNT (rw) register accessor: UART LIN Mode Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lincnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lincnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lincnt`]
module"]
pub type LINCNT = crate :: Reg < lincnt :: LINCNT_SPEC > ; # [doc = "UART LIN Mode Counter Register"]
pub mod lincnt { # [doc = "Register `LINCNT` reader"]
pub type R = crate :: R < LINCNT_SPEC > ; # [doc = "Register `LINCNT` writer"]
pub type W = crate :: W < LINCNT_SPEC > ; # [doc = "Field `LINCNT_VALUE` reader - 16 bit up counter clocked by the module clock of the UART."]
pub type LINCNT_VALUE_R = crate :: FieldReader < u16 > ; # [doc = "Field `LINCNT_VALUE` writer - 16 bit up counter clocked by the module clock of the UART."]
pub type LINCNT_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - 16 bit up counter clocked by the module clock of the UART."]
# [inline (always)]
pub fn lincnt_value (& self) -> LINCNT_VALUE_R { LINCNT_VALUE_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 16 bit up counter clocked by the module clock of the UART."]
# [inline (always)]
# [must_use]
pub fn lincnt_value (& mut self) -> LINCNT_VALUE_W < LINCNT_SPEC , 0 > { LINCNT_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART LIN Mode Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lincnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lincnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LINCNT_SPEC ; impl crate :: RegisterSpec for LINCNT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`lincnt::R`](R) reader structure"]
impl crate :: Readable for LINCNT_SPEC { } # [doc = "`write(|w| ..)` method takes [`lincnt::W`](W) writer structure"]
impl crate :: Writable for LINCNT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LINCNT to value 0"]
impl crate :: Resettable for LINCNT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "LINCTL (rw) register accessor: UART LIN Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`linctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`linctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linctl`]
module"]
pub type LINCTL = crate :: Reg < linctl :: LINCTL_SPEC > ; # [doc = "UART LIN Mode Control Register"]
pub mod linctl { # [doc = "Register `LINCTL` reader"]
pub type R = crate :: R < LINCTL_SPEC > ; # [doc = "Register `LINCTL` writer"]
pub type W = crate :: W < LINCTL_SPEC > ; # [doc = "Field `LINCTL_CTRENA` reader - LIN Counter Enable. LIN counter will only count when enabled."]
pub type LINCTL_CTRENA_R = crate :: BitReader < LINCTL_CTRENA_A > ; # [doc = "LIN Counter Enable. LIN counter will only count when enabled.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LINCTL_CTRENA_A { # [doc = "0: DISABLE"]
LINCTL_CTRENA_DISABLE = 0 , # [doc = "1: ENABLE"]
LINCTL_CTRENA_ENABLE = 1 , } impl From < LINCTL_CTRENA_A > for bool { # [inline (always)]
fn from (variant : LINCTL_CTRENA_A) -> Self { variant as u8 != 0 } } impl LINCTL_CTRENA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LINCTL_CTRENA_A { match self . bits { false => LINCTL_CTRENA_A :: LINCTL_CTRENA_DISABLE , true => LINCTL_CTRENA_A :: LINCTL_CTRENA_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_linctl_ctrena_disable (& self) -> bool { * self == LINCTL_CTRENA_A :: LINCTL_CTRENA_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_linctl_ctrena_enable (& self) -> bool { * self == LINCTL_CTRENA_A :: LINCTL_CTRENA_ENABLE } } # [doc = "Field `LINCTL_CTRENA` writer - LIN Counter Enable. LIN counter will only count when enabled."]
pub type LINCTL_CTRENA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LINCTL_CTRENA_A > ; impl < 'a , REG , const O : u8 > LINCTL_CTRENA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn linctl_ctrena_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_CTRENA_A :: LINCTL_CTRENA_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn linctl_ctrena_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_CTRENA_A :: LINCTL_CTRENA_ENABLE) } } # [doc = "Field `LINCTL_ZERONE` reader - Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD"]
pub type LINCTL_ZERONE_R = crate :: BitReader < LINCTL_ZERONE_A > ; # [doc = "Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LINCTL_ZERONE_A { # [doc = "0: DISABLE"]
LINCTL_ZERONE_DISABLE = 0 , # [doc = "1: ENABLE"]
LINCTL_ZERONE_ENABLE = 1 , } impl From < LINCTL_ZERONE_A > for bool { # [inline (always)]
fn from (variant : LINCTL_ZERONE_A) -> Self { variant as u8 != 0 } } impl LINCTL_ZERONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LINCTL_ZERONE_A { match self . bits { false => LINCTL_ZERONE_A :: LINCTL_ZERONE_DISABLE , true => LINCTL_ZERONE_A :: LINCTL_ZERONE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_linctl_zerone_disable (& self) -> bool { * self == LINCTL_ZERONE_A :: LINCTL_ZERONE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_linctl_zerone_enable (& self) -> bool { * self == LINCTL_ZERONE_A :: LINCTL_ZERONE_ENABLE } } # [doc = "Field `LINCTL_ZERONE` writer - Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD"]
pub type LINCTL_ZERONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LINCTL_ZERONE_A > ; impl < 'a , REG , const O : u8 > LINCTL_ZERONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn linctl_zerone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_ZERONE_A :: LINCTL_ZERONE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn linctl_zerone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_ZERONE_A :: LINCTL_ZERONE_ENABLE) } } # [doc = "Field `LINCTL_CNTRXLOW` reader - Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments."]
pub type LINCTL_CNTRXLOW_R = crate :: BitReader < LINCTL_CNTRXLOW_A > ; # [doc = "Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LINCTL_CNTRXLOW_A { # [doc = "0: DISABLE"]
LINCTL_CNTRXLOW_DISABLE = 0 , # [doc = "1: ENABLE"]
LINCTL_CNTRXLOW_ENABLE = 1 , } impl From < LINCTL_CNTRXLOW_A > for bool { # [inline (always)]
fn from (variant : LINCTL_CNTRXLOW_A) -> Self { variant as u8 != 0 } } impl LINCTL_CNTRXLOW_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LINCTL_CNTRXLOW_A { match self . bits { false => LINCTL_CNTRXLOW_A :: LINCTL_CNTRXLOW_DISABLE , true => LINCTL_CNTRXLOW_A :: LINCTL_CNTRXLOW_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_linctl_cntrxlow_disable (& self) -> bool { * self == LINCTL_CNTRXLOW_A :: LINCTL_CNTRXLOW_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_linctl_cntrxlow_enable (& self) -> bool { * self == LINCTL_CNTRXLOW_A :: LINCTL_CNTRXLOW_ENABLE } } # [doc = "Field `LINCTL_CNTRXLOW` writer - Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments."]
pub type LINCTL_CNTRXLOW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LINCTL_CNTRXLOW_A > ; impl < 'a , REG , const O : u8 > LINCTL_CNTRXLOW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn linctl_cntrxlow_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_CNTRXLOW_A :: LINCTL_CNTRXLOW_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn linctl_cntrxlow_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_CNTRXLOW_A :: LINCTL_CNTRXLOW_ENABLE) } } # [doc = "Field `LINCTL_LINC0CAP` reader - Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled."]
pub type LINCTL_LINC0CAP_R = crate :: BitReader < LINCTL_LINC0CAP_A > ; # [doc = "Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LINCTL_LINC0CAP_A { # [doc = "0: DISABLE"]
LINCTL_LINC0CAP_DISABLE = 0 , # [doc = "1: ENABLE"]
LINCTL_LINC0CAP_ENABLE = 1 , } impl From < LINCTL_LINC0CAP_A > for bool { # [inline (always)]
fn from (variant : LINCTL_LINC0CAP_A) -> Self { variant as u8 != 0 } } impl LINCTL_LINC0CAP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LINCTL_LINC0CAP_A { match self . bits { false => LINCTL_LINC0CAP_A :: LINCTL_LINC0CAP_DISABLE , true => LINCTL_LINC0CAP_A :: LINCTL_LINC0CAP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_linctl_linc0cap_disable (& self) -> bool { * self == LINCTL_LINC0CAP_A :: LINCTL_LINC0CAP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_linctl_linc0cap_enable (& self) -> bool { * self == LINCTL_LINC0CAP_A :: LINCTL_LINC0CAP_ENABLE } } # [doc = "Field `LINCTL_LINC0CAP` writer - Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled."]
pub type LINCTL_LINC0CAP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LINCTL_LINC0CAP_A > ; impl < 'a , REG , const O : u8 > LINCTL_LINC0CAP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn linctl_linc0cap_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_LINC0CAP_A :: LINCTL_LINC0CAP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn linctl_linc0cap_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_LINC0CAP_A :: LINCTL_LINC0CAP_ENABLE) } } # [doc = "Field `LINCTL_LINC1CAP` reader - Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled."]
pub type LINCTL_LINC1CAP_R = crate :: BitReader < LINCTL_LINC1CAP_A > ; # [doc = "Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LINCTL_LINC1CAP_A { # [doc = "0: DISABLE"]
LINCTL_LINC1CAP_DISABLE = 0 , # [doc = "1: ENABLE"]
LINCTL_LINC1CAP_ENABLE = 1 , } impl From < LINCTL_LINC1CAP_A > for bool { # [inline (always)]
fn from (variant : LINCTL_LINC1CAP_A) -> Self { variant as u8 != 0 } } impl LINCTL_LINC1CAP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LINCTL_LINC1CAP_A { match self . bits { false => LINCTL_LINC1CAP_A :: LINCTL_LINC1CAP_DISABLE , true => LINCTL_LINC1CAP_A :: LINCTL_LINC1CAP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_linctl_linc1cap_disable (& self) -> bool { * self == LINCTL_LINC1CAP_A :: LINCTL_LINC1CAP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_linctl_linc1cap_enable (& self) -> bool { * self == LINCTL_LINC1CAP_A :: LINCTL_LINC1CAP_ENABLE } } # [doc = "Field `LINCTL_LINC1CAP` writer - Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled."]
pub type LINCTL_LINC1CAP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LINCTL_LINC1CAP_A > ; impl < 'a , REG , const O : u8 > LINCTL_LINC1CAP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn linctl_linc1cap_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_LINC1CAP_A :: LINCTL_LINC1CAP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn linctl_linc1cap_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_LINC1CAP_A :: LINCTL_LINC1CAP_ENABLE) } } # [doc = "Field `LINCTL_LINC0_MATCH` reader - Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled."]
pub type LINCTL_LINC0_MATCH_R = crate :: BitReader < LINCTL_LINC0_MATCH_A > ; # [doc = "Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LINCTL_LINC0_MATCH_A { # [doc = "0: DISABLE"]
LINCTL_LINC0_MATCH_DISABLE = 0 , # [doc = "1: ENABLE"]
LINCTL_LINC0_MATCH_ENABLE = 1 , } impl From < LINCTL_LINC0_MATCH_A > for bool { # [inline (always)]
fn from (variant : LINCTL_LINC0_MATCH_A) -> Self { variant as u8 != 0 } } impl LINCTL_LINC0_MATCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LINCTL_LINC0_MATCH_A { match self . bits { false => LINCTL_LINC0_MATCH_A :: LINCTL_LINC0_MATCH_DISABLE , true => LINCTL_LINC0_MATCH_A :: LINCTL_LINC0_MATCH_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_linctl_linc0_match_disable (& self) -> bool { * self == LINCTL_LINC0_MATCH_A :: LINCTL_LINC0_MATCH_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_linctl_linc0_match_enable (& self) -> bool { * self == LINCTL_LINC0_MATCH_A :: LINCTL_LINC0_MATCH_ENABLE } } # [doc = "Field `LINCTL_LINC0_MATCH` writer - Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled."]
pub type LINCTL_LINC0_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LINCTL_LINC0_MATCH_A > ; impl < 'a , REG , const O : u8 > LINCTL_LINC0_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn linctl_linc0_match_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_LINC0_MATCH_A :: LINCTL_LINC0_MATCH_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn linctl_linc0_match_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LINCTL_LINC0_MATCH_A :: LINCTL_LINC0_MATCH_ENABLE) } } impl R { # [doc = "Bit 0 - LIN Counter Enable. LIN counter will only count when enabled."]
# [inline (always)]
pub fn linctl_ctrena (& self) -> LINCTL_CTRENA_R { LINCTL_CTRENA_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD"]
# [inline (always)]
pub fn linctl_zerone (& self) -> LINCTL_ZERONE_R { LINCTL_ZERONE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments."]
# [inline (always)]
pub fn linctl_cntrxlow (& self) -> LINCTL_CNTRXLOW_R { LINCTL_CNTRXLOW_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled."]
# [inline (always)]
pub fn linctl_linc0cap (& self) -> LINCTL_LINC0CAP_R { LINCTL_LINC0CAP_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled."]
# [inline (always)]
pub fn linctl_linc1cap (& self) -> LINCTL_LINC1CAP_R { LINCTL_LINC1CAP_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled."]
# [inline (always)]
pub fn linctl_linc0_match (& self) -> LINCTL_LINC0_MATCH_R { LINCTL_LINC0_MATCH_R :: new (((self . bits >> 6) & 1) != 0) } } impl W { # [doc = "Bit 0 - LIN Counter Enable. LIN counter will only count when enabled."]
# [inline (always)]
# [must_use]
pub fn linctl_ctrena (& mut self) -> LINCTL_CTRENA_W < LINCTL_SPEC , 0 > { LINCTL_CTRENA_W :: new (self) } # [doc = "Bit 1 - Zero on negative Edge of RXD. When enabled the counter is set to 0 and starts counting on a negative edge of RXD"]
# [inline (always)]
# [must_use]
pub fn linctl_zerone (& mut self) -> LINCTL_ZERONE_W < LINCTL_SPEC , 1 > { LINCTL_ZERONE_W :: new (self) } # [doc = "Bit 2 - Count while low Signal on RXD When counter is enabled and the signal on RXD is low, the counter increments."]
# [inline (always)]
# [must_use]
pub fn linctl_cntrxlow (& mut self) -> LINCTL_CNTRXLOW_W < LINCTL_SPEC , 2 > { LINCTL_CNTRXLOW_W :: new (self) } # [doc = "Bit 4 - Capture Counter on negative RXD Edge. When enabled the counter value is captured to LINC0 register on each negative RXD edge. A LINC0 interrupt is triggered when enabled."]
# [inline (always)]
# [must_use]
pub fn linctl_linc0cap (& mut self) -> LINCTL_LINC0CAP_W < LINCTL_SPEC , 4 > { LINCTL_LINC0CAP_W :: new (self) } # [doc = "Bit 5 - Capture Counter on positive RXD Edge. When enabled the counter value is captured to LINC1 register on each positive RXD edge. A LINC1 interrupt is triggered when enabled."]
# [inline (always)]
# [must_use]
pub fn linctl_linc1cap (& mut self) -> LINCTL_LINC1CAP_W < LINCTL_SPEC , 5 > { LINCTL_LINC1CAP_W :: new (self) } # [doc = "Bit 6 - Counter Compare Match Mode When this bit is set to 1 a counter compare match with LINC0 register triggers an LINC0 interrupt when enabled."]
# [inline (always)]
# [must_use]
pub fn linctl_linc0_match (& mut self) -> LINCTL_LINC0_MATCH_W < LINCTL_SPEC , 6 > { LINCTL_LINC0_MATCH_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART LIN Mode Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`linctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`linctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LINCTL_SPEC ; impl crate :: RegisterSpec for LINCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`linctl::R`](R) reader structure"]
impl crate :: Readable for LINCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`linctl::W`](W) writer structure"]
impl crate :: Writable for LINCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LINCTL to value 0"]
impl crate :: Resettable for LINCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "LINC0 (rw) register accessor: UART LIN Mode Capture 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`linc0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`linc0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linc0`]
module"]
pub type LINC0 = crate :: Reg < linc0 :: LINC0_SPEC > ; # [doc = "UART LIN Mode Capture 0 Register"]
pub mod linc0 { # [doc = "Register `LINC0` reader"]
pub type R = crate :: R < LINC0_SPEC > ; # [doc = "Register `LINC0` writer"]
pub type W = crate :: W < LINC0_SPEC > ; # [doc = "Field `LINC0_DATA` reader - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt."]
pub type LINC0_DATA_R = crate :: FieldReader < u16 > ; # [doc = "Field `LINC0_DATA` writer - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt."]
pub type LINC0_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt."]
# [inline (always)]
pub fn linc0_data (& self) -> LINC0_DATA_R { LINC0_DATA_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD falling edge when enabled. It can generate a DATA interrupt on capture. If compare mode is enabled (DATA_MATCH = 1) a counter match can generate a LINC0 interrupt."]
# [inline (always)]
# [must_use]
pub fn linc0_data (& mut self) -> LINC0_DATA_W < LINC0_SPEC , 0 > { LINC0_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART LIN Mode Capture 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`linc0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`linc0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LINC0_SPEC ; impl crate :: RegisterSpec for LINC0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`linc0::R`](R) reader structure"]
impl crate :: Readable for LINC0_SPEC { } # [doc = "`write(|w| ..)` method takes [`linc0::W`](W) writer structure"]
impl crate :: Writable for LINC0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LINC0 to value 0"]
impl crate :: Resettable for LINC0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "LINC1 (rw) register accessor: UART LIN Mode Capture 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`linc1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`linc1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@linc1`]
module"]
pub type LINC1 = crate :: Reg < linc1 :: LINC1_SPEC > ; # [doc = "UART LIN Mode Capture 1 Register"]
pub mod linc1 { # [doc = "Register `LINC1` reader"]
pub type R = crate :: R < LINC1_SPEC > ; # [doc = "Register `LINC1` writer"]
pub type W = crate :: W < LINC1_SPEC > ; # [doc = "Field `LINC1_DATA` reader - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture."]
pub type LINC1_DATA_R = crate :: FieldReader < u16 > ; # [doc = "Field `LINC1_DATA` writer - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture."]
pub type LINC1_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture."]
# [inline (always)]
pub fn linc1_data (& self) -> LINC1_DATA_R { LINC1_DATA_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - 16 Bit Capture / Compare Register Captures current LINCTR value on RXD rising edge when enabled. It can generate a LINC1 interrupt on capture."]
# [inline (always)]
# [must_use]
pub fn linc1_data (& mut self) -> LINC1_DATA_W < LINC1_SPEC , 0 > { LINC1_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART LIN Mode Capture 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`linc1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`linc1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LINC1_SPEC ; impl crate :: RegisterSpec for LINC1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`linc1::R`](R) reader structure"]
impl crate :: Readable for LINC1_SPEC { } # [doc = "`write(|w| ..)` method takes [`linc1::W`](W) writer structure"]
impl crate :: Writable for LINC1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LINC1 to value 0"]
impl crate :: Resettable for LINC1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IRCTL (rw) register accessor: eUSCI_Ax IrDA Control Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irctl`]
module"]
pub type IRCTL = crate :: Reg < irctl :: IRCTL_SPEC > ; # [doc = "eUSCI_Ax IrDA Control Word Register"]
pub mod irctl { # [doc = "Register `IRCTL` reader"]
pub type R = crate :: R < IRCTL_SPEC > ; # [doc = "Register `IRCTL` writer"]
pub type W = crate :: W < IRCTL_SPEC > ; # [doc = "Field `IRCTL_IREN` reader - IrDA encoder/decoder enable"]
pub type IRCTL_IREN_R = crate :: BitReader < IRCTL_IREN_A > ; # [doc = "IrDA encoder/decoder enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IRCTL_IREN_A { # [doc = "0: DISABLE"]
IRCTL_IREN_DISABLE = 0 , # [doc = "1: ENABLE"]
IRCTL_IREN_ENABLE = 1 , } impl From < IRCTL_IREN_A > for bool { # [inline (always)]
fn from (variant : IRCTL_IREN_A) -> Self { variant as u8 != 0 } } impl IRCTL_IREN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IRCTL_IREN_A { match self . bits { false => IRCTL_IREN_A :: IRCTL_IREN_DISABLE , true => IRCTL_IREN_A :: IRCTL_IREN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_irctl_iren_disable (& self) -> bool { * self == IRCTL_IREN_A :: IRCTL_IREN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_irctl_iren_enable (& self) -> bool { * self == IRCTL_IREN_A :: IRCTL_IREN_ENABLE } } # [doc = "Field `IRCTL_IREN` writer - IrDA encoder/decoder enable"]
pub type IRCTL_IREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IRCTL_IREN_A > ; impl < 'a , REG , const O : u8 > IRCTL_IREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn irctl_iren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (IRCTL_IREN_A :: IRCTL_IREN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn irctl_iren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (IRCTL_IREN_A :: IRCTL_IREN_ENABLE) } } # [doc = "Field `IRCTL_IRTXCLK` reader - IrDA transmit pulse clock select"]
pub type IRCTL_IRTXCLK_R = crate :: BitReader < IRCTL_IRTXCLK_A > ; # [doc = "IrDA transmit pulse clock select\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IRCTL_IRTXCLK_A { # [doc = "0: BITCLK"]
IRCTL_IRTXCLK_BITCLK = 0 , # [doc = "1: BRCLK"]
IRCTL_IRTXCLK_BRCLK = 1 , } impl From < IRCTL_IRTXCLK_A > for bool { # [inline (always)]
fn from (variant : IRCTL_IRTXCLK_A) -> Self { variant as u8 != 0 } } impl IRCTL_IRTXCLK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IRCTL_IRTXCLK_A { match self . bits { false => IRCTL_IRTXCLK_A :: IRCTL_IRTXCLK_BITCLK , true => IRCTL_IRTXCLK_A :: IRCTL_IRTXCLK_BRCLK , } } # [doc = "BITCLK"]
# [inline (always)]
pub fn is_irctl_irtxclk_bitclk (& self) -> bool { * self == IRCTL_IRTXCLK_A :: IRCTL_IRTXCLK_BITCLK } # [doc = "BRCLK"]
# [inline (always)]
pub fn is_irctl_irtxclk_brclk (& self) -> bool { * self == IRCTL_IRTXCLK_A :: IRCTL_IRTXCLK_BRCLK } } # [doc = "Field `IRCTL_IRTXCLK` writer - IrDA transmit pulse clock select"]
pub type IRCTL_IRTXCLK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IRCTL_IRTXCLK_A > ; impl < 'a , REG , const O : u8 > IRCTL_IRTXCLK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "BITCLK"]
# [inline (always)]
pub fn irctl_irtxclk_bitclk (self) -> & 'a mut crate :: W < REG > { self . variant (IRCTL_IRTXCLK_A :: IRCTL_IRTXCLK_BITCLK) } # [doc = "BRCLK"]
# [inline (always)]
pub fn irctl_irtxclk_brclk (self) -> & 'a mut crate :: W < REG > { self . variant (IRCTL_IRTXCLK_A :: IRCTL_IRTXCLK_BRCLK) } } # [doc = "Field `IRCTL_IRTXPL` reader - Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / \\[2 * f(IRTXCLK)\\]
(IRTXCLK = functional clock of the UART)"]
pub type IRCTL_IRTXPL_R = crate :: FieldReader ; # [doc = "Field `IRCTL_IRTXPL` writer - Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / \\[2 * f(IRTXCLK)\\]
(IRTXCLK = functional clock of the UART)"]
pub type IRCTL_IRTXPL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O > ; # [doc = "Field `IRCTL_IRRXPL` reader - IrDA receive input UCAxRXD polarity"]
pub type IRCTL_IRRXPL_R = crate :: BitReader < IRCTL_IRRXPL_A > ; # [doc = "IrDA receive input UCAxRXD polarity\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IRCTL_IRRXPL_A { # [doc = "0: HIGHPULSE"]
IRCTL_IRRXPL_HIGH = 0 , # [doc = "1: LOWPULSE"]
IRCTL_IRRXPL_LOW = 1 , } impl From < IRCTL_IRRXPL_A > for bool { # [inline (always)]
fn from (variant : IRCTL_IRRXPL_A) -> Self { variant as u8 != 0 } } impl IRCTL_IRRXPL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IRCTL_IRRXPL_A { match self . bits { false => IRCTL_IRRXPL_A :: IRCTL_IRRXPL_HIGH , true => IRCTL_IRRXPL_A :: IRCTL_IRRXPL_LOW , } } # [doc = "HIGHPULSE"]
# [inline (always)]
pub fn is_irctl_irrxpl_high (& self) -> bool { * self == IRCTL_IRRXPL_A :: IRCTL_IRRXPL_HIGH } # [doc = "LOWPULSE"]
# [inline (always)]
pub fn is_irctl_irrxpl_low (& self) -> bool { * self == IRCTL_IRRXPL_A :: IRCTL_IRRXPL_LOW } } # [doc = "Field `IRCTL_IRRXPL` writer - IrDA receive input UCAxRXD polarity"]
pub type IRCTL_IRRXPL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IRCTL_IRRXPL_A > ; impl < 'a , REG , const O : u8 > IRCTL_IRRXPL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HIGHPULSE"]
# [inline (always)]
pub fn irctl_irrxpl_high (self) -> & 'a mut crate :: W < REG > { self . variant (IRCTL_IRRXPL_A :: IRCTL_IRRXPL_HIGH) } # [doc = "LOWPULSE"]
# [inline (always)]
pub fn irctl_irrxpl_low (self) -> & 'a mut crate :: W < REG > { self . variant (IRCTL_IRRXPL_A :: IRCTL_IRRXPL_LOW) } } impl R { # [doc = "Bit 0 - IrDA encoder/decoder enable"]
# [inline (always)]
pub fn irctl_iren (& self) -> IRCTL_IREN_R { IRCTL_IREN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - IrDA transmit pulse clock select"]
# [inline (always)]
pub fn irctl_irtxclk (& self) -> IRCTL_IRTXCLK_R { IRCTL_IRTXCLK_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:7 - Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / \\[2 * f(IRTXCLK)\\]
(IRTXCLK = functional clock of the UART)"]
# [inline (always)]
pub fn irctl_irtxpl (& self) -> IRCTL_IRTXPL_R { IRCTL_IRTXPL_R :: new (((self . bits >> 2) & 0x3f) as u8) } # [doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
# [inline (always)]
pub fn irctl_irrxpl (& self) -> IRCTL_IRRXPL_R { IRCTL_IRRXPL_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bit 0 - IrDA encoder/decoder enable"]
# [inline (always)]
# [must_use]
pub fn irctl_iren (& mut self) -> IRCTL_IREN_W < IRCTL_SPEC , 0 > { IRCTL_IREN_W :: new (self) } # [doc = "Bit 1 - IrDA transmit pulse clock select"]
# [inline (always)]
# [must_use]
pub fn irctl_irtxclk (& mut self) -> IRCTL_IRTXCLK_W < IRCTL_SPEC , 1 > { IRCTL_IRTXCLK_W :: new (self) } # [doc = "Bits 2:7 - Transmit pulse length. Pulse length t(PULSE) = (IRTXPLx + 1) / \\[2 * f(IRTXCLK)\\]
(IRTXCLK = functional clock of the UART)"]
# [inline (always)]
# [must_use]
pub fn irctl_irtxpl (& mut self) -> IRCTL_IRTXPL_W < IRCTL_SPEC , 2 > { IRCTL_IRTXPL_W :: new (self) } # [doc = "Bit 9 - IrDA receive input UCAxRXD polarity"]
# [inline (always)]
# [must_use]
pub fn irctl_irrxpl (& mut self) -> IRCTL_IRRXPL_W < IRCTL_SPEC , 9 > { IRCTL_IRRXPL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "eUSCI_Ax IrDA Control Word Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IRCTL_SPEC ; impl crate :: RegisterSpec for IRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`irctl::R`](R) reader structure"]
impl crate :: Readable for IRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`irctl::W`](W) writer structure"]
impl crate :: Writable for IRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IRCTL to value 0"]
impl crate :: Resettable for IRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "AMASK (rw) register accessor: Self Address Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amask`]
module"]
pub type AMASK = crate :: Reg < amask :: AMASK_SPEC > ; # [doc = "Self Address Mask Register"]
pub mod amask { # [doc = "Register `AMASK` reader"]
pub type R = crate :: R < AMASK_SPEC > ; # [doc = "Register `AMASK` writer"]
pub type W = crate :: W < AMASK_SPEC > ; # [doc = "Field `AMASK_VALUE` reader - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
pub type AMASK_VALUE_R = crate :: FieldReader ; # [doc = "Field `AMASK_VALUE` writer - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
pub type AMASK_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
# [inline (always)]
pub fn amask_value (& self) -> AMASK_VALUE_R { AMASK_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
# [inline (always)]
# [must_use]
pub fn amask_value (& mut self) -> AMASK_VALUE_W < AMASK_SPEC , 0 > { AMASK_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Self Address Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AMASK_SPEC ; impl crate :: RegisterSpec for AMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`amask::R`](R) reader structure"]
impl crate :: Readable for AMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`amask::W`](W) writer structure"]
impl crate :: Writable for AMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets AMASK to value 0xff"]
impl crate :: Resettable for AMASK_SPEC { const RESET_VALUE : Self :: Ux = 0xff ; } } # [doc = "ADDR (rw) register accessor: Self Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
module"]
pub type ADDR = crate :: Reg < addr :: ADDR_SPEC > ; # [doc = "Self Address Register"]
pub mod addr { # [doc = "Register `ADDR` reader"]
pub type R = crate :: R < ADDR_SPEC > ; # [doc = "Register `ADDR` writer"]
pub type W = crate :: W < ADDR_SPEC > ; # [doc = "Field `ADDR_VALUE` reader - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
pub type ADDR_VALUE_R = crate :: FieldReader ; # [doc = "Field `ADDR_VALUE` writer - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
pub type ADDR_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
# [inline (always)]
pub fn addr_value (& self) -> ADDR_VALUE_R { ADDR_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
# [inline (always)]
# [must_use]
pub fn addr_value (& mut self) -> ADDR_VALUE_W < ADDR_SPEC , 0 > { ADDR_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Self Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ADDR_SPEC ; impl crate :: RegisterSpec for ADDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`addr::R`](R) reader structure"]
impl crate :: Readable for ADDR_SPEC { } # [doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"]
impl crate :: Writable for ADDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ADDR to value 0"]
impl crate :: Resettable for ADDR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV2 (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv2`]
module"]
pub type CLKDIV2 = crate :: Reg < clkdiv2 :: CLKDIV2_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv2 { # [doc = "Register `CLKDIV2` reader"]
pub type R = crate :: R < CLKDIV2_SPEC > ; # [doc = "Register `CLKDIV2` writer"]
pub type W = crate :: W < CLKDIV2_SPEC > ; # [doc = "Field `CLKDIV2_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV2_RATIO_R = crate :: FieldReader < CLKDIV2_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV2_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV2_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV2_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV2_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV2_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV2_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV2_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV2_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV2_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV2_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV2_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV2_RATIO_A { type Ux = u8 ; } impl CLKDIV2_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV2_RATIO_A { match self . bits { 0 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_1 , 1 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_2 , 2 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_3 , 3 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_4 , 4 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_5 , 5 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_6 , 6 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_7 , 7 => CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_1 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_2 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_3 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_4 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_5 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_6 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_7 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv2_ratio_div_by_8 (& self) -> bool { * self == CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV2_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV2_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV2_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV2_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv2_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV2_RATIO_A :: CLKDIV2_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv2_ratio (& self) -> CLKDIV2_RATIO_R { CLKDIV2_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv2_ratio (& mut self) -> CLKDIV2_RATIO_W < CLKDIV2_SPEC , 0 > { CLKDIV2_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV2_SPEC ; impl crate :: RegisterSpec for CLKDIV2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv2::R`](R) reader structure"]
impl crate :: Readable for CLKDIV2_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv2::W`](W) writer structure"]
impl crate :: Writable for CLKDIV2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV2 to value 0"]
impl crate :: Resettable for CLKDIV2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "F65NW"]
pub struct FLASHCTL { _marker : PhantomData < * const () > } unsafe impl Send for FLASHCTL { } impl FLASHCTL { # [doc = r"Pointer to the register block"]
pub const PTR : * const flashctl :: RegisterBlock = 0x400c_d000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const flashctl :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for FLASHCTL { type Target = flashctl :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for FLASHCTL { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("FLASHCTL") . finish () } } # [doc = "F65NW"]
pub mod flashctl { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x1020]
, # [doc = "0x1020 - Interrupt Index Register"]
pub iidx : IIDX , _reserved1 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt Mask Register"]
pub imask : IMASK , _reserved2 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw Interrupt Status Register"]
pub ris : RIS , _reserved3 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked Interrupt Status Register"]
pub mis : MIS , _reserved4 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt Set Register"]
pub iset : ISET , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt Clear Register"]
pub iclr : ICLR , _reserved6 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved7 : [u8 ; 0x18]
, # [doc = "0x10fc - Hardware Version Description Register"]
pub desc : DESC , # [doc = "0x1100 - Command Execute Register"]
pub cmdexec : CMDEXEC , # [doc = "0x1104 - Command Type Register"]
pub cmdtype : CMDTYPE , # [doc = "0x1108 - Command Control Register"]
pub cmdctl : CMDCTL , _reserved11 : [u8 ; 0x14]
, # [doc = "0x1120 - Command Address Register"]
pub cmdaddr : CMDADDR , # [doc = "0x1124 - Command Program Byte Enable Register"]
pub cmdbyten : CMDBYTEN , _reserved13 : [u8 ; 0x08]
, # [doc = "0x1130 - Command Data Register 0"]
pub cmddata0 : CMDDATA0 , # [doc = "0x1134 - Command Data Register 1"]
pub cmddata1 : CMDDATA1 , _reserved15 : [u8 ; 0x98]
, # [doc = "0x11d0 - Command Write Erase Protect A Register"]
pub cmdweprota : CMDWEPROTA , # [doc = "0x11d4 - Command Write Erase Protect B Register"]
pub cmdweprotb : CMDWEPROTB , _reserved17 : [u8 ; 0x38]
, # [doc = "0x1210 - Command Write Erase Protect Non-Main Register"]
pub cmdweprotnm : CMDWEPROTNM , # [doc = "0x1214 - Command Write Erase Protect Trim Register"]
pub cmdweprottr : CMDWEPROTTR , # [doc = "0x1218 - Command Write Erase Protect Engr Register"]
pub cmdweproten : CMDWEPROTEN , _reserved20 : [u8 ; 0x0194]
, # [doc = "0x13b0 - Command Configuration Register"]
pub cfgcmd : CFGCMD , # [doc = "0x13b4 - Pulse Counter Configuration Register"]
pub cfgpcnt : CFGPCNT , _reserved22 : [u8 ; 0x18]
, # [doc = "0x13d0 - Command Status Register"]
pub statcmd : STATCMD , # [doc = "0x13d4 - Address Status Register"]
pub stataddr : STATADDR , # [doc = "0x13d8 - Pulse Count Status Register"]
pub statpcnt : STATPCNT , # [doc = "0x13dc - Mode Status Register"]
pub statmode : STATMODE , _reserved26 : [u8 ; 0x10]
, # [doc = "0x13f0 - Global Information Register 0"]
pub gblinfo0 : GBLINFO0 , # [doc = "0x13f4 - Global Information Register 1"]
pub gblinfo1 : GBLINFO1 , # [doc = "0x13f8 - Global Information Register 2"]
pub gblinfo2 : GBLINFO2 , _reserved29 : [u8 ; 0x04]
, # [doc = "0x1400 - Bank Information Register 0 for Bank 0"]
pub bank0info0 : BANK0INFO0 , # [doc = "0x1404 - Bank Information Register 1 for Bank 0"]
pub bank0info1 : BANK0INFO1 , } # [doc = "IIDX (r) register accessor: Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt Index Register"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt."]
pub type IIDX_STAT_R = crate :: BitReader < IIDX_STAT_A > ; # [doc = "Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: DONE"]
IIDX_STAT_DONE = 1 , } impl From < IIDX_STAT_A > for bool { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as u8 != 0 } } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IIDX_STAT_A { match self . bits { false => IIDX_STAT_A :: IIDX_STAT_NO_INTR , true => IIDX_STAT_A :: IIDX_STAT_DONE , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "DONE"]
# [inline (always)]
pub fn is_iidx_stat_done (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DONE } } impl R { # [doc = "Bit 0 - Indicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt."]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 1) != 0) } } # [doc = "Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt Mask Register"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_DONE` reader - Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register"]
pub type IMASK_DONE_R = crate :: BitReader < IMASK_DONE_A > ; # [doc = "Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_DONE_A { # [doc = "0: DISABLED"]
IMASK_DONE_DISABLED = 0 , # [doc = "1: ENABLED"]
IMASK_DONE_ENABLED = 1 , } impl From < IMASK_DONE_A > for bool { # [inline (always)]
fn from (variant : IMASK_DONE_A) -> Self { variant as u8 != 0 } } impl IMASK_DONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_DONE_A { match self . bits { false => IMASK_DONE_A :: IMASK_DONE_DISABLED , true => IMASK_DONE_A :: IMASK_DONE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_imask_done_disabled (& self) -> bool { * self == IMASK_DONE_A :: IMASK_DONE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_imask_done_enabled (& self) -> bool { * self == IMASK_DONE_A :: IMASK_DONE_ENABLED } } # [doc = "Field `IMASK_DONE` writer - Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register"]
pub type IMASK_DONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_DONE_A > ; impl < 'a , REG , const O : u8 > IMASK_DONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn imask_done_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DONE_A :: IMASK_DONE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn imask_done_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DONE_A :: IMASK_DONE_ENABLED) } } impl R { # [doc = "Bit 0 - Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register"]
# [inline (always)]
pub fn imask_done (& self) -> IMASK_DONE_R { IMASK_DONE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register"]
# [inline (always)]
# [must_use]
pub fn imask_done (& mut self) -> IMASK_DONE_W < IMASK_SPEC , 0 > { IMASK_DONE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw Interrupt Status Register"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_DONE` reader - NoWrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority."]
pub type RIS_DONE_R = crate :: BitReader < RIS_DONE_A > ; # [doc = "NoWrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_DONE_A { # [doc = "0: CLR"]
RIS_DONE_CLR = 0 , # [doc = "1: SET"]
RIS_DONE_SET = 1 , } impl From < RIS_DONE_A > for bool { # [inline (always)]
fn from (variant : RIS_DONE_A) -> Self { variant as u8 != 0 } } impl RIS_DONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_DONE_A { match self . bits { false => RIS_DONE_A :: RIS_DONE_CLR , true => RIS_DONE_A :: RIS_DONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_done_clr (& self) -> bool { * self == RIS_DONE_A :: RIS_DONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_done_set (& self) -> bool { * self == RIS_DONE_A :: RIS_DONE_SET } } impl R { # [doc = "Bit 0 - NoWrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority."]
# [inline (always)]
pub fn ris_done (& self) -> RIS_DONE_R { RIS_DONE_R :: new ((self . bits & 1) != 0) } } # [doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked Interrupt Status Register"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_DONE` reader - NoWrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits."]
pub type MIS_DONE_R = crate :: BitReader < MIS_DONE_A > ; # [doc = "NoWrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_DONE_A { # [doc = "0: CLR"]
MIS_DONE_CLR = 0 , # [doc = "1: SET"]
MIS_DONE_SET = 1 , } impl From < MIS_DONE_A > for bool { # [inline (always)]
fn from (variant : MIS_DONE_A) -> Self { variant as u8 != 0 } } impl MIS_DONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_DONE_A { match self . bits { false => MIS_DONE_A :: MIS_DONE_CLR , true => MIS_DONE_A :: MIS_DONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_done_clr (& self) -> bool { * self == MIS_DONE_A :: MIS_DONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_done_set (& self) -> bool { * self == MIS_DONE_A :: MIS_DONE_SET } } impl R { # [doc = "Bit 0 - NoWrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits."]
# [inline (always)]
pub fn mis_done (& self) -> MIS_DONE_R { MIS_DONE_R :: new ((self . bits & 1) != 0) } } # [doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt Set Register"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "0: No effect 1: Set the DONE interrupt in the RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_DONE_AW { # [doc = "0: NO_EFFECT"]
ISET_DONE_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_DONE_SET = 1 , } impl From < ISET_DONE_AW > for bool { # [inline (always)]
fn from (variant : ISET_DONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_DONE` writer - 0: No effect 1: Set the DONE interrupt in the RIS register"]
pub type ISET_DONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_DONE_AW > ; impl < 'a , REG , const O : u8 > ISET_DONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_done_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DONE_AW :: ISET_DONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_done_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DONE_AW :: ISET_DONE_SET) } } impl W { # [doc = "Bit 0 - 0: No effect 1: Set the DONE interrupt in the RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_done (& mut self) -> ISET_DONE_W < ISET_SPEC , 0 > { ISET_DONE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Set Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt Clear Register"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "0: No effect 1: Clear the DONE interrupt in the RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_DONE_AW { # [doc = "0: NO_EFFECT"]
ICLR_DONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_DONE_CLR = 1 , } impl From < ICLR_DONE_AW > for bool { # [inline (always)]
fn from (variant : ICLR_DONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_DONE` writer - 0: No effect 1: Clear the DONE interrupt in the RIS register"]
pub type ICLR_DONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_DONE_AW > ; impl < 'a , REG , const O : u8 > ICLR_DONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_done_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DONE_AW :: ICLR_DONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_done_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DONE_AW :: ICLR_DONE_CLR) } } impl W { # [doc = "Bit 0 - 0: No effect 1: Clear the DONE interrupt in the RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_done (& mut self) -> ICLR_DONE_W < ICLR_SPEC , 0 > { ICLR_DONE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (r) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for peripheral event"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for peripheral event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for peripheral event"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Hardware Version Description Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Hardware Version Description Register"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor Revision"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major Revision"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance number"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature set"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module ID"]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor Revision"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major Revision"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance number"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature set"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module ID"]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Hardware Version Description Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDEXEC (rw) register accessor: Command Execute Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdexec::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdexec::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdexec`]
module"]
pub type CMDEXEC = crate :: Reg < cmdexec :: CMDEXEC_SPEC > ; # [doc = "Command Execute Register"]
pub mod cmdexec { # [doc = "Register `CMDEXEC` reader"]
pub type R = crate :: R < CMDEXEC_SPEC > ; # [doc = "Register `CMDEXEC` writer"]
pub type W = crate :: W < CMDEXEC_SPEC > ; # [doc = "Field `CMDEXEC_VAL` reader - Command Execute value Initiates execution of the command specified in the CMDTYPE register."]
pub type CMDEXEC_VAL_R = crate :: BitReader < CMDEXEC_VAL_A > ; # [doc = "Command Execute value Initiates execution of the command specified in the CMDTYPE register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CMDEXEC_VAL_A { # [doc = "0: NOEXECUTE"]
CMDEXEC_VAL_NOEXECUTE = 0 , # [doc = "1: EXECUTE"]
CMDEXEC_VAL_EXECUTE = 1 , } impl From < CMDEXEC_VAL_A > for bool { # [inline (always)]
fn from (variant : CMDEXEC_VAL_A) -> Self { variant as u8 != 0 } } impl CMDEXEC_VAL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CMDEXEC_VAL_A { match self . bits { false => CMDEXEC_VAL_A :: CMDEXEC_VAL_NOEXECUTE , true => CMDEXEC_VAL_A :: CMDEXEC_VAL_EXECUTE , } } # [doc = "NOEXECUTE"]
# [inline (always)]
pub fn is_cmdexec_val_noexecute (& self) -> bool { * self == CMDEXEC_VAL_A :: CMDEXEC_VAL_NOEXECUTE } # [doc = "EXECUTE"]
# [inline (always)]
pub fn is_cmdexec_val_execute (& self) -> bool { * self == CMDEXEC_VAL_A :: CMDEXEC_VAL_EXECUTE } } # [doc = "Field `CMDEXEC_VAL` writer - Command Execute value Initiates execution of the command specified in the CMDTYPE register."]
pub type CMDEXEC_VAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CMDEXEC_VAL_A > ; impl < 'a , REG , const O : u8 > CMDEXEC_VAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOEXECUTE"]
# [inline (always)]
pub fn cmdexec_val_noexecute (self) -> & 'a mut crate :: W < REG > { self . variant (CMDEXEC_VAL_A :: CMDEXEC_VAL_NOEXECUTE) } # [doc = "EXECUTE"]
# [inline (always)]
pub fn cmdexec_val_execute (self) -> & 'a mut crate :: W < REG > { self . variant (CMDEXEC_VAL_A :: CMDEXEC_VAL_EXECUTE) } } impl R { # [doc = "Bit 0 - Command Execute value Initiates execution of the command specified in the CMDTYPE register."]
# [inline (always)]
pub fn cmdexec_val (& self) -> CMDEXEC_VAL_R { CMDEXEC_VAL_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Command Execute value Initiates execution of the command specified in the CMDTYPE register."]
# [inline (always)]
# [must_use]
pub fn cmdexec_val (& mut self) -> CMDEXEC_VAL_W < CMDEXEC_SPEC , 0 > { CMDEXEC_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Execute Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdexec::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdexec::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDEXEC_SPEC ; impl crate :: RegisterSpec for CMDEXEC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdexec::R`](R) reader structure"]
impl crate :: Readable for CMDEXEC_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdexec::W`](W) writer structure"]
impl crate :: Writable for CMDEXEC_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDEXEC to value 0"]
impl crate :: Resettable for CMDEXEC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDTYPE (rw) register accessor: Command Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtype::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtype::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdtype`]
module"]
pub type CMDTYPE = crate :: Reg < cmdtype :: CMDTYPE_SPEC > ; # [doc = "Command Type Register"]
pub mod cmdtype { # [doc = "Register `CMDTYPE` reader"]
pub type R = crate :: R < CMDTYPE_SPEC > ; # [doc = "Register `CMDTYPE` writer"]
pub type W = crate :: W < CMDTYPE_SPEC > ; # [doc = "Field `CMDTYPE_COMMAND` reader - Command type"]
pub type CMDTYPE_COMMAND_R = crate :: FieldReader < CMDTYPE_COMMAND_A > ; # [doc = "Command type\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CMDTYPE_COMMAND_A { # [doc = "0: NOOP"]
CMDTYPE_COMMAND_NOOP = 0 , # [doc = "1: PROGRAM"]
CMDTYPE_COMMAND_PROGRAM = 1 , # [doc = "2: ERASE"]
CMDTYPE_COMMAND_ERASE = 2 , # [doc = "3: READVERIFY"]
CMDTYPE_COMMAND_READVERIFY = 3 , # [doc = "4: MODECHANGE"]
CMDTYPE_COMMAND_MODECHANGE = 4 , # [doc = "5: CLEARSTATUS"]
CMDTYPE_COMMAND_CLEARSTATUS = 5 , # [doc = "6: BLANKVERIFY"]
CMDTYPE_COMMAND_BLANKVERIFY = 6 , } impl From < CMDTYPE_COMMAND_A > for u8 { # [inline (always)]
fn from (variant : CMDTYPE_COMMAND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CMDTYPE_COMMAND_A { type Ux = u8 ; } impl CMDTYPE_COMMAND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CMDTYPE_COMMAND_A > { match self . bits { 0 => Some (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_NOOP) , 1 => Some (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_PROGRAM) , 2 => Some (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_ERASE) , 3 => Some (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_READVERIFY) , 4 => Some (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_MODECHANGE) , 5 => Some (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_CLEARSTATUS) , 6 => Some (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_BLANKVERIFY) , _ => None , } } # [doc = "NOOP"]
# [inline (always)]
pub fn is_cmdtype_command_noop (& self) -> bool { * self == CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_NOOP } # [doc = "PROGRAM"]
# [inline (always)]
pub fn is_cmdtype_command_program (& self) -> bool { * self == CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_PROGRAM } # [doc = "ERASE"]
# [inline (always)]
pub fn is_cmdtype_command_erase (& self) -> bool { * self == CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_ERASE } # [doc = "READVERIFY"]
# [inline (always)]
pub fn is_cmdtype_command_readverify (& self) -> bool { * self == CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_READVERIFY } # [doc = "MODECHANGE"]
# [inline (always)]
pub fn is_cmdtype_command_modechange (& self) -> bool { * self == CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_MODECHANGE } # [doc = "CLEARSTATUS"]
# [inline (always)]
pub fn is_cmdtype_command_clearstatus (& self) -> bool { * self == CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_CLEARSTATUS } # [doc = "BLANKVERIFY"]
# [inline (always)]
pub fn is_cmdtype_command_blankverify (& self) -> bool { * self == CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_BLANKVERIFY } } # [doc = "Field `CMDTYPE_COMMAND` writer - Command type"]
pub type CMDTYPE_COMMAND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CMDTYPE_COMMAND_A > ; impl < 'a , REG , const O : u8 > CMDTYPE_COMMAND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOOP"]
# [inline (always)]
pub fn cmdtype_command_noop (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_NOOP) } # [doc = "PROGRAM"]
# [inline (always)]
pub fn cmdtype_command_program (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_PROGRAM) } # [doc = "ERASE"]
# [inline (always)]
pub fn cmdtype_command_erase (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_ERASE) } # [doc = "READVERIFY"]
# [inline (always)]
pub fn cmdtype_command_readverify (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_READVERIFY) } # [doc = "MODECHANGE"]
# [inline (always)]
pub fn cmdtype_command_modechange (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_MODECHANGE) } # [doc = "CLEARSTATUS"]
# [inline (always)]
pub fn cmdtype_command_clearstatus (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_CLEARSTATUS) } # [doc = "BLANKVERIFY"]
# [inline (always)]
pub fn cmdtype_command_blankverify (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_COMMAND_A :: CMDTYPE_COMMAND_BLANKVERIFY) } } # [doc = "Field `CMDTYPE_SIZE` reader - Command size"]
pub type CMDTYPE_SIZE_R = crate :: FieldReader < CMDTYPE_SIZE_A > ; # [doc = "Command size\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CMDTYPE_SIZE_A { # [doc = "0: ONEWORD"]
CMDTYPE_SIZE_ONEWORD = 0 , # [doc = "1: TWOWORD"]
CMDTYPE_SIZE_TWOWORD = 1 , # [doc = "2: FOURWORD"]
CMDTYPE_SIZE_FOURWORD = 2 , # [doc = "3: EIGHTWORD"]
CMDTYPE_SIZE_EIGHTWORD = 3 , # [doc = "4: SECTOR"]
CMDTYPE_SIZE_SECTOR = 4 , # [doc = "5: BANK"]
CMDTYPE_SIZE_BANK = 5 , } impl From < CMDTYPE_SIZE_A > for u8 { # [inline (always)]
fn from (variant : CMDTYPE_SIZE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CMDTYPE_SIZE_A { type Ux = u8 ; } impl CMDTYPE_SIZE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CMDTYPE_SIZE_A > { match self . bits { 0 => Some (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_ONEWORD) , 1 => Some (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_TWOWORD) , 2 => Some (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_FOURWORD) , 3 => Some (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_EIGHTWORD) , 4 => Some (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_SECTOR) , 5 => Some (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_BANK) , _ => None , } } # [doc = "ONEWORD"]
# [inline (always)]
pub fn is_cmdtype_size_oneword (& self) -> bool { * self == CMDTYPE_SIZE_A :: CMDTYPE_SIZE_ONEWORD } # [doc = "TWOWORD"]
# [inline (always)]
pub fn is_cmdtype_size_twoword (& self) -> bool { * self == CMDTYPE_SIZE_A :: CMDTYPE_SIZE_TWOWORD } # [doc = "FOURWORD"]
# [inline (always)]
pub fn is_cmdtype_size_fourword (& self) -> bool { * self == CMDTYPE_SIZE_A :: CMDTYPE_SIZE_FOURWORD } # [doc = "EIGHTWORD"]
# [inline (always)]
pub fn is_cmdtype_size_eightword (& self) -> bool { * self == CMDTYPE_SIZE_A :: CMDTYPE_SIZE_EIGHTWORD } # [doc = "SECTOR"]
# [inline (always)]
pub fn is_cmdtype_size_sector (& self) -> bool { * self == CMDTYPE_SIZE_A :: CMDTYPE_SIZE_SECTOR } # [doc = "BANK"]
# [inline (always)]
pub fn is_cmdtype_size_bank (& self) -> bool { * self == CMDTYPE_SIZE_A :: CMDTYPE_SIZE_BANK } } # [doc = "Field `CMDTYPE_SIZE` writer - Command size"]
pub type CMDTYPE_SIZE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CMDTYPE_SIZE_A > ; impl < 'a , REG , const O : u8 > CMDTYPE_SIZE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ONEWORD"]
# [inline (always)]
pub fn cmdtype_size_oneword (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_ONEWORD) } # [doc = "TWOWORD"]
# [inline (always)]
pub fn cmdtype_size_twoword (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_TWOWORD) } # [doc = "FOURWORD"]
# [inline (always)]
pub fn cmdtype_size_fourword (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_FOURWORD) } # [doc = "EIGHTWORD"]
# [inline (always)]
pub fn cmdtype_size_eightword (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_EIGHTWORD) } # [doc = "SECTOR"]
# [inline (always)]
pub fn cmdtype_size_sector (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_SECTOR) } # [doc = "BANK"]
# [inline (always)]
pub fn cmdtype_size_bank (self) -> & 'a mut crate :: W < REG > { self . variant (CMDTYPE_SIZE_A :: CMDTYPE_SIZE_BANK) } } impl R { # [doc = "Bits 0:2 - Command type"]
# [inline (always)]
pub fn cmdtype_command (& self) -> CMDTYPE_COMMAND_R { CMDTYPE_COMMAND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Command size"]
# [inline (always)]
pub fn cmdtype_size (& self) -> CMDTYPE_SIZE_R { CMDTYPE_SIZE_R :: new (((self . bits >> 4) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Command type"]
# [inline (always)]
# [must_use]
pub fn cmdtype_command (& mut self) -> CMDTYPE_COMMAND_W < CMDTYPE_SPEC , 0 > { CMDTYPE_COMMAND_W :: new (self) } # [doc = "Bits 4:6 - Command size"]
# [inline (always)]
# [must_use]
pub fn cmdtype_size (& mut self) -> CMDTYPE_SIZE_W < CMDTYPE_SPEC , 4 > { CMDTYPE_SIZE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Type Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdtype::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdtype::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDTYPE_SPEC ; impl crate :: RegisterSpec for CMDTYPE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdtype::R`](R) reader structure"]
impl crate :: Readable for CMDTYPE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdtype::W`](W) writer structure"]
impl crate :: Writable for CMDTYPE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDTYPE to value 0"]
impl crate :: Resettable for CMDTYPE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDCTL (rw) register accessor: Command Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdctl`]
module"]
pub type CMDCTL = crate :: Reg < cmdctl :: CMDCTL_SPEC > ; # [doc = "Command Control Register"]
pub mod cmdctl { # [doc = "Register `CMDCTL` reader"]
pub type R = crate :: R < CMDCTL_SPEC > ; # [doc = "Register `CMDCTL` writer"]
pub type W = crate :: W < CMDCTL_SPEC > ; # [doc = "Field `CMDCTL_MODESEL` reader - Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware."]
pub type CMDCTL_MODESEL_R = crate :: FieldReader < CMDCTL_MODESEL_A > ; # [doc = "Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CMDCTL_MODESEL_A { # [doc = "0: READ"]
CMDCTL_MODESEL_READ = 0 , # [doc = "2: RDMARG0"]
CMDCTL_MODESEL_RDMARG0 = 2 , # [doc = "4: RDMARG1"]
CMDCTL_MODESEL_RDMARG1 = 4 , # [doc = "6: RDMARG0B"]
CMDCTL_MODESEL_RDMARG0B = 6 , # [doc = "7: RDMARG1B"]
CMDCTL_MODESEL_RDMARG1B = 7 , # [doc = "9: PGMVER"]
CMDCTL_MODESEL_PGMVER = 9 , # [doc = "10: PGMSW"]
CMDCTL_MODESEL_PGMSW = 10 , # [doc = "11: ERASEVER"]
CMDCTL_MODESEL_ERASEVER = 11 , # [doc = "12: ERASESECT"]
CMDCTL_MODESEL_ERASESECT = 12 , # [doc = "14: PGMMW"]
CMDCTL_MODESEL_PGMMW = 14 , # [doc = "15: ERASEBNK"]
CMDCTL_MODESEL_ERASEBNK = 15 , } impl From < CMDCTL_MODESEL_A > for u8 { # [inline (always)]
fn from (variant : CMDCTL_MODESEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CMDCTL_MODESEL_A { type Ux = u8 ; } impl CMDCTL_MODESEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CMDCTL_MODESEL_A > { match self . bits { 0 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_READ) , 2 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG0) , 4 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG1) , 6 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG0B) , 7 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG1B) , 9 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMVER) , 10 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMSW) , 11 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASEVER) , 12 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASESECT) , 14 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMMW) , 15 => Some (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASEBNK) , _ => None , } } # [doc = "READ"]
# [inline (always)]
pub fn is_cmdctl_modesel_read (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_READ } # [doc = "RDMARG0"]
# [inline (always)]
pub fn is_cmdctl_modesel_rdmarg0 (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG0 } # [doc = "RDMARG1"]
# [inline (always)]
pub fn is_cmdctl_modesel_rdmarg1 (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG1 } # [doc = "RDMARG0B"]
# [inline (always)]
pub fn is_cmdctl_modesel_rdmarg0b (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG0B } # [doc = "RDMARG1B"]
# [inline (always)]
pub fn is_cmdctl_modesel_rdmarg1b (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG1B } # [doc = "PGMVER"]
# [inline (always)]
pub fn is_cmdctl_modesel_pgmver (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMVER } # [doc = "PGMSW"]
# [inline (always)]
pub fn is_cmdctl_modesel_pgmsw (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMSW } # [doc = "ERASEVER"]
# [inline (always)]
pub fn is_cmdctl_modesel_erasever (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASEVER } # [doc = "ERASESECT"]
# [inline (always)]
pub fn is_cmdctl_modesel_erasesect (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASESECT } # [doc = "PGMMW"]
# [inline (always)]
pub fn is_cmdctl_modesel_pgmmw (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMMW } # [doc = "ERASEBNK"]
# [inline (always)]
pub fn is_cmdctl_modesel_erasebnk (& self) -> bool { * self == CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASEBNK } } # [doc = "Field `CMDCTL_MODESEL` writer - Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware."]
pub type CMDCTL_MODESEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CMDCTL_MODESEL_A > ; impl < 'a , REG , const O : u8 > CMDCTL_MODESEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "READ"]
# [inline (always)]
pub fn cmdctl_modesel_read (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_READ) } # [doc = "RDMARG0"]
# [inline (always)]
pub fn cmdctl_modesel_rdmarg0 (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG0) } # [doc = "RDMARG1"]
# [inline (always)]
pub fn cmdctl_modesel_rdmarg1 (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG1) } # [doc = "RDMARG0B"]
# [inline (always)]
pub fn cmdctl_modesel_rdmarg0b (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG0B) } # [doc = "RDMARG1B"]
# [inline (always)]
pub fn cmdctl_modesel_rdmarg1b (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_RDMARG1B) } # [doc = "PGMVER"]
# [inline (always)]
pub fn cmdctl_modesel_pgmver (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMVER) } # [doc = "PGMSW"]
# [inline (always)]
pub fn cmdctl_modesel_pgmsw (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMSW) } # [doc = "ERASEVER"]
# [inline (always)]
pub fn cmdctl_modesel_erasever (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASEVER) } # [doc = "ERASESECT"]
# [inline (always)]
pub fn cmdctl_modesel_erasesect (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASESECT) } # [doc = "PGMMW"]
# [inline (always)]
pub fn cmdctl_modesel_pgmmw (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_PGMMW) } # [doc = "ERASEBNK"]
# [inline (always)]
pub fn cmdctl_modesel_erasebnk (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_MODESEL_A :: CMDCTL_MODESEL_ERASEBNK) } } # [doc = "Field `CMDCTL_REGIONSEL` reader - Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set."]
pub type CMDCTL_REGIONSEL_R = crate :: FieldReader < CMDCTL_REGIONSEL_A > ; # [doc = "Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CMDCTL_REGIONSEL_A { # [doc = "1: MAIN"]
CMDCTL_REGIONSEL_MAIN = 1 , # [doc = "2: NONMAIN"]
CMDCTL_REGIONSEL_NONMAIN = 2 , # [doc = "4: TRIM"]
CMDCTL_REGIONSEL_TRIM = 4 , # [doc = "8: ENGR"]
CMDCTL_REGIONSEL_ENGR = 8 , } impl From < CMDCTL_REGIONSEL_A > for u8 { # [inline (always)]
fn from (variant : CMDCTL_REGIONSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CMDCTL_REGIONSEL_A { type Ux = u8 ; } impl CMDCTL_REGIONSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CMDCTL_REGIONSEL_A > { match self . bits { 1 => Some (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_MAIN) , 2 => Some (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_NONMAIN) , 4 => Some (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_TRIM) , 8 => Some (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_ENGR) , _ => None , } } # [doc = "MAIN"]
# [inline (always)]
pub fn is_cmdctl_regionsel_main (& self) -> bool { * self == CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_MAIN } # [doc = "NONMAIN"]
# [inline (always)]
pub fn is_cmdctl_regionsel_nonmain (& self) -> bool { * self == CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_NONMAIN } # [doc = "TRIM"]
# [inline (always)]
pub fn is_cmdctl_regionsel_trim (& self) -> bool { * self == CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_TRIM } # [doc = "ENGR"]
# [inline (always)]
pub fn is_cmdctl_regionsel_engr (& self) -> bool { * self == CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_ENGR } } # [doc = "Field `CMDCTL_REGIONSEL` writer - Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set."]
pub type CMDCTL_REGIONSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CMDCTL_REGIONSEL_A > ; impl < 'a , REG , const O : u8 > CMDCTL_REGIONSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "MAIN"]
# [inline (always)]
pub fn cmdctl_regionsel_main (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_MAIN) } # [doc = "NONMAIN"]
# [inline (always)]
pub fn cmdctl_regionsel_nonmain (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_NONMAIN) } # [doc = "TRIM"]
# [inline (always)]
pub fn cmdctl_regionsel_trim (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_TRIM) } # [doc = "ENGR"]
# [inline (always)]
pub fn cmdctl_regionsel_engr (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_REGIONSEL_A :: CMDCTL_REGIONSEL_ENGR) } } # [doc = "Field `CMDCTL_ADDRXLATEOVR` reader - Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID."]
pub type CMDCTL_ADDRXLATEOVR_R = crate :: BitReader < CMDCTL_ADDRXLATEOVR_A > ; # [doc = "Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CMDCTL_ADDRXLATEOVR_A { # [doc = "0: NOOVERRIDE"]
CMDCTL_ADDRXLATEOVR_NOOVERRIDE = 0 , # [doc = "1: OVERRIDE"]
CMDCTL_ADDRXLATEOVR_OVERRIDE = 1 , } impl From < CMDCTL_ADDRXLATEOVR_A > for bool { # [inline (always)]
fn from (variant : CMDCTL_ADDRXLATEOVR_A) -> Self { variant as u8 != 0 } } impl CMDCTL_ADDRXLATEOVR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CMDCTL_ADDRXLATEOVR_A { match self . bits { false => CMDCTL_ADDRXLATEOVR_A :: CMDCTL_ADDRXLATEOVR_NOOVERRIDE , true => CMDCTL_ADDRXLATEOVR_A :: CMDCTL_ADDRXLATEOVR_OVERRIDE , } } # [doc = "NOOVERRIDE"]
# [inline (always)]
pub fn is_cmdctl_addrxlateovr_nooverride (& self) -> bool { * self == CMDCTL_ADDRXLATEOVR_A :: CMDCTL_ADDRXLATEOVR_NOOVERRIDE } # [doc = "OVERRIDE"]
# [inline (always)]
pub fn is_cmdctl_addrxlateovr_override (& self) -> bool { * self == CMDCTL_ADDRXLATEOVR_A :: CMDCTL_ADDRXLATEOVR_OVERRIDE } } # [doc = "Field `CMDCTL_ADDRXLATEOVR` writer - Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID."]
pub type CMDCTL_ADDRXLATEOVR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CMDCTL_ADDRXLATEOVR_A > ; impl < 'a , REG , const O : u8 > CMDCTL_ADDRXLATEOVR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOOVERRIDE"]
# [inline (always)]
pub fn cmdctl_addrxlateovr_nooverride (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_ADDRXLATEOVR_A :: CMDCTL_ADDRXLATEOVR_NOOVERRIDE) } # [doc = "OVERRIDE"]
# [inline (always)]
pub fn cmdctl_addrxlateovr_override (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_ADDRXLATEOVR_A :: CMDCTL_ADDRXLATEOVR_OVERRIDE) } } # [doc = "Field `CMDCTL_SSERASEDIS` reader - Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired."]
pub type CMDCTL_SSERASEDIS_R = crate :: BitReader < CMDCTL_SSERASEDIS_A > ; # [doc = "Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CMDCTL_SSERASEDIS_A { # [doc = "0: ENABLE"]
CMDCTL_SSERASEDIS_ENABLE = 0 , # [doc = "1: DISABLE"]
CMDCTL_SSERASEDIS_DISABLE = 1 , } impl From < CMDCTL_SSERASEDIS_A > for bool { # [inline (always)]
fn from (variant : CMDCTL_SSERASEDIS_A) -> Self { variant as u8 != 0 } } impl CMDCTL_SSERASEDIS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CMDCTL_SSERASEDIS_A { match self . bits { false => CMDCTL_SSERASEDIS_A :: CMDCTL_SSERASEDIS_ENABLE , true => CMDCTL_SSERASEDIS_A :: CMDCTL_SSERASEDIS_DISABLE , } } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cmdctl_sserasedis_enable (& self) -> bool { * self == CMDCTL_SSERASEDIS_A :: CMDCTL_SSERASEDIS_ENABLE } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_cmdctl_sserasedis_disable (& self) -> bool { * self == CMDCTL_SSERASEDIS_A :: CMDCTL_SSERASEDIS_DISABLE } } # [doc = "Field `CMDCTL_SSERASEDIS` writer - Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired."]
pub type CMDCTL_SSERASEDIS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CMDCTL_SSERASEDIS_A > ; impl < 'a , REG , const O : u8 > CMDCTL_SSERASEDIS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ENABLE"]
# [inline (always)]
pub fn cmdctl_sserasedis_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_SSERASEDIS_A :: CMDCTL_SSERASEDIS_ENABLE) } # [doc = "DISABLE"]
# [inline (always)]
pub fn cmdctl_sserasedis_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_SSERASEDIS_A :: CMDCTL_SSERASEDIS_DISABLE) } } # [doc = "Field `CMDCTL_DATAVEREN` reader - Enable invalid data verify. This checks for 0-&amp;gt;1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming."]
pub type CMDCTL_DATAVEREN_R = crate :: BitReader < CMDCTL_DATAVEREN_A > ; # [doc = "Enable invalid data verify. This checks for 0-&amp;gt;1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CMDCTL_DATAVEREN_A { # [doc = "0: DISABLE"]
CMDCTL_DATAVEREN_DISABLE = 0 , # [doc = "1: ENABLE"]
CMDCTL_DATAVEREN_ENABLE = 1 , } impl From < CMDCTL_DATAVEREN_A > for bool { # [inline (always)]
fn from (variant : CMDCTL_DATAVEREN_A) -> Self { variant as u8 != 0 } } impl CMDCTL_DATAVEREN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CMDCTL_DATAVEREN_A { match self . bits { false => CMDCTL_DATAVEREN_A :: CMDCTL_DATAVEREN_DISABLE , true => CMDCTL_DATAVEREN_A :: CMDCTL_DATAVEREN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_cmdctl_dataveren_disable (& self) -> bool { * self == CMDCTL_DATAVEREN_A :: CMDCTL_DATAVEREN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cmdctl_dataveren_enable (& self) -> bool { * self == CMDCTL_DATAVEREN_A :: CMDCTL_DATAVEREN_ENABLE } } # [doc = "Field `CMDCTL_DATAVEREN` writer - Enable invalid data verify. This checks for 0-&amp;gt;1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming."]
pub type CMDCTL_DATAVEREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CMDCTL_DATAVEREN_A > ; impl < 'a , REG , const O : u8 > CMDCTL_DATAVEREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn cmdctl_dataveren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_DATAVEREN_A :: CMDCTL_DATAVEREN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cmdctl_dataveren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CMDCTL_DATAVEREN_A :: CMDCTL_DATAVEREN_ENABLE) } } impl R { # [doc = "Bits 0:3 - Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware."]
# [inline (always)]
pub fn cmdctl_modesel (& self) -> CMDCTL_MODESEL_R { CMDCTL_MODESEL_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 9:12 - Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set."]
# [inline (always)]
pub fn cmdctl_regionsel (& self) -> CMDCTL_REGIONSEL_R { CMDCTL_REGIONSEL_R :: new (((self . bits >> 9) & 0x0f) as u8) } # [doc = "Bit 16 - Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID."]
# [inline (always)]
pub fn cmdctl_addrxlateovr (& self) -> CMDCTL_ADDRXLATEOVR_R { CMDCTL_ADDRXLATEOVR_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 20 - Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired."]
# [inline (always)]
pub fn cmdctl_sserasedis (& self) -> CMDCTL_SSERASEDIS_R { CMDCTL_SSERASEDIS_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Enable invalid data verify. This checks for 0-&amp;gt;1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming."]
# [inline (always)]
pub fn cmdctl_dataveren (& self) -> CMDCTL_DATAVEREN_R { CMDCTL_DATAVEREN_R :: new (((self . bits >> 21) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware."]
# [inline (always)]
# [must_use]
pub fn cmdctl_modesel (& mut self) -> CMDCTL_MODESEL_W < CMDCTL_SPEC , 0 > { CMDCTL_MODESEL_W :: new (self) } # [doc = "Bits 9:12 - Bank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set."]
# [inline (always)]
# [must_use]
pub fn cmdctl_regionsel (& mut self) -> CMDCTL_REGIONSEL_W < CMDCTL_SPEC , 9 > { CMDCTL_REGIONSEL_W :: new (self) } # [doc = "Bit 16 - Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID."]
# [inline (always)]
# [must_use]
pub fn cmdctl_addrxlateovr (& mut self) -> CMDCTL_ADDRXLATEOVR_W < CMDCTL_SPEC , 16 > { CMDCTL_ADDRXLATEOVR_W :: new (self) } # [doc = "Bit 20 - Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired."]
# [inline (always)]
# [must_use]
pub fn cmdctl_sserasedis (& mut self) -> CMDCTL_SSERASEDIS_W < CMDCTL_SPEC , 20 > { CMDCTL_SSERASEDIS_W :: new (self) } # [doc = "Bit 21 - Enable invalid data verify. This checks for 0-&amp;gt;1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming."]
# [inline (always)]
# [must_use]
pub fn cmdctl_dataveren (& mut self) -> CMDCTL_DATAVEREN_W < CMDCTL_SPEC , 21 > { CMDCTL_DATAVEREN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDCTL_SPEC ; impl crate :: RegisterSpec for CMDCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdctl::R`](R) reader structure"]
impl crate :: Readable for CMDCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdctl::W`](W) writer structure"]
impl crate :: Writable for CMDCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDCTL to value 0"]
impl crate :: Resettable for CMDCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDADDR (rw) register accessor: Command Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdaddr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdaddr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdaddr`]
module"]
pub type CMDADDR = crate :: Reg < cmdaddr :: CMDADDR_SPEC > ; # [doc = "Command Address Register"]
pub mod cmdaddr { # [doc = "Register `CMDADDR` reader"]
pub type R = crate :: R < CMDADDR_SPEC > ; # [doc = "Register `CMDADDR` writer"]
pub type W = crate :: W < CMDADDR_SPEC > ; # [doc = "Field `CMDADDR_VAL` reader - Address value"]
pub type CMDADDR_VAL_R = crate :: FieldReader < u32 > ; # [doc = "Field `CMDADDR_VAL` writer - Address value"]
pub type CMDADDR_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - Address value"]
# [inline (always)]
pub fn cmdaddr_val (& self) -> CMDADDR_VAL_R { CMDADDR_VAL_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Address value"]
# [inline (always)]
# [must_use]
pub fn cmdaddr_val (& mut self) -> CMDADDR_VAL_W < CMDADDR_SPEC , 0 > { CMDADDR_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdaddr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdaddr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDADDR_SPEC ; impl crate :: RegisterSpec for CMDADDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdaddr::R`](R) reader structure"]
impl crate :: Readable for CMDADDR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdaddr::W`](W) writer structure"]
impl crate :: Writable for CMDADDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDADDR to value 0"]
impl crate :: Resettable for CMDADDR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDBYTEN (rw) register accessor: Command Program Byte Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdbyten::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdbyten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdbyten`]
module"]
pub type CMDBYTEN = crate :: Reg < cmdbyten :: CMDBYTEN_SPEC > ; # [doc = "Command Program Byte Enable Register"]
pub mod cmdbyten { # [doc = "Register `CMDBYTEN` reader"]
pub type R = crate :: R < CMDBYTEN_SPEC > ; # [doc = "Register `CMDBYTEN` writer"]
pub type W = crate :: W < CMDBYTEN_SPEC > ; # [doc = "Field `CMDBYTEN_VAL` reader - Command Byte Enable value. A 1-bit per flash word byte value is placed in this register."]
pub type CMDBYTEN_VAL_R = crate :: FieldReader ; # [doc = "Field `CMDBYTEN_VAL` writer - Command Byte Enable value. A 1-bit per flash word byte value is placed in this register."]
pub type CMDBYTEN_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Command Byte Enable value. A 1-bit per flash word byte value is placed in this register."]
# [inline (always)]
pub fn cmdbyten_val (& self) -> CMDBYTEN_VAL_R { CMDBYTEN_VAL_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Command Byte Enable value. A 1-bit per flash word byte value is placed in this register."]
# [inline (always)]
# [must_use]
pub fn cmdbyten_val (& mut self) -> CMDBYTEN_VAL_W < CMDBYTEN_SPEC , 0 > { CMDBYTEN_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Program Byte Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdbyten::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdbyten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDBYTEN_SPEC ; impl crate :: RegisterSpec for CMDBYTEN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdbyten::R`](R) reader structure"]
impl crate :: Readable for CMDBYTEN_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdbyten::W`](W) writer structure"]
impl crate :: Writable for CMDBYTEN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDBYTEN to value 0"]
impl crate :: Resettable for CMDBYTEN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDDATA0 (rw) register accessor: Command Data Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmddata0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmddata0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmddata0`]
module"]
pub type CMDDATA0 = crate :: Reg < cmddata0 :: CMDDATA0_SPEC > ; # [doc = "Command Data Register 0"]
pub mod cmddata0 { # [doc = "Register `CMDDATA0` reader"]
pub type R = crate :: R < CMDDATA0_SPEC > ; # [doc = "Register `CMDDATA0` writer"]
pub type W = crate :: W < CMDDATA0_SPEC > ; # [doc = "Field `CMDDATA0_VAL` reader - A 32-bit data value is placed in this field."]
pub type CMDDATA0_VAL_R = crate :: FieldReader < u32 > ; # [doc = "Field `CMDDATA0_VAL` writer - A 32-bit data value is placed in this field."]
pub type CMDDATA0_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - A 32-bit data value is placed in this field."]
# [inline (always)]
pub fn cmddata0_val (& self) -> CMDDATA0_VAL_R { CMDDATA0_VAL_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - A 32-bit data value is placed in this field."]
# [inline (always)]
# [must_use]
pub fn cmddata0_val (& mut self) -> CMDDATA0_VAL_W < CMDDATA0_SPEC , 0 > { CMDDATA0_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Data Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmddata0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmddata0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDDATA0_SPEC ; impl crate :: RegisterSpec for CMDDATA0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmddata0::R`](R) reader structure"]
impl crate :: Readable for CMDDATA0_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmddata0::W`](W) writer structure"]
impl crate :: Writable for CMDDATA0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDDATA0 to value 0"]
impl crate :: Resettable for CMDDATA0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDDATA1 (rw) register accessor: Command Data Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmddata1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmddata1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmddata1`]
module"]
pub type CMDDATA1 = crate :: Reg < cmddata1 :: CMDDATA1_SPEC > ; # [doc = "Command Data Register 1"]
pub mod cmddata1 { # [doc = "Register `CMDDATA1` reader"]
pub type R = crate :: R < CMDDATA1_SPEC > ; # [doc = "Register `CMDDATA1` writer"]
pub type W = crate :: W < CMDDATA1_SPEC > ; # [doc = "Field `CMDDATA1_VAL` reader - A 32-bit data value is placed in this field."]
pub type CMDDATA1_VAL_R = crate :: FieldReader < u32 > ; # [doc = "Field `CMDDATA1_VAL` writer - A 32-bit data value is placed in this field."]
pub type CMDDATA1_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - A 32-bit data value is placed in this field."]
# [inline (always)]
pub fn cmddata1_val (& self) -> CMDDATA1_VAL_R { CMDDATA1_VAL_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - A 32-bit data value is placed in this field."]
# [inline (always)]
# [must_use]
pub fn cmddata1_val (& mut self) -> CMDDATA1_VAL_W < CMDDATA1_SPEC , 0 > { CMDDATA1_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Data Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmddata1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmddata1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDDATA1_SPEC ; impl crate :: RegisterSpec for CMDDATA1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmddata1::R`](R) reader structure"]
impl crate :: Readable for CMDDATA1_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmddata1::W`](W) writer structure"]
impl crate :: Writable for CMDDATA1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDDATA1 to value 0"]
impl crate :: Resettable for CMDDATA1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDWEPROTA (rw) register accessor: Command Write Erase Protect A Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprota::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprota::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdweprota`]
module"]
pub type CMDWEPROTA = crate :: Reg < cmdweprota :: CMDWEPROTA_SPEC > ; # [doc = "Command Write Erase Protect A Register"]
pub mod cmdweprota { # [doc = "Register `CMDWEPROTA` reader"]
pub type R = crate :: R < CMDWEPROTA_SPEC > ; # [doc = "Register `CMDWEPROTA` writer"]
pub type W = crate :: W < CMDWEPROTA_SPEC > ; # [doc = "Field `CMDWEPROTA_VAL` reader - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the flash memory will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the flash memory will be protected from program and erase."]
pub type CMDWEPROTA_VAL_R = crate :: FieldReader < u32 > ; # [doc = "Field `CMDWEPROTA_VAL` writer - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the flash memory will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the flash memory will be protected from program and erase."]
pub type CMDWEPROTA_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the flash memory will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the flash memory will be protected from program and erase."]
# [inline (always)]
pub fn cmdweprota_val (& self) -> CMDWEPROTA_VAL_R { CMDWEPROTA_VAL_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the flash memory will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the flash memory will be protected from program and erase."]
# [inline (always)]
# [must_use]
pub fn cmdweprota_val (& mut self) -> CMDWEPROTA_VAL_W < CMDWEPROTA_SPEC , 0 > { CMDWEPROTA_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Write Erase Protect A Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprota::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprota::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDWEPROTA_SPEC ; impl crate :: RegisterSpec for CMDWEPROTA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdweprota::R`](R) reader structure"]
impl crate :: Readable for CMDWEPROTA_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdweprota::W`](W) writer structure"]
impl crate :: Writable for CMDWEPROTA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDWEPROTA to value 0"]
impl crate :: Resettable for CMDWEPROTA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDWEPROTB (rw) register accessor: Command Write Erase Protect B Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprotb::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprotb::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdweprotb`]
module"]
pub type CMDWEPROTB = crate :: Reg < cmdweprotb :: CMDWEPROTB_SPEC > ; # [doc = "Command Write Erase Protect B Register"]
pub mod cmdweprotb { # [doc = "Register `CMDWEPROTB` reader"]
pub type R = crate :: R < CMDWEPROTB_SPEC > ; # [doc = "Register `CMDWEPROTB` writer"]
pub type W = crate :: W < CMDWEPROTB_SPEC > ; # [doc = "Field `CMDWEPROTB_VAL` reader - Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register."]
pub type CMDWEPROTB_VAL_R = crate :: FieldReader ; # [doc = "Field `CMDWEPROTB_VAL` writer - Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register."]
pub type CMDWEPROTB_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bits 0:3 - Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register."]
# [inline (always)]
pub fn cmdweprotb_val (& self) -> CMDWEPROTB_VAL_R { CMDWEPROTB_VAL_R :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register."]
# [inline (always)]
# [must_use]
pub fn cmdweprotb_val (& mut self) -> CMDWEPROTB_VAL_W < CMDWEPROTB_SPEC , 0 > { CMDWEPROTB_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Write Erase Protect B Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprotb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprotb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDWEPROTB_SPEC ; impl crate :: RegisterSpec for CMDWEPROTB_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdweprotb::R`](R) reader structure"]
impl crate :: Readable for CMDWEPROTB_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdweprotb::W`](W) writer structure"]
impl crate :: Writable for CMDWEPROTB_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDWEPROTB to value 0"]
impl crate :: Resettable for CMDWEPROTB_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDWEPROTNM (rw) register accessor: Command Write Erase Protect Non-Main Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprotnm::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprotnm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdweprotnm`]
module"]
pub type CMDWEPROTNM = crate :: Reg < cmdweprotnm :: CMDWEPROTNM_SPEC > ; # [doc = "Command Write Erase Protect Non-Main Register"]
pub mod cmdweprotnm { # [doc = "Register `CMDWEPROTNM` reader"]
pub type R = crate :: R < CMDWEPROTNM_SPEC > ; # [doc = "Register `CMDWEPROTNM` writer"]
pub type W = crate :: W < CMDWEPROTNM_SPEC > ; # [doc = "Field `CMDWEPROTNM_VAL` reader - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the non-main region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the non-main will be protected from program and erase."]
pub type CMDWEPROTNM_VAL_R = crate :: BitReader ; # [doc = "Field `CMDWEPROTNM_VAL` writer - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the non-main region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the non-main will be protected from program and erase."]
pub type CMDWEPROTNM_VAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; impl R { # [doc = "Bit 0 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the non-main region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the non-main will be protected from program and erase."]
# [inline (always)]
pub fn cmdweprotnm_val (& self) -> CMDWEPROTNM_VAL_R { CMDWEPROTNM_VAL_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the non-main region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the non-main will be protected from program and erase."]
# [inline (always)]
# [must_use]
pub fn cmdweprotnm_val (& mut self) -> CMDWEPROTNM_VAL_W < CMDWEPROTNM_SPEC , 0 > { CMDWEPROTNM_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Write Erase Protect Non-Main Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprotnm::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprotnm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDWEPROTNM_SPEC ; impl crate :: RegisterSpec for CMDWEPROTNM_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdweprotnm::R`](R) reader structure"]
impl crate :: Readable for CMDWEPROTNM_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdweprotnm::W`](W) writer structure"]
impl crate :: Writable for CMDWEPROTNM_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDWEPROTNM to value 0"]
impl crate :: Resettable for CMDWEPROTNM_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDWEPROTTR (rw) register accessor: Command Write Erase Protect Trim Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprottr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprottr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdweprottr`]
module"]
pub type CMDWEPROTTR = crate :: Reg < cmdweprottr :: CMDWEPROTTR_SPEC > ; # [doc = "Command Write Erase Protect Trim Register"]
pub mod cmdweprottr { # [doc = "Register `CMDWEPROTTR` reader"]
pub type R = crate :: R < CMDWEPROTTR_SPEC > ; # [doc = "Register `CMDWEPROTTR` writer"]
pub type W = crate :: W < CMDWEPROTTR_SPEC > ; # [doc = "Field `CMDWEPROTTR_VAL` reader - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
pub type CMDWEPROTTR_VAL_R = crate :: BitReader ; # [doc = "Field `CMDWEPROTTR_VAL` writer - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
pub type CMDWEPROTTR_VAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; impl R { # [doc = "Bit 0 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
# [inline (always)]
pub fn cmdweprottr_val (& self) -> CMDWEPROTTR_VAL_R { CMDWEPROTTR_VAL_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
# [inline (always)]
# [must_use]
pub fn cmdweprottr_val (& mut self) -> CMDWEPROTTR_VAL_W < CMDWEPROTTR_SPEC , 0 > { CMDWEPROTTR_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Write Erase Protect Trim Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweprottr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweprottr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDWEPROTTR_SPEC ; impl crate :: RegisterSpec for CMDWEPROTTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdweprottr::R`](R) reader structure"]
impl crate :: Readable for CMDWEPROTTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdweprottr::W`](W) writer structure"]
impl crate :: Writable for CMDWEPROTTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDWEPROTTR to value 0"]
impl crate :: Resettable for CMDWEPROTTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CMDWEPROTEN (rw) register accessor: Command Write Erase Protect Engr Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweproten::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweproten::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmdweproten`]
module"]
pub type CMDWEPROTEN = crate :: Reg < cmdweproten :: CMDWEPROTEN_SPEC > ; # [doc = "Command Write Erase Protect Engr Register"]
pub mod cmdweproten { # [doc = "Register `CMDWEPROTEN` reader"]
pub type R = crate :: R < CMDWEPROTEN_SPEC > ; # [doc = "Register `CMDWEPROTEN` writer"]
pub type W = crate :: W < CMDWEPROTEN_SPEC > ; # [doc = "Field `CMDWEPROTEN_VAL` reader - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
pub type CMDWEPROTEN_VAL_R = crate :: FieldReader ; # [doc = "Field `CMDWEPROTEN_VAL` writer - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
pub type CMDWEPROTEN_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O > ; impl R { # [doc = "Bits 0:1 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
# [inline (always)]
pub fn cmdweproten_val (& self) -> CMDWEPROTEN_VAL_R { CMDWEPROTEN_VAL_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Each bit protects 1 sector. bit \\[0\\]: When 1, sector 0 of the engr region will be protected from program and erase. bit \\[1\\]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit \\[31\\]: When 1, sector 31 of the engr region will be protected from program and erase."]
# [inline (always)]
# [must_use]
pub fn cmdweproten_val (& mut self) -> CMDWEPROTEN_VAL_W < CMDWEPROTEN_SPEC , 0 > { CMDWEPROTEN_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Write Erase Protect Engr Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmdweproten::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmdweproten::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CMDWEPROTEN_SPEC ; impl crate :: RegisterSpec for CMDWEPROTEN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cmdweproten::R`](R) reader structure"]
impl crate :: Readable for CMDWEPROTEN_SPEC { } # [doc = "`write(|w| ..)` method takes [`cmdweproten::W`](W) writer structure"]
impl crate :: Writable for CMDWEPROTEN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CMDWEPROTEN to value 0"]
impl crate :: Resettable for CMDWEPROTEN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CFGCMD (rw) register accessor: Command Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgcmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgcmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgcmd`]
module"]
pub type CFGCMD = crate :: Reg < cfgcmd :: CFGCMD_SPEC > ; # [doc = "Command Configuration Register"]
pub mod cfgcmd { # [doc = "Register `CFGCMD` reader"]
pub type R = crate :: R < CFGCMD_SPEC > ; # [doc = "Register `CFGCMD` writer"]
pub type W = crate :: W < CFGCMD_SPEC > ; # [doc = "Field `CFGCMD_WAITSTATE` reader - Wait State setting for program verify, erase verify and read verify"]
pub type CFGCMD_WAITSTATE_R = crate :: FieldReader ; # [doc = "Field `CFGCMD_WAITSTATE` writer - Wait State setting for program verify, erase verify and read verify"]
pub type CFGCMD_WAITSTATE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bits 0:3 - Wait State setting for program verify, erase verify and read verify"]
# [inline (always)]
pub fn cfgcmd_waitstate (& self) -> CFGCMD_WAITSTATE_R { CFGCMD_WAITSTATE_R :: new ((self . bits & 0x0f) as u8) } } impl W { # [doc = "Bits 0:3 - Wait State setting for program verify, erase verify and read verify"]
# [inline (always)]
# [must_use]
pub fn cfgcmd_waitstate (& mut self) -> CFGCMD_WAITSTATE_W < CFGCMD_SPEC , 0 > { CFGCMD_WAITSTATE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Command Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgcmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgcmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGCMD_SPEC ; impl crate :: RegisterSpec for CFGCMD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgcmd::R`](R) reader structure"]
impl crate :: Readable for CFGCMD_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgcmd::W`](W) writer structure"]
impl crate :: Writable for CFGCMD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGCMD to value 0"]
impl crate :: Resettable for CFGCMD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CFGPCNT (rw) register accessor: Pulse Counter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgpcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgpcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgpcnt`]
module"]
pub type CFGPCNT = crate :: Reg < cfgpcnt :: CFGPCNT_SPEC > ; # [doc = "Pulse Counter Configuration Register"]
pub mod cfgpcnt { # [doc = "Register `CFGPCNT` reader"]
pub type R = crate :: R < CFGPCNT_SPEC > ; # [doc = "Register `CFGPCNT` writer"]
pub type W = crate :: W < CFGPCNT_SPEC > ; # [doc = "Field `CFGPCNT_MAXPCNTOVR` reader - Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used."]
pub type CFGPCNT_MAXPCNTOVR_R = crate :: BitReader < CFGPCNT_MAXPCNTOVR_A > ; # [doc = "Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CFGPCNT_MAXPCNTOVR_A { # [doc = "0: DEFAULT"]
CFGPCNT_MAXPCNTOVR_DEFAULT = 0 , # [doc = "1: OVERRIDE"]
CFGPCNT_MAXPCNTOVR_OVERRIDE = 1 , } impl From < CFGPCNT_MAXPCNTOVR_A > for bool { # [inline (always)]
fn from (variant : CFGPCNT_MAXPCNTOVR_A) -> Self { variant as u8 != 0 } } impl CFGPCNT_MAXPCNTOVR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CFGPCNT_MAXPCNTOVR_A { match self . bits { false => CFGPCNT_MAXPCNTOVR_A :: CFGPCNT_MAXPCNTOVR_DEFAULT , true => CFGPCNT_MAXPCNTOVR_A :: CFGPCNT_MAXPCNTOVR_OVERRIDE , } } # [doc = "DEFAULT"]
# [inline (always)]
pub fn is_cfgpcnt_maxpcntovr_default (& self) -> bool { * self == CFGPCNT_MAXPCNTOVR_A :: CFGPCNT_MAXPCNTOVR_DEFAULT } # [doc = "OVERRIDE"]
# [inline (always)]
pub fn is_cfgpcnt_maxpcntovr_override (& self) -> bool { * self == CFGPCNT_MAXPCNTOVR_A :: CFGPCNT_MAXPCNTOVR_OVERRIDE } } # [doc = "Field `CFGPCNT_MAXPCNTOVR` writer - Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used."]
pub type CFGPCNT_MAXPCNTOVR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGPCNT_MAXPCNTOVR_A > ; impl < 'a , REG , const O : u8 > CFGPCNT_MAXPCNTOVR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DEFAULT"]
# [inline (always)]
pub fn cfgpcnt_maxpcntovr_default (self) -> & 'a mut crate :: W < REG > { self . variant (CFGPCNT_MAXPCNTOVR_A :: CFGPCNT_MAXPCNTOVR_DEFAULT) } # [doc = "OVERRIDE"]
# [inline (always)]
pub fn cfgpcnt_maxpcntovr_override (self) -> & 'a mut crate :: W < REG > { self . variant (CFGPCNT_MAXPCNTOVR_A :: CFGPCNT_MAXPCNTOVR_OVERRIDE) } } # [doc = "Field `CFGPCNT_MAXPCNTVAL` reader - Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}."]
pub type CFGPCNT_MAXPCNTVAL_R = crate :: FieldReader ; # [doc = "Field `CFGPCNT_MAXPCNTVAL` writer - Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}."]
pub type CFGPCNT_MAXPCNTVAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bit 0 - Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used."]
# [inline (always)]
pub fn cfgpcnt_maxpcntovr (& self) -> CFGPCNT_MAXPCNTOVR_R { CFGPCNT_MAXPCNTOVR_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 4:11 - Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}."]
# [inline (always)]
pub fn cfgpcnt_maxpcntval (& self) -> CFGPCNT_MAXPCNTVAL_R { CFGPCNT_MAXPCNTVAL_R :: new (((self . bits >> 4) & 0xff) as u8) } } impl W { # [doc = "Bit 0 - Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used."]
# [inline (always)]
# [must_use]
pub fn cfgpcnt_maxpcntovr (& mut self) -> CFGPCNT_MAXPCNTOVR_W < CFGPCNT_SPEC , 0 > { CFGPCNT_MAXPCNTOVR_W :: new (self) } # [doc = "Bits 4:11 - Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}."]
# [inline (always)]
# [must_use]
pub fn cfgpcnt_maxpcntval (& mut self) -> CFGPCNT_MAXPCNTVAL_W < CFGPCNT_SPEC , 4 > { CFGPCNT_MAXPCNTVAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Pulse Counter Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgpcnt::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgpcnt::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGPCNT_SPEC ; impl crate :: RegisterSpec for CFGPCNT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgpcnt::R`](R) reader structure"]
impl crate :: Readable for CFGPCNT_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgpcnt::W`](W) writer structure"]
impl crate :: Writable for CFGPCNT_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGPCNT to value 0"]
impl crate :: Resettable for CFGPCNT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STATCMD (r) register accessor: Command Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statcmd::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statcmd`]
module"]
pub type STATCMD = crate :: Reg < statcmd :: STATCMD_SPEC > ; # [doc = "Command Status Register"]
pub mod statcmd { # [doc = "Register `STATCMD` reader"]
pub type R = crate :: R < STATCMD_SPEC > ; # [doc = "Field `STATCMD_CMDDONE` reader - Command Done"]
pub type STATCMD_CMDDONE_R = crate :: BitReader < STATCMD_CMDDONE_A > ; # [doc = "Command Done\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_CMDDONE_A { # [doc = "0: STATNOTDONE"]
STATCMD_CMDDONE_STATNOTDONE = 0 , # [doc = "1: STATDONE"]
STATCMD_CMDDONE_STATDONE = 1 , } impl From < STATCMD_CMDDONE_A > for bool { # [inline (always)]
fn from (variant : STATCMD_CMDDONE_A) -> Self { variant as u8 != 0 } } impl STATCMD_CMDDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_CMDDONE_A { match self . bits { false => STATCMD_CMDDONE_A :: STATCMD_CMDDONE_STATNOTDONE , true => STATCMD_CMDDONE_A :: STATCMD_CMDDONE_STATDONE , } } # [doc = "STATNOTDONE"]
# [inline (always)]
pub fn is_statcmd_cmddone_statnotdone (& self) -> bool { * self == STATCMD_CMDDONE_A :: STATCMD_CMDDONE_STATNOTDONE } # [doc = "STATDONE"]
# [inline (always)]
pub fn is_statcmd_cmddone_statdone (& self) -> bool { * self == STATCMD_CMDDONE_A :: STATCMD_CMDDONE_STATDONE } } # [doc = "Field `STATCMD_CMDPASS` reader - Command Pass - valid when CMD_DONE field is 1"]
pub type STATCMD_CMDPASS_R = crate :: BitReader < STATCMD_CMDPASS_A > ; # [doc = "Command Pass - valid when CMD_DONE field is 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_CMDPASS_A { # [doc = "0: STATFAIL"]
STATCMD_CMDPASS_STATFAIL = 0 , # [doc = "1: STATPASS"]
STATCMD_CMDPASS_STATPASS = 1 , } impl From < STATCMD_CMDPASS_A > for bool { # [inline (always)]
fn from (variant : STATCMD_CMDPASS_A) -> Self { variant as u8 != 0 } } impl STATCMD_CMDPASS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_CMDPASS_A { match self . bits { false => STATCMD_CMDPASS_A :: STATCMD_CMDPASS_STATFAIL , true => STATCMD_CMDPASS_A :: STATCMD_CMDPASS_STATPASS , } } # [doc = "STATFAIL"]
# [inline (always)]
pub fn is_statcmd_cmdpass_statfail (& self) -> bool { * self == STATCMD_CMDPASS_A :: STATCMD_CMDPASS_STATFAIL } # [doc = "STATPASS"]
# [inline (always)]
pub fn is_statcmd_cmdpass_statpass (& self) -> bool { * self == STATCMD_CMDPASS_A :: STATCMD_CMDPASS_STATPASS } } # [doc = "Field `STATCMD_CMDINPROGRESS` reader - Command In Progress"]
pub type STATCMD_CMDINPROGRESS_R = crate :: BitReader < STATCMD_CMDINPROGRESS_A > ; # [doc = "Command In Progress\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_CMDINPROGRESS_A { # [doc = "0: STATCOMPLETE"]
STATCMD_CMDINPROGRESS_STATCOMPLETE = 0 , # [doc = "1: STATINPROGRESS"]
STATCMD_CMDINPROGRESS_STATINPROGRESS = 1 , } impl From < STATCMD_CMDINPROGRESS_A > for bool { # [inline (always)]
fn from (variant : STATCMD_CMDINPROGRESS_A) -> Self { variant as u8 != 0 } } impl STATCMD_CMDINPROGRESS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_CMDINPROGRESS_A { match self . bits { false => STATCMD_CMDINPROGRESS_A :: STATCMD_CMDINPROGRESS_STATCOMPLETE , true => STATCMD_CMDINPROGRESS_A :: STATCMD_CMDINPROGRESS_STATINPROGRESS , } } # [doc = "STATCOMPLETE"]
# [inline (always)]
pub fn is_statcmd_cmdinprogress_statcomplete (& self) -> bool { * self == STATCMD_CMDINPROGRESS_A :: STATCMD_CMDINPROGRESS_STATCOMPLETE } # [doc = "STATINPROGRESS"]
# [inline (always)]
pub fn is_statcmd_cmdinprogress_statinprogress (& self) -> bool { * self == STATCMD_CMDINPROGRESS_A :: STATCMD_CMDINPROGRESS_STATINPROGRESS } } # [doc = "Field `STATCMD_FAILWEPROT` reader - Command failed due to Write/Erase Protect Sector Violation"]
pub type STATCMD_FAILWEPROT_R = crate :: BitReader < STATCMD_FAILWEPROT_A > ; # [doc = "Command failed due to Write/Erase Protect Sector Violation\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_FAILWEPROT_A { # [doc = "0: STATNOFAIL"]
STATCMD_FAILWEPROT_STATNOFAIL = 0 , # [doc = "1: STATFAIL"]
STATCMD_FAILWEPROT_STATFAIL = 1 , } impl From < STATCMD_FAILWEPROT_A > for bool { # [inline (always)]
fn from (variant : STATCMD_FAILWEPROT_A) -> Self { variant as u8 != 0 } } impl STATCMD_FAILWEPROT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_FAILWEPROT_A { match self . bits { false => STATCMD_FAILWEPROT_A :: STATCMD_FAILWEPROT_STATNOFAIL , true => STATCMD_FAILWEPROT_A :: STATCMD_FAILWEPROT_STATFAIL , } } # [doc = "STATNOFAIL"]
# [inline (always)]
pub fn is_statcmd_failweprot_statnofail (& self) -> bool { * self == STATCMD_FAILWEPROT_A :: STATCMD_FAILWEPROT_STATNOFAIL } # [doc = "STATFAIL"]
# [inline (always)]
pub fn is_statcmd_failweprot_statfail (& self) -> bool { * self == STATCMD_FAILWEPROT_A :: STATCMD_FAILWEPROT_STATFAIL } } # [doc = "Field `STATCMD_FAILVERIFY` reader - Command failed due to verify error"]
pub type STATCMD_FAILVERIFY_R = crate :: BitReader < STATCMD_FAILVERIFY_A > ; # [doc = "Command failed due to verify error\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_FAILVERIFY_A { # [doc = "0: STATNOFAIL"]
STATCMD_FAILVERIFY_STATNOFAIL = 0 , # [doc = "1: STATFAIL"]
STATCMD_FAILVERIFY_STATFAIL = 1 , } impl From < STATCMD_FAILVERIFY_A > for bool { # [inline (always)]
fn from (variant : STATCMD_FAILVERIFY_A) -> Self { variant as u8 != 0 } } impl STATCMD_FAILVERIFY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_FAILVERIFY_A { match self . bits { false => STATCMD_FAILVERIFY_A :: STATCMD_FAILVERIFY_STATNOFAIL , true => STATCMD_FAILVERIFY_A :: STATCMD_FAILVERIFY_STATFAIL , } } # [doc = "STATNOFAIL"]
# [inline (always)]
pub fn is_statcmd_failverify_statnofail (& self) -> bool { * self == STATCMD_FAILVERIFY_A :: STATCMD_FAILVERIFY_STATNOFAIL } # [doc = "STATFAIL"]
# [inline (always)]
pub fn is_statcmd_failverify_statfail (& self) -> bool { * self == STATCMD_FAILVERIFY_A :: STATCMD_FAILVERIFY_STATFAIL } } # [doc = "Field `STATCMD_FAILILLADDR` reader - Command failed due to the use of an illegal address"]
pub type STATCMD_FAILILLADDR_R = crate :: BitReader < STATCMD_FAILILLADDR_A > ; # [doc = "Command failed due to the use of an illegal address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_FAILILLADDR_A { # [doc = "0: STATNOFAIL"]
STATCMD_FAILILLADDR_STATNOFAIL = 0 , # [doc = "1: STATFAIL"]
STATCMD_FAILILLADDR_STATFAIL = 1 , } impl From < STATCMD_FAILILLADDR_A > for bool { # [inline (always)]
fn from (variant : STATCMD_FAILILLADDR_A) -> Self { variant as u8 != 0 } } impl STATCMD_FAILILLADDR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_FAILILLADDR_A { match self . bits { false => STATCMD_FAILILLADDR_A :: STATCMD_FAILILLADDR_STATNOFAIL , true => STATCMD_FAILILLADDR_A :: STATCMD_FAILILLADDR_STATFAIL , } } # [doc = "STATNOFAIL"]
# [inline (always)]
pub fn is_statcmd_faililladdr_statnofail (& self) -> bool { * self == STATCMD_FAILILLADDR_A :: STATCMD_FAILILLADDR_STATNOFAIL } # [doc = "STATFAIL"]
# [inline (always)]
pub fn is_statcmd_faililladdr_statfail (& self) -> bool { * self == STATCMD_FAILILLADDR_A :: STATCMD_FAILILLADDR_STATFAIL } } # [doc = "Field `STATCMD_FAILMODE` reader - Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode."]
pub type STATCMD_FAILMODE_R = crate :: BitReader < STATCMD_FAILMODE_A > ; # [doc = "Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_FAILMODE_A { # [doc = "0: STATNOFAIL"]
STATCMD_FAILMODE_STATNOFAIL = 0 , # [doc = "1: STATFAIL"]
STATCMD_FAILMODE_STATFAIL = 1 , } impl From < STATCMD_FAILMODE_A > for bool { # [inline (always)]
fn from (variant : STATCMD_FAILMODE_A) -> Self { variant as u8 != 0 } } impl STATCMD_FAILMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_FAILMODE_A { match self . bits { false => STATCMD_FAILMODE_A :: STATCMD_FAILMODE_STATNOFAIL , true => STATCMD_FAILMODE_A :: STATCMD_FAILMODE_STATFAIL , } } # [doc = "STATNOFAIL"]
# [inline (always)]
pub fn is_statcmd_failmode_statnofail (& self) -> bool { * self == STATCMD_FAILMODE_A :: STATCMD_FAILMODE_STATNOFAIL } # [doc = "STATFAIL"]
# [inline (always)]
pub fn is_statcmd_failmode_statfail (& self) -> bool { * self == STATCMD_FAILMODE_A :: STATCMD_FAILMODE_STATFAIL } } # [doc = "Field `STATCMD_FAILINVDATA` reader - Program command failed because an attempt was made to program a stored 0 value to a 1."]
pub type STATCMD_FAILINVDATA_R = crate :: BitReader < STATCMD_FAILINVDATA_A > ; # [doc = "Program command failed because an attempt was made to program a stored 0 value to a 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_FAILINVDATA_A { # [doc = "0: STATNOFAIL"]
STATCMD_FAILINVDATA_STATNOFAIL = 0 , # [doc = "1: STATFAIL"]
STATCMD_FAILINVDATA_STATFAIL = 1 , } impl From < STATCMD_FAILINVDATA_A > for bool { # [inline (always)]
fn from (variant : STATCMD_FAILINVDATA_A) -> Self { variant as u8 != 0 } } impl STATCMD_FAILINVDATA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_FAILINVDATA_A { match self . bits { false => STATCMD_FAILINVDATA_A :: STATCMD_FAILINVDATA_STATNOFAIL , true => STATCMD_FAILINVDATA_A :: STATCMD_FAILINVDATA_STATFAIL , } } # [doc = "STATNOFAIL"]
# [inline (always)]
pub fn is_statcmd_failinvdata_statnofail (& self) -> bool { * self == STATCMD_FAILINVDATA_A :: STATCMD_FAILINVDATA_STATNOFAIL } # [doc = "STATFAIL"]
# [inline (always)]
pub fn is_statcmd_failinvdata_statfail (& self) -> bool { * self == STATCMD_FAILINVDATA_A :: STATCMD_FAILINVDATA_STATFAIL } } # [doc = "Field `STATCMD_FAILMISC` reader - Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit."]
pub type STATCMD_FAILMISC_R = crate :: BitReader < STATCMD_FAILMISC_A > ; # [doc = "Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATCMD_FAILMISC_A { # [doc = "0: STATNOFAIL"]
STATCMD_FAILMISC_STATNOFAIL = 0 , # [doc = "1: STATFAIL"]
STATCMD_FAILMISC_STATFAIL = 1 , } impl From < STATCMD_FAILMISC_A > for bool { # [inline (always)]
fn from (variant : STATCMD_FAILMISC_A) -> Self { variant as u8 != 0 } } impl STATCMD_FAILMISC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATCMD_FAILMISC_A { match self . bits { false => STATCMD_FAILMISC_A :: STATCMD_FAILMISC_STATNOFAIL , true => STATCMD_FAILMISC_A :: STATCMD_FAILMISC_STATFAIL , } } # [doc = "STATNOFAIL"]
# [inline (always)]
pub fn is_statcmd_failmisc_statnofail (& self) -> bool { * self == STATCMD_FAILMISC_A :: STATCMD_FAILMISC_STATNOFAIL } # [doc = "STATFAIL"]
# [inline (always)]
pub fn is_statcmd_failmisc_statfail (& self) -> bool { * self == STATCMD_FAILMISC_A :: STATCMD_FAILMISC_STATFAIL } } impl R { # [doc = "Bit 0 - Command Done"]
# [inline (always)]
pub fn statcmd_cmddone (& self) -> STATCMD_CMDDONE_R { STATCMD_CMDDONE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Command Pass - valid when CMD_DONE field is 1"]
# [inline (always)]
pub fn statcmd_cmdpass (& self) -> STATCMD_CMDPASS_R { STATCMD_CMDPASS_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Command In Progress"]
# [inline (always)]
pub fn statcmd_cmdinprogress (& self) -> STATCMD_CMDINPROGRESS_R { STATCMD_CMDINPROGRESS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - Command failed due to Write/Erase Protect Sector Violation"]
# [inline (always)]
pub fn statcmd_failweprot (& self) -> STATCMD_FAILWEPROT_R { STATCMD_FAILWEPROT_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Command failed due to verify error"]
# [inline (always)]
pub fn statcmd_failverify (& self) -> STATCMD_FAILVERIFY_R { STATCMD_FAILVERIFY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Command failed due to the use of an illegal address"]
# [inline (always)]
pub fn statcmd_faililladdr (& self) -> STATCMD_FAILILLADDR_R { STATCMD_FAILILLADDR_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode."]
# [inline (always)]
pub fn statcmd_failmode (& self) -> STATCMD_FAILMODE_R { STATCMD_FAILMODE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Program command failed because an attempt was made to program a stored 0 value to a 1."]
# [inline (always)]
pub fn statcmd_failinvdata (& self) -> STATCMD_FAILINVDATA_R { STATCMD_FAILINVDATA_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 12 - Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit."]
# [inline (always)]
pub fn statcmd_failmisc (& self) -> STATCMD_FAILMISC_R { STATCMD_FAILMISC_R :: new (((self . bits >> 12) & 1) != 0) } } # [doc = "Command Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statcmd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATCMD_SPEC ; impl crate :: RegisterSpec for STATCMD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statcmd::R`](R) reader structure"]
impl crate :: Readable for STATCMD_SPEC { } # [doc = "`reset()` method sets STATCMD to value 0"]
impl crate :: Resettable for STATCMD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STATADDR (r) register accessor: Address Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stataddr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stataddr`]
module"]
pub type STATADDR = crate :: Reg < stataddr :: STATADDR_SPEC > ; # [doc = "Address Status Register"]
pub mod stataddr { # [doc = "Register `STATADDR` reader"]
pub type R = crate :: R < STATADDR_SPEC > ; # [doc = "Field `STATADDR_BANKADDR` reader - Current Bank Address A bank offset address is stored in this register."]
pub type STATADDR_BANKADDR_R = crate :: FieldReader < u16 > ; # [doc = "Field `STATADDR_REGIONID` reader - Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating."]
pub type STATADDR_REGIONID_R = crate :: FieldReader < STATADDR_REGIONID_A > ; # [doc = "Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum STATADDR_REGIONID_A { # [doc = "1: MAIN"]
STATADDR_REGIONID_MAIN = 1 , # [doc = "2: NONMAIN"]
STATADDR_REGIONID_NONMAIN = 2 , # [doc = "4: TRIM"]
STATADDR_REGIONID_TRIM = 4 , # [doc = "8: ENGR"]
STATADDR_REGIONID_ENGR = 8 , } impl From < STATADDR_REGIONID_A > for u8 { # [inline (always)]
fn from (variant : STATADDR_REGIONID_A) -> Self { variant as _ } } impl crate :: FieldSpec for STATADDR_REGIONID_A { type Ux = u8 ; } impl STATADDR_REGIONID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < STATADDR_REGIONID_A > { match self . bits { 1 => Some (STATADDR_REGIONID_A :: STATADDR_REGIONID_MAIN) , 2 => Some (STATADDR_REGIONID_A :: STATADDR_REGIONID_NONMAIN) , 4 => Some (STATADDR_REGIONID_A :: STATADDR_REGIONID_TRIM) , 8 => Some (STATADDR_REGIONID_A :: STATADDR_REGIONID_ENGR) , _ => None , } } # [doc = "MAIN"]
# [inline (always)]
pub fn is_stataddr_regionid_main (& self) -> bool { * self == STATADDR_REGIONID_A :: STATADDR_REGIONID_MAIN } # [doc = "NONMAIN"]
# [inline (always)]
pub fn is_stataddr_regionid_nonmain (& self) -> bool { * self == STATADDR_REGIONID_A :: STATADDR_REGIONID_NONMAIN } # [doc = "TRIM"]
# [inline (always)]
pub fn is_stataddr_regionid_trim (& self) -> bool { * self == STATADDR_REGIONID_A :: STATADDR_REGIONID_TRIM } # [doc = "ENGR"]
# [inline (always)]
pub fn is_stataddr_regionid_engr (& self) -> bool { * self == STATADDR_REGIONID_A :: STATADDR_REGIONID_ENGR } } # [doc = "Field `STATADDR_BANKID` reader - Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank."]
pub type STATADDR_BANKID_R = crate :: FieldReader < STATADDR_BANKID_A > ; # [doc = "Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum STATADDR_BANKID_A { # [doc = "1: BANK0"]
STATADDR_BANKID_BANK0 = 1 , # [doc = "2: BANK1"]
STATADDR_BANKID_BANK1 = 2 , # [doc = "4: BANK2"]
STATADDR_BANKID_BANK2 = 4 , # [doc = "8: BANK3"]
STATADDR_BANKID_BANK3 = 8 , # [doc = "16: BANK4"]
STATADDR_BANKID_BANK4 = 16 , } impl From < STATADDR_BANKID_A > for u8 { # [inline (always)]
fn from (variant : STATADDR_BANKID_A) -> Self { variant as _ } } impl crate :: FieldSpec for STATADDR_BANKID_A { type Ux = u8 ; } impl STATADDR_BANKID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < STATADDR_BANKID_A > { match self . bits { 1 => Some (STATADDR_BANKID_A :: STATADDR_BANKID_BANK0) , 2 => Some (STATADDR_BANKID_A :: STATADDR_BANKID_BANK1) , 4 => Some (STATADDR_BANKID_A :: STATADDR_BANKID_BANK2) , 8 => Some (STATADDR_BANKID_A :: STATADDR_BANKID_BANK3) , 16 => Some (STATADDR_BANKID_A :: STATADDR_BANKID_BANK4) , _ => None , } } # [doc = "BANK0"]
# [inline (always)]
pub fn is_stataddr_bankid_bank0 (& self) -> bool { * self == STATADDR_BANKID_A :: STATADDR_BANKID_BANK0 } # [doc = "BANK1"]
# [inline (always)]
pub fn is_stataddr_bankid_bank1 (& self) -> bool { * self == STATADDR_BANKID_A :: STATADDR_BANKID_BANK1 } # [doc = "BANK2"]
# [inline (always)]
pub fn is_stataddr_bankid_bank2 (& self) -> bool { * self == STATADDR_BANKID_A :: STATADDR_BANKID_BANK2 } # [doc = "BANK3"]
# [inline (always)]
pub fn is_stataddr_bankid_bank3 (& self) -> bool { * self == STATADDR_BANKID_A :: STATADDR_BANKID_BANK3 } # [doc = "BANK4"]
# [inline (always)]
pub fn is_stataddr_bankid_bank4 (& self) -> bool { * self == STATADDR_BANKID_A :: STATADDR_BANKID_BANK4 } } impl R { # [doc = "Bits 0:15 - Current Bank Address A bank offset address is stored in this register."]
# [inline (always)]
pub fn stataddr_bankaddr (& self) -> STATADDR_BANKADDR_R { STATADDR_BANKADDR_R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:20 - Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating."]
# [inline (always)]
pub fn stataddr_regionid (& self) -> STATADDR_REGIONID_R { STATADDR_REGIONID_R :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:25 - Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank."]
# [inline (always)]
pub fn stataddr_bankid (& self) -> STATADDR_BANKID_R { STATADDR_BANKID_R :: new (((self . bits >> 21) & 0x1f) as u8) } } # [doc = "Address Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stataddr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATADDR_SPEC ; impl crate :: RegisterSpec for STATADDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stataddr::R`](R) reader structure"]
impl crate :: Readable for STATADDR_SPEC { } # [doc = "`reset()` method sets STATADDR to value 0"]
impl crate :: Resettable for STATADDR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STATPCNT (r) register accessor: Pulse Count Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statpcnt::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statpcnt`]
module"]
pub type STATPCNT = crate :: Reg < statpcnt :: STATPCNT_SPEC > ; # [doc = "Pulse Count Status Register"]
pub mod statpcnt { # [doc = "Register `STATPCNT` reader"]
pub type R = crate :: R < STATPCNT_SPEC > ; # [doc = "Field `STATPCNT_PULSECNT` reader - Current Pulse Counter Value"]
pub type STATPCNT_PULSECNT_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:11 - Current Pulse Counter Value"]
# [inline (always)]
pub fn statpcnt_pulsecnt (& self) -> STATPCNT_PULSECNT_R { STATPCNT_PULSECNT_R :: new ((self . bits & 0x0fff) as u16) } } # [doc = "Pulse Count Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statpcnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATPCNT_SPEC ; impl crate :: RegisterSpec for STATPCNT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statpcnt::R`](R) reader structure"]
impl crate :: Readable for STATPCNT_SPEC { } # [doc = "`reset()` method sets STATPCNT to value 0"]
impl crate :: Resettable for STATPCNT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STATMODE (r) register accessor: Mode Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statmode::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@statmode`]
module"]
pub type STATMODE = crate :: Reg < statmode :: STATMODE_SPEC > ; # [doc = "Mode Status Register"]
pub mod statmode { # [doc = "Register `STATMODE` reader"]
pub type R = crate :: R < STATMODE_SPEC > ; # [doc = "Field `STATMODE_BANKNOTINRD` reader - Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank."]
pub type STATMODE_BANKNOTINRD_R = crate :: BitReader < STATMODE_BANKNOTINRD_A > ; # [doc = "Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATMODE_BANKNOTINRD_A { # [doc = "1: BANK0"]
STATMODE_BANKNOTINRD_BANK0 = 1 , } impl From < STATMODE_BANKNOTINRD_A > for bool { # [inline (always)]
fn from (variant : STATMODE_BANKNOTINRD_A) -> Self { variant as u8 != 0 } } impl STATMODE_BANKNOTINRD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < STATMODE_BANKNOTINRD_A > { match self . bits { true => Some (STATMODE_BANKNOTINRD_A :: STATMODE_BANKNOTINRD_BANK0) , _ => None , } } # [doc = "BANK0"]
# [inline (always)]
pub fn is_statmode_banknotinrd_bank0 (& self) -> bool { * self == STATMODE_BANKNOTINRD_A :: STATMODE_BANKNOTINRD_BANK0 } } # [doc = "Field `STATMODE_BANKMODE` reader - Indicates mode of bank(s) that are not in READ mode"]
pub type STATMODE_BANKMODE_R = crate :: FieldReader < STATMODE_BANKMODE_A > ; # [doc = "Indicates mode of bank(s) that are not in READ mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum STATMODE_BANKMODE_A { # [doc = "0: READ"]
STATMODE_BANKMODE_READ = 0 , # [doc = "2: RDMARG0"]
STATMODE_BANKMODE_RDMARG0 = 2 , # [doc = "4: RDMARG1"]
STATMODE_BANKMODE_RDMARG1 = 4 , # [doc = "6: RDMARG0B"]
STATMODE_BANKMODE_RDMARG0B = 6 , # [doc = "7: RDMARG1B"]
STATMODE_BANKMODE_RDMARG1B = 7 , # [doc = "9: PGMVER"]
STATMODE_BANKMODE_PGMVER = 9 , # [doc = "10: PGMSW"]
STATMODE_BANKMODE_PGMSW = 10 , # [doc = "11: ERASEVER"]
STATMODE_BANKMODE_ERASEVER = 11 , # [doc = "12: ERASESECT"]
STATMODE_BANKMODE_ERASESECT = 12 , # [doc = "14: PGMMW"]
STATMODE_BANKMODE_PGMMW = 14 , # [doc = "15: ERASEBNK"]
STATMODE_BANKMODE_ERASEBNK = 15 , } impl From < STATMODE_BANKMODE_A > for u8 { # [inline (always)]
fn from (variant : STATMODE_BANKMODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for STATMODE_BANKMODE_A { type Ux = u8 ; } impl STATMODE_BANKMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < STATMODE_BANKMODE_A > { match self . bits { 0 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_READ) , 2 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG0) , 4 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG1) , 6 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG0B) , 7 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG1B) , 9 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_PGMVER) , 10 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_PGMSW) , 11 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_ERASEVER) , 12 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_ERASESECT) , 14 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_PGMMW) , 15 => Some (STATMODE_BANKMODE_A :: STATMODE_BANKMODE_ERASEBNK) , _ => None , } } # [doc = "READ"]
# [inline (always)]
pub fn is_statmode_bankmode_read (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_READ } # [doc = "RDMARG0"]
# [inline (always)]
pub fn is_statmode_bankmode_rdmarg0 (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG0 } # [doc = "RDMARG1"]
# [inline (always)]
pub fn is_statmode_bankmode_rdmarg1 (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG1 } # [doc = "RDMARG0B"]
# [inline (always)]
pub fn is_statmode_bankmode_rdmarg0b (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG0B } # [doc = "RDMARG1B"]
# [inline (always)]
pub fn is_statmode_bankmode_rdmarg1b (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_RDMARG1B } # [doc = "PGMVER"]
# [inline (always)]
pub fn is_statmode_bankmode_pgmver (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_PGMVER } # [doc = "PGMSW"]
# [inline (always)]
pub fn is_statmode_bankmode_pgmsw (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_PGMSW } # [doc = "ERASEVER"]
# [inline (always)]
pub fn is_statmode_bankmode_erasever (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_ERASEVER } # [doc = "ERASESECT"]
# [inline (always)]
pub fn is_statmode_bankmode_erasesect (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_ERASESECT } # [doc = "PGMMW"]
# [inline (always)]
pub fn is_statmode_bankmode_pgmmw (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_PGMMW } # [doc = "ERASEBNK"]
# [inline (always)]
pub fn is_statmode_bankmode_erasebnk (& self) -> bool { * self == STATMODE_BANKMODE_A :: STATMODE_BANKMODE_ERASEBNK } } # [doc = "Field `STATMODE_BANK2TRDY` reader - Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s)."]
pub type STATMODE_BANK2TRDY_R = crate :: BitReader < STATMODE_BANK2TRDY_A > ; # [doc = "Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATMODE_BANK2TRDY_A { # [doc = "0: FALSE"]
STATMODE_BANK2TRDY_FALSE = 0 , # [doc = "1: TRUE"]
STATMODE_BANK2TRDY_TRUE = 1 , } impl From < STATMODE_BANK2TRDY_A > for bool { # [inline (always)]
fn from (variant : STATMODE_BANK2TRDY_A) -> Self { variant as u8 != 0 } } impl STATMODE_BANK2TRDY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATMODE_BANK2TRDY_A { match self . bits { false => STATMODE_BANK2TRDY_A :: STATMODE_BANK2TRDY_FALSE , true => STATMODE_BANK2TRDY_A :: STATMODE_BANK2TRDY_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_statmode_bank2trdy_false (& self) -> bool { * self == STATMODE_BANK2TRDY_A :: STATMODE_BANK2TRDY_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_statmode_bank2trdy_true (& self) -> bool { * self == STATMODE_BANK2TRDY_A :: STATMODE_BANK2TRDY_TRUE } } # [doc = "Field `STATMODE_BANK1TRDY` reader - Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed."]
pub type STATMODE_BANK1TRDY_R = crate :: BitReader < STATMODE_BANK1TRDY_A > ; # [doc = "Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATMODE_BANK1TRDY_A { # [doc = "0: FALSE"]
STATMODE_BANK1TRDY_FALSE = 0 , # [doc = "1: TRUE"]
STATMODE_BANK1TRDY_TRUE = 1 , } impl From < STATMODE_BANK1TRDY_A > for bool { # [inline (always)]
fn from (variant : STATMODE_BANK1TRDY_A) -> Self { variant as u8 != 0 } } impl STATMODE_BANK1TRDY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATMODE_BANK1TRDY_A { match self . bits { false => STATMODE_BANK1TRDY_A :: STATMODE_BANK1TRDY_FALSE , true => STATMODE_BANK1TRDY_A :: STATMODE_BANK1TRDY_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_statmode_bank1trdy_false (& self) -> bool { * self == STATMODE_BANK1TRDY_A :: STATMODE_BANK1TRDY_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_statmode_bank1trdy_true (& self) -> bool { * self == STATMODE_BANK1TRDY_A :: STATMODE_BANK1TRDY_TRUE } } impl R { # [doc = "Bit 0 - Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank."]
# [inline (always)]
pub fn statmode_banknotinrd (& self) -> STATMODE_BANKNOTINRD_R { STATMODE_BANKNOTINRD_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 8:11 - Indicates mode of bank(s) that are not in READ mode"]
# [inline (always)]
pub fn statmode_bankmode (& self) -> STATMODE_BANKMODE_R { STATMODE_BANKMODE_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 16 - Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s)."]
# [inline (always)]
pub fn statmode_bank2trdy (& self) -> STATMODE_BANK2TRDY_R { STATMODE_BANK2TRDY_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed."]
# [inline (always)]
pub fn statmode_bank1trdy (& self) -> STATMODE_BANK1TRDY_R { STATMODE_BANK1TRDY_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "Mode Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`statmode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATMODE_SPEC ; impl crate :: RegisterSpec for STATMODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`statmode::R`](R) reader structure"]
impl crate :: Readable for STATMODE_SPEC { } # [doc = "`reset()` method sets STATMODE to value 0"]
impl crate :: Resettable for STATMODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GBLINFO0 (r) register accessor: Global Information Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gblinfo0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gblinfo0`]
module"]
pub type GBLINFO0 = crate :: Reg < gblinfo0 :: GBLINFO0_SPEC > ; # [doc = "Global Information Register 0"]
pub mod gblinfo0 { # [doc = "Register `GBLINFO0` reader"]
pub type R = crate :: R < GBLINFO0_SPEC > ; # [doc = "Field `GBLINFO0_SECTORSIZE` reader - Sector size in bytes"]
pub type GBLINFO0_SECTORSIZE_R = crate :: FieldReader < GBLINFO0_SECTORSIZE_A > ; # [doc = "Sector size in bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u16)]
pub enum GBLINFO0_SECTORSIZE_A { # [doc = "1024: ONEKB"]
GBLINFO0_SECTORSIZE_ONEKB = 1024 , # [doc = "2048: TWOKB"]
GBLINFO0_SECTORSIZE_TWOKB = 2048 , } impl From < GBLINFO0_SECTORSIZE_A > for u16 { # [inline (always)]
fn from (variant : GBLINFO0_SECTORSIZE_A) -> Self { variant as _ } } impl crate :: FieldSpec for GBLINFO0_SECTORSIZE_A { type Ux = u16 ; } impl GBLINFO0_SECTORSIZE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < GBLINFO0_SECTORSIZE_A > { match self . bits { 1024 => Some (GBLINFO0_SECTORSIZE_A :: GBLINFO0_SECTORSIZE_ONEKB) , 2048 => Some (GBLINFO0_SECTORSIZE_A :: GBLINFO0_SECTORSIZE_TWOKB) , _ => None , } } # [doc = "ONEKB"]
# [inline (always)]
pub fn is_gblinfo0_sectorsize_onekb (& self) -> bool { * self == GBLINFO0_SECTORSIZE_A :: GBLINFO0_SECTORSIZE_ONEKB } # [doc = "TWOKB"]
# [inline (always)]
pub fn is_gblinfo0_sectorsize_twokb (& self) -> bool { * self == GBLINFO0_SECTORSIZE_A :: GBLINFO0_SECTORSIZE_TWOKB } } # [doc = "Field `GBLINFO0_NUMBANKS` reader - Number of banks instantiated Minimum: 1 Maximum: 5"]
pub type GBLINFO0_NUMBANKS_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:15 - Sector size in bytes"]
# [inline (always)]
pub fn gblinfo0_sectorsize (& self) -> GBLINFO0_SECTORSIZE_R { GBLINFO0_SECTORSIZE_R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:18 - Number of banks instantiated Minimum: 1 Maximum: 5"]
# [inline (always)]
pub fn gblinfo0_numbanks (& self) -> GBLINFO0_NUMBANKS_R { GBLINFO0_NUMBANKS_R :: new (((self . bits >> 16) & 7) as u8) } } # [doc = "Global Information Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gblinfo0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GBLINFO0_SPEC ; impl crate :: RegisterSpec for GBLINFO0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gblinfo0::R`](R) reader structure"]
impl crate :: Readable for GBLINFO0_SPEC { } # [doc = "`reset()` method sets GBLINFO0 to value 0"]
impl crate :: Resettable for GBLINFO0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GBLINFO1 (r) register accessor: Global Information Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gblinfo1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gblinfo1`]
module"]
pub type GBLINFO1 = crate :: Reg < gblinfo1 :: GBLINFO1_SPEC > ; # [doc = "Global Information Register 1"]
pub mod gblinfo1 { # [doc = "Register `GBLINFO1` reader"]
pub type R = crate :: R < GBLINFO1_SPEC > ; # [doc = "Field `GBLINFO1_DATAWIDTH` reader - Data width in bits"]
pub type GBLINFO1_DATAWIDTH_R = crate :: FieldReader < GBLINFO1_DATAWIDTH_A > ; # [doc = "Data width in bits\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GBLINFO1_DATAWIDTH_A { # [doc = "64: W64BIT"]
GBLINFO1_DATAWIDTH_W64BIT = 64 , # [doc = "128: W128BIT"]
GBLINFO1_DATAWIDTH_W128BIT = 128 , } impl From < GBLINFO1_DATAWIDTH_A > for u8 { # [inline (always)]
fn from (variant : GBLINFO1_DATAWIDTH_A) -> Self { variant as _ } } impl crate :: FieldSpec for GBLINFO1_DATAWIDTH_A { type Ux = u8 ; } impl GBLINFO1_DATAWIDTH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < GBLINFO1_DATAWIDTH_A > { match self . bits { 64 => Some (GBLINFO1_DATAWIDTH_A :: GBLINFO1_DATAWIDTH_W64BIT) , 128 => Some (GBLINFO1_DATAWIDTH_A :: GBLINFO1_DATAWIDTH_W128BIT) , _ => None , } } # [doc = "W64BIT"]
# [inline (always)]
pub fn is_gblinfo1_datawidth_w64bit (& self) -> bool { * self == GBLINFO1_DATAWIDTH_A :: GBLINFO1_DATAWIDTH_W64BIT } # [doc = "W128BIT"]
# [inline (always)]
pub fn is_gblinfo1_datawidth_w128bit (& self) -> bool { * self == GBLINFO1_DATAWIDTH_A :: GBLINFO1_DATAWIDTH_W128BIT } } # [doc = "Field `GBLINFO1_ECCWIDTH` reader - ECC data width in bits"]
pub type GBLINFO1_ECCWIDTH_R = crate :: FieldReader < GBLINFO1_ECCWIDTH_A > ; # [doc = "ECC data width in bits\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GBLINFO1_ECCWIDTH_A { # [doc = "0: W0BIT"]
GBLINFO1_ECCWIDTH_W0BIT = 0 , # [doc = "8: W8BIT"]
GBLINFO1_ECCWIDTH_W8BIT = 8 , # [doc = "16: W16BIT"]
GBLINFO1_ECCWIDTH_W16BIT = 16 , } impl From < GBLINFO1_ECCWIDTH_A > for u8 { # [inline (always)]
fn from (variant : GBLINFO1_ECCWIDTH_A) -> Self { variant as _ } } impl crate :: FieldSpec for GBLINFO1_ECCWIDTH_A { type Ux = u8 ; } impl GBLINFO1_ECCWIDTH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < GBLINFO1_ECCWIDTH_A > { match self . bits { 0 => Some (GBLINFO1_ECCWIDTH_A :: GBLINFO1_ECCWIDTH_W0BIT) , 8 => Some (GBLINFO1_ECCWIDTH_A :: GBLINFO1_ECCWIDTH_W8BIT) , 16 => Some (GBLINFO1_ECCWIDTH_A :: GBLINFO1_ECCWIDTH_W16BIT) , _ => None , } } # [doc = "W0BIT"]
# [inline (always)]
pub fn is_gblinfo1_eccwidth_w0bit (& self) -> bool { * self == GBLINFO1_ECCWIDTH_A :: GBLINFO1_ECCWIDTH_W0BIT } # [doc = "W8BIT"]
# [inline (always)]
pub fn is_gblinfo1_eccwidth_w8bit (& self) -> bool { * self == GBLINFO1_ECCWIDTH_A :: GBLINFO1_ECCWIDTH_W8BIT } # [doc = "W16BIT"]
# [inline (always)]
pub fn is_gblinfo1_eccwidth_w16bit (& self) -> bool { * self == GBLINFO1_ECCWIDTH_A :: GBLINFO1_ECCWIDTH_W16BIT } } # [doc = "Field `GBLINFO1_REDWIDTH` reader - Redundant data width in bits"]
pub type GBLINFO1_REDWIDTH_R = crate :: FieldReader < GBLINFO1_REDWIDTH_A > ; # [doc = "Redundant data width in bits\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GBLINFO1_REDWIDTH_A { # [doc = "0: W0BIT"]
GBLINFO1_REDWIDTH_W0BIT = 0 , # [doc = "2: W2BIT"]
GBLINFO1_REDWIDTH_W2BIT = 2 , # [doc = "4: W4BIT"]
GBLINFO1_REDWIDTH_W4BIT = 4 , } impl From < GBLINFO1_REDWIDTH_A > for u8 { # [inline (always)]
fn from (variant : GBLINFO1_REDWIDTH_A) -> Self { variant as _ } } impl crate :: FieldSpec for GBLINFO1_REDWIDTH_A { type Ux = u8 ; } impl GBLINFO1_REDWIDTH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < GBLINFO1_REDWIDTH_A > { match self . bits { 0 => Some (GBLINFO1_REDWIDTH_A :: GBLINFO1_REDWIDTH_W0BIT) , 2 => Some (GBLINFO1_REDWIDTH_A :: GBLINFO1_REDWIDTH_W2BIT) , 4 => Some (GBLINFO1_REDWIDTH_A :: GBLINFO1_REDWIDTH_W4BIT) , _ => None , } } # [doc = "W0BIT"]
# [inline (always)]
pub fn is_gblinfo1_redwidth_w0bit (& self) -> bool { * self == GBLINFO1_REDWIDTH_A :: GBLINFO1_REDWIDTH_W0BIT } # [doc = "W2BIT"]
# [inline (always)]
pub fn is_gblinfo1_redwidth_w2bit (& self) -> bool { * self == GBLINFO1_REDWIDTH_A :: GBLINFO1_REDWIDTH_W2BIT } # [doc = "W4BIT"]
# [inline (always)]
pub fn is_gblinfo1_redwidth_w4bit (& self) -> bool { * self == GBLINFO1_REDWIDTH_A :: GBLINFO1_REDWIDTH_W4BIT } } impl R { # [doc = "Bits 0:7 - Data width in bits"]
# [inline (always)]
pub fn gblinfo1_datawidth (& self) -> GBLINFO1_DATAWIDTH_R { GBLINFO1_DATAWIDTH_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:12 - ECC data width in bits"]
# [inline (always)]
pub fn gblinfo1_eccwidth (& self) -> GBLINFO1_ECCWIDTH_R { GBLINFO1_ECCWIDTH_R :: new (((self . bits >> 8) & 0x1f) as u8) } # [doc = "Bits 16:18 - Redundant data width in bits"]
# [inline (always)]
pub fn gblinfo1_redwidth (& self) -> GBLINFO1_REDWIDTH_R { GBLINFO1_REDWIDTH_R :: new (((self . bits >> 16) & 7) as u8) } } # [doc = "Global Information Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gblinfo1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GBLINFO1_SPEC ; impl crate :: RegisterSpec for GBLINFO1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gblinfo1::R`](R) reader structure"]
impl crate :: Readable for GBLINFO1_SPEC { } # [doc = "`reset()` method sets GBLINFO1 to value 0"]
impl crate :: Resettable for GBLINFO1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GBLINFO2 (r) register accessor: Global Information Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gblinfo2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gblinfo2`]
module"]
pub type GBLINFO2 = crate :: Reg < gblinfo2 :: GBLINFO2_SPEC > ; # [doc = "Global Information Register 2"]
pub mod gblinfo2 { # [doc = "Register `GBLINFO2` reader"]
pub type R = crate :: R < GBLINFO2_SPEC > ; # [doc = "Field `GBLINFO2_DATAREGISTERS` reader - Number of data registers present."]
pub type GBLINFO2_DATAREGISTERS_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:3 - Number of data registers present."]
# [inline (always)]
pub fn gblinfo2_dataregisters (& self) -> GBLINFO2_DATAREGISTERS_R { GBLINFO2_DATAREGISTERS_R :: new ((self . bits & 0x0f) as u8) } } # [doc = "Global Information Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gblinfo2::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GBLINFO2_SPEC ; impl crate :: RegisterSpec for GBLINFO2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gblinfo2::R`](R) reader structure"]
impl crate :: Readable for GBLINFO2_SPEC { } # [doc = "`reset()` method sets GBLINFO2 to value 0"]
impl crate :: Resettable for GBLINFO2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "BANK0INFO0 (r) register accessor: Bank Information Register 0 for Bank 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bank0info0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bank0info0`]
module"]
pub type BANK0INFO0 = crate :: Reg < bank0info0 :: BANK0INFO0_SPEC > ; # [doc = "Bank Information Register 0 for Bank 0"]
pub mod bank0info0 { # [doc = "Register `BANK0INFO0` reader"]
pub type R = crate :: R < BANK0INFO0_SPEC > ; # [doc = "Field `BANK0INFO0_MAINSIZE` reader - Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)"]
pub type BANK0INFO0_MAINSIZE_R = crate :: FieldReader < BANK0INFO0_MAINSIZE_A > ; # [doc = "Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u16)]
pub enum BANK0INFO0_MAINSIZE_A { # [doc = "8: MINSECTORS"]
BANK0INFO0_MAINSIZE_MINSECTORS = 8 , # [doc = "512: MAXSECTORS"]
BANK0INFO0_MAINSIZE_MAXSECTORS = 512 , } impl From < BANK0INFO0_MAINSIZE_A > for u16 { # [inline (always)]
fn from (variant : BANK0INFO0_MAINSIZE_A) -> Self { variant as _ } } impl crate :: FieldSpec for BANK0INFO0_MAINSIZE_A { type Ux = u16 ; } impl BANK0INFO0_MAINSIZE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < BANK0INFO0_MAINSIZE_A > { match self . bits { 8 => Some (BANK0INFO0_MAINSIZE_A :: BANK0INFO0_MAINSIZE_MINSECTORS) , 512 => Some (BANK0INFO0_MAINSIZE_A :: BANK0INFO0_MAINSIZE_MAXSECTORS) , _ => None , } } # [doc = "MINSECTORS"]
# [inline (always)]
pub fn is_bank0info0_mainsize_minsectors (& self) -> bool { * self == BANK0INFO0_MAINSIZE_A :: BANK0INFO0_MAINSIZE_MINSECTORS } # [doc = "MAXSECTORS"]
# [inline (always)]
pub fn is_bank0info0_mainsize_maxsectors (& self) -> bool { * self == BANK0INFO0_MAINSIZE_A :: BANK0INFO0_MAINSIZE_MAXSECTORS } } impl R { # [doc = "Bits 0:11 - Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)"]
# [inline (always)]
pub fn bank0info0_mainsize (& self) -> BANK0INFO0_MAINSIZE_R { BANK0INFO0_MAINSIZE_R :: new ((self . bits & 0x0fff) as u16) } } # [doc = "Bank Information Register 0 for Bank 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bank0info0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BANK0INFO0_SPEC ; impl crate :: RegisterSpec for BANK0INFO0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`bank0info0::R`](R) reader structure"]
impl crate :: Readable for BANK0INFO0_SPEC { } # [doc = "`reset()` method sets BANK0INFO0 to value 0"]
impl crate :: Resettable for BANK0INFO0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "BANK0INFO1 (r) register accessor: Bank Information Register 1 for Bank 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bank0info1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@bank0info1`]
module"]
pub type BANK0INFO1 = crate :: Reg < bank0info1 :: BANK0INFO1_SPEC > ; # [doc = "Bank Information Register 1 for Bank 0"]
pub mod bank0info1 { # [doc = "Register `BANK0INFO1` reader"]
pub type R = crate :: R < BANK0INFO1_SPEC > ; # [doc = "Field `BANK0INFO1_NONMAINSIZE` reader - Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)"]
pub type BANK0INFO1_NONMAINSIZE_R = crate :: FieldReader < BANK0INFO1_NONMAINSIZE_A > ; # [doc = "Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum BANK0INFO1_NONMAINSIZE_A { # [doc = "0: MINSECTORS"]
BANK0INFO1_NONMAINSIZE_MINSECTORS = 0 , # [doc = "32: MAXSECTORS"]
BANK0INFO1_NONMAINSIZE_MAXSECTORS = 32 , } impl From < BANK0INFO1_NONMAINSIZE_A > for u8 { # [inline (always)]
fn from (variant : BANK0INFO1_NONMAINSIZE_A) -> Self { variant as _ } } impl crate :: FieldSpec for BANK0INFO1_NONMAINSIZE_A { type Ux = u8 ; } impl BANK0INFO1_NONMAINSIZE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < BANK0INFO1_NONMAINSIZE_A > { match self . bits { 0 => Some (BANK0INFO1_NONMAINSIZE_A :: BANK0INFO1_NONMAINSIZE_MINSECTORS) , 32 => Some (BANK0INFO1_NONMAINSIZE_A :: BANK0INFO1_NONMAINSIZE_MAXSECTORS) , _ => None , } } # [doc = "MINSECTORS"]
# [inline (always)]
pub fn is_bank0info1_nonmainsize_minsectors (& self) -> bool { * self == BANK0INFO1_NONMAINSIZE_A :: BANK0INFO1_NONMAINSIZE_MINSECTORS } # [doc = "MAXSECTORS"]
# [inline (always)]
pub fn is_bank0info1_nonmainsize_maxsectors (& self) -> bool { * self == BANK0INFO1_NONMAINSIZE_A :: BANK0INFO1_NONMAINSIZE_MAXSECTORS } } # [doc = "Field `BANK0INFO1_TRIMSIZE` reader - Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)"]
pub type BANK0INFO1_TRIMSIZE_R = crate :: FieldReader < BANK0INFO1_TRIMSIZE_A > ; # [doc = "Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum BANK0INFO1_TRIMSIZE_A { # [doc = "0: MINSECTORS"]
BANK0INFO1_TRIMSIZE_MINSECTORS = 0 , # [doc = "32: MAXSECTORS"]
BANK0INFO1_TRIMSIZE_MAXSECTORS = 32 , } impl From < BANK0INFO1_TRIMSIZE_A > for u8 { # [inline (always)]
fn from (variant : BANK0INFO1_TRIMSIZE_A) -> Self { variant as _ } } impl crate :: FieldSpec for BANK0INFO1_TRIMSIZE_A { type Ux = u8 ; } impl BANK0INFO1_TRIMSIZE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < BANK0INFO1_TRIMSIZE_A > { match self . bits { 0 => Some (BANK0INFO1_TRIMSIZE_A :: BANK0INFO1_TRIMSIZE_MINSECTORS) , 32 => Some (BANK0INFO1_TRIMSIZE_A :: BANK0INFO1_TRIMSIZE_MAXSECTORS) , _ => None , } } # [doc = "MINSECTORS"]
# [inline (always)]
pub fn is_bank0info1_trimsize_minsectors (& self) -> bool { * self == BANK0INFO1_TRIMSIZE_A :: BANK0INFO1_TRIMSIZE_MINSECTORS } # [doc = "MAXSECTORS"]
# [inline (always)]
pub fn is_bank0info1_trimsize_maxsectors (& self) -> bool { * self == BANK0INFO1_TRIMSIZE_A :: BANK0INFO1_TRIMSIZE_MAXSECTORS } } # [doc = "Field `BANK0INFO1_ENGRSIZE` reader - Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)"]
pub type BANK0INFO1_ENGRSIZE_R = crate :: FieldReader < BANK0INFO1_ENGRSIZE_A > ; # [doc = "Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum BANK0INFO1_ENGRSIZE_A { # [doc = "0: MINSECTORS"]
BANK0INFO1_ENGRSIZE_MINSECTORS = 0 , # [doc = "32: MAXSECTORS"]
BANK0INFO1_ENGRSIZE_MAXSECTORS = 32 , } impl From < BANK0INFO1_ENGRSIZE_A > for u8 { # [inline (always)]
fn from (variant : BANK0INFO1_ENGRSIZE_A) -> Self { variant as _ } } impl crate :: FieldSpec for BANK0INFO1_ENGRSIZE_A { type Ux = u8 ; } impl BANK0INFO1_ENGRSIZE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < BANK0INFO1_ENGRSIZE_A > { match self . bits { 0 => Some (BANK0INFO1_ENGRSIZE_A :: BANK0INFO1_ENGRSIZE_MINSECTORS) , 32 => Some (BANK0INFO1_ENGRSIZE_A :: BANK0INFO1_ENGRSIZE_MAXSECTORS) , _ => None , } } # [doc = "MINSECTORS"]
# [inline (always)]
pub fn is_bank0info1_engrsize_minsectors (& self) -> bool { * self == BANK0INFO1_ENGRSIZE_A :: BANK0INFO1_ENGRSIZE_MINSECTORS } # [doc = "MAXSECTORS"]
# [inline (always)]
pub fn is_bank0info1_engrsize_maxsectors (& self) -> bool { * self == BANK0INFO1_ENGRSIZE_A :: BANK0INFO1_ENGRSIZE_MAXSECTORS } } impl R { # [doc = "Bits 0:7 - Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)"]
# [inline (always)]
pub fn bank0info1_nonmainsize (& self) -> BANK0INFO1_NONMAINSIZE_R { BANK0INFO1_NONMAINSIZE_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 8:15 - Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)"]
# [inline (always)]
pub fn bank0info1_trimsize (& self) -> BANK0INFO1_TRIMSIZE_R { BANK0INFO1_TRIMSIZE_R :: new (((self . bits >> 8) & 0xff) as u8) } # [doc = "Bits 16:23 - Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)"]
# [inline (always)]
pub fn bank0info1_engrsize (& self) -> BANK0INFO1_ENGRSIZE_R { BANK0INFO1_ENGRSIZE_R :: new (((self . bits >> 16) & 0xff) as u8) } } # [doc = "Bank Information Register 1 for Bank 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bank0info1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BANK0INFO1_SPEC ; impl crate :: RegisterSpec for BANK0INFO1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`bank0info1::R`](R) reader structure"]
impl crate :: Readable for BANK0INFO1_SPEC { } # [doc = "`reset()` method sets BANK0INFO1 to value 0"]
impl crate :: Resettable for BANK0INFO1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct SPI0 { _marker : PhantomData < * const () > } unsafe impl Send for SPI0 { } impl SPI0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const spi0 :: RegisterBlock = 0x4046_8000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const spi0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for SPI0 { type Target = spi0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for SPI0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("SPI0") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod spi0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , # [doc = "0x808 - Peripheral Clock Configuration Register"]
pub clkcfg : CLKCFG , _reserved3 : [u8 ; 0x08]
, # [doc = "0x814 - Status Register"]
pub gprcm_stat : GPRCM_STAT , _reserved4 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , # [doc = "0x1004 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved6 : [u8 ; 0x10]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt Index Register"]
pub int_event0_iidx : INT_EVENT0_IIDX , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub int_event0_imask : INT_EVENT0_IMASK , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub int_event0_ris : INT_EVENT0_RIS , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub int_event0_mis : INT_EVENT0_MIS , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub int_event0_iset : INT_EVENT0_ISET , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub int_event0_iclr : INT_EVENT0_ICLR , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1050 - Interrupt Index Register"]
pub int_event1_iidx : INT_EVENT1_IIDX , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1058 - Interrupt mask"]
pub int_event1_imask : INT_EVENT1_IMASK , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1060 - Raw interrupt status"]
pub int_event1_ris : INT_EVENT1_RIS , _reserved16 : [u8 ; 0x04]
, # [doc = "0x1068 - Masked interrupt status"]
pub int_event1_mis : INT_EVENT1_MIS , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1070 - Interrupt set"]
pub int_event1_iset : INT_EVENT1_ISET , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1078 - Interrupt clear"]
pub int_event1_iclr : INT_EVENT1_ICLR , _reserved19 : [u8 ; 0x04]
, # [doc = "0x1080 - Interrupt Index Register"]
pub int_event2_iidx : INT_EVENT2_IIDX , _reserved20 : [u8 ; 0x04]
, # [doc = "0x1088 - Interrupt mask"]
pub int_event2_imask : INT_EVENT2_IMASK , _reserved21 : [u8 ; 0x04]
, # [doc = "0x1090 - Raw interrupt status"]
pub int_event2_ris : INT_EVENT2_RIS , _reserved22 : [u8 ; 0x04]
, # [doc = "0x1098 - Masked interrupt status"]
pub int_event2_mis : INT_EVENT2_MIS , _reserved23 : [u8 ; 0x04]
, # [doc = "0x10a0 - Interrupt set"]
pub int_event2_iset : INT_EVENT2_ISET , _reserved24 : [u8 ; 0x04]
, # [doc = "0x10a8 - Interrupt clear"]
pub int_event2_iclr : INT_EVENT2_ICLR , _reserved25 : [u8 ; 0x34]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved26 : [u8 ; 0x1c]
, # [doc = "0x1100 - SPI control register 0"]
pub ctl0 : CTL0 , # [doc = "0x1104 - SPI control register 1"]
pub ctl1 : CTL1 , # [doc = "0x1108 - Clock prescaler and divider register."]
pub clkctl : CLKCTL , # [doc = "0x110c - UART Interrupt FIFO Level Select Register"]
pub ifls : IFLS , # [doc = "0x1110 - Status Register"]
pub stat : STAT , _reserved31 : [u8 ; 0x1c]
, # [doc = "0x1130 - RXDATA Register"]
pub rxdata : RXDATA , _reserved32 : [u8 ; 0x0c]
, # [doc = "0x1140 - TXDATA Register"]
pub txdata : TXDATA , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKCFG (rw) register accessor: Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkcfg`]
module"]
pub type CLKCFG = crate :: Reg < clkcfg :: CLKCFG_SPEC > ; # [doc = "Peripheral Clock Configuration Register"]
pub mod clkcfg { # [doc = "Register `CLKCFG` reader"]
pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"]
pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"]
CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"]
CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"]
pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"]
# [inline (always)]
pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
# [must_use]
pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"]
# [inline (always)]
# [must_use]
pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"]
impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"]
impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"]
impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GPRCM_STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gprcm_stat`]
module"]
pub type GPRCM_STAT = crate :: Reg < gprcm_stat :: GPRCM_STAT_SPEC > ; # [doc = "Status Register"]
pub mod gprcm_stat { # [doc = "Register `GPRCM_STAT` reader"]
pub type R = crate :: R < GPRCM_STAT_SPEC > ; # [doc = "Field `GPRCM_STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type GPRCM_STAT_RESETSTKY_R = crate :: BitReader < GPRCM_STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GPRCM_STAT_RESETSTKY_A { # [doc = "0: NORES"]
GPRCM_STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
GPRCM_STAT_RESETSTKY_RESET = 1 , } impl From < GPRCM_STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : GPRCM_STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl GPRCM_STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GPRCM_STAT_RESETSTKY_A { match self . bits { false => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES , true => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_nores (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_reset (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn gprcm_stat_resetstky (& self) -> GPRCM_STAT_RESETSTKY_R { GPRCM_STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GPRCM_STAT_SPEC ; impl crate :: RegisterSpec for GPRCM_STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gprcm_stat::R`](R) reader structure"]
impl crate :: Readable for GPRCM_STAT_SPEC { } # [doc = "`reset()` method sets GPRCM_STAT to value 0"]
impl crate :: Resettable for GPRCM_STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_SYSCLK_SEL` reader - Selects SYSCLK as clock source if enabled"]
pub type CLKSEL_SYSCLK_SEL_R = crate :: BitReader < CLKSEL_SYSCLK_SEL_A > ; # [doc = "Selects SYSCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_SYSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_SYSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_SYSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_SYSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_SYSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_SYSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_SYSCLK_SEL_A { match self . bits { false => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE , true => CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_sysclk_sel_disable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_sysclk_sel_enable (& self) -> bool { * self == CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_SYSCLK_SEL` writer - Selects SYSCLK as clock source if enabled"]
pub type CLKSEL_SYSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_SYSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_SYSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_sysclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_sysclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_SYSCLK_SEL_A :: CLKSEL_SYSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_sysclk_sel (& self) -> CLKSEL_SYSCLK_SEL_R { CLKSEL_SYSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects SYSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_sysclk_sel (& mut self) -> CLKSEL_SYSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_SYSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IIDX (r) register accessor: Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iidx`]
module"]
pub type INT_EVENT0_IIDX = crate :: Reg < int_event0_iidx :: INT_EVENT0_IIDX_SPEC > ; # [doc = "Interrupt Index Register"]
pub mod int_event0_iidx { # [doc = "Register `INT_EVENT0_IIDX` reader"]
pub type R = crate :: R < INT_EVENT0_IIDX_SPEC > ; # [doc = "Field `INT_EVENT0_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT0_IIDX_STAT_R = crate :: FieldReader < INT_EVENT0_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: RXFIFO_OFV_EVT"]
INT_EVENT0_IIDX_STAT_RXFIFO_OFV_EVT = 1 , # [doc = "2: PER_EVT"]
INT_EVENT0_IIDX_STAT_PER_EVT = 2 , # [doc = "3: RTOUT_EVT"]
INT_EVENT0_IIDX_STAT_RTOUT_EVT = 3 , # [doc = "4: RX_EVT"]
INT_EVENT0_IIDX_STAT_RX_EVT = 4 , # [doc = "5: TX_EVT"]
INT_EVENT0_IIDX_STAT_TX_EVT = 5 , # [doc = "6: TX_EMPTY"]
INT_EVENT0_IIDX_STAT_TX_EMPTY = 6 , # [doc = "7: IDLE_EVT"]
INT_EVENT0_IIDX_STAT_IDLE_EVT = 7 , # [doc = "8: DMA_DONE_RX_EVT"]
INT_EVENT0_IIDX_STAT_DMA_DONE_RX_EVT = 8 , # [doc = "9: DMA_DONE_TX_EVT"]
INT_EVENT0_IIDX_STAT_DMA_DONE_TX_EVT = 9 , # [doc = "10: TXFIFO_UNF_EVT"]
INT_EVENT0_IIDX_STAT_TXFIFO_UNF_EVT = 10 , # [doc = "11: RXFULL_EVT"]
INT_EVENT0_IIDX_STAT_RXFULL_EVT = 11 , } impl From < INT_EVENT0_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT0_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXFIFO_OFV_EVT) , 2 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_PER_EVT) , 3 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RTOUT_EVT) , 4 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RX_EVT) , 5 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TX_EVT) , 6 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TX_EMPTY) , 7 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_IDLE_EVT) , 8 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_RX_EVT) , 9 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_TX_EVT) , 10 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TXFIFO_UNF_EVT) , 11 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXFULL_EVT) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR } # [doc = "RXFIFO_OFV_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxfifo_ofv_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXFIFO_OFV_EVT } # [doc = "PER_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_per_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_PER_EVT } # [doc = "RTOUT_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rtout_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RTOUT_EVT } # [doc = "RX_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rx_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RX_EVT } # [doc = "TX_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_tx_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TX_EVT } # [doc = "TX_EMPTY"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_tx_empty (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TX_EMPTY } # [doc = "IDLE_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_idle_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_IDLE_EVT } # [doc = "DMA_DONE_RX_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dma_done_rx_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_RX_EVT } # [doc = "DMA_DONE_TX_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dma_done_tx_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_TX_EVT } # [doc = "TXFIFO_UNF_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_txfifo_unf_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TXFIFO_UNF_EVT } # [doc = "RXFULL_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxfull_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXFULL_EVT } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_event0_iidx_stat (& self) -> INT_EVENT0_IIDX_STAT_R { INT_EVENT0_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_imask`]
module"]
pub type INT_EVENT0_IMASK = crate :: Reg < int_event0_imask :: INT_EVENT0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event0_imask { # [doc = "Register `INT_EVENT0_IMASK` reader"]
pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"]
pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` reader - RXFIFO overflow event mask."]
pub type INT_EVENT0_IMASK_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_IMASK_RXFIFO_OVF_A > ; # [doc = "RXFIFO overflow event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXFIFO_OVF_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFIFO_OVF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR , true => INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFIFO_OVF` writer - RXFIFO overflow event mask."]
pub type INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFIFO_OVF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxfifo_ovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxfifo_ovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFIFO_OVF_A :: INT_EVENT0_IMASK_RXFIFO_OVF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PER` reader - Parity error event mask."]
pub type INT_EVENT0_IMASK_PER_R = crate :: BitReader < INT_EVENT0_IMASK_PER_A > ; # [doc = "Parity error event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_PER_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_PER_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_PER_SET = 1 , } impl From < INT_EVENT0_IMASK_PER_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PER_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_PER_A { match self . bits { false => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR , true => INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_per_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_per_set (& self) -> bool { * self == INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET } } # [doc = "Field `INT_EVENT0_IMASK_PER` writer - Parity error event mask."]
pub type INT_EVENT0_IMASK_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PER_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_per_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_per_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PER_A :: INT_EVENT0_IMASK_PER_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable SPI Receive Time-Out event mask."]
pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable SPI Receive Time-Out event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable SPI Receive Time-Out event mask."]
pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
pub type INT_EVENT0_IMASK_RX_R = crate :: BitReader < INT_EVENT0_IMASK_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RX_A { match self . bits { false => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR , true => INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_RX` writer - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
pub type INT_EVENT0_IMASK_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RX_A :: INT_EVENT0_IMASK_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TX` reader - Transmit FIFO event mask."]
pub type INT_EVENT0_IMASK_TX_R = crate :: BitReader < INT_EVENT0_IMASK_TX_A > ; # [doc = "Transmit FIFO event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TX_A { match self . bits { false => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR , true => INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_TX` writer - Transmit FIFO event mask."]
pub type INT_EVENT0_IMASK_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TX_A :: INT_EVENT0_IMASK_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` reader - Transmit FIFO Empty event mask."]
pub type INT_EVENT0_IMASK_TXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_TXEMPTY_A > ; # [doc = "Transmit FIFO Empty event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_TXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR , true => INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_txempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_txempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXEMPTY` writer - Transmit FIFO Empty event mask."]
pub type INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_txempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_txempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXEMPTY_A :: INT_EVENT0_IMASK_TXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` reader - SPI Idle event mask."]
pub type INT_EVENT0_IMASK_IDLE_R = crate :: BitReader < INT_EVENT0_IMASK_IDLE_A > ; # [doc = "SPI Idle event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_IDLE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_IDLE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_IDLE_SET = 1 , } impl From < INT_EVENT0_IMASK_IDLE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_IDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_IDLE_A { match self . bits { false => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR , true => INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_idle_clr (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_idle_set (& self) -> bool { * self == INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET } } # [doc = "Field `INT_EVENT0_IMASK_IDLE` writer - SPI Idle event mask."]
pub type INT_EVENT0_IMASK_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_IDLE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_idle_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_idle_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_IDLE_A :: INT_EVENT0_IMASK_IDLE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - DMA Done 1 event for RX event mask."]
pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "DMA Done 1 event for RX event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - DMA Done 1 event for RX event mask."]
pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - DMA Done 1 event for TX event mask."]
pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "DMA Done 1 event for TX event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - DMA Done 1 event for TX event mask."]
pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` reader - TX FIFO underflow interrupt mask"]
pub type INT_EVENT0_IMASK_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_IMASK_TXFIFO_UNF_A > ; # [doc = "TX FIFO underflow interrupt mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TXFIFO_UNF_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_IMASK_TXFIFO_UNF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR , true => INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXFIFO_UNF` writer - TX FIFO underflow interrupt mask"]
pub type INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXFIFO_UNF_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_txfifo_unf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_txfifo_unf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXFIFO_UNF_A :: INT_EVENT0_IMASK_TXFIFO_UNF_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` reader - RX FIFO Full Interrupt Mask"]
pub type INT_EVENT0_IMASK_RXFULL_R = crate :: BitReader < INT_EVENT0_IMASK_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt Mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXFULL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_RXFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXFULL_A { match self . bits { false => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR , true => INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxfull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxfull_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXFULL` writer - RX FIFO Full Interrupt Mask"]
pub type INT_EVENT0_IMASK_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxfull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxfull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXFULL_A :: INT_EVENT0_IMASK_RXFULL_SET) } } impl R { # [doc = "Bit 0 - RXFIFO overflow event mask."]
# [inline (always)]
pub fn int_event0_imask_rxfifo_ovf (& self) -> INT_EVENT0_IMASK_RXFIFO_OVF_R { INT_EVENT0_IMASK_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Parity error event mask."]
# [inline (always)]
pub fn int_event0_imask_per (& self) -> INT_EVENT0_IMASK_PER_R { INT_EVENT0_IMASK_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."]
# [inline (always)]
pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
# [inline (always)]
pub fn int_event0_imask_rx (& self) -> INT_EVENT0_IMASK_RX_R { INT_EVENT0_IMASK_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transmit FIFO event mask."]
# [inline (always)]
pub fn int_event0_imask_tx (& self) -> INT_EVENT0_IMASK_TX_R { INT_EVENT0_IMASK_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."]
# [inline (always)]
pub fn int_event0_imask_txempty (& self) -> INT_EVENT0_IMASK_TXEMPTY_R { INT_EVENT0_IMASK_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SPI Idle event mask."]
# [inline (always)]
pub fn int_event0_imask_idle (& self) -> INT_EVENT0_IMASK_IDLE_R { INT_EVENT0_IMASK_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"]
# [inline (always)]
pub fn int_event0_imask_txfifo_unf (& self) -> INT_EVENT0_IMASK_TXFIFO_UNF_R { INT_EVENT0_IMASK_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"]
# [inline (always)]
pub fn int_event0_imask_rxfull (& self) -> INT_EVENT0_IMASK_RXFULL_R { INT_EVENT0_IMASK_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - RXFIFO overflow event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxfifo_ovf (& mut self) -> INT_EVENT0_IMASK_RXFIFO_OVF_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Parity error event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_per (& mut self) -> INT_EVENT0_IMASK_PER_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_PER_W :: new (self) } # [doc = "Bit 2 - Enable SPI Receive Time-Out event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rx (& mut self) -> INT_EVENT0_IMASK_RX_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_RX_W :: new (self) } # [doc = "Bit 4 - Transmit FIFO event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_tx (& mut self) -> INT_EVENT0_IMASK_TX_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_TX_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_txempty (& mut self) -> INT_EVENT0_IMASK_TXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - SPI Idle event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_idle (& mut self) -> INT_EVENT0_IMASK_IDLE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_IDLE_W :: new (self) } # [doc = "Bit 7 - DMA Done 1 event for RX event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - DMA Done 1 event for TX event mask."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - TX FIFO underflow interrupt mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_txfifo_unf (& mut self) -> INT_EVENT0_IMASK_TXFIFO_UNF_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - RX FIFO Full Interrupt Mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxfull (& mut self) -> INT_EVENT0_IMASK_RXFULL_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_ris`]
module"]
pub type INT_EVENT0_RIS = crate :: Reg < int_event0_ris :: INT_EVENT0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event0_ris { # [doc = "Register `INT_EVENT0_RIS` reader"]
pub type R = crate :: R < INT_EVENT0_RIS_SPEC > ; # [doc = "Field `INT_EVENT0_RIS_RXFIFO_OVF` reader - RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected."]
pub type INT_EVENT0_RIS_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_RIS_RXFIFO_OVF_A > ; # [doc = "RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXFIFO_OVF_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_RIS_RXFIFO_OVF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_RIS_RXFIFO_OVF_A :: INT_EVENT0_RIS_RXFIFO_OVF_CLR , true => INT_EVENT0_RIS_RXFIFO_OVF_A :: INT_EVENT0_RIS_RXFIFO_OVF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXFIFO_OVF_A :: INT_EVENT0_RIS_RXFIFO_OVF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_RIS_RXFIFO_OVF_A :: INT_EVENT0_RIS_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_RIS_PER` reader - Parity error event: this bit is set if a Parity error has been detected"]
pub type INT_EVENT0_RIS_PER_R = crate :: BitReader < INT_EVENT0_RIS_PER_A > ; # [doc = "Parity error event: this bit is set if a Parity error has been detected\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_PER_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_PER_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_PER_SET = 1 , } impl From < INT_EVENT0_RIS_PER_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_PER_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_PER_A { match self . bits { false => INT_EVENT0_RIS_PER_A :: INT_EVENT0_RIS_PER_CLR , true => INT_EVENT0_RIS_PER_A :: INT_EVENT0_RIS_PER_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_per_clr (& self) -> bool { * self == INT_EVENT0_RIS_PER_A :: INT_EVENT0_RIS_PER_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_per_set (& self) -> bool { * self == INT_EVENT0_RIS_PER_A :: INT_EVENT0_RIS_PER_SET } } # [doc = "Field `INT_EVENT0_RIS_RTOUT` reader - SPI Receive Time-Out event."]
pub type INT_EVENT0_RIS_RTOUT_R = crate :: BitReader < INT_EVENT0_RIS_RTOUT_A > ; # [doc = "SPI Receive Time-Out event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RTOUT_SET = 1 , } impl From < INT_EVENT0_RIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RTOUT_A { match self . bits { false => INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_CLR , true => INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rtout_clr (& self) -> bool { * self == INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rtout_set (& self) -> bool { * self == INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_SET } } # [doc = "Field `INT_EVENT0_RIS_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
pub type INT_EVENT0_RIS_RX_R = crate :: BitReader < INT_EVENT0_RIS_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RX_SET = 1 , } impl From < INT_EVENT0_RIS_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RX_A { match self . bits { false => INT_EVENT0_RIS_RX_A :: INT_EVENT0_RIS_RX_CLR , true => INT_EVENT0_RIS_RX_A :: INT_EVENT0_RIS_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rx_clr (& self) -> bool { * self == INT_EVENT0_RIS_RX_A :: INT_EVENT0_RIS_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rx_set (& self) -> bool { * self == INT_EVENT0_RIS_RX_A :: INT_EVENT0_RIS_RX_SET } } # [doc = "Field `INT_EVENT0_RIS_TX` reader - Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached."]
pub type INT_EVENT0_RIS_TX_R = crate :: BitReader < INT_EVENT0_RIS_TX_A > ; # [doc = "Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TX_SET = 1 , } impl From < INT_EVENT0_RIS_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TX_A { match self . bits { false => INT_EVENT0_RIS_TX_A :: INT_EVENT0_RIS_TX_CLR , true => INT_EVENT0_RIS_TX_A :: INT_EVENT0_RIS_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_tx_clr (& self) -> bool { * self == INT_EVENT0_RIS_TX_A :: INT_EVENT0_RIS_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_tx_set (& self) -> bool { * self == INT_EVENT0_RIS_TX_A :: INT_EVENT0_RIS_TX_SET } } # [doc = "Field `INT_EVENT0_RIS_TXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register."]
pub type INT_EVENT0_RIS_TXEMPTY_R = crate :: BitReader < INT_EVENT0_RIS_TXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_RIS_TXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TXEMPTY_A { match self . bits { false => INT_EVENT0_RIS_TXEMPTY_A :: INT_EVENT0_RIS_TXEMPTY_CLR , true => INT_EVENT0_RIS_TXEMPTY_A :: INT_EVENT0_RIS_TXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_txempty_clr (& self) -> bool { * self == INT_EVENT0_RIS_TXEMPTY_A :: INT_EVENT0_RIS_TXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_txempty_set (& self) -> bool { * self == INT_EVENT0_RIS_TXEMPTY_A :: INT_EVENT0_RIS_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_RIS_IDLE` reader - SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low."]
pub type INT_EVENT0_RIS_IDLE_R = crate :: BitReader < INT_EVENT0_RIS_IDLE_A > ; # [doc = "SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_IDLE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_IDLE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_IDLE_SET = 1 , } impl From < INT_EVENT0_RIS_IDLE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_IDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_IDLE_A { match self . bits { false => INT_EVENT0_RIS_IDLE_A :: INT_EVENT0_RIS_IDLE_CLR , true => INT_EVENT0_RIS_IDLE_A :: INT_EVENT0_RIS_IDLE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_idle_clr (& self) -> bool { * self == INT_EVENT0_RIS_IDLE_A :: INT_EVENT0_RIS_IDLE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_idle_set (& self) -> bool { * self == INT_EVENT0_RIS_IDLE_A :: INT_EVENT0_RIS_IDLE_SET } } # [doc = "Field `INT_EVENT0_RIS_DMA_DONE_RX` reader - DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral."]
pub type INT_EVENT0_RIS_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_RIS_DMA_DONE_RX_A > ; # [doc = "DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_RIS_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_CLR , true => INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_RIS_DMA_DONE_TX` reader - DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral."]
pub type INT_EVENT0_RIS_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_RIS_DMA_DONE_TX_A > ; # [doc = "DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_RIS_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_CLR , true => INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_RIS_TXFIFO_UNF` reader - TX FIFO Underflow Interrupt"]
pub type INT_EVENT0_RIS_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_RIS_TXFIFO_UNF_A > ; # [doc = "TX FIFO Underflow Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TXFIFO_UNF_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_RIS_TXFIFO_UNF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_RIS_TXFIFO_UNF_A :: INT_EVENT0_RIS_TXFIFO_UNF_CLR , true => INT_EVENT0_RIS_TXFIFO_UNF_A :: INT_EVENT0_RIS_TXFIFO_UNF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_RIS_TXFIFO_UNF_A :: INT_EVENT0_RIS_TXFIFO_UNF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_RIS_TXFIFO_UNF_A :: INT_EVENT0_RIS_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_RIS_RXFULL` reader - RX FIFO Full Interrupt"]
pub type INT_EVENT0_RIS_RXFULL_R = crate :: BitReader < INT_EVENT0_RIS_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXFULL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXFULL_SET = 1 , } impl From < INT_EVENT0_RIS_RXFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXFULL_A { match self . bits { false => INT_EVENT0_RIS_RXFULL_A :: INT_EVENT0_RIS_RXFULL_CLR , true => INT_EVENT0_RIS_RXFULL_A :: INT_EVENT0_RIS_RXFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxfull_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXFULL_A :: INT_EVENT0_RIS_RXFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxfull_set (& self) -> bool { * self == INT_EVENT0_RIS_RXFULL_A :: INT_EVENT0_RIS_RXFULL_SET } } impl R { # [doc = "Bit 0 - RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected."]
# [inline (always)]
pub fn int_event0_ris_rxfifo_ovf (& self) -> INT_EVENT0_RIS_RXFIFO_OVF_R { INT_EVENT0_RIS_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Parity error event: this bit is set if a Parity error has been detected"]
# [inline (always)]
pub fn int_event0_ris_per (& self) -> INT_EVENT0_RIS_PER_R { INT_EVENT0_RIS_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - SPI Receive Time-Out event."]
# [inline (always)]
pub fn int_event0_ris_rtout (& self) -> INT_EVENT0_RIS_RTOUT_R { INT_EVENT0_RIS_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
# [inline (always)]
pub fn int_event0_ris_rx (& self) -> INT_EVENT0_RIS_RX_R { INT_EVENT0_RIS_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached."]
# [inline (always)]
pub fn int_event0_ris_tx (& self) -> INT_EVENT0_RIS_TX_R { INT_EVENT0_RIS_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register."]
# [inline (always)]
pub fn int_event0_ris_txempty (& self) -> INT_EVENT0_RIS_TXEMPTY_R { INT_EVENT0_RIS_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low."]
# [inline (always)]
pub fn int_event0_ris_idle (& self) -> INT_EVENT0_RIS_IDLE_R { INT_EVENT0_RIS_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral."]
# [inline (always)]
pub fn int_event0_ris_dma_done_rx (& self) -> INT_EVENT0_RIS_DMA_DONE_RX_R { INT_EVENT0_RIS_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral."]
# [inline (always)]
pub fn int_event0_ris_dma_done_tx (& self) -> INT_EVENT0_RIS_DMA_DONE_TX_R { INT_EVENT0_RIS_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO Underflow Interrupt"]
# [inline (always)]
pub fn int_event0_ris_txfifo_unf (& self) -> INT_EVENT0_RIS_TXFIFO_UNF_R { INT_EVENT0_RIS_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt"]
# [inline (always)]
pub fn int_event0_ris_rxfull (& self) -> INT_EVENT0_RIS_RXFULL_R { INT_EVENT0_RIS_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_RIS to value 0"]
impl crate :: Resettable for INT_EVENT0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_mis`]
module"]
pub type INT_EVENT0_MIS = crate :: Reg < int_event0_mis :: INT_EVENT0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event0_mis { # [doc = "Register `INT_EVENT0_MIS` reader"]
pub type R = crate :: R < INT_EVENT0_MIS_SPEC > ; # [doc = "Field `INT_EVENT0_MIS_RXFIFO_OVF` reader - Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected."]
pub type INT_EVENT0_MIS_RXFIFO_OVF_R = crate :: BitReader < INT_EVENT0_MIS_RXFIFO_OVF_A > ; # [doc = "Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXFIFO_OVF_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXFIFO_OVF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_MIS_RXFIFO_OVF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXFIFO_OVF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXFIFO_OVF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXFIFO_OVF_A { match self . bits { false => INT_EVENT0_MIS_RXFIFO_OVF_A :: INT_EVENT0_MIS_RXFIFO_OVF_CLR , true => INT_EVENT0_MIS_RXFIFO_OVF_A :: INT_EVENT0_MIS_RXFIFO_OVF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxfifo_ovf_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXFIFO_OVF_A :: INT_EVENT0_MIS_RXFIFO_OVF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxfifo_ovf_set (& self) -> bool { * self == INT_EVENT0_MIS_RXFIFO_OVF_A :: INT_EVENT0_MIS_RXFIFO_OVF_SET } } # [doc = "Field `INT_EVENT0_MIS_PER` reader - Masked Parity error event: this bit if a Parity error has been detected"]
pub type INT_EVENT0_MIS_PER_R = crate :: BitReader < INT_EVENT0_MIS_PER_A > ; # [doc = "Masked Parity error event: this bit if a Parity error has been detected\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_PER_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_PER_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_PER_SET = 1 , } impl From < INT_EVENT0_MIS_PER_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_PER_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_PER_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_PER_A { match self . bits { false => INT_EVENT0_MIS_PER_A :: INT_EVENT0_MIS_PER_CLR , true => INT_EVENT0_MIS_PER_A :: INT_EVENT0_MIS_PER_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_per_clr (& self) -> bool { * self == INT_EVENT0_MIS_PER_A :: INT_EVENT0_MIS_PER_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_per_set (& self) -> bool { * self == INT_EVENT0_MIS_PER_A :: INT_EVENT0_MIS_PER_SET } } # [doc = "Field `INT_EVENT0_MIS_RTOUT` reader - Masked SPI Receive Time-Out Interrupt."]
pub type INT_EVENT0_MIS_RTOUT_R = crate :: BitReader < INT_EVENT0_MIS_RTOUT_A > ; # [doc = "Masked SPI Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RTOUT_SET = 1 , } impl From < INT_EVENT0_MIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RTOUT_A { match self . bits { false => INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_CLR , true => INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rtout_clr (& self) -> bool { * self == INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rtout_set (& self) -> bool { * self == INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_SET } } # [doc = "Field `INT_EVENT0_MIS_RX` reader - Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
pub type INT_EVENT0_MIS_RX_R = crate :: BitReader < INT_EVENT0_MIS_RX_A > ; # [doc = "Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RX_SET = 1 , } impl From < INT_EVENT0_MIS_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RX_A { match self . bits { false => INT_EVENT0_MIS_RX_A :: INT_EVENT0_MIS_RX_CLR , true => INT_EVENT0_MIS_RX_A :: INT_EVENT0_MIS_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rx_clr (& self) -> bool { * self == INT_EVENT0_MIS_RX_A :: INT_EVENT0_MIS_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rx_set (& self) -> bool { * self == INT_EVENT0_MIS_RX_A :: INT_EVENT0_MIS_RX_SET } } # [doc = "Field `INT_EVENT0_MIS_TX` reader - Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached."]
pub type INT_EVENT0_MIS_TX_R = crate :: BitReader < INT_EVENT0_MIS_TX_A > ; # [doc = "Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TX_SET = 1 , } impl From < INT_EVENT0_MIS_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TX_A { match self . bits { false => INT_EVENT0_MIS_TX_A :: INT_EVENT0_MIS_TX_CLR , true => INT_EVENT0_MIS_TX_A :: INT_EVENT0_MIS_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_tx_clr (& self) -> bool { * self == INT_EVENT0_MIS_TX_A :: INT_EVENT0_MIS_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_tx_set (& self) -> bool { * self == INT_EVENT0_MIS_TX_A :: INT_EVENT0_MIS_TX_SET } } # [doc = "Field `INT_EVENT0_MIS_TXEMPTY` reader - Masked Transmit FIFO Empty event."]
pub type INT_EVENT0_MIS_TXEMPTY_R = crate :: BitReader < INT_EVENT0_MIS_TXEMPTY_A > ; # [doc = "Masked Transmit FIFO Empty event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_MIS_TXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TXEMPTY_A { match self . bits { false => INT_EVENT0_MIS_TXEMPTY_A :: INT_EVENT0_MIS_TXEMPTY_CLR , true => INT_EVENT0_MIS_TXEMPTY_A :: INT_EVENT0_MIS_TXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_txempty_clr (& self) -> bool { * self == INT_EVENT0_MIS_TXEMPTY_A :: INT_EVENT0_MIS_TXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_txempty_set (& self) -> bool { * self == INT_EVENT0_MIS_TXEMPTY_A :: INT_EVENT0_MIS_TXEMPTY_SET } } # [doc = "Field `INT_EVENT0_MIS_IDLE` reader - Masked SPI IDLE mode event."]
pub type INT_EVENT0_MIS_IDLE_R = crate :: BitReader < INT_EVENT0_MIS_IDLE_A > ; # [doc = "Masked SPI IDLE mode event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_IDLE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_IDLE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_IDLE_SET = 1 , } impl From < INT_EVENT0_MIS_IDLE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_IDLE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_IDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_IDLE_A { match self . bits { false => INT_EVENT0_MIS_IDLE_A :: INT_EVENT0_MIS_IDLE_CLR , true => INT_EVENT0_MIS_IDLE_A :: INT_EVENT0_MIS_IDLE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_idle_clr (& self) -> bool { * self == INT_EVENT0_MIS_IDLE_A :: INT_EVENT0_MIS_IDLE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_idle_set (& self) -> bool { * self == INT_EVENT0_MIS_IDLE_A :: INT_EVENT0_MIS_IDLE_SET } } # [doc = "Field `INT_EVENT0_MIS_DMA_DONE_RX` reader - Masked DMA Done 1 event for RX."]
pub type INT_EVENT0_MIS_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_MIS_DMA_DONE_RX_A > ; # [doc = "Masked DMA Done 1 event for RX.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_MIS_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_CLR , true => INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_MIS_DMA_DONE_TX` reader - Masked DMA Done 1 event for TX."]
pub type INT_EVENT0_MIS_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_MIS_DMA_DONE_TX_A > ; # [doc = "Masked DMA Done 1 event for TX.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_MIS_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_CLR , true => INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_MIS_TXFIFO_UNF` reader - TX FIFO underflow interrupt"]
pub type INT_EVENT0_MIS_TXFIFO_UNF_R = crate :: BitReader < INT_EVENT0_MIS_TXFIFO_UNF_A > ; # [doc = "TX FIFO underflow interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TXFIFO_UNF_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TXFIFO_UNF_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_MIS_TXFIFO_UNF_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TXFIFO_UNF_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TXFIFO_UNF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TXFIFO_UNF_A { match self . bits { false => INT_EVENT0_MIS_TXFIFO_UNF_A :: INT_EVENT0_MIS_TXFIFO_UNF_CLR , true => INT_EVENT0_MIS_TXFIFO_UNF_A :: INT_EVENT0_MIS_TXFIFO_UNF_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_txfifo_unf_clr (& self) -> bool { * self == INT_EVENT0_MIS_TXFIFO_UNF_A :: INT_EVENT0_MIS_TXFIFO_UNF_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_txfifo_unf_set (& self) -> bool { * self == INT_EVENT0_MIS_TXFIFO_UNF_A :: INT_EVENT0_MIS_TXFIFO_UNF_SET } } # [doc = "Field `INT_EVENT0_MIS_RXFULL` reader - RX FIFO Full Interrupt"]
pub type INT_EVENT0_MIS_RXFULL_R = crate :: BitReader < INT_EVENT0_MIS_RXFULL_A > ; # [doc = "RX FIFO Full Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXFULL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXFULL_SET = 1 , } impl From < INT_EVENT0_MIS_RXFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXFULL_A { match self . bits { false => INT_EVENT0_MIS_RXFULL_A :: INT_EVENT0_MIS_RXFULL_CLR , true => INT_EVENT0_MIS_RXFULL_A :: INT_EVENT0_MIS_RXFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxfull_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXFULL_A :: INT_EVENT0_MIS_RXFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxfull_set (& self) -> bool { * self == INT_EVENT0_MIS_RXFULL_A :: INT_EVENT0_MIS_RXFULL_SET } } impl R { # [doc = "Bit 0 - Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected."]
# [inline (always)]
pub fn int_event0_mis_rxfifo_ovf (& self) -> INT_EVENT0_MIS_RXFIFO_OVF_R { INT_EVENT0_MIS_RXFIFO_OVF_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masked Parity error event: this bit if a Parity error has been detected"]
# [inline (always)]
pub fn int_event0_mis_per (& self) -> INT_EVENT0_MIS_PER_R { INT_EVENT0_MIS_PER_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masked SPI Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rtout (& self) -> INT_EVENT0_MIS_RTOUT_R { INT_EVENT0_MIS_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
# [inline (always)]
pub fn int_event0_mis_rx (& self) -> INT_EVENT0_MIS_RX_R { INT_EVENT0_MIS_RX_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached."]
# [inline (always)]
pub fn int_event0_mis_tx (& self) -> INT_EVENT0_MIS_TX_R { INT_EVENT0_MIS_TX_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Masked Transmit FIFO Empty event."]
# [inline (always)]
pub fn int_event0_mis_txempty (& self) -> INT_EVENT0_MIS_TXEMPTY_R { INT_EVENT0_MIS_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Masked SPI IDLE mode event."]
# [inline (always)]
pub fn int_event0_mis_idle (& self) -> INT_EVENT0_MIS_IDLE_R { INT_EVENT0_MIS_IDLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Masked DMA Done 1 event for RX."]
# [inline (always)]
pub fn int_event0_mis_dma_done_rx (& self) -> INT_EVENT0_MIS_DMA_DONE_RX_R { INT_EVENT0_MIS_DMA_DONE_RX_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Masked DMA Done 1 event for TX."]
# [inline (always)]
pub fn int_event0_mis_dma_done_tx (& self) -> INT_EVENT0_MIS_DMA_DONE_TX_R { INT_EVENT0_MIS_DMA_DONE_TX_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - TX FIFO underflow interrupt"]
# [inline (always)]
pub fn int_event0_mis_txfifo_unf (& self) -> INT_EVENT0_MIS_TXFIFO_UNF_R { INT_EVENT0_MIS_TXFIFO_UNF_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - RX FIFO Full Interrupt"]
# [inline (always)]
pub fn int_event0_mis_rxfull (& self) -> INT_EVENT0_MIS_RXFULL_R { INT_EVENT0_MIS_RXFULL_R :: new (((self . bits >> 10) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_MIS to value 0"]
impl crate :: Resettable for INT_EVENT0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iset`]
module"]
pub type INT_EVENT0_ISET = crate :: Reg < int_event0_iset :: INT_EVENT0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event0_iset { # [doc = "Register `INT_EVENT0_ISET` writer"]
pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set RXFIFO overflow event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXFIFO_OVF_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXFIFO_OVF_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXFIFO_OVF_SET = 1 , } impl From < INT_EVENT0_ISET_RXFIFO_OVF_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXFIFO_OVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXFIFO_OVF` writer - Set RXFIFO overflow event."]
pub type INT_EVENT0_ISET_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXFIFO_OVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxfifo_ovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXFIFO_OVF_AW :: INT_EVENT0_ISET_RXFIFO_OVF_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxfifo_ovf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXFIFO_OVF_AW :: INT_EVENT0_ISET_RXFIFO_OVF_SET) } } # [doc = "Set Parity error event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_PER_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_PER_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_PER_SET = 1 , } impl From < INT_EVENT0_ISET_PER_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_PER_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PER` writer - Set Parity error event."]
pub type INT_EVENT0_ISET_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PER_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_per_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PER_AW :: INT_EVENT0_ISET_PER_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_per_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PER_AW :: INT_EVENT0_ISET_PER_SET) } } # [doc = "Set SPI Receive Time-Out Event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set SPI Receive Time-Out Event."]
pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set Receive FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RX_SET = 1 , } impl From < INT_EVENT0_ISET_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RX` writer - Set Receive FIFO event."]
pub type INT_EVENT0_ISET_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RX_AW :: INT_EVENT0_ISET_RX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RX_AW :: INT_EVENT0_ISET_RX_SET) } } # [doc = "Set Transmit FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TX_SET = 1 , } impl From < INT_EVENT0_ISET_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TX` writer - Set Transmit FIFO event."]
pub type INT_EVENT0_ISET_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TX_AW :: INT_EVENT0_ISET_TX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TX_AW :: INT_EVENT0_ISET_TX_SET) } } # [doc = "Set Transmit FIFO Empty event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_TXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXEMPTY` writer - Set Transmit FIFO Empty event."]
pub type INT_EVENT0_ISET_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_txempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXEMPTY_AW :: INT_EVENT0_ISET_TXEMPTY_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_txempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXEMPTY_AW :: INT_EVENT0_ISET_TXEMPTY_SET) } } # [doc = "Set SPI IDLE mode event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_IDLE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_IDLE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_IDLE_SET = 1 , } impl From < INT_EVENT0_ISET_IDLE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_IDLE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_IDLE` writer - Set SPI IDLE mode event."]
pub type INT_EVENT0_ISET_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_IDLE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_idle_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_IDLE_AW :: INT_EVENT0_ISET_IDLE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_idle_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_IDLE_AW :: INT_EVENT0_ISET_IDLE_SET) } } # [doc = "Set DMA Done 1 event for RX.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done 1 event for RX."]
pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done 1 event for TX.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done 1 event for TX."]
pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Set TX FIFO Underflow Event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TXFIFO_UNF_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TXFIFO_UNF_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TXFIFO_UNF_SET = 1 , } impl From < INT_EVENT0_ISET_TXFIFO_UNF_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TXFIFO_UNF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXFIFO_UNF` writer - Set TX FIFO Underflow Event"]
pub type INT_EVENT0_ISET_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXFIFO_UNF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_txfifo_unf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXFIFO_UNF_AW :: INT_EVENT0_ISET_TXFIFO_UNF_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_txfifo_unf_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXFIFO_UNF_AW :: INT_EVENT0_ISET_TXFIFO_UNF_SET) } } # [doc = "Set RX FIFO Full Event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXFULL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXFULL_SET = 1 , } impl From < INT_EVENT0_ISET_RXFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXFULL` writer - Set RX FIFO Full Event"]
pub type INT_EVENT0_ISET_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxfull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXFULL_AW :: INT_EVENT0_ISET_RXFULL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxfull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXFULL_AW :: INT_EVENT0_ISET_RXFULL_SET) } } impl W { # [doc = "Bit 0 - Set RXFIFO overflow event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxfifo_ovf (& mut self) -> INT_EVENT0_ISET_RXFIFO_OVF_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Set Parity error event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_per (& mut self) -> INT_EVENT0_ISET_PER_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_PER_W :: new (self) } # [doc = "Bit 2 - Set SPI Receive Time-Out Event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 3 - Set Receive FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rx (& mut self) -> INT_EVENT0_ISET_RX_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_RX_W :: new (self) } # [doc = "Bit 4 - Set Transmit FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_tx (& mut self) -> INT_EVENT0_ISET_TX_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_TX_W :: new (self) } # [doc = "Bit 5 - Set Transmit FIFO Empty event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_txempty (& mut self) -> INT_EVENT0_ISET_TXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - Set SPI IDLE mode event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_idle (& mut self) -> INT_EVENT0_ISET_IDLE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_IDLE_W :: new (self) } # [doc = "Bit 7 - Set DMA Done 1 event for RX."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - Set DMA Done 1 event for TX."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - Set TX FIFO Underflow Event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_txfifo_unf (& mut self) -> INT_EVENT0_ISET_TXFIFO_UNF_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - Set RX FIFO Full Event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxfull (& mut self) -> INT_EVENT0_ISET_RXFULL_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"]
impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iclr`]
module"]
pub type INT_EVENT0_ICLR = crate :: Reg < int_event0_iclr :: INT_EVENT0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event0_iclr { # [doc = "Register `INT_EVENT0_ICLR` writer"]
pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear RXFIFO overflow event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXFIFO_OVF_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXFIFO_OVF_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXFIFO_OVF_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXFIFO_OVF_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXFIFO_OVF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXFIFO_OVF` writer - Clear RXFIFO overflow event."]
pub type INT_EVENT0_ICLR_RXFIFO_OVF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXFIFO_OVF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXFIFO_OVF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxfifo_ovf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXFIFO_OVF_AW :: INT_EVENT0_ICLR_RXFIFO_OVF_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxfifo_ovf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXFIFO_OVF_AW :: INT_EVENT0_ICLR_RXFIFO_OVF_CLR) } } # [doc = "Clear Parity error event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_PER_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_PER_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_PER_CLR = 1 , } impl From < INT_EVENT0_ICLR_PER_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_PER_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PER` writer - Clear Parity error event."]
pub type INT_EVENT0_ICLR_PER_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PER_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_per_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PER_AW :: INT_EVENT0_ICLR_PER_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_per_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PER_AW :: INT_EVENT0_ICLR_PER_CLR) } } # [doc = "Clear SPI Receive Time-Out Event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear SPI Receive Time-Out Event."]
pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear Receive FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RX` writer - Clear Receive FIFO event."]
pub type INT_EVENT0_ICLR_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RX_AW :: INT_EVENT0_ICLR_RX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RX_AW :: INT_EVENT0_ICLR_RX_CLR) } } # [doc = "Clear Transmit FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TX` writer - Clear Transmit FIFO event."]
pub type INT_EVENT0_ICLR_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TX_AW :: INT_EVENT0_ICLR_TX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TX_AW :: INT_EVENT0_ICLR_TX_CLR) } } # [doc = "Clear Transmit FIFO Empty event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TXEMPTY_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TXEMPTY_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXEMPTY` writer - Clear Transmit FIFO Empty event."]
pub type INT_EVENT0_ICLR_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_txempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXEMPTY_AW :: INT_EVENT0_ICLR_TXEMPTY_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_txempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXEMPTY_AW :: INT_EVENT0_ICLR_TXEMPTY_CLR) } } # [doc = "Clear SPI IDLE mode event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_IDLE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_IDLE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_IDLE_CLR = 1 , } impl From < INT_EVENT0_ICLR_IDLE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_IDLE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_IDLE` writer - Clear SPI IDLE mode event."]
pub type INT_EVENT0_ICLR_IDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_IDLE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_IDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_idle_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_IDLE_AW :: INT_EVENT0_ICLR_IDLE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_idle_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_IDLE_AW :: INT_EVENT0_ICLR_IDLE_CLR) } } # [doc = "Clear DMA Done 1 event for RX.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done 1 event for RX."]
pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done 1 event for TX.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done 1 event for TX."]
pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Clear TXFIFO underflow event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TXFIFO_UNF_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TXFIFO_UNF_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TXFIFO_UNF_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXFIFO_UNF_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TXFIFO_UNF_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXFIFO_UNF` writer - Clear TXFIFO underflow event"]
pub type INT_EVENT0_ICLR_TXFIFO_UNF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXFIFO_UNF_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXFIFO_UNF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_txfifo_unf_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXFIFO_UNF_AW :: INT_EVENT0_ICLR_TXFIFO_UNF_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_txfifo_unf_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXFIFO_UNF_AW :: INT_EVENT0_ICLR_TXFIFO_UNF_CLR) } } # [doc = "Clear RX FIFO underflow event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXFULL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXFULL_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXFULL` writer - Clear RX FIFO underflow event"]
pub type INT_EVENT0_ICLR_RXFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxfull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXFULL_AW :: INT_EVENT0_ICLR_RXFULL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxfull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXFULL_AW :: INT_EVENT0_ICLR_RXFULL_CLR) } } impl W { # [doc = "Bit 0 - Clear RXFIFO overflow event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxfifo_ovf (& mut self) -> INT_EVENT0_ICLR_RXFIFO_OVF_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RXFIFO_OVF_W :: new (self) } # [doc = "Bit 1 - Clear Parity error event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_per (& mut self) -> INT_EVENT0_ICLR_PER_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_PER_W :: new (self) } # [doc = "Bit 2 - Clear SPI Receive Time-Out Event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 3 - Clear Receive FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rx (& mut self) -> INT_EVENT0_ICLR_RX_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_RX_W :: new (self) } # [doc = "Bit 4 - Clear Transmit FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_tx (& mut self) -> INT_EVENT0_ICLR_TX_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_TX_W :: new (self) } # [doc = "Bit 5 - Clear Transmit FIFO Empty event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_txempty (& mut self) -> INT_EVENT0_ICLR_TXEMPTY_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_TXEMPTY_W :: new (self) } # [doc = "Bit 6 - Clear SPI IDLE mode event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_idle (& mut self) -> INT_EVENT0_ICLR_IDLE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_IDLE_W :: new (self) } # [doc = "Bit 7 - Clear DMA Done 1 event for RX."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 8 - Clear DMA Done 1 event for TX."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 9 - Clear TXFIFO underflow event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_txfifo_unf (& mut self) -> INT_EVENT0_ICLR_TXFIFO_UNF_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_TXFIFO_UNF_W :: new (self) } # [doc = "Bit 10 - Clear RX FIFO underflow event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxfull (& mut self) -> INT_EVENT0_ICLR_RXFULL_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXFULL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IIDX (r) register accessor: Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iidx`]
module"]
pub type INT_EVENT1_IIDX = crate :: Reg < int_event1_iidx :: INT_EVENT1_IIDX_SPEC > ; # [doc = "Interrupt Index Register"]
pub mod int_event1_iidx { # [doc = "Register `INT_EVENT1_IIDX` reader"]
pub type R = crate :: R < INT_EVENT1_IIDX_SPEC > ; # [doc = "Field `INT_EVENT1_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT1_IIDX_STAT_R = crate :: FieldReader < INT_EVENT1_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT1_IIDX_STAT_NO_INTR = 0 , # [doc = "3: RTOUT_EVT"]
INT_EVENT1_IIDX_STAT_RTOUT_EVT = 3 , # [doc = "4: RX_EVT"]
INT_EVENT1_IIDX_STAT_RX_EVT = 4 , } impl From < INT_EVENT1_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT1_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR) , 3 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RTOUT_EVT) , 4 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RX_EVT) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR } # [doc = "RTOUT_EVT"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_rtout_evt (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RTOUT_EVT } # [doc = "RX_EVT"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_rx_evt (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RX_EVT } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_event1_iidx_stat (& self) -> INT_EVENT1_IIDX_STAT_R { INT_EVENT1_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_imask`]
module"]
pub type INT_EVENT1_IMASK = crate :: Reg < int_event1_imask :: INT_EVENT1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event1_imask { # [doc = "Register `INT_EVENT1_IMASK` reader"]
pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"]
pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_RTOUT` reader - SPI Receive Time-Out event mask."]
pub type INT_EVENT1_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT1_IMASK_RTOUT_A > ; # [doc = "SPI Receive Time-Out event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT1_IMASK_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_RTOUT_A { match self . bits { false => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR , true => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_rtout_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_rtout_set (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RTOUT` writer - SPI Receive Time-Out event mask."]
pub type INT_EVENT1_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT1_IMASK_RX` reader - Receive FIFO event mask."]
pub type INT_EVENT1_IMASK_RX_R = crate :: BitReader < INT_EVENT1_IMASK_RX_A > ; # [doc = "Receive FIFO event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_RX_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_RX_SET = 1 , } impl From < INT_EVENT1_IMASK_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_RX_A { match self . bits { false => INT_EVENT1_IMASK_RX_A :: INT_EVENT1_IMASK_RX_CLR , true => INT_EVENT1_IMASK_RX_A :: INT_EVENT1_IMASK_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_rx_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RX_A :: INT_EVENT1_IMASK_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_rx_set (& self) -> bool { * self == INT_EVENT1_IMASK_RX_A :: INT_EVENT1_IMASK_RX_SET } } # [doc = "Field `INT_EVENT1_IMASK_RX` writer - Receive FIFO event mask."]
pub type INT_EVENT1_IMASK_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RX_A :: INT_EVENT1_IMASK_RX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RX_A :: INT_EVENT1_IMASK_RX_SET) } } impl R { # [doc = "Bit 2 - SPI Receive Time-Out event mask."]
# [inline (always)]
pub fn int_event1_imask_rtout (& self) -> INT_EVENT1_IMASK_RTOUT_R { INT_EVENT1_IMASK_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event mask."]
# [inline (always)]
pub fn int_event1_imask_rx (& self) -> INT_EVENT1_IMASK_RX_R { INT_EVENT1_IMASK_RX_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 2 - SPI Receive Time-Out event mask."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_rtout (& mut self) -> INT_EVENT1_IMASK_RTOUT_W < INT_EVENT1_IMASK_SPEC , 2 > { INT_EVENT1_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 3 - Receive FIFO event mask."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_rx (& mut self) -> INT_EVENT1_IMASK_RX_W < INT_EVENT1_IMASK_SPEC , 3 > { INT_EVENT1_IMASK_RX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_ris`]
module"]
pub type INT_EVENT1_RIS = crate :: Reg < int_event1_ris :: INT_EVENT1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event1_ris { # [doc = "Register `INT_EVENT1_RIS` reader"]
pub type R = crate :: R < INT_EVENT1_RIS_SPEC > ; # [doc = "Field `INT_EVENT1_RIS_RTOUT` reader - SPI Receive Time-Out Event."]
pub type INT_EVENT1_RIS_RTOUT_R = crate :: BitReader < INT_EVENT1_RIS_RTOUT_A > ; # [doc = "SPI Receive Time-Out Event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_RTOUT_SET = 1 , } impl From < INT_EVENT1_RIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_RTOUT_A { match self . bits { false => INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_CLR , true => INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_rtout_clr (& self) -> bool { * self == INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_rtout_set (& self) -> bool { * self == INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_SET } } # [doc = "Field `INT_EVENT1_RIS_RX` reader - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
pub type INT_EVENT1_RIS_RX_R = crate :: BitReader < INT_EVENT1_RIS_RX_A > ; # [doc = "Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_RX_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_RX_SET = 1 , } impl From < INT_EVENT1_RIS_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_RX_A { match self . bits { false => INT_EVENT1_RIS_RX_A :: INT_EVENT1_RIS_RX_CLR , true => INT_EVENT1_RIS_RX_A :: INT_EVENT1_RIS_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_rx_clr (& self) -> bool { * self == INT_EVENT1_RIS_RX_A :: INT_EVENT1_RIS_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_rx_set (& self) -> bool { * self == INT_EVENT1_RIS_RX_A :: INT_EVENT1_RIS_RX_SET } } impl R { # [doc = "Bit 2 - SPI Receive Time-Out Event."]
# [inline (always)]
pub fn int_event1_ris_rtout (& self) -> INT_EVENT1_RIS_RTOUT_R { INT_EVENT1_RIS_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached"]
# [inline (always)]
pub fn int_event1_ris_rx (& self) -> INT_EVENT1_RIS_RX_R { INT_EVENT1_RIS_RX_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_RIS to value 0"]
impl crate :: Resettable for INT_EVENT1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_mis`]
module"]
pub type INT_EVENT1_MIS = crate :: Reg < int_event1_mis :: INT_EVENT1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event1_mis { # [doc = "Register `INT_EVENT1_MIS` reader"]
pub type R = crate :: R < INT_EVENT1_MIS_SPEC > ; # [doc = "Field `INT_EVENT1_MIS_RTOUT` reader - SPI Receive Time-Out event mask."]
pub type INT_EVENT1_MIS_RTOUT_R = crate :: BitReader < INT_EVENT1_MIS_RTOUT_A > ; # [doc = "SPI Receive Time-Out event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_RTOUT_SET = 1 , } impl From < INT_EVENT1_MIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_RTOUT_A { match self . bits { false => INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_CLR , true => INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_rtout_clr (& self) -> bool { * self == INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_rtout_set (& self) -> bool { * self == INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_SET } } # [doc = "Field `INT_EVENT1_MIS_RX` reader - Receive FIFO event mask."]
pub type INT_EVENT1_MIS_RX_R = crate :: BitReader < INT_EVENT1_MIS_RX_A > ; # [doc = "Receive FIFO event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_RX_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_RX_SET = 1 , } impl From < INT_EVENT1_MIS_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_RX_A { match self . bits { false => INT_EVENT1_MIS_RX_A :: INT_EVENT1_MIS_RX_CLR , true => INT_EVENT1_MIS_RX_A :: INT_EVENT1_MIS_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_rx_clr (& self) -> bool { * self == INT_EVENT1_MIS_RX_A :: INT_EVENT1_MIS_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_rx_set (& self) -> bool { * self == INT_EVENT1_MIS_RX_A :: INT_EVENT1_MIS_RX_SET } } impl R { # [doc = "Bit 2 - SPI Receive Time-Out event mask."]
# [inline (always)]
pub fn int_event1_mis_rtout (& self) -> INT_EVENT1_MIS_RTOUT_R { INT_EVENT1_MIS_RTOUT_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO event mask."]
# [inline (always)]
pub fn int_event1_mis_rx (& self) -> INT_EVENT1_MIS_RX_R { INT_EVENT1_MIS_RX_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_MIS to value 0"]
impl crate :: Resettable for INT_EVENT1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iset`]
module"]
pub type INT_EVENT1_ISET = crate :: Reg < int_event1_iset :: INT_EVENT1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event1_iset { # [doc = "Register `INT_EVENT1_ISET` writer"]
pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Set SPI Receive Time-Out event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT1_ISET_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RTOUT` writer - Set SPI Receive Time-Out event."]
pub type INT_EVENT1_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_SET) } } # [doc = "Set Receive FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_RX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_RX_SET = 1 , } impl From < INT_EVENT1_ISET_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RX` writer - Set Receive FIFO event."]
pub type INT_EVENT1_ISET_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RX_AW :: INT_EVENT1_ISET_RX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RX_AW :: INT_EVENT1_ISET_RX_SET) } } impl W { # [doc = "Bit 2 - Set SPI Receive Time-Out event."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_rtout (& mut self) -> INT_EVENT1_ISET_RTOUT_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_RTOUT_W :: new (self) } # [doc = "Bit 3 - Set Receive FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_rx (& mut self) -> INT_EVENT1_ISET_RX_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_RX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"]
impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iclr`]
module"]
pub type INT_EVENT1_ICLR = crate :: Reg < int_event1_iclr :: INT_EVENT1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event1_iclr { # [doc = "Register `INT_EVENT1_ICLR` writer"]
pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Clear SPI Receive Time-Out event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RTOUT` writer - Clear SPI Receive Time-Out event."]
pub type INT_EVENT1_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_CLR) } } # [doc = "Clear Receive FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_RX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_RX_CLR = 1 , } impl From < INT_EVENT1_ICLR_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RX` writer - Clear Receive FIFO event."]
pub type INT_EVENT1_ICLR_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RX_AW :: INT_EVENT1_ICLR_RX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RX_AW :: INT_EVENT1_ICLR_RX_CLR) } } impl W { # [doc = "Bit 2 - Clear SPI Receive Time-Out event."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_rtout (& mut self) -> INT_EVENT1_ICLR_RTOUT_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 3 - Clear Receive FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_rx (& mut self) -> INT_EVENT1_ICLR_RX_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_RX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IIDX (r) register accessor: Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iidx`]
module"]
pub type INT_EVENT2_IIDX = crate :: Reg < int_event2_iidx :: INT_EVENT2_IIDX_SPEC > ; # [doc = "Interrupt Index Register"]
pub mod int_event2_iidx { # [doc = "Register `INT_EVENT2_IIDX` reader"]
pub type R = crate :: R < INT_EVENT2_IIDX_SPEC > ; # [doc = "Field `INT_EVENT2_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT2_IIDX_STAT_R = crate :: FieldReader < INT_EVENT2_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT2_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT2_IIDX_STAT_NO_INTR = 0 , # [doc = "5: TX_EVT"]
INT_EVENT2_IIDX_STAT_TX_EVT = 5 , } impl From < INT_EVENT2_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT2_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT2_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT2_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT2_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR) , 5 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_TX_EVT) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR } # [doc = "TX_EVT"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_tx_evt (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_TX_EVT } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_event2_iidx_stat (& self) -> INT_EVENT2_IIDX_STAT_R { INT_EVENT2_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt Index Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT2_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_imask`]
module"]
pub type INT_EVENT2_IMASK = crate :: Reg < int_event2_imask :: INT_EVENT2_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event2_imask { # [doc = "Register `INT_EVENT2_IMASK` reader"]
pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"]
pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_TX` reader - Transmit FIFO event mask."]
pub type INT_EVENT2_IMASK_TX_R = crate :: BitReader < INT_EVENT2_IMASK_TX_A > ; # [doc = "Transmit FIFO event mask.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_TX_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_TX_SET = 1 , } impl From < INT_EVENT2_IMASK_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_TX_A { match self . bits { false => INT_EVENT2_IMASK_TX_A :: INT_EVENT2_IMASK_TX_CLR , true => INT_EVENT2_IMASK_TX_A :: INT_EVENT2_IMASK_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_tx_clr (& self) -> bool { * self == INT_EVENT2_IMASK_TX_A :: INT_EVENT2_IMASK_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_tx_set (& self) -> bool { * self == INT_EVENT2_IMASK_TX_A :: INT_EVENT2_IMASK_TX_SET } } # [doc = "Field `INT_EVENT2_IMASK_TX` writer - Transmit FIFO event mask."]
pub type INT_EVENT2_IMASK_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TX_A :: INT_EVENT2_IMASK_TX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TX_A :: INT_EVENT2_IMASK_TX_SET) } } impl R { # [doc = "Bit 4 - Transmit FIFO event mask."]
# [inline (always)]
pub fn int_event2_imask_tx (& self) -> INT_EVENT2_IMASK_TX_R { INT_EVENT2_IMASK_TX_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 4 - Transmit FIFO event mask."]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_tx (& mut self) -> INT_EVENT2_IMASK_TX_W < INT_EVENT2_IMASK_SPEC , 4 > { INT_EVENT2_IMASK_TX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_ris`]
module"]
pub type INT_EVENT2_RIS = crate :: Reg < int_event2_ris :: INT_EVENT2_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event2_ris { # [doc = "Register `INT_EVENT2_RIS` reader"]
pub type R = crate :: R < INT_EVENT2_RIS_SPEC > ; # [doc = "Field `INT_EVENT2_RIS_TX` reader - Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt."]
pub type INT_EVENT2_RIS_TX_R = crate :: BitReader < INT_EVENT2_RIS_TX_A > ; # [doc = "Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_TX_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_TX_SET = 1 , } impl From < INT_EVENT2_RIS_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_TX_A { match self . bits { false => INT_EVENT2_RIS_TX_A :: INT_EVENT2_RIS_TX_CLR , true => INT_EVENT2_RIS_TX_A :: INT_EVENT2_RIS_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_tx_clr (& self) -> bool { * self == INT_EVENT2_RIS_TX_A :: INT_EVENT2_RIS_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_tx_set (& self) -> bool { * self == INT_EVENT2_RIS_TX_A :: INT_EVENT2_RIS_TX_SET } } impl R { # [doc = "Bit 4 - Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt."]
# [inline (always)]
pub fn int_event2_ris_tx (& self) -> INT_EVENT2_RIS_TX_R { INT_EVENT2_RIS_TX_R :: new (((self . bits >> 4) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_RIS to value 0"]
impl crate :: Resettable for INT_EVENT2_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_mis`]
module"]
pub type INT_EVENT2_MIS = crate :: Reg < int_event2_mis :: INT_EVENT2_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event2_mis { # [doc = "Register `INT_EVENT2_MIS` reader"]
pub type R = crate :: R < INT_EVENT2_MIS_SPEC > ; # [doc = "Field `INT_EVENT2_MIS_TX` reader - Masked Transmit FIFO event"]
pub type INT_EVENT2_MIS_TX_R = crate :: BitReader < INT_EVENT2_MIS_TX_A > ; # [doc = "Masked Transmit FIFO event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_TX_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_TX_SET = 1 , } impl From < INT_EVENT2_MIS_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_TX_A { match self . bits { false => INT_EVENT2_MIS_TX_A :: INT_EVENT2_MIS_TX_CLR , true => INT_EVENT2_MIS_TX_A :: INT_EVENT2_MIS_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_tx_clr (& self) -> bool { * self == INT_EVENT2_MIS_TX_A :: INT_EVENT2_MIS_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_tx_set (& self) -> bool { * self == INT_EVENT2_MIS_TX_A :: INT_EVENT2_MIS_TX_SET } } impl R { # [doc = "Bit 4 - Masked Transmit FIFO event"]
# [inline (always)]
pub fn int_event2_mis_tx (& self) -> INT_EVENT2_MIS_TX_R { INT_EVENT2_MIS_TX_R :: new (((self . bits >> 4) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_MIS to value 0"]
impl crate :: Resettable for INT_EVENT2_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iset`]
module"]
pub type INT_EVENT2_ISET = crate :: Reg < int_event2_iset :: INT_EVENT2_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event2_iset { # [doc = "Register `INT_EVENT2_ISET` writer"]
pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Set Transmit FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_TX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_TX_SET = 1 , } impl From < INT_EVENT2_ISET_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_TX` writer - Set Transmit FIFO event."]
pub type INT_EVENT2_ISET_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TX_AW :: INT_EVENT2_ISET_TX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TX_AW :: INT_EVENT2_ISET_TX_SET) } } impl W { # [doc = "Bit 4 - Set Transmit FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_tx (& mut self) -> INT_EVENT2_ISET_TX_W < INT_EVENT2_ISET_SPEC , 4 > { INT_EVENT2_ISET_TX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"]
impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iclr`]
module"]
pub type INT_EVENT2_ICLR = crate :: Reg < int_event2_iclr :: INT_EVENT2_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event2_iclr { # [doc = "Register `INT_EVENT2_ICLR` writer"]
pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "Clear Transmit FIFO event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_TX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_TX_CLR = 1 , } impl From < INT_EVENT2_ICLR_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_TX` writer - Clear Transmit FIFO event."]
pub type INT_EVENT2_ICLR_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TX_AW :: INT_EVENT2_ICLR_TX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TX_AW :: INT_EVENT2_ICLR_TX_CLR) } } impl W { # [doc = "Bit 4 - Clear Transmit FIFO event."]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_tx (& mut self) -> INT_EVENT2_ICLR_TX_W < INT_EVENT2_ICLR_SPEC , 4 > { INT_EVENT2_ICLR_TX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_INT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
pub type EVT_MODE_INT1_CFG_R = crate :: FieldReader < EVT_MODE_INT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_DISABLE) , 1 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_disable (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_software (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_INT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
pub type EVT_MODE_INT2_CFG_R = crate :: FieldReader < EVT_MODE_INT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT2_CFG_A :: EVT_MODE_INT2_CFG_DISABLE) , 1 => Some (EVT_MODE_INT2_CFG_A :: EVT_MODE_INT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT2_CFG_A :: EVT_MODE_INT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int2_cfg_disable (& self) -> bool { * self == EVT_MODE_INT2_CFG_A :: EVT_MODE_INT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int2_cfg_software (& self) -> bool { * self == EVT_MODE_INT2_CFG_A :: EVT_MODE_INT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int2_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT2_CFG_A :: EVT_MODE_INT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
# [inline (always)]
pub fn evt_mode_int1_cfg (& self) -> EVT_MODE_INT1_CFG_R { EVT_MODE_INT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
# [inline (always)]
pub fn evt_mode_int2_cfg (& self) -> EVT_MODE_INT2_CFG_R { EVT_MODE_INT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL0 (rw) register accessor: SPI control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl0`]
module"]
pub type CTL0 = crate :: Reg < ctl0 :: CTL0_SPEC > ; # [doc = "SPI control register 0"]
pub mod ctl0 { # [doc = "Register `CTL0` reader"]
pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"]
pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_DSS` reader - Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit"]
pub type CTL0_DSS_R = crate :: FieldReader < CTL0_DSS_A > ; # [doc = "Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_DSS_A { # [doc = "3: DSS_4"]
CTL0_DSS_DSS_4 = 3 , # [doc = "4: DSS_5"]
CTL0_DSS_DSS_5 = 4 , # [doc = "5: DSS_6"]
CTL0_DSS_DSS_6 = 5 , # [doc = "6: DSS_7"]
CTL0_DSS_DSS_7 = 6 , # [doc = "7: DSS_8"]
CTL0_DSS_DSS_8 = 7 , # [doc = "8: DSS_9"]
CTL0_DSS_DSS_9 = 8 , # [doc = "9: DSS_10"]
CTL0_DSS_DSS_10 = 9 , # [doc = "10: DSS_11"]
CTL0_DSS_DSS_11 = 10 , # [doc = "11: DSS_12"]
CTL0_DSS_DSS_12 = 11 , # [doc = "12: DSS_13"]
CTL0_DSS_DSS_13 = 12 , # [doc = "13: DSS_14"]
CTL0_DSS_DSS_14 = 13 , # [doc = "14: DSS_15"]
CTL0_DSS_DSS_15 = 14 , # [doc = "15: DSS_16"]
CTL0_DSS_DSS_16 = 15 , # [doc = "31: DSS_32"]
CTL0_DSS_DSS_32 = 31 , } impl From < CTL0_DSS_A > for u8 { # [inline (always)]
fn from (variant : CTL0_DSS_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_DSS_A { type Ux = u8 ; } impl CTL0_DSS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL0_DSS_A > { match self . bits { 3 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_4) , 4 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_5) , 5 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_6) , 6 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_7) , 7 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_8) , 8 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_9) , 9 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_10) , 10 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_11) , 11 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_12) , 12 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_13) , 13 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_14) , 14 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_15) , 15 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_16) , 31 => Some (CTL0_DSS_A :: CTL0_DSS_DSS_32) , _ => None , } } # [doc = "DSS_4"]
# [inline (always)]
pub fn is_ctl0_dss_dss_4 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_4 } # [doc = "DSS_5"]
# [inline (always)]
pub fn is_ctl0_dss_dss_5 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_5 } # [doc = "DSS_6"]
# [inline (always)]
pub fn is_ctl0_dss_dss_6 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_6 } # [doc = "DSS_7"]
# [inline (always)]
pub fn is_ctl0_dss_dss_7 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_7 } # [doc = "DSS_8"]
# [inline (always)]
pub fn is_ctl0_dss_dss_8 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_8 } # [doc = "DSS_9"]
# [inline (always)]
pub fn is_ctl0_dss_dss_9 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_9 } # [doc = "DSS_10"]
# [inline (always)]
pub fn is_ctl0_dss_dss_10 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_10 } # [doc = "DSS_11"]
# [inline (always)]
pub fn is_ctl0_dss_dss_11 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_11 } # [doc = "DSS_12"]
# [inline (always)]
pub fn is_ctl0_dss_dss_12 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_12 } # [doc = "DSS_13"]
# [inline (always)]
pub fn is_ctl0_dss_dss_13 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_13 } # [doc = "DSS_14"]
# [inline (always)]
pub fn is_ctl0_dss_dss_14 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_14 } # [doc = "DSS_15"]
# [inline (always)]
pub fn is_ctl0_dss_dss_15 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_15 } # [doc = "DSS_16"]
# [inline (always)]
pub fn is_ctl0_dss_dss_16 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_16 } # [doc = "DSS_32"]
# [inline (always)]
pub fn is_ctl0_dss_dss_32 (& self) -> bool { * self == CTL0_DSS_A :: CTL0_DSS_DSS_32 } } # [doc = "Field `CTL0_DSS` writer - Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit"]
pub type CTL0_DSS_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , CTL0_DSS_A > ; impl < 'a , REG , const O : u8 > CTL0_DSS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DSS_4"]
# [inline (always)]
pub fn ctl0_dss_dss_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_4) } # [doc = "DSS_5"]
# [inline (always)]
pub fn ctl0_dss_dss_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_5) } # [doc = "DSS_6"]
# [inline (always)]
pub fn ctl0_dss_dss_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_6) } # [doc = "DSS_7"]
# [inline (always)]
pub fn ctl0_dss_dss_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_7) } # [doc = "DSS_8"]
# [inline (always)]
pub fn ctl0_dss_dss_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_8) } # [doc = "DSS_9"]
# [inline (always)]
pub fn ctl0_dss_dss_9 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_9) } # [doc = "DSS_10"]
# [inline (always)]
pub fn ctl0_dss_dss_10 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_10) } # [doc = "DSS_11"]
# [inline (always)]
pub fn ctl0_dss_dss_11 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_11) } # [doc = "DSS_12"]
# [inline (always)]
pub fn ctl0_dss_dss_12 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_12) } # [doc = "DSS_13"]
# [inline (always)]
pub fn ctl0_dss_dss_13 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_13) } # [doc = "DSS_14"]
# [inline (always)]
pub fn ctl0_dss_dss_14 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_14) } # [doc = "DSS_15"]
# [inline (always)]
pub fn ctl0_dss_dss_15 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_15) } # [doc = "DSS_16"]
# [inline (always)]
pub fn ctl0_dss_dss_16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_16) } # [doc = "DSS_32"]
# [inline (always)]
pub fn ctl0_dss_dss_32 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_DSS_A :: CTL0_DSS_DSS_32) } } # [doc = "Field `CTL0_FRF` reader - Frame format Select"]
pub type CTL0_FRF_R = crate :: FieldReader < CTL0_FRF_A > ; # [doc = "Frame format Select\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_FRF_A { # [doc = "0: MOTOROLA_3WIRE"]
CTL0_FRF_MOTOROLA_3WIRE = 0 , # [doc = "1: MOTOROLA_4WIRE"]
CTL0_FRF_MOTOROLA_4WIRE = 1 , # [doc = "2: TI_SYNC"]
CTL0_FRF_TI_SYNC = 2 , # [doc = "3: MIRCOWIRE"]
CTL0_FRF_MIRCOWIRE = 3 , } impl From < CTL0_FRF_A > for u8 { # [inline (always)]
fn from (variant : CTL0_FRF_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_FRF_A { type Ux = u8 ; } impl CTL0_FRF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_FRF_A { match self . bits { 0 => CTL0_FRF_A :: CTL0_FRF_MOTOROLA_3WIRE , 1 => CTL0_FRF_A :: CTL0_FRF_MOTOROLA_4WIRE , 2 => CTL0_FRF_A :: CTL0_FRF_TI_SYNC , 3 => CTL0_FRF_A :: CTL0_FRF_MIRCOWIRE , _ => unreachable ! () , } } # [doc = "MOTOROLA_3WIRE"]
# [inline (always)]
pub fn is_ctl0_frf_motorola_3wire (& self) -> bool { * self == CTL0_FRF_A :: CTL0_FRF_MOTOROLA_3WIRE } # [doc = "MOTOROLA_4WIRE"]
# [inline (always)]
pub fn is_ctl0_frf_motorola_4wire (& self) -> bool { * self == CTL0_FRF_A :: CTL0_FRF_MOTOROLA_4WIRE } # [doc = "TI_SYNC"]
# [inline (always)]
pub fn is_ctl0_frf_ti_sync (& self) -> bool { * self == CTL0_FRF_A :: CTL0_FRF_TI_SYNC } # [doc = "MIRCOWIRE"]
# [inline (always)]
pub fn is_ctl0_frf_mircowire (& self) -> bool { * self == CTL0_FRF_A :: CTL0_FRF_MIRCOWIRE } } # [doc = "Field `CTL0_FRF` writer - Frame format Select"]
pub type CTL0_FRF_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL0_FRF_A > ; impl < 'a , REG , const O : u8 > CTL0_FRF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "MOTOROLA_3WIRE"]
# [inline (always)]
pub fn ctl0_frf_motorola_3wire (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FRF_A :: CTL0_FRF_MOTOROLA_3WIRE) } # [doc = "MOTOROLA_4WIRE"]
# [inline (always)]
pub fn ctl0_frf_motorola_4wire (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FRF_A :: CTL0_FRF_MOTOROLA_4WIRE) } # [doc = "TI_SYNC"]
# [inline (always)]
pub fn ctl0_frf_ti_sync (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FRF_A :: CTL0_FRF_TI_SYNC) } # [doc = "MIRCOWIRE"]
# [inline (always)]
pub fn ctl0_frf_mircowire (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FRF_A :: CTL0_FRF_MIRCOWIRE) } } # [doc = "Field `CTL0_PACKEN` reader - Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP"]
pub type CTL0_PACKEN_R = crate :: BitReader < CTL0_PACKEN_A > ; # [doc = "Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_PACKEN_A { # [doc = "0: DISABLED"]
CTL0_PACKEN_DISABLED = 0 , # [doc = "1: ENABLED"]
CTL0_PACKEN_ENABLED = 1 , } impl From < CTL0_PACKEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_PACKEN_A) -> Self { variant as u8 != 0 } } impl CTL0_PACKEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_PACKEN_A { match self . bits { false => CTL0_PACKEN_A :: CTL0_PACKEN_DISABLED , true => CTL0_PACKEN_A :: CTL0_PACKEN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ctl0_packen_disabled (& self) -> bool { * self == CTL0_PACKEN_A :: CTL0_PACKEN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ctl0_packen_enabled (& self) -> bool { * self == CTL0_PACKEN_A :: CTL0_PACKEN_ENABLED } } # [doc = "Field `CTL0_PACKEN` writer - Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP"]
pub type CTL0_PACKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_PACKEN_A > ; impl < 'a , REG , const O : u8 > CTL0_PACKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ctl0_packen_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_PACKEN_A :: CTL0_PACKEN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ctl0_packen_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_PACKEN_A :: CTL0_PACKEN_ENABLED) } } # [doc = "Field `CTL0_SPO` reader - CLKOUT polarity (Motorola SPI frame format only)"]
pub type CTL0_SPO_R = crate :: BitReader < CTL0_SPO_A > ; # [doc = "CLKOUT polarity (Motorola SPI frame format only)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_SPO_A { # [doc = "0: LOW"]
CTL0_SPO_LOW = 0 , # [doc = "1: HIGH"]
CTL0_SPO_HIGH = 1 , } impl From < CTL0_SPO_A > for bool { # [inline (always)]
fn from (variant : CTL0_SPO_A) -> Self { variant as u8 != 0 } } impl CTL0_SPO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_SPO_A { match self . bits { false => CTL0_SPO_A :: CTL0_SPO_LOW , true => CTL0_SPO_A :: CTL0_SPO_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_ctl0_spo_low (& self) -> bool { * self == CTL0_SPO_A :: CTL0_SPO_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_ctl0_spo_high (& self) -> bool { * self == CTL0_SPO_A :: CTL0_SPO_HIGH } } # [doc = "Field `CTL0_SPO` writer - CLKOUT polarity (Motorola SPI frame format only)"]
pub type CTL0_SPO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_SPO_A > ; impl < 'a , REG , const O : u8 > CTL0_SPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"]
# [inline (always)]
pub fn ctl0_spo_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SPO_A :: CTL0_SPO_LOW) } # [doc = "HIGH"]
# [inline (always)]
pub fn ctl0_spo_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SPO_A :: CTL0_SPO_HIGH) } } # [doc = "Field `CTL0_SPH` reader - CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge."]
pub type CTL0_SPH_R = crate :: BitReader < CTL0_SPH_A > ; # [doc = "CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_SPH_A { # [doc = "0: FIRST"]
CTL0_SPH_FIRST = 0 , # [doc = "1: SECOND"]
CTL0_SPH_SECOND = 1 , } impl From < CTL0_SPH_A > for bool { # [inline (always)]
fn from (variant : CTL0_SPH_A) -> Self { variant as u8 != 0 } } impl CTL0_SPH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_SPH_A { match self . bits { false => CTL0_SPH_A :: CTL0_SPH_FIRST , true => CTL0_SPH_A :: CTL0_SPH_SECOND , } } # [doc = "FIRST"]
# [inline (always)]
pub fn is_ctl0_sph_first (& self) -> bool { * self == CTL0_SPH_A :: CTL0_SPH_FIRST } # [doc = "SECOND"]
# [inline (always)]
pub fn is_ctl0_sph_second (& self) -> bool { * self == CTL0_SPH_A :: CTL0_SPH_SECOND } } # [doc = "Field `CTL0_SPH` writer - CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge."]
pub type CTL0_SPH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_SPH_A > ; impl < 'a , REG , const O : u8 > CTL0_SPH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FIRST"]
# [inline (always)]
pub fn ctl0_sph_first (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SPH_A :: CTL0_SPH_FIRST) } # [doc = "SECOND"]
# [inline (always)]
pub fn ctl0_sph_second (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SPH_A :: CTL0_SPH_SECOND) } } # [doc = "Field `CTL0_CSSEL` reader - Select the CS line to control on data transfer This bit is for controller mode only."]
pub type CTL0_CSSEL_R = crate :: FieldReader < CTL0_CSSEL_A > ; # [doc = "Select the CS line to control on data transfer This bit is for controller mode only.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_CSSEL_A { # [doc = "0: CSSEL_0"]
CTL0_CSSEL_CSSEL_0 = 0 , # [doc = "1: CSSEL_1"]
CTL0_CSSEL_CSSEL_1 = 1 , # [doc = "2: CSSEL_2"]
CTL0_CSSEL_CSSEL_2 = 2 , # [doc = "3: CSSEL_3"]
CTL0_CSSEL_CSSEL_3 = 3 , } impl From < CTL0_CSSEL_A > for u8 { # [inline (always)]
fn from (variant : CTL0_CSSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_CSSEL_A { type Ux = u8 ; } impl CTL0_CSSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_CSSEL_A { match self . bits { 0 => CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_0 , 1 => CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_1 , 2 => CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_2 , 3 => CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_3 , _ => unreachable ! () , } } # [doc = "CSSEL_0"]
# [inline (always)]
pub fn is_ctl0_cssel_cssel_0 (& self) -> bool { * self == CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_0 } # [doc = "CSSEL_1"]
# [inline (always)]
pub fn is_ctl0_cssel_cssel_1 (& self) -> bool { * self == CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_1 } # [doc = "CSSEL_2"]
# [inline (always)]
pub fn is_ctl0_cssel_cssel_2 (& self) -> bool { * self == CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_2 } # [doc = "CSSEL_3"]
# [inline (always)]
pub fn is_ctl0_cssel_cssel_3 (& self) -> bool { * self == CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_3 } } # [doc = "Field `CTL0_CSSEL` writer - Select the CS line to control on data transfer This bit is for controller mode only."]
pub type CTL0_CSSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL0_CSSEL_A > ; impl < 'a , REG , const O : u8 > CTL0_CSSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CSSEL_0"]
# [inline (always)]
pub fn ctl0_cssel_cssel_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_0) } # [doc = "CSSEL_1"]
# [inline (always)]
pub fn ctl0_cssel_cssel_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_1) } # [doc = "CSSEL_2"]
# [inline (always)]
pub fn ctl0_cssel_cssel_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_2) } # [doc = "CSSEL_3"]
# [inline (always)]
pub fn ctl0_cssel_cssel_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CSSEL_A :: CTL0_CSSEL_CSSEL_3) } } # [doc = "Field `CTL0_CSCLR` reader - Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0."]
pub type CTL0_CSCLR_R = crate :: BitReader < CTL0_CSCLR_A > ; # [doc = "Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_CSCLR_A { # [doc = "0: DISABLE"]
CTL0_CSCLR_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_CSCLR_ENABLE = 1 , } impl From < CTL0_CSCLR_A > for bool { # [inline (always)]
fn from (variant : CTL0_CSCLR_A) -> Self { variant as u8 != 0 } } impl CTL0_CSCLR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_CSCLR_A { match self . bits { false => CTL0_CSCLR_A :: CTL0_CSCLR_DISABLE , true => CTL0_CSCLR_A :: CTL0_CSCLR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_csclr_disable (& self) -> bool { * self == CTL0_CSCLR_A :: CTL0_CSCLR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_csclr_enable (& self) -> bool { * self == CTL0_CSCLR_A :: CTL0_CSCLR_ENABLE } } # [doc = "Field `CTL0_CSCLR` writer - Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0."]
pub type CTL0_CSCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CSCLR_A > ; impl < 'a , REG , const O : u8 > CTL0_CSCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_csclr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CSCLR_A :: CTL0_CSCLR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_csclr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CSCLR_A :: CTL0_CSCLR_ENABLE) } } impl R { # [doc = "Bits 0:4 - Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit"]
# [inline (always)]
pub fn ctl0_dss (& self) -> CTL0_DSS_R { CTL0_DSS_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 5:6 - Frame format Select"]
# [inline (always)]
pub fn ctl0_frf (& self) -> CTL0_FRF_R { CTL0_FRF_R :: new (((self . bits >> 5) & 3) as u8) } # [doc = "Bit 7 - Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP"]
# [inline (always)]
pub fn ctl0_packen (& self) -> CTL0_PACKEN_R { CTL0_PACKEN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - CLKOUT polarity (Motorola SPI frame format only)"]
# [inline (always)]
pub fn ctl0_spo (& self) -> CTL0_SPO_R { CTL0_SPO_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge."]
# [inline (always)]
pub fn ctl0_sph (& self) -> CTL0_SPH_R { CTL0_SPH_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bits 12:13 - Select the CS line to control on data transfer This bit is for controller mode only."]
# [inline (always)]
pub fn ctl0_cssel (& self) -> CTL0_CSSEL_R { CTL0_CSSEL_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bit 14 - Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0."]
# [inline (always)]
pub fn ctl0_csclr (& self) -> CTL0_CSCLR_R { CTL0_CSCLR_R :: new (((self . bits >> 14) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - Data Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit"]
# [inline (always)]
# [must_use]
pub fn ctl0_dss (& mut self) -> CTL0_DSS_W < CTL0_SPEC , 0 > { CTL0_DSS_W :: new (self) } # [doc = "Bits 5:6 - Frame format Select"]
# [inline (always)]
# [must_use]
pub fn ctl0_frf (& mut self) -> CTL0_FRF_W < CTL0_SPEC , 5 > { CTL0_FRF_W :: new (self) } # [doc = "Bit 7 - Packing Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP"]
# [inline (always)]
# [must_use]
pub fn ctl0_packen (& mut self) -> CTL0_PACKEN_W < CTL0_SPEC , 7 > { CTL0_PACKEN_W :: new (self) } # [doc = "Bit 8 - CLKOUT polarity (Motorola SPI frame format only)"]
# [inline (always)]
# [must_use]
pub fn ctl0_spo (& mut self) -> CTL0_SPO_W < CTL0_SPEC , 8 > { CTL0_SPO_W :: new (self) } # [doc = "Bit 9 - CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge."]
# [inline (always)]
# [must_use]
pub fn ctl0_sph (& mut self) -> CTL0_SPH_W < CTL0_SPEC , 9 > { CTL0_SPH_W :: new (self) } # [doc = "Bits 12:13 - Select the CS line to control on data transfer This bit is for controller mode only."]
# [inline (always)]
# [must_use]
pub fn ctl0_cssel (& mut self) -> CTL0_CSSEL_W < CTL0_SPEC , 12 > { CTL0_CSSEL_W :: new (self) } # [doc = "Bit 14 - Clear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.MS=0."]
# [inline (always)]
# [must_use]
pub fn ctl0_csclr (& mut self) -> CTL0_CSCLR_W < CTL0_SPEC , 14 > { CTL0_CSCLR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SPI control register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0"]
impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL1 (rw) register accessor: SPI control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl1`]
module"]
pub type CTL1 = crate :: Reg < ctl1 :: CTL1_SPEC > ; # [doc = "SPI control register 1"]
pub mod ctl1 { # [doc = "Register `CTL1` reader"]
pub type R = crate :: R < CTL1_SPEC > ; # [doc = "Register `CTL1` writer"]
pub type W = crate :: W < CTL1_SPEC > ; # [doc = "Field `CTL1_ENABLE` reader - SPI enable"]
pub type CTL1_ENABLE_R = crate :: BitReader < CTL1_ENABLE_A > ; # [doc = "SPI enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_ENABLE_A { # [doc = "0: DISABLE"]
CTL1_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_ENABLE_ENABLE = 1 , } impl From < CTL1_ENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL1_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL1_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_ENABLE_A { match self . bits { false => CTL1_ENABLE_A :: CTL1_ENABLE_DISABLE , true => CTL1_ENABLE_A :: CTL1_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_enable_disable (& self) -> bool { * self == CTL1_ENABLE_A :: CTL1_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_enable_enable (& self) -> bool { * self == CTL1_ENABLE_A :: CTL1_ENABLE_ENABLE } } # [doc = "Field `CTL1_ENABLE` writer - SPI enable"]
pub type CTL1_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL1_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_ENABLE_A :: CTL1_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_ENABLE_A :: CTL1_ENABLE_ENABLE) } } # [doc = "Field `CTL1_LBM` reader - Loop back mode"]
pub type CTL1_LBM_R = crate :: BitReader < CTL1_LBM_A > ; # [doc = "Loop back mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_LBM_A { # [doc = "0: DISABLE"]
CTL1_LBM_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_LBM_ENABLE = 1 , } impl From < CTL1_LBM_A > for bool { # [inline (always)]
fn from (variant : CTL1_LBM_A) -> Self { variant as u8 != 0 } } impl CTL1_LBM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_LBM_A { match self . bits { false => CTL1_LBM_A :: CTL1_LBM_DISABLE , true => CTL1_LBM_A :: CTL1_LBM_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_lbm_disable (& self) -> bool { * self == CTL1_LBM_A :: CTL1_LBM_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_lbm_enable (& self) -> bool { * self == CTL1_LBM_A :: CTL1_LBM_ENABLE } } # [doc = "Field `CTL1_LBM` writer - Loop back mode"]
pub type CTL1_LBM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_LBM_A > ; impl < 'a , REG , const O : u8 > CTL1_LBM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_lbm_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_LBM_A :: CTL1_LBM_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_lbm_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_LBM_A :: CTL1_LBM_ENABLE) } } # [doc = "Field `CTL1_MS` reader - Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0."]
pub type CTL1_MS_R = crate :: BitReader < CTL1_MS_A > ; # [doc = "Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_MS_A { # [doc = "0: DISABLE"]
CTL1_MS_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_MS_ENABLE = 1 , } impl From < CTL1_MS_A > for bool { # [inline (always)]
fn from (variant : CTL1_MS_A) -> Self { variant as u8 != 0 } } impl CTL1_MS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_MS_A { match self . bits { false => CTL1_MS_A :: CTL1_MS_DISABLE , true => CTL1_MS_A :: CTL1_MS_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_ms_disable (& self) -> bool { * self == CTL1_MS_A :: CTL1_MS_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_ms_enable (& self) -> bool { * self == CTL1_MS_A :: CTL1_MS_ENABLE } } # [doc = "Field `CTL1_MS` writer - Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0."]
pub type CTL1_MS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_MS_A > ; impl < 'a , REG , const O : u8 > CTL1_MS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_ms_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_MS_A :: CTL1_MS_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_ms_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_MS_A :: CTL1_MS_ENABLE) } } # [doc = "Field `CTL1_SOD` reader - Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line:"]
pub type CTL1_SOD_R = crate :: BitReader < CTL1_SOD_A > ; # [doc = "Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line:\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_SOD_A { # [doc = "0: DISABLE"]
CTL1_SOD_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_SOD_ENABLE = 1 , } impl From < CTL1_SOD_A > for bool { # [inline (always)]
fn from (variant : CTL1_SOD_A) -> Self { variant as u8 != 0 } } impl CTL1_SOD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_SOD_A { match self . bits { false => CTL1_SOD_A :: CTL1_SOD_DISABLE , true => CTL1_SOD_A :: CTL1_SOD_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_sod_disable (& self) -> bool { * self == CTL1_SOD_A :: CTL1_SOD_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_sod_enable (& self) -> bool { * self == CTL1_SOD_A :: CTL1_SOD_ENABLE } } # [doc = "Field `CTL1_SOD` writer - Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line:"]
pub type CTL1_SOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_SOD_A > ; impl < 'a , REG , const O : u8 > CTL1_SOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_sod_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SOD_A :: CTL1_SOD_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_sod_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SOD_A :: CTL1_SOD_ENABLE) } } # [doc = "Field `CTL1_MSB` reader - MSB first select. Controls the direction of the receive and transmit shift register."]
pub type CTL1_MSB_R = crate :: BitReader < CTL1_MSB_A > ; # [doc = "MSB first select. Controls the direction of the receive and transmit shift register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_MSB_A { # [doc = "0: DISABLE"]
CTL1_MSB_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_MSB_ENABLE = 1 , } impl From < CTL1_MSB_A > for bool { # [inline (always)]
fn from (variant : CTL1_MSB_A) -> Self { variant as u8 != 0 } } impl CTL1_MSB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_MSB_A { match self . bits { false => CTL1_MSB_A :: CTL1_MSB_DISABLE , true => CTL1_MSB_A :: CTL1_MSB_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_msb_disable (& self) -> bool { * self == CTL1_MSB_A :: CTL1_MSB_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_msb_enable (& self) -> bool { * self == CTL1_MSB_A :: CTL1_MSB_ENABLE } } # [doc = "Field `CTL1_MSB` writer - MSB first select. Controls the direction of the receive and transmit shift register."]
pub type CTL1_MSB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_MSB_A > ; impl < 'a , REG , const O : u8 > CTL1_MSB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_msb_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_MSB_A :: CTL1_MSB_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_msb_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_MSB_A :: CTL1_MSB_ENABLE) } } # [doc = "Field `CTL1_PREN` reader - Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set."]
pub type CTL1_PREN_R = crate :: BitReader < CTL1_PREN_A > ; # [doc = "Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_PREN_A { # [doc = "0: DISABLE"]
CTL1_PREN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_PREN_ENABLE = 1 , } impl From < CTL1_PREN_A > for bool { # [inline (always)]
fn from (variant : CTL1_PREN_A) -> Self { variant as u8 != 0 } } impl CTL1_PREN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_PREN_A { match self . bits { false => CTL1_PREN_A :: CTL1_PREN_DISABLE , true => CTL1_PREN_A :: CTL1_PREN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_pren_disable (& self) -> bool { * self == CTL1_PREN_A :: CTL1_PREN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_pren_enable (& self) -> bool { * self == CTL1_PREN_A :: CTL1_PREN_ENABLE } } # [doc = "Field `CTL1_PREN` writer - Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set."]
pub type CTL1_PREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_PREN_A > ; impl < 'a , REG , const O : u8 > CTL1_PREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_pren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PREN_A :: CTL1_PREN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_pren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PREN_A :: CTL1_PREN_ENABLE) } } # [doc = "Field `CTL1_PES` reader - Even Parity Select"]
pub type CTL1_PES_R = crate :: BitReader < CTL1_PES_A > ; # [doc = "Even Parity Select\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_PES_A { # [doc = "0: DISABLE"]
CTL1_PES_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_PES_ENABLE = 1 , } impl From < CTL1_PES_A > for bool { # [inline (always)]
fn from (variant : CTL1_PES_A) -> Self { variant as u8 != 0 } } impl CTL1_PES_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_PES_A { match self . bits { false => CTL1_PES_A :: CTL1_PES_DISABLE , true => CTL1_PES_A :: CTL1_PES_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_pes_disable (& self) -> bool { * self == CTL1_PES_A :: CTL1_PES_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_pes_enable (& self) -> bool { * self == CTL1_PES_A :: CTL1_PES_ENABLE } } # [doc = "Field `CTL1_PES` writer - Even Parity Select"]
pub type CTL1_PES_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_PES_A > ; impl < 'a , REG , const O : u8 > CTL1_PES_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_pes_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PES_A :: CTL1_PES_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_pes_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PES_A :: CTL1_PES_ENABLE) } } # [doc = "Field `CTL1_PBS` reader - Parity Bit Select"]
pub type CTL1_PBS_R = crate :: BitReader < CTL1_PBS_A > ; # [doc = "Parity Bit Select\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_PBS_A { # [doc = "0: DISABLE"]
CTL1_PBS_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_PBS_ENABLE = 1 , } impl From < CTL1_PBS_A > for bool { # [inline (always)]
fn from (variant : CTL1_PBS_A) -> Self { variant as u8 != 0 } } impl CTL1_PBS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_PBS_A { match self . bits { false => CTL1_PBS_A :: CTL1_PBS_DISABLE , true => CTL1_PBS_A :: CTL1_PBS_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_pbs_disable (& self) -> bool { * self == CTL1_PBS_A :: CTL1_PBS_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_pbs_enable (& self) -> bool { * self == CTL1_PBS_A :: CTL1_PBS_ENABLE } } # [doc = "Field `CTL1_PBS` writer - Parity Bit Select"]
pub type CTL1_PBS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_PBS_A > ; impl < 'a , REG , const O : u8 > CTL1_PBS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_pbs_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PBS_A :: CTL1_PBS_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_pbs_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PBS_A :: CTL1_PBS_ENABLE) } } # [doc = "Field `CTL1_PTEN` reader - Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes."]
pub type CTL1_PTEN_R = crate :: BitReader < CTL1_PTEN_A > ; # [doc = "Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_PTEN_A { # [doc = "0: DISABLE"]
CTL1_PTEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_PTEN_ENABLE = 1 , } impl From < CTL1_PTEN_A > for bool { # [inline (always)]
fn from (variant : CTL1_PTEN_A) -> Self { variant as u8 != 0 } } impl CTL1_PTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_PTEN_A { match self . bits { false => CTL1_PTEN_A :: CTL1_PTEN_DISABLE , true => CTL1_PTEN_A :: CTL1_PTEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_pten_disable (& self) -> bool { * self == CTL1_PTEN_A :: CTL1_PTEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_pten_enable (& self) -> bool { * self == CTL1_PTEN_A :: CTL1_PTEN_ENABLE } } # [doc = "Field `CTL1_PTEN` writer - Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes."]
pub type CTL1_PTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_PTEN_A > ; impl < 'a , REG , const O : u8 > CTL1_PTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_pten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PTEN_A :: CTL1_PTEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_pten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_PTEN_A :: CTL1_PTEN_ENABLE) } } # [doc = "Field `CTL1_CDENABLE` reader - Command/Data Mode enable"]
pub type CTL1_CDENABLE_R = crate :: BitReader < CTL1_CDENABLE_A > ; # [doc = "Command/Data Mode enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_CDENABLE_A { # [doc = "0: DISABLE"]
CTL1_CDENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_CDENABLE_ENABLE = 1 , } impl From < CTL1_CDENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL1_CDENABLE_A) -> Self { variant as u8 != 0 } } impl CTL1_CDENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_CDENABLE_A { match self . bits { false => CTL1_CDENABLE_A :: CTL1_CDENABLE_DISABLE , true => CTL1_CDENABLE_A :: CTL1_CDENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_cdenable_disable (& self) -> bool { * self == CTL1_CDENABLE_A :: CTL1_CDENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_cdenable_enable (& self) -> bool { * self == CTL1_CDENABLE_A :: CTL1_CDENABLE_ENABLE } } # [doc = "Field `CTL1_CDENABLE` writer - Command/Data Mode enable"]
pub type CTL1_CDENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_CDENABLE_A > ; impl < 'a , REG , const O : u8 > CTL1_CDENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_cdenable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CDENABLE_A :: CTL1_CDENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_cdenable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CDENABLE_A :: CTL1_CDENABLE_ENABLE) } } # [doc = "Field `CTL1_CDMODE` reader - Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low."]
pub type CTL1_CDMODE_R = crate :: FieldReader < CTL1_CDMODE_A > ; # [doc = "Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL1_CDMODE_A { # [doc = "0: DATA"]
CTL1_CDMODE_DATA = 0 , # [doc = "15: COMMAND"]
CTL1_CDMODE_COMMAND = 15 , } impl From < CTL1_CDMODE_A > for u8 { # [inline (always)]
fn from (variant : CTL1_CDMODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL1_CDMODE_A { type Ux = u8 ; } impl CTL1_CDMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL1_CDMODE_A > { match self . bits { 0 => Some (CTL1_CDMODE_A :: CTL1_CDMODE_DATA) , 15 => Some (CTL1_CDMODE_A :: CTL1_CDMODE_COMMAND) , _ => None , } } # [doc = "DATA"]
# [inline (always)]
pub fn is_ctl1_cdmode_data (& self) -> bool { * self == CTL1_CDMODE_A :: CTL1_CDMODE_DATA } # [doc = "COMMAND"]
# [inline (always)]
pub fn is_ctl1_cdmode_command (& self) -> bool { * self == CTL1_CDMODE_A :: CTL1_CDMODE_COMMAND } } # [doc = "Field `CTL1_CDMODE` writer - Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low."]
pub type CTL1_CDMODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CTL1_CDMODE_A > ; impl < 'a , REG , const O : u8 > CTL1_CDMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DATA"]
# [inline (always)]
pub fn ctl1_cdmode_data (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CDMODE_A :: CTL1_CDMODE_DATA) } # [doc = "COMMAND"]
# [inline (always)]
pub fn ctl1_cdmode_command (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CDMODE_A :: CTL1_CDMODE_COMMAND) } } # [doc = "Field `CTL1_REPEATTX` reader - Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral."]
pub type CTL1_REPEATTX_R = crate :: FieldReader < CTL1_REPEATTX_A > ; # [doc = "Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL1_REPEATTX_A { # [doc = "0: DISABLE"]
CTL1_REPEATTX_DISABLE = 0 , } impl From < CTL1_REPEATTX_A > for u8 { # [inline (always)]
fn from (variant : CTL1_REPEATTX_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL1_REPEATTX_A { type Ux = u8 ; } impl CTL1_REPEATTX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL1_REPEATTX_A > { match self . bits { 0 => Some (CTL1_REPEATTX_A :: CTL1_REPEATTX_DISABLE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_repeattx_disable (& self) -> bool { * self == CTL1_REPEATTX_A :: CTL1_REPEATTX_DISABLE } } # [doc = "Field `CTL1_REPEATTX` writer - Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral."]
pub type CTL1_REPEATTX_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CTL1_REPEATTX_A > ; impl < 'a , REG , const O : u8 > CTL1_REPEATTX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_repeattx_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_REPEATTX_A :: CTL1_REPEATTX_DISABLE) } } # [doc = "Field `CTL1_RXTIMEOUT` reader - Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function."]
pub type CTL1_RXTIMEOUT_R = crate :: FieldReader ; # [doc = "Field `CTL1_RXTIMEOUT` writer - Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function."]
pub type CTL1_RXTIMEOUT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O > ; impl R { # [doc = "Bit 0 - SPI enable"]
# [inline (always)]
pub fn ctl1_enable (& self) -> CTL1_ENABLE_R { CTL1_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Loop back mode"]
# [inline (always)]
pub fn ctl1_lbm (& self) -> CTL1_LBM_R { CTL1_LBM_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0."]
# [inline (always)]
pub fn ctl1_ms (& self) -> CTL1_MS_R { CTL1_MS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line:"]
# [inline (always)]
pub fn ctl1_sod (& self) -> CTL1_SOD_R { CTL1_SOD_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - MSB first select. Controls the direction of the receive and transmit shift register."]
# [inline (always)]
pub fn ctl1_msb (& self) -> CTL1_MSB_R { CTL1_MSB_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set."]
# [inline (always)]
pub fn ctl1_pren (& self) -> CTL1_PREN_R { CTL1_PREN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Even Parity Select"]
# [inline (always)]
pub fn ctl1_pes (& self) -> CTL1_PES_R { CTL1_PES_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Parity Bit Select"]
# [inline (always)]
pub fn ctl1_pbs (& self) -> CTL1_PBS_R { CTL1_PBS_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes."]
# [inline (always)]
pub fn ctl1_pten (& self) -> CTL1_PTEN_R { CTL1_PTEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 11 - Command/Data Mode enable"]
# [inline (always)]
pub fn ctl1_cdenable (& self) -> CTL1_CDENABLE_R { CTL1_CDENABLE_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bits 12:15 - Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low."]
# [inline (always)]
pub fn ctl1_cdmode (& self) -> CTL1_CDMODE_R { CTL1_CDMODE_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:23 - Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral."]
# [inline (always)]
pub fn ctl1_repeattx (& self) -> CTL1_REPEATTX_R { CTL1_REPEATTX_R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bits 24:29 - Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function."]
# [inline (always)]
pub fn ctl1_rxtimeout (& self) -> CTL1_RXTIMEOUT_R { CTL1_RXTIMEOUT_R :: new (((self . bits >> 24) & 0x3f) as u8) } } impl W { # [doc = "Bit 0 - SPI enable"]
# [inline (always)]
# [must_use]
pub fn ctl1_enable (& mut self) -> CTL1_ENABLE_W < CTL1_SPEC , 0 > { CTL1_ENABLE_W :: new (self) } # [doc = "Bit 1 - Loop back mode"]
# [inline (always)]
# [must_use]
pub fn ctl1_lbm (& mut self) -> CTL1_LBM_W < CTL1_SPEC , 1 > { CTL1_LBM_W :: new (self) } # [doc = "Bit 2 - Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0."]
# [inline (always)]
# [must_use]
pub fn ctl1_ms (& mut self) -> CTL1_MS_W < CTL1_SPEC , 2 > { CTL1_MS_W :: new (self) } # [doc = "Bit 3 - Peripheral-mode: Data output disabled This bit is relevant only in the peripheral mode, CTL1.MS=1. In multiple-peripheral systems, it is possible for an SPI controller to broadcast a message to all peripherals in the system while ensuring that only one peripheral drives data onto its serial output line. In such systems the MISO lines from multiple peripherals could be tied together. To operate in such systems, this bitfield can be set if the SPI peripheral is not supposed to drive the MISO line:"]
# [inline (always)]
# [must_use]
pub fn ctl1_sod (& mut self) -> CTL1_SOD_W < CTL1_SPEC , 3 > { CTL1_SOD_W :: new (self) } # [doc = "Bit 4 - MSB first select. Controls the direction of the receive and transmit shift register."]
# [inline (always)]
# [must_use]
pub fn ctl1_msb (& mut self) -> CTL1_MSB_W < CTL1_SPEC , 4 > { CTL1_MSB_W :: new (self) } # [doc = "Bit 5 - Parity receive enable If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set."]
# [inline (always)]
# [must_use]
pub fn ctl1_pren (& mut self) -> CTL1_PREN_W < CTL1_SPEC , 5 > { CTL1_PREN_W :: new (self) } # [doc = "Bit 6 - Even Parity Select"]
# [inline (always)]
# [must_use]
pub fn ctl1_pes (& mut self) -> CTL1_PES_W < CTL1_SPEC , 6 > { CTL1_PES_W :: new (self) } # [doc = "Bit 7 - Parity Bit Select"]
# [inline (always)]
# [must_use]
pub fn ctl1_pbs (& mut self) -> CTL1_PBS_W < CTL1_SPEC , 7 > { CTL1_PBS_W :: new (self) } # [doc = "Bit 8 - Parity transmit enable If enabled, parity transmission will be done for both controller and peripheral modes."]
# [inline (always)]
# [must_use]
pub fn ctl1_pten (& mut self) -> CTL1_PTEN_W < CTL1_SPEC , 8 > { CTL1_PTEN_W :: new (self) } # [doc = "Bit 11 - Command/Data Mode enable"]
# [inline (always)]
# [must_use]
pub fn ctl1_cdenable (& mut self) -> CTL1_CDENABLE_W < CTL1_SPEC , 11 > { CTL1_CDENABLE_W :: new (self) } # [doc = "Bits 12:15 - Command/Data Mode Value When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low."]
# [inline (always)]
# [must_use]
pub fn ctl1_cdmode (& mut self) -> CTL1_CDMODE_W < CTL1_SPEC , 12 > { CTL1_CDMODE_W :: new (self) } # [doc = "Bits 16:23 - Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral."]
# [inline (always)]
# [must_use]
pub fn ctl1_repeattx (& mut self) -> CTL1_REPEATTX_W < CTL1_SPEC , 16 > { CTL1_REPEATTX_W :: new (self) } # [doc = "Bits 24:29 - Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function."]
# [inline (always)]
# [must_use]
pub fn ctl1_rxtimeout (& mut self) -> CTL1_RXTIMEOUT_W < CTL1_SPEC , 24 > { CTL1_RXTIMEOUT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SPI control register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL1_SPEC ; impl crate :: RegisterSpec for CTL1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl1::R`](R) reader structure"]
impl crate :: Readable for CTL1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl1::W`](W) writer structure"]
impl crate :: Writable for CTL1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL1 to value 0x04"]
impl crate :: Resettable for CTL1_SPEC { const RESET_VALUE : Self :: Ux = 0x04 ; } } # [doc = "CLKCTL (rw) register accessor: Clock prescaler and divider register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkctl`]
module"]
pub type CLKCTL = crate :: Reg < clkctl :: CLKCTL_SPEC > ; # [doc = "Clock prescaler and divider register."]
pub mod clkctl { # [doc = "Register `CLKCTL` reader"]
pub type R = crate :: R < CLKCTL_SPEC > ; # [doc = "Register `CLKCTL` writer"]
pub type W = crate :: W < CLKCTL_SPEC > ; # [doc = "Field `CLKCTL_SCR` reader - Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023."]
pub type CLKCTL_SCR_R = crate :: FieldReader < u16 > ; # [doc = "Field `CLKCTL_SCR` writer - Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023."]
pub type CLKCTL_SCR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `CLKCTL_DSAMPLE` reader - Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations."]
pub type CLKCTL_DSAMPLE_R = crate :: FieldReader ; # [doc = "Field `CLKCTL_DSAMPLE` writer - Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations."]
pub type CLKCTL_DSAMPLE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bits 0:9 - Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023."]
# [inline (always)]
pub fn clkctl_scr (& self) -> CLKCTL_SCR_R { CLKCTL_SCR_R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bits 28:31 - Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations."]
# [inline (always)]
pub fn clkctl_dsample (& self) -> CLKCTL_DSAMPLE_R { CLKCTL_DSAMPLE_R :: new (((self . bits >> 28) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:9 - Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023."]
# [inline (always)]
# [must_use]
pub fn clkctl_scr (& mut self) -> CLKCTL_SCR_W < CLKCTL_SPEC , 0 > { CLKCTL_SCR_W :: new (self) } # [doc = "Bits 28:31 - Delayed sampling value. In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations."]
# [inline (always)]
# [must_use]
pub fn clkctl_dsample (& mut self) -> CLKCTL_DSAMPLE_W < CLKCTL_SPEC , 28 > { CLKCTL_DSAMPLE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock prescaler and divider register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCTL_SPEC ; impl crate :: RegisterSpec for CLKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkctl::R`](R) reader structure"]
impl crate :: Readable for CLKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkctl::W`](W) writer structure"]
impl crate :: Writable for CLKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCTL to value 0"]
impl crate :: Resettable for CLKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IFLS (rw) register accessor: UART Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifls`]
module"]
pub type IFLS = crate :: Reg < ifls :: IFLS_SPEC > ; # [doc = "UART Interrupt FIFO Level Select Register"]
pub mod ifls { # [doc = "Register `IFLS` reader"]
pub type R = crate :: R < IFLS_SPEC > ; # [doc = "Register `IFLS` writer"]
pub type W = crate :: W < IFLS_SPEC > ; # [doc = "Field `IFLS_TXIFLSEL` reader - SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:"]
pub type IFLS_TXIFLSEL_R = crate :: FieldReader < IFLS_TXIFLSEL_A > ; # [doc = "SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFLS_TXIFLSEL_A { # [doc = "0: LVL_OFF"]
IFLS_TXIFLSEL_LVL_OFF = 0 , # [doc = "1: LVL_3_4"]
IFLS_TXIFLSEL_LVL_3_4 = 1 , # [doc = "2: LVL_1_2"]
IFLS_TXIFLSEL_LVL_1_2 = 2 , # [doc = "3: LVL_1_4"]
IFLS_TXIFLSEL_LVL_1_4 = 3 , # [doc = "4: LVL_RES4"]
IFLS_TXIFLSEL_LVL_RES4 = 4 , # [doc = "5: LVL_EMPTY"]
IFLS_TXIFLSEL_LVL_EMPTY = 5 , # [doc = "6: LVL_RES6"]
IFLS_TXIFLSEL_LVL_RES6 = 6 , # [doc = "7: LEVEL_1"]
IFLS_TXIFLSEL_LEVEL_1 = 7 , } impl From < IFLS_TXIFLSEL_A > for u8 { # [inline (always)]
fn from (variant : IFLS_TXIFLSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFLS_TXIFLSEL_A { type Ux = u8 ; } impl IFLS_TXIFLSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFLS_TXIFLSEL_A { match self . bits { 0 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_OFF , 1 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_3_4 , 2 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_1_2 , 3 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_1_4 , 4 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_RES4 , 5 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_EMPTY , 6 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_RES6 , 7 => IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LEVEL_1 , _ => unreachable ! () , } } # [doc = "LVL_OFF"]
# [inline (always)]
pub fn is_ifls_txiflsel_lvl_off (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_OFF } # [doc = "LVL_3_4"]
# [inline (always)]
pub fn is_ifls_txiflsel_lvl_3_4 (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_3_4 } # [doc = "LVL_1_2"]
# [inline (always)]
pub fn is_ifls_txiflsel_lvl_1_2 (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_1_2 } # [doc = "LVL_1_4"]
# [inline (always)]
pub fn is_ifls_txiflsel_lvl_1_4 (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_1_4 } # [doc = "LVL_RES4"]
# [inline (always)]
pub fn is_ifls_txiflsel_lvl_res4 (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_RES4 } # [doc = "LVL_EMPTY"]
# [inline (always)]
pub fn is_ifls_txiflsel_lvl_empty (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_EMPTY } # [doc = "LVL_RES6"]
# [inline (always)]
pub fn is_ifls_txiflsel_lvl_res6 (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_RES6 } # [doc = "LEVEL_1"]
# [inline (always)]
pub fn is_ifls_txiflsel_level_1 (& self) -> bool { * self == IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LEVEL_1 } } # [doc = "Field `IFLS_TXIFLSEL` writer - SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:"]
pub type IFLS_TXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , IFLS_TXIFLSEL_A > ; impl < 'a , REG , const O : u8 > IFLS_TXIFLSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LVL_OFF"]
# [inline (always)]
pub fn ifls_txiflsel_lvl_off (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_OFF) } # [doc = "LVL_3_4"]
# [inline (always)]
pub fn ifls_txiflsel_lvl_3_4 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_3_4) } # [doc = "LVL_1_2"]
# [inline (always)]
pub fn ifls_txiflsel_lvl_1_2 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_1_2) } # [doc = "LVL_1_4"]
# [inline (always)]
pub fn ifls_txiflsel_lvl_1_4 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_1_4) } # [doc = "LVL_RES4"]
# [inline (always)]
pub fn ifls_txiflsel_lvl_res4 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_RES4) } # [doc = "LVL_EMPTY"]
# [inline (always)]
pub fn ifls_txiflsel_lvl_empty (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_EMPTY) } # [doc = "LVL_RES6"]
# [inline (always)]
pub fn ifls_txiflsel_lvl_res6 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LVL_RES6) } # [doc = "LEVEL_1"]
# [inline (always)]
pub fn ifls_txiflsel_level_1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_TXIFLSEL_A :: IFLS_TXIFLSEL_LEVEL_1) } } # [doc = "Field `IFLS_RXIFLSEL` reader - SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:"]
pub type IFLS_RXIFLSEL_R = crate :: FieldReader < IFLS_RXIFLSEL_A > ; # [doc = "SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFLS_RXIFLSEL_A { # [doc = "0: LVL_OFF"]
IFLS_RXIFLSEL_LVL_OFF = 0 , # [doc = "1: LVL_1_4"]
IFLS_RXIFLSEL_LVL_1_4 = 1 , # [doc = "2: LVL_1_2"]
IFLS_RXIFLSEL_LVL_1_2 = 2 , # [doc = "3: LVL_3_4"]
IFLS_RXIFLSEL_LVL_3_4 = 3 , # [doc = "4: LVL_RES4"]
IFLS_RXIFLSEL_LVL_RES4 = 4 , # [doc = "5: LVL_FULL"]
IFLS_RXIFLSEL_LVL_FULL = 5 , # [doc = "6: LVL_RES6"]
IFLS_RXIFLSEL_LVL_RES6 = 6 , # [doc = "7: LEVEL_1"]
IFLS_RXIFLSEL_LEVEL_1 = 7 , } impl From < IFLS_RXIFLSEL_A > for u8 { # [inline (always)]
fn from (variant : IFLS_RXIFLSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFLS_RXIFLSEL_A { type Ux = u8 ; } impl IFLS_RXIFLSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFLS_RXIFLSEL_A { match self . bits { 0 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_OFF , 1 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_1_4 , 2 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_1_2 , 3 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_3_4 , 4 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_RES4 , 5 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_FULL , 6 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_RES6 , 7 => IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LEVEL_1 , _ => unreachable ! () , } } # [doc = "LVL_OFF"]
# [inline (always)]
pub fn is_ifls_rxiflsel_lvl_off (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_OFF } # [doc = "LVL_1_4"]
# [inline (always)]
pub fn is_ifls_rxiflsel_lvl_1_4 (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_1_4 } # [doc = "LVL_1_2"]
# [inline (always)]
pub fn is_ifls_rxiflsel_lvl_1_2 (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_1_2 } # [doc = "LVL_3_4"]
# [inline (always)]
pub fn is_ifls_rxiflsel_lvl_3_4 (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_3_4 } # [doc = "LVL_RES4"]
# [inline (always)]
pub fn is_ifls_rxiflsel_lvl_res4 (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_RES4 } # [doc = "LVL_FULL"]
# [inline (always)]
pub fn is_ifls_rxiflsel_lvl_full (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_FULL } # [doc = "LVL_RES6"]
# [inline (always)]
pub fn is_ifls_rxiflsel_lvl_res6 (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_RES6 } # [doc = "LEVEL_1"]
# [inline (always)]
pub fn is_ifls_rxiflsel_level_1 (& self) -> bool { * self == IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LEVEL_1 } } # [doc = "Field `IFLS_RXIFLSEL` writer - SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:"]
pub type IFLS_RXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , IFLS_RXIFLSEL_A > ; impl < 'a , REG , const O : u8 > IFLS_RXIFLSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LVL_OFF"]
# [inline (always)]
pub fn ifls_rxiflsel_lvl_off (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_OFF) } # [doc = "LVL_1_4"]
# [inline (always)]
pub fn ifls_rxiflsel_lvl_1_4 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_1_4) } # [doc = "LVL_1_2"]
# [inline (always)]
pub fn ifls_rxiflsel_lvl_1_2 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_1_2) } # [doc = "LVL_3_4"]
# [inline (always)]
pub fn ifls_rxiflsel_lvl_3_4 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_3_4) } # [doc = "LVL_RES4"]
# [inline (always)]
pub fn ifls_rxiflsel_lvl_res4 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_RES4) } # [doc = "LVL_FULL"]
# [inline (always)]
pub fn ifls_rxiflsel_lvl_full (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_FULL) } # [doc = "LVL_RES6"]
# [inline (always)]
pub fn ifls_rxiflsel_lvl_res6 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LVL_RES6) } # [doc = "LEVEL_1"]
# [inline (always)]
pub fn ifls_rxiflsel_level_1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFLS_RXIFLSEL_A :: IFLS_RXIFLSEL_LEVEL_1) } } impl R { # [doc = "Bits 0:2 - SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:"]
# [inline (always)]
pub fn ifls_txiflsel (& self) -> IFLS_TXIFLSEL_R { IFLS_TXIFLSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 3:5 - SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:"]
# [inline (always)]
pub fn ifls_rxiflsel (& self) -> IFLS_RXIFLSEL_R { IFLS_RXIFLSEL_R :: new (((self . bits >> 3) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:"]
# [inline (always)]
# [must_use]
pub fn ifls_txiflsel (& mut self) -> IFLS_TXIFLSEL_W < IFLS_SPEC , 0 > { IFLS_TXIFLSEL_W :: new (self) } # [doc = "Bits 3:5 - SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:"]
# [inline (always)]
# [must_use]
pub fn ifls_rxiflsel (& mut self) -> IFLS_RXIFLSEL_W < IFLS_SPEC , 3 > { IFLS_RXIFLSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IFLS_SPEC ; impl crate :: RegisterSpec for IFLS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifls::R`](R) reader structure"]
impl crate :: Readable for IFLS_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"]
impl crate :: Writable for IFLS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFLS to value 0x12"]
impl crate :: Resettable for IFLS_SPEC { const RESET_VALUE : Self :: Ux = 0x12 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_TFE` reader - Transmit FIFO empty."]
pub type STAT_TFE_R = crate :: BitReader < STAT_TFE_A > ; # [doc = "Transmit FIFO empty.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_TFE_A { # [doc = "0: NOT_EMPTY"]
STAT_TFE_NOT_EMPTY = 0 , # [doc = "1: EMPTY"]
STAT_TFE_EMPTY = 1 , } impl From < STAT_TFE_A > for bool { # [inline (always)]
fn from (variant : STAT_TFE_A) -> Self { variant as u8 != 0 } } impl STAT_TFE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_TFE_A { match self . bits { false => STAT_TFE_A :: STAT_TFE_NOT_EMPTY , true => STAT_TFE_A :: STAT_TFE_EMPTY , } } # [doc = "NOT_EMPTY"]
# [inline (always)]
pub fn is_stat_tfe_not_empty (& self) -> bool { * self == STAT_TFE_A :: STAT_TFE_NOT_EMPTY } # [doc = "EMPTY"]
# [inline (always)]
pub fn is_stat_tfe_empty (& self) -> bool { * self == STAT_TFE_A :: STAT_TFE_EMPTY } } # [doc = "Field `STAT_TNF` reader - Transmit FIFO not full"]
pub type STAT_TNF_R = crate :: BitReader < STAT_TNF_A > ; # [doc = "Transmit FIFO not full\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_TNF_A { # [doc = "0: FULL"]
STAT_TNF_FULL = 0 , # [doc = "1: NOT_FULL"]
STAT_TNF_NOT_FULL = 1 , } impl From < STAT_TNF_A > for bool { # [inline (always)]
fn from (variant : STAT_TNF_A) -> Self { variant as u8 != 0 } } impl STAT_TNF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_TNF_A { match self . bits { false => STAT_TNF_A :: STAT_TNF_FULL , true => STAT_TNF_A :: STAT_TNF_NOT_FULL , } } # [doc = "FULL"]
# [inline (always)]
pub fn is_stat_tnf_full (& self) -> bool { * self == STAT_TNF_A :: STAT_TNF_FULL } # [doc = "NOT_FULL"]
# [inline (always)]
pub fn is_stat_tnf_not_full (& self) -> bool { * self == STAT_TNF_A :: STAT_TNF_NOT_FULL } } # [doc = "Field `STAT_RFE` reader - Receive FIFO empty."]
pub type STAT_RFE_R = crate :: BitReader < STAT_RFE_A > ; # [doc = "Receive FIFO empty.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RFE_A { # [doc = "0: NOT_EMPTY"]
STAT_RFE_NOT_EMPTY = 0 , # [doc = "1: EMPTY"]
STAT_RFE_EMPTY = 1 , } impl From < STAT_RFE_A > for bool { # [inline (always)]
fn from (variant : STAT_RFE_A) -> Self { variant as u8 != 0 } } impl STAT_RFE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RFE_A { match self . bits { false => STAT_RFE_A :: STAT_RFE_NOT_EMPTY , true => STAT_RFE_A :: STAT_RFE_EMPTY , } } # [doc = "NOT_EMPTY"]
# [inline (always)]
pub fn is_stat_rfe_not_empty (& self) -> bool { * self == STAT_RFE_A :: STAT_RFE_NOT_EMPTY } # [doc = "EMPTY"]
# [inline (always)]
pub fn is_stat_rfe_empty (& self) -> bool { * self == STAT_RFE_A :: STAT_RFE_EMPTY } } # [doc = "Field `STAT_RNF` reader - Receive FIFO not full"]
pub type STAT_RNF_R = crate :: BitReader < STAT_RNF_A > ; # [doc = "Receive FIFO not full\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RNF_A { # [doc = "0: FULL"]
STAT_RNF_FULL = 0 , # [doc = "1: NOT_FULL"]
STAT_RNF_NOT_FULL = 1 , } impl From < STAT_RNF_A > for bool { # [inline (always)]
fn from (variant : STAT_RNF_A) -> Self { variant as u8 != 0 } } impl STAT_RNF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RNF_A { match self . bits { false => STAT_RNF_A :: STAT_RNF_FULL , true => STAT_RNF_A :: STAT_RNF_NOT_FULL , } } # [doc = "FULL"]
# [inline (always)]
pub fn is_stat_rnf_full (& self) -> bool { * self == STAT_RNF_A :: STAT_RNF_FULL } # [doc = "NOT_FULL"]
# [inline (always)]
pub fn is_stat_rnf_not_full (& self) -> bool { * self == STAT_RNF_A :: STAT_RNF_NOT_FULL } } # [doc = "Field `STAT_BUSY` reader - Busy"]
pub type STAT_BUSY_R = crate :: BitReader < STAT_BUSY_A > ; # [doc = "Busy\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_BUSY_A { # [doc = "0: IDLE"]
STAT_BUSY_IDLE = 0 , # [doc = "1: ACTIVE"]
STAT_BUSY_ACTIVE = 1 , } impl From < STAT_BUSY_A > for bool { # [inline (always)]
fn from (variant : STAT_BUSY_A) -> Self { variant as u8 != 0 } } impl STAT_BUSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_BUSY_A { match self . bits { false => STAT_BUSY_A :: STAT_BUSY_IDLE , true => STAT_BUSY_A :: STAT_BUSY_ACTIVE , } } # [doc = "IDLE"]
# [inline (always)]
pub fn is_stat_busy_idle (& self) -> bool { * self == STAT_BUSY_A :: STAT_BUSY_IDLE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_stat_busy_active (& self) -> bool { * self == STAT_BUSY_A :: STAT_BUSY_ACTIVE } } impl R { # [doc = "Bit 0 - Transmit FIFO empty."]
# [inline (always)]
pub fn stat_tfe (& self) -> STAT_TFE_R { STAT_TFE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transmit FIFO not full"]
# [inline (always)]
pub fn stat_tnf (& self) -> STAT_TNF_R { STAT_TNF_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Receive FIFO empty."]
# [inline (always)]
pub fn stat_rfe (& self) -> STAT_RFE_R { STAT_RFE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Receive FIFO not full"]
# [inline (always)]
pub fn stat_rnf (& self) -> STAT_RNF_R { STAT_RNF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Busy"]
# [inline (always)]
pub fn stat_busy (& self) -> STAT_BUSY_R { STAT_BUSY_R :: new (((self . bits >> 4) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RXDATA (r) register accessor: RXDATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdata`]
module"]
pub type RXDATA = crate :: Reg < rxdata :: RXDATA_SPEC > ; # [doc = "RXDATA Register"]
pub mod rxdata { # [doc = "Register `RXDATA` reader"]
pub type R = crate :: R < RXDATA_SPEC > ; # [doc = "Field `RXDATA_DATA` reader - Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer."]
pub type RXDATA_DATA_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - Received Data When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer."]
# [inline (always)]
pub fn rxdata_data (& self) -> RXDATA_DATA_R { RXDATA_DATA_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "RXDATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RXDATA_SPEC ; impl crate :: RegisterSpec for RXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rxdata::R`](R) reader structure"]
impl crate :: Readable for RXDATA_SPEC { } # [doc = "`reset()` method sets RXDATA to value 0"]
impl crate :: Resettable for RXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TXDATA (rw) register accessor: TXDATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdata::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txdata`]
module"]
pub type TXDATA = crate :: Reg < txdata :: TXDATA_SPEC > ; # [doc = "TXDATA Register"]
pub mod txdata { # [doc = "Register `TXDATA` reader"]
pub type R = crate :: R < TXDATA_SPEC > ; # [doc = "Register `TXDATA` writer"]
pub type W = crate :: W < TXDATA_SPEC > ; # [doc = "Field `TXDATA_DATA` reader - Transmit Data WWhen read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits."]
pub type TXDATA_DATA_R = crate :: FieldReader < u16 > ; # [doc = "Field `TXDATA_DATA` writer - Transmit Data WWhen read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits."]
pub type TXDATA_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Transmit Data WWhen read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits."]
# [inline (always)]
pub fn txdata_data (& self) -> TXDATA_DATA_R { TXDATA_DATA_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Transmit Data WWhen read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits."]
# [inline (always)]
# [must_use]
pub fn txdata_data (& mut self) -> TXDATA_DATA_W < TXDATA_SPEC , 0 > { TXDATA_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "TXDATA Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TXDATA_SPEC ; impl crate :: RegisterSpec for TXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`txdata::R`](R) reader structure"]
impl crate :: Readable for TXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`txdata::W`](W) writer structure"]
impl crate :: Writable for TXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TXDATA to value 0"]
impl crate :: Resettable for TXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct I2C0 { _marker : PhantomData < * const () > } unsafe impl Send for I2C0 { } impl I2C0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const i2c0 :: RegisterBlock = 0x400f_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const i2c0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for I2C0 { type Target = i2c0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for I2C0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("I2C0") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod i2c0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , # [doc = "0x808 - Peripheral Clock Configuration Register"]
pub clkcfg : CLKCFG , _reserved3 : [u8 ; 0x08]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved4 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , # [doc = "0x1004 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved6 : [u8 ; 0x10]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub int_event0_iidx : INT_EVENT0_IIDX , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub int_event0_imask : INT_EVENT0_IMASK , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub int_event0_ris : INT_EVENT0_RIS , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub int_event0_mis : INT_EVENT0_MIS , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub int_event0_iset : INT_EVENT0_ISET , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub int_event0_iclr : INT_EVENT0_ICLR , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1050 - Interrupt index"]
pub int_event1_iidx : INT_EVENT1_IIDX , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1058 - Interrupt mask"]
pub int_event1_imask : INT_EVENT1_IMASK , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1060 - Raw interrupt status"]
pub int_event1_ris : INT_EVENT1_RIS , _reserved16 : [u8 ; 0x04]
, # [doc = "0x1068 - Masked interrupt status"]
pub int_event1_mis : INT_EVENT1_MIS , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1070 - Interrupt set"]
pub int_event1_iset : INT_EVENT1_ISET , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1078 - Interrupt clear"]
pub int_event1_iclr : INT_EVENT1_ICLR , _reserved19 : [u8 ; 0x04]
, # [doc = "0x1080 - Interrupt index"]
pub int_event2_iidx : INT_EVENT2_IIDX , _reserved20 : [u8 ; 0x04]
, # [doc = "0x1088 - Interrupt mask"]
pub int_event2_imask : INT_EVENT2_IMASK , _reserved21 : [u8 ; 0x04]
, # [doc = "0x1090 - Raw interrupt status"]
pub int_event2_ris : INT_EVENT2_RIS , _reserved22 : [u8 ; 0x04]
, # [doc = "0x1098 - Masked interrupt status"]
pub int_event2_mis : INT_EVENT2_MIS , _reserved23 : [u8 ; 0x04]
, # [doc = "0x10a0 - Interrupt set"]
pub int_event2_iset : INT_EVENT2_ISET , _reserved24 : [u8 ; 0x04]
, # [doc = "0x10a8 - Interrupt clear"]
pub int_event2_iclr : INT_EVENT2_ICLR , _reserved25 : [u8 ; 0x34]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved26 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , _reserved27 : [u8 ; 0x0100]
, # [doc = "0x1200 - I2C Glitch Filter Control"]
pub gfctl : GFCTL , # [doc = "0x1204 - I2C Timeout Count Control Register"]
pub timeout_ctl : TIMEOUT_CTL , # [doc = "0x1208 - I2C Timeout Count Register"]
pub timeout_cnt : TIMEOUT_CNT , _reserved30 : [u8 ; 0x04]
, # [doc = "0x1210 - I2C Master Slave Address Register"]
pub msa : MSA , # [doc = "0x1214 - I2C Master Control Register"]
pub mctr : MCTR , # [doc = "0x1218 - I2C Master Status Register"]
pub msr : MSR , # [doc = "0x121c - I2C Master RXData"]
pub mrxdata : MRXDATA , # [doc = "0x1220 - I2C Master TXData"]
pub mtxdata : MTXDATA , # [doc = "0x1224 - I2C Master Timer Period"]
pub mtpr : MTPR , # [doc = "0x1228 - I2C Master Configuration"]
pub mcr : MCR , _reserved37 : [u8 ; 0x08]
, # [doc = "0x1234 - I2C Master Bus Monitor"]
pub mbmon : MBMON , # [doc = "0x1238 - I2C Master FIFO Control"]
pub mfifoctl : MFIFOCTL , # [doc = "0x123c - I2C Master FIFO Status Register"]
pub mfifosr : MFIFOSR , # [doc = "0x1240 - I2C master PEC control register"]
pub master_i2cpecctl : MASTER_I2CPECCTL , # [doc = "0x1244 - I2C master PEC status register"]
pub master_pecsr : MASTER_PECSR , _reserved42 : [u8 ; 0x08]
, # [doc = "0x1250 - I2C Slave Own Address"]
pub soar : SOAR , # [doc = "0x1254 - I2C Slave Own Address 2"]
pub soar2 : SOAR2 , # [doc = "0x1258 - I2C Slave Control Register"]
pub sctr : SCTR , # [doc = "0x125c - I2C Slave Status Register"]
pub ssr : SSR , # [doc = "0x1260 - I2C Slave RXData"]
pub srxdata : SRXDATA , # [doc = "0x1264 - I2C Slave TXData"]
pub stxdata : STXDATA , # [doc = "0x1268 - I2C Slave ACK Control"]
pub sackctl : SACKCTL , # [doc = "0x126c - I2C Slave FIFO Control"]
pub sfifoctl : SFIFOCTL , # [doc = "0x1270 - I2C Slave FIFO Status Register"]
pub sfifosr : SFIFOSR , # [doc = "0x1274 - I2C Slave PEC control register"]
pub slave_pecctl : SLAVE_PECCTL , # [doc = "0x1278 - I2C slave PEC status register"]
pub slave_pecsr : SLAVE_PECSR , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKCFG (rw) register accessor: Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkcfg`]
module"]
pub type CLKCFG = crate :: Reg < clkcfg :: CLKCFG_SPEC > ; # [doc = "Peripheral Clock Configuration Register"]
pub mod clkcfg { # [doc = "Register `CLKCFG` reader"]
pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"]
pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"]
CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"]
CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"]
pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"]
# [inline (always)]
pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
# [must_use]
pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"]
# [inline (always)]
# [must_use]
pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"]
impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"]
impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"]
impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iidx`]
module"]
pub type INT_EVENT0_IIDX = crate :: Reg < int_event0_iidx :: INT_EVENT0_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event0_iidx { # [doc = "Register `INT_EVENT0_IIDX` reader"]
pub type R = crate :: R < INT_EVENT0_IIDX_SPEC > ; # [doc = "Field `INT_EVENT0_IIDX_STAT` reader - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
pub type INT_EVENT0_IIDX_STAT_R = crate :: FieldReader < INT_EVENT0_IIDX_STAT_A > ; # [doc = "I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: MRXDONEFG"]
INT_EVENT0_IIDX_STAT_MRXDONEFG = 1 , # [doc = "2: MTXDONEFG"]
INT_EVENT0_IIDX_STAT_MTXDONEFG = 2 , # [doc = "3: MRXFIFOTRG"]
INT_EVENT0_IIDX_STAT_MRXFIFOTRG = 3 , # [doc = "4: MTXFIFOTRG"]
INT_EVENT0_IIDX_STAT_MTXFIFOTRG = 4 , # [doc = "5: MRXFIFOFULL"]
INT_EVENT0_IIDX_STAT_MRXFIFOFULL = 5 , # [doc = "6: MTX_EMPTY"]
INT_EVENT0_IIDX_STAT_MTX_EMPTY = 6 , # [doc = "8: MNACKFG"]
INT_EVENT0_IIDX_STAT_MNACKFG = 8 , # [doc = "9: MSTARTFG"]
INT_EVENT0_IIDX_STAT_MSTARTFG = 9 , # [doc = "10: MSTOPFG"]
INT_EVENT0_IIDX_STAT_MSTOPFG = 10 , # [doc = "11: MARBLOSTFG"]
INT_EVENT0_IIDX_STAT_MARBLOSTFG = 11 , # [doc = "12: MDMA_DONE1_CH2"]
INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2 = 12 , # [doc = "13: MDMA_DONE1_CH3"]
INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3 = 13 , # [doc = "14: MPEC_RX_ERR"]
INT_EVENT0_IIDX_STAT_MPEC_RX_ERR = 14 , # [doc = "15: TIMEOUTA"]
INT_EVENT0_IIDX_STAT_TIMEOUTA = 15 , # [doc = "16: TIMEOUTB"]
INT_EVENT0_IIDX_STAT_TIMEOUTB = 16 , # [doc = "17: SRXDONEFG"]
INT_EVENT0_IIDX_STAT_SRXDONEFG = 17 , # [doc = "18: STXDONEFG"]
INT_EVENT0_IIDX_STAT_STXDONEFG = 18 , # [doc = "19: SRXFIFOTRG"]
INT_EVENT0_IIDX_STAT_SRXFIFOTRG = 19 , # [doc = "20: STXFIFOTRG"]
INT_EVENT0_IIDX_STAT_STXFIFOTRG = 20 , # [doc = "21: SRXFIFOFULL"]
INT_EVENT0_IIDX_STAT_SRXFIFOFULL = 21 , # [doc = "22: STXEMPTY"]
INT_EVENT0_IIDX_STAT_STXEMPTY = 22 , # [doc = "23: SSTARTFG"]
INT_EVENT0_IIDX_STAT_SSTARTFG = 23 , # [doc = "24: SSTOPFG"]
INT_EVENT0_IIDX_STAT_SSTOPFG = 24 , # [doc = "25: SGENCALL"]
INT_EVENT0_IIDX_STAT_SGENCALL = 25 , # [doc = "26: SDMA_DONE1_CH2"]
INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2 = 26 , # [doc = "27: SDMA_DONE1_CH3"]
INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3 = 27 , # [doc = "28: SPEC_RX_ERR"]
INT_EVENT0_IIDX_STAT_SPEC_RX_ERR = 28 , # [doc = "29: STX_UNFL"]
INT_EVENT0_IIDX_STAT_STX_UNFL = 29 , # [doc = "30: SRX_OVFL"]
INT_EVENT0_IIDX_STAT_SRX_OVFL = 30 , # [doc = "31: SARBLOST"]
INT_EVENT0_IIDX_STAT_SARBLOST = 31 , # [doc = "32: INTR_OVFL"]
INT_EVENT0_IIDX_STAT_INTR_OVFL = 32 , } impl From < INT_EVENT0_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT0_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXDONEFG) , 2 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXDONEFG) , 3 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOTRG) , 4 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXFIFOTRG) , 5 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOFULL) , 6 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTX_EMPTY) , 8 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MNACKFG) , 9 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTARTFG) , 10 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTOPFG) , 11 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MARBLOSTFG) , 12 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2) , 13 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3) , 14 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MPEC_RX_ERR) , 15 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTA) , 16 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTB) , 17 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXDONEFG) , 18 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXDONEFG) , 19 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOTRG) , 20 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXFIFOTRG) , 21 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOFULL) , 22 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXEMPTY) , 23 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTARTFG) , 24 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTOPFG) , 25 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SGENCALL) , 26 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2) , 27 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3) , 28 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SPEC_RX_ERR) , 29 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STX_UNFL) , 30 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRX_OVFL) , 31 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SARBLOST) , 32 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_INTR_OVFL) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR } # [doc = "MRXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mrxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXDONEFG } # [doc = "MTXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mtxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXDONEFG } # [doc = "MRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mrxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOTRG } # [doc = "MTXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mtxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXFIFOTRG } # [doc = "MRXFIFOFULL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mrxfifofull (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOFULL } # [doc = "MTX_EMPTY"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mtx_empty (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTX_EMPTY } # [doc = "MNACKFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mnackfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MNACKFG } # [doc = "MSTARTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mstartfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTARTFG } # [doc = "MSTOPFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mstopfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTOPFG } # [doc = "MARBLOSTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_marblostfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MARBLOSTFG } # [doc = "MDMA_DONE1_CH2"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mdma_done1_ch2 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2 } # [doc = "MDMA_DONE1_CH3"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mdma_done1_ch3 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3 } # [doc = "MPEC_RX_ERR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mpec_rx_err (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MPEC_RX_ERR } # [doc = "TIMEOUTA"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_timeouta (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTA } # [doc = "TIMEOUTB"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_timeoutb (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTB } # [doc = "SRXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXDONEFG } # [doc = "STXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXDONEFG } # [doc = "SRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOTRG } # [doc = "STXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXFIFOTRG } # [doc = "SRXFIFOFULL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srxfifofull (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOFULL } # [doc = "STXEMPTY"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stxempty (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXEMPTY } # [doc = "SSTARTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sstartfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTARTFG } # [doc = "SSTOPFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sstopfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTOPFG } # [doc = "SGENCALL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sgencall (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SGENCALL } # [doc = "SDMA_DONE1_CH2"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sdma_done1_ch2 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2 } # [doc = "SDMA_DONE1_CH3"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sdma_done1_ch3 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3 } # [doc = "SPEC_RX_ERR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_spec_rx_err (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SPEC_RX_ERR } # [doc = "STX_UNFL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stx_unfl (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STX_UNFL } # [doc = "SRX_OVFL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srx_ovfl (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRX_OVFL } # [doc = "SARBLOST"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sarblost (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SARBLOST } # [doc = "INTR_OVFL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_intr_ovfl (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_INTR_OVFL } } impl R { # [doc = "Bits 0:7 - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event0_iidx_stat (& self) -> INT_EVENT0_IIDX_STAT_R { INT_EVENT0_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_imask`]
module"]
pub type INT_EVENT0_IMASK = crate :: Reg < int_event0_imask :: INT_EVENT0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event0_imask { # [doc = "Register `INT_EVENT0_IMASK` reader"]
pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"]
pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_MRXDONE` reader - Master Receive Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MRXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_MRXDONE_A > ; # [doc = "Master Receive Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MRXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_MRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MRXDONE_A { match self . bits { false => INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_CLR , true => INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mrxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mrxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_MRXDONE` writer - Master Receive Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MRXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mrxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MTXDONE` reader - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MTXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_MTXDONE_A > ; # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MTXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MTXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MTXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_MTXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MTXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MTXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MTXDONE_A { match self . bits { false => INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_CLR , true => INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mtxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mtxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_MTXDONE` writer - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MTXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mtxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_IMASK_MRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_IMASK_MRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_MRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MRXFIFOFULL_A { match self . bits { false => INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_CLR , true => INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifofull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifofull_set (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_IMASK_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MRXFIFOFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mrxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MTXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_MTXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_MTXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MTXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MTXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_MTXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MTXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MTXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MTXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_CLR , true => INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mtxempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mtxempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MTXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mtxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MNACK` reader - Address/Data NACK Interrupt"]
pub type INT_EVENT0_IMASK_MNACK_R = crate :: BitReader < INT_EVENT0_IMASK_MNACK_A > ; # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MNACK_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MNACK_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MNACK_SET = 1 , } impl From < INT_EVENT0_IMASK_MNACK_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MNACK_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MNACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MNACK_A { match self . bits { false => INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_CLR , true => INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mnack_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mnack_set (& self) -> bool { * self == INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_SET } } # [doc = "Field `INT_EVENT0_IMASK_MNACK` writer - Address/Data NACK Interrupt"]
pub type INT_EVENT0_IMASK_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MNACK_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mnack_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MSTART` reader - START Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTART_R = crate :: BitReader < INT_EVENT0_IMASK_MSTART_A > ; # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MSTART_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MSTART_SET = 1 , } impl From < INT_EVENT0_IMASK_MSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MSTART_A { match self . bits { false => INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_CLR , true => INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mstart_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mstart_set (& self) -> bool { * self == INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_SET } } # [doc = "Field `INT_EVENT0_IMASK_MSTART` writer - START Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MSTART_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MSTOP` reader - STOP Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTOP_R = crate :: BitReader < INT_EVENT0_IMASK_MSTOP_A > ; # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MSTOP_SET = 1 , } impl From < INT_EVENT0_IMASK_MSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MSTOP_A { match self . bits { false => INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_CLR , true => INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mstop_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mstop_set (& self) -> bool { * self == INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_SET } } # [doc = "Field `INT_EVENT0_IMASK_MSTOP` writer - STOP Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MSTOP_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MARBLOST` reader - Arbitration Lost Interrupt"]
pub type INT_EVENT0_IMASK_MARBLOST_R = crate :: BitReader < INT_EVENT0_IMASK_MARBLOST_A > ; # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MARBLOST_SET = 1 , } impl From < INT_EVENT0_IMASK_MARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MARBLOST_A { match self . bits { false => INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_CLR , true => INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_marblost_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_marblost_set (& self) -> bool { * self == INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_SET } } # [doc = "Field `INT_EVENT0_IMASK_MARBLOST` writer - Arbitration Lost Interrupt"]
pub type INT_EVENT0_IMASK_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MARBLOST_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_marblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_IMASK_MDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_IMASK_MDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_CLR , true => INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MDMA_DONE1_2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_IMASK_MDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_IMASK_MDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_CLR , true => INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MDMA_DONE1_3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MPEC_RX_ERR` reader - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_MPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_IMASK_MPEC_RX_ERR_A > ; # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_IMASK_MPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_CLR , true => INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mpec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mpec_rx_err_set (& self) -> bool { * self == INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MPEC_RX_ERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mpec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTA` reader - Timeout A Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTA_R = crate :: BitReader < INT_EVENT0_IMASK_TIMEOUTA_A > ; # [doc = "Timeout A Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TIMEOUTA_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TIMEOUTA_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_IMASK_TIMEOUTA_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TIMEOUTA_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TIMEOUTA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TIMEOUTA_A { match self . bits { false => INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_CLR , true => INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_timeouta_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_timeouta_set (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_SET } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTA` writer - Timeout A Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TIMEOUTA_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_timeouta_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTB` reader - Timeout B Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTB_R = crate :: BitReader < INT_EVENT0_IMASK_TIMEOUTB_A > ; # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TIMEOUTB_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TIMEOUTB_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_IMASK_TIMEOUTB_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TIMEOUTB_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TIMEOUTB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TIMEOUTB_A { match self . bits { false => INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_CLR , true => INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_timeoutb_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_timeoutb_set (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_SET } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTB` writer - Timeout B Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TIMEOUTB_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_timeoutb_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRXDONE` reader - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_IMASK_SRXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_SRXDONE_A > ; # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_SRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRXDONE_A { match self . bits { false => INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_CLR , true => INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_IMASK_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STXDONE` reader - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_STXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_STXDONE_A > ; # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_STXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STXDONE_A { match self . bits { false => INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_CLR , true => INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_STXDONE` writer - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_CLR , true => INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
pub type INT_EVENT0_IMASK_SRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_IMASK_SRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an Slave RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_SRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRXFIFOFULL_A { match self . bits { false => INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_CLR , true => INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifofull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifofull_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
pub type INT_EVENT0_IMASK_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRXFIFOFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STXEMPTY` reader - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_STXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_STXEMPTY_A > ; # [doc = "Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_STXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_CLR , true => INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stxempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stxempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_STXEMPTY` writer - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SSTART` reader - Start Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTART_R = crate :: BitReader < INT_EVENT0_IMASK_SSTART_A > ; # [doc = "Start Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SSTART_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SSTART_SET = 1 , } impl From < INT_EVENT0_IMASK_SSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SSTART_A { match self . bits { false => INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_CLR , true => INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sstart_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sstart_set (& self) -> bool { * self == INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_SET } } # [doc = "Field `INT_EVENT0_IMASK_SSTART` writer - Start Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SSTART_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SSTOP` reader - Stop Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTOP_R = crate :: BitReader < INT_EVENT0_IMASK_SSTOP_A > ; # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SSTOP_SET = 1 , } impl From < INT_EVENT0_IMASK_SSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SSTOP_A { match self . bits { false => INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_CLR , true => INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sstop_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sstop_set (& self) -> bool { * self == INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_SET } } # [doc = "Field `INT_EVENT0_IMASK_SSTOP` writer - Stop Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SSTOP_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SGENCALL` reader - General Call Interrupt"]
pub type INT_EVENT0_IMASK_SGENCALL_R = crate :: BitReader < INT_EVENT0_IMASK_SGENCALL_A > ; # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SGENCALL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SGENCALL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SGENCALL_SET = 1 , } impl From < INT_EVENT0_IMASK_SGENCALL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SGENCALL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SGENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SGENCALL_A { match self . bits { false => INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_CLR , true => INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sgencall_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sgencall_set (& self) -> bool { * self == INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_SET } } # [doc = "Field `INT_EVENT0_IMASK_SGENCALL` writer - General Call Interrupt"]
pub type INT_EVENT0_IMASK_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SGENCALL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sgencall_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_2` reader - Slave DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_IMASK_SDMA_DONE1_2_A > ; # [doc = "Slave DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_IMASK_SDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_CLR , true => INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_2` writer - Slave DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SDMA_DONE1_2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_3` reader - Slave DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_IMASK_SDMA_DONE1_3_A > ; # [doc = "Slave DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_IMASK_SDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_CLR , true => INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_3` writer - Slave DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SDMA_DONE1_3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SPEC_RX_ERR` reader - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_SPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_IMASK_SPEC_RX_ERR_A > ; # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_IMASK_SPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_CLR , true => INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_spec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_spec_rx_err_set (& self) -> bool { * self == INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SPEC_RX_ERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_spec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STX_UNFL` reader - Slave TX FIFO underflow"]
pub type INT_EVENT0_IMASK_STX_UNFL_R = crate :: BitReader < INT_EVENT0_IMASK_STX_UNFL_A > ; # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STX_UNFL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STX_UNFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_IMASK_STX_UNFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STX_UNFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STX_UNFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STX_UNFL_A { match self . bits { false => INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_CLR , true => INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stx_unfl_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stx_unfl_set (& self) -> bool { * self == INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_SET } } # [doc = "Field `INT_EVENT0_IMASK_STX_UNFL` writer - Slave TX FIFO underflow"]
pub type INT_EVENT0_IMASK_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STX_UNFL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stx_unfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRX_OVFL` reader - Slave RX FIFO overflow"]
pub type INT_EVENT0_IMASK_SRX_OVFL_R = crate :: BitReader < INT_EVENT0_IMASK_SRX_OVFL_A > ; # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRX_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRX_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_IMASK_SRX_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRX_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRX_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRX_OVFL_A { match self . bits { false => INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_CLR , true => INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srx_ovfl_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srx_ovfl_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRX_OVFL` writer - Slave RX FIFO overflow"]
pub type INT_EVENT0_IMASK_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRX_OVFL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srx_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SARBLOST` reader - Slave Arbitration Lost"]
pub type INT_EVENT0_IMASK_SARBLOST_R = crate :: BitReader < INT_EVENT0_IMASK_SARBLOST_A > ; # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SARBLOST_SET = 1 , } impl From < INT_EVENT0_IMASK_SARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SARBLOST_A { match self . bits { false => INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_CLR , true => INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sarblost_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sarblost_set (& self) -> bool { * self == INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_SET } } # [doc = "Field `INT_EVENT0_IMASK_SARBLOST` writer - Slave Arbitration Lost"]
pub type INT_EVENT0_IMASK_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SARBLOST_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sarblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_SET) } } # [doc = "Field `INT_EVENT0_IMASK_INTR_OVFL` reader - Interrupt Overflow Interrupt Mask"]
pub type INT_EVENT0_IMASK_INTR_OVFL_R = crate :: BitReader < INT_EVENT0_IMASK_INTR_OVFL_A > ; # [doc = "Interrupt Overflow Interrupt Mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_INTR_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_INTR_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_IMASK_INTR_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_INTR_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_INTR_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_INTR_OVFL_A { match self . bits { false => INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_CLR , true => INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_intr_ovfl_clr (& self) -> bool { * self == INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_intr_ovfl_set (& self) -> bool { * self == INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_SET } } # [doc = "Field `INT_EVENT0_IMASK_INTR_OVFL` writer - Interrupt Overflow Interrupt Mask"]
pub type INT_EVENT0_IMASK_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_INTR_OVFL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_intr_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_SET) } } impl R { # [doc = "Bit 0 - Master Receive Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mrxdone (& self) -> INT_EVENT0_IMASK_MRXDONE_R { INT_EVENT0_IMASK_MRXDONE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mtxdone (& self) -> INT_EVENT0_IMASK_MTXDONE_R { INT_EVENT0_IMASK_MTXDONE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event0_imask_mrxfifotrg (& self) -> INT_EVENT0_IMASK_MRXFIFOTRG_R { INT_EVENT0_IMASK_MRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event0_imask_mtxfifotrg (& self) -> INT_EVENT0_IMASK_MTXFIFOTRG_R { INT_EVENT0_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_imask_mrxfifofull (& self) -> INT_EVENT0_IMASK_MRXFIFOFULL_R { INT_EVENT0_IMASK_MRXFIFOFULL_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_imask_mtxempty (& self) -> INT_EVENT0_IMASK_MTXEMPTY_R { INT_EVENT0_IMASK_MTXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mnack (& self) -> INT_EVENT0_IMASK_MNACK_R { INT_EVENT0_IMASK_MNACK_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mstart (& self) -> INT_EVENT0_IMASK_MSTART_R { INT_EVENT0_IMASK_MSTART_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mstop (& self) -> INT_EVENT0_IMASK_MSTOP_R { INT_EVENT0_IMASK_MSTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
pub fn int_event0_imask_marblost (& self) -> INT_EVENT0_IMASK_MARBLOST_R { INT_EVENT0_IMASK_MARBLOST_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_2 (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_2_R { INT_EVENT0_IMASK_MDMA_DONE1_2_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_3 (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_3_R { INT_EVENT0_IMASK_MDMA_DONE1_3_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mpec_rx_err (& self) -> INT_EVENT0_IMASK_MPEC_RX_ERR_R { INT_EVENT0_IMASK_MPEC_RX_ERR_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
pub fn int_event0_imask_timeouta (& self) -> INT_EVENT0_IMASK_TIMEOUTA_R { INT_EVENT0_IMASK_TIMEOUTA_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
pub fn int_event0_imask_timeoutb (& self) -> INT_EVENT0_IMASK_TIMEOUTB_R { INT_EVENT0_IMASK_TIMEOUTB_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
pub fn int_event0_imask_srxdone (& self) -> INT_EVENT0_IMASK_SRXDONE_R { INT_EVENT0_IMASK_SRXDONE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_imask_stxdone (& self) -> INT_EVENT0_IMASK_STXDONE_R { INT_EVENT0_IMASK_STXDONE_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event0_imask_srxfifotrg (& self) -> INT_EVENT0_IMASK_SRXFIFOTRG_R { INT_EVENT0_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event0_imask_stxfifotrg (& self) -> INT_EVENT0_IMASK_STXFIFOTRG_R { INT_EVENT0_IMASK_STXFIFOTRG_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
# [inline (always)]
pub fn int_event0_imask_srxfifofull (& self) -> INT_EVENT0_IMASK_SRXFIFOFULL_R { INT_EVENT0_IMASK_SRXFIFOFULL_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_imask_stxempty (& self) -> INT_EVENT0_IMASK_STXEMPTY_R { INT_EVENT0_IMASK_STXEMPTY_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
pub fn int_event0_imask_sstart (& self) -> INT_EVENT0_IMASK_SSTART_R { INT_EVENT0_IMASK_SSTART_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
pub fn int_event0_imask_sstop (& self) -> INT_EVENT0_IMASK_SSTOP_R { INT_EVENT0_IMASK_SSTOP_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
pub fn int_event0_imask_sgencall (& self) -> INT_EVENT0_IMASK_SGENCALL_R { INT_EVENT0_IMASK_SGENCALL_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Slave DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_2 (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_2_R { INT_EVENT0_IMASK_SDMA_DONE1_2_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - Slave DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_3 (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_3_R { INT_EVENT0_IMASK_SDMA_DONE1_3_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_imask_spec_rx_err (& self) -> INT_EVENT0_IMASK_SPEC_RX_ERR_R { INT_EVENT0_IMASK_SPEC_RX_ERR_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
pub fn int_event0_imask_stx_unfl (& self) -> INT_EVENT0_IMASK_STX_UNFL_R { INT_EVENT0_IMASK_STX_UNFL_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
pub fn int_event0_imask_srx_ovfl (& self) -> INT_EVENT0_IMASK_SRX_OVFL_R { INT_EVENT0_IMASK_SRX_OVFL_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
pub fn int_event0_imask_sarblost (& self) -> INT_EVENT0_IMASK_SARBLOST_R { INT_EVENT0_IMASK_SARBLOST_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Interrupt Overflow Interrupt Mask"]
# [inline (always)]
pub fn int_event0_imask_intr_ovfl (& self) -> INT_EVENT0_IMASK_INTR_OVFL_R { INT_EVENT0_IMASK_INTR_OVFL_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mrxdone (& mut self) -> INT_EVENT0_IMASK_MRXDONE_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mtxdone (& mut self) -> INT_EVENT0_IMASK_MTXDONE_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mrxfifotrg (& mut self) -> INT_EVENT0_IMASK_MRXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mtxfifotrg (& mut self) -> INT_EVENT0_IMASK_MTXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mrxfifofull (& mut self) -> INT_EVENT0_IMASK_MRXFIFOFULL_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mtxempty (& mut self) -> INT_EVENT0_IMASK_MTXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mnack (& mut self) -> INT_EVENT0_IMASK_MNACK_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mstart (& mut self) -> INT_EVENT0_IMASK_MSTART_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mstop (& mut self) -> INT_EVENT0_IMASK_MSTOP_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_marblost (& mut self) -> INT_EVENT0_IMASK_MARBLOST_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mdma_done1_2 (& mut self) -> INT_EVENT0_IMASK_MDMA_DONE1_2_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mdma_done1_3 (& mut self) -> INT_EVENT0_IMASK_MDMA_DONE1_3_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mpec_rx_err (& mut self) -> INT_EVENT0_IMASK_MPEC_RX_ERR_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_timeouta (& mut self) -> INT_EVENT0_IMASK_TIMEOUTA_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_timeoutb (& mut self) -> INT_EVENT0_IMASK_TIMEOUTB_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srxdone (& mut self) -> INT_EVENT0_IMASK_SRXDONE_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stxdone (& mut self) -> INT_EVENT0_IMASK_STXDONE_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srxfifotrg (& mut self) -> INT_EVENT0_IMASK_SRXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stxfifotrg (& mut self) -> INT_EVENT0_IMASK_STXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srxfifofull (& mut self) -> INT_EVENT0_IMASK_SRXFIFOFULL_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stxempty (& mut self) -> INT_EVENT0_IMASK_STXEMPTY_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sstart (& mut self) -> INT_EVENT0_IMASK_SSTART_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sstop (& mut self) -> INT_EVENT0_IMASK_SSTOP_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sgencall (& mut self) -> INT_EVENT0_IMASK_SGENCALL_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_SGENCALL_W :: new (self) } # [doc = "Bit 25 - Slave DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sdma_done1_2 (& mut self) -> INT_EVENT0_IMASK_SDMA_DONE1_2_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - Slave DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sdma_done1_3 (& mut self) -> INT_EVENT0_IMASK_SDMA_DONE1_3_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_spec_rx_err (& mut self) -> INT_EVENT0_IMASK_SPEC_RX_ERR_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stx_unfl (& mut self) -> INT_EVENT0_IMASK_STX_UNFL_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srx_ovfl (& mut self) -> INT_EVENT0_IMASK_SRX_OVFL_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sarblost (& mut self) -> INT_EVENT0_IMASK_SARBLOST_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt Overflow Interrupt Mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_intr_ovfl (& mut self) -> INT_EVENT0_IMASK_INTR_OVFL_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_ris`]
module"]
pub type INT_EVENT0_RIS = crate :: Reg < int_event0_ris :: INT_EVENT0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event0_ris { # [doc = "Register `INT_EVENT0_RIS` reader"]
pub type R = crate :: R < INT_EVENT0_RIS_SPEC > ; # [doc = "Field `INT_EVENT0_RIS_MRXDONE` reader - Master Receive Transaction completed Interrupt"]
pub type INT_EVENT0_RIS_MRXDONE_R = crate :: BitReader < INT_EVENT0_RIS_MRXDONE_A > ; # [doc = "Master Receive Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MRXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_MRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MRXDONE_A { match self . bits { false => INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_CLR , true => INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mrxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mrxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_MTXDONE` reader - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_RIS_MTXDONE_R = crate :: BitReader < INT_EVENT0_RIS_MTXDONE_A > ; # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MTXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MTXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MTXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_MTXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MTXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MTXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MTXDONE_A { match self . bits { false => INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_CLR , true => INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mtxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mtxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_RIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_CLR , true => INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_RIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_CLR , true => INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_MRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_RIS_MRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_RIS_MRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_RIS_MRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MRXFIFOFULL_A { match self . bits { false => INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_CLR , true => INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifofull_clr (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifofull_set (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_RIS_MTXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_RIS_MTXEMPTY_R = crate :: BitReader < INT_EVENT0_RIS_MTXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MTXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MTXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_RIS_MTXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MTXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MTXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MTXEMPTY_A { match self . bits { false => INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_CLR , true => INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mtxempty_clr (& self) -> bool { * self == INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mtxempty_set (& self) -> bool { * self == INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_SET } } # [doc = "Field `INT_EVENT0_RIS_MNACK` reader - Address/Data NACK Interrupt"]
pub type INT_EVENT0_RIS_MNACK_R = crate :: BitReader < INT_EVENT0_RIS_MNACK_A > ; # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MNACK_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MNACK_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MNACK_SET = 1 , } impl From < INT_EVENT0_RIS_MNACK_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MNACK_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MNACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MNACK_A { match self . bits { false => INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_CLR , true => INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mnack_clr (& self) -> bool { * self == INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mnack_set (& self) -> bool { * self == INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_SET } } # [doc = "Field `INT_EVENT0_RIS_MSTART` reader - START Detection Interrupt"]
pub type INT_EVENT0_RIS_MSTART_R = crate :: BitReader < INT_EVENT0_RIS_MSTART_A > ; # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MSTART_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MSTART_SET = 1 , } impl From < INT_EVENT0_RIS_MSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MSTART_A { match self . bits { false => INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_CLR , true => INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mstart_clr (& self) -> bool { * self == INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mstart_set (& self) -> bool { * self == INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_SET } } # [doc = "Field `INT_EVENT0_RIS_MSTOP` reader - STOP Detection Interrupt"]
pub type INT_EVENT0_RIS_MSTOP_R = crate :: BitReader < INT_EVENT0_RIS_MSTOP_A > ; # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MSTOP_SET = 1 , } impl From < INT_EVENT0_RIS_MSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MSTOP_A { match self . bits { false => INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_CLR , true => INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mstop_clr (& self) -> bool { * self == INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mstop_set (& self) -> bool { * self == INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_SET } } # [doc = "Field `INT_EVENT0_RIS_MARBLOST` reader - Arbitration Lost Interrupt"]
pub type INT_EVENT0_RIS_MARBLOST_R = crate :: BitReader < INT_EVENT0_RIS_MARBLOST_A > ; # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MARBLOST_SET = 1 , } impl From < INT_EVENT0_RIS_MARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MARBLOST_A { match self . bits { false => INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_CLR , true => INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_marblost_clr (& self) -> bool { * self == INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_marblost_set (& self) -> bool { * self == INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_SET } } # [doc = "Field `INT_EVENT0_RIS_MDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_RIS_MDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_RIS_MDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_RIS_MDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_CLR , true => INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_RIS_MDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_RIS_MDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_RIS_MDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_RIS_MDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_CLR , true => INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_RIS_MPEC_RX_ERR` reader - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_RIS_MPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_RIS_MPEC_RX_ERR_A > ; # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_RIS_MPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_CLR , true => INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mpec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mpec_rx_err_set (& self) -> bool { * self == INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_RIS_TIMEOUTA` reader - Timeout A Interrupt"]
pub type INT_EVENT0_RIS_TIMEOUTA_R = crate :: BitReader < INT_EVENT0_RIS_TIMEOUTA_A > ; # [doc = "Timeout A Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TIMEOUTA_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TIMEOUTA_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_RIS_TIMEOUTA_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TIMEOUTA_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TIMEOUTA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TIMEOUTA_A { match self . bits { false => INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_CLR , true => INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_timeouta_clr (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_timeouta_set (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_SET } } # [doc = "Field `INT_EVENT0_RIS_TIMEOUTB` reader - Timeout B Interrupt"]
pub type INT_EVENT0_RIS_TIMEOUTB_R = crate :: BitReader < INT_EVENT0_RIS_TIMEOUTB_A > ; # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TIMEOUTB_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TIMEOUTB_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_RIS_TIMEOUTB_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TIMEOUTB_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TIMEOUTB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TIMEOUTB_A { match self . bits { false => INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_CLR , true => INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_timeoutb_clr (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_timeoutb_set (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_SET } } # [doc = "Field `INT_EVENT0_RIS_SRXDONE` reader - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_RIS_SRXDONE_R = crate :: BitReader < INT_EVENT0_RIS_SRXDONE_A > ; # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_SRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRXDONE_A { match self . bits { false => INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_CLR , true => INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_STXDONE` reader - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_RIS_STXDONE_R = crate :: BitReader < INT_EVENT0_RIS_STXDONE_A > ; # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_STXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STXDONE_A { match self . bits { false => INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_CLR , true => INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_RIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_CLR , true => INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_RIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_CLR , true => INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_SRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_RIS_SRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_RIS_SRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_RIS_SRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRXFIFOFULL_A { match self . bits { false => INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_CLR , true => INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifofull_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifofull_set (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_RIS_STXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_RIS_STXEMPTY_R = crate :: BitReader < INT_EVENT0_RIS_STXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_RIS_STXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STXEMPTY_A { match self . bits { false => INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_CLR , true => INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stxempty_clr (& self) -> bool { * self == INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stxempty_set (& self) -> bool { * self == INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_SET } } # [doc = "Field `INT_EVENT0_RIS_SSTART` reader - Start Condition Interrupt"]
pub type INT_EVENT0_RIS_SSTART_R = crate :: BitReader < INT_EVENT0_RIS_SSTART_A > ; # [doc = "Start Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SSTART_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SSTART_SET = 1 , } impl From < INT_EVENT0_RIS_SSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SSTART_A { match self . bits { false => INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_CLR , true => INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sstart_clr (& self) -> bool { * self == INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sstart_set (& self) -> bool { * self == INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_SET } } # [doc = "Field `INT_EVENT0_RIS_SSTOP` reader - Stop Condition Interrupt"]
pub type INT_EVENT0_RIS_SSTOP_R = crate :: BitReader < INT_EVENT0_RIS_SSTOP_A > ; # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SSTOP_SET = 1 , } impl From < INT_EVENT0_RIS_SSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SSTOP_A { match self . bits { false => INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_CLR , true => INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sstop_clr (& self) -> bool { * self == INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sstop_set (& self) -> bool { * self == INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_SET } } # [doc = "Field `INT_EVENT0_RIS_SGENCALL` reader - General Call Interrupt"]
pub type INT_EVENT0_RIS_SGENCALL_R = crate :: BitReader < INT_EVENT0_RIS_SGENCALL_A > ; # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SGENCALL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SGENCALL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SGENCALL_SET = 1 , } impl From < INT_EVENT0_RIS_SGENCALL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SGENCALL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SGENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SGENCALL_A { match self . bits { false => INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_CLR , true => INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sgencall_clr (& self) -> bool { * self == INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sgencall_set (& self) -> bool { * self == INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_SET } } # [doc = "Field `INT_EVENT0_RIS_SDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_RIS_SDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_RIS_SDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_RIS_SDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_CLR , true => INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_RIS_SDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_RIS_SDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_RIS_SDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_RIS_SDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_CLR , true => INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_RIS_SPEC_RX_ERR` reader - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_RIS_SPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_RIS_SPEC_RX_ERR_A > ; # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_RIS_SPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_CLR , true => INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_spec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_spec_rx_err_set (& self) -> bool { * self == INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_RIS_STX_UNFL` reader - Slave TX FIFO underflow"]
pub type INT_EVENT0_RIS_STX_UNFL_R = crate :: BitReader < INT_EVENT0_RIS_STX_UNFL_A > ; # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STX_UNFL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STX_UNFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_RIS_STX_UNFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STX_UNFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STX_UNFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STX_UNFL_A { match self . bits { false => INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_CLR , true => INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stx_unfl_clr (& self) -> bool { * self == INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stx_unfl_set (& self) -> bool { * self == INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_SET } } # [doc = "Field `INT_EVENT0_RIS_SRX_OVFL` reader - Slave RX FIFO overflow"]
pub type INT_EVENT0_RIS_SRX_OVFL_R = crate :: BitReader < INT_EVENT0_RIS_SRX_OVFL_A > ; # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRX_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRX_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_RIS_SRX_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRX_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRX_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRX_OVFL_A { match self . bits { false => INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_CLR , true => INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srx_ovfl_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srx_ovfl_set (& self) -> bool { * self == INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_SET } } # [doc = "Field `INT_EVENT0_RIS_SARBLOST` reader - Slave Arbitration Lost"]
pub type INT_EVENT0_RIS_SARBLOST_R = crate :: BitReader < INT_EVENT0_RIS_SARBLOST_A > ; # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SARBLOST_SET = 1 , } impl From < INT_EVENT0_RIS_SARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SARBLOST_A { match self . bits { false => INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_CLR , true => INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sarblost_clr (& self) -> bool { * self == INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sarblost_set (& self) -> bool { * self == INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_SET } } # [doc = "Field `INT_EVENT0_RIS_INTR_OVFL` reader - Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced"]
pub type INT_EVENT0_RIS_INTR_OVFL_R = crate :: BitReader < INT_EVENT0_RIS_INTR_OVFL_A > ; # [doc = "Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_INTR_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_INTR_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_RIS_INTR_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_INTR_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_INTR_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_INTR_OVFL_A { match self . bits { false => INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_CLR , true => INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_intr_ovfl_clr (& self) -> bool { * self == INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_intr_ovfl_set (& self) -> bool { * self == INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_SET } } impl R { # [doc = "Bit 0 - Master Receive Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mrxdone (& self) -> INT_EVENT0_RIS_MRXDONE_R { INT_EVENT0_RIS_MRXDONE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mtxdone (& self) -> INT_EVENT0_RIS_MTXDONE_R { INT_EVENT0_RIS_MTXDONE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event0_ris_mrxfifotrg (& self) -> INT_EVENT0_RIS_MRXFIFOTRG_R { INT_EVENT0_RIS_MRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event0_ris_mtxfifotrg (& self) -> INT_EVENT0_RIS_MTXFIFOTRG_R { INT_EVENT0_RIS_MTXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_ris_mrxfifofull (& self) -> INT_EVENT0_RIS_MRXFIFOFULL_R { INT_EVENT0_RIS_MRXFIFOFULL_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_ris_mtxempty (& self) -> INT_EVENT0_RIS_MTXEMPTY_R { INT_EVENT0_RIS_MTXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mnack (& self) -> INT_EVENT0_RIS_MNACK_R { INT_EVENT0_RIS_MNACK_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mstart (& self) -> INT_EVENT0_RIS_MSTART_R { INT_EVENT0_RIS_MSTART_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mstop (& self) -> INT_EVENT0_RIS_MSTOP_R { INT_EVENT0_RIS_MSTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
pub fn int_event0_ris_marblost (& self) -> INT_EVENT0_RIS_MARBLOST_R { INT_EVENT0_RIS_MARBLOST_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_ris_mdma_done1_2 (& self) -> INT_EVENT0_RIS_MDMA_DONE1_2_R { INT_EVENT0_RIS_MDMA_DONE1_2_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_ris_mdma_done1_3 (& self) -> INT_EVENT0_RIS_MDMA_DONE1_3_R { INT_EVENT0_RIS_MDMA_DONE1_3_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mpec_rx_err (& self) -> INT_EVENT0_RIS_MPEC_RX_ERR_R { INT_EVENT0_RIS_MPEC_RX_ERR_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
pub fn int_event0_ris_timeouta (& self) -> INT_EVENT0_RIS_TIMEOUTA_R { INT_EVENT0_RIS_TIMEOUTA_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
pub fn int_event0_ris_timeoutb (& self) -> INT_EVENT0_RIS_TIMEOUTB_R { INT_EVENT0_RIS_TIMEOUTB_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
pub fn int_event0_ris_srxdone (& self) -> INT_EVENT0_RIS_SRXDONE_R { INT_EVENT0_RIS_SRXDONE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_ris_stxdone (& self) -> INT_EVENT0_RIS_STXDONE_R { INT_EVENT0_RIS_STXDONE_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event0_ris_srxfifotrg (& self) -> INT_EVENT0_RIS_SRXFIFOTRG_R { INT_EVENT0_RIS_SRXFIFOTRG_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event0_ris_stxfifotrg (& self) -> INT_EVENT0_RIS_STXFIFOTRG_R { INT_EVENT0_RIS_STXFIFOTRG_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_ris_srxfifofull (& self) -> INT_EVENT0_RIS_SRXFIFOFULL_R { INT_EVENT0_RIS_SRXFIFOFULL_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_ris_stxempty (& self) -> INT_EVENT0_RIS_STXEMPTY_R { INT_EVENT0_RIS_STXEMPTY_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
pub fn int_event0_ris_sstart (& self) -> INT_EVENT0_RIS_SSTART_R { INT_EVENT0_RIS_SSTART_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
pub fn int_event0_ris_sstop (& self) -> INT_EVENT0_RIS_SSTOP_R { INT_EVENT0_RIS_SSTOP_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
pub fn int_event0_ris_sgencall (& self) -> INT_EVENT0_RIS_SGENCALL_R { INT_EVENT0_RIS_SGENCALL_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_ris_sdma_done1_2 (& self) -> INT_EVENT0_RIS_SDMA_DONE1_2_R { INT_EVENT0_RIS_SDMA_DONE1_2_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_ris_sdma_done1_3 (& self) -> INT_EVENT0_RIS_SDMA_DONE1_3_R { INT_EVENT0_RIS_SDMA_DONE1_3_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_ris_spec_rx_err (& self) -> INT_EVENT0_RIS_SPEC_RX_ERR_R { INT_EVENT0_RIS_SPEC_RX_ERR_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
pub fn int_event0_ris_stx_unfl (& self) -> INT_EVENT0_RIS_STX_UNFL_R { INT_EVENT0_RIS_STX_UNFL_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
pub fn int_event0_ris_srx_ovfl (& self) -> INT_EVENT0_RIS_SRX_OVFL_R { INT_EVENT0_RIS_SRX_OVFL_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
pub fn int_event0_ris_sarblost (& self) -> INT_EVENT0_RIS_SARBLOST_R { INT_EVENT0_RIS_SARBLOST_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced"]
# [inline (always)]
pub fn int_event0_ris_intr_ovfl (& self) -> INT_EVENT0_RIS_INTR_OVFL_R { INT_EVENT0_RIS_INTR_OVFL_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_RIS to value 0"]
impl crate :: Resettable for INT_EVENT0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_mis`]
module"]
pub type INT_EVENT0_MIS = crate :: Reg < int_event0_mis :: INT_EVENT0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event0_mis { # [doc = "Register `INT_EVENT0_MIS` reader"]
pub type R = crate :: R < INT_EVENT0_MIS_SPEC > ; # [doc = "Field `INT_EVENT0_MIS_MRXDONE` reader - Master Receive Data Interrupt"]
pub type INT_EVENT0_MIS_MRXDONE_R = crate :: BitReader < INT_EVENT0_MIS_MRXDONE_A > ; # [doc = "Master Receive Data Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MRXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_MRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MRXDONE_A { match self . bits { false => INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_CLR , true => INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mrxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mrxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_MTXDONE` reader - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_MIS_MTXDONE_R = crate :: BitReader < INT_EVENT0_MIS_MTXDONE_A > ; # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MTXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MTXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MTXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_MTXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MTXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MTXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MTXDONE_A { match self . bits { false => INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_CLR , true => INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mtxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mtxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_MIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_CLR , true => INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_MIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_CLR , true => INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_MRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if the RX FIFO is full."]
pub type INT_EVENT0_MIS_MRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_MIS_MRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if the RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_MIS_MRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MRXFIFOFULL_A { match self . bits { false => INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_CLR , true => INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifofull_clr (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifofull_set (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_MIS_MTXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_MIS_MTXEMPTY_R = crate :: BitReader < INT_EVENT0_MIS_MTXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MTXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MTXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_MIS_MTXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MTXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MTXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MTXEMPTY_A { match self . bits { false => INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_CLR , true => INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mtxempty_clr (& self) -> bool { * self == INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mtxempty_set (& self) -> bool { * self == INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_SET } } # [doc = "Field `INT_EVENT0_MIS_MNACK` reader - Address/Data NACK Interrupt"]
pub type INT_EVENT0_MIS_MNACK_R = crate :: BitReader < INT_EVENT0_MIS_MNACK_A > ; # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MNACK_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MNACK_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MNACK_SET = 1 , } impl From < INT_EVENT0_MIS_MNACK_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MNACK_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MNACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MNACK_A { match self . bits { false => INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_CLR , true => INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mnack_clr (& self) -> bool { * self == INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mnack_set (& self) -> bool { * self == INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_SET } } # [doc = "Field `INT_EVENT0_MIS_MSTART` reader - START Detection Interrupt"]
pub type INT_EVENT0_MIS_MSTART_R = crate :: BitReader < INT_EVENT0_MIS_MSTART_A > ; # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MSTART_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MSTART_SET = 1 , } impl From < INT_EVENT0_MIS_MSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MSTART_A { match self . bits { false => INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_CLR , true => INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mstart_clr (& self) -> bool { * self == INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mstart_set (& self) -> bool { * self == INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_SET } } # [doc = "Field `INT_EVENT0_MIS_MSTOP` reader - STOP Detection Interrupt"]
pub type INT_EVENT0_MIS_MSTOP_R = crate :: BitReader < INT_EVENT0_MIS_MSTOP_A > ; # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MSTOP_SET = 1 , } impl From < INT_EVENT0_MIS_MSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MSTOP_A { match self . bits { false => INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_CLR , true => INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mstop_clr (& self) -> bool { * self == INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mstop_set (& self) -> bool { * self == INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_SET } } # [doc = "Field `INT_EVENT0_MIS_MARBLOST` reader - Arbitration Lost Interrupt"]
pub type INT_EVENT0_MIS_MARBLOST_R = crate :: BitReader < INT_EVENT0_MIS_MARBLOST_A > ; # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MARBLOST_SET = 1 , } impl From < INT_EVENT0_MIS_MARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MARBLOST_A { match self . bits { false => INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_CLR , true => INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_marblost_clr (& self) -> bool { * self == INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_marblost_set (& self) -> bool { * self == INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_SET } } # [doc = "Field `INT_EVENT0_MIS_MDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_MIS_MDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_MIS_MDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_MIS_MDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_CLR , true => INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_MIS_MDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_MIS_MDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_MIS_MDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_MIS_MDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_CLR , true => INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_MIS_MPEC_RX_ERR` reader - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_MIS_MPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_MIS_MPEC_RX_ERR_A > ; # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_MIS_MPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_CLR , true => INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mpec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mpec_rx_err_set (& self) -> bool { * self == INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_MIS_TIMEOUTA` reader - Timeout A Interrupt"]
pub type INT_EVENT0_MIS_TIMEOUTA_R = crate :: BitReader < INT_EVENT0_MIS_TIMEOUTA_A > ; # [doc = "Timeout A Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TIMEOUTA_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TIMEOUTA_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_MIS_TIMEOUTA_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TIMEOUTA_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TIMEOUTA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TIMEOUTA_A { match self . bits { false => INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_CLR , true => INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_timeouta_clr (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_timeouta_set (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_SET } } # [doc = "Field `INT_EVENT0_MIS_TIMEOUTB` reader - Timeout B Interrupt"]
pub type INT_EVENT0_MIS_TIMEOUTB_R = crate :: BitReader < INT_EVENT0_MIS_TIMEOUTB_A > ; # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TIMEOUTB_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TIMEOUTB_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_MIS_TIMEOUTB_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TIMEOUTB_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TIMEOUTB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TIMEOUTB_A { match self . bits { false => INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_CLR , true => INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_timeoutb_clr (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_timeoutb_set (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_SET } } # [doc = "Field `INT_EVENT0_MIS_SRXDONE` reader - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_MIS_SRXDONE_R = crate :: BitReader < INT_EVENT0_MIS_SRXDONE_A > ; # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_SRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRXDONE_A { match self . bits { false => INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_CLR , true => INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_STXDONE` reader - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_MIS_STXDONE_R = crate :: BitReader < INT_EVENT0_MIS_STXDONE_A > ; # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_STXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STXDONE_A { match self . bits { false => INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_CLR , true => INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_MIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_CLR , true => INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_MIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_CLR , true => INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_SRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_MIS_SRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_MIS_SRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_MIS_SRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRXFIFOFULL_A { match self . bits { false => INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_CLR , true => INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifofull_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifofull_set (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_MIS_STXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_MIS_STXEMPTY_R = crate :: BitReader < INT_EVENT0_MIS_STXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_MIS_STXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STXEMPTY_A { match self . bits { false => INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_CLR , true => INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stxempty_clr (& self) -> bool { * self == INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stxempty_set (& self) -> bool { * self == INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_SET } } # [doc = "Field `INT_EVENT0_MIS_SSTART` reader - Slave START Detection Interrupt"]
pub type INT_EVENT0_MIS_SSTART_R = crate :: BitReader < INT_EVENT0_MIS_SSTART_A > ; # [doc = "Slave START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SSTART_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SSTART_SET = 1 , } impl From < INT_EVENT0_MIS_SSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SSTART_A { match self . bits { false => INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_CLR , true => INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sstart_clr (& self) -> bool { * self == INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sstart_set (& self) -> bool { * self == INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_SET } } # [doc = "Field `INT_EVENT0_MIS_SSTOP` reader - Slave STOP Detection Interrupt"]
pub type INT_EVENT0_MIS_SSTOP_R = crate :: BitReader < INT_EVENT0_MIS_SSTOP_A > ; # [doc = "Slave STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SSTOP_SET = 1 , } impl From < INT_EVENT0_MIS_SSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SSTOP_A { match self . bits { false => INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_CLR , true => INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sstop_clr (& self) -> bool { * self == INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sstop_set (& self) -> bool { * self == INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_SET } } # [doc = "Field `INT_EVENT0_MIS_SGENCALL` reader - General Call Interrupt"]
pub type INT_EVENT0_MIS_SGENCALL_R = crate :: BitReader < INT_EVENT0_MIS_SGENCALL_A > ; # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SGENCALL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SGENCALL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SGENCALL_SET = 1 , } impl From < INT_EVENT0_MIS_SGENCALL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SGENCALL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SGENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SGENCALL_A { match self . bits { false => INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_CLR , true => INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sgencall_clr (& self) -> bool { * self == INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sgencall_set (& self) -> bool { * self == INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_SET } } # [doc = "Field `INT_EVENT0_MIS_SDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_MIS_SDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_MIS_SDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_MIS_SDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_CLR , true => INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_MIS_SDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_MIS_SDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_MIS_SDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_MIS_SDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_CLR , true => INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_MIS_SPEC_RX_ERR` reader - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_MIS_SPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_MIS_SPEC_RX_ERR_A > ; # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_MIS_SPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_CLR , true => INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_spec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_spec_rx_err_set (& self) -> bool { * self == INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_MIS_STX_UNFL` reader - Slave TX FIFO underflow"]
pub type INT_EVENT0_MIS_STX_UNFL_R = crate :: BitReader < INT_EVENT0_MIS_STX_UNFL_A > ; # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STX_UNFL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STX_UNFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_MIS_STX_UNFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STX_UNFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STX_UNFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STX_UNFL_A { match self . bits { false => INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_CLR , true => INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stx_unfl_clr (& self) -> bool { * self == INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stx_unfl_set (& self) -> bool { * self == INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_SET } } # [doc = "Field `INT_EVENT0_MIS_SRX_OVFL` reader - Slave RX FIFO overflow"]
pub type INT_EVENT0_MIS_SRX_OVFL_R = crate :: BitReader < INT_EVENT0_MIS_SRX_OVFL_A > ; # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRX_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRX_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_MIS_SRX_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRX_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRX_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRX_OVFL_A { match self . bits { false => INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_CLR , true => INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srx_ovfl_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srx_ovfl_set (& self) -> bool { * self == INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_SET } } # [doc = "Field `INT_EVENT0_MIS_SARBLOST` reader - Slave Arbitration Lost"]
pub type INT_EVENT0_MIS_SARBLOST_R = crate :: BitReader < INT_EVENT0_MIS_SARBLOST_A > ; # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SARBLOST_SET = 1 , } impl From < INT_EVENT0_MIS_SARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SARBLOST_A { match self . bits { false => INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_CLR , true => INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sarblost_clr (& self) -> bool { * self == INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sarblost_set (& self) -> bool { * self == INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_SET } } # [doc = "Field `INT_EVENT0_MIS_INTR_OVFL` reader - Interrupt overflow"]
pub type INT_EVENT0_MIS_INTR_OVFL_R = crate :: BitReader < INT_EVENT0_MIS_INTR_OVFL_A > ; # [doc = "Interrupt overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_INTR_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_INTR_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_MIS_INTR_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_INTR_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_INTR_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_INTR_OVFL_A { match self . bits { false => INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_CLR , true => INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_intr_ovfl_clr (& self) -> bool { * self == INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_intr_ovfl_set (& self) -> bool { * self == INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_SET } } impl R { # [doc = "Bit 0 - Master Receive Data Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mrxdone (& self) -> INT_EVENT0_MIS_MRXDONE_R { INT_EVENT0_MIS_MRXDONE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mtxdone (& self) -> INT_EVENT0_MIS_MTXDONE_R { INT_EVENT0_MIS_MTXDONE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event0_mis_mrxfifotrg (& self) -> INT_EVENT0_MIS_MRXFIFOTRG_R { INT_EVENT0_MIS_MRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event0_mis_mtxfifotrg (& self) -> INT_EVENT0_MIS_MTXFIFOTRG_R { INT_EVENT0_MIS_MTXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if the RX FIFO is full."]
# [inline (always)]
pub fn int_event0_mis_mrxfifofull (& self) -> INT_EVENT0_MIS_MRXFIFOFULL_R { INT_EVENT0_MIS_MRXFIFOFULL_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_mis_mtxempty (& self) -> INT_EVENT0_MIS_MTXEMPTY_R { INT_EVENT0_MIS_MTXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mnack (& self) -> INT_EVENT0_MIS_MNACK_R { INT_EVENT0_MIS_MNACK_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mstart (& self) -> INT_EVENT0_MIS_MSTART_R { INT_EVENT0_MIS_MSTART_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mstop (& self) -> INT_EVENT0_MIS_MSTOP_R { INT_EVENT0_MIS_MSTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
pub fn int_event0_mis_marblost (& self) -> INT_EVENT0_MIS_MARBLOST_R { INT_EVENT0_MIS_MARBLOST_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_mis_mdma_done1_2 (& self) -> INT_EVENT0_MIS_MDMA_DONE1_2_R { INT_EVENT0_MIS_MDMA_DONE1_2_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_mis_mdma_done1_3 (& self) -> INT_EVENT0_MIS_MDMA_DONE1_3_R { INT_EVENT0_MIS_MDMA_DONE1_3_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mpec_rx_err (& self) -> INT_EVENT0_MIS_MPEC_RX_ERR_R { INT_EVENT0_MIS_MPEC_RX_ERR_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
pub fn int_event0_mis_timeouta (& self) -> INT_EVENT0_MIS_TIMEOUTA_R { INT_EVENT0_MIS_TIMEOUTA_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
pub fn int_event0_mis_timeoutb (& self) -> INT_EVENT0_MIS_TIMEOUTB_R { INT_EVENT0_MIS_TIMEOUTB_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
pub fn int_event0_mis_srxdone (& self) -> INT_EVENT0_MIS_SRXDONE_R { INT_EVENT0_MIS_SRXDONE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_mis_stxdone (& self) -> INT_EVENT0_MIS_STXDONE_R { INT_EVENT0_MIS_STXDONE_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event0_mis_srxfifotrg (& self) -> INT_EVENT0_MIS_SRXFIFOTRG_R { INT_EVENT0_MIS_SRXFIFOTRG_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event0_mis_stxfifotrg (& self) -> INT_EVENT0_MIS_STXFIFOTRG_R { INT_EVENT0_MIS_STXFIFOTRG_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_mis_srxfifofull (& self) -> INT_EVENT0_MIS_SRXFIFOFULL_R { INT_EVENT0_MIS_SRXFIFOFULL_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_mis_stxempty (& self) -> INT_EVENT0_MIS_STXEMPTY_R { INT_EVENT0_MIS_STXEMPTY_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Slave START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_sstart (& self) -> INT_EVENT0_MIS_SSTART_R { INT_EVENT0_MIS_SSTART_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Slave STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_sstop (& self) -> INT_EVENT0_MIS_SSTOP_R { INT_EVENT0_MIS_SSTOP_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
pub fn int_event0_mis_sgencall (& self) -> INT_EVENT0_MIS_SGENCALL_R { INT_EVENT0_MIS_SGENCALL_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_mis_sdma_done1_2 (& self) -> INT_EVENT0_MIS_SDMA_DONE1_2_R { INT_EVENT0_MIS_SDMA_DONE1_2_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_mis_sdma_done1_3 (& self) -> INT_EVENT0_MIS_SDMA_DONE1_3_R { INT_EVENT0_MIS_SDMA_DONE1_3_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_mis_spec_rx_err (& self) -> INT_EVENT0_MIS_SPEC_RX_ERR_R { INT_EVENT0_MIS_SPEC_RX_ERR_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
pub fn int_event0_mis_stx_unfl (& self) -> INT_EVENT0_MIS_STX_UNFL_R { INT_EVENT0_MIS_STX_UNFL_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
pub fn int_event0_mis_srx_ovfl (& self) -> INT_EVENT0_MIS_SRX_OVFL_R { INT_EVENT0_MIS_SRX_OVFL_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
pub fn int_event0_mis_sarblost (& self) -> INT_EVENT0_MIS_SARBLOST_R { INT_EVENT0_MIS_SARBLOST_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Interrupt overflow"]
# [inline (always)]
pub fn int_event0_mis_intr_ovfl (& self) -> INT_EVENT0_MIS_INTR_OVFL_R { INT_EVENT0_MIS_INTR_OVFL_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_MIS to value 0"]
impl crate :: Resettable for INT_EVENT0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iset`]
module"]
pub type INT_EVENT0_ISET = crate :: Reg < int_event0_iset :: INT_EVENT0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event0_iset { # [doc = "Register `INT_EVENT0_ISET` writer"]
pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."]
pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"]
pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"]
pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"]
pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"]
pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"]
pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"]
pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"]
pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"]
pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"]
pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"]
pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"]
pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"]
pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"]
pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"]
impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iclr`]
module"]
pub type INT_EVENT0_ICLR = crate :: Reg < int_event0_iclr :: INT_EVENT0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event0_iclr { # [doc = "Register `INT_EVENT0_ICLR` writer"]
pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MRXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MRXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_MRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ICLR_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXDONE_AW :: INT_EVENT0_ICLR_MRXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mrxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXDONE_AW :: INT_EVENT0_ICLR_MRXDONE_CLR) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MTXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MTXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MTXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_MTXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MTXDONE` writer - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ICLR_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXDONE_AW :: INT_EVENT0_ICLR_MTXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mtxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXDONE_AW :: INT_EVENT0_ICLR_MTXDONE_CLR) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOTRG_AW :: INT_EVENT0_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOTRG_AW :: INT_EVENT0_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXFIFOTRG_AW :: INT_EVENT0_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXFIFOTRG_AW :: INT_EVENT0_ICLR_MTXFIFOTRG_CLR) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MRXFIFOFULL_CLR = 1 , } impl From < INT_EVENT0_ICLR_MRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MRXFIFOFULL` writer - RXFIFO full event."]
pub type INT_EVENT0_ICLR_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOFULL_AW :: INT_EVENT0_ICLR_MRXFIFOFULL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOFULL_AW :: INT_EVENT0_ICLR_MRXFIFOFULL_CLR) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MTXEMPTY_CLR = 1 , } impl From < INT_EVENT0_ICLR_MTXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ICLR_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXEMPTY_AW :: INT_EVENT0_ICLR_MTXEMPTY_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mtxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXEMPTY_AW :: INT_EVENT0_ICLR_MTXEMPTY_CLR) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MNACK_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MNACK_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MNACK_CLR = 1 , } impl From < INT_EVENT0_ICLR_MNACK_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MNACK` writer - Address/Data NACK Interrupt"]
pub type INT_EVENT0_ICLR_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MNACK_AW :: INT_EVENT0_ICLR_MNACK_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mnack_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MNACK_AW :: INT_EVENT0_ICLR_MNACK_CLR) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MSTART_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MSTART_CLR = 1 , } impl From < INT_EVENT0_ICLR_MSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MSTART` writer - START Detection Interrupt"]
pub type INT_EVENT0_ICLR_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTART_AW :: INT_EVENT0_ICLR_MSTART_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTART_AW :: INT_EVENT0_ICLR_MSTART_CLR) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MSTOP_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MSTOP_CLR = 1 , } impl From < INT_EVENT0_ICLR_MSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MSTOP` writer - STOP Detection Interrupt"]
pub type INT_EVENT0_ICLR_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTOP_AW :: INT_EVENT0_ICLR_MSTOP_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTOP_AW :: INT_EVENT0_ICLR_MSTOP_CLR) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MARBLOST_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MARBLOST_CLR = 1 , } impl From < INT_EVENT0_ICLR_MARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MARBLOST` writer - Arbitration Lost Interrupt"]
pub type INT_EVENT0_ICLR_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MARBLOST_AW :: INT_EVENT0_ICLR_MARBLOST_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_marblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MARBLOST_AW :: INT_EVENT0_ICLR_MARBLOST_CLR) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MDMA_DONE1_2_CLR = 1 , } impl From < INT_EVENT0_ICLR_MDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ICLR_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_2_AW :: INT_EVENT0_ICLR_MDMA_DONE1_2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_2_AW :: INT_EVENT0_ICLR_MDMA_DONE1_2_CLR) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MDMA_DONE1_3_CLR = 1 , } impl From < INT_EVENT0_ICLR_MDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ICLR_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_3_AW :: INT_EVENT0_ICLR_MDMA_DONE1_3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_3_AW :: INT_EVENT0_ICLR_MDMA_DONE1_3_CLR) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MPEC_RX_ERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_MPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_ICLR_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MPEC_RX_ERR_AW :: INT_EVENT0_ICLR_MPEC_RX_ERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mpec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MPEC_RX_ERR_AW :: INT_EVENT0_ICLR_MPEC_RX_ERR_CLR) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TIMEOUTA_CLR = 1 , } impl From < INT_EVENT0_ICLR_TIMEOUTA_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TIMEOUTA` writer - Timeout A interrupt"]
pub type INT_EVENT0_ICLR_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTA_AW :: INT_EVENT0_ICLR_TIMEOUTA_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_timeouta_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTA_AW :: INT_EVENT0_ICLR_TIMEOUTA_CLR) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TIMEOUTB_CLR = 1 , } impl From < INT_EVENT0_ICLR_TIMEOUTB_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TIMEOUTB` writer - Timeout B Interrupt"]
pub type INT_EVENT0_ICLR_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTB_AW :: INT_EVENT0_ICLR_TIMEOUTB_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_timeoutb_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTB_AW :: INT_EVENT0_ICLR_TIMEOUTB_CLR) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ICLR_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXDONE_AW :: INT_EVENT0_ICLR_SRXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXDONE_AW :: INT_EVENT0_ICLR_SRXDONE_CLR) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_STXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STXDONE` writer - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ICLR_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXDONE_AW :: INT_EVENT0_ICLR_STXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXDONE_AW :: INT_EVENT0_ICLR_STXDONE_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOTRG_AW :: INT_EVENT0_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOTRG_AW :: INT_EVENT0_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXFIFOTRG_AW :: INT_EVENT0_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXFIFOTRG_AW :: INT_EVENT0_ICLR_STXFIFOTRG_CLR) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRXFIFOFULL_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_ICLR_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOFULL_AW :: INT_EVENT0_ICLR_SRXFIFOFULL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOFULL_AW :: INT_EVENT0_ICLR_SRXFIFOFULL_CLR) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STXEMPTY_CLR = 1 , } impl From < INT_EVENT0_ICLR_STXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ICLR_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXEMPTY_AW :: INT_EVENT0_ICLR_STXEMPTY_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXEMPTY_AW :: INT_EVENT0_ICLR_STXEMPTY_CLR) } } # [doc = "Slave START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SSTART_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SSTART_CLR = 1 , } impl From < INT_EVENT0_ICLR_SSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SSTART` writer - Slave START Detection Interrupt"]
pub type INT_EVENT0_ICLR_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTART_AW :: INT_EVENT0_ICLR_SSTART_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTART_AW :: INT_EVENT0_ICLR_SSTART_CLR) } } # [doc = "Slave STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SSTOP_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SSTOP_CLR = 1 , } impl From < INT_EVENT0_ICLR_SSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SSTOP` writer - Slave STOP Detection Interrupt"]
pub type INT_EVENT0_ICLR_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTOP_AW :: INT_EVENT0_ICLR_SSTOP_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTOP_AW :: INT_EVENT0_ICLR_SSTOP_CLR) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SGENCALL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SGENCALL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SGENCALL_CLR = 1 , } impl From < INT_EVENT0_ICLR_SGENCALL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SGENCALL` writer - General Call Interrupt"]
pub type INT_EVENT0_ICLR_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SGENCALL_AW :: INT_EVENT0_ICLR_SGENCALL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sgencall_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SGENCALL_AW :: INT_EVENT0_ICLR_SGENCALL_CLR) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SDMA_DONE1_2_CLR = 1 , } impl From < INT_EVENT0_ICLR_SDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ICLR_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_2_AW :: INT_EVENT0_ICLR_SDMA_DONE1_2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_2_AW :: INT_EVENT0_ICLR_SDMA_DONE1_2_CLR) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SDMA_DONE1_3_CLR = 1 , } impl From < INT_EVENT0_ICLR_SDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ICLR_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_3_AW :: INT_EVENT0_ICLR_SDMA_DONE1_3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_3_AW :: INT_EVENT0_ICLR_SDMA_DONE1_3_CLR) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SPEC_RX_ERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_SPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_ICLR_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SPEC_RX_ERR_AW :: INT_EVENT0_ICLR_SPEC_RX_ERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_spec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SPEC_RX_ERR_AW :: INT_EVENT0_ICLR_SPEC_RX_ERR_CLR) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STX_UNFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STX_UNFL_CLR = 1 , } impl From < INT_EVENT0_ICLR_STX_UNFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STX_UNFL` writer - Slave TX FIFO underflow"]
pub type INT_EVENT0_ICLR_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STX_UNFL_AW :: INT_EVENT0_ICLR_STX_UNFL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stx_unfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STX_UNFL_AW :: INT_EVENT0_ICLR_STX_UNFL_CLR) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRX_OVFL_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRX_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRX_OVFL` writer - Slave RX FIFO overflow"]
pub type INT_EVENT0_ICLR_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRX_OVFL_AW :: INT_EVENT0_ICLR_SRX_OVFL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srx_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRX_OVFL_AW :: INT_EVENT0_ICLR_SRX_OVFL_CLR) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SARBLOST_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SARBLOST_CLR = 1 , } impl From < INT_EVENT0_ICLR_SARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SARBLOST` writer - Slave Arbitration Lost"]
pub type INT_EVENT0_ICLR_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SARBLOST_AW :: INT_EVENT0_ICLR_SARBLOST_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sarblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SARBLOST_AW :: INT_EVENT0_ICLR_SARBLOST_CLR) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_INTR_OVFL_CLR = 1 , } impl From < INT_EVENT0_ICLR_INTR_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_INTR_OVFL` writer - Interrupt overflow"]
pub type INT_EVENT0_ICLR_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_INTR_OVFL_AW :: INT_EVENT0_ICLR_INTR_OVFL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_intr_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_INTR_OVFL_AW :: INT_EVENT0_ICLR_INTR_OVFL_CLR) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mrxdone (& mut self) -> INT_EVENT0_ICLR_MRXDONE_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mtxdone (& mut self) -> INT_EVENT0_ICLR_MTXDONE_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mrxfifotrg (& mut self) -> INT_EVENT0_ICLR_MRXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mtxfifotrg (& mut self) -> INT_EVENT0_ICLR_MTXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mrxfifofull (& mut self) -> INT_EVENT0_ICLR_MRXFIFOFULL_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mtxempty (& mut self) -> INT_EVENT0_ICLR_MTXEMPTY_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mnack (& mut self) -> INT_EVENT0_ICLR_MNACK_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mstart (& mut self) -> INT_EVENT0_ICLR_MSTART_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mstop (& mut self) -> INT_EVENT0_ICLR_MSTOP_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_marblost (& mut self) -> INT_EVENT0_ICLR_MARBLOST_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mdma_done1_2 (& mut self) -> INT_EVENT0_ICLR_MDMA_DONE1_2_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mdma_done1_3 (& mut self) -> INT_EVENT0_ICLR_MDMA_DONE1_3_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mpec_rx_err (& mut self) -> INT_EVENT0_ICLR_MPEC_RX_ERR_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_timeouta (& mut self) -> INT_EVENT0_ICLR_TIMEOUTA_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_timeoutb (& mut self) -> INT_EVENT0_ICLR_TIMEOUTB_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srxdone (& mut self) -> INT_EVENT0_ICLR_SRXDONE_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stxdone (& mut self) -> INT_EVENT0_ICLR_STXDONE_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srxfifotrg (& mut self) -> INT_EVENT0_ICLR_SRXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 18 > { INT_EVENT0_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stxfifotrg (& mut self) -> INT_EVENT0_ICLR_STXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 19 > { INT_EVENT0_ICLR_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srxfifofull (& mut self) -> INT_EVENT0_ICLR_SRXFIFOFULL_W < INT_EVENT0_ICLR_SPEC , 20 > { INT_EVENT0_ICLR_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stxempty (& mut self) -> INT_EVENT0_ICLR_STXEMPTY_W < INT_EVENT0_ICLR_SPEC , 21 > { INT_EVENT0_ICLR_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Slave START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sstart (& mut self) -> INT_EVENT0_ICLR_SSTART_W < INT_EVENT0_ICLR_SPEC , 22 > { INT_EVENT0_ICLR_SSTART_W :: new (self) } # [doc = "Bit 23 - Slave STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sstop (& mut self) -> INT_EVENT0_ICLR_SSTOP_W < INT_EVENT0_ICLR_SPEC , 23 > { INT_EVENT0_ICLR_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sgencall (& mut self) -> INT_EVENT0_ICLR_SGENCALL_W < INT_EVENT0_ICLR_SPEC , 24 > { INT_EVENT0_ICLR_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sdma_done1_2 (& mut self) -> INT_EVENT0_ICLR_SDMA_DONE1_2_W < INT_EVENT0_ICLR_SPEC , 25 > { INT_EVENT0_ICLR_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sdma_done1_3 (& mut self) -> INT_EVENT0_ICLR_SDMA_DONE1_3_W < INT_EVENT0_ICLR_SPEC , 26 > { INT_EVENT0_ICLR_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_spec_rx_err (& mut self) -> INT_EVENT0_ICLR_SPEC_RX_ERR_W < INT_EVENT0_ICLR_SPEC , 27 > { INT_EVENT0_ICLR_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stx_unfl (& mut self) -> INT_EVENT0_ICLR_STX_UNFL_W < INT_EVENT0_ICLR_SPEC , 28 > { INT_EVENT0_ICLR_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srx_ovfl (& mut self) -> INT_EVENT0_ICLR_SRX_OVFL_W < INT_EVENT0_ICLR_SPEC , 29 > { INT_EVENT0_ICLR_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sarblost (& mut self) -> INT_EVENT0_ICLR_SARBLOST_W < INT_EVENT0_ICLR_SPEC , 30 > { INT_EVENT0_ICLR_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_intr_ovfl (& mut self) -> INT_EVENT0_ICLR_INTR_OVFL_W < INT_EVENT0_ICLR_SPEC , 31 > { INT_EVENT0_ICLR_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iidx`]
module"]
pub type INT_EVENT1_IIDX = crate :: Reg < int_event1_iidx :: INT_EVENT1_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event1_iidx { # [doc = "Register `INT_EVENT1_IIDX` reader"]
pub type R = crate :: R < INT_EVENT1_IIDX_SPEC > ; # [doc = "Field `INT_EVENT1_IIDX_STAT` reader - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
pub type INT_EVENT1_IIDX_STAT_R = crate :: FieldReader < INT_EVENT1_IIDX_STAT_A > ; # [doc = "I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT1_IIDX_STAT_NO_INTR = 0 , # [doc = "1: MRXFIFOTRG"]
INT_EVENT1_IIDX_STAT_MRXFIFOTRG = 1 , # [doc = "2: MTXFIFOTRG"]
INT_EVENT1_IIDX_STAT_MTXFIFOTRG = 2 , # [doc = "3: SRXFIFOTRG"]
INT_EVENT1_IIDX_STAT_SRXFIFOTRG = 3 , # [doc = "4: STXFIFOTRG"]
INT_EVENT1_IIDX_STAT_STXFIFOTRG = 4 , } impl From < INT_EVENT1_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT1_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MRXFIFOTRG) , 2 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MTXFIFOTRG) , 3 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_SRXFIFOTRG) , 4 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_STXFIFOTRG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR } # [doc = "MRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_mrxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MRXFIFOTRG } # [doc = "MTXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_mtxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MTXFIFOTRG } # [doc = "SRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_srxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_SRXFIFOTRG } # [doc = "STXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_stxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_STXFIFOTRG } } impl R { # [doc = "Bits 0:7 - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event1_iidx_stat (& self) -> INT_EVENT1_IIDX_STAT_R { INT_EVENT1_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_imask`]
module"]
pub type INT_EVENT1_IMASK = crate :: Reg < int_event1_imask :: INT_EVENT1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event1_imask { # [doc = "Register `INT_EVENT1_IMASK` reader"]
pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"]
pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_CLR , true => INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event1_imask_mrxfifotrg (& self) -> INT_EVENT1_IMASK_MRXFIFOTRG_R { INT_EVENT1_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event1_imask_mtxfifotrg (& self) -> INT_EVENT1_IMASK_MTXFIFOTRG_R { INT_EVENT1_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event1_imask_srxfifotrg (& self) -> INT_EVENT1_IMASK_SRXFIFOTRG_R { INT_EVENT1_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event1_imask_stxfifotrg (& self) -> INT_EVENT1_IMASK_STXFIFOTRG_R { INT_EVENT1_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_mrxfifotrg (& mut self) -> INT_EVENT1_IMASK_MRXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_mtxfifotrg (& mut self) -> INT_EVENT1_IMASK_MTXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 1 > { INT_EVENT1_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_srxfifotrg (& mut self) -> INT_EVENT1_IMASK_SRXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 2 > { INT_EVENT1_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_stxfifotrg (& mut self) -> INT_EVENT1_IMASK_STXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 3 > { INT_EVENT1_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_ris`]
module"]
pub type INT_EVENT1_RIS = crate :: Reg < int_event1_ris :: INT_EVENT1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event1_ris { # [doc = "Register `INT_EVENT1_RIS` reader"]
pub type R = crate :: R < INT_EVENT1_RIS_SPEC > ; # [doc = "Field `INT_EVENT1_RIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_RIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_CLR , true => INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_RIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_RIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_CLR , true => INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_RIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_RIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_CLR , true => INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_srxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_RIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_RIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_CLR , true => INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_stxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event1_ris_mrxfifotrg (& self) -> INT_EVENT1_RIS_MRXFIFOTRG_R { INT_EVENT1_RIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event1_ris_mtxfifotrg (& self) -> INT_EVENT1_RIS_MTXFIFOTRG_R { INT_EVENT1_RIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event1_ris_srxfifotrg (& self) -> INT_EVENT1_RIS_SRXFIFOTRG_R { INT_EVENT1_RIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event1_ris_stxfifotrg (& self) -> INT_EVENT1_RIS_STXFIFOTRG_R { INT_EVENT1_RIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_RIS to value 0"]
impl crate :: Resettable for INT_EVENT1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_mis`]
module"]
pub type INT_EVENT1_MIS = crate :: Reg < int_event1_mis :: INT_EVENT1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event1_mis { # [doc = "Register `INT_EVENT1_MIS` reader"]
pub type R = crate :: R < INT_EVENT1_MIS_SPEC > ; # [doc = "Field `INT_EVENT1_MIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_MIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_CLR , true => INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_MIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_MIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_CLR , true => INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_MIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_MIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_CLR , true => INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_srxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_MIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_MIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_CLR , true => INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_stxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event1_mis_mrxfifotrg (& self) -> INT_EVENT1_MIS_MRXFIFOTRG_R { INT_EVENT1_MIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event1_mis_mtxfifotrg (& self) -> INT_EVENT1_MIS_MTXFIFOTRG_R { INT_EVENT1_MIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event1_mis_srxfifotrg (& self) -> INT_EVENT1_MIS_SRXFIFOTRG_R { INT_EVENT1_MIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event1_mis_stxfifotrg (& self) -> INT_EVENT1_MIS_STXFIFOTRG_R { INT_EVENT1_MIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_MIS to value 0"]
impl crate :: Resettable for INT_EVENT1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iset`]
module"]
pub type INT_EVENT1_ISET = crate :: Reg < int_event1_iset :: INT_EVENT1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event1_iset { # [doc = "Register `INT_EVENT1_ISET` writer"]
pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"]
impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iclr`]
module"]
pub type INT_EVENT1_ICLR = crate :: Reg < int_event1_iclr :: INT_EVENT1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event1_iclr { # [doc = "Register `INT_EVENT1_ICLR` writer"]
pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_mrxfifotrg (& mut self) -> INT_EVENT1_ICLR_MRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_mtxfifotrg (& mut self) -> INT_EVENT1_ICLR_MTXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_srxfifotrg (& mut self) -> INT_EVENT1_ICLR_SRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_stxfifotrg (& mut self) -> INT_EVENT1_ICLR_STXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iidx`]
module"]
pub type INT_EVENT2_IIDX = crate :: Reg < int_event2_iidx :: INT_EVENT2_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event2_iidx { # [doc = "Register `INT_EVENT2_IIDX` reader"]
pub type R = crate :: R < INT_EVENT2_IIDX_SPEC > ; # [doc = "Field `INT_EVENT2_IIDX_STAT` reader - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
pub type INT_EVENT2_IIDX_STAT_R = crate :: FieldReader < INT_EVENT2_IIDX_STAT_A > ; # [doc = "I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT2_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT2_IIDX_STAT_NO_INTR = 0 , # [doc = "1: MRXFIFOTRG"]
INT_EVENT2_IIDX_STAT_MRXFIFOTRG = 1 , # [doc = "2: MTXFIFOTRG"]
INT_EVENT2_IIDX_STAT_MTXFIFOTRG = 2 , # [doc = "3: SRXFIFOTRG"]
INT_EVENT2_IIDX_STAT_SRXFIFOTRG = 3 , # [doc = "4: STXFIFOTRG"]
INT_EVENT2_IIDX_STAT_STXFIFOTRG = 4 , } impl From < INT_EVENT2_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT2_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT2_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT2_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT2_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MRXFIFOTRG) , 2 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MTXFIFOTRG) , 3 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_SRXFIFOTRG) , 4 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_STXFIFOTRG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR } # [doc = "MRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_mrxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MRXFIFOTRG } # [doc = "MTXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_mtxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MTXFIFOTRG } # [doc = "SRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_srxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_SRXFIFOTRG } # [doc = "STXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_stxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_STXFIFOTRG } } impl R { # [doc = "Bits 0:7 - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event2_iidx_stat (& self) -> INT_EVENT2_IIDX_STAT_R { INT_EVENT2_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT2_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_imask`]
module"]
pub type INT_EVENT2_IMASK = crate :: Reg < int_event2_imask :: INT_EVENT2_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event2_imask { # [doc = "Register `INT_EVENT2_IMASK` reader"]
pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"]
pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR , true => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event2_imask_mrxfifotrg (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_R { INT_EVENT2_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event2_imask_mtxfifotrg (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_R { INT_EVENT2_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event2_imask_srxfifotrg (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_R { INT_EVENT2_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event2_imask_stxfifotrg (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_R { INT_EVENT2_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_mrxfifotrg (& mut self) -> INT_EVENT2_IMASK_MRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 0 > { INT_EVENT2_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_mtxfifotrg (& mut self) -> INT_EVENT2_IMASK_MTXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 1 > { INT_EVENT2_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_srxfifotrg (& mut self) -> INT_EVENT2_IMASK_SRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 2 > { INT_EVENT2_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_stxfifotrg (& mut self) -> INT_EVENT2_IMASK_STXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 3 > { INT_EVENT2_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_ris`]
module"]
pub type INT_EVENT2_RIS = crate :: Reg < int_event2_ris :: INT_EVENT2_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event2_ris { # [doc = "Register `INT_EVENT2_RIS` reader"]
pub type R = crate :: R < INT_EVENT2_RIS_SPEC > ; # [doc = "Field `INT_EVENT2_RIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_RIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_CLR , true => INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_RIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_RIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_CLR , true => INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_RIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_RIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_CLR , true => INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_RIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_RIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_CLR , true => INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event2_ris_mrxfifotrg (& self) -> INT_EVENT2_RIS_MRXFIFOTRG_R { INT_EVENT2_RIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event2_ris_mtxfifotrg (& self) -> INT_EVENT2_RIS_MTXFIFOTRG_R { INT_EVENT2_RIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event2_ris_srxfifotrg (& self) -> INT_EVENT2_RIS_SRXFIFOTRG_R { INT_EVENT2_RIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event2_ris_stxfifotrg (& self) -> INT_EVENT2_RIS_STXFIFOTRG_R { INT_EVENT2_RIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_RIS to value 0"]
impl crate :: Resettable for INT_EVENT2_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_mis`]
module"]
pub type INT_EVENT2_MIS = crate :: Reg < int_event2_mis :: INT_EVENT2_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event2_mis { # [doc = "Register `INT_EVENT2_MIS` reader"]
pub type R = crate :: R < INT_EVENT2_MIS_SPEC > ; # [doc = "Field `INT_EVENT2_MIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_MIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_CLR , true => INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_MIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_MIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_CLR , true => INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_MIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_MIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_CLR , true => INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_MIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_MIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_CLR , true => INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event2_mis_mrxfifotrg (& self) -> INT_EVENT2_MIS_MRXFIFOTRG_R { INT_EVENT2_MIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event2_mis_mtxfifotrg (& self) -> INT_EVENT2_MIS_MTXFIFOTRG_R { INT_EVENT2_MIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event2_mis_srxfifotrg (& self) -> INT_EVENT2_MIS_SRXFIFOTRG_R { INT_EVENT2_MIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event2_mis_stxfifotrg (& self) -> INT_EVENT2_MIS_STXFIFOTRG_R { INT_EVENT2_MIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_MIS to value 0"]
impl crate :: Resettable for INT_EVENT2_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iset`]
module"]
pub type INT_EVENT2_ISET = crate :: Reg < int_event2_iset :: INT_EVENT2_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event2_iset { # [doc = "Register `INT_EVENT2_ISET` writer"]
pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_mrxfifotrg (& mut self) -> INT_EVENT2_ISET_MRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 0 > { INT_EVENT2_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_mtxfifotrg (& mut self) -> INT_EVENT2_ISET_MTXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 1 > { INT_EVENT2_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_srxfifotrg (& mut self) -> INT_EVENT2_ISET_SRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 2 > { INT_EVENT2_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_stxfifotrg (& mut self) -> INT_EVENT2_ISET_STXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 3 > { INT_EVENT2_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"]
impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iclr`]
module"]
pub type INT_EVENT2_ICLR = crate :: Reg < int_event2_iclr :: INT_EVENT2_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event2_iclr { # [doc = "Register `INT_EVENT2_ICLR` writer"]
pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MRXFIFOTRG_AW :: INT_EVENT2_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MRXFIFOTRG_AW :: INT_EVENT2_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MTXFIFOTRG_AW :: INT_EVENT2_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MTXFIFOTRG_AW :: INT_EVENT2_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_SRXFIFOTRG_AW :: INT_EVENT2_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_SRXFIFOTRG_AW :: INT_EVENT2_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_STXFIFOTRG_AW :: INT_EVENT2_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_STXFIFOTRG_AW :: INT_EVENT2_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_mrxfifotrg (& mut self) -> INT_EVENT2_ICLR_MRXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 0 > { INT_EVENT2_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_mtxfifotrg (& mut self) -> INT_EVENT2_ICLR_MTXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 1 > { INT_EVENT2_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_srxfifotrg (& mut self) -> INT_EVENT2_ICLR_SRXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 2 > { INT_EVENT2_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_stxfifotrg (& mut self) -> INT_EVENT2_ICLR_STXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 3 > { INT_EVENT2_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_INT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
pub type EVT_MODE_INT1_CFG_R = crate :: FieldReader < EVT_MODE_INT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_DISABLE) , 1 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_disable (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_software (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
# [inline (always)]
pub fn evt_mode_int1_cfg (& self) -> EVT_MODE_INT1_CFG_R { EVT_MODE_INT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GFCTL (rw) register accessor: I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gfctl`]
module"]
pub type GFCTL = crate :: Reg < gfctl :: GFCTL_SPEC > ; # [doc = "I2C Glitch Filter Control"]
pub mod gfctl { # [doc = "Register `GFCTL` reader"]
pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"]
pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_DGFSEL` reader - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
pub type GFCTL_DGFSEL_R = crate :: FieldReader < GFCTL_DGFSEL_A > ; # [doc = "Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GFCTL_DGFSEL_A { # [doc = "0: DISABLED"]
GFCTL_DGFSEL_DISABLED = 0 , # [doc = "1: CLK_1"]
GFCTL_DGFSEL_CLK_1 = 1 , # [doc = "2: CLK_2"]
GFCTL_DGFSEL_CLK_2 = 2 , # [doc = "3: CLK_3"]
GFCTL_DGFSEL_CLK_3 = 3 , # [doc = "4: CLK_4"]
GFCTL_DGFSEL_CLK_4 = 4 , # [doc = "5: CLK_8"]
GFCTL_DGFSEL_CLK_8 = 5 , # [doc = "6: CLK_16"]
GFCTL_DGFSEL_CLK_16 = 6 , # [doc = "7: CLK_31"]
GFCTL_DGFSEL_CLK_31 = 7 , } impl From < GFCTL_DGFSEL_A > for u8 { # [inline (always)]
fn from (variant : GFCTL_DGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_DGFSEL_A { type Ux = u8 ; } impl GFCTL_DGFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_DGFSEL_A { match self . bits { 0 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED , 1 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 , 2 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 , 3 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 , 4 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 , 5 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 , 6 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 , 7 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_gfctl_dgfsel_disabled (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED } # [doc = "CLK_1"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_1 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 } # [doc = "CLK_2"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_2 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 } # [doc = "CLK_3"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_3 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 } # [doc = "CLK_4"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_4 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 } # [doc = "CLK_8"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_8 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 } # [doc = "CLK_16"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_16 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 } # [doc = "CLK_31"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_31 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 } } # [doc = "Field `GFCTL_DGFSEL` writer - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
pub type GFCTL_DGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , GFCTL_DGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_DGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn gfctl_dgfsel_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) } # [doc = "CLK_1"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_1 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1) } # [doc = "CLK_2"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_2 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2) } # [doc = "CLK_3"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_3 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3) } # [doc = "CLK_4"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_4 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4) } # [doc = "CLK_8"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_8 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8) } # [doc = "CLK_16"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_16 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16) } # [doc = "CLK_31"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_31 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31) } } # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"]
GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"]
GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)]
fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"]
GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"]
GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"]
GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"]
GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)]
fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } # [doc = "Field `GFCTL_CHAIN` reader - Analog and digital noise filters chaining enable."]
pub type GFCTL_CHAIN_R = crate :: BitReader < GFCTL_CHAIN_A > ; # [doc = "Analog and digital noise filters chaining enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GFCTL_CHAIN_A { # [doc = "0: DISABLE"]
GFCTL_CHAIN_DISABLE = 0 , # [doc = "1: ENABLE"]
GFCTL_CHAIN_ENABLE = 1 , } impl From < GFCTL_CHAIN_A > for bool { # [inline (always)]
fn from (variant : GFCTL_CHAIN_A) -> Self { variant as u8 != 0 } } impl GFCTL_CHAIN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_CHAIN_A { match self . bits { false => GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE , true => GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_gfctl_chain_disable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_gfctl_chain_enable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE } } # [doc = "Field `GFCTL_CHAIN` writer - Analog and digital noise filters chaining enable."]
pub type GFCTL_CHAIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_CHAIN_A > ; impl < 'a , REG , const O : u8 > GFCTL_CHAIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn gfctl_chain_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn gfctl_chain_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE) } } impl R { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
# [inline (always)]
pub fn gfctl_dgfsel (& self) -> GFCTL_DGFSEL_R { GFCTL_DGFSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
# [inline (always)]
pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."]
# [inline (always)]
pub fn gfctl_chain (& self) -> GFCTL_CHAIN_R { GFCTL_CHAIN_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
# [inline (always)]
# [must_use]
pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W < GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."]
# [inline (always)]
# [must_use]
pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W < GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"]
impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"]
impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"]
impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TIMEOUT_CTL (rw) register accessor: I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeout_ctl`]
module"]
pub type TIMEOUT_CTL = crate :: Reg < timeout_ctl :: TIMEOUT_CTL_SPEC > ; # [doc = "I2C Timeout Count Control Register"]
pub mod timeout_ctl { # [doc = "Register `TIMEOUT_CTL` reader"]
pub type R = crate :: R < TIMEOUT_CTL_SPEC > ; # [doc = "Register `TIMEOUT_CTL` writer"]
pub type W = crate :: W < TIMEOUT_CTL_SPEC > ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` reader - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
pub type TIMEOUT_CTL_TCNTLA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` writer - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
pub type TIMEOUT_CTL_TCNTLA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTAEN` reader - Timeout Counter A Enable"]
pub type TIMEOUT_CTL_TCNTAEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTAEN_A > ; # [doc = "Timeout Counter A Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TIMEOUT_CTL_TCNTAEN_A { # [doc = "0: DISABLE"]
TIMEOUT_CTL_TCNTAEN_DISABLE = 0 , # [doc = "1: ENABLE"]
TIMEOUT_CTL_TCNTAEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTAEN_A > for bool { # [inline (always)]
fn from (variant : TIMEOUT_CTL_TCNTAEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTAEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TIMEOUT_CTL_TCNTAEN_A { match self . bits { false => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE , true => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntaen_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntaen_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTAEN` writer - Timeout Counter A Enable"]
pub type TIMEOUT_CTL_TCNTAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTAEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE) } } # [doc = "Field `TIMEOUT_CTL_TCNTLB` reader - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
pub type TIMEOUT_CTL_TCNTLB_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLB` writer - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
pub type TIMEOUT_CTL_TCNTLB_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTBEN` reader - Timeout Counter B Enable"]
pub type TIMEOUT_CTL_TCNTBEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTBEN_A > ; # [doc = "Timeout Counter B Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TIMEOUT_CTL_TCNTBEN_A { # [doc = "0: DISABLE"]
TIMEOUT_CTL_TCNTBEN_DISABLE = 0 , # [doc = "1: ENABLE"]
TIMEOUT_CTL_TCNTBEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTBEN_A > for bool { # [inline (always)]
fn from (variant : TIMEOUT_CTL_TCNTBEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTBEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TIMEOUT_CTL_TCNTBEN_A { match self . bits { false => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE , true => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntben_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntben_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTBEN` writer - Timeout Counter B Enable"]
pub type TIMEOUT_CTL_TCNTBEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTBEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTBEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntben_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntben_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE) } } impl R { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
# [inline (always)]
pub fn timeout_ctl_tcntla (& self) -> TIMEOUT_CTL_TCNTLA_R { TIMEOUT_CTL_TCNTLA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 15 - Timeout Counter A Enable"]
# [inline (always)]
pub fn timeout_ctl_tcntaen (& self) -> TIMEOUT_CTL_TCNTAEN_R { TIMEOUT_CTL_TCNTAEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
# [inline (always)]
pub fn timeout_ctl_tcntlb (& self) -> TIMEOUT_CTL_TCNTLB_R { TIMEOUT_CTL_TCNTLB_R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 31 - Timeout Counter B Enable"]
# [inline (always)]
pub fn timeout_ctl_tcntben (& self) -> TIMEOUT_CTL_TCNTBEN_R { TIMEOUT_CTL_TCNTBEN_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntla (& mut self) -> TIMEOUT_CTL_TCNTLA_W < TIMEOUT_CTL_SPEC , 0 > { TIMEOUT_CTL_TCNTLA_W :: new (self) } # [doc = "Bit 15 - Timeout Counter A Enable"]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntaen (& mut self) -> TIMEOUT_CTL_TCNTAEN_W < TIMEOUT_CTL_SPEC , 15 > { TIMEOUT_CTL_TCNTAEN_W :: new (self) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntlb (& mut self) -> TIMEOUT_CTL_TCNTLB_W < TIMEOUT_CTL_SPEC , 16 > { TIMEOUT_CTL_TCNTLB_W :: new (self) } # [doc = "Bit 31 - Timeout Counter B Enable"]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntben (& mut self) -> TIMEOUT_CTL_TCNTBEN_W < TIMEOUT_CTL_SPEC , 31 > { TIMEOUT_CTL_TCNTBEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TIMEOUT_CTL_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_ctl::R`](R) reader structure"]
impl crate :: Readable for TIMEOUT_CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`timeout_ctl::W`](W) writer structure"]
impl crate :: Writable for TIMEOUT_CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TIMEOUT_CTL to value 0x0002_0002"]
impl crate :: Resettable for TIMEOUT_CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } } # [doc = "TIMEOUT_CNT (r) register accessor: I2C Timeout Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_cnt::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeout_cnt`]
module"]
pub type TIMEOUT_CNT = crate :: Reg < timeout_cnt :: TIMEOUT_CNT_SPEC > ; # [doc = "I2C Timeout Count Register"]
pub mod timeout_cnt { # [doc = "Register `TIMEOUT_CNT` reader"]
pub type R = crate :: R < TIMEOUT_CNT_SPEC > ; # [doc = "Field `TIMEOUT_CNT_TCNTA` reader - Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"]
pub type TIMEOUT_CNT_TCNTA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CNT_TCNTB` reader - Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"]
pub type TIMEOUT_CNT_TCNTB_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"]
# [inline (always)]
pub fn timeout_cnt_tcnta (& self) -> TIMEOUT_CNT_TCNTA_R { TIMEOUT_CNT_TCNTA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 16:23 - Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"]
# [inline (always)]
pub fn timeout_cnt_tcntb (& self) -> TIMEOUT_CNT_TCNTB_R { TIMEOUT_CNT_TCNTB_R :: new (((self . bits >> 16) & 0xff) as u8) } } # [doc = "I2C Timeout Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TIMEOUT_CNT_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CNT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_cnt::R`](R) reader structure"]
impl crate :: Readable for TIMEOUT_CNT_SPEC { } # [doc = "`reset()` method sets TIMEOUT_CNT to value 0x0002_0002"]
impl crate :: Resettable for TIMEOUT_CNT_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } } # [doc = "MSA (rw) register accessor: I2C Master Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msa::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msa`]
module"]
pub type MSA = crate :: Reg < msa :: MSA_SPEC > ; # [doc = "I2C Master Slave Address Register"]
pub mod msa { # [doc = "Register `MSA` reader"]
pub type R = crate :: R < MSA_SPEC > ; # [doc = "Register `MSA` writer"]
pub type W = crate :: W < MSA_SPEC > ; # [doc = "Field `MSA_DIR` reader - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
pub type MSA_DIR_R = crate :: BitReader < MSA_DIR_A > ; # [doc = "Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSA_DIR_A { # [doc = "0: TRANSMIT"]
MSA_DIR_TRANSMIT = 0 , # [doc = "1: RECEIVE"]
MSA_DIR_RECEIVE = 1 , } impl From < MSA_DIR_A > for bool { # [inline (always)]
fn from (variant : MSA_DIR_A) -> Self { variant as u8 != 0 } } impl MSA_DIR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSA_DIR_A { match self . bits { false => MSA_DIR_A :: MSA_DIR_TRANSMIT , true => MSA_DIR_A :: MSA_DIR_RECEIVE , } } # [doc = "TRANSMIT"]
# [inline (always)]
pub fn is_msa_dir_transmit (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_TRANSMIT } # [doc = "RECEIVE"]
# [inline (always)]
pub fn is_msa_dir_receive (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_RECEIVE } } # [doc = "Field `MSA_DIR` writer - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
pub type MSA_DIR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_DIR_A > ; impl < 'a , REG , const O : u8 > MSA_DIR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRANSMIT"]
# [inline (always)]
pub fn msa_dir_transmit (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_TRANSMIT) } # [doc = "RECEIVE"]
# [inline (always)]
pub fn msa_dir_receive (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_RECEIVE) } } # [doc = "Field `MSA_SADDR` reader - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
pub type MSA_SADDR_R = crate :: FieldReader < u16 > ; # [doc = "Field `MSA_SADDR` writer - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
pub type MSA_SADDR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `MSA_MMODE` reader - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type MSA_MMODE_R = crate :: BitReader < MSA_MMODE_A > ; # [doc = "This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSA_MMODE_A { # [doc = "0: MODE7"]
MSA_MMODE_MODE7 = 0 , # [doc = "1: MODE10"]
MSA_MMODE_MODE10 = 1 , } impl From < MSA_MMODE_A > for bool { # [inline (always)]
fn from (variant : MSA_MMODE_A) -> Self { variant as u8 != 0 } } impl MSA_MMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSA_MMODE_A { match self . bits { false => MSA_MMODE_A :: MSA_MMODE_MODE7 , true => MSA_MMODE_A :: MSA_MMODE_MODE10 , } } # [doc = "MODE7"]
# [inline (always)]
pub fn is_msa_mmode_mode7 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE7 } # [doc = "MODE10"]
# [inline (always)]
pub fn is_msa_mmode_mode10 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE10 } } # [doc = "Field `MSA_MMODE` writer - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type MSA_MMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_MMODE_A > ; impl < 'a , REG , const O : u8 > MSA_MMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"]
# [inline (always)]
pub fn msa_mmode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE7) } # [doc = "MODE10"]
# [inline (always)]
pub fn msa_mmode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE10) } } impl R { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
# [inline (always)]
pub fn msa_dir (& self) -> MSA_DIR_R { MSA_DIR_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
pub fn msa_saddr (& self) -> MSA_SADDR_R { MSA_SADDR_R :: new (((self . bits >> 1) & 0x03ff) as u16) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
pub fn msa_mmode (& self) -> MSA_MMODE_R { MSA_MMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
# [inline (always)]
# [must_use]
pub fn msa_dir (& mut self) -> MSA_DIR_W < MSA_SPEC , 0 > { MSA_DIR_W :: new (self) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
# [must_use]
pub fn msa_saddr (& mut self) -> MSA_SADDR_W < MSA_SPEC , 1 > { MSA_SADDR_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
# [must_use]
pub fn msa_mmode (& mut self) -> MSA_MMODE_W < MSA_SPEC , 15 > { MSA_MMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msa::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MSA_SPEC ; impl crate :: RegisterSpec for MSA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`msa::R`](R) reader structure"]
impl crate :: Readable for MSA_SPEC { } # [doc = "`write(|w| ..)` method takes [`msa::W`](W) writer structure"]
impl crate :: Writable for MSA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MSA to value 0"]
impl crate :: Resettable for MSA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MCTR (rw) register accessor: I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctr`]
module"]
pub type MCTR = crate :: Reg < mctr :: MCTR_SPEC > ; # [doc = "I2C Master Control Register"]
pub mod mctr { # [doc = "Register `MCTR` reader"]
pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"]
pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"]
pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"]
MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)]
fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"]
pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"]
pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_START_A { # [doc = "0: DISABLE"]
MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)]
fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"]
pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"]
pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_STOP_A { # [doc = "0: DISABLE"]
MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)]
fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"]
pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_ACK_A { # [doc = "0: DISABLE"]
MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)]
fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"]
pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"]
MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)]
fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"]
pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"]
pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"]
MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)]
fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"]
pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"]
# [inline (always)]
pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"]
# [inline (always)]
pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"]
# [inline (always)]
pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
# [inline (always)]
pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"]
# [inline (always)]
pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"]
# [inline (always)]
pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
# [inline (always)]
pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"]
# [inline (always)]
# [must_use]
pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"]
# [inline (always)]
# [must_use]
pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"]
# [inline (always)]
# [must_use]
pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
# [inline (always)]
# [must_use]
pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"]
# [inline (always)]
# [must_use]
pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"]
# [inline (always)]
# [must_use]
pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
# [inline (always)]
# [must_use]
pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"]
impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"]
impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"]
impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MSR (r) register accessor: I2C Master Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`]
module"]
pub type MSR = crate :: Reg < msr :: MSR_SPEC > ; # [doc = "I2C Master Status Register"]
pub mod msr { # [doc = "Register `MSR` reader"]
pub type R = crate :: R < MSR_SPEC > ; # [doc = "Field `MSR_BUSY` reader - I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction."]
pub type MSR_BUSY_R = crate :: BitReader < MSR_BUSY_A > ; # [doc = "I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_BUSY_A { # [doc = "0: CLEARED"]
MSR_BUSY_CLEARED = 0 , # [doc = "1: SET"]
MSR_BUSY_SET = 1 , } impl From < MSR_BUSY_A > for bool { # [inline (always)]
fn from (variant : MSR_BUSY_A) -> Self { variant as u8 != 0 } } impl MSR_BUSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_BUSY_A { match self . bits { false => MSR_BUSY_A :: MSR_BUSY_CLEARED , true => MSR_BUSY_A :: MSR_BUSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_busy_cleared (& self) -> bool { * self == MSR_BUSY_A :: MSR_BUSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_busy_set (& self) -> bool { * self == MSR_BUSY_A :: MSR_BUSY_SET } } # [doc = "Field `MSR_ERR` reader - Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged."]
pub type MSR_ERR_R = crate :: BitReader < MSR_ERR_A > ; # [doc = "Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_ERR_A { # [doc = "0: CLEARED"]
MSR_ERR_CLEARED = 0 , # [doc = "1: SET"]
MSR_ERR_SET = 1 , } impl From < MSR_ERR_A > for bool { # [inline (always)]
fn from (variant : MSR_ERR_A) -> Self { variant as u8 != 0 } } impl MSR_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_ERR_A { match self . bits { false => MSR_ERR_A :: MSR_ERR_CLEARED , true => MSR_ERR_A :: MSR_ERR_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_err_cleared (& self) -> bool { * self == MSR_ERR_A :: MSR_ERR_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_err_set (& self) -> bool { * self == MSR_ERR_A :: MSR_ERR_SET } } # [doc = "Field `MSR_ADRACK` reader - Acknowledge Address"]
pub type MSR_ADRACK_R = crate :: BitReader < MSR_ADRACK_A > ; # [doc = "Acknowledge Address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_ADRACK_A { # [doc = "0: CLEARED"]
MSR_ADRACK_CLEARED = 0 , # [doc = "1: SET"]
MSR_ADRACK_SET = 1 , } impl From < MSR_ADRACK_A > for bool { # [inline (always)]
fn from (variant : MSR_ADRACK_A) -> Self { variant as u8 != 0 } } impl MSR_ADRACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_ADRACK_A { match self . bits { false => MSR_ADRACK_A :: MSR_ADRACK_CLEARED , true => MSR_ADRACK_A :: MSR_ADRACK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_adrack_cleared (& self) -> bool { * self == MSR_ADRACK_A :: MSR_ADRACK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_adrack_set (& self) -> bool { * self == MSR_ADRACK_A :: MSR_ADRACK_SET } } # [doc = "Field `MSR_DATACK` reader - Acknowledge Data"]
pub type MSR_DATACK_R = crate :: BitReader < MSR_DATACK_A > ; # [doc = "Acknowledge Data\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_DATACK_A { # [doc = "0: CLEARED"]
MSR_DATACK_CLEARED = 0 , # [doc = "1: SET"]
MSR_DATACK_SET = 1 , } impl From < MSR_DATACK_A > for bool { # [inline (always)]
fn from (variant : MSR_DATACK_A) -> Self { variant as u8 != 0 } } impl MSR_DATACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_DATACK_A { match self . bits { false => MSR_DATACK_A :: MSR_DATACK_CLEARED , true => MSR_DATACK_A :: MSR_DATACK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_datack_cleared (& self) -> bool { * self == MSR_DATACK_A :: MSR_DATACK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_datack_set (& self) -> bool { * self == MSR_DATACK_A :: MSR_DATACK_SET } } # [doc = "Field `MSR_ARBLST` reader - Arbitration Lost"]
pub type MSR_ARBLST_R = crate :: BitReader < MSR_ARBLST_A > ; # [doc = "Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_ARBLST_A { # [doc = "0: CLEARED"]
MSR_ARBLST_CLEARED = 0 , # [doc = "1: SET"]
MSR_ARBLST_SET = 1 , } impl From < MSR_ARBLST_A > for bool { # [inline (always)]
fn from (variant : MSR_ARBLST_A) -> Self { variant as u8 != 0 } } impl MSR_ARBLST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_ARBLST_A { match self . bits { false => MSR_ARBLST_A :: MSR_ARBLST_CLEARED , true => MSR_ARBLST_A :: MSR_ARBLST_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_arblst_cleared (& self) -> bool { * self == MSR_ARBLST_A :: MSR_ARBLST_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_arblst_set (& self) -> bool { * self == MSR_ARBLST_A :: MSR_ARBLST_SET } } # [doc = "Field `MSR_IDLE` reader - I2C Idle"]
pub type MSR_IDLE_R = crate :: BitReader < MSR_IDLE_A > ; # [doc = "I2C Idle\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_IDLE_A { # [doc = "0: CLEARED"]
MSR_IDLE_CLEARED = 0 , # [doc = "1: SET"]
MSR_IDLE_SET = 1 , } impl From < MSR_IDLE_A > for bool { # [inline (always)]
fn from (variant : MSR_IDLE_A) -> Self { variant as u8 != 0 } } impl MSR_IDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_IDLE_A { match self . bits { false => MSR_IDLE_A :: MSR_IDLE_CLEARED , true => MSR_IDLE_A :: MSR_IDLE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_idle_cleared (& self) -> bool { * self == MSR_IDLE_A :: MSR_IDLE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_idle_set (& self) -> bool { * self == MSR_IDLE_A :: MSR_IDLE_SET } } # [doc = "Field `MSR_BUSBSY` reader - I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY."]
pub type MSR_BUSBSY_R = crate :: BitReader < MSR_BUSBSY_A > ; # [doc = "I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_BUSBSY_A { # [doc = "0: CLEARED"]
MSR_BUSBSY_CLEARED = 0 , # [doc = "1: SET"]
MSR_BUSBSY_SET = 1 , } impl From < MSR_BUSBSY_A > for bool { # [inline (always)]
fn from (variant : MSR_BUSBSY_A) -> Self { variant as u8 != 0 } } impl MSR_BUSBSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_BUSBSY_A { match self . bits { false => MSR_BUSBSY_A :: MSR_BUSBSY_CLEARED , true => MSR_BUSBSY_A :: MSR_BUSBSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_busbsy_cleared (& self) -> bool { * self == MSR_BUSBSY_A :: MSR_BUSBSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_busbsy_set (& self) -> bool { * self == MSR_BUSBSY_A :: MSR_BUSBSY_SET } } # [doc = "Field `MSR_MBCNT` reader - I2C Master Transaction Count This field contains the current count-down value of the transaction."]
pub type MSR_MBCNT_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bit 0 - I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction."]
# [inline (always)]
pub fn msr_busy (& self) -> MSR_BUSY_R { MSR_BUSY_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged."]
# [inline (always)]
pub fn msr_err (& self) -> MSR_ERR_R { MSR_ERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Acknowledge Address"]
# [inline (always)]
pub fn msr_adrack (& self) -> MSR_ADRACK_R { MSR_ADRACK_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Acknowledge Data"]
# [inline (always)]
pub fn msr_datack (& self) -> MSR_DATACK_R { MSR_DATACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Arbitration Lost"]
# [inline (always)]
pub fn msr_arblst (& self) -> MSR_ARBLST_R { MSR_ARBLST_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - I2C Idle"]
# [inline (always)]
pub fn msr_idle (& self) -> MSR_IDLE_R { MSR_IDLE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY."]
# [inline (always)]
pub fn msr_busbsy (& self) -> MSR_BUSBSY_R { MSR_BUSBSY_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 16:27 - I2C Master Transaction Count This field contains the current count-down value of the transaction."]
# [inline (always)]
pub fn msr_mbcnt (& self) -> MSR_MBCNT_R { MSR_MBCNT_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } # [doc = "I2C Master Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MSR_SPEC ; impl crate :: RegisterSpec for MSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`msr::R`](R) reader structure"]
impl crate :: Readable for MSR_SPEC { } # [doc = "`reset()` method sets MSR to value 0"]
impl crate :: Resettable for MSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MRXDATA (r) register accessor: I2C Master RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mrxdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrxdata`]
module"]
pub type MRXDATA = crate :: Reg < mrxdata :: MRXDATA_SPEC > ; # [doc = "I2C Master RXData"]
pub mod mrxdata { # [doc = "Register `MRXDATA` reader"]
pub type R = crate :: R < MRXDATA_SPEC > ; # [doc = "Field `MRXDATA_VALUE` reader - Received Data. This field contains the last received data."]
pub type MRXDATA_VALUE_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Received Data. This field contains the last received data."]
# [inline (always)]
pub fn mrxdata_value (& self) -> MRXDATA_VALUE_R { MRXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } # [doc = "I2C Master RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mrxdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MRXDATA_SPEC ; impl crate :: RegisterSpec for MRXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mrxdata::R`](R) reader structure"]
impl crate :: Readable for MRXDATA_SPEC { } # [doc = "`reset()` method sets MRXDATA to value 0"]
impl crate :: Resettable for MRXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MTXDATA (rw) register accessor: I2C Master TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtxdata::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtxdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtxdata`]
module"]
pub type MTXDATA = crate :: Reg < mtxdata :: MTXDATA_SPEC > ; # [doc = "I2C Master TXData"]
pub mod mtxdata { # [doc = "Register `MTXDATA` reader"]
pub type R = crate :: R < MTXDATA_SPEC > ; # [doc = "Register `MTXDATA` writer"]
pub type W = crate :: W < MTXDATA_SPEC > ; # [doc = "Field `MTXDATA_VALUE` reader - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type MTXDATA_VALUE_R = crate :: FieldReader ; # [doc = "Field `MTXDATA_VALUE` writer - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type MTXDATA_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
pub fn mtxdata_value (& self) -> MTXDATA_VALUE_R { MTXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
# [must_use]
pub fn mtxdata_value (& mut self) -> MTXDATA_VALUE_W < MTXDATA_SPEC , 0 > { MTXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtxdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtxdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MTXDATA_SPEC ; impl crate :: RegisterSpec for MTXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mtxdata::R`](R) reader structure"]
impl crate :: Readable for MTXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`mtxdata::W`](W) writer structure"]
impl crate :: Writable for MTXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MTXDATA to value 0"]
impl crate :: Resettable for MTXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MTPR (rw) register accessor: I2C Master Timer Period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtpr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtpr`]
module"]
pub type MTPR = crate :: Reg < mtpr :: MTPR_SPEC > ; # [doc = "I2C Master Timer Period"]
pub mod mtpr { # [doc = "Register `MTPR` reader"]
pub type R = crate :: R < MTPR_SPEC > ; # [doc = "Register `MTPR` writer"]
pub type W = crate :: W < MTPR_SPEC > ; # [doc = "Field `MTPR_TPR` reader - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
pub type MTPR_TPR_R = crate :: FieldReader ; # [doc = "Field `MTPR_TPR` writer - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
pub type MTPR_TPR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
# [inline (always)]
pub fn mtpr_tpr (& self) -> MTPR_TPR_R { MTPR_TPR_R :: new ((self . bits & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
# [inline (always)]
# [must_use]
pub fn mtpr_tpr (& mut self) -> MTPR_TPR_W < MTPR_SPEC , 0 > { MTPR_TPR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Timer Period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtpr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MTPR_SPEC ; impl crate :: RegisterSpec for MTPR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mtpr::R`](R) reader structure"]
impl crate :: Readable for MTPR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mtpr::W`](W) writer structure"]
impl crate :: Writable for MTPR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MTPR to value 0x01"]
impl crate :: Resettable for MTPR_SPEC { const RESET_VALUE : Self :: Ux = 0x01 ; } } # [doc = "MCR (rw) register accessor: I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
module"]
pub type MCR = crate :: Reg < mcr :: MCR_SPEC > ; # [doc = "I2C Master Configuration"]
pub mod mcr { # [doc = "Register `MCR` reader"]
pub type R = crate :: R < MCR_SPEC > ; # [doc = "Register `MCR` writer"]
pub type W = crate :: W < MCR_SPEC > ; # [doc = "Field `MCR_ACTIVE` reader - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
pub type MCR_ACTIVE_R = crate :: BitReader < MCR_ACTIVE_A > ; # [doc = "Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_ACTIVE_A { # [doc = "0: DISABLE"]
MCR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_ACTIVE_ENABLE = 1 , } impl From < MCR_ACTIVE_A > for bool { # [inline (always)]
fn from (variant : MCR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl MCR_ACTIVE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_ACTIVE_A { match self . bits { false => MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE , true => MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_active_disable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_active_enable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE } } # [doc = "Field `MCR_ACTIVE` writer - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
pub type MCR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > MCR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE) } } # [doc = "Field `MCR_MMST` reader - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
pub type MCR_MMST_R = crate :: BitReader < MCR_MMST_A > ; # [doc = "Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_MMST_A { # [doc = "0: DISABLE"]
MCR_MMST_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_MMST_ENABLE = 1 , } impl From < MCR_MMST_A > for bool { # [inline (always)]
fn from (variant : MCR_MMST_A) -> Self { variant as u8 != 0 } } impl MCR_MMST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_MMST_A { match self . bits { false => MCR_MMST_A :: MCR_MMST_DISABLE , true => MCR_MMST_A :: MCR_MMST_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_mmst_disable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_mmst_enable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_ENABLE } } # [doc = "Field `MCR_MMST` writer - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
pub type MCR_MMST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_MMST_A > ; impl < 'a , REG , const O : u8 > MCR_MMST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_mmst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_mmst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_ENABLE) } } # [doc = "Field `MCR_CLKSTRETCH` reader - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
pub type MCR_CLKSTRETCH_R = crate :: BitReader < MCR_CLKSTRETCH_A > ; # [doc = "Clock Stretching. This bit controls the support for clock stretching of the I2C bus.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_CLKSTRETCH_A { # [doc = "0: DISABLE"]
MCR_CLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_CLKSTRETCH_ENABLE = 1 , } impl From < MCR_CLKSTRETCH_A > for bool { # [inline (always)]
fn from (variant : MCR_CLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl MCR_CLKSTRETCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_CLKSTRETCH_A { match self . bits { false => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE , true => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_clkstretch_disable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_clkstretch_enable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE } } # [doc = "Field `MCR_CLKSTRETCH` writer - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
pub type MCR_CLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_CLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > MCR_CLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_clkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_clkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE) } } # [doc = "Field `MCR_LPBK` reader - I2C Loopback"]
pub type MCR_LPBK_R = crate :: BitReader < MCR_LPBK_A > ; # [doc = "I2C Loopback\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_LPBK_A { # [doc = "0: DISABLE"]
MCR_LPBK_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_LPBK_ENABLE = 1 , } impl From < MCR_LPBK_A > for bool { # [inline (always)]
fn from (variant : MCR_LPBK_A) -> Self { variant as u8 != 0 } } impl MCR_LPBK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_LPBK_A { match self . bits { false => MCR_LPBK_A :: MCR_LPBK_DISABLE , true => MCR_LPBK_A :: MCR_LPBK_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_lpbk_disable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_lpbk_enable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_ENABLE } } # [doc = "Field `MCR_LPBK` writer - I2C Loopback"]
pub type MCR_LPBK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_LPBK_A > ; impl < 'a , REG , const O : u8 > MCR_LPBK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_lpbk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_lpbk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
# [inline (always)]
pub fn mcr_active (& self) -> MCR_ACTIVE_R { MCR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
# [inline (always)]
pub fn mcr_mmst (& self) -> MCR_MMST_R { MCR_MMST_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
# [inline (always)]
pub fn mcr_clkstretch (& self) -> MCR_CLKSTRETCH_R { MCR_CLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - I2C Loopback"]
# [inline (always)]
pub fn mcr_lpbk (& self) -> MCR_LPBK_R { MCR_LPBK_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
# [inline (always)]
# [must_use]
pub fn mcr_active (& mut self) -> MCR_ACTIVE_W < MCR_SPEC , 0 > { MCR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
# [inline (always)]
# [must_use]
pub fn mcr_mmst (& mut self) -> MCR_MMST_W < MCR_SPEC , 1 > { MCR_MMST_W :: new (self) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
# [inline (always)]
# [must_use]
pub fn mcr_clkstretch (& mut self) -> MCR_CLKSTRETCH_W < MCR_SPEC , 2 > { MCR_CLKSTRETCH_W :: new (self) } # [doc = "Bit 8 - I2C Loopback"]
# [inline (always)]
# [must_use]
pub fn mcr_lpbk (& mut self) -> MCR_LPBK_W < MCR_SPEC , 8 > { MCR_LPBK_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MCR_SPEC ; impl crate :: RegisterSpec for MCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mcr::R`](R) reader structure"]
impl crate :: Readable for MCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"]
impl crate :: Writable for MCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCR to value 0"]
impl crate :: Resettable for MCR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MBMON (r) register accessor: I2C Master Bus Monitor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mbmon::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbmon`]
module"]
pub type MBMON = crate :: Reg < mbmon :: MBMON_SPEC > ; # [doc = "I2C Master Bus Monitor"]
pub mod mbmon { # [doc = "Register `MBMON` reader"]
pub type R = crate :: R < MBMON_SPEC > ; # [doc = "Field `MBMON_SCL` reader - I2C SCL Status"]
pub type MBMON_SCL_R = crate :: BitReader < MBMON_SCL_A > ; # [doc = "I2C SCL Status\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MBMON_SCL_A { # [doc = "0: CLEARED"]
MBMON_SCL_CLEARED = 0 , # [doc = "1: SET"]
MBMON_SCL_SET = 1 , } impl From < MBMON_SCL_A > for bool { # [inline (always)]
fn from (variant : MBMON_SCL_A) -> Self { variant as u8 != 0 } } impl MBMON_SCL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MBMON_SCL_A { match self . bits { false => MBMON_SCL_A :: MBMON_SCL_CLEARED , true => MBMON_SCL_A :: MBMON_SCL_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_mbmon_scl_cleared (& self) -> bool { * self == MBMON_SCL_A :: MBMON_SCL_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_mbmon_scl_set (& self) -> bool { * self == MBMON_SCL_A :: MBMON_SCL_SET } } # [doc = "Field `MBMON_SDA` reader - I2C SDA Status"]
pub type MBMON_SDA_R = crate :: BitReader < MBMON_SDA_A > ; # [doc = "I2C SDA Status\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MBMON_SDA_A { # [doc = "0: CLEARED"]
MBMON_SDA_CLEARED = 0 , # [doc = "1: SET"]
MBMON_SDA_SET = 1 , } impl From < MBMON_SDA_A > for bool { # [inline (always)]
fn from (variant : MBMON_SDA_A) -> Self { variant as u8 != 0 } } impl MBMON_SDA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MBMON_SDA_A { match self . bits { false => MBMON_SDA_A :: MBMON_SDA_CLEARED , true => MBMON_SDA_A :: MBMON_SDA_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_mbmon_sda_cleared (& self) -> bool { * self == MBMON_SDA_A :: MBMON_SDA_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_mbmon_sda_set (& self) -> bool { * self == MBMON_SDA_A :: MBMON_SDA_SET } } impl R { # [doc = "Bit 0 - I2C SCL Status"]
# [inline (always)]
pub fn mbmon_scl (& self) -> MBMON_SCL_R { MBMON_SCL_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C SDA Status"]
# [inline (always)]
pub fn mbmon_sda (& self) -> MBMON_SDA_R { MBMON_SDA_R :: new (((self . bits >> 1) & 1) != 0) } } # [doc = "I2C Master Bus Monitor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mbmon::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MBMON_SPEC ; impl crate :: RegisterSpec for MBMON_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mbmon::R`](R) reader structure"]
impl crate :: Readable for MBMON_SPEC { } # [doc = "`reset()` method sets MBMON to value 0x03"]
impl crate :: Resettable for MBMON_SPEC { const RESET_VALUE : Self :: Ux = 0x03 ; } } # [doc = "MFIFOCTL (rw) register accessor: I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfifoctl`]
module"]
pub type MFIFOCTL = crate :: Reg < mfifoctl :: MFIFOCTL_SPEC > ; # [doc = "I2C Master FIFO Control"]
pub mod mfifoctl { # [doc = "Register `MFIFOCTL` reader"]
pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"]
pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"]
MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"]
MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"]
MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"]
MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)]
fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"]
MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"]
MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"]
MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"]
MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"]
MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)]
fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"]
MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"]
impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"]
impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"]
impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MFIFOSR (r) register accessor: I2C Master FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifosr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfifosr`]
module"]
pub type MFIFOSR = crate :: Reg < mfifosr :: MFIFOSR_SPEC > ; # [doc = "I2C Master FIFO Status Register"]
pub mod mfifosr { # [doc = "Register `MFIFOSR` reader"]
pub type R = crate :: R < MFIFOSR_SPEC > ; # [doc = "Field `MFIFOSR_RXFIFOCNT` reader - Number of Bytes which could be read from the RX FIFO"]
pub type MFIFOSR_RXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `MFIFOSR_RXFLUSH` reader - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
pub type MFIFOSR_RXFLUSH_R = crate :: BitReader < MFIFOSR_RXFLUSH_A > ; # [doc = "RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOSR_RXFLUSH_A { # [doc = "0: INACTIVE"]
MFIFOSR_RXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
MFIFOSR_RXFLUSH_ACTIVE = 1 , } impl From < MFIFOSR_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOSR_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOSR_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOSR_RXFLUSH_A { match self . bits { false => MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_INACTIVE , true => MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_mfifosr_rxflush_inactive (& self) -> bool { * self == MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_mfifosr_rxflush_active (& self) -> bool { * self == MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_ACTIVE } } # [doc = "Field `MFIFOSR_TXFIFOCNT` reader - Number of Bytes which could be put into the TX FIFO"]
pub type MFIFOSR_TXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `MFIFOSR_TXFLUSH` reader - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
pub type MFIFOSR_TXFLUSH_R = crate :: BitReader < MFIFOSR_TXFLUSH_A > ; # [doc = "TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOSR_TXFLUSH_A { # [doc = "0: INACTIVE"]
MFIFOSR_TXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
MFIFOSR_TXFLUSH_ACTIVE = 1 , } impl From < MFIFOSR_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOSR_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOSR_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOSR_TXFLUSH_A { match self . bits { false => MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_INACTIVE , true => MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_mfifosr_txflush_inactive (& self) -> bool { * self == MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_mfifosr_txflush_active (& self) -> bool { * self == MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_ACTIVE } } impl R { # [doc = "Bits 0:3 - Number of Bytes which could be read from the RX FIFO"]
# [inline (always)]
pub fn mfifosr_rxfifocnt (& self) -> MFIFOSR_RXFIFOCNT_R { MFIFOSR_RXFIFOCNT_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn mfifosr_rxflush (& self) -> MFIFOSR_RXFLUSH_R { MFIFOSR_RXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:11 - Number of Bytes which could be put into the TX FIFO"]
# [inline (always)]
pub fn mfifosr_txfifocnt (& self) -> MFIFOSR_TXFIFOCNT_R { MFIFOSR_TXFIFOCNT_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 15 - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn mfifosr_txflush (& self) -> MFIFOSR_TXFLUSH_R { MFIFOSR_TXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "I2C Master FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifosr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MFIFOSR_SPEC ; impl crate :: RegisterSpec for MFIFOSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifosr::R`](R) reader structure"]
impl crate :: Readable for MFIFOSR_SPEC { } # [doc = "`reset()` method sets MFIFOSR to value 0x0800"]
impl crate :: Resettable for MFIFOSR_SPEC { const RESET_VALUE : Self :: Ux = 0x0800 ; } } # [doc = "MASTER_I2CPECCTL (rw) register accessor: I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@master_i2cpecctl`]
module"]
pub type MASTER_I2CPECCTL = crate :: Reg < master_i2cpecctl :: MASTER_I2CPECCTL_SPEC > ; # [doc = "I2C master PEC control register"]
pub mod master_i2cpecctl { # [doc = "Register `MASTER_I2CPECCTL` reader"]
pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"]
pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"]
MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"]
MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)]
fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
# [inline (always)]
pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
# [inline (always)]
# [must_use]
pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
# [must_use]
pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"]
impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"]
impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"]
impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MASTER_PECSR (r) register accessor: I2C master PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_pecsr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@master_pecsr`]
module"]
pub type MASTER_PECSR = crate :: Reg < master_pecsr :: MASTER_PECSR_SPEC > ; # [doc = "I2C master PEC status register"]
pub mod master_pecsr { # [doc = "Register `MASTER_PECSR` reader"]
pub type R = crate :: R < MASTER_PECSR_SPEC > ; # [doc = "Field `MASTER_PECSR_PECBYTECNT` reader - PEC Byte Count This is the current PEC Byte Count of the Master State Machine."]
pub type MASTER_PECSR_PECBYTECNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_PECSR_PECSTS_CHECK` reader - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
pub type MASTER_PECSR_PECSTS_CHECK_R = crate :: BitReader < MASTER_PECSR_PECSTS_CHECK_A > ; # [doc = "This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MASTER_PECSR_PECSTS_CHECK_A { # [doc = "0: CLEARED"]
MASTER_PECSR_PECSTS_CHECK_CLEARED = 0 , # [doc = "1: SET"]
MASTER_PECSR_PECSTS_CHECK_SET = 1 , } impl From < MASTER_PECSR_PECSTS_CHECK_A > for bool { # [inline (always)]
fn from (variant : MASTER_PECSR_PECSTS_CHECK_A) -> Self { variant as u8 != 0 } } impl MASTER_PECSR_PECSTS_CHECK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MASTER_PECSR_PECSTS_CHECK_A { match self . bits { false => MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_CLEARED , true => MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_check_cleared (& self) -> bool { * self == MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_check_set (& self) -> bool { * self == MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_SET } } # [doc = "Field `MASTER_PECSR_PECSTS_ERROR` reader - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
pub type MASTER_PECSR_PECSTS_ERROR_R = crate :: BitReader < MASTER_PECSR_PECSTS_ERROR_A > ; # [doc = "This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MASTER_PECSR_PECSTS_ERROR_A { # [doc = "0: CLEARED"]
MASTER_PECSR_PECSTS_ERROR_CLEARED = 0 , # [doc = "1: SET"]
MASTER_PECSR_PECSTS_ERROR_SET = 1 , } impl From < MASTER_PECSR_PECSTS_ERROR_A > for bool { # [inline (always)]
fn from (variant : MASTER_PECSR_PECSTS_ERROR_A) -> Self { variant as u8 != 0 } } impl MASTER_PECSR_PECSTS_ERROR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MASTER_PECSR_PECSTS_ERROR_A { match self . bits { false => MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_CLEARED , true => MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_error_cleared (& self) -> bool { * self == MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_error_set (& self) -> bool { * self == MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_SET } } impl R { # [doc = "Bits 0:8 - PEC Byte Count This is the current PEC Byte Count of the Master State Machine."]
# [inline (always)]
pub fn master_pecsr_pecbytecnt (& self) -> MASTER_PECSR_PECBYTECNT_R { MASTER_PECSR_PECBYTECNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 16 - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn master_pecsr_pecsts_check (& self) -> MASTER_PECSR_PECSTS_CHECK_R { MASTER_PECSR_PECSTS_CHECK_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn master_pecsr_pecsts_error (& self) -> MASTER_PECSR_PECSTS_ERROR_R { MASTER_PECSR_PECSTS_ERROR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "I2C master PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_pecsr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MASTER_PECSR_SPEC ; impl crate :: RegisterSpec for MASTER_PECSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_pecsr::R`](R) reader structure"]
impl crate :: Readable for MASTER_PECSR_SPEC { } # [doc = "`reset()` method sets MASTER_PECSR to value 0"]
impl crate :: Resettable for MASTER_PECSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SOAR (rw) register accessor: I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soar`]
module"]
pub type SOAR = crate :: Reg < soar :: SOAR_SPEC > ; # [doc = "I2C Slave Own Address"]
pub mod soar { # [doc = "Register `SOAR` reader"]
pub type R = crate :: R < SOAR_SPEC > ; # [doc = "Register `SOAR` writer"]
pub type W = crate :: W < SOAR_SPEC > ; # [doc = "Field `SOAR_OAR` reader - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
pub type SOAR_OAR_R = crate :: FieldReader < u16 > ; # [doc = "Field `SOAR_OAR` writer - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
pub type SOAR_OAR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `SOAR_OAREN` reader - I2C Slave Own Address Enable"]
pub type SOAR_OAREN_R = crate :: BitReader < SOAR_OAREN_A > ; # [doc = "I2C Slave Own Address Enable\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SOAR_OAREN_A { # [doc = "0: DISABLE"]
SOAR_OAREN_DISABLE = 0 , # [doc = "1: ENABLE"]
SOAR_OAREN_ENABLE = 1 , } impl From < SOAR_OAREN_A > for bool { # [inline (always)]
fn from (variant : SOAR_OAREN_A) -> Self { variant as u8 != 0 } } impl SOAR_OAREN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SOAR_OAREN_A { match self . bits { false => SOAR_OAREN_A :: SOAR_OAREN_DISABLE , true => SOAR_OAREN_A :: SOAR_OAREN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_soar_oaren_disable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_soar_oaren_enable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_ENABLE } } # [doc = "Field `SOAR_OAREN` writer - I2C Slave Own Address Enable"]
pub type SOAR_OAREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_OAREN_A > ; impl < 'a , REG , const O : u8 > SOAR_OAREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn soar_oaren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn soar_oaren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_ENABLE) } } # [doc = "Field `SOAR_SMODE` reader - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type SOAR_SMODE_R = crate :: BitReader < SOAR_SMODE_A > ; # [doc = "This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SOAR_SMODE_A { # [doc = "0: MODE7"]
SOAR_SMODE_MODE7 = 0 , # [doc = "1: MODE10"]
SOAR_SMODE_MODE10 = 1 , } impl From < SOAR_SMODE_A > for bool { # [inline (always)]
fn from (variant : SOAR_SMODE_A) -> Self { variant as u8 != 0 } } impl SOAR_SMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SOAR_SMODE_A { match self . bits { false => SOAR_SMODE_A :: SOAR_SMODE_MODE7 , true => SOAR_SMODE_A :: SOAR_SMODE_MODE10 , } } # [doc = "MODE7"]
# [inline (always)]
pub fn is_soar_smode_mode7 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE7 } # [doc = "MODE10"]
# [inline (always)]
pub fn is_soar_smode_mode10 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE10 } } # [doc = "Field `SOAR_SMODE` writer - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type SOAR_SMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_SMODE_A > ; impl < 'a , REG , const O : u8 > SOAR_SMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"]
# [inline (always)]
pub fn soar_smode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE7) } # [doc = "MODE10"]
# [inline (always)]
pub fn soar_smode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE10) } } impl R { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
pub fn soar_oar (& self) -> SOAR_OAR_R { SOAR_OAR_R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bit 14 - I2C Slave Own Address Enable"]
# [inline (always)]
pub fn soar_oaren (& self) -> SOAR_OAREN_R { SOAR_OAREN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
pub fn soar_smode (& self) -> SOAR_SMODE_R { SOAR_SMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
# [must_use]
pub fn soar_oar (& mut self) -> SOAR_OAR_W < SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own Address Enable"]
# [inline (always)]
# [must_use]
pub fn soar_oaren (& mut self) -> SOAR_OAREN_W < SOAR_SPEC , 14 > { SOAR_OAREN_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
# [must_use]
pub fn soar_smode (& mut self) -> SOAR_SMODE_W < SOAR_SPEC , 15 > { SOAR_SMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOAR_SPEC ; impl crate :: RegisterSpec for SOAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar::R`](R) reader structure"]
impl crate :: Readable for SOAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar::W`](W) writer structure"]
impl crate :: Writable for SOAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR to value 0x4000"]
impl crate :: Resettable for SOAR_SPEC { const RESET_VALUE : Self :: Ux = 0x4000 ; } } # [doc = "SOAR2 (rw) register accessor: I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soar2`]
module"]
pub type SOAR2 = crate :: Reg < soar2 :: SOAR2_SPEC > ; # [doc = "I2C Slave Own Address 2"]
pub mod soar2 { # [doc = "Register `SOAR2` reader"]
pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"]
pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"]
pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"]
SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"]
SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)]
fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"]
pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
# [inline (always)]
pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"]
# [inline (always)]
pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
# [inline (always)]
pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
# [inline (always)]
# [must_use]
pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"]
# [inline (always)]
# [must_use]
pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
# [inline (always)]
# [must_use]
pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"]
impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"]
impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"]
impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SCTR (rw) register accessor: I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sctr`]
module"]
pub type SCTR = crate :: Reg < sctr :: SCTR_SPEC > ; # [doc = "I2C Slave Control Register"]
pub mod sctr { # [doc = "Register `SCTR` reader"]
pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"]
pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."]
pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"]
SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)]
fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."]
pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"]
SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)]
fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"]
pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"]
SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)]
fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"]
pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"]
pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"]
SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)]
fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"]
pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"]
pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"]
SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)]
fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"]
pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"]
SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)]
fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"]
pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"]
SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)]
fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"]
pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"]
pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"]
SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)]
fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"]
pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"]
pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"]
SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)]
fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"]
pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"]
pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"]
SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)]
fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"]
pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"]
pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"]
SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)]
fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"]
pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."]
# [inline (always)]
pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
# [inline (always)]
pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"]
# [inline (always)]
pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"]
# [inline (always)]
pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"]
# [inline (always)]
pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
# [inline (always)]
pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"]
# [inline (always)]
pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"]
# [inline (always)]
pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"]
# [inline (always)]
pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"]
# [inline (always)]
pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"]
# [inline (always)]
pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."]
# [inline (always)]
# [must_use]
pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
# [inline (always)]
# [must_use]
pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"]
# [inline (always)]
# [must_use]
pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"]
# [inline (always)]
# [must_use]
pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"]
# [inline (always)]
# [must_use]
pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
# [inline (always)]
# [must_use]
pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"]
# [inline (always)]
# [must_use]
pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"]
# [inline (always)]
# [must_use]
pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"]
# [inline (always)]
# [must_use]
pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"]
# [inline (always)]
# [must_use]
pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"]
# [inline (always)]
# [must_use]
pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"]
impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"]
impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"]
impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } } # [doc = "SSR (r) register accessor: I2C Slave Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssr`]
module"]
pub type SSR = crate :: Reg < ssr :: SSR_SPEC > ; # [doc = "I2C Slave Status Register"]
pub mod ssr { # [doc = "Register `SSR` reader"]
pub type R = crate :: R < SSR_SPEC > ; # [doc = "Field `SSR_RREQ` reader - Receive Request"]
pub type SSR_RREQ_R = crate :: BitReader < SSR_RREQ_A > ; # [doc = "Receive Request\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_RREQ_A { # [doc = "0: CLEARED"]
SSR_RREQ_CLEARED = 0 , # [doc = "1: SET"]
SSR_RREQ_SET = 1 , } impl From < SSR_RREQ_A > for bool { # [inline (always)]
fn from (variant : SSR_RREQ_A) -> Self { variant as u8 != 0 } } impl SSR_RREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_RREQ_A { match self . bits { false => SSR_RREQ_A :: SSR_RREQ_CLEARED , true => SSR_RREQ_A :: SSR_RREQ_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_rreq_cleared (& self) -> bool { * self == SSR_RREQ_A :: SSR_RREQ_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_rreq_set (& self) -> bool { * self == SSR_RREQ_A :: SSR_RREQ_SET } } # [doc = "Field `SSR_TREQ` reader - Transmit Request"]
pub type SSR_TREQ_R = crate :: BitReader < SSR_TREQ_A > ; # [doc = "Transmit Request\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_TREQ_A { # [doc = "0: CLEARED"]
SSR_TREQ_CLEARED = 0 , # [doc = "1: SET"]
SSR_TREQ_SET = 1 , } impl From < SSR_TREQ_A > for bool { # [inline (always)]
fn from (variant : SSR_TREQ_A) -> Self { variant as u8 != 0 } } impl SSR_TREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_TREQ_A { match self . bits { false => SSR_TREQ_A :: SSR_TREQ_CLEARED , true => SSR_TREQ_A :: SSR_TREQ_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_treq_cleared (& self) -> bool { * self == SSR_TREQ_A :: SSR_TREQ_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_treq_set (& self) -> bool { * self == SSR_TREQ_A :: SSR_TREQ_SET } } # [doc = "Field `SSR_RXMODE` reader - Slave FSM is in Rx MODE"]
pub type SSR_RXMODE_R = crate :: BitReader < SSR_RXMODE_A > ; # [doc = "Slave FSM is in Rx MODE\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_RXMODE_A { # [doc = "0: CLEARED"]
SSR_RXMODE_CLEARED = 0 , # [doc = "1: SET"]
SSR_RXMODE_SET = 1 , } impl From < SSR_RXMODE_A > for bool { # [inline (always)]
fn from (variant : SSR_RXMODE_A) -> Self { variant as u8 != 0 } } impl SSR_RXMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_RXMODE_A { match self . bits { false => SSR_RXMODE_A :: SSR_RXMODE_CLEARED , true => SSR_RXMODE_A :: SSR_RXMODE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_rxmode_cleared (& self) -> bool { * self == SSR_RXMODE_A :: SSR_RXMODE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_rxmode_set (& self) -> bool { * self == SSR_RXMODE_A :: SSR_RXMODE_SET } } # [doc = "Field `SSR_OAR2SEL` reader - OAR2 Address Matched This bit gets reevaluated after every address comparison."]
pub type SSR_OAR2SEL_R = crate :: BitReader < SSR_OAR2SEL_A > ; # [doc = "OAR2 Address Matched This bit gets reevaluated after every address comparison.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_OAR2SEL_A { # [doc = "0: CLEARED"]
SSR_OAR2SEL_CLEARED = 0 , # [doc = "1: SET"]
SSR_OAR2SEL_SET = 1 , } impl From < SSR_OAR2SEL_A > for bool { # [inline (always)]
fn from (variant : SSR_OAR2SEL_A) -> Self { variant as u8 != 0 } } impl SSR_OAR2SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_OAR2SEL_A { match self . bits { false => SSR_OAR2SEL_A :: SSR_OAR2SEL_CLEARED , true => SSR_OAR2SEL_A :: SSR_OAR2SEL_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_oar2sel_cleared (& self) -> bool { * self == SSR_OAR2SEL_A :: SSR_OAR2SEL_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_oar2sel_set (& self) -> bool { * self == SSR_OAR2SEL_A :: SSR_OAR2SEL_SET } } # [doc = "Field `SSR_QCMDST` reader - Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction"]
pub type SSR_QCMDST_R = crate :: BitReader < SSR_QCMDST_A > ; # [doc = "Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_QCMDST_A { # [doc = "0: CLEARED"]
SSR_QCMDST_CLEARED = 0 , # [doc = "1: SET"]
SSR_QCMDST_SET = 1 , } impl From < SSR_QCMDST_A > for bool { # [inline (always)]
fn from (variant : SSR_QCMDST_A) -> Self { variant as u8 != 0 } } impl SSR_QCMDST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_QCMDST_A { match self . bits { false => SSR_QCMDST_A :: SSR_QCMDST_CLEARED , true => SSR_QCMDST_A :: SSR_QCMDST_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_qcmdst_cleared (& self) -> bool { * self == SSR_QCMDST_A :: SSR_QCMDST_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_qcmdst_set (& self) -> bool { * self == SSR_QCMDST_A :: SSR_QCMDST_SET } } # [doc = "Field `SSR_QCMDRW` reader - Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read"]
pub type SSR_QCMDRW_R = crate :: BitReader < SSR_QCMDRW_A > ; # [doc = "Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_QCMDRW_A { # [doc = "0: CLEARED"]
SSR_QCMDRW_CLEARED = 0 , # [doc = "1: SET"]
SSR_QCMDRW_SET = 1 , } impl From < SSR_QCMDRW_A > for bool { # [inline (always)]
fn from (variant : SSR_QCMDRW_A) -> Self { variant as u8 != 0 } } impl SSR_QCMDRW_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_QCMDRW_A { match self . bits { false => SSR_QCMDRW_A :: SSR_QCMDRW_CLEARED , true => SSR_QCMDRW_A :: SSR_QCMDRW_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_qcmdrw_cleared (& self) -> bool { * self == SSR_QCMDRW_A :: SSR_QCMDRW_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_qcmdrw_set (& self) -> bool { * self == SSR_QCMDRW_A :: SSR_QCMDRW_SET } } # [doc = "Field `SSR_BUSBSY` reader - I2C bus is busy"]
pub type SSR_BUSBSY_R = crate :: BitReader < SSR_BUSBSY_A > ; # [doc = "I2C bus is busy\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_BUSBSY_A { # [doc = "0: CLEARED"]
SSR_BUSBSY_CLEARED = 0 , # [doc = "1: SET"]
SSR_BUSBSY_SET = 1 , } impl From < SSR_BUSBSY_A > for bool { # [inline (always)]
fn from (variant : SSR_BUSBSY_A) -> Self { variant as u8 != 0 } } impl SSR_BUSBSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_BUSBSY_A { match self . bits { false => SSR_BUSBSY_A :: SSR_BUSBSY_CLEARED , true => SSR_BUSBSY_A :: SSR_BUSBSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_busbsy_cleared (& self) -> bool { * self == SSR_BUSBSY_A :: SSR_BUSBSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_busbsy_set (& self) -> bool { * self == SSR_BUSBSY_A :: SSR_BUSBSY_SET } } # [doc = "Field `SSR_TXMODE` reader - Slave FSM is in TX MODE"]
pub type SSR_TXMODE_R = crate :: BitReader < SSR_TXMODE_A > ; # [doc = "Slave FSM is in TX MODE\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_TXMODE_A { # [doc = "0: CLEARED"]
SSR_TXMODE_CLEARED = 0 , # [doc = "1: SET"]
SSR_TXMODE_SET = 1 , } impl From < SSR_TXMODE_A > for bool { # [inline (always)]
fn from (variant : SSR_TXMODE_A) -> Self { variant as u8 != 0 } } impl SSR_TXMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_TXMODE_A { match self . bits { false => SSR_TXMODE_A :: SSR_TXMODE_CLEARED , true => SSR_TXMODE_A :: SSR_TXMODE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_txmode_cleared (& self) -> bool { * self == SSR_TXMODE_A :: SSR_TXMODE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_txmode_set (& self) -> bool { * self == SSR_TXMODE_A :: SSR_TXMODE_SET } } # [doc = "Field `SSR_STALE_TXFIFO` reader - Stale Tx FIFO"]
pub type SSR_STALE_TXFIFO_R = crate :: BitReader < SSR_STALE_TXFIFO_A > ; # [doc = "Stale Tx FIFO\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_STALE_TXFIFO_A { # [doc = "0: CLEARED"]
SSR_STALE_TXFIFO_CLEARED = 0 , # [doc = "1: SET"]
SSR_STALE_TXFIFO_SET = 1 , } impl From < SSR_STALE_TXFIFO_A > for bool { # [inline (always)]
fn from (variant : SSR_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SSR_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_STALE_TXFIFO_A { match self . bits { false => SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_CLEARED , true => SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_stale_txfifo_cleared (& self) -> bool { * self == SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_stale_txfifo_set (& self) -> bool { * self == SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_SET } } # [doc = "Field `SSR_ADDRMATCH` reader - Indicates the address for which slave address match happened"]
pub type SSR_ADDRMATCH_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bit 0 - Receive Request"]
# [inline (always)]
pub fn ssr_rreq (& self) -> SSR_RREQ_R { SSR_RREQ_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transmit Request"]
# [inline (always)]
pub fn ssr_treq (& self) -> SSR_TREQ_R { SSR_TREQ_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave FSM is in Rx MODE"]
# [inline (always)]
pub fn ssr_rxmode (& self) -> SSR_RXMODE_R { SSR_RXMODE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - OAR2 Address Matched This bit gets reevaluated after every address comparison."]
# [inline (always)]
pub fn ssr_oar2sel (& self) -> SSR_OAR2SEL_R { SSR_OAR2SEL_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction"]
# [inline (always)]
pub fn ssr_qcmdst (& self) -> SSR_QCMDST_R { SSR_QCMDST_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read"]
# [inline (always)]
pub fn ssr_qcmdrw (& self) -> SSR_QCMDRW_R { SSR_QCMDRW_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - I2C bus is busy"]
# [inline (always)]
pub fn ssr_busbsy (& self) -> SSR_BUSBSY_R { SSR_BUSBSY_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Slave FSM is in TX MODE"]
# [inline (always)]
pub fn ssr_txmode (& self) -> SSR_TXMODE_R { SSR_TXMODE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Stale Tx FIFO"]
# [inline (always)]
pub fn ssr_stale_txfifo (& self) -> SSR_STALE_TXFIFO_R { SSR_STALE_TXFIFO_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:18 - Indicates the address for which slave address match happened"]
# [inline (always)]
pub fn ssr_addrmatch (& self) -> SSR_ADDRMATCH_R { SSR_ADDRMATCH_R :: new (((self . bits >> 9) & 0x03ff) as u16) } } # [doc = "I2C Slave Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SSR_SPEC ; impl crate :: RegisterSpec for SSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ssr::R`](R) reader structure"]
impl crate :: Readable for SSR_SPEC { } # [doc = "`reset()` method sets SSR to value 0"]
impl crate :: Resettable for SSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SRXDATA (r) register accessor: I2C Slave RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srxdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srxdata`]
module"]
pub type SRXDATA = crate :: Reg < srxdata :: SRXDATA_SPEC > ; # [doc = "I2C Slave RXData"]
pub mod srxdata { # [doc = "Register `SRXDATA` reader"]
pub type R = crate :: R < SRXDATA_SPEC > ; # [doc = "Field `SRXDATA_VALUE` reader - Received Data. This field contains the last received data."]
pub type SRXDATA_VALUE_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Received Data. This field contains the last received data."]
# [inline (always)]
pub fn srxdata_value (& self) -> SRXDATA_VALUE_R { SRXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } # [doc = "I2C Slave RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srxdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRXDATA_SPEC ; impl crate :: RegisterSpec for SRXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`srxdata::R`](R) reader structure"]
impl crate :: Readable for SRXDATA_SPEC { } # [doc = "`reset()` method sets SRXDATA to value 0"]
impl crate :: Resettable for SRXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STXDATA (rw) register accessor: I2C Slave TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stxdata::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stxdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stxdata`]
module"]
pub type STXDATA = crate :: Reg < stxdata :: STXDATA_SPEC > ; # [doc = "I2C Slave TXData"]
pub mod stxdata { # [doc = "Register `STXDATA` reader"]
pub type R = crate :: R < STXDATA_SPEC > ; # [doc = "Register `STXDATA` writer"]
pub type W = crate :: W < STXDATA_SPEC > ; # [doc = "Field `STXDATA_VALUE` reader - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type STXDATA_VALUE_R = crate :: FieldReader ; # [doc = "Field `STXDATA_VALUE` writer - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type STXDATA_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
pub fn stxdata_value (& self) -> STXDATA_VALUE_R { STXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
# [must_use]
pub fn stxdata_value (& mut self) -> STXDATA_VALUE_W < STXDATA_SPEC , 0 > { STXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stxdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stxdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STXDATA_SPEC ; impl crate :: RegisterSpec for STXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stxdata::R`](R) reader structure"]
impl crate :: Readable for STXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`stxdata::W`](W) writer structure"]
impl crate :: Writable for STXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets STXDATA to value 0"]
impl crate :: Resettable for STXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SACKCTL (rw) register accessor: I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sackctl`]
module"]
pub type SACKCTL = crate :: Reg < sackctl :: SACKCTL_SPEC > ; # [doc = "I2C Slave ACK Control"]
pub mod sackctl { # [doc = "Register `SACKCTL` reader"]
pub type R = crate :: R < SACKCTL_SPEC > ; # [doc = "Register `SACKCTL` writer"]
pub type W = crate :: W < SACKCTL_SPEC > ; # [doc = "Field `SACKCTL_ACKOEN` reader - I2C Slave ACK Override Enable"]
pub type SACKCTL_ACKOEN_R = crate :: BitReader < SACKCTL_ACKOEN_A > ; # [doc = "I2C Slave ACK Override Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_A { match self . bits { false => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE , true => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_disable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_enable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN` writer - I2C Slave ACK Override Enable"]
pub type SACKCTL_ACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE) } } # [doc = "Field `SACKCTL_ACKOVAL` reader - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
pub type SACKCTL_ACKOVAL_R = crate :: BitReader < SACKCTL_ACKOVAL_A > ; # [doc = "I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOVAL_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOVAL_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOVAL_ENABLE = 1 , } impl From < SACKCTL_ACKOVAL_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOVAL_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOVAL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOVAL_A { match self . bits { false => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE , true => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoval_disable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoval_enable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE } } # [doc = "Field `SACKCTL_ACKOVAL` writer - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
pub type SACKCTL_ACKOVAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOVAL_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOVAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoval_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoval_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` reader - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
pub type SACKCTL_ACKOEN_ON_START_R = crate :: BitReader < SACKCTL_ACKOEN_ON_START_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_ON_START_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_ON_START_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ON_START_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_START_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_ON_START_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_START_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_START_A { match self . bits { false => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE , true => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_start_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_start_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` writer - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
pub type SACKCTL_ACKOEN_ON_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_START_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
pub type SACKCTL_ACKOEN_ON_PECNEXT_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECNEXT_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_ON_PECNEXT_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_ON_PECNEXT_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ON_PECNEXT_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECNEXT_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_ON_PECNEXT_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECNEXT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE , true => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecnext_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecnext_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
pub type SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECNEXT_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecnext_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecnext_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
pub type SACKCTL_ACKOEN_ON_PECDONE_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECDONE_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_ON_PECDONE_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_ON_PECDONE_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ON_PECDONE_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECDONE_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_ON_PECDONE_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECDONE_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE , true => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecdone_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecdone_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
pub type SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECDONE_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecdone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecdone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE) } } impl R { # [doc = "Bit 0 - I2C Slave ACK Override Enable"]
# [inline (always)]
pub fn sackctl_ackoen (& self) -> SACKCTL_ACKOEN_R { SACKCTL_ACKOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
# [inline (always)]
pub fn sackctl_ackoval (& self) -> SACKCTL_ACKOVAL_R { SACKCTL_ACKOVAL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
# [inline (always)]
pub fn sackctl_ackoen_on_start (& self) -> SACKCTL_ACKOEN_ON_START_R { SACKCTL_ACKOEN_ON_START_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
# [inline (always)]
pub fn sackctl_ackoen_on_pecnext (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_R { SACKCTL_ACKOEN_ON_PECNEXT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
# [inline (always)]
pub fn sackctl_ackoen_on_pecdone (& self) -> SACKCTL_ACKOEN_ON_PECDONE_R { SACKCTL_ACKOEN_ON_PECDONE_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - I2C Slave ACK Override Enable"]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W < SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W < SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W < SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W < SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W < SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SACKCTL_SPEC ; impl crate :: RegisterSpec for SACKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sackctl::R`](R) reader structure"]
impl crate :: Readable for SACKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sackctl::W`](W) writer structure"]
impl crate :: Writable for SACKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SACKCTL to value 0"]
impl crate :: Resettable for SACKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SFIFOCTL (rw) register accessor: I2C Slave FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifoctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfifoctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfifoctl`]
module"]
pub type SFIFOCTL = crate :: Reg < sfifoctl :: SFIFOCTL_SPEC > ; # [doc = "I2C Slave FIFO Control"]
pub mod sfifoctl { # [doc = "Register `SFIFOCTL` reader"]
pub type R = crate :: R < SFIFOCTL_SPEC > ; # [doc = "Register `SFIFOCTL` writer"]
pub type W = crate :: W < SFIFOCTL_SPEC > ; # [doc = "Field `SFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type SFIFOCTL_TXTRIG_R = crate :: FieldReader < SFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"]
SFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"]
SFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"]
SFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"]
SFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < SFIFOCTL_TXTRIG_A > for u8 { # [inline (always)]
fn from (variant : SFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for SFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl SFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_4 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_5 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_6 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_7 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `SFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type SFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , SFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `SFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type SFIFOCTL_TXFLUSH_R = crate :: BitReader < SFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"]
SFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
SFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < SFIFOCTL_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOCTL_TXFLUSH_A { match self . bits { false => SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH , true => SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_sfifoctl_txflush_noflush (& self) -> bool { * self == SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_sfifoctl_txflush_flush (& self) -> bool { * self == SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `SFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type SFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn sfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn sfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `SFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type SFIFOCTL_RXTRIG_R = crate :: FieldReader < SFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"]
SFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"]
SFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"]
SFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"]
SFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < SFIFOCTL_RXTRIG_A > for u8 { # [inline (always)]
fn from (variant : SFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for SFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl SFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_5 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_6 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_7 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_8 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `SFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type SFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , SFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `SFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type SFIFOCTL_RXFLUSH_R = crate :: BitReader < SFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"]
SFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
SFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < SFIFOCTL_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOCTL_RXFLUSH_A { match self . bits { false => SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH , true => SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_sfifoctl_rxflush_noflush (& self) -> bool { * self == SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_sfifoctl_rxflush_flush (& self) -> bool { * self == SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `SFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type SFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn sfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn sfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
pub fn sfifoctl_txtrig (& self) -> SFIFOCTL_TXTRIG_R { SFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
pub fn sfifoctl_txflush (& self) -> SFIFOCTL_TXFLUSH_R { SFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
pub fn sfifoctl_rxtrig (& self) -> SFIFOCTL_RXTRIG_R { SFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
pub fn sfifoctl_rxflush (& self) -> SFIFOCTL_RXFLUSH_R { SFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_txtrig (& mut self) -> SFIFOCTL_TXTRIG_W < SFIFOCTL_SPEC , 0 > { SFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_txflush (& mut self) -> SFIFOCTL_TXFLUSH_W < SFIFOCTL_SPEC , 7 > { SFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_rxtrig (& mut self) -> SFIFOCTL_RXTRIG_W < SFIFOCTL_SPEC , 8 > { SFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_rxflush (& mut self) -> SFIFOCTL_RXFLUSH_W < SFIFOCTL_SPEC , 15 > { SFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifoctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SFIFOCTL_SPEC ; impl crate :: RegisterSpec for SFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sfifoctl::R`](R) reader structure"]
impl crate :: Readable for SFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sfifoctl::W`](W) writer structure"]
impl crate :: Writable for SFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SFIFOCTL to value 0"]
impl crate :: Resettable for SFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SFIFOSR (r) register accessor: I2C Slave FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifosr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfifosr`]
module"]
pub type SFIFOSR = crate :: Reg < sfifosr :: SFIFOSR_SPEC > ; # [doc = "I2C Slave FIFO Status Register"]
pub mod sfifosr { # [doc = "Register `SFIFOSR` reader"]
pub type R = crate :: R < SFIFOSR_SPEC > ; # [doc = "Field `SFIFOSR_RXFIFOCNT` reader - Number of Bytes which could be read from the RX FIFO"]
pub type SFIFOSR_RXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `SFIFOSR_RXFLUSH` reader - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
pub type SFIFOSR_RXFLUSH_R = crate :: BitReader < SFIFOSR_RXFLUSH_A > ; # [doc = "RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOSR_RXFLUSH_A { # [doc = "0: INACTIVE"]
SFIFOSR_RXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
SFIFOSR_RXFLUSH_ACTIVE = 1 , } impl From < SFIFOSR_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOSR_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOSR_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOSR_RXFLUSH_A { match self . bits { false => SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_INACTIVE , true => SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_sfifosr_rxflush_inactive (& self) -> bool { * self == SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_sfifosr_rxflush_active (& self) -> bool { * self == SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_ACTIVE } } # [doc = "Field `SFIFOSR_TXFIFOCNT` reader - Number of Bytes which could be put into the TX FIFO"]
pub type SFIFOSR_TXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `SFIFOSR_TXFLUSH` reader - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
pub type SFIFOSR_TXFLUSH_R = crate :: BitReader < SFIFOSR_TXFLUSH_A > ; # [doc = "TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOSR_TXFLUSH_A { # [doc = "0: INACTIVE"]
SFIFOSR_TXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
SFIFOSR_TXFLUSH_ACTIVE = 1 , } impl From < SFIFOSR_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOSR_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOSR_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOSR_TXFLUSH_A { match self . bits { false => SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_INACTIVE , true => SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_sfifosr_txflush_inactive (& self) -> bool { * self == SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_sfifosr_txflush_active (& self) -> bool { * self == SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_ACTIVE } } impl R { # [doc = "Bits 0:3 - Number of Bytes which could be read from the RX FIFO"]
# [inline (always)]
pub fn sfifosr_rxfifocnt (& self) -> SFIFOSR_RXFIFOCNT_R { SFIFOSR_RXFIFOCNT_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn sfifosr_rxflush (& self) -> SFIFOSR_RXFLUSH_R { SFIFOSR_RXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:11 - Number of Bytes which could be put into the TX FIFO"]
# [inline (always)]
pub fn sfifosr_txfifocnt (& self) -> SFIFOSR_TXFIFOCNT_R { SFIFOSR_TXFIFOCNT_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 15 - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn sfifosr_txflush (& self) -> SFIFOSR_TXFLUSH_R { SFIFOSR_TXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "I2C Slave FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifosr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SFIFOSR_SPEC ; impl crate :: RegisterSpec for SFIFOSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sfifosr::R`](R) reader structure"]
impl crate :: Readable for SFIFOSR_SPEC { } # [doc = "`reset()` method sets SFIFOSR to value 0x0800"]
impl crate :: Resettable for SFIFOSR_SPEC { const RESET_VALUE : Self :: Ux = 0x0800 ; } } # [doc = "SLAVE_PECCTL (rw) register accessor: I2C Slave PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave_pecctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slave_pecctl`]
module"]
pub type SLAVE_PECCTL = crate :: Reg < slave_pecctl :: SLAVE_PECCTL_SPEC > ; # [doc = "I2C Slave PEC control register"]
pub mod slave_pecctl { # [doc = "Register `SLAVE_PECCTL` reader"]
pub type R = crate :: R < SLAVE_PECCTL_SPEC > ; # [doc = "Register `SLAVE_PECCTL` writer"]
pub type W = crate :: W < SLAVE_PECCTL_SPEC > ; # [doc = "Field `SLAVE_PECCTL_PECCNT` reader - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
pub type SLAVE_PECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `SLAVE_PECCTL_PECCNT` writer - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
pub type SLAVE_PECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `SLAVE_PECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type SLAVE_PECCTL_PECEN_R = crate :: BitReader < SLAVE_PECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SLAVE_PECCTL_PECEN_A { # [doc = "0: DISABLE"]
SLAVE_PECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SLAVE_PECCTL_PECEN_ENABLE = 1 , } impl From < SLAVE_PECCTL_PECEN_A > for bool { # [inline (always)]
fn from (variant : SLAVE_PECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl SLAVE_PECCTL_PECEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SLAVE_PECCTL_PECEN_A { match self . bits { false => SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_DISABLE , true => SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_slave_pecctl_pecen_disable (& self) -> bool { * self == SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_slave_pecctl_pecen_enable (& self) -> bool { * self == SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_ENABLE } } # [doc = "Field `SLAVE_PECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type SLAVE_PECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SLAVE_PECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > SLAVE_PECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn slave_pecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn slave_pecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
# [inline (always)]
pub fn slave_pecctl_peccnt (& self) -> SLAVE_PECCTL_PECCNT_R { SLAVE_PECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
pub fn slave_pecctl_pecen (& self) -> SLAVE_PECCTL_PECEN_R { SLAVE_PECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
# [inline (always)]
# [must_use]
pub fn slave_pecctl_peccnt (& mut self) -> SLAVE_PECCTL_PECCNT_W < SLAVE_PECCTL_SPEC , 0 > { SLAVE_PECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
# [must_use]
pub fn slave_pecctl_pecen (& mut self) -> SLAVE_PECCTL_PECEN_W < SLAVE_PECCTL_SPEC , 12 > { SLAVE_PECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave_pecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SLAVE_PECCTL_SPEC ; impl crate :: RegisterSpec for SLAVE_PECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`slave_pecctl::R`](R) reader structure"]
impl crate :: Readable for SLAVE_PECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`slave_pecctl::W`](W) writer structure"]
impl crate :: Writable for SLAVE_PECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SLAVE_PECCTL to value 0"]
impl crate :: Resettable for SLAVE_PECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SLAVE_PECSR (r) register accessor: I2C slave PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecsr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slave_pecsr`]
module"]
pub type SLAVE_PECSR = crate :: Reg < slave_pecsr :: SLAVE_PECSR_SPEC > ; # [doc = "I2C slave PEC status register"]
pub mod slave_pecsr { # [doc = "Register `SLAVE_PECSR` reader"]
pub type R = crate :: R < SLAVE_PECSR_SPEC > ; # [doc = "Field `SLAVE_PECSR_PECBYTECNT` reader - This is the current PEC Byte Count of the Slave State Machine."]
pub type SLAVE_PECSR_PECBYTECNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `SLAVE_PECSR_PECSTS_CHECK` reader - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
pub type SLAVE_PECSR_PECSTS_CHECK_R = crate :: BitReader < SLAVE_PECSR_PECSTS_CHECK_A > ; # [doc = "This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SLAVE_PECSR_PECSTS_CHECK_A { # [doc = "0: CLEARED"]
SLAVE_PECSR_PECSTS_CHECK_CLEARED = 0 , # [doc = "1: SET"]
SLAVE_PECSR_PECSTS_CHECK_SET = 1 , } impl From < SLAVE_PECSR_PECSTS_CHECK_A > for bool { # [inline (always)]
fn from (variant : SLAVE_PECSR_PECSTS_CHECK_A) -> Self { variant as u8 != 0 } } impl SLAVE_PECSR_PECSTS_CHECK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SLAVE_PECSR_PECSTS_CHECK_A { match self . bits { false => SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_CLEARED , true => SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_check_cleared (& self) -> bool { * self == SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_check_set (& self) -> bool { * self == SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_SET } } # [doc = "Field `SLAVE_PECSR_PECSTS_ERROR` reader - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
pub type SLAVE_PECSR_PECSTS_ERROR_R = crate :: BitReader < SLAVE_PECSR_PECSTS_ERROR_A > ; # [doc = "This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SLAVE_PECSR_PECSTS_ERROR_A { # [doc = "0: CLEARED"]
SLAVE_PECSR_PECSTS_ERROR_CLEARED = 0 , # [doc = "1: SET"]
SLAVE_PECSR_PECSTS_ERROR_SET = 1 , } impl From < SLAVE_PECSR_PECSTS_ERROR_A > for bool { # [inline (always)]
fn from (variant : SLAVE_PECSR_PECSTS_ERROR_A) -> Self { variant as u8 != 0 } } impl SLAVE_PECSR_PECSTS_ERROR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SLAVE_PECSR_PECSTS_ERROR_A { match self . bits { false => SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_CLEARED , true => SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_error_cleared (& self) -> bool { * self == SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_error_set (& self) -> bool { * self == SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_SET } } impl R { # [doc = "Bits 0:8 - This is the current PEC Byte Count of the Slave State Machine."]
# [inline (always)]
pub fn slave_pecsr_pecbytecnt (& self) -> SLAVE_PECSR_PECBYTECNT_R { SLAVE_PECSR_PECBYTECNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 16 - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn slave_pecsr_pecsts_check (& self) -> SLAVE_PECSR_PECSTS_CHECK_R { SLAVE_PECSR_PECSTS_CHECK_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn slave_pecsr_pecsts_error (& self) -> SLAVE_PECSR_PECSTS_ERROR_R { SLAVE_PECSR_PECSTS_ERROR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "I2C slave PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecsr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SLAVE_PECSR_SPEC ; impl crate :: RegisterSpec for SLAVE_PECSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`slave_pecsr::R`](R) reader structure"]
impl crate :: Readable for SLAVE_PECSR_SPEC { } # [doc = "`reset()` method sets SLAVE_PECSR to value 0"]
impl crate :: Resettable for SLAVE_PECSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "CPUSSMMR"]
pub struct CPUSS { _marker : PhantomData < * const () > } unsafe impl Send for CPUSS { } impl CPUSS { # [doc = r"Pointer to the register block"]
pub const PTR : * const cpuss :: RegisterBlock = 0x4040_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const cpuss :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for CPUSS { type Target = cpuss :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for CPUSS { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("CPUSS") . finish () } } # [doc = "CPUSSMMR"]
pub mod cpuss { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x10e0]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved1 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - Interrupt index"]
pub int_group0_iidx : INT_GROUP0_IIDX , _reserved3 : [u8 ; 0x04]
, # [doc = "0x1108 - Interrupt mask"]
pub int_group0_imask : INT_GROUP0_IMASK , _reserved4 : [u8 ; 0x04]
, # [doc = "0x1110 - Raw interrupt status"]
pub int_group0_ris : INT_GROUP0_RIS , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1118 - Masked interrupt status"]
pub int_group0_mis : INT_GROUP0_MIS , _reserved6 : [u8 ; 0x04]
, # [doc = "0x1120 - Interrupt set"]
pub int_group0_iset : INT_GROUP0_ISET , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1128 - Interrupt clear"]
pub int_group0_iclr : INT_GROUP0_ICLR , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1130 - Interrupt index"]
pub int_group1_iidx : INT_GROUP1_IIDX , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1138 - Interrupt mask"]
pub int_group1_imask : INT_GROUP1_IMASK , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1140 - Raw interrupt status"]
pub int_group1_ris : INT_GROUP1_RIS , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1148 - Masked interrupt status"]
pub int_group1_mis : INT_GROUP1_MIS , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1150 - Interrupt set"]
pub int_group1_iset : INT_GROUP1_ISET , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1158 - Interrupt clear"]
pub int_group1_iclr : INT_GROUP1_ICLR , _reserved14 : [u8 ; 0x01a4]
, # [doc = "0x1300 - Prefetch/Cache control"]
pub ctl : CTL , } # [doc = "EVT_MODE (r) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT_CFG` reader - Event line mode select"]
pub type EVT_MODE_INT_CFG_R = crate :: FieldReader < EVT_MODE_INT_CFG_A > ; # [doc = "Event line mode select\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT_CFG_A :: EVT_MODE_INT_CFG_DISABLE) , 1 => Some (EVT_MODE_INT_CFG_A :: EVT_MODE_INT_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT_CFG_A :: EVT_MODE_INT_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int_cfg_disable (& self) -> bool { * self == EVT_MODE_INT_CFG_A :: EVT_MODE_INT_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int_cfg_software (& self) -> bool { * self == EVT_MODE_INT_CFG_A :: EVT_MODE_INT_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT_CFG_A :: EVT_MODE_INT_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select"]
# [inline (always)]
pub fn evt_mode_int_cfg (& self) -> EVT_MODE_INT_CFG_R { EVT_MODE_INT_CFG_R :: new ((self . bits & 3) as u8) } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP0_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group0_iidx`]
module"]
pub type INT_GROUP0_IIDX = crate :: Reg < int_group0_iidx :: INT_GROUP0_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_group0_iidx { # [doc = "Register `INT_GROUP0_IIDX` reader"]
pub type R = crate :: R < INT_GROUP0_IIDX_SPEC > ; # [doc = "Field `INT_GROUP0_IIDX_STAT` reader - Interrupt index status"]
pub type INT_GROUP0_IIDX_STAT_R = crate :: FieldReader < INT_GROUP0_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_GROUP0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_GROUP0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: INT0"]
INT_GROUP0_IIDX_STAT_INT0 = 1 , # [doc = "2: INT1"]
INT_GROUP0_IIDX_STAT_INT1 = 2 , # [doc = "3: INT2"]
INT_GROUP0_IIDX_STAT_INT2 = 3 , # [doc = "4: INT3"]
INT_GROUP0_IIDX_STAT_INT3 = 4 , # [doc = "5: INT4"]
INT_GROUP0_IIDX_STAT_INT4 = 5 , # [doc = "6: INT5"]
INT_GROUP0_IIDX_STAT_INT5 = 6 , # [doc = "7: INT6"]
INT_GROUP0_IIDX_STAT_INT6 = 7 , # [doc = "8: INT7"]
INT_GROUP0_IIDX_STAT_INT7 = 8 , } impl From < INT_GROUP0_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_GROUP0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_GROUP0_IIDX_STAT_A { type Ux = u8 ; } impl INT_GROUP0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_GROUP0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_NO_INTR) , 1 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT0) , 2 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT1) , 3 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT2) , 4 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT3) , 5 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT4) , 6 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT5) , 7 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT6) , 8 => Some (INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT7) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_no_intr (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_NO_INTR } # [doc = "INT0"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int0 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT0 } # [doc = "INT1"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int1 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT1 } # [doc = "INT2"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int2 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT2 } # [doc = "INT3"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int3 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT3 } # [doc = "INT4"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int4 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT4 } # [doc = "INT5"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int5 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT5 } # [doc = "INT6"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int6 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT6 } # [doc = "INT7"]
# [inline (always)]
pub fn is_int_group0_iidx_stat_int7 (& self) -> bool { * self == INT_GROUP0_IIDX_STAT_A :: INT_GROUP0_IIDX_STAT_INT7 } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_group0_iidx_stat (& self) -> INT_GROUP0_IIDX_STAT_R { INT_GROUP0_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_GROUP0_IIDX to value 0"]
impl crate :: Resettable for INT_GROUP0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP0_IMASK (r) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_imask::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group0_imask`]
module"]
pub type INT_GROUP0_IMASK = crate :: Reg < int_group0_imask :: INT_GROUP0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_group0_imask { # [doc = "Register `INT_GROUP0_IMASK` reader"]
pub type R = crate :: R < INT_GROUP0_IMASK_SPEC > ; # [doc = "Field `INT_GROUP0_IMASK_INT` reader - Masks the corresponding interrupt"]
pub type INT_GROUP0_IMASK_INT_R = crate :: FieldReader < INT_GROUP0_IMASK_INT_A > ; # [doc = "Masks the corresponding interrupt\n\nValue on reset: 255"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_GROUP0_IMASK_INT_A { # [doc = "0: CLR"]
INT_GROUP0_IMASK_INT_CLR = 0 , # [doc = "1: SET"]
INT_GROUP0_IMASK_INT_SET = 1 , } impl From < INT_GROUP0_IMASK_INT_A > for u8 { # [inline (always)]
fn from (variant : INT_GROUP0_IMASK_INT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_GROUP0_IMASK_INT_A { type Ux = u8 ; } impl INT_GROUP0_IMASK_INT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_GROUP0_IMASK_INT_A > { match self . bits { 0 => Some (INT_GROUP0_IMASK_INT_A :: INT_GROUP0_IMASK_INT_CLR) , 1 => Some (INT_GROUP0_IMASK_INT_A :: INT_GROUP0_IMASK_INT_SET) , _ => None , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_group0_imask_int_clr (& self) -> bool { * self == INT_GROUP0_IMASK_INT_A :: INT_GROUP0_IMASK_INT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_group0_imask_int_set (& self) -> bool { * self == INT_GROUP0_IMASK_INT_A :: INT_GROUP0_IMASK_INT_SET } } impl R { # [doc = "Bits 0:7 - Masks the corresponding interrupt"]
# [inline (always)]
pub fn int_group0_imask_int (& self) -> INT_GROUP0_IMASK_INT_R { INT_GROUP0_IMASK_INT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_imask::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP0_IMASK_SPEC { } # [doc = "`reset()` method sets INT_GROUP0_IMASK to value 0xff"]
impl crate :: Resettable for INT_GROUP0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0xff ; } } # [doc = "INT_GROUP0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group0_ris`]
module"]
pub type INT_GROUP0_RIS = crate :: Reg < int_group0_ris :: INT_GROUP0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_group0_ris { # [doc = "Register `INT_GROUP0_RIS` reader"]
pub type R = crate :: R < INT_GROUP0_RIS_SPEC > ; # [doc = "Field `INT_GROUP0_RIS_INT` reader - Raw interrupt status for INT"]
pub type INT_GROUP0_RIS_INT_R = crate :: FieldReader < INT_GROUP0_RIS_INT_A > ; # [doc = "Raw interrupt status for INT\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_GROUP0_RIS_INT_A { # [doc = "0: CLR"]
INT_GROUP0_RIS_INT_CLR = 0 , # [doc = "1: SET"]
INT_GROUP0_RIS_INT_SET = 1 , } impl From < INT_GROUP0_RIS_INT_A > for u8 { # [inline (always)]
fn from (variant : INT_GROUP0_RIS_INT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_GROUP0_RIS_INT_A { type Ux = u8 ; } impl INT_GROUP0_RIS_INT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_GROUP0_RIS_INT_A > { match self . bits { 0 => Some (INT_GROUP0_RIS_INT_A :: INT_GROUP0_RIS_INT_CLR) , 1 => Some (INT_GROUP0_RIS_INT_A :: INT_GROUP0_RIS_INT_SET) , _ => None , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_group0_ris_int_clr (& self) -> bool { * self == INT_GROUP0_RIS_INT_A :: INT_GROUP0_RIS_INT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_group0_ris_int_set (& self) -> bool { * self == INT_GROUP0_RIS_INT_A :: INT_GROUP0_RIS_INT_SET } } impl R { # [doc = "Bits 0:7 - Raw interrupt status for INT"]
# [inline (always)]
pub fn int_group0_ris_int (& self) -> INT_GROUP0_RIS_INT_R { INT_GROUP0_RIS_INT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP0_RIS_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP0_RIS_SPEC { } # [doc = "`reset()` method sets INT_GROUP0_RIS to value 0"]
impl crate :: Resettable for INT_GROUP0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group0_mis`]
module"]
pub type INT_GROUP0_MIS = crate :: Reg < int_group0_mis :: INT_GROUP0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_group0_mis { # [doc = "Register `INT_GROUP0_MIS` reader"]
pub type R = crate :: R < INT_GROUP0_MIS_SPEC > ; # [doc = "Field `INT_GROUP0_MIS_INT` reader - Masked interrupt status for INT0"]
pub type INT_GROUP0_MIS_INT_R = crate :: BitReader < INT_GROUP0_MIS_INT_A > ; # [doc = "Masked interrupt status for INT0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_GROUP0_MIS_INT_A { # [doc = "0: CLR"]
INT_GROUP0_MIS_INT_CLR = 0 , # [doc = "1: SET"]
INT_GROUP0_MIS_INT_SET = 1 , } impl From < INT_GROUP0_MIS_INT_A > for bool { # [inline (always)]
fn from (variant : INT_GROUP0_MIS_INT_A) -> Self { variant as u8 != 0 } } impl INT_GROUP0_MIS_INT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_GROUP0_MIS_INT_A { match self . bits { false => INT_GROUP0_MIS_INT_A :: INT_GROUP0_MIS_INT_CLR , true => INT_GROUP0_MIS_INT_A :: INT_GROUP0_MIS_INT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_group0_mis_int_clr (& self) -> bool { * self == INT_GROUP0_MIS_INT_A :: INT_GROUP0_MIS_INT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_group0_mis_int_set (& self) -> bool { * self == INT_GROUP0_MIS_INT_A :: INT_GROUP0_MIS_INT_SET } } impl R { # [doc = "Bit 0 - Masked interrupt status for INT0"]
# [inline (always)]
pub fn int_group0_mis_int (& self) -> INT_GROUP0_MIS_INT_R { INT_GROUP0_MIS_INT_R :: new ((self . bits & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP0_MIS_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP0_MIS_SPEC { } # [doc = "`reset()` method sets INT_GROUP0_MIS to value 0"]
impl crate :: Resettable for INT_GROUP0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group0_iset`]
module"]
pub type INT_GROUP0_ISET = crate :: Reg < int_group0_iset :: INT_GROUP0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_group0_iset { # [doc = "Register `INT_GROUP0_ISET` writer"]
pub type W = crate :: W < INT_GROUP0_ISET_SPEC > ; # [doc = "Sets INT in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_GROUP0_ISET_INT_AW { # [doc = "0: NO_EFFECT"]
INT_GROUP0_ISET_INT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_GROUP0_ISET_INT_SET = 1 , } impl From < INT_GROUP0_ISET_INT_AW > for bool { # [inline (always)]
fn from (variant : INT_GROUP0_ISET_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP0_ISET_INT` writer - Sets INT in RIS register"]
pub type INT_GROUP0_ISET_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP0_ISET_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP0_ISET_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_group0_iset_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ISET_INT_AW :: INT_GROUP0_ISET_INT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_group0_iset_int_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ISET_INT_AW :: INT_GROUP0_ISET_INT_SET) } } impl W { # [doc = "Bit 0 - Sets INT in RIS register"]
# [inline (always)]
# [must_use]
pub fn int_group0_iset_int (& mut self) -> INT_GROUP0_ISET_INT_W < INT_GROUP0_ISET_SPEC , 0 > { INT_GROUP0_ISET_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP0_ISET_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_GROUP0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP0_ISET to value 0"]
impl crate :: Resettable for INT_GROUP0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group0_iclr`]
module"]
pub type INT_GROUP0_ICLR = crate :: Reg < int_group0_iclr :: INT_GROUP0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_group0_iclr { # [doc = "Register `INT_GROUP0_ICLR` writer"]
pub type W = crate :: W < INT_GROUP0_ICLR_SPEC > ; # [doc = "Clears INT in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_GROUP0_ICLR_INT_AW { # [doc = "0: NO_EFFECT"]
INT_GROUP0_ICLR_INT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_GROUP0_ICLR_INT_CLR = 1 , } impl From < INT_GROUP0_ICLR_INT_AW > for bool { # [inline (always)]
fn from (variant : INT_GROUP0_ICLR_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP0_ICLR_INT` writer - Clears INT in RIS register"]
pub type INT_GROUP0_ICLR_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP0_ICLR_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP0_ICLR_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_group0_iclr_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ICLR_INT_AW :: INT_GROUP0_ICLR_INT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_group0_iclr_int_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP0_ICLR_INT_AW :: INT_GROUP0_ICLR_INT_CLR) } } impl W { # [doc = "Bit 0 - Clears INT in RIS register"]
# [inline (always)]
# [must_use]
pub fn int_group0_iclr_int (& mut self) -> INT_GROUP0_ICLR_INT_W < INT_GROUP0_ICLR_SPEC , 0 > { INT_GROUP0_ICLR_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_GROUP0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_GROUP0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP0_ICLR to value 0"]
impl crate :: Resettable for INT_GROUP0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP1_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group1_iidx`]
module"]
pub type INT_GROUP1_IIDX = crate :: Reg < int_group1_iidx :: INT_GROUP1_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_group1_iidx { # [doc = "Register `INT_GROUP1_IIDX` reader"]
pub type R = crate :: R < INT_GROUP1_IIDX_SPEC > ; # [doc = "Field `INT_GROUP1_IIDX_STAT` reader - Interrupt index status"]
pub type INT_GROUP1_IIDX_STAT_R = crate :: FieldReader < INT_GROUP1_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_GROUP1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_GROUP1_IIDX_STAT_NO_INTR = 0 , # [doc = "1: INT0"]
INT_GROUP1_IIDX_STAT_INT0 = 1 , # [doc = "2: INT1"]
INT_GROUP1_IIDX_STAT_INT1 = 2 , # [doc = "3: INT2"]
INT_GROUP1_IIDX_STAT_INT2 = 3 , # [doc = "4: INT3"]
INT_GROUP1_IIDX_STAT_INT3 = 4 , # [doc = "5: INT4"]
INT_GROUP1_IIDX_STAT_INT4 = 5 , # [doc = "6: INT5"]
INT_GROUP1_IIDX_STAT_INT5 = 6 , # [doc = "7: INT6"]
INT_GROUP1_IIDX_STAT_INT6 = 7 , # [doc = "8: INT7"]
INT_GROUP1_IIDX_STAT_INT7 = 8 , } impl From < INT_GROUP1_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_GROUP1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_GROUP1_IIDX_STAT_A { type Ux = u8 ; } impl INT_GROUP1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_GROUP1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_NO_INTR) , 1 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT0) , 2 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT1) , 3 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT2) , 4 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT3) , 5 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT4) , 6 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT5) , 7 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT6) , 8 => Some (INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT7) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_no_intr (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_NO_INTR } # [doc = "INT0"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int0 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT0 } # [doc = "INT1"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int1 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT1 } # [doc = "INT2"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int2 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT2 } # [doc = "INT3"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int3 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT3 } # [doc = "INT4"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int4 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT4 } # [doc = "INT5"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int5 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT5 } # [doc = "INT6"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int6 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT6 } # [doc = "INT7"]
# [inline (always)]
pub fn is_int_group1_iidx_stat_int7 (& self) -> bool { * self == INT_GROUP1_IIDX_STAT_A :: INT_GROUP1_IIDX_STAT_INT7 } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_group1_iidx_stat (& self) -> INT_GROUP1_IIDX_STAT_R { INT_GROUP1_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_GROUP1_IIDX to value 0"]
impl crate :: Resettable for INT_GROUP1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP1_IMASK (r) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_imask::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group1_imask`]
module"]
pub type INT_GROUP1_IMASK = crate :: Reg < int_group1_imask :: INT_GROUP1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_group1_imask { # [doc = "Register `INT_GROUP1_IMASK` reader"]
pub type R = crate :: R < INT_GROUP1_IMASK_SPEC > ; # [doc = "Field `INT_GROUP1_IMASK_INT` reader - Masks the corresponding interrupt"]
pub type INT_GROUP1_IMASK_INT_R = crate :: FieldReader < INT_GROUP1_IMASK_INT_A > ; # [doc = "Masks the corresponding interrupt\n\nValue on reset: 255"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_GROUP1_IMASK_INT_A { # [doc = "0: CLR"]
INT_GROUP1_IMASK_INT_CLR = 0 , # [doc = "1: SET"]
INT_GROUP1_IMASK_INT_SET = 1 , } impl From < INT_GROUP1_IMASK_INT_A > for u8 { # [inline (always)]
fn from (variant : INT_GROUP1_IMASK_INT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_GROUP1_IMASK_INT_A { type Ux = u8 ; } impl INT_GROUP1_IMASK_INT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_GROUP1_IMASK_INT_A > { match self . bits { 0 => Some (INT_GROUP1_IMASK_INT_A :: INT_GROUP1_IMASK_INT_CLR) , 1 => Some (INT_GROUP1_IMASK_INT_A :: INT_GROUP1_IMASK_INT_SET) , _ => None , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_group1_imask_int_clr (& self) -> bool { * self == INT_GROUP1_IMASK_INT_A :: INT_GROUP1_IMASK_INT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_group1_imask_int_set (& self) -> bool { * self == INT_GROUP1_IMASK_INT_A :: INT_GROUP1_IMASK_INT_SET } } impl R { # [doc = "Bits 0:7 - Masks the corresponding interrupt"]
# [inline (always)]
pub fn int_group1_imask_int (& self) -> INT_GROUP1_IMASK_INT_R { INT_GROUP1_IMASK_INT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_imask::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP1_IMASK_SPEC { } # [doc = "`reset()` method sets INT_GROUP1_IMASK to value 0xff"]
impl crate :: Resettable for INT_GROUP1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0xff ; } } # [doc = "INT_GROUP1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group1_ris`]
module"]
pub type INT_GROUP1_RIS = crate :: Reg < int_group1_ris :: INT_GROUP1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_group1_ris { # [doc = "Register `INT_GROUP1_RIS` reader"]
pub type R = crate :: R < INT_GROUP1_RIS_SPEC > ; # [doc = "Field `INT_GROUP1_RIS_INT` reader - Raw interrupt status for INT"]
pub type INT_GROUP1_RIS_INT_R = crate :: BitReader < INT_GROUP1_RIS_INT_A > ; # [doc = "Raw interrupt status for INT\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_GROUP1_RIS_INT_A { # [doc = "0: CLR"]
INT_GROUP1_RIS_INT_CLR = 0 , # [doc = "1: SET"]
INT_GROUP1_RIS_INT_SET = 1 , } impl From < INT_GROUP1_RIS_INT_A > for bool { # [inline (always)]
fn from (variant : INT_GROUP1_RIS_INT_A) -> Self { variant as u8 != 0 } } impl INT_GROUP1_RIS_INT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_GROUP1_RIS_INT_A { match self . bits { false => INT_GROUP1_RIS_INT_A :: INT_GROUP1_RIS_INT_CLR , true => INT_GROUP1_RIS_INT_A :: INT_GROUP1_RIS_INT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_group1_ris_int_clr (& self) -> bool { * self == INT_GROUP1_RIS_INT_A :: INT_GROUP1_RIS_INT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_group1_ris_int_set (& self) -> bool { * self == INT_GROUP1_RIS_INT_A :: INT_GROUP1_RIS_INT_SET } } impl R { # [doc = "Bit 0 - Raw interrupt status for INT"]
# [inline (always)]
pub fn int_group1_ris_int (& self) -> INT_GROUP1_RIS_INT_R { INT_GROUP1_RIS_INT_R :: new ((self . bits & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP1_RIS_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP1_RIS_SPEC { } # [doc = "`reset()` method sets INT_GROUP1_RIS to value 0"]
impl crate :: Resettable for INT_GROUP1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group1_mis`]
module"]
pub type INT_GROUP1_MIS = crate :: Reg < int_group1_mis :: INT_GROUP1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_group1_mis { # [doc = "Register `INT_GROUP1_MIS` reader"]
pub type R = crate :: R < INT_GROUP1_MIS_SPEC > ; # [doc = "Field `INT_GROUP1_MIS_INT` reader - Masked interrupt status for INT0"]
pub type INT_GROUP1_MIS_INT_R = crate :: BitReader < INT_GROUP1_MIS_INT_A > ; # [doc = "Masked interrupt status for INT0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_GROUP1_MIS_INT_A { # [doc = "0: CLR"]
INT_GROUP1_MIS_INT_CLR = 0 , # [doc = "1: SET"]
INT_GROUP1_MIS_INT_SET = 1 , } impl From < INT_GROUP1_MIS_INT_A > for bool { # [inline (always)]
fn from (variant : INT_GROUP1_MIS_INT_A) -> Self { variant as u8 != 0 } } impl INT_GROUP1_MIS_INT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_GROUP1_MIS_INT_A { match self . bits { false => INT_GROUP1_MIS_INT_A :: INT_GROUP1_MIS_INT_CLR , true => INT_GROUP1_MIS_INT_A :: INT_GROUP1_MIS_INT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_group1_mis_int_clr (& self) -> bool { * self == INT_GROUP1_MIS_INT_A :: INT_GROUP1_MIS_INT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_group1_mis_int_set (& self) -> bool { * self == INT_GROUP1_MIS_INT_A :: INT_GROUP1_MIS_INT_SET } } impl R { # [doc = "Bit 0 - Masked interrupt status for INT0"]
# [inline (always)]
pub fn int_group1_mis_int (& self) -> INT_GROUP1_MIS_INT_R { INT_GROUP1_MIS_INT_R :: new ((self . bits & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_group1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP1_MIS_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_group1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_GROUP1_MIS_SPEC { } # [doc = "`reset()` method sets INT_GROUP1_MIS to value 0"]
impl crate :: Resettable for INT_GROUP1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group1_iset`]
module"]
pub type INT_GROUP1_ISET = crate :: Reg < int_group1_iset :: INT_GROUP1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_group1_iset { # [doc = "Register `INT_GROUP1_ISET` writer"]
pub type W = crate :: W < INT_GROUP1_ISET_SPEC > ; # [doc = "Sets INT in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_GROUP1_ISET_INT_AW { # [doc = "0: NO_EFFECT"]
INT_GROUP1_ISET_INT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_GROUP1_ISET_INT_SET = 1 , } impl From < INT_GROUP1_ISET_INT_AW > for bool { # [inline (always)]
fn from (variant : INT_GROUP1_ISET_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP1_ISET_INT` writer - Sets INT in RIS register"]
pub type INT_GROUP1_ISET_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP1_ISET_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP1_ISET_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_group1_iset_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ISET_INT_AW :: INT_GROUP1_ISET_INT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_group1_iset_int_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ISET_INT_AW :: INT_GROUP1_ISET_INT_SET) } } impl W { # [doc = "Bit 0 - Sets INT in RIS register"]
# [inline (always)]
# [must_use]
pub fn int_group1_iset_int (& mut self) -> INT_GROUP1_ISET_INT_W < INT_GROUP1_ISET_SPEC , 0 > { INT_GROUP1_ISET_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP1_ISET_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_GROUP1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP1_ISET to value 0"]
impl crate :: Resettable for INT_GROUP1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_GROUP1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_group1_iclr`]
module"]
pub type INT_GROUP1_ICLR = crate :: Reg < int_group1_iclr :: INT_GROUP1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_group1_iclr { # [doc = "Register `INT_GROUP1_ICLR` writer"]
pub type W = crate :: W < INT_GROUP1_ICLR_SPEC > ; # [doc = "Clears INT in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_GROUP1_ICLR_INT_AW { # [doc = "0: NO_EFFECT"]
INT_GROUP1_ICLR_INT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_GROUP1_ICLR_INT_CLR = 1 , } impl From < INT_GROUP1_ICLR_INT_AW > for bool { # [inline (always)]
fn from (variant : INT_GROUP1_ICLR_INT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_GROUP1_ICLR_INT` writer - Clears INT in RIS register"]
pub type INT_GROUP1_ICLR_INT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_GROUP1_ICLR_INT_AW > ; impl < 'a , REG , const O : u8 > INT_GROUP1_ICLR_INT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_group1_iclr_int_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ICLR_INT_AW :: INT_GROUP1_ICLR_INT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_group1_iclr_int_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_GROUP1_ICLR_INT_AW :: INT_GROUP1_ICLR_INT_CLR) } } impl W { # [doc = "Bit 0 - Clears INT in RIS register"]
# [inline (always)]
# [must_use]
pub fn int_group1_iclr_int (& mut self) -> INT_GROUP1_ICLR_INT_W < INT_GROUP1_ICLR_SPEC , 0 > { INT_GROUP1_ICLR_INT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_group1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_GROUP1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_GROUP1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_group1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_GROUP1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_GROUP1_ICLR to value 0"]
impl crate :: Resettable for INT_GROUP1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL (rw) register accessor: Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`]
module"]
pub type CTL = crate :: Reg < ctl :: CTL_SPEC > ; # [doc = "Prefetch/Cache control"]
pub mod ctl { # [doc = "Register `CTL` reader"]
pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"]
pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_PREFETCH` reader - Used to enable/disable instruction prefetch to Flash."]
pub type CTL_PREFETCH_R = crate :: BitReader < CTL_PREFETCH_A > ; # [doc = "Used to enable/disable instruction prefetch to Flash.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL_PREFETCH_A { # [doc = "0: DISABLE"]
CTL_PREFETCH_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL_PREFETCH_ENABLE = 1 , } impl From < CTL_PREFETCH_A > for bool { # [inline (always)]
fn from (variant : CTL_PREFETCH_A) -> Self { variant as u8 != 0 } } impl CTL_PREFETCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL_PREFETCH_A { match self . bits { false => CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE , true => CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl_prefetch_disable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl_prefetch_enable (& self) -> bool { * self == CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE } } # [doc = "Field `CTL_PREFETCH` writer - Used to enable/disable instruction prefetch to Flash."]
pub type CTL_PREFETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_PREFETCH_A > ; impl < 'a , REG , const O : u8 > CTL_PREFETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl_prefetch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl_prefetch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_PREFETCH_A :: CTL_PREFETCH_ENABLE) } } # [doc = "Field `CTL_ICACHE` reader - Used to enable/disable Instruction caching on flash access."]
pub type CTL_ICACHE_R = crate :: BitReader < CTL_ICACHE_A > ; # [doc = "Used to enable/disable Instruction caching on flash access.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL_ICACHE_A { # [doc = "0: DISABLE"]
CTL_ICACHE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL_ICACHE_ENABLE = 1 , } impl From < CTL_ICACHE_A > for bool { # [inline (always)]
fn from (variant : CTL_ICACHE_A) -> Self { variant as u8 != 0 } } impl CTL_ICACHE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL_ICACHE_A { match self . bits { false => CTL_ICACHE_A :: CTL_ICACHE_DISABLE , true => CTL_ICACHE_A :: CTL_ICACHE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl_icache_disable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl_icache_enable (& self) -> bool { * self == CTL_ICACHE_A :: CTL_ICACHE_ENABLE } } # [doc = "Field `CTL_ICACHE` writer - Used to enable/disable Instruction caching on flash access."]
pub type CTL_ICACHE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ICACHE_A > ; impl < 'a , REG , const O : u8 > CTL_ICACHE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl_icache_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl_icache_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ICACHE_A :: CTL_ICACHE_ENABLE) } } # [doc = "Field `CTL_LITEN` reader - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"]
pub type CTL_LITEN_R = crate :: BitReader < CTL_LITEN_A > ; # [doc = "Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL_LITEN_A { # [doc = "0: DISABLE"]
CTL_LITEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL_LITEN_ENABLE = 1 , } impl From < CTL_LITEN_A > for bool { # [inline (always)]
fn from (variant : CTL_LITEN_A) -> Self { variant as u8 != 0 } } impl CTL_LITEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL_LITEN_A { match self . bits { false => CTL_LITEN_A :: CTL_LITEN_DISABLE , true => CTL_LITEN_A :: CTL_LITEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl_liten_disable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl_liten_enable (& self) -> bool { * self == CTL_LITEN_A :: CTL_LITEN_ENABLE } } # [doc = "Field `CTL_LITEN` writer - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"]
pub type CTL_LITEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_LITEN_A > ; impl < 'a , REG , const O : u8 > CTL_LITEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl_liten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl_liten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_LITEN_A :: CTL_LITEN_ENABLE) } } impl R { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."]
# [inline (always)]
pub fn ctl_prefetch (& self) -> CTL_PREFETCH_R { CTL_PREFETCH_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."]
# [inline (always)]
pub fn ctl_icache (& self) -> CTL_ICACHE_R { CTL_ICACHE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"]
# [inline (always)]
pub fn ctl_liten (& self) -> CTL_LITEN_R { CTL_LITEN_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Used to enable/disable instruction prefetch to Flash."]
# [inline (always)]
# [must_use]
pub fn ctl_prefetch (& mut self) -> CTL_PREFETCH_W < CTL_SPEC , 0 > { CTL_PREFETCH_W :: new (self) } # [doc = "Bit 1 - Used to enable/disable Instruction caching on flash access."]
# [inline (always)]
# [must_use]
pub fn ctl_icache (& mut self) -> CTL_ICACHE_W < CTL_SPEC , 1 > { CTL_ICACHE_W :: new (self) } # [doc = "Bit 2 - Literal caching and prefetch enable. This bit is a subset of ICACHE/PREFETCH bit i.e. literal caching or literal prefetching will only happen if ICACHE or PREFETCH bits have been set respectively When enabled, the cache and prefetcher structures inside CPUSS will cache and prefetch literals When disabled, the cache and prefetcher structures inside CPUSS will not cache and prefetch literals"]
# [inline (always)]
# [must_use]
pub fn ctl_liten (& mut self) -> CTL_LITEN_W < CTL_SPEC , 2 > { CTL_LITEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Prefetch/Cache control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"]
impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"]
impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0x07"]
impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x07 ; } } } # [doc = "PERIPHERALREGION"]
pub struct GPIOA { _marker : PhantomData < * const () > } unsafe impl Send for GPIOA { } impl GPIOA { # [doc = r"Pointer to the register block"]
pub const PTR : * const gpioa :: RegisterBlock = 0x400a_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const gpioa :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for GPIOA { type Target = gpioa :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for GPIOA { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("GPIOA") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod gpioa { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subsciber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , _reserved2 : [u8 ; 0x3c]
, # [doc = "0x444 - Publisher Port 0"]
pub fpub_0 : FPUB_0 , # [doc = "0x448 - Publisher Port 1"]
pub fpub_1 : FPUB_1 , _reserved4 : [u8 ; 0x03b4]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved6 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved7 : [u8 ; 0x07f8]
, # [doc = "0x1010 - Clock Override"]
pub clkovr : CLKOVR , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub int_event0_iidx : INT_EVENT0_IIDX , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub int_event0_imask : INT_EVENT0_IMASK , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub int_event0_ris : INT_EVENT0_RIS , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub int_event0_mis : INT_EVENT0_MIS , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub int_event0_iset : INT_EVENT0_ISET , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub int_event0_iclr : INT_EVENT0_ICLR , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1050 - Interrupt index"]
pub int_event1_iidx : INT_EVENT1_IIDX , _reserved16 : [u8 ; 0x04]
, # [doc = "0x1058 - Interrupt mask"]
pub int_event1_imask : INT_EVENT1_IMASK , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1060 - Raw interrupt status"]
pub int_event1_ris : INT_EVENT1_RIS , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1068 - Masked interrupt status"]
pub int_event1_mis : INT_EVENT1_MIS , _reserved19 : [u8 ; 0x04]
, # [doc = "0x1070 - Interrupt set"]
pub int_event1_iset : INT_EVENT1_ISET , _reserved20 : [u8 ; 0x04]
, # [doc = "0x1078 - Interrupt clear"]
pub int_event1_iclr : INT_EVENT1_ICLR , _reserved21 : [u8 ; 0x04]
, # [doc = "0x1080 - Interrupt index"]
pub int_event2_iidx : INT_EVENT2_IIDX , _reserved22 : [u8 ; 0x04]
, # [doc = "0x1088 - Interrupt mask"]
pub int_event2_imask : INT_EVENT2_IMASK , _reserved23 : [u8 ; 0x04]
, # [doc = "0x1090 - Raw interrupt status"]
pub int_event2_ris : INT_EVENT2_RIS , _reserved24 : [u8 ; 0x04]
, # [doc = "0x1098 - Masked interrupt status"]
pub int_event2_mis : INT_EVENT2_MIS , _reserved25 : [u8 ; 0x04]
, # [doc = "0x10a0 - Interrupt set"]
pub int_event2_iset : INT_EVENT2_ISET , _reserved26 : [u8 ; 0x04]
, # [doc = "0x10a8 - Interrupt clear"]
pub int_event2_iclr : INT_EVENT2_ICLR , _reserved27 : [u8 ; 0x34]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved28 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , _reserved29 : [u8 ; 0x0100]
, # [doc = "0x1200 - Data output 3 to 0"]
pub dout3_0 : DOUT3_0 , # [doc = "0x1204 - Data output 7 to 4"]
pub dout7_4 : DOUT7_4 , # [doc = "0x1208 - Data output 11 to 8"]
pub dout11_8 : DOUT11_8 , # [doc = "0x120c - Data output 15 to 12"]
pub dout15_12 : DOUT15_12 , # [doc = "0x1210 - Data output 19 to 16"]
pub dout19_16 : DOUT19_16 , # [doc = "0x1214 - Data output 23 to 20"]
pub dout23_20 : DOUT23_20 , # [doc = "0x1218 - Data output 27 to 24"]
pub dout27_24 : DOUT27_24 , # [doc = "0x121c - Data output 31 to 28"]
pub dout31_28 : DOUT31_28 , _reserved37 : [u8 ; 0x60]
, # [doc = "0x1280 - Data output 31 to 0"]
pub dout31_0 : DOUT31_0 , _reserved38 : [u8 ; 0x0c]
, # [doc = "0x1290 - Data output set 31 to 0"]
pub doutset31_0 : DOUTSET31_0 , _reserved39 : [u8 ; 0x0c]
, # [doc = "0x12a0 - Data output clear 31 to 0"]
pub doutclr31_0 : DOUTCLR31_0 , _reserved40 : [u8 ; 0x0c]
, # [doc = "0x12b0 - Data output toggle 31 to 0"]
pub douttgl31_0 : DOUTTGL31_0 , _reserved41 : [u8 ; 0x0c]
, # [doc = "0x12c0 - Data output enable 31 to 0"]
pub doe31_0 : DOE31_0 , _reserved42 : [u8 ; 0x0c]
, # [doc = "0x12d0 - Data output enable set 31 to 0"]
pub doeset31_0 : DOESET31_0 , _reserved43 : [u8 ; 0x0c]
, # [doc = "0x12e0 - Data output enable clear 31 to 0"]
pub doeclr31_0 : DOECLR31_0 , _reserved44 : [u8 ; 0x1c]
, # [doc = "0x1300 - Data input 3 to 0"]
pub din3_0 : DIN3_0 , # [doc = "0x1304 - Data input 7 to 4"]
pub din7_4 : DIN7_4 , # [doc = "0x1308 - Data input 11 to 8"]
pub din11_8 : DIN11_8 , # [doc = "0x130c - Data input 15 to 12"]
pub din15_12 : DIN15_12 , # [doc = "0x1310 - Data input 19 to 16"]
pub din19_16 : DIN19_16 , # [doc = "0x1314 - Data input 23 to 20"]
pub din23_20 : DIN23_20 , # [doc = "0x1318 - Data input 27 to 24"]
pub din27_24 : DIN27_24 , # [doc = "0x131c - Data input 31 to 28"]
pub din31_28 : DIN31_28 , _reserved52 : [u8 ; 0x60]
, # [doc = "0x1380 - Data input 31 to 0"]
pub din31_0 : DIN31_0 , _reserved53 : [u8 ; 0x0c]
, # [doc = "0x1390 - Polarity 15 to 0"]
pub polarity15_0 : POLARITY15_0 , _reserved54 : [u8 ; 0x0c]
, # [doc = "0x13a0 - Polarity 31 to 16"]
pub polarity31_16 : POLARITY31_16 , _reserved55 : [u8 ; 0x5c]
, # [doc = "0x1400 - FAST WAKE GLOBAL EN"]
pub ctl : CTL , # [doc = "0x1404 - FAST WAKE ENABLE"]
pub fastwake : FASTWAKE , _reserved57 : [u8 ; 0xf8]
, # [doc = "0x1500 - Subscriber 0 configuration"]
pub sub0cfg : SUB0CFG , _reserved58 : [u8 ; 0x04]
, # [doc = "0x1508 - Filter Enable 15 to 0"]
pub filteren15_0 : FILTEREN15_0 , # [doc = "0x150c - Filter Enable 31 to 16"]
pub filteren31_16 : FILTEREN31_16 , # [doc = "0x1510 - DMA Write MASK"]
pub dmamask : DMAMASK , _reserved61 : [u8 ; 0x0c]
, # [doc = "0x1520 - Subscriber 1 configuration"]
pub sub1cfg : SUB1CFG , } # [doc = "FSUB_0 (rw) register accessor: Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subsciber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_0 (rw) register accessor: Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_0`]
module"]
pub type FPUB_0 = crate :: Reg < fpub_0 :: FPUB_0_SPEC > ; # [doc = "Publisher Port 0"]
pub mod fpub_0 { # [doc = "Register `FPUB_0` reader"]
pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"]
pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"]
impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"]
impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"]
impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher Port 1"]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKOVR (rw) register accessor: Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkovr`]
module"]
pub type CLKOVR = crate :: Reg < clkovr :: CLKOVR_SPEC > ; # [doc = "Clock Override"]
pub mod clkovr { # [doc = "Register `CLKOVR` reader"]
pub type R = crate :: R < CLKOVR_SPEC > ; # [doc = "Register `CLKOVR` writer"]
pub type W = crate :: W < CLKOVR_SPEC > ; # [doc = "Field `CLKOVR_OVERRIDE` reader - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
pub type CLKOVR_OVERRIDE_R = crate :: BitReader < CLKOVR_OVERRIDE_A > ; # [doc = "Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKOVR_OVERRIDE_A { # [doc = "0: DISABLED"]
CLKOVR_OVERRIDE_DISABLED = 0 , # [doc = "1: ENABLED"]
CLKOVR_OVERRIDE_ENABLED = 1 , } impl From < CLKOVR_OVERRIDE_A > for bool { # [inline (always)]
fn from (variant : CLKOVR_OVERRIDE_A) -> Self { variant as u8 != 0 } } impl CLKOVR_OVERRIDE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKOVR_OVERRIDE_A { match self . bits { false => CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED , true => CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_clkovr_override_disabled (& self) -> bool { * self == CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_clkovr_override_enabled (& self) -> bool { * self == CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED } } # [doc = "Field `CLKOVR_OVERRIDE` writer - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
pub type CLKOVR_OVERRIDE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKOVR_OVERRIDE_A > ; impl < 'a , REG , const O : u8 > CLKOVR_OVERRIDE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn clkovr_override_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn clkovr_override_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED) } } # [doc = "Field `CLKOVR_RUN_STOP` reader - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
pub type CLKOVR_RUN_STOP_R = crate :: BitReader < CLKOVR_RUN_STOP_A > ; # [doc = "If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKOVR_RUN_STOP_A { # [doc = "0: RUN"]
CLKOVR_RUN_STOP_RUN = 0 , # [doc = "1: STOP"]
CLKOVR_RUN_STOP_STOP = 1 , } impl From < CLKOVR_RUN_STOP_A > for bool { # [inline (always)]
fn from (variant : CLKOVR_RUN_STOP_A) -> Self { variant as u8 != 0 } } impl CLKOVR_RUN_STOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKOVR_RUN_STOP_A { match self . bits { false => CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN , true => CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP , } } # [doc = "RUN"]
# [inline (always)]
pub fn is_clkovr_run_stop_run (& self) -> bool { * self == CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN } # [doc = "STOP"]
# [inline (always)]
pub fn is_clkovr_run_stop_stop (& self) -> bool { * self == CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP } } # [doc = "Field `CLKOVR_RUN_STOP` writer - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
pub type CLKOVR_RUN_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKOVR_RUN_STOP_A > ; impl < 'a , REG , const O : u8 > CLKOVR_RUN_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RUN"]
# [inline (always)]
pub fn clkovr_run_stop_run (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN) } # [doc = "STOP"]
# [inline (always)]
pub fn clkovr_run_stop_stop (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP) } } impl R { # [doc = "Bit 0 - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
# [inline (always)]
pub fn clkovr_override (& self) -> CLKOVR_OVERRIDE_R { CLKOVR_OVERRIDE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
# [inline (always)]
pub fn clkovr_run_stop (& self) -> CLKOVR_RUN_STOP_R { CLKOVR_RUN_STOP_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
# [inline (always)]
# [must_use]
pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W < CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
# [inline (always)]
# [must_use]
pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W < CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKOVR_SPEC ; impl crate :: RegisterSpec for CLKOVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkovr::R`](R) reader structure"]
impl crate :: Readable for CLKOVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkovr::W`](W) writer structure"]
impl crate :: Writable for CLKOVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKOVR to value 0"]
impl crate :: Resettable for CLKOVR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0x01"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0x01 ; } } # [doc = "INT_EVENT0_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iidx`]
module"]
pub type INT_EVENT0_IIDX = crate :: Reg < int_event0_iidx :: INT_EVENT0_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event0_iidx { # [doc = "Register `INT_EVENT0_IIDX` reader"]
pub type R = crate :: R < INT_EVENT0_IIDX_SPEC > ; # [doc = "Field `INT_EVENT0_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT0_IIDX_STAT_R = crate :: FieldReader < INT_EVENT0_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: DIO0"]
INT_EVENT0_IIDX_STAT_DIO0 = 1 , # [doc = "2: DIO1"]
INT_EVENT0_IIDX_STAT_DIO1 = 2 , # [doc = "3: DIO2"]
INT_EVENT0_IIDX_STAT_DIO2 = 3 , # [doc = "4: DIO3"]
INT_EVENT0_IIDX_STAT_DIO3 = 4 , # [doc = "5: DIO4"]
INT_EVENT0_IIDX_STAT_DIO4 = 5 , # [doc = "6: DIO5"]
INT_EVENT0_IIDX_STAT_DIO5 = 6 , # [doc = "7: DIO6"]
INT_EVENT0_IIDX_STAT_DIO6 = 7 , # [doc = "8: DIO7"]
INT_EVENT0_IIDX_STAT_DIO7 = 8 , # [doc = "9: DIO8"]
INT_EVENT0_IIDX_STAT_DIO8 = 9 , # [doc = "10: DIO9"]
INT_EVENT0_IIDX_STAT_DIO9 = 10 , # [doc = "11: DIO10"]
INT_EVENT0_IIDX_STAT_DIO10 = 11 , # [doc = "12: DIO11"]
INT_EVENT0_IIDX_STAT_DIO11 = 12 , # [doc = "13: DIO12"]
INT_EVENT0_IIDX_STAT_DIO12 = 13 , # [doc = "14: DIO13"]
INT_EVENT0_IIDX_STAT_DIO13 = 14 , # [doc = "15: DIO14"]
INT_EVENT0_IIDX_STAT_DIO14 = 15 , # [doc = "16: DIO15"]
INT_EVENT0_IIDX_STAT_DIO15 = 16 , # [doc = "17: DIO16"]
INT_EVENT0_IIDX_STAT_DIO16 = 17 , # [doc = "18: DIO17"]
INT_EVENT0_IIDX_STAT_DIO17 = 18 , # [doc = "19: DIO18"]
INT_EVENT0_IIDX_STAT_DIO18 = 19 , # [doc = "20: DIO19"]
INT_EVENT0_IIDX_STAT_DIO19 = 20 , # [doc = "21: DIO20"]
INT_EVENT0_IIDX_STAT_DIO20 = 21 , # [doc = "22: DIO21"]
INT_EVENT0_IIDX_STAT_DIO21 = 22 , # [doc = "23: DIO22"]
INT_EVENT0_IIDX_STAT_DIO22 = 23 , # [doc = "24: DIO23"]
INT_EVENT0_IIDX_STAT_DIO23 = 24 , # [doc = "25: DIO24"]
INT_EVENT0_IIDX_STAT_DIO24 = 25 , # [doc = "26: DIO25"]
INT_EVENT0_IIDX_STAT_DIO25 = 26 , # [doc = "27: DIO26"]
INT_EVENT0_IIDX_STAT_DIO26 = 27 , # [doc = "28: DIO27"]
INT_EVENT0_IIDX_STAT_DIO27 = 28 , # [doc = "29: DIO28"]
INT_EVENT0_IIDX_STAT_DIO28 = 29 , # [doc = "30: DIO29"]
INT_EVENT0_IIDX_STAT_DIO29 = 30 , # [doc = "31: DIO30"]
INT_EVENT0_IIDX_STAT_DIO30 = 31 , # [doc = "32: DIO31"]
INT_EVENT0_IIDX_STAT_DIO31 = 32 , } impl From < INT_EVENT0_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT0_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO0) , 2 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO1) , 3 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO2) , 4 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO3) , 5 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO4) , 6 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO5) , 7 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO6) , 8 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO7) , 9 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO8) , 10 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO9) , 11 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO10) , 12 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO11) , 13 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO12) , 14 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO13) , 15 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO14) , 16 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO15) , 17 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO16) , 18 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO17) , 19 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO18) , 20 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO19) , 21 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO20) , 22 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO21) , 23 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO22) , 24 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO23) , 25 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO24) , 26 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO25) , 27 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO26) , 28 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO27) , 29 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO28) , 30 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO29) , 31 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO30) , 32 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO31) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR } # [doc = "DIO0"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio0 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO0 } # [doc = "DIO1"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio1 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO1 } # [doc = "DIO2"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio2 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO2 } # [doc = "DIO3"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio3 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO3 } # [doc = "DIO4"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio4 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO4 } # [doc = "DIO5"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio5 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO5 } # [doc = "DIO6"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio6 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO6 } # [doc = "DIO7"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio7 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO7 } # [doc = "DIO8"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio8 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO8 } # [doc = "DIO9"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio9 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO9 } # [doc = "DIO10"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio10 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO10 } # [doc = "DIO11"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio11 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO11 } # [doc = "DIO12"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio12 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO12 } # [doc = "DIO13"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio13 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO13 } # [doc = "DIO14"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio14 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO14 } # [doc = "DIO15"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio15 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO15 } # [doc = "DIO16"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio16 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO16 } # [doc = "DIO17"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio17 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO17 } # [doc = "DIO18"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio18 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO18 } # [doc = "DIO19"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio19 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO19 } # [doc = "DIO20"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio20 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO20 } # [doc = "DIO21"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio21 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO21 } # [doc = "DIO22"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio22 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO22 } # [doc = "DIO23"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio23 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO23 } # [doc = "DIO24"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio24 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO24 } # [doc = "DIO25"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio25 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO25 } # [doc = "DIO26"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio26 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO26 } # [doc = "DIO27"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio27 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO27 } # [doc = "DIO28"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio28 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO28 } # [doc = "DIO29"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio29 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO29 } # [doc = "DIO30"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio30 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO30 } # [doc = "DIO31"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dio31 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DIO31 } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_event0_iidx_stat (& self) -> INT_EVENT0_IIDX_STAT_R { INT_EVENT0_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_imask`]
module"]
pub type INT_EVENT0_IMASK = crate :: Reg < int_event0_imask :: INT_EVENT0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event0_imask { # [doc = "Register `INT_EVENT0_IMASK` reader"]
pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"]
pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_DIO0` reader - DIO0 event mask"]
pub type INT_EVENT0_IMASK_DIO0_R = crate :: BitReader < INT_EVENT0_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO0_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO0_A { match self . bits { false => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR , true => INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio0_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO0` writer - DIO0 event mask"]
pub type INT_EVENT0_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO0_A :: INT_EVENT0_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` reader - DIO1 event mask"]
pub type INT_EVENT0_IMASK_DIO1_R = crate :: BitReader < INT_EVENT0_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO1_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO1_A { match self . bits { false => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR , true => INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio1_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO1` writer - DIO1 event mask"]
pub type INT_EVENT0_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO1_A :: INT_EVENT0_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` reader - DIO2 event mask"]
pub type INT_EVENT0_IMASK_DIO2_R = crate :: BitReader < INT_EVENT0_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO2_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO2_A { match self . bits { false => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR , true => INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio2_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO2` writer - DIO2 event mask"]
pub type INT_EVENT0_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO2_A :: INT_EVENT0_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` reader - DIO3 event mask"]
pub type INT_EVENT0_IMASK_DIO3_R = crate :: BitReader < INT_EVENT0_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO3_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO3_A { match self . bits { false => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR , true => INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio3_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO3` writer - DIO3 event mask"]
pub type INT_EVENT0_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO3_A :: INT_EVENT0_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` reader - DIO4 event mask"]
pub type INT_EVENT0_IMASK_DIO4_R = crate :: BitReader < INT_EVENT0_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO4_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO4_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO4_A { match self . bits { false => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR , true => INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio4_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio4_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO4` writer - DIO4 event mask"]
pub type INT_EVENT0_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO4_A :: INT_EVENT0_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` reader - DIO5 event mask"]
pub type INT_EVENT0_IMASK_DIO5_R = crate :: BitReader < INT_EVENT0_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO5_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO5_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO5_A { match self . bits { false => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR , true => INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio5_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio5_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO5` writer - DIO5 event mask"]
pub type INT_EVENT0_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO5_A :: INT_EVENT0_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` reader - DIO6 event mask"]
pub type INT_EVENT0_IMASK_DIO6_R = crate :: BitReader < INT_EVENT0_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO6_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO6_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO6_A { match self . bits { false => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR , true => INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio6_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio6_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO6` writer - DIO6 event mask"]
pub type INT_EVENT0_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO6_A :: INT_EVENT0_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` reader - DIO7 event mask"]
pub type INT_EVENT0_IMASK_DIO7_R = crate :: BitReader < INT_EVENT0_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO7_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO7_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO7_A { match self . bits { false => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR , true => INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio7_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio7_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO7` writer - DIO7 event mask"]
pub type INT_EVENT0_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO7_A :: INT_EVENT0_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` reader - DIO8 event mask"]
pub type INT_EVENT0_IMASK_DIO8_R = crate :: BitReader < INT_EVENT0_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO8_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO8_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO8_A { match self . bits { false => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR , true => INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio8_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio8_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO8` writer - DIO8 event mask"]
pub type INT_EVENT0_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO8_A :: INT_EVENT0_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` reader - DIO9 event mask"]
pub type INT_EVENT0_IMASK_DIO9_R = crate :: BitReader < INT_EVENT0_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO9_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO9_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO9_A { match self . bits { false => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR , true => INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio9_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio9_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO9` writer - DIO9 event mask"]
pub type INT_EVENT0_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO9_A :: INT_EVENT0_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` reader - DIO10 event mask"]
pub type INT_EVENT0_IMASK_DIO10_R = crate :: BitReader < INT_EVENT0_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO10_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO10_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO10_A { match self . bits { false => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR , true => INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio10_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio10_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO10` writer - DIO10 event mask"]
pub type INT_EVENT0_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO10_A :: INT_EVENT0_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` reader - DIO11 event mask"]
pub type INT_EVENT0_IMASK_DIO11_R = crate :: BitReader < INT_EVENT0_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO11_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO11_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO11_A { match self . bits { false => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR , true => INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio11_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio11_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO11` writer - DIO11 event mask"]
pub type INT_EVENT0_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO11_A :: INT_EVENT0_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` reader - DIO12 event mask"]
pub type INT_EVENT0_IMASK_DIO12_R = crate :: BitReader < INT_EVENT0_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO12_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO12_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO12_A { match self . bits { false => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR , true => INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio12_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio12_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO12` writer - DIO12 event mask"]
pub type INT_EVENT0_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO12_A :: INT_EVENT0_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` reader - DIO13 event mask"]
pub type INT_EVENT0_IMASK_DIO13_R = crate :: BitReader < INT_EVENT0_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO13_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO13_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO13_A { match self . bits { false => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR , true => INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio13_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio13_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO13` writer - DIO13 event mask"]
pub type INT_EVENT0_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO13_A :: INT_EVENT0_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` reader - DIO14 event mask"]
pub type INT_EVENT0_IMASK_DIO14_R = crate :: BitReader < INT_EVENT0_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO14_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO14_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO14_A { match self . bits { false => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR , true => INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio14_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio14_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO14` writer - DIO14 event mask"]
pub type INT_EVENT0_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO14_A :: INT_EVENT0_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` reader - DIO15 event mask"]
pub type INT_EVENT0_IMASK_DIO15_R = crate :: BitReader < INT_EVENT0_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO15_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO15_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO15_A { match self . bits { false => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR , true => INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio15_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio15_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO15` writer - DIO15 event mask"]
pub type INT_EVENT0_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO15_A :: INT_EVENT0_IMASK_DIO15_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` reader - DIO16 event mask"]
pub type INT_EVENT0_IMASK_DIO16_R = crate :: BitReader < INT_EVENT0_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO16_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO16_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO16_A { match self . bits { false => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR , true => INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio16_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio16_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO16` writer - DIO16 event mask"]
pub type INT_EVENT0_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO16_A :: INT_EVENT0_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` reader - DIO17 event mask"]
pub type INT_EVENT0_IMASK_DIO17_R = crate :: BitReader < INT_EVENT0_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO17_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO17_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO17_A { match self . bits { false => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR , true => INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio17_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio17_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO17` writer - DIO17 event mask"]
pub type INT_EVENT0_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO17_A :: INT_EVENT0_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` reader - DIO18 event mask"]
pub type INT_EVENT0_IMASK_DIO18_R = crate :: BitReader < INT_EVENT0_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO18_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO18_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO18_A { match self . bits { false => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR , true => INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio18_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio18_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO18` writer - DIO18 event mask"]
pub type INT_EVENT0_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO18_A :: INT_EVENT0_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` reader - DIO19 event mask"]
pub type INT_EVENT0_IMASK_DIO19_R = crate :: BitReader < INT_EVENT0_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO19_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO19_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO19_A { match self . bits { false => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR , true => INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio19_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio19_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO19` writer - DIO19 event mask"]
pub type INT_EVENT0_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO19_A :: INT_EVENT0_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` reader - DIO20 event mask"]
pub type INT_EVENT0_IMASK_DIO20_R = crate :: BitReader < INT_EVENT0_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO20_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO20_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO20_A { match self . bits { false => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR , true => INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio20_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio20_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO20` writer - DIO20 event mask"]
pub type INT_EVENT0_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO20_A :: INT_EVENT0_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` reader - DIO21 event mask"]
pub type INT_EVENT0_IMASK_DIO21_R = crate :: BitReader < INT_EVENT0_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO21_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO21_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO21_A { match self . bits { false => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR , true => INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio21_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio21_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO21` writer - DIO21 event mask"]
pub type INT_EVENT0_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO21_A :: INT_EVENT0_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` reader - DIO22 event mask"]
pub type INT_EVENT0_IMASK_DIO22_R = crate :: BitReader < INT_EVENT0_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO22_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO22_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO22_A { match self . bits { false => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR , true => INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio22_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio22_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO22` writer - DIO22 event mask"]
pub type INT_EVENT0_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO22_A :: INT_EVENT0_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` reader - DIO23 event mask"]
pub type INT_EVENT0_IMASK_DIO23_R = crate :: BitReader < INT_EVENT0_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO23_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO23_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO23_A { match self . bits { false => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR , true => INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio23_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio23_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO23` writer - DIO23 event mask"]
pub type INT_EVENT0_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO23_A :: INT_EVENT0_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` reader - DIO24 event mask"]
pub type INT_EVENT0_IMASK_DIO24_R = crate :: BitReader < INT_EVENT0_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO24_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO24_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO24_A { match self . bits { false => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR , true => INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio24_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio24_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO24` writer - DIO24 event mask"]
pub type INT_EVENT0_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO24_A :: INT_EVENT0_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` reader - DIO25 event mask"]
pub type INT_EVENT0_IMASK_DIO25_R = crate :: BitReader < INT_EVENT0_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO25_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO25_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO25_A { match self . bits { false => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR , true => INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio25_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio25_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO25` writer - DIO25 event mask"]
pub type INT_EVENT0_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO25_A :: INT_EVENT0_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` reader - DIO26 event mask"]
pub type INT_EVENT0_IMASK_DIO26_R = crate :: BitReader < INT_EVENT0_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO26_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO26_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO26_A { match self . bits { false => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR , true => INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio26_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio26_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO26` writer - DIO26 event mask"]
pub type INT_EVENT0_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO26_A :: INT_EVENT0_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` reader - DIO27 event mask"]
pub type INT_EVENT0_IMASK_DIO27_R = crate :: BitReader < INT_EVENT0_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO27_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO27_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO27_A { match self . bits { false => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR , true => INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio27_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio27_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO27` writer - DIO27 event mask"]
pub type INT_EVENT0_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO27_A :: INT_EVENT0_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` reader - DIO28 event mask"]
pub type INT_EVENT0_IMASK_DIO28_R = crate :: BitReader < INT_EVENT0_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO28_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO28_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO28_A { match self . bits { false => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR , true => INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio28_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio28_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO28` writer - DIO28 event mask"]
pub type INT_EVENT0_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO28_A :: INT_EVENT0_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` reader - DIO29 event mask"]
pub type INT_EVENT0_IMASK_DIO29_R = crate :: BitReader < INT_EVENT0_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO29_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO29_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO29_A { match self . bits { false => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR , true => INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio29_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio29_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO29` writer - DIO29 event mask"]
pub type INT_EVENT0_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO29_A :: INT_EVENT0_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` reader - DIO30 event mask"]
pub type INT_EVENT0_IMASK_DIO30_R = crate :: BitReader < INT_EVENT0_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO30_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO30_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO30_A { match self . bits { false => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR , true => INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio30_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio30_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO30` writer - DIO30 event mask"]
pub type INT_EVENT0_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO30_A :: INT_EVENT0_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` reader - DIO31 event mask"]
pub type INT_EVENT0_IMASK_DIO31_R = crate :: BitReader < INT_EVENT0_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DIO31_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT0_IMASK_DIO31_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DIO31_A { match self . bits { false => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR , true => INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dio31_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dio31_set (& self) -> bool { * self == INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT0_IMASK_DIO31` writer - DIO31 event mask"]
pub type INT_EVENT0_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DIO31_A :: INT_EVENT0_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio0 (& self) -> INT_EVENT0_IMASK_DIO0_R { INT_EVENT0_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio1 (& self) -> INT_EVENT0_IMASK_DIO1_R { INT_EVENT0_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio2 (& self) -> INT_EVENT0_IMASK_DIO2_R { INT_EVENT0_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio3 (& self) -> INT_EVENT0_IMASK_DIO3_R { INT_EVENT0_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio4 (& self) -> INT_EVENT0_IMASK_DIO4_R { INT_EVENT0_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio5 (& self) -> INT_EVENT0_IMASK_DIO5_R { INT_EVENT0_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio6 (& self) -> INT_EVENT0_IMASK_DIO6_R { INT_EVENT0_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio7 (& self) -> INT_EVENT0_IMASK_DIO7_R { INT_EVENT0_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio8 (& self) -> INT_EVENT0_IMASK_DIO8_R { INT_EVENT0_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio9 (& self) -> INT_EVENT0_IMASK_DIO9_R { INT_EVENT0_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio10 (& self) -> INT_EVENT0_IMASK_DIO10_R { INT_EVENT0_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio11 (& self) -> INT_EVENT0_IMASK_DIO11_R { INT_EVENT0_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio12 (& self) -> INT_EVENT0_IMASK_DIO12_R { INT_EVENT0_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio13 (& self) -> INT_EVENT0_IMASK_DIO13_R { INT_EVENT0_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio14 (& self) -> INT_EVENT0_IMASK_DIO14_R { INT_EVENT0_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio15 (& self) -> INT_EVENT0_IMASK_DIO15_R { INT_EVENT0_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio16 (& self) -> INT_EVENT0_IMASK_DIO16_R { INT_EVENT0_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio17 (& self) -> INT_EVENT0_IMASK_DIO17_R { INT_EVENT0_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio18 (& self) -> INT_EVENT0_IMASK_DIO18_R { INT_EVENT0_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio19 (& self) -> INT_EVENT0_IMASK_DIO19_R { INT_EVENT0_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio20 (& self) -> INT_EVENT0_IMASK_DIO20_R { INT_EVENT0_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio21 (& self) -> INT_EVENT0_IMASK_DIO21_R { INT_EVENT0_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio22 (& self) -> INT_EVENT0_IMASK_DIO22_R { INT_EVENT0_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio23 (& self) -> INT_EVENT0_IMASK_DIO23_R { INT_EVENT0_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio24 (& self) -> INT_EVENT0_IMASK_DIO24_R { INT_EVENT0_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio25 (& self) -> INT_EVENT0_IMASK_DIO25_R { INT_EVENT0_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio26 (& self) -> INT_EVENT0_IMASK_DIO26_R { INT_EVENT0_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio27 (& self) -> INT_EVENT0_IMASK_DIO27_R { INT_EVENT0_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio28 (& self) -> INT_EVENT0_IMASK_DIO28_R { INT_EVENT0_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio29 (& self) -> INT_EVENT0_IMASK_DIO29_R { INT_EVENT0_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio30 (& self) -> INT_EVENT0_IMASK_DIO30_R { INT_EVENT0_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"]
# [inline (always)]
pub fn int_event0_imask_dio31 (& self) -> INT_EVENT0_IMASK_DIO31_R { INT_EVENT0_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio0 (& mut self) -> INT_EVENT0_IMASK_DIO0_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio1 (& mut self) -> INT_EVENT0_IMASK_DIO1_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio2 (& mut self) -> INT_EVENT0_IMASK_DIO2_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio3 (& mut self) -> INT_EVENT0_IMASK_DIO3_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio4 (& mut self) -> INT_EVENT0_IMASK_DIO4_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio5 (& mut self) -> INT_EVENT0_IMASK_DIO5_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio6 (& mut self) -> INT_EVENT0_IMASK_DIO6_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio7 (& mut self) -> INT_EVENT0_IMASK_DIO7_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio8 (& mut self) -> INT_EVENT0_IMASK_DIO8_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio9 (& mut self) -> INT_EVENT0_IMASK_DIO9_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio10 (& mut self) -> INT_EVENT0_IMASK_DIO10_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio11 (& mut self) -> INT_EVENT0_IMASK_DIO11_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio12 (& mut self) -> INT_EVENT0_IMASK_DIO12_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio13 (& mut self) -> INT_EVENT0_IMASK_DIO13_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio14 (& mut self) -> INT_EVENT0_IMASK_DIO14_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio15 (& mut self) -> INT_EVENT0_IMASK_DIO15_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio16 (& mut self) -> INT_EVENT0_IMASK_DIO16_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio17 (& mut self) -> INT_EVENT0_IMASK_DIO17_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio18 (& mut self) -> INT_EVENT0_IMASK_DIO18_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio19 (& mut self) -> INT_EVENT0_IMASK_DIO19_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio20 (& mut self) -> INT_EVENT0_IMASK_DIO20_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio21 (& mut self) -> INT_EVENT0_IMASK_DIO21_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio22 (& mut self) -> INT_EVENT0_IMASK_DIO22_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio23 (& mut self) -> INT_EVENT0_IMASK_DIO23_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio24 (& mut self) -> INT_EVENT0_IMASK_DIO24_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio25 (& mut self) -> INT_EVENT0_IMASK_DIO25_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio26 (& mut self) -> INT_EVENT0_IMASK_DIO26_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio27 (& mut self) -> INT_EVENT0_IMASK_DIO27_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio28 (& mut self) -> INT_EVENT0_IMASK_DIO28_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio29 (& mut self) -> INT_EVENT0_IMASK_DIO29_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio30 (& mut self) -> INT_EVENT0_IMASK_DIO30_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dio31 (& mut self) -> INT_EVENT0_IMASK_DIO31_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_ris`]
module"]
pub type INT_EVENT0_RIS = crate :: Reg < int_event0_ris :: INT_EVENT0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event0_ris { # [doc = "Register `INT_EVENT0_RIS` reader"]
pub type R = crate :: R < INT_EVENT0_RIS_SPEC > ; # [doc = "Field `INT_EVENT0_RIS_DIO0` reader - DIO0 event"]
pub type INT_EVENT0_RIS_DIO0_R = crate :: BitReader < INT_EVENT0_RIS_DIO0_A > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO0_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO0_SET = 1 , } impl From < INT_EVENT0_RIS_DIO0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO0_A { match self . bits { false => INT_EVENT0_RIS_DIO0_A :: INT_EVENT0_RIS_DIO0_CLR , true => INT_EVENT0_RIS_DIO0_A :: INT_EVENT0_RIS_DIO0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio0_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO0_A :: INT_EVENT0_RIS_DIO0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio0_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO0_A :: INT_EVENT0_RIS_DIO0_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO1` reader - DIO1 event"]
pub type INT_EVENT0_RIS_DIO1_R = crate :: BitReader < INT_EVENT0_RIS_DIO1_A > ; # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO1_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO1_SET = 1 , } impl From < INT_EVENT0_RIS_DIO1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO1_A { match self . bits { false => INT_EVENT0_RIS_DIO1_A :: INT_EVENT0_RIS_DIO1_CLR , true => INT_EVENT0_RIS_DIO1_A :: INT_EVENT0_RIS_DIO1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio1_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO1_A :: INT_EVENT0_RIS_DIO1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio1_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO1_A :: INT_EVENT0_RIS_DIO1_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO2` reader - DIO2 event"]
pub type INT_EVENT0_RIS_DIO2_R = crate :: BitReader < INT_EVENT0_RIS_DIO2_A > ; # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO2_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO2_SET = 1 , } impl From < INT_EVENT0_RIS_DIO2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO2_A { match self . bits { false => INT_EVENT0_RIS_DIO2_A :: INT_EVENT0_RIS_DIO2_CLR , true => INT_EVENT0_RIS_DIO2_A :: INT_EVENT0_RIS_DIO2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio2_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO2_A :: INT_EVENT0_RIS_DIO2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio2_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO2_A :: INT_EVENT0_RIS_DIO2_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO3` reader - DIO3 event"]
pub type INT_EVENT0_RIS_DIO3_R = crate :: BitReader < INT_EVENT0_RIS_DIO3_A > ; # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO3_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO3_SET = 1 , } impl From < INT_EVENT0_RIS_DIO3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO3_A { match self . bits { false => INT_EVENT0_RIS_DIO3_A :: INT_EVENT0_RIS_DIO3_CLR , true => INT_EVENT0_RIS_DIO3_A :: INT_EVENT0_RIS_DIO3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio3_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO3_A :: INT_EVENT0_RIS_DIO3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio3_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO3_A :: INT_EVENT0_RIS_DIO3_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO4` reader - DIO4 event"]
pub type INT_EVENT0_RIS_DIO4_R = crate :: BitReader < INT_EVENT0_RIS_DIO4_A > ; # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO4_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO4_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO4_SET = 1 , } impl From < INT_EVENT0_RIS_DIO4_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO4_A { match self . bits { false => INT_EVENT0_RIS_DIO4_A :: INT_EVENT0_RIS_DIO4_CLR , true => INT_EVENT0_RIS_DIO4_A :: INT_EVENT0_RIS_DIO4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio4_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO4_A :: INT_EVENT0_RIS_DIO4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio4_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO4_A :: INT_EVENT0_RIS_DIO4_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO5` reader - DIO5 event"]
pub type INT_EVENT0_RIS_DIO5_R = crate :: BitReader < INT_EVENT0_RIS_DIO5_A > ; # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO5_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO5_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO5_SET = 1 , } impl From < INT_EVENT0_RIS_DIO5_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO5_A { match self . bits { false => INT_EVENT0_RIS_DIO5_A :: INT_EVENT0_RIS_DIO5_CLR , true => INT_EVENT0_RIS_DIO5_A :: INT_EVENT0_RIS_DIO5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio5_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO5_A :: INT_EVENT0_RIS_DIO5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio5_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO5_A :: INT_EVENT0_RIS_DIO5_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO6` reader - DIO6 event"]
pub type INT_EVENT0_RIS_DIO6_R = crate :: BitReader < INT_EVENT0_RIS_DIO6_A > ; # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO6_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO6_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO6_SET = 1 , } impl From < INT_EVENT0_RIS_DIO6_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO6_A { match self . bits { false => INT_EVENT0_RIS_DIO6_A :: INT_EVENT0_RIS_DIO6_CLR , true => INT_EVENT0_RIS_DIO6_A :: INT_EVENT0_RIS_DIO6_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio6_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO6_A :: INT_EVENT0_RIS_DIO6_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio6_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO6_A :: INT_EVENT0_RIS_DIO6_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO7` reader - DIO7 event"]
pub type INT_EVENT0_RIS_DIO7_R = crate :: BitReader < INT_EVENT0_RIS_DIO7_A > ; # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO7_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO7_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO7_SET = 1 , } impl From < INT_EVENT0_RIS_DIO7_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO7_A { match self . bits { false => INT_EVENT0_RIS_DIO7_A :: INT_EVENT0_RIS_DIO7_CLR , true => INT_EVENT0_RIS_DIO7_A :: INT_EVENT0_RIS_DIO7_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio7_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO7_A :: INT_EVENT0_RIS_DIO7_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio7_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO7_A :: INT_EVENT0_RIS_DIO7_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO8` reader - DIO8 event"]
pub type INT_EVENT0_RIS_DIO8_R = crate :: BitReader < INT_EVENT0_RIS_DIO8_A > ; # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO8_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO8_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO8_SET = 1 , } impl From < INT_EVENT0_RIS_DIO8_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO8_A { match self . bits { false => INT_EVENT0_RIS_DIO8_A :: INT_EVENT0_RIS_DIO8_CLR , true => INT_EVENT0_RIS_DIO8_A :: INT_EVENT0_RIS_DIO8_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio8_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO8_A :: INT_EVENT0_RIS_DIO8_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio8_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO8_A :: INT_EVENT0_RIS_DIO8_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO9` reader - DIO9 event"]
pub type INT_EVENT0_RIS_DIO9_R = crate :: BitReader < INT_EVENT0_RIS_DIO9_A > ; # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO9_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO9_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO9_SET = 1 , } impl From < INT_EVENT0_RIS_DIO9_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO9_A { match self . bits { false => INT_EVENT0_RIS_DIO9_A :: INT_EVENT0_RIS_DIO9_CLR , true => INT_EVENT0_RIS_DIO9_A :: INT_EVENT0_RIS_DIO9_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio9_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO9_A :: INT_EVENT0_RIS_DIO9_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio9_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO9_A :: INT_EVENT0_RIS_DIO9_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO10` reader - DIO10 event"]
pub type INT_EVENT0_RIS_DIO10_R = crate :: BitReader < INT_EVENT0_RIS_DIO10_A > ; # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO10_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO10_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO10_SET = 1 , } impl From < INT_EVENT0_RIS_DIO10_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO10_A { match self . bits { false => INT_EVENT0_RIS_DIO10_A :: INT_EVENT0_RIS_DIO10_CLR , true => INT_EVENT0_RIS_DIO10_A :: INT_EVENT0_RIS_DIO10_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio10_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO10_A :: INT_EVENT0_RIS_DIO10_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio10_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO10_A :: INT_EVENT0_RIS_DIO10_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO11` reader - DIO11 event"]
pub type INT_EVENT0_RIS_DIO11_R = crate :: BitReader < INT_EVENT0_RIS_DIO11_A > ; # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO11_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO11_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO11_SET = 1 , } impl From < INT_EVENT0_RIS_DIO11_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO11_A { match self . bits { false => INT_EVENT0_RIS_DIO11_A :: INT_EVENT0_RIS_DIO11_CLR , true => INT_EVENT0_RIS_DIO11_A :: INT_EVENT0_RIS_DIO11_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio11_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO11_A :: INT_EVENT0_RIS_DIO11_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio11_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO11_A :: INT_EVENT0_RIS_DIO11_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO12` reader - DIO12 event"]
pub type INT_EVENT0_RIS_DIO12_R = crate :: BitReader < INT_EVENT0_RIS_DIO12_A > ; # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO12_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO12_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO12_SET = 1 , } impl From < INT_EVENT0_RIS_DIO12_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO12_A { match self . bits { false => INT_EVENT0_RIS_DIO12_A :: INT_EVENT0_RIS_DIO12_CLR , true => INT_EVENT0_RIS_DIO12_A :: INT_EVENT0_RIS_DIO12_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio12_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO12_A :: INT_EVENT0_RIS_DIO12_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio12_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO12_A :: INT_EVENT0_RIS_DIO12_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO13` reader - DIO13 event"]
pub type INT_EVENT0_RIS_DIO13_R = crate :: BitReader < INT_EVENT0_RIS_DIO13_A > ; # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO13_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO13_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO13_SET = 1 , } impl From < INT_EVENT0_RIS_DIO13_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO13_A { match self . bits { false => INT_EVENT0_RIS_DIO13_A :: INT_EVENT0_RIS_DIO13_CLR , true => INT_EVENT0_RIS_DIO13_A :: INT_EVENT0_RIS_DIO13_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio13_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO13_A :: INT_EVENT0_RIS_DIO13_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio13_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO13_A :: INT_EVENT0_RIS_DIO13_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO14` reader - DIO14 event"]
pub type INT_EVENT0_RIS_DIO14_R = crate :: BitReader < INT_EVENT0_RIS_DIO14_A > ; # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO14_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO14_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO14_SET = 1 , } impl From < INT_EVENT0_RIS_DIO14_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO14_A { match self . bits { false => INT_EVENT0_RIS_DIO14_A :: INT_EVENT0_RIS_DIO14_CLR , true => INT_EVENT0_RIS_DIO14_A :: INT_EVENT0_RIS_DIO14_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio14_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO14_A :: INT_EVENT0_RIS_DIO14_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio14_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO14_A :: INT_EVENT0_RIS_DIO14_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO15` reader - DIO15 event"]
pub type INT_EVENT0_RIS_DIO15_R = crate :: BitReader < INT_EVENT0_RIS_DIO15_A > ; # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO15_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO15_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO15_SET = 1 , } impl From < INT_EVENT0_RIS_DIO15_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO15_A { match self . bits { false => INT_EVENT0_RIS_DIO15_A :: INT_EVENT0_RIS_DIO15_CLR , true => INT_EVENT0_RIS_DIO15_A :: INT_EVENT0_RIS_DIO15_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio15_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO15_A :: INT_EVENT0_RIS_DIO15_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio15_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO15_A :: INT_EVENT0_RIS_DIO15_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO16` reader - DIO16 event"]
pub type INT_EVENT0_RIS_DIO16_R = crate :: BitReader < INT_EVENT0_RIS_DIO16_A > ; # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO16_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO16_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO16_SET = 1 , } impl From < INT_EVENT0_RIS_DIO16_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO16_A { match self . bits { false => INT_EVENT0_RIS_DIO16_A :: INT_EVENT0_RIS_DIO16_CLR , true => INT_EVENT0_RIS_DIO16_A :: INT_EVENT0_RIS_DIO16_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio16_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO16_A :: INT_EVENT0_RIS_DIO16_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio16_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO16_A :: INT_EVENT0_RIS_DIO16_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO17` reader - DIO17 event"]
pub type INT_EVENT0_RIS_DIO17_R = crate :: BitReader < INT_EVENT0_RIS_DIO17_A > ; # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO17_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO17_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO17_SET = 1 , } impl From < INT_EVENT0_RIS_DIO17_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO17_A { match self . bits { false => INT_EVENT0_RIS_DIO17_A :: INT_EVENT0_RIS_DIO17_CLR , true => INT_EVENT0_RIS_DIO17_A :: INT_EVENT0_RIS_DIO17_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio17_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO17_A :: INT_EVENT0_RIS_DIO17_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio17_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO17_A :: INT_EVENT0_RIS_DIO17_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO18` reader - DIO18 event"]
pub type INT_EVENT0_RIS_DIO18_R = crate :: BitReader < INT_EVENT0_RIS_DIO18_A > ; # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO18_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO18_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO18_SET = 1 , } impl From < INT_EVENT0_RIS_DIO18_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO18_A { match self . bits { false => INT_EVENT0_RIS_DIO18_A :: INT_EVENT0_RIS_DIO18_CLR , true => INT_EVENT0_RIS_DIO18_A :: INT_EVENT0_RIS_DIO18_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio18_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO18_A :: INT_EVENT0_RIS_DIO18_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio18_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO18_A :: INT_EVENT0_RIS_DIO18_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO19` reader - DIO19 event"]
pub type INT_EVENT0_RIS_DIO19_R = crate :: BitReader < INT_EVENT0_RIS_DIO19_A > ; # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO19_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO19_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO19_SET = 1 , } impl From < INT_EVENT0_RIS_DIO19_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO19_A { match self . bits { false => INT_EVENT0_RIS_DIO19_A :: INT_EVENT0_RIS_DIO19_CLR , true => INT_EVENT0_RIS_DIO19_A :: INT_EVENT0_RIS_DIO19_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio19_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO19_A :: INT_EVENT0_RIS_DIO19_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio19_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO19_A :: INT_EVENT0_RIS_DIO19_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO20` reader - DIO20 event"]
pub type INT_EVENT0_RIS_DIO20_R = crate :: BitReader < INT_EVENT0_RIS_DIO20_A > ; # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO20_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO20_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO20_SET = 1 , } impl From < INT_EVENT0_RIS_DIO20_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO20_A { match self . bits { false => INT_EVENT0_RIS_DIO20_A :: INT_EVENT0_RIS_DIO20_CLR , true => INT_EVENT0_RIS_DIO20_A :: INT_EVENT0_RIS_DIO20_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio20_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO20_A :: INT_EVENT0_RIS_DIO20_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio20_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO20_A :: INT_EVENT0_RIS_DIO20_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO21` reader - DIO21 event"]
pub type INT_EVENT0_RIS_DIO21_R = crate :: BitReader < INT_EVENT0_RIS_DIO21_A > ; # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO21_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO21_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO21_SET = 1 , } impl From < INT_EVENT0_RIS_DIO21_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO21_A { match self . bits { false => INT_EVENT0_RIS_DIO21_A :: INT_EVENT0_RIS_DIO21_CLR , true => INT_EVENT0_RIS_DIO21_A :: INT_EVENT0_RIS_DIO21_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio21_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO21_A :: INT_EVENT0_RIS_DIO21_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio21_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO21_A :: INT_EVENT0_RIS_DIO21_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO22` reader - DIO22 event"]
pub type INT_EVENT0_RIS_DIO22_R = crate :: BitReader < INT_EVENT0_RIS_DIO22_A > ; # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO22_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO22_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO22_SET = 1 , } impl From < INT_EVENT0_RIS_DIO22_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO22_A { match self . bits { false => INT_EVENT0_RIS_DIO22_A :: INT_EVENT0_RIS_DIO22_CLR , true => INT_EVENT0_RIS_DIO22_A :: INT_EVENT0_RIS_DIO22_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio22_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO22_A :: INT_EVENT0_RIS_DIO22_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio22_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO22_A :: INT_EVENT0_RIS_DIO22_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO23` reader - DIO23 event"]
pub type INT_EVENT0_RIS_DIO23_R = crate :: BitReader < INT_EVENT0_RIS_DIO23_A > ; # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO23_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO23_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO23_SET = 1 , } impl From < INT_EVENT0_RIS_DIO23_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO23_A { match self . bits { false => INT_EVENT0_RIS_DIO23_A :: INT_EVENT0_RIS_DIO23_CLR , true => INT_EVENT0_RIS_DIO23_A :: INT_EVENT0_RIS_DIO23_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio23_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO23_A :: INT_EVENT0_RIS_DIO23_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio23_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO23_A :: INT_EVENT0_RIS_DIO23_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO24` reader - DIO24 event"]
pub type INT_EVENT0_RIS_DIO24_R = crate :: BitReader < INT_EVENT0_RIS_DIO24_A > ; # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO24_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO24_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO24_SET = 1 , } impl From < INT_EVENT0_RIS_DIO24_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO24_A { match self . bits { false => INT_EVENT0_RIS_DIO24_A :: INT_EVENT0_RIS_DIO24_CLR , true => INT_EVENT0_RIS_DIO24_A :: INT_EVENT0_RIS_DIO24_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio24_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO24_A :: INT_EVENT0_RIS_DIO24_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio24_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO24_A :: INT_EVENT0_RIS_DIO24_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO25` reader - DIO25 event"]
pub type INT_EVENT0_RIS_DIO25_R = crate :: BitReader < INT_EVENT0_RIS_DIO25_A > ; # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO25_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO25_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO25_SET = 1 , } impl From < INT_EVENT0_RIS_DIO25_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO25_A { match self . bits { false => INT_EVENT0_RIS_DIO25_A :: INT_EVENT0_RIS_DIO25_CLR , true => INT_EVENT0_RIS_DIO25_A :: INT_EVENT0_RIS_DIO25_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio25_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO25_A :: INT_EVENT0_RIS_DIO25_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio25_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO25_A :: INT_EVENT0_RIS_DIO25_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO26` reader - DIO26 event"]
pub type INT_EVENT0_RIS_DIO26_R = crate :: BitReader < INT_EVENT0_RIS_DIO26_A > ; # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO26_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO26_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO26_SET = 1 , } impl From < INT_EVENT0_RIS_DIO26_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO26_A { match self . bits { false => INT_EVENT0_RIS_DIO26_A :: INT_EVENT0_RIS_DIO26_CLR , true => INT_EVENT0_RIS_DIO26_A :: INT_EVENT0_RIS_DIO26_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio26_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO26_A :: INT_EVENT0_RIS_DIO26_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio26_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO26_A :: INT_EVENT0_RIS_DIO26_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO27` reader - DIO27 event"]
pub type INT_EVENT0_RIS_DIO27_R = crate :: BitReader < INT_EVENT0_RIS_DIO27_A > ; # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO27_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO27_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO27_SET = 1 , } impl From < INT_EVENT0_RIS_DIO27_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO27_A { match self . bits { false => INT_EVENT0_RIS_DIO27_A :: INT_EVENT0_RIS_DIO27_CLR , true => INT_EVENT0_RIS_DIO27_A :: INT_EVENT0_RIS_DIO27_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio27_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO27_A :: INT_EVENT0_RIS_DIO27_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio27_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO27_A :: INT_EVENT0_RIS_DIO27_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO28` reader - DIO28 event"]
pub type INT_EVENT0_RIS_DIO28_R = crate :: BitReader < INT_EVENT0_RIS_DIO28_A > ; # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO28_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO28_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO28_SET = 1 , } impl From < INT_EVENT0_RIS_DIO28_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO28_A { match self . bits { false => INT_EVENT0_RIS_DIO28_A :: INT_EVENT0_RIS_DIO28_CLR , true => INT_EVENT0_RIS_DIO28_A :: INT_EVENT0_RIS_DIO28_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio28_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO28_A :: INT_EVENT0_RIS_DIO28_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio28_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO28_A :: INT_EVENT0_RIS_DIO28_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO29` reader - DIO29 event"]
pub type INT_EVENT0_RIS_DIO29_R = crate :: BitReader < INT_EVENT0_RIS_DIO29_A > ; # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO29_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO29_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO29_SET = 1 , } impl From < INT_EVENT0_RIS_DIO29_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO29_A { match self . bits { false => INT_EVENT0_RIS_DIO29_A :: INT_EVENT0_RIS_DIO29_CLR , true => INT_EVENT0_RIS_DIO29_A :: INT_EVENT0_RIS_DIO29_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio29_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO29_A :: INT_EVENT0_RIS_DIO29_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio29_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO29_A :: INT_EVENT0_RIS_DIO29_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO30` reader - DIO30 event"]
pub type INT_EVENT0_RIS_DIO30_R = crate :: BitReader < INT_EVENT0_RIS_DIO30_A > ; # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO30_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO30_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO30_SET = 1 , } impl From < INT_EVENT0_RIS_DIO30_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO30_A { match self . bits { false => INT_EVENT0_RIS_DIO30_A :: INT_EVENT0_RIS_DIO30_CLR , true => INT_EVENT0_RIS_DIO30_A :: INT_EVENT0_RIS_DIO30_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio30_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO30_A :: INT_EVENT0_RIS_DIO30_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio30_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO30_A :: INT_EVENT0_RIS_DIO30_SET } } # [doc = "Field `INT_EVENT0_RIS_DIO31` reader - DIO31 event"]
pub type INT_EVENT0_RIS_DIO31_R = crate :: BitReader < INT_EVENT0_RIS_DIO31_A > ; # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DIO31_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DIO31_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DIO31_SET = 1 , } impl From < INT_EVENT0_RIS_DIO31_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DIO31_A { match self . bits { false => INT_EVENT0_RIS_DIO31_A :: INT_EVENT0_RIS_DIO31_CLR , true => INT_EVENT0_RIS_DIO31_A :: INT_EVENT0_RIS_DIO31_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dio31_clr (& self) -> bool { * self == INT_EVENT0_RIS_DIO31_A :: INT_EVENT0_RIS_DIO31_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dio31_set (& self) -> bool { * self == INT_EVENT0_RIS_DIO31_A :: INT_EVENT0_RIS_DIO31_SET } } impl R { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
pub fn int_event0_ris_dio0 (& self) -> INT_EVENT0_RIS_DIO0_R { INT_EVENT0_RIS_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
pub fn int_event0_ris_dio1 (& self) -> INT_EVENT0_RIS_DIO1_R { INT_EVENT0_RIS_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
pub fn int_event0_ris_dio2 (& self) -> INT_EVENT0_RIS_DIO2_R { INT_EVENT0_RIS_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
pub fn int_event0_ris_dio3 (& self) -> INT_EVENT0_RIS_DIO3_R { INT_EVENT0_RIS_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
pub fn int_event0_ris_dio4 (& self) -> INT_EVENT0_RIS_DIO4_R { INT_EVENT0_RIS_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
pub fn int_event0_ris_dio5 (& self) -> INT_EVENT0_RIS_DIO5_R { INT_EVENT0_RIS_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
pub fn int_event0_ris_dio6 (& self) -> INT_EVENT0_RIS_DIO6_R { INT_EVENT0_RIS_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
pub fn int_event0_ris_dio7 (& self) -> INT_EVENT0_RIS_DIO7_R { INT_EVENT0_RIS_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
pub fn int_event0_ris_dio8 (& self) -> INT_EVENT0_RIS_DIO8_R { INT_EVENT0_RIS_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
pub fn int_event0_ris_dio9 (& self) -> INT_EVENT0_RIS_DIO9_R { INT_EVENT0_RIS_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
pub fn int_event0_ris_dio10 (& self) -> INT_EVENT0_RIS_DIO10_R { INT_EVENT0_RIS_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
pub fn int_event0_ris_dio11 (& self) -> INT_EVENT0_RIS_DIO11_R { INT_EVENT0_RIS_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
pub fn int_event0_ris_dio12 (& self) -> INT_EVENT0_RIS_DIO12_R { INT_EVENT0_RIS_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
pub fn int_event0_ris_dio13 (& self) -> INT_EVENT0_RIS_DIO13_R { INT_EVENT0_RIS_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
pub fn int_event0_ris_dio14 (& self) -> INT_EVENT0_RIS_DIO14_R { INT_EVENT0_RIS_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
pub fn int_event0_ris_dio15 (& self) -> INT_EVENT0_RIS_DIO15_R { INT_EVENT0_RIS_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
pub fn int_event0_ris_dio16 (& self) -> INT_EVENT0_RIS_DIO16_R { INT_EVENT0_RIS_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
pub fn int_event0_ris_dio17 (& self) -> INT_EVENT0_RIS_DIO17_R { INT_EVENT0_RIS_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
pub fn int_event0_ris_dio18 (& self) -> INT_EVENT0_RIS_DIO18_R { INT_EVENT0_RIS_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
pub fn int_event0_ris_dio19 (& self) -> INT_EVENT0_RIS_DIO19_R { INT_EVENT0_RIS_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
pub fn int_event0_ris_dio20 (& self) -> INT_EVENT0_RIS_DIO20_R { INT_EVENT0_RIS_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
pub fn int_event0_ris_dio21 (& self) -> INT_EVENT0_RIS_DIO21_R { INT_EVENT0_RIS_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
pub fn int_event0_ris_dio22 (& self) -> INT_EVENT0_RIS_DIO22_R { INT_EVENT0_RIS_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
pub fn int_event0_ris_dio23 (& self) -> INT_EVENT0_RIS_DIO23_R { INT_EVENT0_RIS_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
pub fn int_event0_ris_dio24 (& self) -> INT_EVENT0_RIS_DIO24_R { INT_EVENT0_RIS_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
pub fn int_event0_ris_dio25 (& self) -> INT_EVENT0_RIS_DIO25_R { INT_EVENT0_RIS_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
pub fn int_event0_ris_dio26 (& self) -> INT_EVENT0_RIS_DIO26_R { INT_EVENT0_RIS_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
pub fn int_event0_ris_dio27 (& self) -> INT_EVENT0_RIS_DIO27_R { INT_EVENT0_RIS_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
pub fn int_event0_ris_dio28 (& self) -> INT_EVENT0_RIS_DIO28_R { INT_EVENT0_RIS_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
pub fn int_event0_ris_dio29 (& self) -> INT_EVENT0_RIS_DIO29_R { INT_EVENT0_RIS_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
pub fn int_event0_ris_dio30 (& self) -> INT_EVENT0_RIS_DIO30_R { INT_EVENT0_RIS_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
pub fn int_event0_ris_dio31 (& self) -> INT_EVENT0_RIS_DIO31_R { INT_EVENT0_RIS_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_RIS to value 0"]
impl crate :: Resettable for INT_EVENT0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_mis`]
module"]
pub type INT_EVENT0_MIS = crate :: Reg < int_event0_mis :: INT_EVENT0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event0_mis { # [doc = "Register `INT_EVENT0_MIS` reader"]
pub type R = crate :: R < INT_EVENT0_MIS_SPEC > ; # [doc = "Field `INT_EVENT0_MIS_DIO0` reader - DIO0 event"]
pub type INT_EVENT0_MIS_DIO0_R = crate :: BitReader < INT_EVENT0_MIS_DIO0_A > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO0_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO0_SET = 1 , } impl From < INT_EVENT0_MIS_DIO0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO0_A { match self . bits { false => INT_EVENT0_MIS_DIO0_A :: INT_EVENT0_MIS_DIO0_CLR , true => INT_EVENT0_MIS_DIO0_A :: INT_EVENT0_MIS_DIO0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio0_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO0_A :: INT_EVENT0_MIS_DIO0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio0_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO0_A :: INT_EVENT0_MIS_DIO0_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO1` reader - DIO1 event"]
pub type INT_EVENT0_MIS_DIO1_R = crate :: BitReader < INT_EVENT0_MIS_DIO1_A > ; # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO1_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO1_SET = 1 , } impl From < INT_EVENT0_MIS_DIO1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO1_A { match self . bits { false => INT_EVENT0_MIS_DIO1_A :: INT_EVENT0_MIS_DIO1_CLR , true => INT_EVENT0_MIS_DIO1_A :: INT_EVENT0_MIS_DIO1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio1_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO1_A :: INT_EVENT0_MIS_DIO1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio1_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO1_A :: INT_EVENT0_MIS_DIO1_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO2` reader - DIO2 event"]
pub type INT_EVENT0_MIS_DIO2_R = crate :: BitReader < INT_EVENT0_MIS_DIO2_A > ; # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO2_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO2_SET = 1 , } impl From < INT_EVENT0_MIS_DIO2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO2_A { match self . bits { false => INT_EVENT0_MIS_DIO2_A :: INT_EVENT0_MIS_DIO2_CLR , true => INT_EVENT0_MIS_DIO2_A :: INT_EVENT0_MIS_DIO2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio2_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO2_A :: INT_EVENT0_MIS_DIO2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio2_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO2_A :: INT_EVENT0_MIS_DIO2_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO3` reader - DIO3 event"]
pub type INT_EVENT0_MIS_DIO3_R = crate :: BitReader < INT_EVENT0_MIS_DIO3_A > ; # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO3_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO3_SET = 1 , } impl From < INT_EVENT0_MIS_DIO3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO3_A { match self . bits { false => INT_EVENT0_MIS_DIO3_A :: INT_EVENT0_MIS_DIO3_CLR , true => INT_EVENT0_MIS_DIO3_A :: INT_EVENT0_MIS_DIO3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio3_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO3_A :: INT_EVENT0_MIS_DIO3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio3_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO3_A :: INT_EVENT0_MIS_DIO3_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO4` reader - DIO4 event"]
pub type INT_EVENT0_MIS_DIO4_R = crate :: BitReader < INT_EVENT0_MIS_DIO4_A > ; # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO4_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO4_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO4_SET = 1 , } impl From < INT_EVENT0_MIS_DIO4_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO4_A { match self . bits { false => INT_EVENT0_MIS_DIO4_A :: INT_EVENT0_MIS_DIO4_CLR , true => INT_EVENT0_MIS_DIO4_A :: INT_EVENT0_MIS_DIO4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio4_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO4_A :: INT_EVENT0_MIS_DIO4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio4_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO4_A :: INT_EVENT0_MIS_DIO4_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO5` reader - DIO5 event"]
pub type INT_EVENT0_MIS_DIO5_R = crate :: BitReader < INT_EVENT0_MIS_DIO5_A > ; # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO5_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO5_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO5_SET = 1 , } impl From < INT_EVENT0_MIS_DIO5_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO5_A { match self . bits { false => INT_EVENT0_MIS_DIO5_A :: INT_EVENT0_MIS_DIO5_CLR , true => INT_EVENT0_MIS_DIO5_A :: INT_EVENT0_MIS_DIO5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio5_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO5_A :: INT_EVENT0_MIS_DIO5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio5_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO5_A :: INT_EVENT0_MIS_DIO5_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO6` reader - DIO6 event"]
pub type INT_EVENT0_MIS_DIO6_R = crate :: BitReader < INT_EVENT0_MIS_DIO6_A > ; # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO6_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO6_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO6_SET = 1 , } impl From < INT_EVENT0_MIS_DIO6_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO6_A { match self . bits { false => INT_EVENT0_MIS_DIO6_A :: INT_EVENT0_MIS_DIO6_CLR , true => INT_EVENT0_MIS_DIO6_A :: INT_EVENT0_MIS_DIO6_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio6_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO6_A :: INT_EVENT0_MIS_DIO6_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio6_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO6_A :: INT_EVENT0_MIS_DIO6_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO7` reader - DIO7 event"]
pub type INT_EVENT0_MIS_DIO7_R = crate :: BitReader < INT_EVENT0_MIS_DIO7_A > ; # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO7_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO7_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO7_SET = 1 , } impl From < INT_EVENT0_MIS_DIO7_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO7_A { match self . bits { false => INT_EVENT0_MIS_DIO7_A :: INT_EVENT0_MIS_DIO7_CLR , true => INT_EVENT0_MIS_DIO7_A :: INT_EVENT0_MIS_DIO7_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio7_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO7_A :: INT_EVENT0_MIS_DIO7_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio7_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO7_A :: INT_EVENT0_MIS_DIO7_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO8` reader - DIO8 event"]
pub type INT_EVENT0_MIS_DIO8_R = crate :: BitReader < INT_EVENT0_MIS_DIO8_A > ; # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO8_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO8_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO8_SET = 1 , } impl From < INT_EVENT0_MIS_DIO8_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO8_A { match self . bits { false => INT_EVENT0_MIS_DIO8_A :: INT_EVENT0_MIS_DIO8_CLR , true => INT_EVENT0_MIS_DIO8_A :: INT_EVENT0_MIS_DIO8_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio8_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO8_A :: INT_EVENT0_MIS_DIO8_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio8_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO8_A :: INT_EVENT0_MIS_DIO8_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO9` reader - DIO9 event"]
pub type INT_EVENT0_MIS_DIO9_R = crate :: BitReader < INT_EVENT0_MIS_DIO9_A > ; # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO9_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO9_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO9_SET = 1 , } impl From < INT_EVENT0_MIS_DIO9_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO9_A { match self . bits { false => INT_EVENT0_MIS_DIO9_A :: INT_EVENT0_MIS_DIO9_CLR , true => INT_EVENT0_MIS_DIO9_A :: INT_EVENT0_MIS_DIO9_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio9_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO9_A :: INT_EVENT0_MIS_DIO9_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio9_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO9_A :: INT_EVENT0_MIS_DIO9_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO10` reader - DIO10 event"]
pub type INT_EVENT0_MIS_DIO10_R = crate :: BitReader < INT_EVENT0_MIS_DIO10_A > ; # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO10_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO10_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO10_SET = 1 , } impl From < INT_EVENT0_MIS_DIO10_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO10_A { match self . bits { false => INT_EVENT0_MIS_DIO10_A :: INT_EVENT0_MIS_DIO10_CLR , true => INT_EVENT0_MIS_DIO10_A :: INT_EVENT0_MIS_DIO10_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio10_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO10_A :: INT_EVENT0_MIS_DIO10_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio10_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO10_A :: INT_EVENT0_MIS_DIO10_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO11` reader - DIO11 event"]
pub type INT_EVENT0_MIS_DIO11_R = crate :: BitReader < INT_EVENT0_MIS_DIO11_A > ; # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO11_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO11_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO11_SET = 1 , } impl From < INT_EVENT0_MIS_DIO11_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO11_A { match self . bits { false => INT_EVENT0_MIS_DIO11_A :: INT_EVENT0_MIS_DIO11_CLR , true => INT_EVENT0_MIS_DIO11_A :: INT_EVENT0_MIS_DIO11_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio11_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO11_A :: INT_EVENT0_MIS_DIO11_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio11_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO11_A :: INT_EVENT0_MIS_DIO11_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO12` reader - DIO12 event"]
pub type INT_EVENT0_MIS_DIO12_R = crate :: BitReader < INT_EVENT0_MIS_DIO12_A > ; # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO12_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO12_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO12_SET = 1 , } impl From < INT_EVENT0_MIS_DIO12_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO12_A { match self . bits { false => INT_EVENT0_MIS_DIO12_A :: INT_EVENT0_MIS_DIO12_CLR , true => INT_EVENT0_MIS_DIO12_A :: INT_EVENT0_MIS_DIO12_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio12_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO12_A :: INT_EVENT0_MIS_DIO12_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio12_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO12_A :: INT_EVENT0_MIS_DIO12_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO13` reader - DIO13 event"]
pub type INT_EVENT0_MIS_DIO13_R = crate :: BitReader < INT_EVENT0_MIS_DIO13_A > ; # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO13_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO13_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO13_SET = 1 , } impl From < INT_EVENT0_MIS_DIO13_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO13_A { match self . bits { false => INT_EVENT0_MIS_DIO13_A :: INT_EVENT0_MIS_DIO13_CLR , true => INT_EVENT0_MIS_DIO13_A :: INT_EVENT0_MIS_DIO13_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio13_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO13_A :: INT_EVENT0_MIS_DIO13_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio13_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO13_A :: INT_EVENT0_MIS_DIO13_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO14` reader - DIO14 event"]
pub type INT_EVENT0_MIS_DIO14_R = crate :: BitReader < INT_EVENT0_MIS_DIO14_A > ; # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO14_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO14_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO14_SET = 1 , } impl From < INT_EVENT0_MIS_DIO14_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO14_A { match self . bits { false => INT_EVENT0_MIS_DIO14_A :: INT_EVENT0_MIS_DIO14_CLR , true => INT_EVENT0_MIS_DIO14_A :: INT_EVENT0_MIS_DIO14_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio14_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO14_A :: INT_EVENT0_MIS_DIO14_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio14_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO14_A :: INT_EVENT0_MIS_DIO14_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO15` reader - DIO15 event"]
pub type INT_EVENT0_MIS_DIO15_R = crate :: BitReader < INT_EVENT0_MIS_DIO15_A > ; # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO15_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO15_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO15_SET = 1 , } impl From < INT_EVENT0_MIS_DIO15_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO15_A { match self . bits { false => INT_EVENT0_MIS_DIO15_A :: INT_EVENT0_MIS_DIO15_CLR , true => INT_EVENT0_MIS_DIO15_A :: INT_EVENT0_MIS_DIO15_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio15_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO15_A :: INT_EVENT0_MIS_DIO15_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio15_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO15_A :: INT_EVENT0_MIS_DIO15_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO16` reader - DIO16 event"]
pub type INT_EVENT0_MIS_DIO16_R = crate :: BitReader < INT_EVENT0_MIS_DIO16_A > ; # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO16_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO16_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO16_SET = 1 , } impl From < INT_EVENT0_MIS_DIO16_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO16_A { match self . bits { false => INT_EVENT0_MIS_DIO16_A :: INT_EVENT0_MIS_DIO16_CLR , true => INT_EVENT0_MIS_DIO16_A :: INT_EVENT0_MIS_DIO16_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio16_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO16_A :: INT_EVENT0_MIS_DIO16_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio16_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO16_A :: INT_EVENT0_MIS_DIO16_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO17` reader - DIO17 event"]
pub type INT_EVENT0_MIS_DIO17_R = crate :: BitReader < INT_EVENT0_MIS_DIO17_A > ; # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO17_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO17_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO17_SET = 1 , } impl From < INT_EVENT0_MIS_DIO17_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO17_A { match self . bits { false => INT_EVENT0_MIS_DIO17_A :: INT_EVENT0_MIS_DIO17_CLR , true => INT_EVENT0_MIS_DIO17_A :: INT_EVENT0_MIS_DIO17_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio17_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO17_A :: INT_EVENT0_MIS_DIO17_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio17_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO17_A :: INT_EVENT0_MIS_DIO17_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO18` reader - DIO18 event"]
pub type INT_EVENT0_MIS_DIO18_R = crate :: BitReader < INT_EVENT0_MIS_DIO18_A > ; # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO18_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO18_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO18_SET = 1 , } impl From < INT_EVENT0_MIS_DIO18_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO18_A { match self . bits { false => INT_EVENT0_MIS_DIO18_A :: INT_EVENT0_MIS_DIO18_CLR , true => INT_EVENT0_MIS_DIO18_A :: INT_EVENT0_MIS_DIO18_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio18_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO18_A :: INT_EVENT0_MIS_DIO18_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio18_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO18_A :: INT_EVENT0_MIS_DIO18_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO19` reader - DIO19 event"]
pub type INT_EVENT0_MIS_DIO19_R = crate :: BitReader < INT_EVENT0_MIS_DIO19_A > ; # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO19_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO19_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO19_SET = 1 , } impl From < INT_EVENT0_MIS_DIO19_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO19_A { match self . bits { false => INT_EVENT0_MIS_DIO19_A :: INT_EVENT0_MIS_DIO19_CLR , true => INT_EVENT0_MIS_DIO19_A :: INT_EVENT0_MIS_DIO19_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio19_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO19_A :: INT_EVENT0_MIS_DIO19_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio19_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO19_A :: INT_EVENT0_MIS_DIO19_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO20` reader - DIO20 event"]
pub type INT_EVENT0_MIS_DIO20_R = crate :: BitReader < INT_EVENT0_MIS_DIO20_A > ; # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO20_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO20_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO20_SET = 1 , } impl From < INT_EVENT0_MIS_DIO20_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO20_A { match self . bits { false => INT_EVENT0_MIS_DIO20_A :: INT_EVENT0_MIS_DIO20_CLR , true => INT_EVENT0_MIS_DIO20_A :: INT_EVENT0_MIS_DIO20_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio20_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO20_A :: INT_EVENT0_MIS_DIO20_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio20_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO20_A :: INT_EVENT0_MIS_DIO20_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO21` reader - DIO21 event"]
pub type INT_EVENT0_MIS_DIO21_R = crate :: BitReader < INT_EVENT0_MIS_DIO21_A > ; # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO21_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO21_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO21_SET = 1 , } impl From < INT_EVENT0_MIS_DIO21_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO21_A { match self . bits { false => INT_EVENT0_MIS_DIO21_A :: INT_EVENT0_MIS_DIO21_CLR , true => INT_EVENT0_MIS_DIO21_A :: INT_EVENT0_MIS_DIO21_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio21_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO21_A :: INT_EVENT0_MIS_DIO21_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio21_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO21_A :: INT_EVENT0_MIS_DIO21_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO22` reader - DIO22 event"]
pub type INT_EVENT0_MIS_DIO22_R = crate :: BitReader < INT_EVENT0_MIS_DIO22_A > ; # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO22_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO22_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO22_SET = 1 , } impl From < INT_EVENT0_MIS_DIO22_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO22_A { match self . bits { false => INT_EVENT0_MIS_DIO22_A :: INT_EVENT0_MIS_DIO22_CLR , true => INT_EVENT0_MIS_DIO22_A :: INT_EVENT0_MIS_DIO22_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio22_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO22_A :: INT_EVENT0_MIS_DIO22_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio22_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO22_A :: INT_EVENT0_MIS_DIO22_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO23` reader - DIO23 event"]
pub type INT_EVENT0_MIS_DIO23_R = crate :: BitReader < INT_EVENT0_MIS_DIO23_A > ; # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO23_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO23_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO23_SET = 1 , } impl From < INT_EVENT0_MIS_DIO23_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO23_A { match self . bits { false => INT_EVENT0_MIS_DIO23_A :: INT_EVENT0_MIS_DIO23_CLR , true => INT_EVENT0_MIS_DIO23_A :: INT_EVENT0_MIS_DIO23_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio23_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO23_A :: INT_EVENT0_MIS_DIO23_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio23_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO23_A :: INT_EVENT0_MIS_DIO23_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO24` reader - DIO24 event"]
pub type INT_EVENT0_MIS_DIO24_R = crate :: BitReader < INT_EVENT0_MIS_DIO24_A > ; # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO24_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO24_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO24_SET = 1 , } impl From < INT_EVENT0_MIS_DIO24_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO24_A { match self . bits { false => INT_EVENT0_MIS_DIO24_A :: INT_EVENT0_MIS_DIO24_CLR , true => INT_EVENT0_MIS_DIO24_A :: INT_EVENT0_MIS_DIO24_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio24_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO24_A :: INT_EVENT0_MIS_DIO24_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio24_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO24_A :: INT_EVENT0_MIS_DIO24_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO25` reader - DIO25 event"]
pub type INT_EVENT0_MIS_DIO25_R = crate :: BitReader < INT_EVENT0_MIS_DIO25_A > ; # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO25_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO25_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO25_SET = 1 , } impl From < INT_EVENT0_MIS_DIO25_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO25_A { match self . bits { false => INT_EVENT0_MIS_DIO25_A :: INT_EVENT0_MIS_DIO25_CLR , true => INT_EVENT0_MIS_DIO25_A :: INT_EVENT0_MIS_DIO25_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio25_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO25_A :: INT_EVENT0_MIS_DIO25_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio25_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO25_A :: INT_EVENT0_MIS_DIO25_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO26` reader - DIO26 event"]
pub type INT_EVENT0_MIS_DIO26_R = crate :: BitReader < INT_EVENT0_MIS_DIO26_A > ; # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO26_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO26_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO26_SET = 1 , } impl From < INT_EVENT0_MIS_DIO26_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO26_A { match self . bits { false => INT_EVENT0_MIS_DIO26_A :: INT_EVENT0_MIS_DIO26_CLR , true => INT_EVENT0_MIS_DIO26_A :: INT_EVENT0_MIS_DIO26_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio26_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO26_A :: INT_EVENT0_MIS_DIO26_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio26_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO26_A :: INT_EVENT0_MIS_DIO26_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO27` reader - DIO27 event"]
pub type INT_EVENT0_MIS_DIO27_R = crate :: BitReader < INT_EVENT0_MIS_DIO27_A > ; # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO27_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO27_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO27_SET = 1 , } impl From < INT_EVENT0_MIS_DIO27_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO27_A { match self . bits { false => INT_EVENT0_MIS_DIO27_A :: INT_EVENT0_MIS_DIO27_CLR , true => INT_EVENT0_MIS_DIO27_A :: INT_EVENT0_MIS_DIO27_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio27_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO27_A :: INT_EVENT0_MIS_DIO27_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio27_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO27_A :: INT_EVENT0_MIS_DIO27_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO28` reader - DIO28 event"]
pub type INT_EVENT0_MIS_DIO28_R = crate :: BitReader < INT_EVENT0_MIS_DIO28_A > ; # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO28_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO28_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO28_SET = 1 , } impl From < INT_EVENT0_MIS_DIO28_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO28_A { match self . bits { false => INT_EVENT0_MIS_DIO28_A :: INT_EVENT0_MIS_DIO28_CLR , true => INT_EVENT0_MIS_DIO28_A :: INT_EVENT0_MIS_DIO28_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio28_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO28_A :: INT_EVENT0_MIS_DIO28_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio28_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO28_A :: INT_EVENT0_MIS_DIO28_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO29` reader - DIO29 event"]
pub type INT_EVENT0_MIS_DIO29_R = crate :: BitReader < INT_EVENT0_MIS_DIO29_A > ; # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO29_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO29_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO29_SET = 1 , } impl From < INT_EVENT0_MIS_DIO29_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO29_A { match self . bits { false => INT_EVENT0_MIS_DIO29_A :: INT_EVENT0_MIS_DIO29_CLR , true => INT_EVENT0_MIS_DIO29_A :: INT_EVENT0_MIS_DIO29_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio29_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO29_A :: INT_EVENT0_MIS_DIO29_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio29_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO29_A :: INT_EVENT0_MIS_DIO29_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO30` reader - DIO30 event"]
pub type INT_EVENT0_MIS_DIO30_R = crate :: BitReader < INT_EVENT0_MIS_DIO30_A > ; # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO30_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO30_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO30_SET = 1 , } impl From < INT_EVENT0_MIS_DIO30_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO30_A { match self . bits { false => INT_EVENT0_MIS_DIO30_A :: INT_EVENT0_MIS_DIO30_CLR , true => INT_EVENT0_MIS_DIO30_A :: INT_EVENT0_MIS_DIO30_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio30_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO30_A :: INT_EVENT0_MIS_DIO30_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio30_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO30_A :: INT_EVENT0_MIS_DIO30_SET } } # [doc = "Field `INT_EVENT0_MIS_DIO31` reader - DIO31 event"]
pub type INT_EVENT0_MIS_DIO31_R = crate :: BitReader < INT_EVENT0_MIS_DIO31_A > ; # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DIO31_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DIO31_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DIO31_SET = 1 , } impl From < INT_EVENT0_MIS_DIO31_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DIO31_A { match self . bits { false => INT_EVENT0_MIS_DIO31_A :: INT_EVENT0_MIS_DIO31_CLR , true => INT_EVENT0_MIS_DIO31_A :: INT_EVENT0_MIS_DIO31_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dio31_clr (& self) -> bool { * self == INT_EVENT0_MIS_DIO31_A :: INT_EVENT0_MIS_DIO31_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dio31_set (& self) -> bool { * self == INT_EVENT0_MIS_DIO31_A :: INT_EVENT0_MIS_DIO31_SET } } impl R { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
pub fn int_event0_mis_dio0 (& self) -> INT_EVENT0_MIS_DIO0_R { INT_EVENT0_MIS_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
pub fn int_event0_mis_dio1 (& self) -> INT_EVENT0_MIS_DIO1_R { INT_EVENT0_MIS_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
pub fn int_event0_mis_dio2 (& self) -> INT_EVENT0_MIS_DIO2_R { INT_EVENT0_MIS_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
pub fn int_event0_mis_dio3 (& self) -> INT_EVENT0_MIS_DIO3_R { INT_EVENT0_MIS_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
pub fn int_event0_mis_dio4 (& self) -> INT_EVENT0_MIS_DIO4_R { INT_EVENT0_MIS_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
pub fn int_event0_mis_dio5 (& self) -> INT_EVENT0_MIS_DIO5_R { INT_EVENT0_MIS_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
pub fn int_event0_mis_dio6 (& self) -> INT_EVENT0_MIS_DIO6_R { INT_EVENT0_MIS_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
pub fn int_event0_mis_dio7 (& self) -> INT_EVENT0_MIS_DIO7_R { INT_EVENT0_MIS_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
pub fn int_event0_mis_dio8 (& self) -> INT_EVENT0_MIS_DIO8_R { INT_EVENT0_MIS_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
pub fn int_event0_mis_dio9 (& self) -> INT_EVENT0_MIS_DIO9_R { INT_EVENT0_MIS_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
pub fn int_event0_mis_dio10 (& self) -> INT_EVENT0_MIS_DIO10_R { INT_EVENT0_MIS_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
pub fn int_event0_mis_dio11 (& self) -> INT_EVENT0_MIS_DIO11_R { INT_EVENT0_MIS_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
pub fn int_event0_mis_dio12 (& self) -> INT_EVENT0_MIS_DIO12_R { INT_EVENT0_MIS_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
pub fn int_event0_mis_dio13 (& self) -> INT_EVENT0_MIS_DIO13_R { INT_EVENT0_MIS_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
pub fn int_event0_mis_dio14 (& self) -> INT_EVENT0_MIS_DIO14_R { INT_EVENT0_MIS_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
pub fn int_event0_mis_dio15 (& self) -> INT_EVENT0_MIS_DIO15_R { INT_EVENT0_MIS_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
pub fn int_event0_mis_dio16 (& self) -> INT_EVENT0_MIS_DIO16_R { INT_EVENT0_MIS_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
pub fn int_event0_mis_dio17 (& self) -> INT_EVENT0_MIS_DIO17_R { INT_EVENT0_MIS_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
pub fn int_event0_mis_dio18 (& self) -> INT_EVENT0_MIS_DIO18_R { INT_EVENT0_MIS_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
pub fn int_event0_mis_dio19 (& self) -> INT_EVENT0_MIS_DIO19_R { INT_EVENT0_MIS_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
pub fn int_event0_mis_dio20 (& self) -> INT_EVENT0_MIS_DIO20_R { INT_EVENT0_MIS_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
pub fn int_event0_mis_dio21 (& self) -> INT_EVENT0_MIS_DIO21_R { INT_EVENT0_MIS_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
pub fn int_event0_mis_dio22 (& self) -> INT_EVENT0_MIS_DIO22_R { INT_EVENT0_MIS_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
pub fn int_event0_mis_dio23 (& self) -> INT_EVENT0_MIS_DIO23_R { INT_EVENT0_MIS_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
pub fn int_event0_mis_dio24 (& self) -> INT_EVENT0_MIS_DIO24_R { INT_EVENT0_MIS_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
pub fn int_event0_mis_dio25 (& self) -> INT_EVENT0_MIS_DIO25_R { INT_EVENT0_MIS_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
pub fn int_event0_mis_dio26 (& self) -> INT_EVENT0_MIS_DIO26_R { INT_EVENT0_MIS_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
pub fn int_event0_mis_dio27 (& self) -> INT_EVENT0_MIS_DIO27_R { INT_EVENT0_MIS_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
pub fn int_event0_mis_dio28 (& self) -> INT_EVENT0_MIS_DIO28_R { INT_EVENT0_MIS_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
pub fn int_event0_mis_dio29 (& self) -> INT_EVENT0_MIS_DIO29_R { INT_EVENT0_MIS_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
pub fn int_event0_mis_dio30 (& self) -> INT_EVENT0_MIS_DIO30_R { INT_EVENT0_MIS_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
pub fn int_event0_mis_dio31 (& self) -> INT_EVENT0_MIS_DIO31_R { INT_EVENT0_MIS_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_MIS to value 0"]
impl crate :: Resettable for INT_EVENT0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iset`]
module"]
pub type INT_EVENT0_ISET = crate :: Reg < int_event0_iset :: INT_EVENT0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event0_iset { # [doc = "Register `INT_EVENT0_ISET` writer"]
pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO0_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO0_SET = 1 , } impl From < INT_EVENT0_ISET_DIO0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO0` writer - DIO0 event"]
pub type INT_EVENT0_ISET_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO0_AW :: INT_EVENT0_ISET_DIO0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO0_AW :: INT_EVENT0_ISET_DIO0_SET) } } # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO1_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO1_SET = 1 , } impl From < INT_EVENT0_ISET_DIO1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO1` writer - DIO1 event"]
pub type INT_EVENT0_ISET_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO1_AW :: INT_EVENT0_ISET_DIO1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO1_AW :: INT_EVENT0_ISET_DIO1_SET) } } # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO2_SET = 1 , } impl From < INT_EVENT0_ISET_DIO2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO2` writer - DIO2 event"]
pub type INT_EVENT0_ISET_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO2_AW :: INT_EVENT0_ISET_DIO2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO2_AW :: INT_EVENT0_ISET_DIO2_SET) } } # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO3_SET = 1 , } impl From < INT_EVENT0_ISET_DIO3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO3` writer - DIO3 event"]
pub type INT_EVENT0_ISET_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO3_AW :: INT_EVENT0_ISET_DIO3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO3_AW :: INT_EVENT0_ISET_DIO3_SET) } } # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO4_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO4_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO4_SET = 1 , } impl From < INT_EVENT0_ISET_DIO4_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO4` writer - DIO4 event"]
pub type INT_EVENT0_ISET_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO4_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO4_AW :: INT_EVENT0_ISET_DIO4_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO4_AW :: INT_EVENT0_ISET_DIO4_SET) } } # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO5_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO5_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO5_SET = 1 , } impl From < INT_EVENT0_ISET_DIO5_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO5` writer - DIO5 event"]
pub type INT_EVENT0_ISET_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO5_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO5_AW :: INT_EVENT0_ISET_DIO5_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO5_AW :: INT_EVENT0_ISET_DIO5_SET) } } # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO6_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO6_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO6_SET = 1 , } impl From < INT_EVENT0_ISET_DIO6_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO6` writer - DIO6 event"]
pub type INT_EVENT0_ISET_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO6_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO6_AW :: INT_EVENT0_ISET_DIO6_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO6_AW :: INT_EVENT0_ISET_DIO6_SET) } } # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO7_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO7_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO7_SET = 1 , } impl From < INT_EVENT0_ISET_DIO7_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO7` writer - DIO7 event"]
pub type INT_EVENT0_ISET_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO7_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO7_AW :: INT_EVENT0_ISET_DIO7_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO7_AW :: INT_EVENT0_ISET_DIO7_SET) } } # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO8_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO8_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO8_SET = 1 , } impl From < INT_EVENT0_ISET_DIO8_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO8` writer - DIO8 event"]
pub type INT_EVENT0_ISET_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO8_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO8_AW :: INT_EVENT0_ISET_DIO8_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO8_AW :: INT_EVENT0_ISET_DIO8_SET) } } # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO9_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO9_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO9_SET = 1 , } impl From < INT_EVENT0_ISET_DIO9_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO9` writer - DIO9 event"]
pub type INT_EVENT0_ISET_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO9_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO9_AW :: INT_EVENT0_ISET_DIO9_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO9_AW :: INT_EVENT0_ISET_DIO9_SET) } } # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO10_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO10_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO10_SET = 1 , } impl From < INT_EVENT0_ISET_DIO10_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO10` writer - DIO10 event"]
pub type INT_EVENT0_ISET_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO10_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO10_AW :: INT_EVENT0_ISET_DIO10_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO10_AW :: INT_EVENT0_ISET_DIO10_SET) } } # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO11_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO11_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO11_SET = 1 , } impl From < INT_EVENT0_ISET_DIO11_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO11` writer - DIO11 event"]
pub type INT_EVENT0_ISET_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO11_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO11_AW :: INT_EVENT0_ISET_DIO11_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO11_AW :: INT_EVENT0_ISET_DIO11_SET) } } # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO12_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO12_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO12_SET = 1 , } impl From < INT_EVENT0_ISET_DIO12_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO12` writer - DIO12 event"]
pub type INT_EVENT0_ISET_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO12_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO12_AW :: INT_EVENT0_ISET_DIO12_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO12_AW :: INT_EVENT0_ISET_DIO12_SET) } } # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO13_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO13_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO13_SET = 1 , } impl From < INT_EVENT0_ISET_DIO13_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO13` writer - DIO13 event"]
pub type INT_EVENT0_ISET_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO13_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO13_AW :: INT_EVENT0_ISET_DIO13_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO13_AW :: INT_EVENT0_ISET_DIO13_SET) } } # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO14_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO14_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO14_SET = 1 , } impl From < INT_EVENT0_ISET_DIO14_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO14` writer - DIO14 event"]
pub type INT_EVENT0_ISET_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO14_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO14_AW :: INT_EVENT0_ISET_DIO14_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO14_AW :: INT_EVENT0_ISET_DIO14_SET) } } # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO15_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO15_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO15_SET = 1 , } impl From < INT_EVENT0_ISET_DIO15_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO15` writer - DIO15 event"]
pub type INT_EVENT0_ISET_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO15_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO15_AW :: INT_EVENT0_ISET_DIO15_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO15_AW :: INT_EVENT0_ISET_DIO15_SET) } } # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO16_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO16_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO16_SET = 1 , } impl From < INT_EVENT0_ISET_DIO16_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO16` writer - DIO16 event"]
pub type INT_EVENT0_ISET_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO16_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO16_AW :: INT_EVENT0_ISET_DIO16_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO16_AW :: INT_EVENT0_ISET_DIO16_SET) } } # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO17_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO17_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO17_SET = 1 , } impl From < INT_EVENT0_ISET_DIO17_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO17` writer - DIO17 event"]
pub type INT_EVENT0_ISET_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO17_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO17_AW :: INT_EVENT0_ISET_DIO17_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO17_AW :: INT_EVENT0_ISET_DIO17_SET) } } # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO18_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO18_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO18_SET = 1 , } impl From < INT_EVENT0_ISET_DIO18_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO18` writer - DIO18 event"]
pub type INT_EVENT0_ISET_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO18_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO18_AW :: INT_EVENT0_ISET_DIO18_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO18_AW :: INT_EVENT0_ISET_DIO18_SET) } } # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO19_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO19_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO19_SET = 1 , } impl From < INT_EVENT0_ISET_DIO19_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO19` writer - DIO19 event"]
pub type INT_EVENT0_ISET_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO19_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO19_AW :: INT_EVENT0_ISET_DIO19_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO19_AW :: INT_EVENT0_ISET_DIO19_SET) } } # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO20_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO20_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO20_SET = 1 , } impl From < INT_EVENT0_ISET_DIO20_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO20` writer - DIO20 event"]
pub type INT_EVENT0_ISET_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO20_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO20_AW :: INT_EVENT0_ISET_DIO20_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO20_AW :: INT_EVENT0_ISET_DIO20_SET) } } # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO21_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO21_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO21_SET = 1 , } impl From < INT_EVENT0_ISET_DIO21_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO21` writer - DIO21 event"]
pub type INT_EVENT0_ISET_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO21_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO21_AW :: INT_EVENT0_ISET_DIO21_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO21_AW :: INT_EVENT0_ISET_DIO21_SET) } } # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO22_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO22_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO22_SET = 1 , } impl From < INT_EVENT0_ISET_DIO22_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO22` writer - DIO22 event"]
pub type INT_EVENT0_ISET_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO22_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO22_AW :: INT_EVENT0_ISET_DIO22_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO22_AW :: INT_EVENT0_ISET_DIO22_SET) } } # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO23_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO23_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO23_SET = 1 , } impl From < INT_EVENT0_ISET_DIO23_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO23` writer - DIO23 event"]
pub type INT_EVENT0_ISET_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO23_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO23_AW :: INT_EVENT0_ISET_DIO23_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO23_AW :: INT_EVENT0_ISET_DIO23_SET) } } # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO24_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO24_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO24_SET = 1 , } impl From < INT_EVENT0_ISET_DIO24_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO24` writer - DIO24 event"]
pub type INT_EVENT0_ISET_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO24_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO24_AW :: INT_EVENT0_ISET_DIO24_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO24_AW :: INT_EVENT0_ISET_DIO24_SET) } } # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO25_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO25_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO25_SET = 1 , } impl From < INT_EVENT0_ISET_DIO25_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO25` writer - DIO25 event"]
pub type INT_EVENT0_ISET_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO25_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO25_AW :: INT_EVENT0_ISET_DIO25_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO25_AW :: INT_EVENT0_ISET_DIO25_SET) } } # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO26_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO26_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO26_SET = 1 , } impl From < INT_EVENT0_ISET_DIO26_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO26` writer - DIO26 event"]
pub type INT_EVENT0_ISET_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO26_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO26_AW :: INT_EVENT0_ISET_DIO26_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO26_AW :: INT_EVENT0_ISET_DIO26_SET) } } # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO27_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO27_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO27_SET = 1 , } impl From < INT_EVENT0_ISET_DIO27_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO27` writer - DIO27 event"]
pub type INT_EVENT0_ISET_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO27_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO27_AW :: INT_EVENT0_ISET_DIO27_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO27_AW :: INT_EVENT0_ISET_DIO27_SET) } } # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO28_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO28_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO28_SET = 1 , } impl From < INT_EVENT0_ISET_DIO28_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO28` writer - DIO28 event"]
pub type INT_EVENT0_ISET_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO28_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO28_AW :: INT_EVENT0_ISET_DIO28_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO28_AW :: INT_EVENT0_ISET_DIO28_SET) } } # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO29_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO29_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO29_SET = 1 , } impl From < INT_EVENT0_ISET_DIO29_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO29` writer - DIO29 event"]
pub type INT_EVENT0_ISET_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO29_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO29_AW :: INT_EVENT0_ISET_DIO29_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO29_AW :: INT_EVENT0_ISET_DIO29_SET) } } # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO30_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO30_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO30_SET = 1 , } impl From < INT_EVENT0_ISET_DIO30_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO30` writer - DIO30 event"]
pub type INT_EVENT0_ISET_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO30_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO30_AW :: INT_EVENT0_ISET_DIO30_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO30_AW :: INT_EVENT0_ISET_DIO30_SET) } } # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DIO31_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DIO31_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DIO31_SET = 1 , } impl From < INT_EVENT0_ISET_DIO31_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DIO31` writer - DIO31 event"]
pub type INT_EVENT0_ISET_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DIO31_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO31_AW :: INT_EVENT0_ISET_DIO31_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DIO31_AW :: INT_EVENT0_ISET_DIO31_SET) } } impl W { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio0 (& mut self) -> INT_EVENT0_ISET_DIO0_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio1 (& mut self) -> INT_EVENT0_ISET_DIO1_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio2 (& mut self) -> INT_EVENT0_ISET_DIO2_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio3 (& mut self) -> INT_EVENT0_ISET_DIO3_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio4 (& mut self) -> INT_EVENT0_ISET_DIO4_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio5 (& mut self) -> INT_EVENT0_ISET_DIO5_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio6 (& mut self) -> INT_EVENT0_ISET_DIO6_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio7 (& mut self) -> INT_EVENT0_ISET_DIO7_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio8 (& mut self) -> INT_EVENT0_ISET_DIO8_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio9 (& mut self) -> INT_EVENT0_ISET_DIO9_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio10 (& mut self) -> INT_EVENT0_ISET_DIO10_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio11 (& mut self) -> INT_EVENT0_ISET_DIO11_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio12 (& mut self) -> INT_EVENT0_ISET_DIO12_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio13 (& mut self) -> INT_EVENT0_ISET_DIO13_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio14 (& mut self) -> INT_EVENT0_ISET_DIO14_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio15 (& mut self) -> INT_EVENT0_ISET_DIO15_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio16 (& mut self) -> INT_EVENT0_ISET_DIO16_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio17 (& mut self) -> INT_EVENT0_ISET_DIO17_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio18 (& mut self) -> INT_EVENT0_ISET_DIO18_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio19 (& mut self) -> INT_EVENT0_ISET_DIO19_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio20 (& mut self) -> INT_EVENT0_ISET_DIO20_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio21 (& mut self) -> INT_EVENT0_ISET_DIO21_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio22 (& mut self) -> INT_EVENT0_ISET_DIO22_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio23 (& mut self) -> INT_EVENT0_ISET_DIO23_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio24 (& mut self) -> INT_EVENT0_ISET_DIO24_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio25 (& mut self) -> INT_EVENT0_ISET_DIO25_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio26 (& mut self) -> INT_EVENT0_ISET_DIO26_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio27 (& mut self) -> INT_EVENT0_ISET_DIO27_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio28 (& mut self) -> INT_EVENT0_ISET_DIO28_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio29 (& mut self) -> INT_EVENT0_ISET_DIO29_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio30 (& mut self) -> INT_EVENT0_ISET_DIO30_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dio31 (& mut self) -> INT_EVENT0_ISET_DIO31_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"]
impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iclr`]
module"]
pub type INT_EVENT0_ICLR = crate :: Reg < int_event0_iclr :: INT_EVENT0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event0_iclr { # [doc = "Register `INT_EVENT0_ICLR` writer"]
pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO0_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO0_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO0` writer - DIO0 event"]
pub type INT_EVENT0_ICLR_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO0_AW :: INT_EVENT0_ICLR_DIO0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO0_AW :: INT_EVENT0_ICLR_DIO0_CLR) } } # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO1_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO1_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO1` writer - DIO1 event"]
pub type INT_EVENT0_ICLR_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO1_AW :: INT_EVENT0_ICLR_DIO1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO1_AW :: INT_EVENT0_ICLR_DIO1_CLR) } } # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO2_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO2` writer - DIO2 event"]
pub type INT_EVENT0_ICLR_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO2_AW :: INT_EVENT0_ICLR_DIO2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO2_AW :: INT_EVENT0_ICLR_DIO2_CLR) } } # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO3_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO3` writer - DIO3 event"]
pub type INT_EVENT0_ICLR_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO3_AW :: INT_EVENT0_ICLR_DIO3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO3_AW :: INT_EVENT0_ICLR_DIO3_CLR) } } # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO4_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO4_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO4_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO4_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO4` writer - DIO4 event"]
pub type INT_EVENT0_ICLR_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO4_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO4_AW :: INT_EVENT0_ICLR_DIO4_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO4_AW :: INT_EVENT0_ICLR_DIO4_CLR) } } # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO5_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO5_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO5_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO5_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO5` writer - DIO5 event"]
pub type INT_EVENT0_ICLR_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO5_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO5_AW :: INT_EVENT0_ICLR_DIO5_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO5_AW :: INT_EVENT0_ICLR_DIO5_CLR) } } # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO6_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO6_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO6_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO6_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO6` writer - DIO6 event"]
pub type INT_EVENT0_ICLR_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO6_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO6_AW :: INT_EVENT0_ICLR_DIO6_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO6_AW :: INT_EVENT0_ICLR_DIO6_CLR) } } # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO7_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO7_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO7_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO7_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO7` writer - DIO7 event"]
pub type INT_EVENT0_ICLR_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO7_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO7_AW :: INT_EVENT0_ICLR_DIO7_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO7_AW :: INT_EVENT0_ICLR_DIO7_CLR) } } # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO8_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO8_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO8_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO8_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO8` writer - DIO8 event"]
pub type INT_EVENT0_ICLR_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO8_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO8_AW :: INT_EVENT0_ICLR_DIO8_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO8_AW :: INT_EVENT0_ICLR_DIO8_CLR) } } # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO9_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO9_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO9_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO9_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO9` writer - DIO9 event"]
pub type INT_EVENT0_ICLR_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO9_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO9_AW :: INT_EVENT0_ICLR_DIO9_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO9_AW :: INT_EVENT0_ICLR_DIO9_CLR) } } # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO10_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO10_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO10_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO10_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO10` writer - DIO10 event"]
pub type INT_EVENT0_ICLR_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO10_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO10_AW :: INT_EVENT0_ICLR_DIO10_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO10_AW :: INT_EVENT0_ICLR_DIO10_CLR) } } # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO11_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO11_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO11_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO11_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO11` writer - DIO11 event"]
pub type INT_EVENT0_ICLR_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO11_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO11_AW :: INT_EVENT0_ICLR_DIO11_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO11_AW :: INT_EVENT0_ICLR_DIO11_CLR) } } # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO12_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO12_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO12_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO12_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO12` writer - DIO12 event"]
pub type INT_EVENT0_ICLR_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO12_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO12_AW :: INT_EVENT0_ICLR_DIO12_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO12_AW :: INT_EVENT0_ICLR_DIO12_CLR) } } # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO13_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO13_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO13_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO13_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO13` writer - DIO13 event"]
pub type INT_EVENT0_ICLR_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO13_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO13_AW :: INT_EVENT0_ICLR_DIO13_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO13_AW :: INT_EVENT0_ICLR_DIO13_CLR) } } # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO14_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO14_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO14_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO14_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO14` writer - DIO14 event"]
pub type INT_EVENT0_ICLR_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO14_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO14_AW :: INT_EVENT0_ICLR_DIO14_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO14_AW :: INT_EVENT0_ICLR_DIO14_CLR) } } # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO15_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO15_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO15_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO15_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO15` writer - DIO15 event"]
pub type INT_EVENT0_ICLR_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO15_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO15_AW :: INT_EVENT0_ICLR_DIO15_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO15_AW :: INT_EVENT0_ICLR_DIO15_CLR) } } # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO16_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO16_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO16_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO16_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO16` writer - DIO16 event"]
pub type INT_EVENT0_ICLR_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO16_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO16_AW :: INT_EVENT0_ICLR_DIO16_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO16_AW :: INT_EVENT0_ICLR_DIO16_CLR) } } # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO17_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO17_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO17_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO17_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO17` writer - DIO17 event"]
pub type INT_EVENT0_ICLR_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO17_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO17_AW :: INT_EVENT0_ICLR_DIO17_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO17_AW :: INT_EVENT0_ICLR_DIO17_CLR) } } # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO18_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO18_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO18_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO18_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO18` writer - DIO18 event"]
pub type INT_EVENT0_ICLR_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO18_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO18_AW :: INT_EVENT0_ICLR_DIO18_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO18_AW :: INT_EVENT0_ICLR_DIO18_CLR) } } # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO19_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO19_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO19_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO19_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO19` writer - DIO19 event"]
pub type INT_EVENT0_ICLR_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO19_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO19_AW :: INT_EVENT0_ICLR_DIO19_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO19_AW :: INT_EVENT0_ICLR_DIO19_CLR) } } # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO20_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO20_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO20_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO20_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO20` writer - DIO20 event"]
pub type INT_EVENT0_ICLR_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO20_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO20_AW :: INT_EVENT0_ICLR_DIO20_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO20_AW :: INT_EVENT0_ICLR_DIO20_CLR) } } # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO21_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO21_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO21_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO21_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO21` writer - DIO21 event"]
pub type INT_EVENT0_ICLR_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO21_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO21_AW :: INT_EVENT0_ICLR_DIO21_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO21_AW :: INT_EVENT0_ICLR_DIO21_CLR) } } # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO22_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO22_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO22_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO22_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO22` writer - DIO22 event"]
pub type INT_EVENT0_ICLR_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO22_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO22_AW :: INT_EVENT0_ICLR_DIO22_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO22_AW :: INT_EVENT0_ICLR_DIO22_CLR) } } # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO23_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO23_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO23_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO23_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO23` writer - DIO23 event"]
pub type INT_EVENT0_ICLR_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO23_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO23_AW :: INT_EVENT0_ICLR_DIO23_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO23_AW :: INT_EVENT0_ICLR_DIO23_CLR) } } # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO24_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO24_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO24_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO24_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO24` writer - DIO24 event"]
pub type INT_EVENT0_ICLR_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO24_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO24_AW :: INT_EVENT0_ICLR_DIO24_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO24_AW :: INT_EVENT0_ICLR_DIO24_CLR) } } # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO25_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO25_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO25_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO25_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO25` writer - DIO25 event"]
pub type INT_EVENT0_ICLR_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO25_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO25_AW :: INT_EVENT0_ICLR_DIO25_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO25_AW :: INT_EVENT0_ICLR_DIO25_CLR) } } # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO26_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO26_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO26_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO26_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO26` writer - DIO26 event"]
pub type INT_EVENT0_ICLR_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO26_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO26_AW :: INT_EVENT0_ICLR_DIO26_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO26_AW :: INT_EVENT0_ICLR_DIO26_CLR) } } # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO27_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO27_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO27_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO27_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO27` writer - DIO27 event"]
pub type INT_EVENT0_ICLR_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO27_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO27_AW :: INT_EVENT0_ICLR_DIO27_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO27_AW :: INT_EVENT0_ICLR_DIO27_CLR) } } # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO28_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO28_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO28_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO28_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO28` writer - DIO28 event"]
pub type INT_EVENT0_ICLR_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO28_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO28_AW :: INT_EVENT0_ICLR_DIO28_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO28_AW :: INT_EVENT0_ICLR_DIO28_CLR) } } # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO29_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO29_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO29_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO29_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO29` writer - DIO29 event"]
pub type INT_EVENT0_ICLR_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO29_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO29_AW :: INT_EVENT0_ICLR_DIO29_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO29_AW :: INT_EVENT0_ICLR_DIO29_CLR) } } # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO30_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO30_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO30_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO30_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO30` writer - DIO30 event"]
pub type INT_EVENT0_ICLR_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO30_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO30_AW :: INT_EVENT0_ICLR_DIO30_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO30_AW :: INT_EVENT0_ICLR_DIO30_CLR) } } # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DIO31_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DIO31_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DIO31_CLR = 1 , } impl From < INT_EVENT0_ICLR_DIO31_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DIO31` writer - DIO31 event"]
pub type INT_EVENT0_ICLR_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DIO31_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO31_AW :: INT_EVENT0_ICLR_DIO31_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DIO31_AW :: INT_EVENT0_ICLR_DIO31_CLR) } } impl W { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio0 (& mut self) -> INT_EVENT0_ICLR_DIO0_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio1 (& mut self) -> INT_EVENT0_ICLR_DIO1_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio2 (& mut self) -> INT_EVENT0_ICLR_DIO2_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio3 (& mut self) -> INT_EVENT0_ICLR_DIO3_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio4 (& mut self) -> INT_EVENT0_ICLR_DIO4_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio5 (& mut self) -> INT_EVENT0_ICLR_DIO5_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio6 (& mut self) -> INT_EVENT0_ICLR_DIO6_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio7 (& mut self) -> INT_EVENT0_ICLR_DIO7_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio8 (& mut self) -> INT_EVENT0_ICLR_DIO8_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio9 (& mut self) -> INT_EVENT0_ICLR_DIO9_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio10 (& mut self) -> INT_EVENT0_ICLR_DIO10_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio11 (& mut self) -> INT_EVENT0_ICLR_DIO11_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio12 (& mut self) -> INT_EVENT0_ICLR_DIO12_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio13 (& mut self) -> INT_EVENT0_ICLR_DIO13_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio14 (& mut self) -> INT_EVENT0_ICLR_DIO14_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio15 (& mut self) -> INT_EVENT0_ICLR_DIO15_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DIO15_W :: new (self) } # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio16 (& mut self) -> INT_EVENT0_ICLR_DIO16_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio17 (& mut self) -> INT_EVENT0_ICLR_DIO17_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio18 (& mut self) -> INT_EVENT0_ICLR_DIO18_W < INT_EVENT0_ICLR_SPEC , 18 > { INT_EVENT0_ICLR_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio19 (& mut self) -> INT_EVENT0_ICLR_DIO19_W < INT_EVENT0_ICLR_SPEC , 19 > { INT_EVENT0_ICLR_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio20 (& mut self) -> INT_EVENT0_ICLR_DIO20_W < INT_EVENT0_ICLR_SPEC , 20 > { INT_EVENT0_ICLR_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio21 (& mut self) -> INT_EVENT0_ICLR_DIO21_W < INT_EVENT0_ICLR_SPEC , 21 > { INT_EVENT0_ICLR_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio22 (& mut self) -> INT_EVENT0_ICLR_DIO22_W < INT_EVENT0_ICLR_SPEC , 22 > { INT_EVENT0_ICLR_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio23 (& mut self) -> INT_EVENT0_ICLR_DIO23_W < INT_EVENT0_ICLR_SPEC , 23 > { INT_EVENT0_ICLR_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio24 (& mut self) -> INT_EVENT0_ICLR_DIO24_W < INT_EVENT0_ICLR_SPEC , 24 > { INT_EVENT0_ICLR_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio25 (& mut self) -> INT_EVENT0_ICLR_DIO25_W < INT_EVENT0_ICLR_SPEC , 25 > { INT_EVENT0_ICLR_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio26 (& mut self) -> INT_EVENT0_ICLR_DIO26_W < INT_EVENT0_ICLR_SPEC , 26 > { INT_EVENT0_ICLR_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio27 (& mut self) -> INT_EVENT0_ICLR_DIO27_W < INT_EVENT0_ICLR_SPEC , 27 > { INT_EVENT0_ICLR_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio28 (& mut self) -> INT_EVENT0_ICLR_DIO28_W < INT_EVENT0_ICLR_SPEC , 28 > { INT_EVENT0_ICLR_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio29 (& mut self) -> INT_EVENT0_ICLR_DIO29_W < INT_EVENT0_ICLR_SPEC , 29 > { INT_EVENT0_ICLR_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio30 (& mut self) -> INT_EVENT0_ICLR_DIO30_W < INT_EVENT0_ICLR_SPEC , 30 > { INT_EVENT0_ICLR_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dio31 (& mut self) -> INT_EVENT0_ICLR_DIO31_W < INT_EVENT0_ICLR_SPEC , 31 > { INT_EVENT0_ICLR_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iidx`]
module"]
pub type INT_EVENT1_IIDX = crate :: Reg < int_event1_iidx :: INT_EVENT1_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event1_iidx { # [doc = "Register `INT_EVENT1_IIDX` reader"]
pub type R = crate :: R < INT_EVENT1_IIDX_SPEC > ; # [doc = "Field `INT_EVENT1_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT1_IIDX_STAT_R = crate :: FieldReader < INT_EVENT1_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT1_IIDX_STAT_NO_INTR = 0 , # [doc = "1: DIO0"]
INT_EVENT1_IIDX_STAT_DIO0 = 1 , # [doc = "2: DIO1"]
INT_EVENT1_IIDX_STAT_DIO1 = 2 , # [doc = "3: DIO2"]
INT_EVENT1_IIDX_STAT_DIO2 = 3 , # [doc = "4: DIO3"]
INT_EVENT1_IIDX_STAT_DIO3 = 4 , # [doc = "5: DIO4"]
INT_EVENT1_IIDX_STAT_DIO4 = 5 , # [doc = "6: DIO5"]
INT_EVENT1_IIDX_STAT_DIO5 = 6 , # [doc = "7: DIO6"]
INT_EVENT1_IIDX_STAT_DIO6 = 7 , # [doc = "8: DIO7"]
INT_EVENT1_IIDX_STAT_DIO7 = 8 , # [doc = "9: DIO8"]
INT_EVENT1_IIDX_STAT_DIO8 = 9 , # [doc = "10: DIO9"]
INT_EVENT1_IIDX_STAT_DIO9 = 10 , # [doc = "11: DIO10"]
INT_EVENT1_IIDX_STAT_DIO10 = 11 , # [doc = "12: DIO11"]
INT_EVENT1_IIDX_STAT_DIO11 = 12 , # [doc = "13: DIO12"]
INT_EVENT1_IIDX_STAT_DIO12 = 13 , # [doc = "14: DIO13"]
INT_EVENT1_IIDX_STAT_DIO13 = 14 , # [doc = "15: DIO14"]
INT_EVENT1_IIDX_STAT_DIO14 = 15 , # [doc = "16: DIO15"]
INT_EVENT1_IIDX_STAT_DIO15 = 16 , } impl From < INT_EVENT1_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT1_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO0) , 2 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO1) , 3 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO2) , 4 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO3) , 5 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO4) , 6 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO5) , 7 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO6) , 8 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO7) , 9 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO8) , 10 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO9) , 11 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO10) , 12 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO11) , 13 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO12) , 14 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO13) , 15 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO14) , 16 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO15) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR } # [doc = "DIO0"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio0 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO0 } # [doc = "DIO1"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio1 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO1 } # [doc = "DIO2"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio2 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO2 } # [doc = "DIO3"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio3 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO3 } # [doc = "DIO4"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio4 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO4 } # [doc = "DIO5"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio5 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO5 } # [doc = "DIO6"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio6 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO6 } # [doc = "DIO7"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio7 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO7 } # [doc = "DIO8"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio8 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO8 } # [doc = "DIO9"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio9 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO9 } # [doc = "DIO10"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio10 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO10 } # [doc = "DIO11"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio11 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO11 } # [doc = "DIO12"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio12 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO12 } # [doc = "DIO13"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio13 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO13 } # [doc = "DIO14"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio14 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO14 } # [doc = "DIO15"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_dio15 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_DIO15 } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_event1_iidx_stat (& self) -> INT_EVENT1_IIDX_STAT_R { INT_EVENT1_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_imask`]
module"]
pub type INT_EVENT1_IMASK = crate :: Reg < int_event1_imask :: INT_EVENT1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event1_imask { # [doc = "Register `INT_EVENT1_IMASK` reader"]
pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"]
pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_DIO0` reader - DIO0 event mask"]
pub type INT_EVENT1_IMASK_DIO0_R = crate :: BitReader < INT_EVENT1_IMASK_DIO0_A > ; # [doc = "DIO0 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO0_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO0_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO0_A { match self . bits { false => INT_EVENT1_IMASK_DIO0_A :: INT_EVENT1_IMASK_DIO0_CLR , true => INT_EVENT1_IMASK_DIO0_A :: INT_EVENT1_IMASK_DIO0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio0_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO0_A :: INT_EVENT1_IMASK_DIO0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio0_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO0_A :: INT_EVENT1_IMASK_DIO0_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO0` writer - DIO0 event mask"]
pub type INT_EVENT1_IMASK_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO0_A :: INT_EVENT1_IMASK_DIO0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO0_A :: INT_EVENT1_IMASK_DIO0_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO1` reader - DIO1 event mask"]
pub type INT_EVENT1_IMASK_DIO1_R = crate :: BitReader < INT_EVENT1_IMASK_DIO1_A > ; # [doc = "DIO1 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO1_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO1_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO1_A { match self . bits { false => INT_EVENT1_IMASK_DIO1_A :: INT_EVENT1_IMASK_DIO1_CLR , true => INT_EVENT1_IMASK_DIO1_A :: INT_EVENT1_IMASK_DIO1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio1_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO1_A :: INT_EVENT1_IMASK_DIO1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio1_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO1_A :: INT_EVENT1_IMASK_DIO1_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO1` writer - DIO1 event mask"]
pub type INT_EVENT1_IMASK_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO1_A :: INT_EVENT1_IMASK_DIO1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO1_A :: INT_EVENT1_IMASK_DIO1_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO2` reader - DIO2 event mask"]
pub type INT_EVENT1_IMASK_DIO2_R = crate :: BitReader < INT_EVENT1_IMASK_DIO2_A > ; # [doc = "DIO2 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO2_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO2_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO2_A { match self . bits { false => INT_EVENT1_IMASK_DIO2_A :: INT_EVENT1_IMASK_DIO2_CLR , true => INT_EVENT1_IMASK_DIO2_A :: INT_EVENT1_IMASK_DIO2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio2_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO2_A :: INT_EVENT1_IMASK_DIO2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio2_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO2_A :: INT_EVENT1_IMASK_DIO2_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO2` writer - DIO2 event mask"]
pub type INT_EVENT1_IMASK_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO2_A :: INT_EVENT1_IMASK_DIO2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO2_A :: INT_EVENT1_IMASK_DIO2_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO3` reader - DIO3 event mask"]
pub type INT_EVENT1_IMASK_DIO3_R = crate :: BitReader < INT_EVENT1_IMASK_DIO3_A > ; # [doc = "DIO3 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO3_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO3_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO3_A { match self . bits { false => INT_EVENT1_IMASK_DIO3_A :: INT_EVENT1_IMASK_DIO3_CLR , true => INT_EVENT1_IMASK_DIO3_A :: INT_EVENT1_IMASK_DIO3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio3_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO3_A :: INT_EVENT1_IMASK_DIO3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio3_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO3_A :: INT_EVENT1_IMASK_DIO3_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO3` writer - DIO3 event mask"]
pub type INT_EVENT1_IMASK_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO3_A :: INT_EVENT1_IMASK_DIO3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO3_A :: INT_EVENT1_IMASK_DIO3_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO4` reader - DIO4 event mask"]
pub type INT_EVENT1_IMASK_DIO4_R = crate :: BitReader < INT_EVENT1_IMASK_DIO4_A > ; # [doc = "DIO4 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO4_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO4_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO4_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO4_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO4_A { match self . bits { false => INT_EVENT1_IMASK_DIO4_A :: INT_EVENT1_IMASK_DIO4_CLR , true => INT_EVENT1_IMASK_DIO4_A :: INT_EVENT1_IMASK_DIO4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio4_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO4_A :: INT_EVENT1_IMASK_DIO4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio4_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO4_A :: INT_EVENT1_IMASK_DIO4_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO4` writer - DIO4 event mask"]
pub type INT_EVENT1_IMASK_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO4_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO4_A :: INT_EVENT1_IMASK_DIO4_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO4_A :: INT_EVENT1_IMASK_DIO4_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO5` reader - DIO5 event mask"]
pub type INT_EVENT1_IMASK_DIO5_R = crate :: BitReader < INT_EVENT1_IMASK_DIO5_A > ; # [doc = "DIO5 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO5_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO5_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO5_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO5_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO5_A { match self . bits { false => INT_EVENT1_IMASK_DIO5_A :: INT_EVENT1_IMASK_DIO5_CLR , true => INT_EVENT1_IMASK_DIO5_A :: INT_EVENT1_IMASK_DIO5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio5_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO5_A :: INT_EVENT1_IMASK_DIO5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio5_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO5_A :: INT_EVENT1_IMASK_DIO5_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO5` writer - DIO5 event mask"]
pub type INT_EVENT1_IMASK_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO5_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO5_A :: INT_EVENT1_IMASK_DIO5_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO5_A :: INT_EVENT1_IMASK_DIO5_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO6` reader - DIO6 event mask"]
pub type INT_EVENT1_IMASK_DIO6_R = crate :: BitReader < INT_EVENT1_IMASK_DIO6_A > ; # [doc = "DIO6 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO6_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO6_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO6_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO6_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO6_A { match self . bits { false => INT_EVENT1_IMASK_DIO6_A :: INT_EVENT1_IMASK_DIO6_CLR , true => INT_EVENT1_IMASK_DIO6_A :: INT_EVENT1_IMASK_DIO6_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio6_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO6_A :: INT_EVENT1_IMASK_DIO6_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio6_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO6_A :: INT_EVENT1_IMASK_DIO6_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO6` writer - DIO6 event mask"]
pub type INT_EVENT1_IMASK_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO6_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO6_A :: INT_EVENT1_IMASK_DIO6_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO6_A :: INT_EVENT1_IMASK_DIO6_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO7` reader - DIO7 event mask"]
pub type INT_EVENT1_IMASK_DIO7_R = crate :: BitReader < INT_EVENT1_IMASK_DIO7_A > ; # [doc = "DIO7 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO7_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO7_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO7_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO7_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO7_A { match self . bits { false => INT_EVENT1_IMASK_DIO7_A :: INT_EVENT1_IMASK_DIO7_CLR , true => INT_EVENT1_IMASK_DIO7_A :: INT_EVENT1_IMASK_DIO7_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio7_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO7_A :: INT_EVENT1_IMASK_DIO7_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio7_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO7_A :: INT_EVENT1_IMASK_DIO7_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO7` writer - DIO7 event mask"]
pub type INT_EVENT1_IMASK_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO7_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO7_A :: INT_EVENT1_IMASK_DIO7_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO7_A :: INT_EVENT1_IMASK_DIO7_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO8` reader - DIO8 event mask"]
pub type INT_EVENT1_IMASK_DIO8_R = crate :: BitReader < INT_EVENT1_IMASK_DIO8_A > ; # [doc = "DIO8 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO8_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO8_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO8_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO8_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO8_A { match self . bits { false => INT_EVENT1_IMASK_DIO8_A :: INT_EVENT1_IMASK_DIO8_CLR , true => INT_EVENT1_IMASK_DIO8_A :: INT_EVENT1_IMASK_DIO8_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio8_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO8_A :: INT_EVENT1_IMASK_DIO8_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio8_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO8_A :: INT_EVENT1_IMASK_DIO8_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO8` writer - DIO8 event mask"]
pub type INT_EVENT1_IMASK_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO8_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO8_A :: INT_EVENT1_IMASK_DIO8_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO8_A :: INT_EVENT1_IMASK_DIO8_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO9` reader - DIO9 event mask"]
pub type INT_EVENT1_IMASK_DIO9_R = crate :: BitReader < INT_EVENT1_IMASK_DIO9_A > ; # [doc = "DIO9 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO9_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO9_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO9_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO9_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO9_A { match self . bits { false => INT_EVENT1_IMASK_DIO9_A :: INT_EVENT1_IMASK_DIO9_CLR , true => INT_EVENT1_IMASK_DIO9_A :: INT_EVENT1_IMASK_DIO9_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio9_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO9_A :: INT_EVENT1_IMASK_DIO9_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio9_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO9_A :: INT_EVENT1_IMASK_DIO9_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO9` writer - DIO9 event mask"]
pub type INT_EVENT1_IMASK_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO9_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO9_A :: INT_EVENT1_IMASK_DIO9_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO9_A :: INT_EVENT1_IMASK_DIO9_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO10` reader - DIO10 event mask"]
pub type INT_EVENT1_IMASK_DIO10_R = crate :: BitReader < INT_EVENT1_IMASK_DIO10_A > ; # [doc = "DIO10 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO10_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO10_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO10_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO10_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO10_A { match self . bits { false => INT_EVENT1_IMASK_DIO10_A :: INT_EVENT1_IMASK_DIO10_CLR , true => INT_EVENT1_IMASK_DIO10_A :: INT_EVENT1_IMASK_DIO10_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio10_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO10_A :: INT_EVENT1_IMASK_DIO10_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio10_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO10_A :: INT_EVENT1_IMASK_DIO10_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO10` writer - DIO10 event mask"]
pub type INT_EVENT1_IMASK_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO10_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO10_A :: INT_EVENT1_IMASK_DIO10_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO10_A :: INT_EVENT1_IMASK_DIO10_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO11` reader - DIO11 event mask"]
pub type INT_EVENT1_IMASK_DIO11_R = crate :: BitReader < INT_EVENT1_IMASK_DIO11_A > ; # [doc = "DIO11 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO11_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO11_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO11_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO11_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO11_A { match self . bits { false => INT_EVENT1_IMASK_DIO11_A :: INT_EVENT1_IMASK_DIO11_CLR , true => INT_EVENT1_IMASK_DIO11_A :: INT_EVENT1_IMASK_DIO11_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio11_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO11_A :: INT_EVENT1_IMASK_DIO11_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio11_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO11_A :: INT_EVENT1_IMASK_DIO11_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO11` writer - DIO11 event mask"]
pub type INT_EVENT1_IMASK_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO11_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO11_A :: INT_EVENT1_IMASK_DIO11_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO11_A :: INT_EVENT1_IMASK_DIO11_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO12` reader - DIO12 event mask"]
pub type INT_EVENT1_IMASK_DIO12_R = crate :: BitReader < INT_EVENT1_IMASK_DIO12_A > ; # [doc = "DIO12 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO12_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO12_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO12_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO12_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO12_A { match self . bits { false => INT_EVENT1_IMASK_DIO12_A :: INT_EVENT1_IMASK_DIO12_CLR , true => INT_EVENT1_IMASK_DIO12_A :: INT_EVENT1_IMASK_DIO12_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio12_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO12_A :: INT_EVENT1_IMASK_DIO12_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio12_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO12_A :: INT_EVENT1_IMASK_DIO12_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO12` writer - DIO12 event mask"]
pub type INT_EVENT1_IMASK_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO12_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO12_A :: INT_EVENT1_IMASK_DIO12_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO12_A :: INT_EVENT1_IMASK_DIO12_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO13` reader - DIO13 event mask"]
pub type INT_EVENT1_IMASK_DIO13_R = crate :: BitReader < INT_EVENT1_IMASK_DIO13_A > ; # [doc = "DIO13 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO13_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO13_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO13_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO13_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO13_A { match self . bits { false => INT_EVENT1_IMASK_DIO13_A :: INT_EVENT1_IMASK_DIO13_CLR , true => INT_EVENT1_IMASK_DIO13_A :: INT_EVENT1_IMASK_DIO13_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio13_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO13_A :: INT_EVENT1_IMASK_DIO13_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio13_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO13_A :: INT_EVENT1_IMASK_DIO13_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO13` writer - DIO13 event mask"]
pub type INT_EVENT1_IMASK_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO13_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO13_A :: INT_EVENT1_IMASK_DIO13_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO13_A :: INT_EVENT1_IMASK_DIO13_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO14` reader - DIO14 event mask"]
pub type INT_EVENT1_IMASK_DIO14_R = crate :: BitReader < INT_EVENT1_IMASK_DIO14_A > ; # [doc = "DIO14 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO14_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO14_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO14_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO14_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO14_A { match self . bits { false => INT_EVENT1_IMASK_DIO14_A :: INT_EVENT1_IMASK_DIO14_CLR , true => INT_EVENT1_IMASK_DIO14_A :: INT_EVENT1_IMASK_DIO14_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio14_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO14_A :: INT_EVENT1_IMASK_DIO14_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio14_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO14_A :: INT_EVENT1_IMASK_DIO14_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO14` writer - DIO14 event mask"]
pub type INT_EVENT1_IMASK_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO14_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO14_A :: INT_EVENT1_IMASK_DIO14_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO14_A :: INT_EVENT1_IMASK_DIO14_SET) } } # [doc = "Field `INT_EVENT1_IMASK_DIO15` reader - DIO15 event mask"]
pub type INT_EVENT1_IMASK_DIO15_R = crate :: BitReader < INT_EVENT1_IMASK_DIO15_A > ; # [doc = "DIO15 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_DIO15_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_DIO15_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_DIO15_SET = 1 , } impl From < INT_EVENT1_IMASK_DIO15_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_DIO15_A { match self . bits { false => INT_EVENT1_IMASK_DIO15_A :: INT_EVENT1_IMASK_DIO15_CLR , true => INT_EVENT1_IMASK_DIO15_A :: INT_EVENT1_IMASK_DIO15_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_dio15_clr (& self) -> bool { * self == INT_EVENT1_IMASK_DIO15_A :: INT_EVENT1_IMASK_DIO15_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_dio15_set (& self) -> bool { * self == INT_EVENT1_IMASK_DIO15_A :: INT_EVENT1_IMASK_DIO15_SET } } # [doc = "Field `INT_EVENT1_IMASK_DIO15` writer - DIO15 event mask"]
pub type INT_EVENT1_IMASK_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_DIO15_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO15_A :: INT_EVENT1_IMASK_DIO15_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_DIO15_A :: INT_EVENT1_IMASK_DIO15_SET) } } impl R { # [doc = "Bit 0 - DIO0 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio0 (& self) -> INT_EVENT1_IMASK_DIO0_R { INT_EVENT1_IMASK_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio1 (& self) -> INT_EVENT1_IMASK_DIO1_R { INT_EVENT1_IMASK_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio2 (& self) -> INT_EVENT1_IMASK_DIO2_R { INT_EVENT1_IMASK_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio3 (& self) -> INT_EVENT1_IMASK_DIO3_R { INT_EVENT1_IMASK_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio4 (& self) -> INT_EVENT1_IMASK_DIO4_R { INT_EVENT1_IMASK_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio5 (& self) -> INT_EVENT1_IMASK_DIO5_R { INT_EVENT1_IMASK_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio6 (& self) -> INT_EVENT1_IMASK_DIO6_R { INT_EVENT1_IMASK_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio7 (& self) -> INT_EVENT1_IMASK_DIO7_R { INT_EVENT1_IMASK_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio8 (& self) -> INT_EVENT1_IMASK_DIO8_R { INT_EVENT1_IMASK_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio9 (& self) -> INT_EVENT1_IMASK_DIO9_R { INT_EVENT1_IMASK_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio10 (& self) -> INT_EVENT1_IMASK_DIO10_R { INT_EVENT1_IMASK_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio11 (& self) -> INT_EVENT1_IMASK_DIO11_R { INT_EVENT1_IMASK_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio12 (& self) -> INT_EVENT1_IMASK_DIO12_R { INT_EVENT1_IMASK_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio13 (& self) -> INT_EVENT1_IMASK_DIO13_R { INT_EVENT1_IMASK_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio14 (& self) -> INT_EVENT1_IMASK_DIO14_R { INT_EVENT1_IMASK_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event mask"]
# [inline (always)]
pub fn int_event1_imask_dio15 (& self) -> INT_EVENT1_IMASK_DIO15_R { INT_EVENT1_IMASK_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - DIO0 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio0 (& mut self) -> INT_EVENT1_IMASK_DIO0_W < INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio1 (& mut self) -> INT_EVENT1_IMASK_DIO1_W < INT_EVENT1_IMASK_SPEC , 1 > { INT_EVENT1_IMASK_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio2 (& mut self) -> INT_EVENT1_IMASK_DIO2_W < INT_EVENT1_IMASK_SPEC , 2 > { INT_EVENT1_IMASK_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio3 (& mut self) -> INT_EVENT1_IMASK_DIO3_W < INT_EVENT1_IMASK_SPEC , 3 > { INT_EVENT1_IMASK_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio4 (& mut self) -> INT_EVENT1_IMASK_DIO4_W < INT_EVENT1_IMASK_SPEC , 4 > { INT_EVENT1_IMASK_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio5 (& mut self) -> INT_EVENT1_IMASK_DIO5_W < INT_EVENT1_IMASK_SPEC , 5 > { INT_EVENT1_IMASK_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio6 (& mut self) -> INT_EVENT1_IMASK_DIO6_W < INT_EVENT1_IMASK_SPEC , 6 > { INT_EVENT1_IMASK_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio7 (& mut self) -> INT_EVENT1_IMASK_DIO7_W < INT_EVENT1_IMASK_SPEC , 7 > { INT_EVENT1_IMASK_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio8 (& mut self) -> INT_EVENT1_IMASK_DIO8_W < INT_EVENT1_IMASK_SPEC , 8 > { INT_EVENT1_IMASK_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio9 (& mut self) -> INT_EVENT1_IMASK_DIO9_W < INT_EVENT1_IMASK_SPEC , 9 > { INT_EVENT1_IMASK_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio10 (& mut self) -> INT_EVENT1_IMASK_DIO10_W < INT_EVENT1_IMASK_SPEC , 10 > { INT_EVENT1_IMASK_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio11 (& mut self) -> INT_EVENT1_IMASK_DIO11_W < INT_EVENT1_IMASK_SPEC , 11 > { INT_EVENT1_IMASK_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio12 (& mut self) -> INT_EVENT1_IMASK_DIO12_W < INT_EVENT1_IMASK_SPEC , 12 > { INT_EVENT1_IMASK_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio13 (& mut self) -> INT_EVENT1_IMASK_DIO13_W < INT_EVENT1_IMASK_SPEC , 13 > { INT_EVENT1_IMASK_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio14 (& mut self) -> INT_EVENT1_IMASK_DIO14_W < INT_EVENT1_IMASK_SPEC , 14 > { INT_EVENT1_IMASK_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_dio15 (& mut self) -> INT_EVENT1_IMASK_DIO15_W < INT_EVENT1_IMASK_SPEC , 15 > { INT_EVENT1_IMASK_DIO15_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_ris`]
module"]
pub type INT_EVENT1_RIS = crate :: Reg < int_event1_ris :: INT_EVENT1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event1_ris { # [doc = "Register `INT_EVENT1_RIS` reader"]
pub type R = crate :: R < INT_EVENT1_RIS_SPEC > ; # [doc = "Field `INT_EVENT1_RIS_DIO0` reader - DIO0 event"]
pub type INT_EVENT1_RIS_DIO0_R = crate :: BitReader < INT_EVENT1_RIS_DIO0_A > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO0_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO0_SET = 1 , } impl From < INT_EVENT1_RIS_DIO0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO0_A { match self . bits { false => INT_EVENT1_RIS_DIO0_A :: INT_EVENT1_RIS_DIO0_CLR , true => INT_EVENT1_RIS_DIO0_A :: INT_EVENT1_RIS_DIO0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio0_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO0_A :: INT_EVENT1_RIS_DIO0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio0_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO0_A :: INT_EVENT1_RIS_DIO0_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO1` reader - DIO1 event"]
pub type INT_EVENT1_RIS_DIO1_R = crate :: BitReader < INT_EVENT1_RIS_DIO1_A > ; # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO1_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO1_SET = 1 , } impl From < INT_EVENT1_RIS_DIO1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO1_A { match self . bits { false => INT_EVENT1_RIS_DIO1_A :: INT_EVENT1_RIS_DIO1_CLR , true => INT_EVENT1_RIS_DIO1_A :: INT_EVENT1_RIS_DIO1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio1_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO1_A :: INT_EVENT1_RIS_DIO1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio1_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO1_A :: INT_EVENT1_RIS_DIO1_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO2` reader - DIO2 event"]
pub type INT_EVENT1_RIS_DIO2_R = crate :: BitReader < INT_EVENT1_RIS_DIO2_A > ; # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO2_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO2_SET = 1 , } impl From < INT_EVENT1_RIS_DIO2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO2_A { match self . bits { false => INT_EVENT1_RIS_DIO2_A :: INT_EVENT1_RIS_DIO2_CLR , true => INT_EVENT1_RIS_DIO2_A :: INT_EVENT1_RIS_DIO2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio2_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO2_A :: INT_EVENT1_RIS_DIO2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio2_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO2_A :: INT_EVENT1_RIS_DIO2_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO3` reader - DIO3 event"]
pub type INT_EVENT1_RIS_DIO3_R = crate :: BitReader < INT_EVENT1_RIS_DIO3_A > ; # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO3_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO3_SET = 1 , } impl From < INT_EVENT1_RIS_DIO3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO3_A { match self . bits { false => INT_EVENT1_RIS_DIO3_A :: INT_EVENT1_RIS_DIO3_CLR , true => INT_EVENT1_RIS_DIO3_A :: INT_EVENT1_RIS_DIO3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio3_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO3_A :: INT_EVENT1_RIS_DIO3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio3_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO3_A :: INT_EVENT1_RIS_DIO3_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO4` reader - DIO4 event"]
pub type INT_EVENT1_RIS_DIO4_R = crate :: BitReader < INT_EVENT1_RIS_DIO4_A > ; # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO4_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO4_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO4_SET = 1 , } impl From < INT_EVENT1_RIS_DIO4_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO4_A { match self . bits { false => INT_EVENT1_RIS_DIO4_A :: INT_EVENT1_RIS_DIO4_CLR , true => INT_EVENT1_RIS_DIO4_A :: INT_EVENT1_RIS_DIO4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio4_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO4_A :: INT_EVENT1_RIS_DIO4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio4_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO4_A :: INT_EVENT1_RIS_DIO4_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO5` reader - DIO5 event"]
pub type INT_EVENT1_RIS_DIO5_R = crate :: BitReader < INT_EVENT1_RIS_DIO5_A > ; # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO5_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO5_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO5_SET = 1 , } impl From < INT_EVENT1_RIS_DIO5_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO5_A { match self . bits { false => INT_EVENT1_RIS_DIO5_A :: INT_EVENT1_RIS_DIO5_CLR , true => INT_EVENT1_RIS_DIO5_A :: INT_EVENT1_RIS_DIO5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio5_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO5_A :: INT_EVENT1_RIS_DIO5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio5_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO5_A :: INT_EVENT1_RIS_DIO5_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO6` reader - DIO6 event"]
pub type INT_EVENT1_RIS_DIO6_R = crate :: BitReader < INT_EVENT1_RIS_DIO6_A > ; # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO6_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO6_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO6_SET = 1 , } impl From < INT_EVENT1_RIS_DIO6_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO6_A { match self . bits { false => INT_EVENT1_RIS_DIO6_A :: INT_EVENT1_RIS_DIO6_CLR , true => INT_EVENT1_RIS_DIO6_A :: INT_EVENT1_RIS_DIO6_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio6_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO6_A :: INT_EVENT1_RIS_DIO6_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio6_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO6_A :: INT_EVENT1_RIS_DIO6_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO7` reader - DIO7 event"]
pub type INT_EVENT1_RIS_DIO7_R = crate :: BitReader < INT_EVENT1_RIS_DIO7_A > ; # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO7_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO7_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO7_SET = 1 , } impl From < INT_EVENT1_RIS_DIO7_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO7_A { match self . bits { false => INT_EVENT1_RIS_DIO7_A :: INT_EVENT1_RIS_DIO7_CLR , true => INT_EVENT1_RIS_DIO7_A :: INT_EVENT1_RIS_DIO7_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio7_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO7_A :: INT_EVENT1_RIS_DIO7_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio7_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO7_A :: INT_EVENT1_RIS_DIO7_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO8` reader - DIO8 event"]
pub type INT_EVENT1_RIS_DIO8_R = crate :: BitReader < INT_EVENT1_RIS_DIO8_A > ; # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO8_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO8_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO8_SET = 1 , } impl From < INT_EVENT1_RIS_DIO8_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO8_A { match self . bits { false => INT_EVENT1_RIS_DIO8_A :: INT_EVENT1_RIS_DIO8_CLR , true => INT_EVENT1_RIS_DIO8_A :: INT_EVENT1_RIS_DIO8_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio8_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO8_A :: INT_EVENT1_RIS_DIO8_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio8_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO8_A :: INT_EVENT1_RIS_DIO8_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO9` reader - DIO9 event"]
pub type INT_EVENT1_RIS_DIO9_R = crate :: BitReader < INT_EVENT1_RIS_DIO9_A > ; # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO9_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO9_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO9_SET = 1 , } impl From < INT_EVENT1_RIS_DIO9_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO9_A { match self . bits { false => INT_EVENT1_RIS_DIO9_A :: INT_EVENT1_RIS_DIO9_CLR , true => INT_EVENT1_RIS_DIO9_A :: INT_EVENT1_RIS_DIO9_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio9_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO9_A :: INT_EVENT1_RIS_DIO9_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio9_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO9_A :: INT_EVENT1_RIS_DIO9_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO10` reader - DIO10 event"]
pub type INT_EVENT1_RIS_DIO10_R = crate :: BitReader < INT_EVENT1_RIS_DIO10_A > ; # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO10_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO10_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO10_SET = 1 , } impl From < INT_EVENT1_RIS_DIO10_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO10_A { match self . bits { false => INT_EVENT1_RIS_DIO10_A :: INT_EVENT1_RIS_DIO10_CLR , true => INT_EVENT1_RIS_DIO10_A :: INT_EVENT1_RIS_DIO10_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio10_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO10_A :: INT_EVENT1_RIS_DIO10_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio10_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO10_A :: INT_EVENT1_RIS_DIO10_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO11` reader - DIO11 event"]
pub type INT_EVENT1_RIS_DIO11_R = crate :: BitReader < INT_EVENT1_RIS_DIO11_A > ; # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO11_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO11_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO11_SET = 1 , } impl From < INT_EVENT1_RIS_DIO11_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO11_A { match self . bits { false => INT_EVENT1_RIS_DIO11_A :: INT_EVENT1_RIS_DIO11_CLR , true => INT_EVENT1_RIS_DIO11_A :: INT_EVENT1_RIS_DIO11_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio11_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO11_A :: INT_EVENT1_RIS_DIO11_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio11_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO11_A :: INT_EVENT1_RIS_DIO11_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO12` reader - DIO12 event"]
pub type INT_EVENT1_RIS_DIO12_R = crate :: BitReader < INT_EVENT1_RIS_DIO12_A > ; # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO12_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO12_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO12_SET = 1 , } impl From < INT_EVENT1_RIS_DIO12_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO12_A { match self . bits { false => INT_EVENT1_RIS_DIO12_A :: INT_EVENT1_RIS_DIO12_CLR , true => INT_EVENT1_RIS_DIO12_A :: INT_EVENT1_RIS_DIO12_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio12_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO12_A :: INT_EVENT1_RIS_DIO12_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio12_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO12_A :: INT_EVENT1_RIS_DIO12_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO13` reader - DIO13 event"]
pub type INT_EVENT1_RIS_DIO13_R = crate :: BitReader < INT_EVENT1_RIS_DIO13_A > ; # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO13_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO13_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO13_SET = 1 , } impl From < INT_EVENT1_RIS_DIO13_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO13_A { match self . bits { false => INT_EVENT1_RIS_DIO13_A :: INT_EVENT1_RIS_DIO13_CLR , true => INT_EVENT1_RIS_DIO13_A :: INT_EVENT1_RIS_DIO13_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio13_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO13_A :: INT_EVENT1_RIS_DIO13_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio13_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO13_A :: INT_EVENT1_RIS_DIO13_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO14` reader - DIO14 event"]
pub type INT_EVENT1_RIS_DIO14_R = crate :: BitReader < INT_EVENT1_RIS_DIO14_A > ; # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO14_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO14_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO14_SET = 1 , } impl From < INT_EVENT1_RIS_DIO14_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO14_A { match self . bits { false => INT_EVENT1_RIS_DIO14_A :: INT_EVENT1_RIS_DIO14_CLR , true => INT_EVENT1_RIS_DIO14_A :: INT_EVENT1_RIS_DIO14_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio14_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO14_A :: INT_EVENT1_RIS_DIO14_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio14_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO14_A :: INT_EVENT1_RIS_DIO14_SET } } # [doc = "Field `INT_EVENT1_RIS_DIO15` reader - DIO15 event"]
pub type INT_EVENT1_RIS_DIO15_R = crate :: BitReader < INT_EVENT1_RIS_DIO15_A > ; # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_DIO15_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_DIO15_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_DIO15_SET = 1 , } impl From < INT_EVENT1_RIS_DIO15_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_DIO15_A { match self . bits { false => INT_EVENT1_RIS_DIO15_A :: INT_EVENT1_RIS_DIO15_CLR , true => INT_EVENT1_RIS_DIO15_A :: INT_EVENT1_RIS_DIO15_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_dio15_clr (& self) -> bool { * self == INT_EVENT1_RIS_DIO15_A :: INT_EVENT1_RIS_DIO15_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_dio15_set (& self) -> bool { * self == INT_EVENT1_RIS_DIO15_A :: INT_EVENT1_RIS_DIO15_SET } } impl R { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
pub fn int_event1_ris_dio0 (& self) -> INT_EVENT1_RIS_DIO0_R { INT_EVENT1_RIS_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
pub fn int_event1_ris_dio1 (& self) -> INT_EVENT1_RIS_DIO1_R { INT_EVENT1_RIS_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
pub fn int_event1_ris_dio2 (& self) -> INT_EVENT1_RIS_DIO2_R { INT_EVENT1_RIS_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
pub fn int_event1_ris_dio3 (& self) -> INT_EVENT1_RIS_DIO3_R { INT_EVENT1_RIS_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
pub fn int_event1_ris_dio4 (& self) -> INT_EVENT1_RIS_DIO4_R { INT_EVENT1_RIS_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
pub fn int_event1_ris_dio5 (& self) -> INT_EVENT1_RIS_DIO5_R { INT_EVENT1_RIS_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
pub fn int_event1_ris_dio6 (& self) -> INT_EVENT1_RIS_DIO6_R { INT_EVENT1_RIS_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
pub fn int_event1_ris_dio7 (& self) -> INT_EVENT1_RIS_DIO7_R { INT_EVENT1_RIS_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
pub fn int_event1_ris_dio8 (& self) -> INT_EVENT1_RIS_DIO8_R { INT_EVENT1_RIS_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
pub fn int_event1_ris_dio9 (& self) -> INT_EVENT1_RIS_DIO9_R { INT_EVENT1_RIS_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
pub fn int_event1_ris_dio10 (& self) -> INT_EVENT1_RIS_DIO10_R { INT_EVENT1_RIS_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
pub fn int_event1_ris_dio11 (& self) -> INT_EVENT1_RIS_DIO11_R { INT_EVENT1_RIS_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
pub fn int_event1_ris_dio12 (& self) -> INT_EVENT1_RIS_DIO12_R { INT_EVENT1_RIS_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
pub fn int_event1_ris_dio13 (& self) -> INT_EVENT1_RIS_DIO13_R { INT_EVENT1_RIS_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
pub fn int_event1_ris_dio14 (& self) -> INT_EVENT1_RIS_DIO14_R { INT_EVENT1_RIS_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
pub fn int_event1_ris_dio15 (& self) -> INT_EVENT1_RIS_DIO15_R { INT_EVENT1_RIS_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_RIS to value 0"]
impl crate :: Resettable for INT_EVENT1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_mis`]
module"]
pub type INT_EVENT1_MIS = crate :: Reg < int_event1_mis :: INT_EVENT1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event1_mis { # [doc = "Register `INT_EVENT1_MIS` reader"]
pub type R = crate :: R < INT_EVENT1_MIS_SPEC > ; # [doc = "Field `INT_EVENT1_MIS_DIO0` reader - DIO0 event"]
pub type INT_EVENT1_MIS_DIO0_R = crate :: BitReader < INT_EVENT1_MIS_DIO0_A > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO0_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO0_SET = 1 , } impl From < INT_EVENT1_MIS_DIO0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO0_A { match self . bits { false => INT_EVENT1_MIS_DIO0_A :: INT_EVENT1_MIS_DIO0_CLR , true => INT_EVENT1_MIS_DIO0_A :: INT_EVENT1_MIS_DIO0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio0_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO0_A :: INT_EVENT1_MIS_DIO0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio0_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO0_A :: INT_EVENT1_MIS_DIO0_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO1` reader - DIO1 event"]
pub type INT_EVENT1_MIS_DIO1_R = crate :: BitReader < INT_EVENT1_MIS_DIO1_A > ; # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO1_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO1_SET = 1 , } impl From < INT_EVENT1_MIS_DIO1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO1_A { match self . bits { false => INT_EVENT1_MIS_DIO1_A :: INT_EVENT1_MIS_DIO1_CLR , true => INT_EVENT1_MIS_DIO1_A :: INT_EVENT1_MIS_DIO1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio1_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO1_A :: INT_EVENT1_MIS_DIO1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio1_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO1_A :: INT_EVENT1_MIS_DIO1_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO2` reader - DIO2 event"]
pub type INT_EVENT1_MIS_DIO2_R = crate :: BitReader < INT_EVENT1_MIS_DIO2_A > ; # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO2_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO2_SET = 1 , } impl From < INT_EVENT1_MIS_DIO2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO2_A { match self . bits { false => INT_EVENT1_MIS_DIO2_A :: INT_EVENT1_MIS_DIO2_CLR , true => INT_EVENT1_MIS_DIO2_A :: INT_EVENT1_MIS_DIO2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio2_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO2_A :: INT_EVENT1_MIS_DIO2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio2_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO2_A :: INT_EVENT1_MIS_DIO2_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO3` reader - DIO3 event"]
pub type INT_EVENT1_MIS_DIO3_R = crate :: BitReader < INT_EVENT1_MIS_DIO3_A > ; # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO3_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO3_SET = 1 , } impl From < INT_EVENT1_MIS_DIO3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO3_A { match self . bits { false => INT_EVENT1_MIS_DIO3_A :: INT_EVENT1_MIS_DIO3_CLR , true => INT_EVENT1_MIS_DIO3_A :: INT_EVENT1_MIS_DIO3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio3_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO3_A :: INT_EVENT1_MIS_DIO3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio3_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO3_A :: INT_EVENT1_MIS_DIO3_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO4` reader - DIO4 event"]
pub type INT_EVENT1_MIS_DIO4_R = crate :: BitReader < INT_EVENT1_MIS_DIO4_A > ; # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO4_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO4_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO4_SET = 1 , } impl From < INT_EVENT1_MIS_DIO4_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO4_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO4_A { match self . bits { false => INT_EVENT1_MIS_DIO4_A :: INT_EVENT1_MIS_DIO4_CLR , true => INT_EVENT1_MIS_DIO4_A :: INT_EVENT1_MIS_DIO4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio4_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO4_A :: INT_EVENT1_MIS_DIO4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio4_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO4_A :: INT_EVENT1_MIS_DIO4_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO5` reader - DIO5 event"]
pub type INT_EVENT1_MIS_DIO5_R = crate :: BitReader < INT_EVENT1_MIS_DIO5_A > ; # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO5_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO5_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO5_SET = 1 , } impl From < INT_EVENT1_MIS_DIO5_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO5_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO5_A { match self . bits { false => INT_EVENT1_MIS_DIO5_A :: INT_EVENT1_MIS_DIO5_CLR , true => INT_EVENT1_MIS_DIO5_A :: INT_EVENT1_MIS_DIO5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio5_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO5_A :: INT_EVENT1_MIS_DIO5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio5_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO5_A :: INT_EVENT1_MIS_DIO5_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO6` reader - DIO6 event"]
pub type INT_EVENT1_MIS_DIO6_R = crate :: BitReader < INT_EVENT1_MIS_DIO6_A > ; # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO6_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO6_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO6_SET = 1 , } impl From < INT_EVENT1_MIS_DIO6_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO6_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO6_A { match self . bits { false => INT_EVENT1_MIS_DIO6_A :: INT_EVENT1_MIS_DIO6_CLR , true => INT_EVENT1_MIS_DIO6_A :: INT_EVENT1_MIS_DIO6_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio6_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO6_A :: INT_EVENT1_MIS_DIO6_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio6_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO6_A :: INT_EVENT1_MIS_DIO6_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO7` reader - DIO7 event"]
pub type INT_EVENT1_MIS_DIO7_R = crate :: BitReader < INT_EVENT1_MIS_DIO7_A > ; # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO7_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO7_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO7_SET = 1 , } impl From < INT_EVENT1_MIS_DIO7_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO7_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO7_A { match self . bits { false => INT_EVENT1_MIS_DIO7_A :: INT_EVENT1_MIS_DIO7_CLR , true => INT_EVENT1_MIS_DIO7_A :: INT_EVENT1_MIS_DIO7_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio7_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO7_A :: INT_EVENT1_MIS_DIO7_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio7_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO7_A :: INT_EVENT1_MIS_DIO7_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO8` reader - DIO8 event"]
pub type INT_EVENT1_MIS_DIO8_R = crate :: BitReader < INT_EVENT1_MIS_DIO8_A > ; # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO8_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO8_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO8_SET = 1 , } impl From < INT_EVENT1_MIS_DIO8_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO8_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO8_A { match self . bits { false => INT_EVENT1_MIS_DIO8_A :: INT_EVENT1_MIS_DIO8_CLR , true => INT_EVENT1_MIS_DIO8_A :: INT_EVENT1_MIS_DIO8_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio8_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO8_A :: INT_EVENT1_MIS_DIO8_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio8_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO8_A :: INT_EVENT1_MIS_DIO8_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO9` reader - DIO9 event"]
pub type INT_EVENT1_MIS_DIO9_R = crate :: BitReader < INT_EVENT1_MIS_DIO9_A > ; # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO9_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO9_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO9_SET = 1 , } impl From < INT_EVENT1_MIS_DIO9_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO9_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO9_A { match self . bits { false => INT_EVENT1_MIS_DIO9_A :: INT_EVENT1_MIS_DIO9_CLR , true => INT_EVENT1_MIS_DIO9_A :: INT_EVENT1_MIS_DIO9_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio9_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO9_A :: INT_EVENT1_MIS_DIO9_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio9_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO9_A :: INT_EVENT1_MIS_DIO9_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO10` reader - DIO10 event"]
pub type INT_EVENT1_MIS_DIO10_R = crate :: BitReader < INT_EVENT1_MIS_DIO10_A > ; # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO10_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO10_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO10_SET = 1 , } impl From < INT_EVENT1_MIS_DIO10_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO10_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO10_A { match self . bits { false => INT_EVENT1_MIS_DIO10_A :: INT_EVENT1_MIS_DIO10_CLR , true => INT_EVENT1_MIS_DIO10_A :: INT_EVENT1_MIS_DIO10_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio10_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO10_A :: INT_EVENT1_MIS_DIO10_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio10_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO10_A :: INT_EVENT1_MIS_DIO10_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO11` reader - DIO11 event"]
pub type INT_EVENT1_MIS_DIO11_R = crate :: BitReader < INT_EVENT1_MIS_DIO11_A > ; # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO11_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO11_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO11_SET = 1 , } impl From < INT_EVENT1_MIS_DIO11_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO11_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO11_A { match self . bits { false => INT_EVENT1_MIS_DIO11_A :: INT_EVENT1_MIS_DIO11_CLR , true => INT_EVENT1_MIS_DIO11_A :: INT_EVENT1_MIS_DIO11_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio11_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO11_A :: INT_EVENT1_MIS_DIO11_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio11_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO11_A :: INT_EVENT1_MIS_DIO11_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO12` reader - DIO12 event"]
pub type INT_EVENT1_MIS_DIO12_R = crate :: BitReader < INT_EVENT1_MIS_DIO12_A > ; # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO12_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO12_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO12_SET = 1 , } impl From < INT_EVENT1_MIS_DIO12_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO12_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO12_A { match self . bits { false => INT_EVENT1_MIS_DIO12_A :: INT_EVENT1_MIS_DIO12_CLR , true => INT_EVENT1_MIS_DIO12_A :: INT_EVENT1_MIS_DIO12_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio12_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO12_A :: INT_EVENT1_MIS_DIO12_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio12_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO12_A :: INT_EVENT1_MIS_DIO12_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO13` reader - DIO13 event"]
pub type INT_EVENT1_MIS_DIO13_R = crate :: BitReader < INT_EVENT1_MIS_DIO13_A > ; # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO13_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO13_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO13_SET = 1 , } impl From < INT_EVENT1_MIS_DIO13_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO13_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO13_A { match self . bits { false => INT_EVENT1_MIS_DIO13_A :: INT_EVENT1_MIS_DIO13_CLR , true => INT_EVENT1_MIS_DIO13_A :: INT_EVENT1_MIS_DIO13_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio13_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO13_A :: INT_EVENT1_MIS_DIO13_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio13_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO13_A :: INT_EVENT1_MIS_DIO13_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO14` reader - DIO14 event"]
pub type INT_EVENT1_MIS_DIO14_R = crate :: BitReader < INT_EVENT1_MIS_DIO14_A > ; # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO14_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO14_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO14_SET = 1 , } impl From < INT_EVENT1_MIS_DIO14_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO14_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO14_A { match self . bits { false => INT_EVENT1_MIS_DIO14_A :: INT_EVENT1_MIS_DIO14_CLR , true => INT_EVENT1_MIS_DIO14_A :: INT_EVENT1_MIS_DIO14_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio14_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO14_A :: INT_EVENT1_MIS_DIO14_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio14_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO14_A :: INT_EVENT1_MIS_DIO14_SET } } # [doc = "Field `INT_EVENT1_MIS_DIO15` reader - DIO15 event"]
pub type INT_EVENT1_MIS_DIO15_R = crate :: BitReader < INT_EVENT1_MIS_DIO15_A > ; # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_DIO15_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_DIO15_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_DIO15_SET = 1 , } impl From < INT_EVENT1_MIS_DIO15_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_DIO15_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_DIO15_A { match self . bits { false => INT_EVENT1_MIS_DIO15_A :: INT_EVENT1_MIS_DIO15_CLR , true => INT_EVENT1_MIS_DIO15_A :: INT_EVENT1_MIS_DIO15_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_dio15_clr (& self) -> bool { * self == INT_EVENT1_MIS_DIO15_A :: INT_EVENT1_MIS_DIO15_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_dio15_set (& self) -> bool { * self == INT_EVENT1_MIS_DIO15_A :: INT_EVENT1_MIS_DIO15_SET } } impl R { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
pub fn int_event1_mis_dio0 (& self) -> INT_EVENT1_MIS_DIO0_R { INT_EVENT1_MIS_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
pub fn int_event1_mis_dio1 (& self) -> INT_EVENT1_MIS_DIO1_R { INT_EVENT1_MIS_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
pub fn int_event1_mis_dio2 (& self) -> INT_EVENT1_MIS_DIO2_R { INT_EVENT1_MIS_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
pub fn int_event1_mis_dio3 (& self) -> INT_EVENT1_MIS_DIO3_R { INT_EVENT1_MIS_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
pub fn int_event1_mis_dio4 (& self) -> INT_EVENT1_MIS_DIO4_R { INT_EVENT1_MIS_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
pub fn int_event1_mis_dio5 (& self) -> INT_EVENT1_MIS_DIO5_R { INT_EVENT1_MIS_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
pub fn int_event1_mis_dio6 (& self) -> INT_EVENT1_MIS_DIO6_R { INT_EVENT1_MIS_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
pub fn int_event1_mis_dio7 (& self) -> INT_EVENT1_MIS_DIO7_R { INT_EVENT1_MIS_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
pub fn int_event1_mis_dio8 (& self) -> INT_EVENT1_MIS_DIO8_R { INT_EVENT1_MIS_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
pub fn int_event1_mis_dio9 (& self) -> INT_EVENT1_MIS_DIO9_R { INT_EVENT1_MIS_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
pub fn int_event1_mis_dio10 (& self) -> INT_EVENT1_MIS_DIO10_R { INT_EVENT1_MIS_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
pub fn int_event1_mis_dio11 (& self) -> INT_EVENT1_MIS_DIO11_R { INT_EVENT1_MIS_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
pub fn int_event1_mis_dio12 (& self) -> INT_EVENT1_MIS_DIO12_R { INT_EVENT1_MIS_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
pub fn int_event1_mis_dio13 (& self) -> INT_EVENT1_MIS_DIO13_R { INT_EVENT1_MIS_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
pub fn int_event1_mis_dio14 (& self) -> INT_EVENT1_MIS_DIO14_R { INT_EVENT1_MIS_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
pub fn int_event1_mis_dio15 (& self) -> INT_EVENT1_MIS_DIO15_R { INT_EVENT1_MIS_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_MIS to value 0"]
impl crate :: Resettable for INT_EVENT1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iset`]
module"]
pub type INT_EVENT1_ISET = crate :: Reg < int_event1_iset :: INT_EVENT1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event1_iset { # [doc = "Register `INT_EVENT1_ISET` writer"]
pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO0_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO0_SET = 1 , } impl From < INT_EVENT1_ISET_DIO0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO0` writer - DIO0 event"]
pub type INT_EVENT1_ISET_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO0_AW :: INT_EVENT1_ISET_DIO0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO0_AW :: INT_EVENT1_ISET_DIO0_SET) } } # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO1_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO1_SET = 1 , } impl From < INT_EVENT1_ISET_DIO1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO1` writer - DIO1 event"]
pub type INT_EVENT1_ISET_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO1_AW :: INT_EVENT1_ISET_DIO1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO1_AW :: INT_EVENT1_ISET_DIO1_SET) } } # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO2_SET = 1 , } impl From < INT_EVENT1_ISET_DIO2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO2` writer - DIO2 event"]
pub type INT_EVENT1_ISET_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO2_AW :: INT_EVENT1_ISET_DIO2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO2_AW :: INT_EVENT1_ISET_DIO2_SET) } } # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO3_SET = 1 , } impl From < INT_EVENT1_ISET_DIO3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO3` writer - DIO3 event"]
pub type INT_EVENT1_ISET_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO3_AW :: INT_EVENT1_ISET_DIO3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO3_AW :: INT_EVENT1_ISET_DIO3_SET) } } # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO4_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO4_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO4_SET = 1 , } impl From < INT_EVENT1_ISET_DIO4_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO4` writer - DIO4 event"]
pub type INT_EVENT1_ISET_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO4_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO4_AW :: INT_EVENT1_ISET_DIO4_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO4_AW :: INT_EVENT1_ISET_DIO4_SET) } } # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO5_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO5_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO5_SET = 1 , } impl From < INT_EVENT1_ISET_DIO5_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO5` writer - DIO5 event"]
pub type INT_EVENT1_ISET_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO5_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO5_AW :: INT_EVENT1_ISET_DIO5_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO5_AW :: INT_EVENT1_ISET_DIO5_SET) } } # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO6_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO6_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO6_SET = 1 , } impl From < INT_EVENT1_ISET_DIO6_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO6` writer - DIO6 event"]
pub type INT_EVENT1_ISET_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO6_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO6_AW :: INT_EVENT1_ISET_DIO6_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO6_AW :: INT_EVENT1_ISET_DIO6_SET) } } # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO7_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO7_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO7_SET = 1 , } impl From < INT_EVENT1_ISET_DIO7_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO7` writer - DIO7 event"]
pub type INT_EVENT1_ISET_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO7_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO7_AW :: INT_EVENT1_ISET_DIO7_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO7_AW :: INT_EVENT1_ISET_DIO7_SET) } } # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO8_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO8_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO8_SET = 1 , } impl From < INT_EVENT1_ISET_DIO8_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO8` writer - DIO8 event"]
pub type INT_EVENT1_ISET_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO8_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO8_AW :: INT_EVENT1_ISET_DIO8_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO8_AW :: INT_EVENT1_ISET_DIO8_SET) } } # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO9_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO9_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO9_SET = 1 , } impl From < INT_EVENT1_ISET_DIO9_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO9` writer - DIO9 event"]
pub type INT_EVENT1_ISET_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO9_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO9_AW :: INT_EVENT1_ISET_DIO9_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO9_AW :: INT_EVENT1_ISET_DIO9_SET) } } # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO10_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO10_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO10_SET = 1 , } impl From < INT_EVENT1_ISET_DIO10_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO10` writer - DIO10 event"]
pub type INT_EVENT1_ISET_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO10_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO10_AW :: INT_EVENT1_ISET_DIO10_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO10_AW :: INT_EVENT1_ISET_DIO10_SET) } } # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO11_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO11_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO11_SET = 1 , } impl From < INT_EVENT1_ISET_DIO11_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO11` writer - DIO11 event"]
pub type INT_EVENT1_ISET_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO11_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO11_AW :: INT_EVENT1_ISET_DIO11_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO11_AW :: INT_EVENT1_ISET_DIO11_SET) } } # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO12_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO12_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO12_SET = 1 , } impl From < INT_EVENT1_ISET_DIO12_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO12` writer - DIO12 event"]
pub type INT_EVENT1_ISET_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO12_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO12_AW :: INT_EVENT1_ISET_DIO12_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO12_AW :: INT_EVENT1_ISET_DIO12_SET) } } # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO13_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO13_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO13_SET = 1 , } impl From < INT_EVENT1_ISET_DIO13_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO13` writer - DIO13 event"]
pub type INT_EVENT1_ISET_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO13_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO13_AW :: INT_EVENT1_ISET_DIO13_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO13_AW :: INT_EVENT1_ISET_DIO13_SET) } } # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO14_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO14_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO14_SET = 1 , } impl From < INT_EVENT1_ISET_DIO14_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO14` writer - DIO14 event"]
pub type INT_EVENT1_ISET_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO14_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO14_AW :: INT_EVENT1_ISET_DIO14_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO14_AW :: INT_EVENT1_ISET_DIO14_SET) } } # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_DIO15_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_DIO15_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_DIO15_SET = 1 , } impl From < INT_EVENT1_ISET_DIO15_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_DIO15` writer - DIO15 event"]
pub type INT_EVENT1_ISET_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_DIO15_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO15_AW :: INT_EVENT1_ISET_DIO15_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_DIO15_AW :: INT_EVENT1_ISET_DIO15_SET) } } impl W { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio0 (& mut self) -> INT_EVENT1_ISET_DIO0_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio1 (& mut self) -> INT_EVENT1_ISET_DIO1_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio2 (& mut self) -> INT_EVENT1_ISET_DIO2_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio3 (& mut self) -> INT_EVENT1_ISET_DIO3_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio4 (& mut self) -> INT_EVENT1_ISET_DIO4_W < INT_EVENT1_ISET_SPEC , 4 > { INT_EVENT1_ISET_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio5 (& mut self) -> INT_EVENT1_ISET_DIO5_W < INT_EVENT1_ISET_SPEC , 5 > { INT_EVENT1_ISET_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio6 (& mut self) -> INT_EVENT1_ISET_DIO6_W < INT_EVENT1_ISET_SPEC , 6 > { INT_EVENT1_ISET_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio7 (& mut self) -> INT_EVENT1_ISET_DIO7_W < INT_EVENT1_ISET_SPEC , 7 > { INT_EVENT1_ISET_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio8 (& mut self) -> INT_EVENT1_ISET_DIO8_W < INT_EVENT1_ISET_SPEC , 8 > { INT_EVENT1_ISET_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio9 (& mut self) -> INT_EVENT1_ISET_DIO9_W < INT_EVENT1_ISET_SPEC , 9 > { INT_EVENT1_ISET_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio10 (& mut self) -> INT_EVENT1_ISET_DIO10_W < INT_EVENT1_ISET_SPEC , 10 > { INT_EVENT1_ISET_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio11 (& mut self) -> INT_EVENT1_ISET_DIO11_W < INT_EVENT1_ISET_SPEC , 11 > { INT_EVENT1_ISET_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio12 (& mut self) -> INT_EVENT1_ISET_DIO12_W < INT_EVENT1_ISET_SPEC , 12 > { INT_EVENT1_ISET_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio13 (& mut self) -> INT_EVENT1_ISET_DIO13_W < INT_EVENT1_ISET_SPEC , 13 > { INT_EVENT1_ISET_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio14 (& mut self) -> INT_EVENT1_ISET_DIO14_W < INT_EVENT1_ISET_SPEC , 14 > { INT_EVENT1_ISET_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_dio15 (& mut self) -> INT_EVENT1_ISET_DIO15_W < INT_EVENT1_ISET_SPEC , 15 > { INT_EVENT1_ISET_DIO15_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"]
impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iclr`]
module"]
pub type INT_EVENT1_ICLR = crate :: Reg < int_event1_iclr :: INT_EVENT1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event1_iclr { # [doc = "Register `INT_EVENT1_ICLR` writer"]
pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "DIO0 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO0_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO0_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO0` writer - DIO0 event"]
pub type INT_EVENT1_ICLR_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO0_AW :: INT_EVENT1_ICLR_DIO0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO0_AW :: INT_EVENT1_ICLR_DIO0_CLR) } } # [doc = "DIO1 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO1_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO1_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO1` writer - DIO1 event"]
pub type INT_EVENT1_ICLR_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO1_AW :: INT_EVENT1_ICLR_DIO1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO1_AW :: INT_EVENT1_ICLR_DIO1_CLR) } } # [doc = "DIO2 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO2_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO2` writer - DIO2 event"]
pub type INT_EVENT1_ICLR_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO2_AW :: INT_EVENT1_ICLR_DIO2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO2_AW :: INT_EVENT1_ICLR_DIO2_CLR) } } # [doc = "DIO3 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO3_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO3` writer - DIO3 event"]
pub type INT_EVENT1_ICLR_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO3_AW :: INT_EVENT1_ICLR_DIO3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO3_AW :: INT_EVENT1_ICLR_DIO3_CLR) } } # [doc = "DIO4 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO4_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO4_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO4_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO4_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO4` writer - DIO4 event"]
pub type INT_EVENT1_ICLR_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO4_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO4_AW :: INT_EVENT1_ICLR_DIO4_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO4_AW :: INT_EVENT1_ICLR_DIO4_CLR) } } # [doc = "DIO5 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO5_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO5_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO5_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO5_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO5` writer - DIO5 event"]
pub type INT_EVENT1_ICLR_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO5_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO5_AW :: INT_EVENT1_ICLR_DIO5_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO5_AW :: INT_EVENT1_ICLR_DIO5_CLR) } } # [doc = "DIO6 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO6_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO6_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO6_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO6_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO6` writer - DIO6 event"]
pub type INT_EVENT1_ICLR_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO6_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO6_AW :: INT_EVENT1_ICLR_DIO6_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO6_AW :: INT_EVENT1_ICLR_DIO6_CLR) } } # [doc = "DIO7 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO7_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO7_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO7_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO7_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO7` writer - DIO7 event"]
pub type INT_EVENT1_ICLR_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO7_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO7_AW :: INT_EVENT1_ICLR_DIO7_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO7_AW :: INT_EVENT1_ICLR_DIO7_CLR) } } # [doc = "DIO8 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO8_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO8_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO8_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO8_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO8` writer - DIO8 event"]
pub type INT_EVENT1_ICLR_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO8_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO8_AW :: INT_EVENT1_ICLR_DIO8_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO8_AW :: INT_EVENT1_ICLR_DIO8_CLR) } } # [doc = "DIO9 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO9_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO9_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO9_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO9_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO9` writer - DIO9 event"]
pub type INT_EVENT1_ICLR_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO9_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO9_AW :: INT_EVENT1_ICLR_DIO9_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO9_AW :: INT_EVENT1_ICLR_DIO9_CLR) } } # [doc = "DIO10 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO10_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO10_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO10_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO10_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO10` writer - DIO10 event"]
pub type INT_EVENT1_ICLR_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO10_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO10_AW :: INT_EVENT1_ICLR_DIO10_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO10_AW :: INT_EVENT1_ICLR_DIO10_CLR) } } # [doc = "DIO11 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO11_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO11_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO11_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO11_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO11` writer - DIO11 event"]
pub type INT_EVENT1_ICLR_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO11_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO11_AW :: INT_EVENT1_ICLR_DIO11_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO11_AW :: INT_EVENT1_ICLR_DIO11_CLR) } } # [doc = "DIO12 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO12_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO12_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO12_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO12_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO12` writer - DIO12 event"]
pub type INT_EVENT1_ICLR_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO12_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO12_AW :: INT_EVENT1_ICLR_DIO12_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO12_AW :: INT_EVENT1_ICLR_DIO12_CLR) } } # [doc = "DIO13 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO13_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO13_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO13_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO13_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO13` writer - DIO13 event"]
pub type INT_EVENT1_ICLR_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO13_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO13_AW :: INT_EVENT1_ICLR_DIO13_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO13_AW :: INT_EVENT1_ICLR_DIO13_CLR) } } # [doc = "DIO14 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO14_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO14_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO14_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO14_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO14` writer - DIO14 event"]
pub type INT_EVENT1_ICLR_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO14_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO14_AW :: INT_EVENT1_ICLR_DIO14_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO14_AW :: INT_EVENT1_ICLR_DIO14_CLR) } } # [doc = "DIO15 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_DIO15_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_DIO15_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_DIO15_CLR = 1 , } impl From < INT_EVENT1_ICLR_DIO15_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_DIO15` writer - DIO15 event"]
pub type INT_EVENT1_ICLR_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_DIO15_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO15_AW :: INT_EVENT1_ICLR_DIO15_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_DIO15_AW :: INT_EVENT1_ICLR_DIO15_CLR) } } impl W { # [doc = "Bit 0 - DIO0 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio0 (& mut self) -> INT_EVENT1_ICLR_DIO0_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_DIO0_W :: new (self) } # [doc = "Bit 1 - DIO1 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio1 (& mut self) -> INT_EVENT1_ICLR_DIO1_W < INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_DIO1_W :: new (self) } # [doc = "Bit 2 - DIO2 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio2 (& mut self) -> INT_EVENT1_ICLR_DIO2_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_DIO2_W :: new (self) } # [doc = "Bit 3 - DIO3 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio3 (& mut self) -> INT_EVENT1_ICLR_DIO3_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_DIO3_W :: new (self) } # [doc = "Bit 4 - DIO4 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio4 (& mut self) -> INT_EVENT1_ICLR_DIO4_W < INT_EVENT1_ICLR_SPEC , 4 > { INT_EVENT1_ICLR_DIO4_W :: new (self) } # [doc = "Bit 5 - DIO5 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio5 (& mut self) -> INT_EVENT1_ICLR_DIO5_W < INT_EVENT1_ICLR_SPEC , 5 > { INT_EVENT1_ICLR_DIO5_W :: new (self) } # [doc = "Bit 6 - DIO6 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio6 (& mut self) -> INT_EVENT1_ICLR_DIO6_W < INT_EVENT1_ICLR_SPEC , 6 > { INT_EVENT1_ICLR_DIO6_W :: new (self) } # [doc = "Bit 7 - DIO7 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio7 (& mut self) -> INT_EVENT1_ICLR_DIO7_W < INT_EVENT1_ICLR_SPEC , 7 > { INT_EVENT1_ICLR_DIO7_W :: new (self) } # [doc = "Bit 8 - DIO8 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio8 (& mut self) -> INT_EVENT1_ICLR_DIO8_W < INT_EVENT1_ICLR_SPEC , 8 > { INT_EVENT1_ICLR_DIO8_W :: new (self) } # [doc = "Bit 9 - DIO9 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio9 (& mut self) -> INT_EVENT1_ICLR_DIO9_W < INT_EVENT1_ICLR_SPEC , 9 > { INT_EVENT1_ICLR_DIO9_W :: new (self) } # [doc = "Bit 10 - DIO10 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio10 (& mut self) -> INT_EVENT1_ICLR_DIO10_W < INT_EVENT1_ICLR_SPEC , 10 > { INT_EVENT1_ICLR_DIO10_W :: new (self) } # [doc = "Bit 11 - DIO11 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio11 (& mut self) -> INT_EVENT1_ICLR_DIO11_W < INT_EVENT1_ICLR_SPEC , 11 > { INT_EVENT1_ICLR_DIO11_W :: new (self) } # [doc = "Bit 12 - DIO12 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio12 (& mut self) -> INT_EVENT1_ICLR_DIO12_W < INT_EVENT1_ICLR_SPEC , 12 > { INT_EVENT1_ICLR_DIO12_W :: new (self) } # [doc = "Bit 13 - DIO13 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio13 (& mut self) -> INT_EVENT1_ICLR_DIO13_W < INT_EVENT1_ICLR_SPEC , 13 > { INT_EVENT1_ICLR_DIO13_W :: new (self) } # [doc = "Bit 14 - DIO14 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio14 (& mut self) -> INT_EVENT1_ICLR_DIO14_W < INT_EVENT1_ICLR_SPEC , 14 > { INT_EVENT1_ICLR_DIO14_W :: new (self) } # [doc = "Bit 15 - DIO15 event"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_dio15 (& mut self) -> INT_EVENT1_ICLR_DIO15_W < INT_EVENT1_ICLR_SPEC , 15 > { INT_EVENT1_ICLR_DIO15_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iidx`]
module"]
pub type INT_EVENT2_IIDX = crate :: Reg < int_event2_iidx :: INT_EVENT2_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event2_iidx { # [doc = "Register `INT_EVENT2_IIDX` reader"]
pub type R = crate :: R < INT_EVENT2_IIDX_SPEC > ; # [doc = "Field `INT_EVENT2_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT2_IIDX_STAT_R = crate :: FieldReader < INT_EVENT2_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT2_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT2_IIDX_STAT_NO_INTR = 0 , # [doc = "1: DIO16"]
INT_EVENT2_IIDX_STAT_DIO16 = 1 , # [doc = "2: DIO17"]
INT_EVENT2_IIDX_STAT_DIO17 = 2 , # [doc = "3: DIO18"]
INT_EVENT2_IIDX_STAT_DIO18 = 3 , # [doc = "4: DIO19"]
INT_EVENT2_IIDX_STAT_DIO19 = 4 , # [doc = "5: DIO20"]
INT_EVENT2_IIDX_STAT_DIO20 = 5 , # [doc = "6: DIO21"]
INT_EVENT2_IIDX_STAT_DIO21 = 6 , # [doc = "7: DIO22"]
INT_EVENT2_IIDX_STAT_DIO22 = 7 , # [doc = "8: DIO23"]
INT_EVENT2_IIDX_STAT_DIO23 = 8 , # [doc = "9: DIO24"]
INT_EVENT2_IIDX_STAT_DIO24 = 9 , # [doc = "10: DIO25"]
INT_EVENT2_IIDX_STAT_DIO25 = 10 , # [doc = "11: DIO26"]
INT_EVENT2_IIDX_STAT_DIO26 = 11 , # [doc = "12: DIO27"]
INT_EVENT2_IIDX_STAT_DIO27 = 12 , # [doc = "13: DIO28"]
INT_EVENT2_IIDX_STAT_DIO28 = 13 , # [doc = "14: DIO29"]
INT_EVENT2_IIDX_STAT_DIO29 = 14 , # [doc = "15: DIO30"]
INT_EVENT2_IIDX_STAT_DIO30 = 15 , # [doc = "16: DIO31"]
INT_EVENT2_IIDX_STAT_DIO31 = 16 , } impl From < INT_EVENT2_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT2_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT2_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT2_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT2_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO16) , 2 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO17) , 3 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO18) , 4 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO19) , 5 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO20) , 6 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO21) , 7 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO22) , 8 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO23) , 9 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO24) , 10 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO25) , 11 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO26) , 12 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO27) , 13 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO28) , 14 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO29) , 15 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO30) , 16 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO31) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR } # [doc = "DIO16"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio16 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO16 } # [doc = "DIO17"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio17 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO17 } # [doc = "DIO18"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio18 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO18 } # [doc = "DIO19"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio19 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO19 } # [doc = "DIO20"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio20 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO20 } # [doc = "DIO21"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio21 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO21 } # [doc = "DIO22"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio22 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO22 } # [doc = "DIO23"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio23 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO23 } # [doc = "DIO24"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio24 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO24 } # [doc = "DIO25"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio25 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO25 } # [doc = "DIO26"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio26 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO26 } # [doc = "DIO27"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio27 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO27 } # [doc = "DIO28"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio28 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO28 } # [doc = "DIO29"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio29 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO29 } # [doc = "DIO30"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio30 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO30 } # [doc = "DIO31"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_dio31 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_DIO31 } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn int_event2_iidx_stat (& self) -> INT_EVENT2_IIDX_STAT_R { INT_EVENT2_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT2_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_imask`]
module"]
pub type INT_EVENT2_IMASK = crate :: Reg < int_event2_imask :: INT_EVENT2_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event2_imask { # [doc = "Register `INT_EVENT2_IMASK` reader"]
pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"]
pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_DIO16` reader - DIO16 event mask"]
pub type INT_EVENT2_IMASK_DIO16_R = crate :: BitReader < INT_EVENT2_IMASK_DIO16_A > ; # [doc = "DIO16 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO16_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO16_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO16_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO16_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO16_A { match self . bits { false => INT_EVENT2_IMASK_DIO16_A :: INT_EVENT2_IMASK_DIO16_CLR , true => INT_EVENT2_IMASK_DIO16_A :: INT_EVENT2_IMASK_DIO16_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio16_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO16_A :: INT_EVENT2_IMASK_DIO16_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio16_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO16_A :: INT_EVENT2_IMASK_DIO16_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO16` writer - DIO16 event mask"]
pub type INT_EVENT2_IMASK_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO16_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO16_A :: INT_EVENT2_IMASK_DIO16_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO16_A :: INT_EVENT2_IMASK_DIO16_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO17` reader - DIO17 event mask"]
pub type INT_EVENT2_IMASK_DIO17_R = crate :: BitReader < INT_EVENT2_IMASK_DIO17_A > ; # [doc = "DIO17 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO17_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO17_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO17_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO17_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO17_A { match self . bits { false => INT_EVENT2_IMASK_DIO17_A :: INT_EVENT2_IMASK_DIO17_CLR , true => INT_EVENT2_IMASK_DIO17_A :: INT_EVENT2_IMASK_DIO17_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio17_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO17_A :: INT_EVENT2_IMASK_DIO17_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio17_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO17_A :: INT_EVENT2_IMASK_DIO17_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO17` writer - DIO17 event mask"]
pub type INT_EVENT2_IMASK_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO17_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO17_A :: INT_EVENT2_IMASK_DIO17_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO17_A :: INT_EVENT2_IMASK_DIO17_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO18` reader - DIO18 event mask"]
pub type INT_EVENT2_IMASK_DIO18_R = crate :: BitReader < INT_EVENT2_IMASK_DIO18_A > ; # [doc = "DIO18 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO18_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO18_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO18_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO18_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO18_A { match self . bits { false => INT_EVENT2_IMASK_DIO18_A :: INT_EVENT2_IMASK_DIO18_CLR , true => INT_EVENT2_IMASK_DIO18_A :: INT_EVENT2_IMASK_DIO18_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio18_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO18_A :: INT_EVENT2_IMASK_DIO18_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio18_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO18_A :: INT_EVENT2_IMASK_DIO18_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO18` writer - DIO18 event mask"]
pub type INT_EVENT2_IMASK_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO18_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO18_A :: INT_EVENT2_IMASK_DIO18_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO18_A :: INT_EVENT2_IMASK_DIO18_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO19` reader - DIO19 event mask"]
pub type INT_EVENT2_IMASK_DIO19_R = crate :: BitReader < INT_EVENT2_IMASK_DIO19_A > ; # [doc = "DIO19 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO19_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO19_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO19_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO19_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO19_A { match self . bits { false => INT_EVENT2_IMASK_DIO19_A :: INT_EVENT2_IMASK_DIO19_CLR , true => INT_EVENT2_IMASK_DIO19_A :: INT_EVENT2_IMASK_DIO19_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio19_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO19_A :: INT_EVENT2_IMASK_DIO19_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio19_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO19_A :: INT_EVENT2_IMASK_DIO19_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO19` writer - DIO19 event mask"]
pub type INT_EVENT2_IMASK_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO19_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO19_A :: INT_EVENT2_IMASK_DIO19_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO19_A :: INT_EVENT2_IMASK_DIO19_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO20` reader - DIO20 event mask"]
pub type INT_EVENT2_IMASK_DIO20_R = crate :: BitReader < INT_EVENT2_IMASK_DIO20_A > ; # [doc = "DIO20 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO20_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO20_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO20_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO20_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO20_A { match self . bits { false => INT_EVENT2_IMASK_DIO20_A :: INT_EVENT2_IMASK_DIO20_CLR , true => INT_EVENT2_IMASK_DIO20_A :: INT_EVENT2_IMASK_DIO20_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio20_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO20_A :: INT_EVENT2_IMASK_DIO20_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio20_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO20_A :: INT_EVENT2_IMASK_DIO20_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO20` writer - DIO20 event mask"]
pub type INT_EVENT2_IMASK_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO20_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO20_A :: INT_EVENT2_IMASK_DIO20_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO20_A :: INT_EVENT2_IMASK_DIO20_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO21` reader - DIO21 event mask"]
pub type INT_EVENT2_IMASK_DIO21_R = crate :: BitReader < INT_EVENT2_IMASK_DIO21_A > ; # [doc = "DIO21 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO21_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO21_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO21_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO21_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO21_A { match self . bits { false => INT_EVENT2_IMASK_DIO21_A :: INT_EVENT2_IMASK_DIO21_CLR , true => INT_EVENT2_IMASK_DIO21_A :: INT_EVENT2_IMASK_DIO21_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio21_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO21_A :: INT_EVENT2_IMASK_DIO21_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio21_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO21_A :: INT_EVENT2_IMASK_DIO21_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO21` writer - DIO21 event mask"]
pub type INT_EVENT2_IMASK_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO21_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO21_A :: INT_EVENT2_IMASK_DIO21_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO21_A :: INT_EVENT2_IMASK_DIO21_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO22` reader - DIO22 event mask"]
pub type INT_EVENT2_IMASK_DIO22_R = crate :: BitReader < INT_EVENT2_IMASK_DIO22_A > ; # [doc = "DIO22 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO22_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO22_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO22_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO22_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO22_A { match self . bits { false => INT_EVENT2_IMASK_DIO22_A :: INT_EVENT2_IMASK_DIO22_CLR , true => INT_EVENT2_IMASK_DIO22_A :: INT_EVENT2_IMASK_DIO22_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio22_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO22_A :: INT_EVENT2_IMASK_DIO22_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio22_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO22_A :: INT_EVENT2_IMASK_DIO22_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO22` writer - DIO22 event mask"]
pub type INT_EVENT2_IMASK_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO22_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO22_A :: INT_EVENT2_IMASK_DIO22_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO22_A :: INT_EVENT2_IMASK_DIO22_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO23` reader - DIO23 event mask"]
pub type INT_EVENT2_IMASK_DIO23_R = crate :: BitReader < INT_EVENT2_IMASK_DIO23_A > ; # [doc = "DIO23 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO23_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO23_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO23_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO23_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO23_A { match self . bits { false => INT_EVENT2_IMASK_DIO23_A :: INT_EVENT2_IMASK_DIO23_CLR , true => INT_EVENT2_IMASK_DIO23_A :: INT_EVENT2_IMASK_DIO23_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio23_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO23_A :: INT_EVENT2_IMASK_DIO23_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio23_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO23_A :: INT_EVENT2_IMASK_DIO23_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO23` writer - DIO23 event mask"]
pub type INT_EVENT2_IMASK_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO23_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO23_A :: INT_EVENT2_IMASK_DIO23_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO23_A :: INT_EVENT2_IMASK_DIO23_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO24` reader - DIO24 event mask"]
pub type INT_EVENT2_IMASK_DIO24_R = crate :: BitReader < INT_EVENT2_IMASK_DIO24_A > ; # [doc = "DIO24 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO24_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO24_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO24_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO24_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO24_A { match self . bits { false => INT_EVENT2_IMASK_DIO24_A :: INT_EVENT2_IMASK_DIO24_CLR , true => INT_EVENT2_IMASK_DIO24_A :: INT_EVENT2_IMASK_DIO24_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio24_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO24_A :: INT_EVENT2_IMASK_DIO24_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio24_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO24_A :: INT_EVENT2_IMASK_DIO24_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO24` writer - DIO24 event mask"]
pub type INT_EVENT2_IMASK_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO24_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO24_A :: INT_EVENT2_IMASK_DIO24_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO24_A :: INT_EVENT2_IMASK_DIO24_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO25` reader - DIO25 event mask"]
pub type INT_EVENT2_IMASK_DIO25_R = crate :: BitReader < INT_EVENT2_IMASK_DIO25_A > ; # [doc = "DIO25 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO25_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO25_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO25_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO25_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO25_A { match self . bits { false => INT_EVENT2_IMASK_DIO25_A :: INT_EVENT2_IMASK_DIO25_CLR , true => INT_EVENT2_IMASK_DIO25_A :: INT_EVENT2_IMASK_DIO25_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio25_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO25_A :: INT_EVENT2_IMASK_DIO25_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio25_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO25_A :: INT_EVENT2_IMASK_DIO25_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO25` writer - DIO25 event mask"]
pub type INT_EVENT2_IMASK_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO25_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO25_A :: INT_EVENT2_IMASK_DIO25_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO25_A :: INT_EVENT2_IMASK_DIO25_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO26` reader - DIO26 event mask"]
pub type INT_EVENT2_IMASK_DIO26_R = crate :: BitReader < INT_EVENT2_IMASK_DIO26_A > ; # [doc = "DIO26 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO26_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO26_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO26_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO26_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO26_A { match self . bits { false => INT_EVENT2_IMASK_DIO26_A :: INT_EVENT2_IMASK_DIO26_CLR , true => INT_EVENT2_IMASK_DIO26_A :: INT_EVENT2_IMASK_DIO26_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio26_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO26_A :: INT_EVENT2_IMASK_DIO26_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio26_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO26_A :: INT_EVENT2_IMASK_DIO26_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO26` writer - DIO26 event mask"]
pub type INT_EVENT2_IMASK_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO26_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO26_A :: INT_EVENT2_IMASK_DIO26_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO26_A :: INT_EVENT2_IMASK_DIO26_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO27` reader - DIO27 event mask"]
pub type INT_EVENT2_IMASK_DIO27_R = crate :: BitReader < INT_EVENT2_IMASK_DIO27_A > ; # [doc = "DIO27 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO27_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO27_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO27_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO27_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO27_A { match self . bits { false => INT_EVENT2_IMASK_DIO27_A :: INT_EVENT2_IMASK_DIO27_CLR , true => INT_EVENT2_IMASK_DIO27_A :: INT_EVENT2_IMASK_DIO27_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio27_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO27_A :: INT_EVENT2_IMASK_DIO27_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio27_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO27_A :: INT_EVENT2_IMASK_DIO27_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO27` writer - DIO27 event mask"]
pub type INT_EVENT2_IMASK_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO27_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO27_A :: INT_EVENT2_IMASK_DIO27_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO27_A :: INT_EVENT2_IMASK_DIO27_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO28` reader - DIO28 event mask"]
pub type INT_EVENT2_IMASK_DIO28_R = crate :: BitReader < INT_EVENT2_IMASK_DIO28_A > ; # [doc = "DIO28 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO28_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO28_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO28_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO28_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO28_A { match self . bits { false => INT_EVENT2_IMASK_DIO28_A :: INT_EVENT2_IMASK_DIO28_CLR , true => INT_EVENT2_IMASK_DIO28_A :: INT_EVENT2_IMASK_DIO28_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio28_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO28_A :: INT_EVENT2_IMASK_DIO28_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio28_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO28_A :: INT_EVENT2_IMASK_DIO28_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO28` writer - DIO28 event mask"]
pub type INT_EVENT2_IMASK_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO28_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO28_A :: INT_EVENT2_IMASK_DIO28_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO28_A :: INT_EVENT2_IMASK_DIO28_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO29` reader - DIO29 event mask"]
pub type INT_EVENT2_IMASK_DIO29_R = crate :: BitReader < INT_EVENT2_IMASK_DIO29_A > ; # [doc = "DIO29 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO29_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO29_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO29_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO29_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO29_A { match self . bits { false => INT_EVENT2_IMASK_DIO29_A :: INT_EVENT2_IMASK_DIO29_CLR , true => INT_EVENT2_IMASK_DIO29_A :: INT_EVENT2_IMASK_DIO29_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio29_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO29_A :: INT_EVENT2_IMASK_DIO29_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio29_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO29_A :: INT_EVENT2_IMASK_DIO29_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO29` writer - DIO29 event mask"]
pub type INT_EVENT2_IMASK_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO29_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO29_A :: INT_EVENT2_IMASK_DIO29_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO29_A :: INT_EVENT2_IMASK_DIO29_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO30` reader - DIO30 event mask"]
pub type INT_EVENT2_IMASK_DIO30_R = crate :: BitReader < INT_EVENT2_IMASK_DIO30_A > ; # [doc = "DIO30 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO30_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO30_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO30_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO30_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO30_A { match self . bits { false => INT_EVENT2_IMASK_DIO30_A :: INT_EVENT2_IMASK_DIO30_CLR , true => INT_EVENT2_IMASK_DIO30_A :: INT_EVENT2_IMASK_DIO30_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio30_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO30_A :: INT_EVENT2_IMASK_DIO30_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio30_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO30_A :: INT_EVENT2_IMASK_DIO30_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO30` writer - DIO30 event mask"]
pub type INT_EVENT2_IMASK_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO30_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO30_A :: INT_EVENT2_IMASK_DIO30_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO30_A :: INT_EVENT2_IMASK_DIO30_SET) } } # [doc = "Field `INT_EVENT2_IMASK_DIO31` reader - DIO31 event mask"]
pub type INT_EVENT2_IMASK_DIO31_R = crate :: BitReader < INT_EVENT2_IMASK_DIO31_A > ; # [doc = "DIO31 event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_DIO31_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_DIO31_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_DIO31_SET = 1 , } impl From < INT_EVENT2_IMASK_DIO31_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_DIO31_A { match self . bits { false => INT_EVENT2_IMASK_DIO31_A :: INT_EVENT2_IMASK_DIO31_CLR , true => INT_EVENT2_IMASK_DIO31_A :: INT_EVENT2_IMASK_DIO31_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_dio31_clr (& self) -> bool { * self == INT_EVENT2_IMASK_DIO31_A :: INT_EVENT2_IMASK_DIO31_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_dio31_set (& self) -> bool { * self == INT_EVENT2_IMASK_DIO31_A :: INT_EVENT2_IMASK_DIO31_SET } } # [doc = "Field `INT_EVENT2_IMASK_DIO31` writer - DIO31 event mask"]
pub type INT_EVENT2_IMASK_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_DIO31_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO31_A :: INT_EVENT2_IMASK_DIO31_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_DIO31_A :: INT_EVENT2_IMASK_DIO31_SET) } } impl R { # [doc = "Bit 16 - DIO16 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio16 (& self) -> INT_EVENT2_IMASK_DIO16_R { INT_EVENT2_IMASK_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio17 (& self) -> INT_EVENT2_IMASK_DIO17_R { INT_EVENT2_IMASK_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio18 (& self) -> INT_EVENT2_IMASK_DIO18_R { INT_EVENT2_IMASK_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio19 (& self) -> INT_EVENT2_IMASK_DIO19_R { INT_EVENT2_IMASK_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio20 (& self) -> INT_EVENT2_IMASK_DIO20_R { INT_EVENT2_IMASK_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio21 (& self) -> INT_EVENT2_IMASK_DIO21_R { INT_EVENT2_IMASK_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio22 (& self) -> INT_EVENT2_IMASK_DIO22_R { INT_EVENT2_IMASK_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio23 (& self) -> INT_EVENT2_IMASK_DIO23_R { INT_EVENT2_IMASK_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio24 (& self) -> INT_EVENT2_IMASK_DIO24_R { INT_EVENT2_IMASK_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio25 (& self) -> INT_EVENT2_IMASK_DIO25_R { INT_EVENT2_IMASK_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio26 (& self) -> INT_EVENT2_IMASK_DIO26_R { INT_EVENT2_IMASK_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio27 (& self) -> INT_EVENT2_IMASK_DIO27_R { INT_EVENT2_IMASK_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio28 (& self) -> INT_EVENT2_IMASK_DIO28_R { INT_EVENT2_IMASK_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio29 (& self) -> INT_EVENT2_IMASK_DIO29_R { INT_EVENT2_IMASK_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio30 (& self) -> INT_EVENT2_IMASK_DIO30_R { INT_EVENT2_IMASK_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event mask"]
# [inline (always)]
pub fn int_event2_imask_dio31 (& self) -> INT_EVENT2_IMASK_DIO31_R { INT_EVENT2_IMASK_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 16 - DIO16 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio16 (& mut self) -> INT_EVENT2_IMASK_DIO16_W < INT_EVENT2_IMASK_SPEC , 16 > { INT_EVENT2_IMASK_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio17 (& mut self) -> INT_EVENT2_IMASK_DIO17_W < INT_EVENT2_IMASK_SPEC , 17 > { INT_EVENT2_IMASK_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio18 (& mut self) -> INT_EVENT2_IMASK_DIO18_W < INT_EVENT2_IMASK_SPEC , 18 > { INT_EVENT2_IMASK_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio19 (& mut self) -> INT_EVENT2_IMASK_DIO19_W < INT_EVENT2_IMASK_SPEC , 19 > { INT_EVENT2_IMASK_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio20 (& mut self) -> INT_EVENT2_IMASK_DIO20_W < INT_EVENT2_IMASK_SPEC , 20 > { INT_EVENT2_IMASK_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio21 (& mut self) -> INT_EVENT2_IMASK_DIO21_W < INT_EVENT2_IMASK_SPEC , 21 > { INT_EVENT2_IMASK_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio22 (& mut self) -> INT_EVENT2_IMASK_DIO22_W < INT_EVENT2_IMASK_SPEC , 22 > { INT_EVENT2_IMASK_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio23 (& mut self) -> INT_EVENT2_IMASK_DIO23_W < INT_EVENT2_IMASK_SPEC , 23 > { INT_EVENT2_IMASK_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio24 (& mut self) -> INT_EVENT2_IMASK_DIO24_W < INT_EVENT2_IMASK_SPEC , 24 > { INT_EVENT2_IMASK_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio25 (& mut self) -> INT_EVENT2_IMASK_DIO25_W < INT_EVENT2_IMASK_SPEC , 25 > { INT_EVENT2_IMASK_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio26 (& mut self) -> INT_EVENT2_IMASK_DIO26_W < INT_EVENT2_IMASK_SPEC , 26 > { INT_EVENT2_IMASK_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio27 (& mut self) -> INT_EVENT2_IMASK_DIO27_W < INT_EVENT2_IMASK_SPEC , 27 > { INT_EVENT2_IMASK_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio28 (& mut self) -> INT_EVENT2_IMASK_DIO28_W < INT_EVENT2_IMASK_SPEC , 28 > { INT_EVENT2_IMASK_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio29 (& mut self) -> INT_EVENT2_IMASK_DIO29_W < INT_EVENT2_IMASK_SPEC , 29 > { INT_EVENT2_IMASK_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio30 (& mut self) -> INT_EVENT2_IMASK_DIO30_W < INT_EVENT2_IMASK_SPEC , 30 > { INT_EVENT2_IMASK_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event mask"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_dio31 (& mut self) -> INT_EVENT2_IMASK_DIO31_W < INT_EVENT2_IMASK_SPEC , 31 > { INT_EVENT2_IMASK_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_ris`]
module"]
pub type INT_EVENT2_RIS = crate :: Reg < int_event2_ris :: INT_EVENT2_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event2_ris { # [doc = "Register `INT_EVENT2_RIS` reader"]
pub type R = crate :: R < INT_EVENT2_RIS_SPEC > ; # [doc = "Field `INT_EVENT2_RIS_DIO16` reader - DIO16 event"]
pub type INT_EVENT2_RIS_DIO16_R = crate :: BitReader < INT_EVENT2_RIS_DIO16_A > ; # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO16_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO16_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO16_SET = 1 , } impl From < INT_EVENT2_RIS_DIO16_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO16_A { match self . bits { false => INT_EVENT2_RIS_DIO16_A :: INT_EVENT2_RIS_DIO16_CLR , true => INT_EVENT2_RIS_DIO16_A :: INT_EVENT2_RIS_DIO16_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio16_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO16_A :: INT_EVENT2_RIS_DIO16_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio16_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO16_A :: INT_EVENT2_RIS_DIO16_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO17` reader - DIO17 event"]
pub type INT_EVENT2_RIS_DIO17_R = crate :: BitReader < INT_EVENT2_RIS_DIO17_A > ; # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO17_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO17_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO17_SET = 1 , } impl From < INT_EVENT2_RIS_DIO17_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO17_A { match self . bits { false => INT_EVENT2_RIS_DIO17_A :: INT_EVENT2_RIS_DIO17_CLR , true => INT_EVENT2_RIS_DIO17_A :: INT_EVENT2_RIS_DIO17_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio17_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO17_A :: INT_EVENT2_RIS_DIO17_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio17_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO17_A :: INT_EVENT2_RIS_DIO17_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO18` reader - DIO18 event"]
pub type INT_EVENT2_RIS_DIO18_R = crate :: BitReader < INT_EVENT2_RIS_DIO18_A > ; # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO18_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO18_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO18_SET = 1 , } impl From < INT_EVENT2_RIS_DIO18_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO18_A { match self . bits { false => INT_EVENT2_RIS_DIO18_A :: INT_EVENT2_RIS_DIO18_CLR , true => INT_EVENT2_RIS_DIO18_A :: INT_EVENT2_RIS_DIO18_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio18_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO18_A :: INT_EVENT2_RIS_DIO18_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio18_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO18_A :: INT_EVENT2_RIS_DIO18_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO19` reader - DIO19 event"]
pub type INT_EVENT2_RIS_DIO19_R = crate :: BitReader < INT_EVENT2_RIS_DIO19_A > ; # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO19_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO19_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO19_SET = 1 , } impl From < INT_EVENT2_RIS_DIO19_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO19_A { match self . bits { false => INT_EVENT2_RIS_DIO19_A :: INT_EVENT2_RIS_DIO19_CLR , true => INT_EVENT2_RIS_DIO19_A :: INT_EVENT2_RIS_DIO19_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio19_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO19_A :: INT_EVENT2_RIS_DIO19_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio19_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO19_A :: INT_EVENT2_RIS_DIO19_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO20` reader - DIO20 event"]
pub type INT_EVENT2_RIS_DIO20_R = crate :: BitReader < INT_EVENT2_RIS_DIO20_A > ; # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO20_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO20_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO20_SET = 1 , } impl From < INT_EVENT2_RIS_DIO20_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO20_A { match self . bits { false => INT_EVENT2_RIS_DIO20_A :: INT_EVENT2_RIS_DIO20_CLR , true => INT_EVENT2_RIS_DIO20_A :: INT_EVENT2_RIS_DIO20_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio20_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO20_A :: INT_EVENT2_RIS_DIO20_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio20_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO20_A :: INT_EVENT2_RIS_DIO20_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO21` reader - DIO21 event"]
pub type INT_EVENT2_RIS_DIO21_R = crate :: BitReader < INT_EVENT2_RIS_DIO21_A > ; # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO21_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO21_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO21_SET = 1 , } impl From < INT_EVENT2_RIS_DIO21_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO21_A { match self . bits { false => INT_EVENT2_RIS_DIO21_A :: INT_EVENT2_RIS_DIO21_CLR , true => INT_EVENT2_RIS_DIO21_A :: INT_EVENT2_RIS_DIO21_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio21_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO21_A :: INT_EVENT2_RIS_DIO21_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio21_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO21_A :: INT_EVENT2_RIS_DIO21_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO22` reader - DIO22 event"]
pub type INT_EVENT2_RIS_DIO22_R = crate :: BitReader < INT_EVENT2_RIS_DIO22_A > ; # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO22_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO22_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO22_SET = 1 , } impl From < INT_EVENT2_RIS_DIO22_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO22_A { match self . bits { false => INT_EVENT2_RIS_DIO22_A :: INT_EVENT2_RIS_DIO22_CLR , true => INT_EVENT2_RIS_DIO22_A :: INT_EVENT2_RIS_DIO22_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio22_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO22_A :: INT_EVENT2_RIS_DIO22_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio22_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO22_A :: INT_EVENT2_RIS_DIO22_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO23` reader - DIO23 event"]
pub type INT_EVENT2_RIS_DIO23_R = crate :: BitReader < INT_EVENT2_RIS_DIO23_A > ; # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO23_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO23_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO23_SET = 1 , } impl From < INT_EVENT2_RIS_DIO23_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO23_A { match self . bits { false => INT_EVENT2_RIS_DIO23_A :: INT_EVENT2_RIS_DIO23_CLR , true => INT_EVENT2_RIS_DIO23_A :: INT_EVENT2_RIS_DIO23_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio23_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO23_A :: INT_EVENT2_RIS_DIO23_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio23_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO23_A :: INT_EVENT2_RIS_DIO23_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO24` reader - DIO24 event"]
pub type INT_EVENT2_RIS_DIO24_R = crate :: BitReader < INT_EVENT2_RIS_DIO24_A > ; # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO24_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO24_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO24_SET = 1 , } impl From < INT_EVENT2_RIS_DIO24_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO24_A { match self . bits { false => INT_EVENT2_RIS_DIO24_A :: INT_EVENT2_RIS_DIO24_CLR , true => INT_EVENT2_RIS_DIO24_A :: INT_EVENT2_RIS_DIO24_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio24_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO24_A :: INT_EVENT2_RIS_DIO24_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio24_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO24_A :: INT_EVENT2_RIS_DIO24_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO25` reader - DIO25 event"]
pub type INT_EVENT2_RIS_DIO25_R = crate :: BitReader < INT_EVENT2_RIS_DIO25_A > ; # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO25_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO25_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO25_SET = 1 , } impl From < INT_EVENT2_RIS_DIO25_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO25_A { match self . bits { false => INT_EVENT2_RIS_DIO25_A :: INT_EVENT2_RIS_DIO25_CLR , true => INT_EVENT2_RIS_DIO25_A :: INT_EVENT2_RIS_DIO25_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio25_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO25_A :: INT_EVENT2_RIS_DIO25_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio25_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO25_A :: INT_EVENT2_RIS_DIO25_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO26` reader - DIO26 event"]
pub type INT_EVENT2_RIS_DIO26_R = crate :: BitReader < INT_EVENT2_RIS_DIO26_A > ; # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO26_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO26_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO26_SET = 1 , } impl From < INT_EVENT2_RIS_DIO26_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO26_A { match self . bits { false => INT_EVENT2_RIS_DIO26_A :: INT_EVENT2_RIS_DIO26_CLR , true => INT_EVENT2_RIS_DIO26_A :: INT_EVENT2_RIS_DIO26_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio26_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO26_A :: INT_EVENT2_RIS_DIO26_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio26_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO26_A :: INT_EVENT2_RIS_DIO26_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO27` reader - DIO27 event"]
pub type INT_EVENT2_RIS_DIO27_R = crate :: BitReader < INT_EVENT2_RIS_DIO27_A > ; # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO27_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO27_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO27_SET = 1 , } impl From < INT_EVENT2_RIS_DIO27_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO27_A { match self . bits { false => INT_EVENT2_RIS_DIO27_A :: INT_EVENT2_RIS_DIO27_CLR , true => INT_EVENT2_RIS_DIO27_A :: INT_EVENT2_RIS_DIO27_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio27_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO27_A :: INT_EVENT2_RIS_DIO27_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio27_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO27_A :: INT_EVENT2_RIS_DIO27_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO28` reader - DIO28 event"]
pub type INT_EVENT2_RIS_DIO28_R = crate :: BitReader < INT_EVENT2_RIS_DIO28_A > ; # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO28_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO28_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO28_SET = 1 , } impl From < INT_EVENT2_RIS_DIO28_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO28_A { match self . bits { false => INT_EVENT2_RIS_DIO28_A :: INT_EVENT2_RIS_DIO28_CLR , true => INT_EVENT2_RIS_DIO28_A :: INT_EVENT2_RIS_DIO28_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio28_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO28_A :: INT_EVENT2_RIS_DIO28_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio28_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO28_A :: INT_EVENT2_RIS_DIO28_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO29` reader - DIO29 event"]
pub type INT_EVENT2_RIS_DIO29_R = crate :: BitReader < INT_EVENT2_RIS_DIO29_A > ; # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO29_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO29_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO29_SET = 1 , } impl From < INT_EVENT2_RIS_DIO29_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO29_A { match self . bits { false => INT_EVENT2_RIS_DIO29_A :: INT_EVENT2_RIS_DIO29_CLR , true => INT_EVENT2_RIS_DIO29_A :: INT_EVENT2_RIS_DIO29_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio29_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO29_A :: INT_EVENT2_RIS_DIO29_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio29_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO29_A :: INT_EVENT2_RIS_DIO29_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO30` reader - DIO30 event"]
pub type INT_EVENT2_RIS_DIO30_R = crate :: BitReader < INT_EVENT2_RIS_DIO30_A > ; # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO30_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO30_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO30_SET = 1 , } impl From < INT_EVENT2_RIS_DIO30_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO30_A { match self . bits { false => INT_EVENT2_RIS_DIO30_A :: INT_EVENT2_RIS_DIO30_CLR , true => INT_EVENT2_RIS_DIO30_A :: INT_EVENT2_RIS_DIO30_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio30_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO30_A :: INT_EVENT2_RIS_DIO30_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio30_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO30_A :: INT_EVENT2_RIS_DIO30_SET } } # [doc = "Field `INT_EVENT2_RIS_DIO31` reader - DIO31 event"]
pub type INT_EVENT2_RIS_DIO31_R = crate :: BitReader < INT_EVENT2_RIS_DIO31_A > ; # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_DIO31_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_DIO31_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_DIO31_SET = 1 , } impl From < INT_EVENT2_RIS_DIO31_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_DIO31_A { match self . bits { false => INT_EVENT2_RIS_DIO31_A :: INT_EVENT2_RIS_DIO31_CLR , true => INT_EVENT2_RIS_DIO31_A :: INT_EVENT2_RIS_DIO31_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_dio31_clr (& self) -> bool { * self == INT_EVENT2_RIS_DIO31_A :: INT_EVENT2_RIS_DIO31_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_dio31_set (& self) -> bool { * self == INT_EVENT2_RIS_DIO31_A :: INT_EVENT2_RIS_DIO31_SET } } impl R { # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
pub fn int_event2_ris_dio16 (& self) -> INT_EVENT2_RIS_DIO16_R { INT_EVENT2_RIS_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
pub fn int_event2_ris_dio17 (& self) -> INT_EVENT2_RIS_DIO17_R { INT_EVENT2_RIS_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
pub fn int_event2_ris_dio18 (& self) -> INT_EVENT2_RIS_DIO18_R { INT_EVENT2_RIS_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
pub fn int_event2_ris_dio19 (& self) -> INT_EVENT2_RIS_DIO19_R { INT_EVENT2_RIS_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
pub fn int_event2_ris_dio20 (& self) -> INT_EVENT2_RIS_DIO20_R { INT_EVENT2_RIS_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
pub fn int_event2_ris_dio21 (& self) -> INT_EVENT2_RIS_DIO21_R { INT_EVENT2_RIS_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
pub fn int_event2_ris_dio22 (& self) -> INT_EVENT2_RIS_DIO22_R { INT_EVENT2_RIS_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
pub fn int_event2_ris_dio23 (& self) -> INT_EVENT2_RIS_DIO23_R { INT_EVENT2_RIS_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
pub fn int_event2_ris_dio24 (& self) -> INT_EVENT2_RIS_DIO24_R { INT_EVENT2_RIS_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
pub fn int_event2_ris_dio25 (& self) -> INT_EVENT2_RIS_DIO25_R { INT_EVENT2_RIS_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
pub fn int_event2_ris_dio26 (& self) -> INT_EVENT2_RIS_DIO26_R { INT_EVENT2_RIS_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
pub fn int_event2_ris_dio27 (& self) -> INT_EVENT2_RIS_DIO27_R { INT_EVENT2_RIS_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
pub fn int_event2_ris_dio28 (& self) -> INT_EVENT2_RIS_DIO28_R { INT_EVENT2_RIS_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
pub fn int_event2_ris_dio29 (& self) -> INT_EVENT2_RIS_DIO29_R { INT_EVENT2_RIS_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
pub fn int_event2_ris_dio30 (& self) -> INT_EVENT2_RIS_DIO30_R { INT_EVENT2_RIS_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
pub fn int_event2_ris_dio31 (& self) -> INT_EVENT2_RIS_DIO31_R { INT_EVENT2_RIS_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_RIS to value 0"]
impl crate :: Resettable for INT_EVENT2_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_mis`]
module"]
pub type INT_EVENT2_MIS = crate :: Reg < int_event2_mis :: INT_EVENT2_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event2_mis { # [doc = "Register `INT_EVENT2_MIS` reader"]
pub type R = crate :: R < INT_EVENT2_MIS_SPEC > ; # [doc = "Field `INT_EVENT2_MIS_DIO16` reader - DIO16 event"]
pub type INT_EVENT2_MIS_DIO16_R = crate :: BitReader < INT_EVENT2_MIS_DIO16_A > ; # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO16_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO16_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO16_SET = 1 , } impl From < INT_EVENT2_MIS_DIO16_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO16_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO16_A { match self . bits { false => INT_EVENT2_MIS_DIO16_A :: INT_EVENT2_MIS_DIO16_CLR , true => INT_EVENT2_MIS_DIO16_A :: INT_EVENT2_MIS_DIO16_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio16_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO16_A :: INT_EVENT2_MIS_DIO16_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio16_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO16_A :: INT_EVENT2_MIS_DIO16_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO17` reader - DIO17 event"]
pub type INT_EVENT2_MIS_DIO17_R = crate :: BitReader < INT_EVENT2_MIS_DIO17_A > ; # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO17_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO17_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO17_SET = 1 , } impl From < INT_EVENT2_MIS_DIO17_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO17_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO17_A { match self . bits { false => INT_EVENT2_MIS_DIO17_A :: INT_EVENT2_MIS_DIO17_CLR , true => INT_EVENT2_MIS_DIO17_A :: INT_EVENT2_MIS_DIO17_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio17_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO17_A :: INT_EVENT2_MIS_DIO17_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio17_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO17_A :: INT_EVENT2_MIS_DIO17_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO18` reader - DIO18 event"]
pub type INT_EVENT2_MIS_DIO18_R = crate :: BitReader < INT_EVENT2_MIS_DIO18_A > ; # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO18_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO18_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO18_SET = 1 , } impl From < INT_EVENT2_MIS_DIO18_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO18_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO18_A { match self . bits { false => INT_EVENT2_MIS_DIO18_A :: INT_EVENT2_MIS_DIO18_CLR , true => INT_EVENT2_MIS_DIO18_A :: INT_EVENT2_MIS_DIO18_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio18_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO18_A :: INT_EVENT2_MIS_DIO18_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio18_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO18_A :: INT_EVENT2_MIS_DIO18_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO19` reader - DIO19 event"]
pub type INT_EVENT2_MIS_DIO19_R = crate :: BitReader < INT_EVENT2_MIS_DIO19_A > ; # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO19_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO19_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO19_SET = 1 , } impl From < INT_EVENT2_MIS_DIO19_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO19_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO19_A { match self . bits { false => INT_EVENT2_MIS_DIO19_A :: INT_EVENT2_MIS_DIO19_CLR , true => INT_EVENT2_MIS_DIO19_A :: INT_EVENT2_MIS_DIO19_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio19_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO19_A :: INT_EVENT2_MIS_DIO19_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio19_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO19_A :: INT_EVENT2_MIS_DIO19_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO20` reader - DIO20 event"]
pub type INT_EVENT2_MIS_DIO20_R = crate :: BitReader < INT_EVENT2_MIS_DIO20_A > ; # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO20_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO20_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO20_SET = 1 , } impl From < INT_EVENT2_MIS_DIO20_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO20_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO20_A { match self . bits { false => INT_EVENT2_MIS_DIO20_A :: INT_EVENT2_MIS_DIO20_CLR , true => INT_EVENT2_MIS_DIO20_A :: INT_EVENT2_MIS_DIO20_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio20_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO20_A :: INT_EVENT2_MIS_DIO20_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio20_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO20_A :: INT_EVENT2_MIS_DIO20_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO21` reader - DIO21 event"]
pub type INT_EVENT2_MIS_DIO21_R = crate :: BitReader < INT_EVENT2_MIS_DIO21_A > ; # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO21_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO21_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO21_SET = 1 , } impl From < INT_EVENT2_MIS_DIO21_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO21_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO21_A { match self . bits { false => INT_EVENT2_MIS_DIO21_A :: INT_EVENT2_MIS_DIO21_CLR , true => INT_EVENT2_MIS_DIO21_A :: INT_EVENT2_MIS_DIO21_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio21_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO21_A :: INT_EVENT2_MIS_DIO21_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio21_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO21_A :: INT_EVENT2_MIS_DIO21_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO22` reader - DIO22 event"]
pub type INT_EVENT2_MIS_DIO22_R = crate :: BitReader < INT_EVENT2_MIS_DIO22_A > ; # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO22_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO22_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO22_SET = 1 , } impl From < INT_EVENT2_MIS_DIO22_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO22_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO22_A { match self . bits { false => INT_EVENT2_MIS_DIO22_A :: INT_EVENT2_MIS_DIO22_CLR , true => INT_EVENT2_MIS_DIO22_A :: INT_EVENT2_MIS_DIO22_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio22_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO22_A :: INT_EVENT2_MIS_DIO22_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio22_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO22_A :: INT_EVENT2_MIS_DIO22_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO23` reader - DIO23 event"]
pub type INT_EVENT2_MIS_DIO23_R = crate :: BitReader < INT_EVENT2_MIS_DIO23_A > ; # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO23_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO23_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO23_SET = 1 , } impl From < INT_EVENT2_MIS_DIO23_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO23_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO23_A { match self . bits { false => INT_EVENT2_MIS_DIO23_A :: INT_EVENT2_MIS_DIO23_CLR , true => INT_EVENT2_MIS_DIO23_A :: INT_EVENT2_MIS_DIO23_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio23_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO23_A :: INT_EVENT2_MIS_DIO23_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio23_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO23_A :: INT_EVENT2_MIS_DIO23_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO24` reader - DIO24 event"]
pub type INT_EVENT2_MIS_DIO24_R = crate :: BitReader < INT_EVENT2_MIS_DIO24_A > ; # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO24_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO24_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO24_SET = 1 , } impl From < INT_EVENT2_MIS_DIO24_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO24_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO24_A { match self . bits { false => INT_EVENT2_MIS_DIO24_A :: INT_EVENT2_MIS_DIO24_CLR , true => INT_EVENT2_MIS_DIO24_A :: INT_EVENT2_MIS_DIO24_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio24_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO24_A :: INT_EVENT2_MIS_DIO24_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio24_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO24_A :: INT_EVENT2_MIS_DIO24_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO25` reader - DIO25 event"]
pub type INT_EVENT2_MIS_DIO25_R = crate :: BitReader < INT_EVENT2_MIS_DIO25_A > ; # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO25_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO25_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO25_SET = 1 , } impl From < INT_EVENT2_MIS_DIO25_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO25_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO25_A { match self . bits { false => INT_EVENT2_MIS_DIO25_A :: INT_EVENT2_MIS_DIO25_CLR , true => INT_EVENT2_MIS_DIO25_A :: INT_EVENT2_MIS_DIO25_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio25_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO25_A :: INT_EVENT2_MIS_DIO25_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio25_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO25_A :: INT_EVENT2_MIS_DIO25_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO26` reader - DIO26 event"]
pub type INT_EVENT2_MIS_DIO26_R = crate :: BitReader < INT_EVENT2_MIS_DIO26_A > ; # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO26_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO26_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO26_SET = 1 , } impl From < INT_EVENT2_MIS_DIO26_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO26_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO26_A { match self . bits { false => INT_EVENT2_MIS_DIO26_A :: INT_EVENT2_MIS_DIO26_CLR , true => INT_EVENT2_MIS_DIO26_A :: INT_EVENT2_MIS_DIO26_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio26_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO26_A :: INT_EVENT2_MIS_DIO26_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio26_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO26_A :: INT_EVENT2_MIS_DIO26_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO27` reader - DIO27 event"]
pub type INT_EVENT2_MIS_DIO27_R = crate :: BitReader < INT_EVENT2_MIS_DIO27_A > ; # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO27_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO27_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO27_SET = 1 , } impl From < INT_EVENT2_MIS_DIO27_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO27_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO27_A { match self . bits { false => INT_EVENT2_MIS_DIO27_A :: INT_EVENT2_MIS_DIO27_CLR , true => INT_EVENT2_MIS_DIO27_A :: INT_EVENT2_MIS_DIO27_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio27_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO27_A :: INT_EVENT2_MIS_DIO27_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio27_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO27_A :: INT_EVENT2_MIS_DIO27_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO28` reader - DIO28 event"]
pub type INT_EVENT2_MIS_DIO28_R = crate :: BitReader < INT_EVENT2_MIS_DIO28_A > ; # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO28_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO28_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO28_SET = 1 , } impl From < INT_EVENT2_MIS_DIO28_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO28_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO28_A { match self . bits { false => INT_EVENT2_MIS_DIO28_A :: INT_EVENT2_MIS_DIO28_CLR , true => INT_EVENT2_MIS_DIO28_A :: INT_EVENT2_MIS_DIO28_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio28_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO28_A :: INT_EVENT2_MIS_DIO28_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio28_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO28_A :: INT_EVENT2_MIS_DIO28_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO29` reader - DIO29 event"]
pub type INT_EVENT2_MIS_DIO29_R = crate :: BitReader < INT_EVENT2_MIS_DIO29_A > ; # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO29_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO29_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO29_SET = 1 , } impl From < INT_EVENT2_MIS_DIO29_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO29_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO29_A { match self . bits { false => INT_EVENT2_MIS_DIO29_A :: INT_EVENT2_MIS_DIO29_CLR , true => INT_EVENT2_MIS_DIO29_A :: INT_EVENT2_MIS_DIO29_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio29_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO29_A :: INT_EVENT2_MIS_DIO29_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio29_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO29_A :: INT_EVENT2_MIS_DIO29_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO30` reader - DIO30 event"]
pub type INT_EVENT2_MIS_DIO30_R = crate :: BitReader < INT_EVENT2_MIS_DIO30_A > ; # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO30_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO30_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO30_SET = 1 , } impl From < INT_EVENT2_MIS_DIO30_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO30_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO30_A { match self . bits { false => INT_EVENT2_MIS_DIO30_A :: INT_EVENT2_MIS_DIO30_CLR , true => INT_EVENT2_MIS_DIO30_A :: INT_EVENT2_MIS_DIO30_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio30_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO30_A :: INT_EVENT2_MIS_DIO30_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio30_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO30_A :: INT_EVENT2_MIS_DIO30_SET } } # [doc = "Field `INT_EVENT2_MIS_DIO31` reader - DIO31 event"]
pub type INT_EVENT2_MIS_DIO31_R = crate :: BitReader < INT_EVENT2_MIS_DIO31_A > ; # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_DIO31_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_DIO31_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_DIO31_SET = 1 , } impl From < INT_EVENT2_MIS_DIO31_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_DIO31_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_DIO31_A { match self . bits { false => INT_EVENT2_MIS_DIO31_A :: INT_EVENT2_MIS_DIO31_CLR , true => INT_EVENT2_MIS_DIO31_A :: INT_EVENT2_MIS_DIO31_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_dio31_clr (& self) -> bool { * self == INT_EVENT2_MIS_DIO31_A :: INT_EVENT2_MIS_DIO31_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_dio31_set (& self) -> bool { * self == INT_EVENT2_MIS_DIO31_A :: INT_EVENT2_MIS_DIO31_SET } } impl R { # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
pub fn int_event2_mis_dio16 (& self) -> INT_EVENT2_MIS_DIO16_R { INT_EVENT2_MIS_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
pub fn int_event2_mis_dio17 (& self) -> INT_EVENT2_MIS_DIO17_R { INT_EVENT2_MIS_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
pub fn int_event2_mis_dio18 (& self) -> INT_EVENT2_MIS_DIO18_R { INT_EVENT2_MIS_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
pub fn int_event2_mis_dio19 (& self) -> INT_EVENT2_MIS_DIO19_R { INT_EVENT2_MIS_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
pub fn int_event2_mis_dio20 (& self) -> INT_EVENT2_MIS_DIO20_R { INT_EVENT2_MIS_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
pub fn int_event2_mis_dio21 (& self) -> INT_EVENT2_MIS_DIO21_R { INT_EVENT2_MIS_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
pub fn int_event2_mis_dio22 (& self) -> INT_EVENT2_MIS_DIO22_R { INT_EVENT2_MIS_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
pub fn int_event2_mis_dio23 (& self) -> INT_EVENT2_MIS_DIO23_R { INT_EVENT2_MIS_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
pub fn int_event2_mis_dio24 (& self) -> INT_EVENT2_MIS_DIO24_R { INT_EVENT2_MIS_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
pub fn int_event2_mis_dio25 (& self) -> INT_EVENT2_MIS_DIO25_R { INT_EVENT2_MIS_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
pub fn int_event2_mis_dio26 (& self) -> INT_EVENT2_MIS_DIO26_R { INT_EVENT2_MIS_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
pub fn int_event2_mis_dio27 (& self) -> INT_EVENT2_MIS_DIO27_R { INT_EVENT2_MIS_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
pub fn int_event2_mis_dio28 (& self) -> INT_EVENT2_MIS_DIO28_R { INT_EVENT2_MIS_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
pub fn int_event2_mis_dio29 (& self) -> INT_EVENT2_MIS_DIO29_R { INT_EVENT2_MIS_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
pub fn int_event2_mis_dio30 (& self) -> INT_EVENT2_MIS_DIO30_R { INT_EVENT2_MIS_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
pub fn int_event2_mis_dio31 (& self) -> INT_EVENT2_MIS_DIO31_R { INT_EVENT2_MIS_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_MIS to value 0"]
impl crate :: Resettable for INT_EVENT2_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iset`]
module"]
pub type INT_EVENT2_ISET = crate :: Reg < int_event2_iset :: INT_EVENT2_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event2_iset { # [doc = "Register `INT_EVENT2_ISET` writer"]
pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO16_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO16_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO16_SET = 1 , } impl From < INT_EVENT2_ISET_DIO16_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO16` writer - DIO16 event"]
pub type INT_EVENT2_ISET_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO16_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO16_AW :: INT_EVENT2_ISET_DIO16_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO16_AW :: INT_EVENT2_ISET_DIO16_SET) } } # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO17_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO17_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO17_SET = 1 , } impl From < INT_EVENT2_ISET_DIO17_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO17` writer - DIO17 event"]
pub type INT_EVENT2_ISET_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO17_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO17_AW :: INT_EVENT2_ISET_DIO17_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO17_AW :: INT_EVENT2_ISET_DIO17_SET) } } # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO18_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO18_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO18_SET = 1 , } impl From < INT_EVENT2_ISET_DIO18_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO18` writer - DIO18 event"]
pub type INT_EVENT2_ISET_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO18_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO18_AW :: INT_EVENT2_ISET_DIO18_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO18_AW :: INT_EVENT2_ISET_DIO18_SET) } } # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO19_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO19_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO19_SET = 1 , } impl From < INT_EVENT2_ISET_DIO19_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO19` writer - DIO19 event"]
pub type INT_EVENT2_ISET_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO19_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO19_AW :: INT_EVENT2_ISET_DIO19_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO19_AW :: INT_EVENT2_ISET_DIO19_SET) } } # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO20_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO20_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO20_SET = 1 , } impl From < INT_EVENT2_ISET_DIO20_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO20` writer - DIO20 event"]
pub type INT_EVENT2_ISET_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO20_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO20_AW :: INT_EVENT2_ISET_DIO20_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO20_AW :: INT_EVENT2_ISET_DIO20_SET) } } # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO21_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO21_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO21_SET = 1 , } impl From < INT_EVENT2_ISET_DIO21_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO21` writer - DIO21 event"]
pub type INT_EVENT2_ISET_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO21_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO21_AW :: INT_EVENT2_ISET_DIO21_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO21_AW :: INT_EVENT2_ISET_DIO21_SET) } } # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO22_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO22_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO22_SET = 1 , } impl From < INT_EVENT2_ISET_DIO22_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO22` writer - DIO22 event"]
pub type INT_EVENT2_ISET_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO22_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO22_AW :: INT_EVENT2_ISET_DIO22_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO22_AW :: INT_EVENT2_ISET_DIO22_SET) } } # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO23_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO23_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO23_SET = 1 , } impl From < INT_EVENT2_ISET_DIO23_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO23` writer - DIO23 event"]
pub type INT_EVENT2_ISET_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO23_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO23_AW :: INT_EVENT2_ISET_DIO23_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO23_AW :: INT_EVENT2_ISET_DIO23_SET) } } # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO24_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO24_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO24_SET = 1 , } impl From < INT_EVENT2_ISET_DIO24_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO24` writer - DIO24 event"]
pub type INT_EVENT2_ISET_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO24_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO24_AW :: INT_EVENT2_ISET_DIO24_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO24_AW :: INT_EVENT2_ISET_DIO24_SET) } } # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO25_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO25_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO25_SET = 1 , } impl From < INT_EVENT2_ISET_DIO25_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO25` writer - DIO25 event"]
pub type INT_EVENT2_ISET_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO25_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO25_AW :: INT_EVENT2_ISET_DIO25_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO25_AW :: INT_EVENT2_ISET_DIO25_SET) } } # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO26_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO26_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO26_SET = 1 , } impl From < INT_EVENT2_ISET_DIO26_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO26` writer - DIO26 event"]
pub type INT_EVENT2_ISET_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO26_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO26_AW :: INT_EVENT2_ISET_DIO26_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO26_AW :: INT_EVENT2_ISET_DIO26_SET) } } # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO27_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO27_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO27_SET = 1 , } impl From < INT_EVENT2_ISET_DIO27_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO27` writer - DIO27 event"]
pub type INT_EVENT2_ISET_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO27_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO27_AW :: INT_EVENT2_ISET_DIO27_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO27_AW :: INT_EVENT2_ISET_DIO27_SET) } } # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO28_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO28_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO28_SET = 1 , } impl From < INT_EVENT2_ISET_DIO28_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO28` writer - DIO28 event"]
pub type INT_EVENT2_ISET_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO28_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO28_AW :: INT_EVENT2_ISET_DIO28_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO28_AW :: INT_EVENT2_ISET_DIO28_SET) } } # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO29_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO29_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO29_SET = 1 , } impl From < INT_EVENT2_ISET_DIO29_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO29` writer - DIO29 event"]
pub type INT_EVENT2_ISET_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO29_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO29_AW :: INT_EVENT2_ISET_DIO29_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO29_AW :: INT_EVENT2_ISET_DIO29_SET) } } # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO30_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO30_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO30_SET = 1 , } impl From < INT_EVENT2_ISET_DIO30_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO30` writer - DIO30 event"]
pub type INT_EVENT2_ISET_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO30_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO30_AW :: INT_EVENT2_ISET_DIO30_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO30_AW :: INT_EVENT2_ISET_DIO30_SET) } } # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_DIO31_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_DIO31_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_DIO31_SET = 1 , } impl From < INT_EVENT2_ISET_DIO31_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_DIO31` writer - DIO31 event"]
pub type INT_EVENT2_ISET_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_DIO31_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO31_AW :: INT_EVENT2_ISET_DIO31_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_DIO31_AW :: INT_EVENT2_ISET_DIO31_SET) } } impl W { # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio16 (& mut self) -> INT_EVENT2_ISET_DIO16_W < INT_EVENT2_ISET_SPEC , 16 > { INT_EVENT2_ISET_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio17 (& mut self) -> INT_EVENT2_ISET_DIO17_W < INT_EVENT2_ISET_SPEC , 17 > { INT_EVENT2_ISET_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio18 (& mut self) -> INT_EVENT2_ISET_DIO18_W < INT_EVENT2_ISET_SPEC , 18 > { INT_EVENT2_ISET_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio19 (& mut self) -> INT_EVENT2_ISET_DIO19_W < INT_EVENT2_ISET_SPEC , 19 > { INT_EVENT2_ISET_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio20 (& mut self) -> INT_EVENT2_ISET_DIO20_W < INT_EVENT2_ISET_SPEC , 20 > { INT_EVENT2_ISET_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio21 (& mut self) -> INT_EVENT2_ISET_DIO21_W < INT_EVENT2_ISET_SPEC , 21 > { INT_EVENT2_ISET_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio22 (& mut self) -> INT_EVENT2_ISET_DIO22_W < INT_EVENT2_ISET_SPEC , 22 > { INT_EVENT2_ISET_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio23 (& mut self) -> INT_EVENT2_ISET_DIO23_W < INT_EVENT2_ISET_SPEC , 23 > { INT_EVENT2_ISET_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio24 (& mut self) -> INT_EVENT2_ISET_DIO24_W < INT_EVENT2_ISET_SPEC , 24 > { INT_EVENT2_ISET_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio25 (& mut self) -> INT_EVENT2_ISET_DIO25_W < INT_EVENT2_ISET_SPEC , 25 > { INT_EVENT2_ISET_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio26 (& mut self) -> INT_EVENT2_ISET_DIO26_W < INT_EVENT2_ISET_SPEC , 26 > { INT_EVENT2_ISET_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio27 (& mut self) -> INT_EVENT2_ISET_DIO27_W < INT_EVENT2_ISET_SPEC , 27 > { INT_EVENT2_ISET_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio28 (& mut self) -> INT_EVENT2_ISET_DIO28_W < INT_EVENT2_ISET_SPEC , 28 > { INT_EVENT2_ISET_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio29 (& mut self) -> INT_EVENT2_ISET_DIO29_W < INT_EVENT2_ISET_SPEC , 29 > { INT_EVENT2_ISET_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio30 (& mut self) -> INT_EVENT2_ISET_DIO30_W < INT_EVENT2_ISET_SPEC , 30 > { INT_EVENT2_ISET_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_dio31 (& mut self) -> INT_EVENT2_ISET_DIO31_W < INT_EVENT2_ISET_SPEC , 31 > { INT_EVENT2_ISET_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"]
impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iclr`]
module"]
pub type INT_EVENT2_ICLR = crate :: Reg < int_event2_iclr :: INT_EVENT2_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event2_iclr { # [doc = "Register `INT_EVENT2_ICLR` writer"]
pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "DIO16 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO16_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO16_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO16_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO16_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO16` writer - DIO16 event"]
pub type INT_EVENT2_ICLR_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO16_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO16_AW :: INT_EVENT2_ICLR_DIO16_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO16_AW :: INT_EVENT2_ICLR_DIO16_CLR) } } # [doc = "DIO17 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO17_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO17_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO17_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO17_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO17` writer - DIO17 event"]
pub type INT_EVENT2_ICLR_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO17_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO17_AW :: INT_EVENT2_ICLR_DIO17_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO17_AW :: INT_EVENT2_ICLR_DIO17_CLR) } } # [doc = "DIO18 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO18_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO18_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO18_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO18_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO18` writer - DIO18 event"]
pub type INT_EVENT2_ICLR_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO18_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO18_AW :: INT_EVENT2_ICLR_DIO18_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO18_AW :: INT_EVENT2_ICLR_DIO18_CLR) } } # [doc = "DIO19 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO19_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO19_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO19_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO19_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO19` writer - DIO19 event"]
pub type INT_EVENT2_ICLR_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO19_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO19_AW :: INT_EVENT2_ICLR_DIO19_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO19_AW :: INT_EVENT2_ICLR_DIO19_CLR) } } # [doc = "DIO20 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO20_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO20_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO20_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO20_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO20` writer - DIO20 event"]
pub type INT_EVENT2_ICLR_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO20_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO20_AW :: INT_EVENT2_ICLR_DIO20_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO20_AW :: INT_EVENT2_ICLR_DIO20_CLR) } } # [doc = "DIO21 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO21_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO21_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO21_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO21_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO21` writer - DIO21 event"]
pub type INT_EVENT2_ICLR_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO21_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO21_AW :: INT_EVENT2_ICLR_DIO21_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO21_AW :: INT_EVENT2_ICLR_DIO21_CLR) } } # [doc = "DIO22 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO22_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO22_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO22_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO22_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO22` writer - DIO22 event"]
pub type INT_EVENT2_ICLR_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO22_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO22_AW :: INT_EVENT2_ICLR_DIO22_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO22_AW :: INT_EVENT2_ICLR_DIO22_CLR) } } # [doc = "DIO23 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO23_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO23_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO23_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO23_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO23` writer - DIO23 event"]
pub type INT_EVENT2_ICLR_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO23_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO23_AW :: INT_EVENT2_ICLR_DIO23_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO23_AW :: INT_EVENT2_ICLR_DIO23_CLR) } } # [doc = "DIO24 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO24_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO24_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO24_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO24_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO24` writer - DIO24 event"]
pub type INT_EVENT2_ICLR_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO24_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO24_AW :: INT_EVENT2_ICLR_DIO24_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO24_AW :: INT_EVENT2_ICLR_DIO24_CLR) } } # [doc = "DIO25 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO25_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO25_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO25_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO25_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO25` writer - DIO25 event"]
pub type INT_EVENT2_ICLR_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO25_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO25_AW :: INT_EVENT2_ICLR_DIO25_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO25_AW :: INT_EVENT2_ICLR_DIO25_CLR) } } # [doc = "DIO26 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO26_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO26_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO26_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO26_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO26` writer - DIO26 event"]
pub type INT_EVENT2_ICLR_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO26_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO26_AW :: INT_EVENT2_ICLR_DIO26_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO26_AW :: INT_EVENT2_ICLR_DIO26_CLR) } } # [doc = "DIO27 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO27_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO27_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO27_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO27_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO27` writer - DIO27 event"]
pub type INT_EVENT2_ICLR_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO27_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO27_AW :: INT_EVENT2_ICLR_DIO27_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO27_AW :: INT_EVENT2_ICLR_DIO27_CLR) } } # [doc = "DIO28 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO28_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO28_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO28_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO28_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO28` writer - DIO28 event"]
pub type INT_EVENT2_ICLR_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO28_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO28_AW :: INT_EVENT2_ICLR_DIO28_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO28_AW :: INT_EVENT2_ICLR_DIO28_CLR) } } # [doc = "DIO29 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO29_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO29_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO29_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO29_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO29` writer - DIO29 event"]
pub type INT_EVENT2_ICLR_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO29_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO29_AW :: INT_EVENT2_ICLR_DIO29_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO29_AW :: INT_EVENT2_ICLR_DIO29_CLR) } } # [doc = "DIO30 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO30_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO30_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO30_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO30_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO30` writer - DIO30 event"]
pub type INT_EVENT2_ICLR_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO30_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO30_AW :: INT_EVENT2_ICLR_DIO30_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO30_AW :: INT_EVENT2_ICLR_DIO30_CLR) } } # [doc = "DIO31 event\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_DIO31_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_DIO31_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_DIO31_CLR = 1 , } impl From < INT_EVENT2_ICLR_DIO31_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_DIO31` writer - DIO31 event"]
pub type INT_EVENT2_ICLR_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_DIO31_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO31_AW :: INT_EVENT2_ICLR_DIO31_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_DIO31_AW :: INT_EVENT2_ICLR_DIO31_CLR) } } impl W { # [doc = "Bit 16 - DIO16 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio16 (& mut self) -> INT_EVENT2_ICLR_DIO16_W < INT_EVENT2_ICLR_SPEC , 16 > { INT_EVENT2_ICLR_DIO16_W :: new (self) } # [doc = "Bit 17 - DIO17 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio17 (& mut self) -> INT_EVENT2_ICLR_DIO17_W < INT_EVENT2_ICLR_SPEC , 17 > { INT_EVENT2_ICLR_DIO17_W :: new (self) } # [doc = "Bit 18 - DIO18 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio18 (& mut self) -> INT_EVENT2_ICLR_DIO18_W < INT_EVENT2_ICLR_SPEC , 18 > { INT_EVENT2_ICLR_DIO18_W :: new (self) } # [doc = "Bit 19 - DIO19 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio19 (& mut self) -> INT_EVENT2_ICLR_DIO19_W < INT_EVENT2_ICLR_SPEC , 19 > { INT_EVENT2_ICLR_DIO19_W :: new (self) } # [doc = "Bit 20 - DIO20 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio20 (& mut self) -> INT_EVENT2_ICLR_DIO20_W < INT_EVENT2_ICLR_SPEC , 20 > { INT_EVENT2_ICLR_DIO20_W :: new (self) } # [doc = "Bit 21 - DIO21 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio21 (& mut self) -> INT_EVENT2_ICLR_DIO21_W < INT_EVENT2_ICLR_SPEC , 21 > { INT_EVENT2_ICLR_DIO21_W :: new (self) } # [doc = "Bit 22 - DIO22 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio22 (& mut self) -> INT_EVENT2_ICLR_DIO22_W < INT_EVENT2_ICLR_SPEC , 22 > { INT_EVENT2_ICLR_DIO22_W :: new (self) } # [doc = "Bit 23 - DIO23 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio23 (& mut self) -> INT_EVENT2_ICLR_DIO23_W < INT_EVENT2_ICLR_SPEC , 23 > { INT_EVENT2_ICLR_DIO23_W :: new (self) } # [doc = "Bit 24 - DIO24 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio24 (& mut self) -> INT_EVENT2_ICLR_DIO24_W < INT_EVENT2_ICLR_SPEC , 24 > { INT_EVENT2_ICLR_DIO24_W :: new (self) } # [doc = "Bit 25 - DIO25 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio25 (& mut self) -> INT_EVENT2_ICLR_DIO25_W < INT_EVENT2_ICLR_SPEC , 25 > { INT_EVENT2_ICLR_DIO25_W :: new (self) } # [doc = "Bit 26 - DIO26 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio26 (& mut self) -> INT_EVENT2_ICLR_DIO26_W < INT_EVENT2_ICLR_SPEC , 26 > { INT_EVENT2_ICLR_DIO26_W :: new (self) } # [doc = "Bit 27 - DIO27 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio27 (& mut self) -> INT_EVENT2_ICLR_DIO27_W < INT_EVENT2_ICLR_SPEC , 27 > { INT_EVENT2_ICLR_DIO27_W :: new (self) } # [doc = "Bit 28 - DIO28 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio28 (& mut self) -> INT_EVENT2_ICLR_DIO28_W < INT_EVENT2_ICLR_SPEC , 28 > { INT_EVENT2_ICLR_DIO28_W :: new (self) } # [doc = "Bit 29 - DIO29 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio29 (& mut self) -> INT_EVENT2_ICLR_DIO29_W < INT_EVENT2_ICLR_SPEC , 29 > { INT_EVENT2_ICLR_DIO29_W :: new (self) } # [doc = "Bit 30 - DIO30 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio30 (& mut self) -> INT_EVENT2_ICLR_DIO30_W < INT_EVENT2_ICLR_SPEC , 30 > { INT_EVENT2_ICLR_DIO30_W :: new (self) } # [doc = "Bit 31 - DIO31 event"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_dio31 (& mut self) -> INT_EVENT2_ICLR_DIO31_W < INT_EVENT2_ICLR_SPEC , 31 > { INT_EVENT2_ICLR_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT3_0 (w) register accessor: Data output 3 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout3_0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout3_0`]
module"]
pub type DOUT3_0 = crate :: Reg < dout3_0 :: DOUT3_0_SPEC > ; # [doc = "Data output 3 to 0"]
pub mod dout3_0 { # [doc = "Register `DOUT3_0` writer"]
pub type W = crate :: W < DOUT3_0_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT3_0_DIO0_AW { # [doc = "0: ZERO"]
DOUT3_0_DIO0_ZERO = 0 , # [doc = "1: ONE"]
DOUT3_0_DIO0_ONE = 1 , } impl From < DOUT3_0_DIO0_AW > for bool { # [inline (always)]
fn from (variant : DOUT3_0_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT3_0_DIO0` writer - This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register."]
pub type DOUT3_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT3_0_DIO0_AW > ; impl < 'a , REG , const O : u8 > DOUT3_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout3_0_dio0_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO0_AW :: DOUT3_0_DIO0_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout3_0_dio0_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO0_AW :: DOUT3_0_DIO0_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT3_0_DIO1_AW { # [doc = "0: ZERO"]
DOUT3_0_DIO1_ZERO = 0 , # [doc = "1: ONE"]
DOUT3_0_DIO1_ONE = 1 , } impl From < DOUT3_0_DIO1_AW > for bool { # [inline (always)]
fn from (variant : DOUT3_0_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT3_0_DIO1` writer - This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register."]
pub type DOUT3_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT3_0_DIO1_AW > ; impl < 'a , REG , const O : u8 > DOUT3_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout3_0_dio1_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO1_AW :: DOUT3_0_DIO1_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout3_0_dio1_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO1_AW :: DOUT3_0_DIO1_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT3_0_DIO2_AW { # [doc = "0: ZERO"]
DOUT3_0_DIO2_ZERO = 0 , # [doc = "1: ONE"]
DOUT3_0_DIO2_ONE = 1 , } impl From < DOUT3_0_DIO2_AW > for bool { # [inline (always)]
fn from (variant : DOUT3_0_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT3_0_DIO2` writer - This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register."]
pub type DOUT3_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT3_0_DIO2_AW > ; impl < 'a , REG , const O : u8 > DOUT3_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout3_0_dio2_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO2_AW :: DOUT3_0_DIO2_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout3_0_dio2_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO2_AW :: DOUT3_0_DIO2_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT3_0_DIO3_AW { # [doc = "0: ZERO"]
DOUT3_0_DIO3_ZERO = 0 , # [doc = "1: ONE"]
DOUT3_0_DIO3_ONE = 1 , } impl From < DOUT3_0_DIO3_AW > for bool { # [inline (always)]
fn from (variant : DOUT3_0_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT3_0_DIO3` writer - This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register."]
pub type DOUT3_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT3_0_DIO3_AW > ; impl < 'a , REG , const O : u8 > DOUT3_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout3_0_dio3_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO3_AW :: DOUT3_0_DIO3_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout3_0_dio3_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT3_0_DIO3_AW :: DOUT3_0_DIO3_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout3_0_dio0 (& mut self) -> DOUT3_0_DIO0_W < DOUT3_0_SPEC , 0 > { DOUT3_0_DIO0_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout3_0_dio1 (& mut self) -> DOUT3_0_DIO1_W < DOUT3_0_SPEC , 8 > { DOUT3_0_DIO1_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout3_0_dio2 (& mut self) -> DOUT3_0_DIO2_W < DOUT3_0_SPEC , 16 > { DOUT3_0_DIO2_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout3_0_dio3 (& mut self) -> DOUT3_0_DIO3_W < DOUT3_0_SPEC , 24 > { DOUT3_0_DIO3_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 3 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout3_0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT3_0_SPEC ; impl crate :: RegisterSpec for DOUT3_0_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout3_0::W`](W) writer structure"]
impl crate :: Writable for DOUT3_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT3_0 to value 0"]
impl crate :: Resettable for DOUT3_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT7_4 (w) register accessor: Data output 7 to 4\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout7_4::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout7_4`]
module"]
pub type DOUT7_4 = crate :: Reg < dout7_4 :: DOUT7_4_SPEC > ; # [doc = "Data output 7 to 4"]
pub mod dout7_4 { # [doc = "Register `DOUT7_4` writer"]
pub type W = crate :: W < DOUT7_4_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT7_4_DIO4_AW { # [doc = "0: ZERO"]
DOUT7_4_DIO4_ZERO = 0 , # [doc = "1: ONE"]
DOUT7_4_DIO4_ONE = 1 , } impl From < DOUT7_4_DIO4_AW > for bool { # [inline (always)]
fn from (variant : DOUT7_4_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT7_4_DIO4` writer - This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register."]
pub type DOUT7_4_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT7_4_DIO4_AW > ; impl < 'a , REG , const O : u8 > DOUT7_4_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout7_4_dio4_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO4_AW :: DOUT7_4_DIO4_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout7_4_dio4_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO4_AW :: DOUT7_4_DIO4_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT7_4_DIO5_AW { # [doc = "0: ZERO"]
DOUT7_4_DIO5_ZERO = 0 , # [doc = "1: ONE"]
DOUT7_4_DIO5_ONE = 1 , } impl From < DOUT7_4_DIO5_AW > for bool { # [inline (always)]
fn from (variant : DOUT7_4_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT7_4_DIO5` writer - This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register."]
pub type DOUT7_4_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT7_4_DIO5_AW > ; impl < 'a , REG , const O : u8 > DOUT7_4_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout7_4_dio5_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO5_AW :: DOUT7_4_DIO5_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout7_4_dio5_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO5_AW :: DOUT7_4_DIO5_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT7_4_DIO6_AW { # [doc = "0: ZERO"]
DOUT7_4_DIO6_ZERO = 0 , # [doc = "1: ONE"]
DOUT7_4_DIO6_ONE = 1 , } impl From < DOUT7_4_DIO6_AW > for bool { # [inline (always)]
fn from (variant : DOUT7_4_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT7_4_DIO6` writer - This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register."]
pub type DOUT7_4_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT7_4_DIO6_AW > ; impl < 'a , REG , const O : u8 > DOUT7_4_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout7_4_dio6_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO6_AW :: DOUT7_4_DIO6_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout7_4_dio6_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO6_AW :: DOUT7_4_DIO6_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT7_4_DIO7_AW { # [doc = "0: ZERO"]
DOUT7_4_DIO7_ZERO = 0 , # [doc = "1: ONE"]
DOUT7_4_DIO7_ONE = 1 , } impl From < DOUT7_4_DIO7_AW > for bool { # [inline (always)]
fn from (variant : DOUT7_4_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT7_4_DIO7` writer - This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register."]
pub type DOUT7_4_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT7_4_DIO7_AW > ; impl < 'a , REG , const O : u8 > DOUT7_4_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout7_4_dio7_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO7_AW :: DOUT7_4_DIO7_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout7_4_dio7_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT7_4_DIO7_AW :: DOUT7_4_DIO7_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout7_4_dio4 (& mut self) -> DOUT7_4_DIO4_W < DOUT7_4_SPEC , 0 > { DOUT7_4_DIO4_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout7_4_dio5 (& mut self) -> DOUT7_4_DIO5_W < DOUT7_4_SPEC , 8 > { DOUT7_4_DIO5_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout7_4_dio6 (& mut self) -> DOUT7_4_DIO6_W < DOUT7_4_SPEC , 16 > { DOUT7_4_DIO6_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout7_4_dio7 (& mut self) -> DOUT7_4_DIO7_W < DOUT7_4_SPEC , 24 > { DOUT7_4_DIO7_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 7 to 4\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout7_4::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT7_4_SPEC ; impl crate :: RegisterSpec for DOUT7_4_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout7_4::W`](W) writer structure"]
impl crate :: Writable for DOUT7_4_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT7_4 to value 0"]
impl crate :: Resettable for DOUT7_4_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT11_8 (w) register accessor: Data output 11 to 8\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout11_8::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout11_8`]
module"]
pub type DOUT11_8 = crate :: Reg < dout11_8 :: DOUT11_8_SPEC > ; # [doc = "Data output 11 to 8"]
pub mod dout11_8 { # [doc = "Register `DOUT11_8` writer"]
pub type W = crate :: W < DOUT11_8_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT11_8_DIO8_AW { # [doc = "0: ZERO"]
DOUT11_8_DIO8_ZERO = 0 , # [doc = "1: ONE"]
DOUT11_8_DIO8_ONE = 1 , } impl From < DOUT11_8_DIO8_AW > for bool { # [inline (always)]
fn from (variant : DOUT11_8_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT11_8_DIO8` writer - This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register."]
pub type DOUT11_8_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT11_8_DIO8_AW > ; impl < 'a , REG , const O : u8 > DOUT11_8_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout11_8_dio8_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO8_AW :: DOUT11_8_DIO8_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout11_8_dio8_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO8_AW :: DOUT11_8_DIO8_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT11_8_DIO9_AW { # [doc = "0: ZERO"]
DOUT11_8_DIO9_ZERO = 0 , # [doc = "1: ONE"]
DOUT11_8_DIO9_ONE = 1 , } impl From < DOUT11_8_DIO9_AW > for bool { # [inline (always)]
fn from (variant : DOUT11_8_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT11_8_DIO9` writer - This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register."]
pub type DOUT11_8_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT11_8_DIO9_AW > ; impl < 'a , REG , const O : u8 > DOUT11_8_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout11_8_dio9_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO9_AW :: DOUT11_8_DIO9_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout11_8_dio9_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO9_AW :: DOUT11_8_DIO9_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT11_8_DIO10_AW { # [doc = "0: ZERO"]
DOUT11_8_DIO10_ZERO = 0 , # [doc = "1: ONE"]
DOUT11_8_DIO10_ONE = 1 , } impl From < DOUT11_8_DIO10_AW > for bool { # [inline (always)]
fn from (variant : DOUT11_8_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT11_8_DIO10` writer - This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register."]
pub type DOUT11_8_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT11_8_DIO10_AW > ; impl < 'a , REG , const O : u8 > DOUT11_8_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout11_8_dio10_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO10_AW :: DOUT11_8_DIO10_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout11_8_dio10_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO10_AW :: DOUT11_8_DIO10_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT11_8_DIO11_AW { # [doc = "0: ZERO"]
DOUT11_8_DIO11_ZERO = 0 , # [doc = "1: ONE"]
DOUT11_8_DIO11_ONE = 1 , } impl From < DOUT11_8_DIO11_AW > for bool { # [inline (always)]
fn from (variant : DOUT11_8_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT11_8_DIO11` writer - This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register."]
pub type DOUT11_8_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT11_8_DIO11_AW > ; impl < 'a , REG , const O : u8 > DOUT11_8_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout11_8_dio11_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO11_AW :: DOUT11_8_DIO11_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout11_8_dio11_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT11_8_DIO11_AW :: DOUT11_8_DIO11_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout11_8_dio8 (& mut self) -> DOUT11_8_DIO8_W < DOUT11_8_SPEC , 0 > { DOUT11_8_DIO8_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout11_8_dio9 (& mut self) -> DOUT11_8_DIO9_W < DOUT11_8_SPEC , 8 > { DOUT11_8_DIO9_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout11_8_dio10 (& mut self) -> DOUT11_8_DIO10_W < DOUT11_8_SPEC , 16 > { DOUT11_8_DIO10_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout11_8_dio11 (& mut self) -> DOUT11_8_DIO11_W < DOUT11_8_SPEC , 24 > { DOUT11_8_DIO11_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 11 to 8\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout11_8::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT11_8_SPEC ; impl crate :: RegisterSpec for DOUT11_8_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout11_8::W`](W) writer structure"]
impl crate :: Writable for DOUT11_8_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT11_8 to value 0"]
impl crate :: Resettable for DOUT11_8_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT15_12 (w) register accessor: Data output 15 to 12\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout15_12::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout15_12`]
module"]
pub type DOUT15_12 = crate :: Reg < dout15_12 :: DOUT15_12_SPEC > ; # [doc = "Data output 15 to 12"]
pub mod dout15_12 { # [doc = "Register `DOUT15_12` writer"]
pub type W = crate :: W < DOUT15_12_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT15_12_DIO12_AW { # [doc = "0: ZERO"]
DOUT15_12_DIO12_ZERO = 0 , # [doc = "1: ONE"]
DOUT15_12_DIO12_ONE = 1 , } impl From < DOUT15_12_DIO12_AW > for bool { # [inline (always)]
fn from (variant : DOUT15_12_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT15_12_DIO12` writer - This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register."]
pub type DOUT15_12_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT15_12_DIO12_AW > ; impl < 'a , REG , const O : u8 > DOUT15_12_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout15_12_dio12_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO12_AW :: DOUT15_12_DIO12_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout15_12_dio12_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO12_AW :: DOUT15_12_DIO12_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT15_12_DIO13_AW { # [doc = "0: ZERO"]
DOUT15_12_DIO13_ZERO = 0 , # [doc = "1: ONE"]
DOUT15_12_DIO13_ONE = 1 , } impl From < DOUT15_12_DIO13_AW > for bool { # [inline (always)]
fn from (variant : DOUT15_12_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT15_12_DIO13` writer - This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register."]
pub type DOUT15_12_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT15_12_DIO13_AW > ; impl < 'a , REG , const O : u8 > DOUT15_12_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout15_12_dio13_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO13_AW :: DOUT15_12_DIO13_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout15_12_dio13_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO13_AW :: DOUT15_12_DIO13_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT15_12_DIO14_AW { # [doc = "0: ZERO"]
DOUT15_12_DIO14_ZERO = 0 , # [doc = "1: ONE"]
DOUT15_12_DIO14_ONE = 1 , } impl From < DOUT15_12_DIO14_AW > for bool { # [inline (always)]
fn from (variant : DOUT15_12_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT15_12_DIO14` writer - This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register."]
pub type DOUT15_12_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT15_12_DIO14_AW > ; impl < 'a , REG , const O : u8 > DOUT15_12_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout15_12_dio14_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO14_AW :: DOUT15_12_DIO14_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout15_12_dio14_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO14_AW :: DOUT15_12_DIO14_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT15_12_DIO15_AW { # [doc = "0: ZERO"]
DOUT15_12_DIO15_ZERO = 0 , # [doc = "1: ONE"]
DOUT15_12_DIO15_ONE = 1 , } impl From < DOUT15_12_DIO15_AW > for bool { # [inline (always)]
fn from (variant : DOUT15_12_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT15_12_DIO15` writer - This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register."]
pub type DOUT15_12_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT15_12_DIO15_AW > ; impl < 'a , REG , const O : u8 > DOUT15_12_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout15_12_dio15_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO15_AW :: DOUT15_12_DIO15_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout15_12_dio15_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT15_12_DIO15_AW :: DOUT15_12_DIO15_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout15_12_dio12 (& mut self) -> DOUT15_12_DIO12_W < DOUT15_12_SPEC , 0 > { DOUT15_12_DIO12_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout15_12_dio13 (& mut self) -> DOUT15_12_DIO13_W < DOUT15_12_SPEC , 8 > { DOUT15_12_DIO13_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout15_12_dio14 (& mut self) -> DOUT15_12_DIO14_W < DOUT15_12_SPEC , 16 > { DOUT15_12_DIO14_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout15_12_dio15 (& mut self) -> DOUT15_12_DIO15_W < DOUT15_12_SPEC , 24 > { DOUT15_12_DIO15_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 15 to 12\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout15_12::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT15_12_SPEC ; impl crate :: RegisterSpec for DOUT15_12_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout15_12::W`](W) writer structure"]
impl crate :: Writable for DOUT15_12_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT15_12 to value 0"]
impl crate :: Resettable for DOUT15_12_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT19_16 (w) register accessor: Data output 19 to 16\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout19_16::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout19_16`]
module"]
pub type DOUT19_16 = crate :: Reg < dout19_16 :: DOUT19_16_SPEC > ; # [doc = "Data output 19 to 16"]
pub mod dout19_16 { # [doc = "Register `DOUT19_16` writer"]
pub type W = crate :: W < DOUT19_16_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT19_16_DIO16_AW { # [doc = "0: ZERO"]
DOUT19_16_DIO16_ZERO = 0 , # [doc = "1: ONE"]
DOUT19_16_DIO16_ONE = 1 , } impl From < DOUT19_16_DIO16_AW > for bool { # [inline (always)]
fn from (variant : DOUT19_16_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT19_16_DIO16` writer - This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register."]
pub type DOUT19_16_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT19_16_DIO16_AW > ; impl < 'a , REG , const O : u8 > DOUT19_16_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout19_16_dio16_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO16_AW :: DOUT19_16_DIO16_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout19_16_dio16_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO16_AW :: DOUT19_16_DIO16_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT19_16_DIO17_AW { # [doc = "0: ZERO"]
DOUT19_16_DIO17_ZERO = 0 , # [doc = "1: ONE"]
DOUT19_16_DIO17_ONE = 1 , } impl From < DOUT19_16_DIO17_AW > for bool { # [inline (always)]
fn from (variant : DOUT19_16_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT19_16_DIO17` writer - This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register."]
pub type DOUT19_16_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT19_16_DIO17_AW > ; impl < 'a , REG , const O : u8 > DOUT19_16_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout19_16_dio17_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO17_AW :: DOUT19_16_DIO17_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout19_16_dio17_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO17_AW :: DOUT19_16_DIO17_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT19_16_DIO18_AW { # [doc = "0: ZERO"]
DOUT19_16_DIO18_ZERO = 0 , # [doc = "1: ONE"]
DOUT19_16_DIO18_ONE = 1 , } impl From < DOUT19_16_DIO18_AW > for bool { # [inline (always)]
fn from (variant : DOUT19_16_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT19_16_DIO18` writer - This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register."]
pub type DOUT19_16_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT19_16_DIO18_AW > ; impl < 'a , REG , const O : u8 > DOUT19_16_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout19_16_dio18_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO18_AW :: DOUT19_16_DIO18_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout19_16_dio18_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO18_AW :: DOUT19_16_DIO18_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT19_16_DIO19_AW { # [doc = "0: ZERO"]
DOUT19_16_DIO19_ZERO = 0 , # [doc = "1: ONE"]
DOUT19_16_DIO19_ONE = 1 , } impl From < DOUT19_16_DIO19_AW > for bool { # [inline (always)]
fn from (variant : DOUT19_16_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT19_16_DIO19` writer - This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register."]
pub type DOUT19_16_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT19_16_DIO19_AW > ; impl < 'a , REG , const O : u8 > DOUT19_16_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout19_16_dio19_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO19_AW :: DOUT19_16_DIO19_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout19_16_dio19_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT19_16_DIO19_AW :: DOUT19_16_DIO19_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout19_16_dio16 (& mut self) -> DOUT19_16_DIO16_W < DOUT19_16_SPEC , 0 > { DOUT19_16_DIO16_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout19_16_dio17 (& mut self) -> DOUT19_16_DIO17_W < DOUT19_16_SPEC , 8 > { DOUT19_16_DIO17_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout19_16_dio18 (& mut self) -> DOUT19_16_DIO18_W < DOUT19_16_SPEC , 16 > { DOUT19_16_DIO18_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout19_16_dio19 (& mut self) -> DOUT19_16_DIO19_W < DOUT19_16_SPEC , 24 > { DOUT19_16_DIO19_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 19 to 16\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout19_16::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT19_16_SPEC ; impl crate :: RegisterSpec for DOUT19_16_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout19_16::W`](W) writer structure"]
impl crate :: Writable for DOUT19_16_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT19_16 to value 0"]
impl crate :: Resettable for DOUT19_16_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT23_20 (w) register accessor: Data output 23 to 20\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout23_20::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout23_20`]
module"]
pub type DOUT23_20 = crate :: Reg < dout23_20 :: DOUT23_20_SPEC > ; # [doc = "Data output 23 to 20"]
pub mod dout23_20 { # [doc = "Register `DOUT23_20` writer"]
pub type W = crate :: W < DOUT23_20_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT23_20_DIO20_AW { # [doc = "0: ZERO"]
DOUT23_20_DIO20_ZERO = 0 , # [doc = "1: ONE"]
DOUT23_20_DIO20_ONE = 1 , } impl From < DOUT23_20_DIO20_AW > for bool { # [inline (always)]
fn from (variant : DOUT23_20_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT23_20_DIO20` writer - This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register."]
pub type DOUT23_20_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT23_20_DIO20_AW > ; impl < 'a , REG , const O : u8 > DOUT23_20_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout23_20_dio20_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO20_AW :: DOUT23_20_DIO20_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout23_20_dio20_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO20_AW :: DOUT23_20_DIO20_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT23_20_DIO21_AW { # [doc = "0: ZERO"]
DOUT23_20_DIO21_ZERO = 0 , # [doc = "1: ONE"]
DOUT23_20_DIO21_ONE = 1 , } impl From < DOUT23_20_DIO21_AW > for bool { # [inline (always)]
fn from (variant : DOUT23_20_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT23_20_DIO21` writer - This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register."]
pub type DOUT23_20_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT23_20_DIO21_AW > ; impl < 'a , REG , const O : u8 > DOUT23_20_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout23_20_dio21_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO21_AW :: DOUT23_20_DIO21_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout23_20_dio21_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO21_AW :: DOUT23_20_DIO21_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT23_20_DIO22_AW { # [doc = "0: ZERO"]
DOUT23_20_DIO22_ZERO = 0 , # [doc = "1: ONE"]
DOUT23_20_DIO22_ONE = 1 , } impl From < DOUT23_20_DIO22_AW > for bool { # [inline (always)]
fn from (variant : DOUT23_20_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT23_20_DIO22` writer - This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register."]
pub type DOUT23_20_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT23_20_DIO22_AW > ; impl < 'a , REG , const O : u8 > DOUT23_20_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout23_20_dio22_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO22_AW :: DOUT23_20_DIO22_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout23_20_dio22_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO22_AW :: DOUT23_20_DIO22_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT23_20_DIO23_AW { # [doc = "0: ZERO"]
DOUT23_20_DIO23_ZERO = 0 , # [doc = "1: ONE"]
DOUT23_20_DIO23_ONE = 1 , } impl From < DOUT23_20_DIO23_AW > for bool { # [inline (always)]
fn from (variant : DOUT23_20_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT23_20_DIO23` writer - This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register."]
pub type DOUT23_20_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT23_20_DIO23_AW > ; impl < 'a , REG , const O : u8 > DOUT23_20_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout23_20_dio23_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO23_AW :: DOUT23_20_DIO23_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout23_20_dio23_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT23_20_DIO23_AW :: DOUT23_20_DIO23_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout23_20_dio20 (& mut self) -> DOUT23_20_DIO20_W < DOUT23_20_SPEC , 0 > { DOUT23_20_DIO20_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout23_20_dio21 (& mut self) -> DOUT23_20_DIO21_W < DOUT23_20_SPEC , 8 > { DOUT23_20_DIO21_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout23_20_dio22 (& mut self) -> DOUT23_20_DIO22_W < DOUT23_20_SPEC , 16 > { DOUT23_20_DIO22_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout23_20_dio23 (& mut self) -> DOUT23_20_DIO23_W < DOUT23_20_SPEC , 24 > { DOUT23_20_DIO23_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 23 to 20\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout23_20::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT23_20_SPEC ; impl crate :: RegisterSpec for DOUT23_20_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout23_20::W`](W) writer structure"]
impl crate :: Writable for DOUT23_20_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT23_20 to value 0"]
impl crate :: Resettable for DOUT23_20_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT27_24 (w) register accessor: Data output 27 to 24\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout27_24::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout27_24`]
module"]
pub type DOUT27_24 = crate :: Reg < dout27_24 :: DOUT27_24_SPEC > ; # [doc = "Data output 27 to 24"]
pub mod dout27_24 { # [doc = "Register `DOUT27_24` writer"]
pub type W = crate :: W < DOUT27_24_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT27_24_DIO24_AW { # [doc = "0: ZERO"]
DOUT27_24_DIO24_ZERO = 0 , # [doc = "1: ONE"]
DOUT27_24_DIO24_ONE = 1 , } impl From < DOUT27_24_DIO24_AW > for bool { # [inline (always)]
fn from (variant : DOUT27_24_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT27_24_DIO24` writer - This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register."]
pub type DOUT27_24_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT27_24_DIO24_AW > ; impl < 'a , REG , const O : u8 > DOUT27_24_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout27_24_dio24_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO24_AW :: DOUT27_24_DIO24_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout27_24_dio24_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO24_AW :: DOUT27_24_DIO24_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT27_24_DIO25_AW { # [doc = "0: ZERO"]
DOUT27_24_DIO25_ZERO = 0 , # [doc = "1: ONE"]
DOUT27_24_DIO25_ONE = 1 , } impl From < DOUT27_24_DIO25_AW > for bool { # [inline (always)]
fn from (variant : DOUT27_24_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT27_24_DIO25` writer - This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register."]
pub type DOUT27_24_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT27_24_DIO25_AW > ; impl < 'a , REG , const O : u8 > DOUT27_24_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout27_24_dio25_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO25_AW :: DOUT27_24_DIO25_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout27_24_dio25_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO25_AW :: DOUT27_24_DIO25_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT27_24_DIO26_AW { # [doc = "0: ZERO"]
DOUT27_24_DIO26_ZERO = 0 , # [doc = "1: ONE"]
DOUT27_24_DIO26_ONE = 1 , } impl From < DOUT27_24_DIO26_AW > for bool { # [inline (always)]
fn from (variant : DOUT27_24_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT27_24_DIO26` writer - This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register."]
pub type DOUT27_24_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT27_24_DIO26_AW > ; impl < 'a , REG , const O : u8 > DOUT27_24_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout27_24_dio26_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO26_AW :: DOUT27_24_DIO26_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout27_24_dio26_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO26_AW :: DOUT27_24_DIO26_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT27_24_DIO27_AW { # [doc = "0: ZERO"]
DOUT27_24_DIO27_ZERO = 0 , # [doc = "1: ONE"]
DOUT27_24_DIO27_ONE = 1 , } impl From < DOUT27_24_DIO27_AW > for bool { # [inline (always)]
fn from (variant : DOUT27_24_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT27_24_DIO27` writer - This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register."]
pub type DOUT27_24_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT27_24_DIO27_AW > ; impl < 'a , REG , const O : u8 > DOUT27_24_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout27_24_dio27_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO27_AW :: DOUT27_24_DIO27_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout27_24_dio27_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT27_24_DIO27_AW :: DOUT27_24_DIO27_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout27_24_dio24 (& mut self) -> DOUT27_24_DIO24_W < DOUT27_24_SPEC , 0 > { DOUT27_24_DIO24_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout27_24_dio25 (& mut self) -> DOUT27_24_DIO25_W < DOUT27_24_SPEC , 8 > { DOUT27_24_DIO25_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout27_24_dio26 (& mut self) -> DOUT27_24_DIO26_W < DOUT27_24_SPEC , 16 > { DOUT27_24_DIO26_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout27_24_dio27 (& mut self) -> DOUT27_24_DIO27_W < DOUT27_24_SPEC , 24 > { DOUT27_24_DIO27_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 27 to 24\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout27_24::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT27_24_SPEC ; impl crate :: RegisterSpec for DOUT27_24_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout27_24::W`](W) writer structure"]
impl crate :: Writable for DOUT27_24_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT27_24 to value 0"]
impl crate :: Resettable for DOUT27_24_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT31_28 (w) register accessor: Data output 31 to 28\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout31_28::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout31_28`]
module"]
pub type DOUT31_28 = crate :: Reg < dout31_28 :: DOUT31_28_SPEC > ; # [doc = "Data output 31 to 28"]
pub mod dout31_28 { # [doc = "Register `DOUT31_28` writer"]
pub type W = crate :: W < DOUT31_28_SPEC > ; # [doc = "This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_28_DIO28_AW { # [doc = "0: ZERO"]
DOUT31_28_DIO28_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_28_DIO28_ONE = 1 , } impl From < DOUT31_28_DIO28_AW > for bool { # [inline (always)]
fn from (variant : DOUT31_28_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT31_28_DIO28` writer - This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register."]
pub type DOUT31_28_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_28_DIO28_AW > ; impl < 'a , REG , const O : u8 > DOUT31_28_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_28_dio28_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO28_AW :: DOUT31_28_DIO28_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_28_dio28_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO28_AW :: DOUT31_28_DIO28_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_28_DIO29_AW { # [doc = "0: ZERO"]
DOUT31_28_DIO29_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_28_DIO29_ONE = 1 , } impl From < DOUT31_28_DIO29_AW > for bool { # [inline (always)]
fn from (variant : DOUT31_28_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT31_28_DIO29` writer - This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register."]
pub type DOUT31_28_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_28_DIO29_AW > ; impl < 'a , REG , const O : u8 > DOUT31_28_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_28_dio29_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO29_AW :: DOUT31_28_DIO29_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_28_dio29_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO29_AW :: DOUT31_28_DIO29_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_28_DIO30_AW { # [doc = "0: ZERO"]
DOUT31_28_DIO30_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_28_DIO30_ONE = 1 , } impl From < DOUT31_28_DIO30_AW > for bool { # [inline (always)]
fn from (variant : DOUT31_28_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT31_28_DIO30` writer - This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register."]
pub type DOUT31_28_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_28_DIO30_AW > ; impl < 'a , REG , const O : u8 > DOUT31_28_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_28_dio30_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO30_AW :: DOUT31_28_DIO30_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_28_dio30_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO30_AW :: DOUT31_28_DIO30_ONE) } } # [doc = "This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_28_DIO31_AW { # [doc = "0: ZERO"]
DOUT31_28_DIO31_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_28_DIO31_ONE = 1 , } impl From < DOUT31_28_DIO31_AW > for bool { # [inline (always)]
fn from (variant : DOUT31_28_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUT31_28_DIO31` writer - This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register."]
pub type DOUT31_28_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_28_DIO31_AW > ; impl < 'a , REG , const O : u8 > DOUT31_28_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_28_dio31_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO31_AW :: DOUT31_28_DIO31_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_28_dio31_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_28_DIO31_AW :: DOUT31_28_DIO31_ONE) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_28_dio28 (& mut self) -> DOUT31_28_DIO28_W < DOUT31_28_SPEC , 0 > { DOUT31_28_DIO28_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_28_dio29 (& mut self) -> DOUT31_28_DIO29_W < DOUT31_28_SPEC , 8 > { DOUT31_28_DIO29_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_28_dio30 (& mut self) -> DOUT31_28_DIO30_W < DOUT31_28_SPEC , 16 > { DOUT31_28_DIO30_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_28_dio31 (& mut self) -> DOUT31_28_DIO31_W < DOUT31_28_SPEC , 24 > { DOUT31_28_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 31 to 28\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout31_28::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT31_28_SPEC ; impl crate :: RegisterSpec for DOUT31_28_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`dout31_28::W`](W) writer structure"]
impl crate :: Writable for DOUT31_28_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT31_28 to value 0"]
impl crate :: Resettable for DOUT31_28_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUT31_0 (rw) register accessor: Data output 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dout31_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout31_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dout31_0`]
module"]
pub type DOUT31_0 = crate :: Reg < dout31_0 :: DOUT31_0_SPEC > ; # [doc = "Data output 31 to 0"]
pub mod dout31_0 { # [doc = "Register `DOUT31_0` reader"]
pub type R = crate :: R < DOUT31_0_SPEC > ; # [doc = "Register `DOUT31_0` writer"]
pub type W = crate :: W < DOUT31_0_SPEC > ; # [doc = "Field `DOUT31_0_DIO0` reader - This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO0_R = crate :: BitReader < DOUT31_0_DIO0_A > ; # [doc = "This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO0_A { # [doc = "0: ZERO"]
DOUT31_0_DIO0_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO0_ONE = 1 , } impl From < DOUT31_0_DIO0_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO0_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO0_A { match self . bits { false => DOUT31_0_DIO0_A :: DOUT31_0_DIO0_ZERO , true => DOUT31_0_DIO0_A :: DOUT31_0_DIO0_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio0_zero (& self) -> bool { * self == DOUT31_0_DIO0_A :: DOUT31_0_DIO0_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio0_one (& self) -> bool { * self == DOUT31_0_DIO0_A :: DOUT31_0_DIO0_ONE } } # [doc = "Field `DOUT31_0_DIO0` writer - This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO0_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio0_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO0_A :: DOUT31_0_DIO0_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio0_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO0_A :: DOUT31_0_DIO0_ONE) } } # [doc = "Field `DOUT31_0_DIO1` reader - This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO1_R = crate :: BitReader < DOUT31_0_DIO1_A > ; # [doc = "This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO1_A { # [doc = "0: ZERO"]
DOUT31_0_DIO1_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO1_ONE = 1 , } impl From < DOUT31_0_DIO1_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO1_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO1_A { match self . bits { false => DOUT31_0_DIO1_A :: DOUT31_0_DIO1_ZERO , true => DOUT31_0_DIO1_A :: DOUT31_0_DIO1_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio1_zero (& self) -> bool { * self == DOUT31_0_DIO1_A :: DOUT31_0_DIO1_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio1_one (& self) -> bool { * self == DOUT31_0_DIO1_A :: DOUT31_0_DIO1_ONE } } # [doc = "Field `DOUT31_0_DIO1` writer - This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO1_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio1_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO1_A :: DOUT31_0_DIO1_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio1_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO1_A :: DOUT31_0_DIO1_ONE) } } # [doc = "Field `DOUT31_0_DIO2` reader - This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO2_R = crate :: BitReader < DOUT31_0_DIO2_A > ; # [doc = "This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO2_A { # [doc = "0: ZERO"]
DOUT31_0_DIO2_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO2_ONE = 1 , } impl From < DOUT31_0_DIO2_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO2_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO2_A { match self . bits { false => DOUT31_0_DIO2_A :: DOUT31_0_DIO2_ZERO , true => DOUT31_0_DIO2_A :: DOUT31_0_DIO2_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio2_zero (& self) -> bool { * self == DOUT31_0_DIO2_A :: DOUT31_0_DIO2_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio2_one (& self) -> bool { * self == DOUT31_0_DIO2_A :: DOUT31_0_DIO2_ONE } } # [doc = "Field `DOUT31_0_DIO2` writer - This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO2_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio2_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO2_A :: DOUT31_0_DIO2_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio2_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO2_A :: DOUT31_0_DIO2_ONE) } } # [doc = "Field `DOUT31_0_DIO3` reader - This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO3_R = crate :: BitReader < DOUT31_0_DIO3_A > ; # [doc = "This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO3_A { # [doc = "0: ZERO"]
DOUT31_0_DIO3_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO3_ONE = 1 , } impl From < DOUT31_0_DIO3_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO3_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO3_A { match self . bits { false => DOUT31_0_DIO3_A :: DOUT31_0_DIO3_ZERO , true => DOUT31_0_DIO3_A :: DOUT31_0_DIO3_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio3_zero (& self) -> bool { * self == DOUT31_0_DIO3_A :: DOUT31_0_DIO3_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio3_one (& self) -> bool { * self == DOUT31_0_DIO3_A :: DOUT31_0_DIO3_ONE } } # [doc = "Field `DOUT31_0_DIO3` writer - This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO3_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio3_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO3_A :: DOUT31_0_DIO3_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio3_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO3_A :: DOUT31_0_DIO3_ONE) } } # [doc = "Field `DOUT31_0_DIO4` reader - This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO4_R = crate :: BitReader < DOUT31_0_DIO4_A > ; # [doc = "This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO4_A { # [doc = "0: ZERO"]
DOUT31_0_DIO4_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO4_ONE = 1 , } impl From < DOUT31_0_DIO4_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO4_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO4_A { match self . bits { false => DOUT31_0_DIO4_A :: DOUT31_0_DIO4_ZERO , true => DOUT31_0_DIO4_A :: DOUT31_0_DIO4_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio4_zero (& self) -> bool { * self == DOUT31_0_DIO4_A :: DOUT31_0_DIO4_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio4_one (& self) -> bool { * self == DOUT31_0_DIO4_A :: DOUT31_0_DIO4_ONE } } # [doc = "Field `DOUT31_0_DIO4` writer - This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO4_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio4_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO4_A :: DOUT31_0_DIO4_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio4_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO4_A :: DOUT31_0_DIO4_ONE) } } # [doc = "Field `DOUT31_0_DIO5` reader - This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO5_R = crate :: BitReader < DOUT31_0_DIO5_A > ; # [doc = "This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO5_A { # [doc = "0: ZERO"]
DOUT31_0_DIO5_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO5_ONE = 1 , } impl From < DOUT31_0_DIO5_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO5_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO5_A { match self . bits { false => DOUT31_0_DIO5_A :: DOUT31_0_DIO5_ZERO , true => DOUT31_0_DIO5_A :: DOUT31_0_DIO5_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio5_zero (& self) -> bool { * self == DOUT31_0_DIO5_A :: DOUT31_0_DIO5_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio5_one (& self) -> bool { * self == DOUT31_0_DIO5_A :: DOUT31_0_DIO5_ONE } } # [doc = "Field `DOUT31_0_DIO5` writer - This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO5_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio5_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO5_A :: DOUT31_0_DIO5_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio5_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO5_A :: DOUT31_0_DIO5_ONE) } } # [doc = "Field `DOUT31_0_DIO6` reader - This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO6_R = crate :: BitReader < DOUT31_0_DIO6_A > ; # [doc = "This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO6_A { # [doc = "0: ZERO"]
DOUT31_0_DIO6_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO6_ONE = 1 , } impl From < DOUT31_0_DIO6_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO6_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO6_A { match self . bits { false => DOUT31_0_DIO6_A :: DOUT31_0_DIO6_ZERO , true => DOUT31_0_DIO6_A :: DOUT31_0_DIO6_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio6_zero (& self) -> bool { * self == DOUT31_0_DIO6_A :: DOUT31_0_DIO6_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio6_one (& self) -> bool { * self == DOUT31_0_DIO6_A :: DOUT31_0_DIO6_ONE } } # [doc = "Field `DOUT31_0_DIO6` writer - This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO6_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio6_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO6_A :: DOUT31_0_DIO6_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio6_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO6_A :: DOUT31_0_DIO6_ONE) } } # [doc = "Field `DOUT31_0_DIO7` reader - This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO7_R = crate :: BitReader < DOUT31_0_DIO7_A > ; # [doc = "This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO7_A { # [doc = "0: ZERO"]
DOUT31_0_DIO7_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO7_ONE = 1 , } impl From < DOUT31_0_DIO7_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO7_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO7_A { match self . bits { false => DOUT31_0_DIO7_A :: DOUT31_0_DIO7_ZERO , true => DOUT31_0_DIO7_A :: DOUT31_0_DIO7_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio7_zero (& self) -> bool { * self == DOUT31_0_DIO7_A :: DOUT31_0_DIO7_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio7_one (& self) -> bool { * self == DOUT31_0_DIO7_A :: DOUT31_0_DIO7_ONE } } # [doc = "Field `DOUT31_0_DIO7` writer - This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO7_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio7_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO7_A :: DOUT31_0_DIO7_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio7_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO7_A :: DOUT31_0_DIO7_ONE) } } # [doc = "Field `DOUT31_0_DIO8` reader - This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO8_R = crate :: BitReader < DOUT31_0_DIO8_A > ; # [doc = "This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO8_A { # [doc = "0: ZERO"]
DOUT31_0_DIO8_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO8_ONE = 1 , } impl From < DOUT31_0_DIO8_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO8_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO8_A { match self . bits { false => DOUT31_0_DIO8_A :: DOUT31_0_DIO8_ZERO , true => DOUT31_0_DIO8_A :: DOUT31_0_DIO8_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio8_zero (& self) -> bool { * self == DOUT31_0_DIO8_A :: DOUT31_0_DIO8_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio8_one (& self) -> bool { * self == DOUT31_0_DIO8_A :: DOUT31_0_DIO8_ONE } } # [doc = "Field `DOUT31_0_DIO8` writer - This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO8_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio8_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO8_A :: DOUT31_0_DIO8_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio8_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO8_A :: DOUT31_0_DIO8_ONE) } } # [doc = "Field `DOUT31_0_DIO9` reader - This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO9_R = crate :: BitReader < DOUT31_0_DIO9_A > ; # [doc = "This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO9_A { # [doc = "0: ZERO"]
DOUT31_0_DIO9_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO9_ONE = 1 , } impl From < DOUT31_0_DIO9_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO9_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO9_A { match self . bits { false => DOUT31_0_DIO9_A :: DOUT31_0_DIO9_ZERO , true => DOUT31_0_DIO9_A :: DOUT31_0_DIO9_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio9_zero (& self) -> bool { * self == DOUT31_0_DIO9_A :: DOUT31_0_DIO9_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio9_one (& self) -> bool { * self == DOUT31_0_DIO9_A :: DOUT31_0_DIO9_ONE } } # [doc = "Field `DOUT31_0_DIO9` writer - This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO9_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio9_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO9_A :: DOUT31_0_DIO9_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio9_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO9_A :: DOUT31_0_DIO9_ONE) } } # [doc = "Field `DOUT31_0_DIO10` reader - This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO10_R = crate :: BitReader < DOUT31_0_DIO10_A > ; # [doc = "This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO10_A { # [doc = "0: ZERO"]
DOUT31_0_DIO10_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO10_ONE = 1 , } impl From < DOUT31_0_DIO10_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO10_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO10_A { match self . bits { false => DOUT31_0_DIO10_A :: DOUT31_0_DIO10_ZERO , true => DOUT31_0_DIO10_A :: DOUT31_0_DIO10_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio10_zero (& self) -> bool { * self == DOUT31_0_DIO10_A :: DOUT31_0_DIO10_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio10_one (& self) -> bool { * self == DOUT31_0_DIO10_A :: DOUT31_0_DIO10_ONE } } # [doc = "Field `DOUT31_0_DIO10` writer - This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO10_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio10_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO10_A :: DOUT31_0_DIO10_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio10_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO10_A :: DOUT31_0_DIO10_ONE) } } # [doc = "Field `DOUT31_0_DIO11` reader - This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO11_R = crate :: BitReader < DOUT31_0_DIO11_A > ; # [doc = "This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO11_A { # [doc = "0: ZERO"]
DOUT31_0_DIO11_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO11_ONE = 1 , } impl From < DOUT31_0_DIO11_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO11_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO11_A { match self . bits { false => DOUT31_0_DIO11_A :: DOUT31_0_DIO11_ZERO , true => DOUT31_0_DIO11_A :: DOUT31_0_DIO11_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio11_zero (& self) -> bool { * self == DOUT31_0_DIO11_A :: DOUT31_0_DIO11_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio11_one (& self) -> bool { * self == DOUT31_0_DIO11_A :: DOUT31_0_DIO11_ONE } } # [doc = "Field `DOUT31_0_DIO11` writer - This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO11_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio11_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO11_A :: DOUT31_0_DIO11_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio11_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO11_A :: DOUT31_0_DIO11_ONE) } } # [doc = "Field `DOUT31_0_DIO12` reader - This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO12_R = crate :: BitReader < DOUT31_0_DIO12_A > ; # [doc = "This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO12_A { # [doc = "0: ZERO"]
DOUT31_0_DIO12_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO12_ONE = 1 , } impl From < DOUT31_0_DIO12_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO12_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO12_A { match self . bits { false => DOUT31_0_DIO12_A :: DOUT31_0_DIO12_ZERO , true => DOUT31_0_DIO12_A :: DOUT31_0_DIO12_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio12_zero (& self) -> bool { * self == DOUT31_0_DIO12_A :: DOUT31_0_DIO12_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio12_one (& self) -> bool { * self == DOUT31_0_DIO12_A :: DOUT31_0_DIO12_ONE } } # [doc = "Field `DOUT31_0_DIO12` writer - This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO12_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio12_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO12_A :: DOUT31_0_DIO12_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio12_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO12_A :: DOUT31_0_DIO12_ONE) } } # [doc = "Field `DOUT31_0_DIO13` reader - This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO13_R = crate :: BitReader < DOUT31_0_DIO13_A > ; # [doc = "This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO13_A { # [doc = "0: ZERO"]
DOUT31_0_DIO13_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO13_ONE = 1 , } impl From < DOUT31_0_DIO13_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO13_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO13_A { match self . bits { false => DOUT31_0_DIO13_A :: DOUT31_0_DIO13_ZERO , true => DOUT31_0_DIO13_A :: DOUT31_0_DIO13_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio13_zero (& self) -> bool { * self == DOUT31_0_DIO13_A :: DOUT31_0_DIO13_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio13_one (& self) -> bool { * self == DOUT31_0_DIO13_A :: DOUT31_0_DIO13_ONE } } # [doc = "Field `DOUT31_0_DIO13` writer - This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO13_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio13_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO13_A :: DOUT31_0_DIO13_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio13_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO13_A :: DOUT31_0_DIO13_ONE) } } # [doc = "Field `DOUT31_0_DIO14` reader - This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO14_R = crate :: BitReader < DOUT31_0_DIO14_A > ; # [doc = "This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO14_A { # [doc = "0: ZERO"]
DOUT31_0_DIO14_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO14_ONE = 1 , } impl From < DOUT31_0_DIO14_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO14_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO14_A { match self . bits { false => DOUT31_0_DIO14_A :: DOUT31_0_DIO14_ZERO , true => DOUT31_0_DIO14_A :: DOUT31_0_DIO14_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio14_zero (& self) -> bool { * self == DOUT31_0_DIO14_A :: DOUT31_0_DIO14_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio14_one (& self) -> bool { * self == DOUT31_0_DIO14_A :: DOUT31_0_DIO14_ONE } } # [doc = "Field `DOUT31_0_DIO14` writer - This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO14_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio14_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO14_A :: DOUT31_0_DIO14_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio14_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO14_A :: DOUT31_0_DIO14_ONE) } } # [doc = "Field `DOUT31_0_DIO15` reader - This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO15_R = crate :: BitReader < DOUT31_0_DIO15_A > ; # [doc = "This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO15_A { # [doc = "0: ZERO"]
DOUT31_0_DIO15_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO15_ONE = 1 , } impl From < DOUT31_0_DIO15_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO15_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO15_A { match self . bits { false => DOUT31_0_DIO15_A :: DOUT31_0_DIO15_ZERO , true => DOUT31_0_DIO15_A :: DOUT31_0_DIO15_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio15_zero (& self) -> bool { * self == DOUT31_0_DIO15_A :: DOUT31_0_DIO15_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio15_one (& self) -> bool { * self == DOUT31_0_DIO15_A :: DOUT31_0_DIO15_ONE } } # [doc = "Field `DOUT31_0_DIO15` writer - This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO15_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio15_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO15_A :: DOUT31_0_DIO15_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio15_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO15_A :: DOUT31_0_DIO15_ONE) } } # [doc = "Field `DOUT31_0_DIO16` reader - This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO16_R = crate :: BitReader < DOUT31_0_DIO16_A > ; # [doc = "This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO16_A { # [doc = "0: ZERO"]
DOUT31_0_DIO16_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO16_ONE = 1 , } impl From < DOUT31_0_DIO16_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO16_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO16_A { match self . bits { false => DOUT31_0_DIO16_A :: DOUT31_0_DIO16_ZERO , true => DOUT31_0_DIO16_A :: DOUT31_0_DIO16_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio16_zero (& self) -> bool { * self == DOUT31_0_DIO16_A :: DOUT31_0_DIO16_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio16_one (& self) -> bool { * self == DOUT31_0_DIO16_A :: DOUT31_0_DIO16_ONE } } # [doc = "Field `DOUT31_0_DIO16` writer - This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO16_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio16_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO16_A :: DOUT31_0_DIO16_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio16_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO16_A :: DOUT31_0_DIO16_ONE) } } # [doc = "Field `DOUT31_0_DIO17` reader - This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO17_R = crate :: BitReader < DOUT31_0_DIO17_A > ; # [doc = "This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO17_A { # [doc = "0: ZERO"]
DOUT31_0_DIO17_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO17_ONE = 1 , } impl From < DOUT31_0_DIO17_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO17_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO17_A { match self . bits { false => DOUT31_0_DIO17_A :: DOUT31_0_DIO17_ZERO , true => DOUT31_0_DIO17_A :: DOUT31_0_DIO17_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio17_zero (& self) -> bool { * self == DOUT31_0_DIO17_A :: DOUT31_0_DIO17_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio17_one (& self) -> bool { * self == DOUT31_0_DIO17_A :: DOUT31_0_DIO17_ONE } } # [doc = "Field `DOUT31_0_DIO17` writer - This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO17_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio17_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO17_A :: DOUT31_0_DIO17_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio17_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO17_A :: DOUT31_0_DIO17_ONE) } } # [doc = "Field `DOUT31_0_DIO18` reader - This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO18_R = crate :: BitReader < DOUT31_0_DIO18_A > ; # [doc = "This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO18_A { # [doc = "0: ZERO"]
DOUT31_0_DIO18_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO18_ONE = 1 , } impl From < DOUT31_0_DIO18_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO18_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO18_A { match self . bits { false => DOUT31_0_DIO18_A :: DOUT31_0_DIO18_ZERO , true => DOUT31_0_DIO18_A :: DOUT31_0_DIO18_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio18_zero (& self) -> bool { * self == DOUT31_0_DIO18_A :: DOUT31_0_DIO18_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio18_one (& self) -> bool { * self == DOUT31_0_DIO18_A :: DOUT31_0_DIO18_ONE } } # [doc = "Field `DOUT31_0_DIO18` writer - This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO18_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio18_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO18_A :: DOUT31_0_DIO18_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio18_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO18_A :: DOUT31_0_DIO18_ONE) } } # [doc = "Field `DOUT31_0_DIO19` reader - This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO19_R = crate :: BitReader < DOUT31_0_DIO19_A > ; # [doc = "This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO19_A { # [doc = "0: ZERO"]
DOUT31_0_DIO19_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO19_ONE = 1 , } impl From < DOUT31_0_DIO19_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO19_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO19_A { match self . bits { false => DOUT31_0_DIO19_A :: DOUT31_0_DIO19_ZERO , true => DOUT31_0_DIO19_A :: DOUT31_0_DIO19_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio19_zero (& self) -> bool { * self == DOUT31_0_DIO19_A :: DOUT31_0_DIO19_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio19_one (& self) -> bool { * self == DOUT31_0_DIO19_A :: DOUT31_0_DIO19_ONE } } # [doc = "Field `DOUT31_0_DIO19` writer - This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO19_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio19_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO19_A :: DOUT31_0_DIO19_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio19_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO19_A :: DOUT31_0_DIO19_ONE) } } # [doc = "Field `DOUT31_0_DIO20` reader - This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO20_R = crate :: BitReader < DOUT31_0_DIO20_A > ; # [doc = "This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO20_A { # [doc = "0: ZERO"]
DOUT31_0_DIO20_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO20_ONE = 1 , } impl From < DOUT31_0_DIO20_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO20_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO20_A { match self . bits { false => DOUT31_0_DIO20_A :: DOUT31_0_DIO20_ZERO , true => DOUT31_0_DIO20_A :: DOUT31_0_DIO20_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio20_zero (& self) -> bool { * self == DOUT31_0_DIO20_A :: DOUT31_0_DIO20_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio20_one (& self) -> bool { * self == DOUT31_0_DIO20_A :: DOUT31_0_DIO20_ONE } } # [doc = "Field `DOUT31_0_DIO20` writer - This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO20_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio20_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO20_A :: DOUT31_0_DIO20_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio20_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO20_A :: DOUT31_0_DIO20_ONE) } } # [doc = "Field `DOUT31_0_DIO21` reader - This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO21_R = crate :: BitReader < DOUT31_0_DIO21_A > ; # [doc = "This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO21_A { # [doc = "0: ZERO"]
DOUT31_0_DIO21_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO21_ONE = 1 , } impl From < DOUT31_0_DIO21_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO21_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO21_A { match self . bits { false => DOUT31_0_DIO21_A :: DOUT31_0_DIO21_ZERO , true => DOUT31_0_DIO21_A :: DOUT31_0_DIO21_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio21_zero (& self) -> bool { * self == DOUT31_0_DIO21_A :: DOUT31_0_DIO21_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio21_one (& self) -> bool { * self == DOUT31_0_DIO21_A :: DOUT31_0_DIO21_ONE } } # [doc = "Field `DOUT31_0_DIO21` writer - This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO21_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio21_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO21_A :: DOUT31_0_DIO21_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio21_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO21_A :: DOUT31_0_DIO21_ONE) } } # [doc = "Field `DOUT31_0_DIO22` reader - This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO22_R = crate :: BitReader < DOUT31_0_DIO22_A > ; # [doc = "This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO22_A { # [doc = "0: ZERO"]
DOUT31_0_DIO22_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO22_ONE = 1 , } impl From < DOUT31_0_DIO22_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO22_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO22_A { match self . bits { false => DOUT31_0_DIO22_A :: DOUT31_0_DIO22_ZERO , true => DOUT31_0_DIO22_A :: DOUT31_0_DIO22_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio22_zero (& self) -> bool { * self == DOUT31_0_DIO22_A :: DOUT31_0_DIO22_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio22_one (& self) -> bool { * self == DOUT31_0_DIO22_A :: DOUT31_0_DIO22_ONE } } # [doc = "Field `DOUT31_0_DIO22` writer - This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO22_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio22_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO22_A :: DOUT31_0_DIO22_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio22_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO22_A :: DOUT31_0_DIO22_ONE) } } # [doc = "Field `DOUT31_0_DIO23` reader - This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO23_R = crate :: BitReader < DOUT31_0_DIO23_A > ; # [doc = "This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO23_A { # [doc = "0: ZERO"]
DOUT31_0_DIO23_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO23_ONE = 1 , } impl From < DOUT31_0_DIO23_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO23_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO23_A { match self . bits { false => DOUT31_0_DIO23_A :: DOUT31_0_DIO23_ZERO , true => DOUT31_0_DIO23_A :: DOUT31_0_DIO23_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio23_zero (& self) -> bool { * self == DOUT31_0_DIO23_A :: DOUT31_0_DIO23_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio23_one (& self) -> bool { * self == DOUT31_0_DIO23_A :: DOUT31_0_DIO23_ONE } } # [doc = "Field `DOUT31_0_DIO23` writer - This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO23_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio23_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO23_A :: DOUT31_0_DIO23_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio23_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO23_A :: DOUT31_0_DIO23_ONE) } } # [doc = "Field `DOUT31_0_DIO24` reader - This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO24_R = crate :: BitReader < DOUT31_0_DIO24_A > ; # [doc = "This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO24_A { # [doc = "0: ZERO"]
DOUT31_0_DIO24_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO24_ONE = 1 , } impl From < DOUT31_0_DIO24_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO24_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO24_A { match self . bits { false => DOUT31_0_DIO24_A :: DOUT31_0_DIO24_ZERO , true => DOUT31_0_DIO24_A :: DOUT31_0_DIO24_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio24_zero (& self) -> bool { * self == DOUT31_0_DIO24_A :: DOUT31_0_DIO24_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio24_one (& self) -> bool { * self == DOUT31_0_DIO24_A :: DOUT31_0_DIO24_ONE } } # [doc = "Field `DOUT31_0_DIO24` writer - This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO24_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio24_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO24_A :: DOUT31_0_DIO24_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio24_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO24_A :: DOUT31_0_DIO24_ONE) } } # [doc = "Field `DOUT31_0_DIO25` reader - This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO25_R = crate :: BitReader < DOUT31_0_DIO25_A > ; # [doc = "This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO25_A { # [doc = "0: ZERO"]
DOUT31_0_DIO25_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO25_ONE = 1 , } impl From < DOUT31_0_DIO25_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO25_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO25_A { match self . bits { false => DOUT31_0_DIO25_A :: DOUT31_0_DIO25_ZERO , true => DOUT31_0_DIO25_A :: DOUT31_0_DIO25_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio25_zero (& self) -> bool { * self == DOUT31_0_DIO25_A :: DOUT31_0_DIO25_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio25_one (& self) -> bool { * self == DOUT31_0_DIO25_A :: DOUT31_0_DIO25_ONE } } # [doc = "Field `DOUT31_0_DIO25` writer - This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO25_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio25_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO25_A :: DOUT31_0_DIO25_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio25_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO25_A :: DOUT31_0_DIO25_ONE) } } # [doc = "Field `DOUT31_0_DIO26` reader - This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO26_R = crate :: BitReader < DOUT31_0_DIO26_A > ; # [doc = "This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO26_A { # [doc = "0: ZERO"]
DOUT31_0_DIO26_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO26_ONE = 1 , } impl From < DOUT31_0_DIO26_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO26_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO26_A { match self . bits { false => DOUT31_0_DIO26_A :: DOUT31_0_DIO26_ZERO , true => DOUT31_0_DIO26_A :: DOUT31_0_DIO26_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio26_zero (& self) -> bool { * self == DOUT31_0_DIO26_A :: DOUT31_0_DIO26_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio26_one (& self) -> bool { * self == DOUT31_0_DIO26_A :: DOUT31_0_DIO26_ONE } } # [doc = "Field `DOUT31_0_DIO26` writer - This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO26_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio26_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO26_A :: DOUT31_0_DIO26_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio26_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO26_A :: DOUT31_0_DIO26_ONE) } } # [doc = "Field `DOUT31_0_DIO27` reader - This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO27_R = crate :: BitReader < DOUT31_0_DIO27_A > ; # [doc = "This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO27_A { # [doc = "0: ZERO"]
DOUT31_0_DIO27_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO27_ONE = 1 , } impl From < DOUT31_0_DIO27_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO27_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO27_A { match self . bits { false => DOUT31_0_DIO27_A :: DOUT31_0_DIO27_ZERO , true => DOUT31_0_DIO27_A :: DOUT31_0_DIO27_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio27_zero (& self) -> bool { * self == DOUT31_0_DIO27_A :: DOUT31_0_DIO27_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio27_one (& self) -> bool { * self == DOUT31_0_DIO27_A :: DOUT31_0_DIO27_ONE } } # [doc = "Field `DOUT31_0_DIO27` writer - This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO27_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio27_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO27_A :: DOUT31_0_DIO27_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio27_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO27_A :: DOUT31_0_DIO27_ONE) } } # [doc = "Field `DOUT31_0_DIO28` reader - This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO28_R = crate :: BitReader < DOUT31_0_DIO28_A > ; # [doc = "This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO28_A { # [doc = "0: ZERO"]
DOUT31_0_DIO28_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO28_ONE = 1 , } impl From < DOUT31_0_DIO28_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO28_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO28_A { match self . bits { false => DOUT31_0_DIO28_A :: DOUT31_0_DIO28_ZERO , true => DOUT31_0_DIO28_A :: DOUT31_0_DIO28_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio28_zero (& self) -> bool { * self == DOUT31_0_DIO28_A :: DOUT31_0_DIO28_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio28_one (& self) -> bool { * self == DOUT31_0_DIO28_A :: DOUT31_0_DIO28_ONE } } # [doc = "Field `DOUT31_0_DIO28` writer - This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO28_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio28_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO28_A :: DOUT31_0_DIO28_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio28_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO28_A :: DOUT31_0_DIO28_ONE) } } # [doc = "Field `DOUT31_0_DIO29` reader - This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO29_R = crate :: BitReader < DOUT31_0_DIO29_A > ; # [doc = "This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO29_A { # [doc = "0: ZERO"]
DOUT31_0_DIO29_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO29_ONE = 1 , } impl From < DOUT31_0_DIO29_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO29_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO29_A { match self . bits { false => DOUT31_0_DIO29_A :: DOUT31_0_DIO29_ZERO , true => DOUT31_0_DIO29_A :: DOUT31_0_DIO29_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio29_zero (& self) -> bool { * self == DOUT31_0_DIO29_A :: DOUT31_0_DIO29_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio29_one (& self) -> bool { * self == DOUT31_0_DIO29_A :: DOUT31_0_DIO29_ONE } } # [doc = "Field `DOUT31_0_DIO29` writer - This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO29_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio29_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO29_A :: DOUT31_0_DIO29_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio29_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO29_A :: DOUT31_0_DIO29_ONE) } } # [doc = "Field `DOUT31_0_DIO30` reader - This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO30_R = crate :: BitReader < DOUT31_0_DIO30_A > ; # [doc = "This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO30_A { # [doc = "0: ZERO"]
DOUT31_0_DIO30_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO30_ONE = 1 , } impl From < DOUT31_0_DIO30_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO30_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO30_A { match self . bits { false => DOUT31_0_DIO30_A :: DOUT31_0_DIO30_ZERO , true => DOUT31_0_DIO30_A :: DOUT31_0_DIO30_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio30_zero (& self) -> bool { * self == DOUT31_0_DIO30_A :: DOUT31_0_DIO30_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio30_one (& self) -> bool { * self == DOUT31_0_DIO30_A :: DOUT31_0_DIO30_ONE } } # [doc = "Field `DOUT31_0_DIO30` writer - This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO30_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio30_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO30_A :: DOUT31_0_DIO30_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio30_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO30_A :: DOUT31_0_DIO30_ONE) } } # [doc = "Field `DOUT31_0_DIO31` reader - This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO31_R = crate :: BitReader < DOUT31_0_DIO31_A > ; # [doc = "This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUT31_0_DIO31_A { # [doc = "0: ZERO"]
DOUT31_0_DIO31_ZERO = 0 , # [doc = "1: ONE"]
DOUT31_0_DIO31_ONE = 1 , } impl From < DOUT31_0_DIO31_A > for bool { # [inline (always)]
fn from (variant : DOUT31_0_DIO31_A) -> Self { variant as u8 != 0 } } impl DOUT31_0_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOUT31_0_DIO31_A { match self . bits { false => DOUT31_0_DIO31_A :: DOUT31_0_DIO31_ZERO , true => DOUT31_0_DIO31_A :: DOUT31_0_DIO31_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_dout31_0_dio31_zero (& self) -> bool { * self == DOUT31_0_DIO31_A :: DOUT31_0_DIO31_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_dout31_0_dio31_one (& self) -> bool { * self == DOUT31_0_DIO31_A :: DOUT31_0_DIO31_ONE } } # [doc = "Field `DOUT31_0_DIO31` writer - This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register."]
pub type DOUT31_0_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUT31_0_DIO31_A > ; impl < 'a , REG , const O : u8 > DOUT31_0_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ZERO"]
# [inline (always)]
pub fn dout31_0_dio31_zero (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO31_A :: DOUT31_0_DIO31_ZERO) } # [doc = "ONE"]
# [inline (always)]
pub fn dout31_0_dio31_one (self) -> & 'a mut crate :: W < REG > { self . variant (DOUT31_0_DIO31_A :: DOUT31_0_DIO31_ONE) } } impl R { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio0 (& self) -> DOUT31_0_DIO0_R { DOUT31_0_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio1 (& self) -> DOUT31_0_DIO1_R { DOUT31_0_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio2 (& self) -> DOUT31_0_DIO2_R { DOUT31_0_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio3 (& self) -> DOUT31_0_DIO3_R { DOUT31_0_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio4 (& self) -> DOUT31_0_DIO4_R { DOUT31_0_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio5 (& self) -> DOUT31_0_DIO5_R { DOUT31_0_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio6 (& self) -> DOUT31_0_DIO6_R { DOUT31_0_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio7 (& self) -> DOUT31_0_DIO7_R { DOUT31_0_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio8 (& self) -> DOUT31_0_DIO8_R { DOUT31_0_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio9 (& self) -> DOUT31_0_DIO9_R { DOUT31_0_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio10 (& self) -> DOUT31_0_DIO10_R { DOUT31_0_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio11 (& self) -> DOUT31_0_DIO11_R { DOUT31_0_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio12 (& self) -> DOUT31_0_DIO12_R { DOUT31_0_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio13 (& self) -> DOUT31_0_DIO13_R { DOUT31_0_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio14 (& self) -> DOUT31_0_DIO14_R { DOUT31_0_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio15 (& self) -> DOUT31_0_DIO15_R { DOUT31_0_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio16 (& self) -> DOUT31_0_DIO16_R { DOUT31_0_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio17 (& self) -> DOUT31_0_DIO17_R { DOUT31_0_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio18 (& self) -> DOUT31_0_DIO18_R { DOUT31_0_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio19 (& self) -> DOUT31_0_DIO19_R { DOUT31_0_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio20 (& self) -> DOUT31_0_DIO20_R { DOUT31_0_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio21 (& self) -> DOUT31_0_DIO21_R { DOUT31_0_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio22 (& self) -> DOUT31_0_DIO22_R { DOUT31_0_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio23 (& self) -> DOUT31_0_DIO23_R { DOUT31_0_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio24 (& self) -> DOUT31_0_DIO24_R { DOUT31_0_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio25 (& self) -> DOUT31_0_DIO25_R { DOUT31_0_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio26 (& self) -> DOUT31_0_DIO26_R { DOUT31_0_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio27 (& self) -> DOUT31_0_DIO27_R { DOUT31_0_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio28 (& self) -> DOUT31_0_DIO28_R { DOUT31_0_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio29 (& self) -> DOUT31_0_DIO29_R { DOUT31_0_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio30 (& self) -> DOUT31_0_DIO30_R { DOUT31_0_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register."]
# [inline (always)]
pub fn dout31_0_dio31 (& self) -> DOUT31_0_DIO31_R { DOUT31_0_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - This bit sets the value of the pin configured as DIO0 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio0 (& mut self) -> DOUT31_0_DIO0_W < DOUT31_0_SPEC , 0 > { DOUT31_0_DIO0_W :: new (self) } # [doc = "Bit 1 - This bit sets the value of the pin configured as DIO1 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio1 (& mut self) -> DOUT31_0_DIO1_W < DOUT31_0_SPEC , 1 > { DOUT31_0_DIO1_W :: new (self) } # [doc = "Bit 2 - This bit sets the value of the pin configured as DIO2 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio2 (& mut self) -> DOUT31_0_DIO2_W < DOUT31_0_SPEC , 2 > { DOUT31_0_DIO2_W :: new (self) } # [doc = "Bit 3 - This bit sets the value of the pin configured as DIO3 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio3 (& mut self) -> DOUT31_0_DIO3_W < DOUT31_0_SPEC , 3 > { DOUT31_0_DIO3_W :: new (self) } # [doc = "Bit 4 - This bit sets the value of the pin configured as DIO4 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio4 (& mut self) -> DOUT31_0_DIO4_W < DOUT31_0_SPEC , 4 > { DOUT31_0_DIO4_W :: new (self) } # [doc = "Bit 5 - This bit sets the value of the pin configured as DIO5 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio5 (& mut self) -> DOUT31_0_DIO5_W < DOUT31_0_SPEC , 5 > { DOUT31_0_DIO5_W :: new (self) } # [doc = "Bit 6 - This bit sets the value of the pin configured as DIO6 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio6 (& mut self) -> DOUT31_0_DIO6_W < DOUT31_0_SPEC , 6 > { DOUT31_0_DIO6_W :: new (self) } # [doc = "Bit 7 - This bit sets the value of the pin configured as DIO7 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio7 (& mut self) -> DOUT31_0_DIO7_W < DOUT31_0_SPEC , 7 > { DOUT31_0_DIO7_W :: new (self) } # [doc = "Bit 8 - This bit sets the value of the pin configured as DIO8 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio8 (& mut self) -> DOUT31_0_DIO8_W < DOUT31_0_SPEC , 8 > { DOUT31_0_DIO8_W :: new (self) } # [doc = "Bit 9 - This bit sets the value of the pin configured as DIO9 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio9 (& mut self) -> DOUT31_0_DIO9_W < DOUT31_0_SPEC , 9 > { DOUT31_0_DIO9_W :: new (self) } # [doc = "Bit 10 - This bit sets the value of the pin configured as DIO10 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio10 (& mut self) -> DOUT31_0_DIO10_W < DOUT31_0_SPEC , 10 > { DOUT31_0_DIO10_W :: new (self) } # [doc = "Bit 11 - This bit sets the value of the pin configured as DIO11 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio11 (& mut self) -> DOUT31_0_DIO11_W < DOUT31_0_SPEC , 11 > { DOUT31_0_DIO11_W :: new (self) } # [doc = "Bit 12 - This bit sets the value of the pin configured as DIO12 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio12 (& mut self) -> DOUT31_0_DIO12_W < DOUT31_0_SPEC , 12 > { DOUT31_0_DIO12_W :: new (self) } # [doc = "Bit 13 - This bit sets the value of the pin configured as DIO13 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio13 (& mut self) -> DOUT31_0_DIO13_W < DOUT31_0_SPEC , 13 > { DOUT31_0_DIO13_W :: new (self) } # [doc = "Bit 14 - This bit sets the value of the pin configured as DIO14 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio14 (& mut self) -> DOUT31_0_DIO14_W < DOUT31_0_SPEC , 14 > { DOUT31_0_DIO14_W :: new (self) } # [doc = "Bit 15 - This bit sets the value of the pin configured as DIO15 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio15 (& mut self) -> DOUT31_0_DIO15_W < DOUT31_0_SPEC , 15 > { DOUT31_0_DIO15_W :: new (self) } # [doc = "Bit 16 - This bit sets the value of the pin configured as DIO16 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio16 (& mut self) -> DOUT31_0_DIO16_W < DOUT31_0_SPEC , 16 > { DOUT31_0_DIO16_W :: new (self) } # [doc = "Bit 17 - This bit sets the value of the pin configured as DIO17 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio17 (& mut self) -> DOUT31_0_DIO17_W < DOUT31_0_SPEC , 17 > { DOUT31_0_DIO17_W :: new (self) } # [doc = "Bit 18 - This bit sets the value of the pin configured as DIO18 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio18 (& mut self) -> DOUT31_0_DIO18_W < DOUT31_0_SPEC , 18 > { DOUT31_0_DIO18_W :: new (self) } # [doc = "Bit 19 - This bit sets the value of the pin configured as DIO19 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio19 (& mut self) -> DOUT31_0_DIO19_W < DOUT31_0_SPEC , 19 > { DOUT31_0_DIO19_W :: new (self) } # [doc = "Bit 20 - This bit sets the value of the pin configured as DIO20 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio20 (& mut self) -> DOUT31_0_DIO20_W < DOUT31_0_SPEC , 20 > { DOUT31_0_DIO20_W :: new (self) } # [doc = "Bit 21 - This bit sets the value of the pin configured as DIO21 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio21 (& mut self) -> DOUT31_0_DIO21_W < DOUT31_0_SPEC , 21 > { DOUT31_0_DIO21_W :: new (self) } # [doc = "Bit 22 - This bit sets the value of the pin configured as DIO22 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio22 (& mut self) -> DOUT31_0_DIO22_W < DOUT31_0_SPEC , 22 > { DOUT31_0_DIO22_W :: new (self) } # [doc = "Bit 23 - This bit sets the value of the pin configured as DIO23 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio23 (& mut self) -> DOUT31_0_DIO23_W < DOUT31_0_SPEC , 23 > { DOUT31_0_DIO23_W :: new (self) } # [doc = "Bit 24 - This bit sets the value of the pin configured as DIO24 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio24 (& mut self) -> DOUT31_0_DIO24_W < DOUT31_0_SPEC , 24 > { DOUT31_0_DIO24_W :: new (self) } # [doc = "Bit 25 - This bit sets the value of the pin configured as DIO25 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio25 (& mut self) -> DOUT31_0_DIO25_W < DOUT31_0_SPEC , 25 > { DOUT31_0_DIO25_W :: new (self) } # [doc = "Bit 26 - This bit sets the value of the pin configured as DIO26 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio26 (& mut self) -> DOUT31_0_DIO26_W < DOUT31_0_SPEC , 26 > { DOUT31_0_DIO26_W :: new (self) } # [doc = "Bit 27 - This bit sets the value of the pin configured as DIO27 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio27 (& mut self) -> DOUT31_0_DIO27_W < DOUT31_0_SPEC , 27 > { DOUT31_0_DIO27_W :: new (self) } # [doc = "Bit 28 - This bit sets the value of the pin configured as DIO28 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio28 (& mut self) -> DOUT31_0_DIO28_W < DOUT31_0_SPEC , 28 > { DOUT31_0_DIO28_W :: new (self) } # [doc = "Bit 29 - This bit sets the value of the pin configured as DIO29 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio29 (& mut self) -> DOUT31_0_DIO29_W < DOUT31_0_SPEC , 29 > { DOUT31_0_DIO29_W :: new (self) } # [doc = "Bit 30 - This bit sets the value of the pin configured as DIO30 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio30 (& mut self) -> DOUT31_0_DIO30_W < DOUT31_0_SPEC , 30 > { DOUT31_0_DIO30_W :: new (self) } # [doc = "Bit 31 - This bit sets the value of the pin configured as DIO31 when the output is enabled through DOE31_0 register."]
# [inline (always)]
# [must_use]
pub fn dout31_0_dio31 (& mut self) -> DOUT31_0_DIO31_W < DOUT31_0_SPEC , 31 > { DOUT31_0_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dout31_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dout31_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUT31_0_SPEC ; impl crate :: RegisterSpec for DOUT31_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dout31_0::R`](R) reader structure"]
impl crate :: Readable for DOUT31_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`dout31_0::W`](W) writer structure"]
impl crate :: Writable for DOUT31_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUT31_0 to value 0"]
impl crate :: Resettable for DOUT31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUTSET31_0 (w) register accessor: Data output set 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doutset31_0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doutset31_0`]
module"]
pub type DOUTSET31_0 = crate :: Reg < doutset31_0 :: DOUTSET31_0_SPEC > ; # [doc = "Data output set 31 to 0"]
pub mod doutset31_0 { # [doc = "Register `DOUTSET31_0` writer"]
pub type W = crate :: W < DOUTSET31_0_SPEC > ; # [doc = "Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO0_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO0_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO0_SET = 1 , } impl From < DOUTSET31_0_DIO0_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO0` writer - Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO0_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO0_AW :: DOUTSET31_0_DIO0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO0_AW :: DOUTSET31_0_DIO0_SET) } } # [doc = "Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO1_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO1_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO1_SET = 1 , } impl From < DOUTSET31_0_DIO1_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO1` writer - Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO1_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO1_AW :: DOUTSET31_0_DIO1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO1_AW :: DOUTSET31_0_DIO1_SET) } } # [doc = "Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO2_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO2_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO2_SET = 1 , } impl From < DOUTSET31_0_DIO2_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO2` writer - Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO2_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO2_AW :: DOUTSET31_0_DIO2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO2_AW :: DOUTSET31_0_DIO2_SET) } } # [doc = "Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO3_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO3_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO3_SET = 1 , } impl From < DOUTSET31_0_DIO3_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO3` writer - Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO3_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO3_AW :: DOUTSET31_0_DIO3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO3_AW :: DOUTSET31_0_DIO3_SET) } } # [doc = "Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO4_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO4_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO4_SET = 1 , } impl From < DOUTSET31_0_DIO4_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO4` writer - Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO4_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO4_AW :: DOUTSET31_0_DIO4_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO4_AW :: DOUTSET31_0_DIO4_SET) } } # [doc = "Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO5_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO5_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO5_SET = 1 , } impl From < DOUTSET31_0_DIO5_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO5` writer - Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO5_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO5_AW :: DOUTSET31_0_DIO5_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO5_AW :: DOUTSET31_0_DIO5_SET) } } # [doc = "Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO6_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO6_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO6_SET = 1 , } impl From < DOUTSET31_0_DIO6_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO6` writer - Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO6_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO6_AW :: DOUTSET31_0_DIO6_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO6_AW :: DOUTSET31_0_DIO6_SET) } } # [doc = "Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO7_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO7_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO7_SET = 1 , } impl From < DOUTSET31_0_DIO7_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO7` writer - Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO7_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO7_AW :: DOUTSET31_0_DIO7_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO7_AW :: DOUTSET31_0_DIO7_SET) } } # [doc = "Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO8_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO8_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO8_SET = 1 , } impl From < DOUTSET31_0_DIO8_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO8` writer - Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO8_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO8_AW :: DOUTSET31_0_DIO8_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO8_AW :: DOUTSET31_0_DIO8_SET) } } # [doc = "Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO9_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO9_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO9_SET = 1 , } impl From < DOUTSET31_0_DIO9_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO9` writer - Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO9_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO9_AW :: DOUTSET31_0_DIO9_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO9_AW :: DOUTSET31_0_DIO9_SET) } } # [doc = "Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO10_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO10_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO10_SET = 1 , } impl From < DOUTSET31_0_DIO10_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO10` writer - Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO10_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO10_AW :: DOUTSET31_0_DIO10_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO10_AW :: DOUTSET31_0_DIO10_SET) } } # [doc = "Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO11_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO11_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO11_SET = 1 , } impl From < DOUTSET31_0_DIO11_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO11` writer - Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO11_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO11_AW :: DOUTSET31_0_DIO11_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO11_AW :: DOUTSET31_0_DIO11_SET) } } # [doc = "Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO12_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO12_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO12_SET = 1 , } impl From < DOUTSET31_0_DIO12_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO12` writer - Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO12_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO12_AW :: DOUTSET31_0_DIO12_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO12_AW :: DOUTSET31_0_DIO12_SET) } } # [doc = "Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO13_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO13_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO13_SET = 1 , } impl From < DOUTSET31_0_DIO13_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO13` writer - Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO13_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO13_AW :: DOUTSET31_0_DIO13_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO13_AW :: DOUTSET31_0_DIO13_SET) } } # [doc = "Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO14_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO14_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO14_SET = 1 , } impl From < DOUTSET31_0_DIO14_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO14` writer - Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO14_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO14_AW :: DOUTSET31_0_DIO14_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO14_AW :: DOUTSET31_0_DIO14_SET) } } # [doc = "Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO15_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO15_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO15_SET = 1 , } impl From < DOUTSET31_0_DIO15_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO15` writer - Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO15_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO15_AW :: DOUTSET31_0_DIO15_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO15_AW :: DOUTSET31_0_DIO15_SET) } } # [doc = "Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO16_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO16_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO16_SET = 1 , } impl From < DOUTSET31_0_DIO16_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO16` writer - Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO16_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO16_AW :: DOUTSET31_0_DIO16_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO16_AW :: DOUTSET31_0_DIO16_SET) } } # [doc = "Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO17_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO17_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO17_SET = 1 , } impl From < DOUTSET31_0_DIO17_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO17` writer - Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO17_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO17_AW :: DOUTSET31_0_DIO17_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO17_AW :: DOUTSET31_0_DIO17_SET) } } # [doc = "Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO18_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO18_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO18_SET = 1 , } impl From < DOUTSET31_0_DIO18_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO18` writer - Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO18_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO18_AW :: DOUTSET31_0_DIO18_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO18_AW :: DOUTSET31_0_DIO18_SET) } } # [doc = "Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO19_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO19_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO19_SET = 1 , } impl From < DOUTSET31_0_DIO19_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO19` writer - Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO19_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO19_AW :: DOUTSET31_0_DIO19_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO19_AW :: DOUTSET31_0_DIO19_SET) } } # [doc = "Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO20_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO20_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO20_SET = 1 , } impl From < DOUTSET31_0_DIO20_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO20` writer - Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO20_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO20_AW :: DOUTSET31_0_DIO20_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO20_AW :: DOUTSET31_0_DIO20_SET) } } # [doc = "Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO21_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO21_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO21_SET = 1 , } impl From < DOUTSET31_0_DIO21_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO21` writer - Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO21_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO21_AW :: DOUTSET31_0_DIO21_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO21_AW :: DOUTSET31_0_DIO21_SET) } } # [doc = "Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO22_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO22_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO22_SET = 1 , } impl From < DOUTSET31_0_DIO22_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO22` writer - Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO22_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO22_AW :: DOUTSET31_0_DIO22_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO22_AW :: DOUTSET31_0_DIO22_SET) } } # [doc = "Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO23_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO23_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO23_SET = 1 , } impl From < DOUTSET31_0_DIO23_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO23` writer - Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO23_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO23_AW :: DOUTSET31_0_DIO23_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO23_AW :: DOUTSET31_0_DIO23_SET) } } # [doc = "Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO24_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO24_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO24_SET = 1 , } impl From < DOUTSET31_0_DIO24_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO24` writer - Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO24_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO24_AW :: DOUTSET31_0_DIO24_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO24_AW :: DOUTSET31_0_DIO24_SET) } } # [doc = "Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO25_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO25_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO25_SET = 1 , } impl From < DOUTSET31_0_DIO25_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO25` writer - Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO25_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO25_AW :: DOUTSET31_0_DIO25_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO25_AW :: DOUTSET31_0_DIO25_SET) } } # [doc = "Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO26_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO26_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO26_SET = 1 , } impl From < DOUTSET31_0_DIO26_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO26` writer - Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO26_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO26_AW :: DOUTSET31_0_DIO26_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO26_AW :: DOUTSET31_0_DIO26_SET) } } # [doc = "Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO27_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO27_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO27_SET = 1 , } impl From < DOUTSET31_0_DIO27_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO27` writer - Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO27_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO27_AW :: DOUTSET31_0_DIO27_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO27_AW :: DOUTSET31_0_DIO27_SET) } } # [doc = "Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO28_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO28_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO28_SET = 1 , } impl From < DOUTSET31_0_DIO28_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO28` writer - Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO28_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO28_AW :: DOUTSET31_0_DIO28_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO28_AW :: DOUTSET31_0_DIO28_SET) } } # [doc = "Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO29_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO29_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO29_SET = 1 , } impl From < DOUTSET31_0_DIO29_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO29` writer - Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO29_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO29_AW :: DOUTSET31_0_DIO29_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO29_AW :: DOUTSET31_0_DIO29_SET) } } # [doc = "Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO30_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO30_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO30_SET = 1 , } impl From < DOUTSET31_0_DIO30_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO30` writer - Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO30_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO30_AW :: DOUTSET31_0_DIO30_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO30_AW :: DOUTSET31_0_DIO30_SET) } } # [doc = "Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTSET31_0_DIO31_AW { # [doc = "0: NO_EFFECT"]
DOUTSET31_0_DIO31_NO_EFFECT = 0 , # [doc = "1: SET"]
DOUTSET31_0_DIO31_SET = 1 , } impl From < DOUTSET31_0_DIO31_AW > for bool { # [inline (always)]
fn from (variant : DOUTSET31_0_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTSET31_0_DIO31` writer - Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTSET31_0_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTSET31_0_DIO31_AW > ; impl < 'a , REG , const O : u8 > DOUTSET31_0_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutset31_0_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO31_AW :: DOUTSET31_0_DIO31_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doutset31_0_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTSET31_0_DIO31_AW :: DOUTSET31_0_DIO31_SET) } } impl W { # [doc = "Bit 0 - Writing 1 to this bit sets the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio0 (& mut self) -> DOUTSET31_0_DIO0_W < DOUTSET31_0_SPEC , 0 > { DOUTSET31_0_DIO0_W :: new (self) } # [doc = "Bit 1 - Writing 1 to this bit sets the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio1 (& mut self) -> DOUTSET31_0_DIO1_W < DOUTSET31_0_SPEC , 1 > { DOUTSET31_0_DIO1_W :: new (self) } # [doc = "Bit 2 - Writing 1 to this bit sets the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio2 (& mut self) -> DOUTSET31_0_DIO2_W < DOUTSET31_0_SPEC , 2 > { DOUTSET31_0_DIO2_W :: new (self) } # [doc = "Bit 3 - Writing 1 to this bit sets the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio3 (& mut self) -> DOUTSET31_0_DIO3_W < DOUTSET31_0_SPEC , 3 > { DOUTSET31_0_DIO3_W :: new (self) } # [doc = "Bit 4 - Writing 1 to this bit sets the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio4 (& mut self) -> DOUTSET31_0_DIO4_W < DOUTSET31_0_SPEC , 4 > { DOUTSET31_0_DIO4_W :: new (self) } # [doc = "Bit 5 - Writing 1 to this bit sets the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio5 (& mut self) -> DOUTSET31_0_DIO5_W < DOUTSET31_0_SPEC , 5 > { DOUTSET31_0_DIO5_W :: new (self) } # [doc = "Bit 6 - Writing 1 to this bit sets the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio6 (& mut self) -> DOUTSET31_0_DIO6_W < DOUTSET31_0_SPEC , 6 > { DOUTSET31_0_DIO6_W :: new (self) } # [doc = "Bit 7 - Writing 1 to this bit sets the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio7 (& mut self) -> DOUTSET31_0_DIO7_W < DOUTSET31_0_SPEC , 7 > { DOUTSET31_0_DIO7_W :: new (self) } # [doc = "Bit 8 - Writing 1 to this bit sets the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio8 (& mut self) -> DOUTSET31_0_DIO8_W < DOUTSET31_0_SPEC , 8 > { DOUTSET31_0_DIO8_W :: new (self) } # [doc = "Bit 9 - Writing 1 to this bit sets the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio9 (& mut self) -> DOUTSET31_0_DIO9_W < DOUTSET31_0_SPEC , 9 > { DOUTSET31_0_DIO9_W :: new (self) } # [doc = "Bit 10 - Writing 1 to this bit sets the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio10 (& mut self) -> DOUTSET31_0_DIO10_W < DOUTSET31_0_SPEC , 10 > { DOUTSET31_0_DIO10_W :: new (self) } # [doc = "Bit 11 - Writing 1 to this bit sets the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio11 (& mut self) -> DOUTSET31_0_DIO11_W < DOUTSET31_0_SPEC , 11 > { DOUTSET31_0_DIO11_W :: new (self) } # [doc = "Bit 12 - Writing 1 to this bit sets the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio12 (& mut self) -> DOUTSET31_0_DIO12_W < DOUTSET31_0_SPEC , 12 > { DOUTSET31_0_DIO12_W :: new (self) } # [doc = "Bit 13 - Writing 1 to this bit sets the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio13 (& mut self) -> DOUTSET31_0_DIO13_W < DOUTSET31_0_SPEC , 13 > { DOUTSET31_0_DIO13_W :: new (self) } # [doc = "Bit 14 - Writing 1 to this bit sets the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio14 (& mut self) -> DOUTSET31_0_DIO14_W < DOUTSET31_0_SPEC , 14 > { DOUTSET31_0_DIO14_W :: new (self) } # [doc = "Bit 15 - Writing 1 to this bit sets the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio15 (& mut self) -> DOUTSET31_0_DIO15_W < DOUTSET31_0_SPEC , 15 > { DOUTSET31_0_DIO15_W :: new (self) } # [doc = "Bit 16 - Writing 1 to this bit sets the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio16 (& mut self) -> DOUTSET31_0_DIO16_W < DOUTSET31_0_SPEC , 16 > { DOUTSET31_0_DIO16_W :: new (self) } # [doc = "Bit 17 - Writing 1 to this bit sets the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio17 (& mut self) -> DOUTSET31_0_DIO17_W < DOUTSET31_0_SPEC , 17 > { DOUTSET31_0_DIO17_W :: new (self) } # [doc = "Bit 18 - Writing 1 to this bit sets the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio18 (& mut self) -> DOUTSET31_0_DIO18_W < DOUTSET31_0_SPEC , 18 > { DOUTSET31_0_DIO18_W :: new (self) } # [doc = "Bit 19 - Writing 1 to this bit sets the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio19 (& mut self) -> DOUTSET31_0_DIO19_W < DOUTSET31_0_SPEC , 19 > { DOUTSET31_0_DIO19_W :: new (self) } # [doc = "Bit 20 - Writing 1 to this bit sets the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio20 (& mut self) -> DOUTSET31_0_DIO20_W < DOUTSET31_0_SPEC , 20 > { DOUTSET31_0_DIO20_W :: new (self) } # [doc = "Bit 21 - Writing 1 to this bit sets the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio21 (& mut self) -> DOUTSET31_0_DIO21_W < DOUTSET31_0_SPEC , 21 > { DOUTSET31_0_DIO21_W :: new (self) } # [doc = "Bit 22 - Writing 1 to this bit sets the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio22 (& mut self) -> DOUTSET31_0_DIO22_W < DOUTSET31_0_SPEC , 22 > { DOUTSET31_0_DIO22_W :: new (self) } # [doc = "Bit 23 - Writing 1 to this bit sets the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio23 (& mut self) -> DOUTSET31_0_DIO23_W < DOUTSET31_0_SPEC , 23 > { DOUTSET31_0_DIO23_W :: new (self) } # [doc = "Bit 24 - Writing 1 to this bit sets the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio24 (& mut self) -> DOUTSET31_0_DIO24_W < DOUTSET31_0_SPEC , 24 > { DOUTSET31_0_DIO24_W :: new (self) } # [doc = "Bit 25 - Writing 1 to this bit sets the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio25 (& mut self) -> DOUTSET31_0_DIO25_W < DOUTSET31_0_SPEC , 25 > { DOUTSET31_0_DIO25_W :: new (self) } # [doc = "Bit 26 - Writing 1 to this bit sets the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio26 (& mut self) -> DOUTSET31_0_DIO26_W < DOUTSET31_0_SPEC , 26 > { DOUTSET31_0_DIO26_W :: new (self) } # [doc = "Bit 27 - Writing 1 to this bit sets the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio27 (& mut self) -> DOUTSET31_0_DIO27_W < DOUTSET31_0_SPEC , 27 > { DOUTSET31_0_DIO27_W :: new (self) } # [doc = "Bit 28 - Writing 1 to this bit sets the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio28 (& mut self) -> DOUTSET31_0_DIO28_W < DOUTSET31_0_SPEC , 28 > { DOUTSET31_0_DIO28_W :: new (self) } # [doc = "Bit 29 - Writing 1 to this bit sets the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio29 (& mut self) -> DOUTSET31_0_DIO29_W < DOUTSET31_0_SPEC , 29 > { DOUTSET31_0_DIO29_W :: new (self) } # [doc = "Bit 30 - Writing 1 to this bit sets the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio30 (& mut self) -> DOUTSET31_0_DIO30_W < DOUTSET31_0_SPEC , 30 > { DOUTSET31_0_DIO30_W :: new (self) } # [doc = "Bit 31 - Writing 1 to this bit sets the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutset31_0_dio31 (& mut self) -> DOUTSET31_0_DIO31_W < DOUTSET31_0_SPEC , 31 > { DOUTSET31_0_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output set 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doutset31_0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUTSET31_0_SPEC ; impl crate :: RegisterSpec for DOUTSET31_0_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`doutset31_0::W`](W) writer structure"]
impl crate :: Writable for DOUTSET31_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUTSET31_0 to value 0"]
impl crate :: Resettable for DOUTSET31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUTCLR31_0 (w) register accessor: Data output clear 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doutclr31_0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doutclr31_0`]
module"]
pub type DOUTCLR31_0 = crate :: Reg < doutclr31_0 :: DOUTCLR31_0_SPEC > ; # [doc = "Data output clear 31 to 0"]
pub mod doutclr31_0 { # [doc = "Register `DOUTCLR31_0` writer"]
pub type W = crate :: W < DOUTCLR31_0_SPEC > ; # [doc = "Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO0_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO0_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO0_CLR = 1 , } impl From < DOUTCLR31_0_DIO0_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO0` writer - Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO0_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO0_AW :: DOUTCLR31_0_DIO0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO0_AW :: DOUTCLR31_0_DIO0_CLR) } } # [doc = "Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO1_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO1_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO1_CLR = 1 , } impl From < DOUTCLR31_0_DIO1_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO1` writer - Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO1_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO1_AW :: DOUTCLR31_0_DIO1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO1_AW :: DOUTCLR31_0_DIO1_CLR) } } # [doc = "Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO2_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO2_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO2_CLR = 1 , } impl From < DOUTCLR31_0_DIO2_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO2` writer - Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO2_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO2_AW :: DOUTCLR31_0_DIO2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO2_AW :: DOUTCLR31_0_DIO2_CLR) } } # [doc = "Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO3_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO3_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO3_CLR = 1 , } impl From < DOUTCLR31_0_DIO3_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO3` writer - Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO3_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO3_AW :: DOUTCLR31_0_DIO3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO3_AW :: DOUTCLR31_0_DIO3_CLR) } } # [doc = "Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO4_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO4_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO4_CLR = 1 , } impl From < DOUTCLR31_0_DIO4_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO4` writer - Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO4_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO4_AW :: DOUTCLR31_0_DIO4_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO4_AW :: DOUTCLR31_0_DIO4_CLR) } } # [doc = "Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO5_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO5_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO5_CLR = 1 , } impl From < DOUTCLR31_0_DIO5_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO5` writer - Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO5_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO5_AW :: DOUTCLR31_0_DIO5_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO5_AW :: DOUTCLR31_0_DIO5_CLR) } } # [doc = "Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO6_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO6_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO6_CLR = 1 , } impl From < DOUTCLR31_0_DIO6_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO6` writer - Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO6_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO6_AW :: DOUTCLR31_0_DIO6_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO6_AW :: DOUTCLR31_0_DIO6_CLR) } } # [doc = "Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO7_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO7_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO7_CLR = 1 , } impl From < DOUTCLR31_0_DIO7_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO7` writer - Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO7_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO7_AW :: DOUTCLR31_0_DIO7_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO7_AW :: DOUTCLR31_0_DIO7_CLR) } } # [doc = "Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO8_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO8_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO8_CLR = 1 , } impl From < DOUTCLR31_0_DIO8_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO8` writer - Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO8_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO8_AW :: DOUTCLR31_0_DIO8_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO8_AW :: DOUTCLR31_0_DIO8_CLR) } } # [doc = "Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO9_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO9_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO9_CLR = 1 , } impl From < DOUTCLR31_0_DIO9_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO9` writer - Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO9_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO9_AW :: DOUTCLR31_0_DIO9_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO9_AW :: DOUTCLR31_0_DIO9_CLR) } } # [doc = "Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO10_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO10_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO10_CLR = 1 , } impl From < DOUTCLR31_0_DIO10_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO10` writer - Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO10_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO10_AW :: DOUTCLR31_0_DIO10_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO10_AW :: DOUTCLR31_0_DIO10_CLR) } } # [doc = "Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO11_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO11_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO11_CLR = 1 , } impl From < DOUTCLR31_0_DIO11_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO11` writer - Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO11_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO11_AW :: DOUTCLR31_0_DIO11_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO11_AW :: DOUTCLR31_0_DIO11_CLR) } } # [doc = "Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO12_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO12_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO12_CLR = 1 , } impl From < DOUTCLR31_0_DIO12_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO12` writer - Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO12_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO12_AW :: DOUTCLR31_0_DIO12_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO12_AW :: DOUTCLR31_0_DIO12_CLR) } } # [doc = "Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO13_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO13_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO13_CLR = 1 , } impl From < DOUTCLR31_0_DIO13_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO13` writer - Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO13_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO13_AW :: DOUTCLR31_0_DIO13_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO13_AW :: DOUTCLR31_0_DIO13_CLR) } } # [doc = "Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO14_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO14_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO14_CLR = 1 , } impl From < DOUTCLR31_0_DIO14_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO14` writer - Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO14_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO14_AW :: DOUTCLR31_0_DIO14_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO14_AW :: DOUTCLR31_0_DIO14_CLR) } } # [doc = "Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO15_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO15_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO15_CLR = 1 , } impl From < DOUTCLR31_0_DIO15_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO15` writer - Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO15_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO15_AW :: DOUTCLR31_0_DIO15_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO15_AW :: DOUTCLR31_0_DIO15_CLR) } } # [doc = "Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO16_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO16_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO16_CLR = 1 , } impl From < DOUTCLR31_0_DIO16_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO16` writer - Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO16_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO16_AW :: DOUTCLR31_0_DIO16_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO16_AW :: DOUTCLR31_0_DIO16_CLR) } } # [doc = "Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO17_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO17_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO17_CLR = 1 , } impl From < DOUTCLR31_0_DIO17_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO17` writer - Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO17_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO17_AW :: DOUTCLR31_0_DIO17_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO17_AW :: DOUTCLR31_0_DIO17_CLR) } } # [doc = "Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO18_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO18_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO18_CLR = 1 , } impl From < DOUTCLR31_0_DIO18_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO18` writer - Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO18_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO18_AW :: DOUTCLR31_0_DIO18_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO18_AW :: DOUTCLR31_0_DIO18_CLR) } } # [doc = "Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO19_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO19_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO19_CLR = 1 , } impl From < DOUTCLR31_0_DIO19_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO19` writer - Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO19_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO19_AW :: DOUTCLR31_0_DIO19_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO19_AW :: DOUTCLR31_0_DIO19_CLR) } } # [doc = "Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO20_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO20_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO20_CLR = 1 , } impl From < DOUTCLR31_0_DIO20_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO20` writer - Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO20_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO20_AW :: DOUTCLR31_0_DIO20_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO20_AW :: DOUTCLR31_0_DIO20_CLR) } } # [doc = "Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO21_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO21_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO21_CLR = 1 , } impl From < DOUTCLR31_0_DIO21_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO21` writer - Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO21_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO21_AW :: DOUTCLR31_0_DIO21_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO21_AW :: DOUTCLR31_0_DIO21_CLR) } } # [doc = "Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO22_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO22_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO22_CLR = 1 , } impl From < DOUTCLR31_0_DIO22_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO22` writer - Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO22_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO22_AW :: DOUTCLR31_0_DIO22_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO22_AW :: DOUTCLR31_0_DIO22_CLR) } } # [doc = "Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO23_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO23_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO23_CLR = 1 , } impl From < DOUTCLR31_0_DIO23_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO23` writer - Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO23_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO23_AW :: DOUTCLR31_0_DIO23_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO23_AW :: DOUTCLR31_0_DIO23_CLR) } } # [doc = "Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO24_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO24_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO24_CLR = 1 , } impl From < DOUTCLR31_0_DIO24_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO24` writer - Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO24_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO24_AW :: DOUTCLR31_0_DIO24_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO24_AW :: DOUTCLR31_0_DIO24_CLR) } } # [doc = "Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO25_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO25_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO25_CLR = 1 , } impl From < DOUTCLR31_0_DIO25_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO25` writer - Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO25_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO25_AW :: DOUTCLR31_0_DIO25_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO25_AW :: DOUTCLR31_0_DIO25_CLR) } } # [doc = "Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO26_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO26_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO26_CLR = 1 , } impl From < DOUTCLR31_0_DIO26_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO26` writer - Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO26_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO26_AW :: DOUTCLR31_0_DIO26_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO26_AW :: DOUTCLR31_0_DIO26_CLR) } } # [doc = "Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO27_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO27_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO27_CLR = 1 , } impl From < DOUTCLR31_0_DIO27_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO27` writer - Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO27_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO27_AW :: DOUTCLR31_0_DIO27_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO27_AW :: DOUTCLR31_0_DIO27_CLR) } } # [doc = "Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO28_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO28_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO28_CLR = 1 , } impl From < DOUTCLR31_0_DIO28_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO28` writer - Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO28_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO28_AW :: DOUTCLR31_0_DIO28_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO28_AW :: DOUTCLR31_0_DIO28_CLR) } } # [doc = "Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO29_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO29_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO29_CLR = 1 , } impl From < DOUTCLR31_0_DIO29_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO29` writer - Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO29_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO29_AW :: DOUTCLR31_0_DIO29_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO29_AW :: DOUTCLR31_0_DIO29_CLR) } } # [doc = "Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO30_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO30_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO30_CLR = 1 , } impl From < DOUTCLR31_0_DIO30_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO30` writer - Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO30_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO30_AW :: DOUTCLR31_0_DIO30_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO30_AW :: DOUTCLR31_0_DIO30_CLR) } } # [doc = "Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTCLR31_0_DIO31_AW { # [doc = "0: NO_EFFECT"]
DOUTCLR31_0_DIO31_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOUTCLR31_0_DIO31_CLR = 1 , } impl From < DOUTCLR31_0_DIO31_AW > for bool { # [inline (always)]
fn from (variant : DOUTCLR31_0_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTCLR31_0_DIO31` writer - Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect."]
pub type DOUTCLR31_0_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTCLR31_0_DIO31_AW > ; impl < 'a , REG , const O : u8 > DOUTCLR31_0_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doutclr31_0_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO31_AW :: DOUTCLR31_0_DIO31_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doutclr31_0_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTCLR31_0_DIO31_AW :: DOUTCLR31_0_DIO31_CLR) } } impl W { # [doc = "Bit 0 - Writing 1 to this bit clears the DIO0 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio0 (& mut self) -> DOUTCLR31_0_DIO0_W < DOUTCLR31_0_SPEC , 0 > { DOUTCLR31_0_DIO0_W :: new (self) } # [doc = "Bit 1 - Writing 1 to this bit clears the DIO1 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio1 (& mut self) -> DOUTCLR31_0_DIO1_W < DOUTCLR31_0_SPEC , 1 > { DOUTCLR31_0_DIO1_W :: new (self) } # [doc = "Bit 2 - Writing 1 to this bit clears the DIO2 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio2 (& mut self) -> DOUTCLR31_0_DIO2_W < DOUTCLR31_0_SPEC , 2 > { DOUTCLR31_0_DIO2_W :: new (self) } # [doc = "Bit 3 - Writing 1 to this bit clears the DIO3 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio3 (& mut self) -> DOUTCLR31_0_DIO3_W < DOUTCLR31_0_SPEC , 3 > { DOUTCLR31_0_DIO3_W :: new (self) } # [doc = "Bit 4 - Writing 1 to this bit clears the DIO4 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio4 (& mut self) -> DOUTCLR31_0_DIO4_W < DOUTCLR31_0_SPEC , 4 > { DOUTCLR31_0_DIO4_W :: new (self) } # [doc = "Bit 5 - Writing 1 to this bit clears the DIO5 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio5 (& mut self) -> DOUTCLR31_0_DIO5_W < DOUTCLR31_0_SPEC , 5 > { DOUTCLR31_0_DIO5_W :: new (self) } # [doc = "Bit 6 - Writing 1 to this bit clears the DIO6 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio6 (& mut self) -> DOUTCLR31_0_DIO6_W < DOUTCLR31_0_SPEC , 6 > { DOUTCLR31_0_DIO6_W :: new (self) } # [doc = "Bit 7 - Writing 1 to this bit clears the DIO7 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio7 (& mut self) -> DOUTCLR31_0_DIO7_W < DOUTCLR31_0_SPEC , 7 > { DOUTCLR31_0_DIO7_W :: new (self) } # [doc = "Bit 8 - Writing 1 to this bit clears the DIO8 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio8 (& mut self) -> DOUTCLR31_0_DIO8_W < DOUTCLR31_0_SPEC , 8 > { DOUTCLR31_0_DIO8_W :: new (self) } # [doc = "Bit 9 - Writing 1 to this bit clears the DIO9 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio9 (& mut self) -> DOUTCLR31_0_DIO9_W < DOUTCLR31_0_SPEC , 9 > { DOUTCLR31_0_DIO9_W :: new (self) } # [doc = "Bit 10 - Writing 1 to this bit clears the DIO10 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio10 (& mut self) -> DOUTCLR31_0_DIO10_W < DOUTCLR31_0_SPEC , 10 > { DOUTCLR31_0_DIO10_W :: new (self) } # [doc = "Bit 11 - Writing 1 to this bit clears the DIO11 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio11 (& mut self) -> DOUTCLR31_0_DIO11_W < DOUTCLR31_0_SPEC , 11 > { DOUTCLR31_0_DIO11_W :: new (self) } # [doc = "Bit 12 - Writing 1 to this bit clears the DIO12 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio12 (& mut self) -> DOUTCLR31_0_DIO12_W < DOUTCLR31_0_SPEC , 12 > { DOUTCLR31_0_DIO12_W :: new (self) } # [doc = "Bit 13 - Writing 1 to this bit clears the DIO13 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio13 (& mut self) -> DOUTCLR31_0_DIO13_W < DOUTCLR31_0_SPEC , 13 > { DOUTCLR31_0_DIO13_W :: new (self) } # [doc = "Bit 14 - Writing 1 to this bit clears the DIO14 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio14 (& mut self) -> DOUTCLR31_0_DIO14_W < DOUTCLR31_0_SPEC , 14 > { DOUTCLR31_0_DIO14_W :: new (self) } # [doc = "Bit 15 - Writing 1 to this bit clears the DIO15 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio15 (& mut self) -> DOUTCLR31_0_DIO15_W < DOUTCLR31_0_SPEC , 15 > { DOUTCLR31_0_DIO15_W :: new (self) } # [doc = "Bit 16 - Writing 1 to this bit clears the DIO16 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio16 (& mut self) -> DOUTCLR31_0_DIO16_W < DOUTCLR31_0_SPEC , 16 > { DOUTCLR31_0_DIO16_W :: new (self) } # [doc = "Bit 17 - Writing 1 to this bit clears the DIO17 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio17 (& mut self) -> DOUTCLR31_0_DIO17_W < DOUTCLR31_0_SPEC , 17 > { DOUTCLR31_0_DIO17_W :: new (self) } # [doc = "Bit 18 - Writing 1 to this bit clears the DIO18 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio18 (& mut self) -> DOUTCLR31_0_DIO18_W < DOUTCLR31_0_SPEC , 18 > { DOUTCLR31_0_DIO18_W :: new (self) } # [doc = "Bit 19 - Writing 1 to this bit clears the DIO19 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio19 (& mut self) -> DOUTCLR31_0_DIO19_W < DOUTCLR31_0_SPEC , 19 > { DOUTCLR31_0_DIO19_W :: new (self) } # [doc = "Bit 20 - Writing 1 to this bit clears the DIO20 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio20 (& mut self) -> DOUTCLR31_0_DIO20_W < DOUTCLR31_0_SPEC , 20 > { DOUTCLR31_0_DIO20_W :: new (self) } # [doc = "Bit 21 - Writing 1 to this bit clears the DIO21 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio21 (& mut self) -> DOUTCLR31_0_DIO21_W < DOUTCLR31_0_SPEC , 21 > { DOUTCLR31_0_DIO21_W :: new (self) } # [doc = "Bit 22 - Writing 1 to this bit clears the DIO22 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio22 (& mut self) -> DOUTCLR31_0_DIO22_W < DOUTCLR31_0_SPEC , 22 > { DOUTCLR31_0_DIO22_W :: new (self) } # [doc = "Bit 23 - Writing 1 to this bit clears the DIO23 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio23 (& mut self) -> DOUTCLR31_0_DIO23_W < DOUTCLR31_0_SPEC , 23 > { DOUTCLR31_0_DIO23_W :: new (self) } # [doc = "Bit 24 - Writing 1 to this bit clears the DIO24 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio24 (& mut self) -> DOUTCLR31_0_DIO24_W < DOUTCLR31_0_SPEC , 24 > { DOUTCLR31_0_DIO24_W :: new (self) } # [doc = "Bit 25 - Writing 1 to this bit clears the DIO25 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio25 (& mut self) -> DOUTCLR31_0_DIO25_W < DOUTCLR31_0_SPEC , 25 > { DOUTCLR31_0_DIO25_W :: new (self) } # [doc = "Bit 26 - Writing 1 to this bit clears the DIO26 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio26 (& mut self) -> DOUTCLR31_0_DIO26_W < DOUTCLR31_0_SPEC , 26 > { DOUTCLR31_0_DIO26_W :: new (self) } # [doc = "Bit 27 - Writing 1 to this bit clears the DIO27 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio27 (& mut self) -> DOUTCLR31_0_DIO27_W < DOUTCLR31_0_SPEC , 27 > { DOUTCLR31_0_DIO27_W :: new (self) } # [doc = "Bit 28 - Writing 1 to this bit clears the DIO28 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio28 (& mut self) -> DOUTCLR31_0_DIO28_W < DOUTCLR31_0_SPEC , 28 > { DOUTCLR31_0_DIO28_W :: new (self) } # [doc = "Bit 29 - Writing 1 to this bit clears the DIO29 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio29 (& mut self) -> DOUTCLR31_0_DIO29_W < DOUTCLR31_0_SPEC , 29 > { DOUTCLR31_0_DIO29_W :: new (self) } # [doc = "Bit 30 - Writing 1 to this bit clears the DIO30 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio30 (& mut self) -> DOUTCLR31_0_DIO30_W < DOUTCLR31_0_SPEC , 30 > { DOUTCLR31_0_DIO30_W :: new (self) } # [doc = "Bit 31 - Writing 1 to this bit clears the DIO31 bit in the DOUT31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doutclr31_0_dio31 (& mut self) -> DOUTCLR31_0_DIO31_W < DOUTCLR31_0_SPEC , 31 > { DOUTCLR31_0_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output clear 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doutclr31_0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUTCLR31_0_SPEC ; impl crate :: RegisterSpec for DOUTCLR31_0_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`doutclr31_0::W`](W) writer structure"]
impl crate :: Writable for DOUTCLR31_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUTCLR31_0 to value 0"]
impl crate :: Resettable for DOUTCLR31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOUTTGL31_0 (w) register accessor: Data output toggle 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`douttgl31_0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@douttgl31_0`]
module"]
pub type DOUTTGL31_0 = crate :: Reg < douttgl31_0 :: DOUTTGL31_0_SPEC > ; # [doc = "Data output toggle 31 to 0"]
pub mod douttgl31_0 { # [doc = "Register `DOUTTGL31_0` writer"]
pub type W = crate :: W < DOUTTGL31_0_SPEC > ; # [doc = "This bit is used to toggle DIO0 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO0_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO0_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO0_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO0_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO0` writer - This bit is used to toggle DIO0 output."]
pub type DOUTTGL31_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO0_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO0_AW :: DOUTTGL31_0_DIO0_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio0_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO0_AW :: DOUTTGL31_0_DIO0_TOGGLE) } } # [doc = "This bit is used to toggle DIO1 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO1_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO1_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO1_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO1_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO1` writer - This bit is used to toggle DIO1 output."]
pub type DOUTTGL31_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO1_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO1_AW :: DOUTTGL31_0_DIO1_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio1_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO1_AW :: DOUTTGL31_0_DIO1_TOGGLE) } } # [doc = "This bit is used to toggle DIO2 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO2_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO2_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO2_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO2_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO2` writer - This bit is used to toggle DIO2 output."]
pub type DOUTTGL31_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO2_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO2_AW :: DOUTTGL31_0_DIO2_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio2_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO2_AW :: DOUTTGL31_0_DIO2_TOGGLE) } } # [doc = "This bit is used to toggle DIO3 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO3_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO3_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO3_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO3_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO3` writer - This bit is used to toggle DIO3 output."]
pub type DOUTTGL31_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO3_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO3_AW :: DOUTTGL31_0_DIO3_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio3_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO3_AW :: DOUTTGL31_0_DIO3_TOGGLE) } } # [doc = "This bit is used to toggle DIO4 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO4_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO4_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO4_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO4_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO4` writer - This bit is used to toggle DIO4 output."]
pub type DOUTTGL31_0_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO4_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO4_AW :: DOUTTGL31_0_DIO4_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio4_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO4_AW :: DOUTTGL31_0_DIO4_TOGGLE) } } # [doc = "This bit is used to toggle DIO5 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO5_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO5_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO5_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO5_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO5` writer - This bit is used to toggle DIO5 output."]
pub type DOUTTGL31_0_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO5_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO5_AW :: DOUTTGL31_0_DIO5_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio5_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO5_AW :: DOUTTGL31_0_DIO5_TOGGLE) } } # [doc = "This bit is used to toggle DIO6 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO6_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO6_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO6_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO6_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO6` writer - This bit is used to toggle DIO6 output."]
pub type DOUTTGL31_0_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO6_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO6_AW :: DOUTTGL31_0_DIO6_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio6_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO6_AW :: DOUTTGL31_0_DIO6_TOGGLE) } } # [doc = "This bit is used to toggle DIO7 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO7_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO7_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO7_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO7_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO7` writer - This bit is used to toggle DIO7 output."]
pub type DOUTTGL31_0_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO7_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO7_AW :: DOUTTGL31_0_DIO7_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio7_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO7_AW :: DOUTTGL31_0_DIO7_TOGGLE) } } # [doc = "This bit is used to toggle DIO8 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO8_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO8_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO8_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO8_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO8` writer - This bit is used to toggle DIO8 output."]
pub type DOUTTGL31_0_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO8_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO8_AW :: DOUTTGL31_0_DIO8_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio8_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO8_AW :: DOUTTGL31_0_DIO8_TOGGLE) } } # [doc = "This bit is used to toggle DIO9 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO9_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO9_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO9_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO9_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO9` writer - This bit is used to toggle DIO9 output."]
pub type DOUTTGL31_0_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO9_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO9_AW :: DOUTTGL31_0_DIO9_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio9_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO9_AW :: DOUTTGL31_0_DIO9_TOGGLE) } } # [doc = "This bit is used to toggle DIO10 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO10_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO10_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO10_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO10_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO10` writer - This bit is used to toggle DIO10 output."]
pub type DOUTTGL31_0_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO10_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO10_AW :: DOUTTGL31_0_DIO10_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio10_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO10_AW :: DOUTTGL31_0_DIO10_TOGGLE) } } # [doc = "This bit is used to toggle DIO11 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO11_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO11_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO11_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO11_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO11` writer - This bit is used to toggle DIO11 output."]
pub type DOUTTGL31_0_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO11_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO11_AW :: DOUTTGL31_0_DIO11_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio11_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO11_AW :: DOUTTGL31_0_DIO11_TOGGLE) } } # [doc = "This bit is used to toggle DIO12 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO12_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO12_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO12_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO12_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO12` writer - This bit is used to toggle DIO12 output."]
pub type DOUTTGL31_0_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO12_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO12_AW :: DOUTTGL31_0_DIO12_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio12_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO12_AW :: DOUTTGL31_0_DIO12_TOGGLE) } } # [doc = "This bit is used to toggle DIO13 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO13_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO13_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO13_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO13_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO13` writer - This bit is used to toggle DIO13 output."]
pub type DOUTTGL31_0_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO13_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO13_AW :: DOUTTGL31_0_DIO13_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio13_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO13_AW :: DOUTTGL31_0_DIO13_TOGGLE) } } # [doc = "This bit is used to toggle DIO14 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO14_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO14_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO14_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO14_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO14` writer - This bit is used to toggle DIO14 output."]
pub type DOUTTGL31_0_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO14_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO14_AW :: DOUTTGL31_0_DIO14_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio14_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO14_AW :: DOUTTGL31_0_DIO14_TOGGLE) } } # [doc = "This bit is used to toggle DIO15 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO15_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO15_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO15_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO15_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO15` writer - This bit is used to toggle DIO15 output."]
pub type DOUTTGL31_0_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO15_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO15_AW :: DOUTTGL31_0_DIO15_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio15_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO15_AW :: DOUTTGL31_0_DIO15_TOGGLE) } } # [doc = "This bit is used to toggle DIO16 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO16_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO16_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO16_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO16_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO16` writer - This bit is used to toggle DIO16 output."]
pub type DOUTTGL31_0_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO16_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO16_AW :: DOUTTGL31_0_DIO16_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio16_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO16_AW :: DOUTTGL31_0_DIO16_TOGGLE) } } # [doc = "This bit is used to toggle DIO17 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO17_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO17_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO17_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO17_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO17` writer - This bit is used to toggle DIO17 output."]
pub type DOUTTGL31_0_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO17_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO17_AW :: DOUTTGL31_0_DIO17_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio17_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO17_AW :: DOUTTGL31_0_DIO17_TOGGLE) } } # [doc = "This bit is used to toggle DIO18 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO18_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO18_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO18_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO18_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO18` writer - This bit is used to toggle DIO18 output."]
pub type DOUTTGL31_0_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO18_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO18_AW :: DOUTTGL31_0_DIO18_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio18_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO18_AW :: DOUTTGL31_0_DIO18_TOGGLE) } } # [doc = "This bit is used to toggle DIO19 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO19_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO19_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO19_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO19_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO19` writer - This bit is used to toggle DIO19 output."]
pub type DOUTTGL31_0_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO19_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO19_AW :: DOUTTGL31_0_DIO19_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio19_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO19_AW :: DOUTTGL31_0_DIO19_TOGGLE) } } # [doc = "This bit is used to toggle DIO20 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO20_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO20_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO20_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO20_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO20` writer - This bit is used to toggle DIO20 output."]
pub type DOUTTGL31_0_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO20_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO20_AW :: DOUTTGL31_0_DIO20_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio20_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO20_AW :: DOUTTGL31_0_DIO20_TOGGLE) } } # [doc = "This bit is used to toggle DIO21 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO21_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO21_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO21_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO21_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO21` writer - This bit is used to toggle DIO21 output."]
pub type DOUTTGL31_0_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO21_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO21_AW :: DOUTTGL31_0_DIO21_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio21_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO21_AW :: DOUTTGL31_0_DIO21_TOGGLE) } } # [doc = "This bit is used to toggle DIO22 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO22_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO22_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO22_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO22_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO22` writer - This bit is used to toggle DIO22 output."]
pub type DOUTTGL31_0_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO22_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO22_AW :: DOUTTGL31_0_DIO22_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio22_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO22_AW :: DOUTTGL31_0_DIO22_TOGGLE) } } # [doc = "This bit is used to toggle DIO23 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO23_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO23_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO23_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO23_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO23` writer - This bit is used to toggle DIO23 output."]
pub type DOUTTGL31_0_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO23_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO23_AW :: DOUTTGL31_0_DIO23_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio23_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO23_AW :: DOUTTGL31_0_DIO23_TOGGLE) } } # [doc = "This bit is used to toggle DIO24 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO24_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO24_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO24_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO24_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO24` writer - This bit is used to toggle DIO24 output."]
pub type DOUTTGL31_0_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO24_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO24_AW :: DOUTTGL31_0_DIO24_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio24_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO24_AW :: DOUTTGL31_0_DIO24_TOGGLE) } } # [doc = "This bit is used to toggle DIO25 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO25_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO25_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO25_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO25_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO25` writer - This bit is used to toggle DIO25 output."]
pub type DOUTTGL31_0_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO25_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO25_AW :: DOUTTGL31_0_DIO25_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio25_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO25_AW :: DOUTTGL31_0_DIO25_TOGGLE) } } # [doc = "This bit is used to toggle DIO26 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO26_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO26_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO26_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO26_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO26` writer - This bit is used to toggle DIO26 output."]
pub type DOUTTGL31_0_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO26_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO26_AW :: DOUTTGL31_0_DIO26_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio26_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO26_AW :: DOUTTGL31_0_DIO26_TOGGLE) } } # [doc = "This bit is used to toggle DIO27 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO27_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO27_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO27_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO27_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO27` writer - This bit is used to toggle DIO27 output."]
pub type DOUTTGL31_0_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO27_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO27_AW :: DOUTTGL31_0_DIO27_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio27_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO27_AW :: DOUTTGL31_0_DIO27_TOGGLE) } } # [doc = "This bit is used to toggle DIO28 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO28_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO28_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO28_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO28_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO28` writer - This bit is used to toggle DIO28 output."]
pub type DOUTTGL31_0_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO28_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO28_AW :: DOUTTGL31_0_DIO28_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio28_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO28_AW :: DOUTTGL31_0_DIO28_TOGGLE) } } # [doc = "This bit is used to toggle DIO29 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO29_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO29_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO29_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO29_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO29` writer - This bit is used to toggle DIO29 output."]
pub type DOUTTGL31_0_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO29_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO29_AW :: DOUTTGL31_0_DIO29_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio29_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO29_AW :: DOUTTGL31_0_DIO29_TOGGLE) } } # [doc = "This bit is used to toggle DIO30 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO30_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO30_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO30_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO30_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO30` writer - This bit is used to toggle DIO30 output."]
pub type DOUTTGL31_0_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO30_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO30_AW :: DOUTTGL31_0_DIO30_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio30_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO30_AW :: DOUTTGL31_0_DIO30_TOGGLE) } } # [doc = "This bit is used to toggle DIO31 output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOUTTGL31_0_DIO31_AW { # [doc = "0: NO_EFFECT"]
DOUTTGL31_0_DIO31_NO_EFFECT = 0 , # [doc = "1: TOGGLE"]
DOUTTGL31_0_DIO31_TOGGLE = 1 , } impl From < DOUTTGL31_0_DIO31_AW > for bool { # [inline (always)]
fn from (variant : DOUTTGL31_0_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOUTTGL31_0_DIO31` writer - This bit is used to toggle DIO31 output."]
pub type DOUTTGL31_0_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOUTTGL31_0_DIO31_AW > ; impl < 'a , REG , const O : u8 > DOUTTGL31_0_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn douttgl31_0_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO31_AW :: DOUTTGL31_0_DIO31_NO_EFFECT) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn douttgl31_0_dio31_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (DOUTTGL31_0_DIO31_AW :: DOUTTGL31_0_DIO31_TOGGLE) } } impl W { # [doc = "Bit 0 - This bit is used to toggle DIO0 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio0 (& mut self) -> DOUTTGL31_0_DIO0_W < DOUTTGL31_0_SPEC , 0 > { DOUTTGL31_0_DIO0_W :: new (self) } # [doc = "Bit 1 - This bit is used to toggle DIO1 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio1 (& mut self) -> DOUTTGL31_0_DIO1_W < DOUTTGL31_0_SPEC , 1 > { DOUTTGL31_0_DIO1_W :: new (self) } # [doc = "Bit 2 - This bit is used to toggle DIO2 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio2 (& mut self) -> DOUTTGL31_0_DIO2_W < DOUTTGL31_0_SPEC , 2 > { DOUTTGL31_0_DIO2_W :: new (self) } # [doc = "Bit 3 - This bit is used to toggle DIO3 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio3 (& mut self) -> DOUTTGL31_0_DIO3_W < DOUTTGL31_0_SPEC , 3 > { DOUTTGL31_0_DIO3_W :: new (self) } # [doc = "Bit 4 - This bit is used to toggle DIO4 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio4 (& mut self) -> DOUTTGL31_0_DIO4_W < DOUTTGL31_0_SPEC , 4 > { DOUTTGL31_0_DIO4_W :: new (self) } # [doc = "Bit 5 - This bit is used to toggle DIO5 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio5 (& mut self) -> DOUTTGL31_0_DIO5_W < DOUTTGL31_0_SPEC , 5 > { DOUTTGL31_0_DIO5_W :: new (self) } # [doc = "Bit 6 - This bit is used to toggle DIO6 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio6 (& mut self) -> DOUTTGL31_0_DIO6_W < DOUTTGL31_0_SPEC , 6 > { DOUTTGL31_0_DIO6_W :: new (self) } # [doc = "Bit 7 - This bit is used to toggle DIO7 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio7 (& mut self) -> DOUTTGL31_0_DIO7_W < DOUTTGL31_0_SPEC , 7 > { DOUTTGL31_0_DIO7_W :: new (self) } # [doc = "Bit 8 - This bit is used to toggle DIO8 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio8 (& mut self) -> DOUTTGL31_0_DIO8_W < DOUTTGL31_0_SPEC , 8 > { DOUTTGL31_0_DIO8_W :: new (self) } # [doc = "Bit 9 - This bit is used to toggle DIO9 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio9 (& mut self) -> DOUTTGL31_0_DIO9_W < DOUTTGL31_0_SPEC , 9 > { DOUTTGL31_0_DIO9_W :: new (self) } # [doc = "Bit 10 - This bit is used to toggle DIO10 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio10 (& mut self) -> DOUTTGL31_0_DIO10_W < DOUTTGL31_0_SPEC , 10 > { DOUTTGL31_0_DIO10_W :: new (self) } # [doc = "Bit 11 - This bit is used to toggle DIO11 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio11 (& mut self) -> DOUTTGL31_0_DIO11_W < DOUTTGL31_0_SPEC , 11 > { DOUTTGL31_0_DIO11_W :: new (self) } # [doc = "Bit 12 - This bit is used to toggle DIO12 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio12 (& mut self) -> DOUTTGL31_0_DIO12_W < DOUTTGL31_0_SPEC , 12 > { DOUTTGL31_0_DIO12_W :: new (self) } # [doc = "Bit 13 - This bit is used to toggle DIO13 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio13 (& mut self) -> DOUTTGL31_0_DIO13_W < DOUTTGL31_0_SPEC , 13 > { DOUTTGL31_0_DIO13_W :: new (self) } # [doc = "Bit 14 - This bit is used to toggle DIO14 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio14 (& mut self) -> DOUTTGL31_0_DIO14_W < DOUTTGL31_0_SPEC , 14 > { DOUTTGL31_0_DIO14_W :: new (self) } # [doc = "Bit 15 - This bit is used to toggle DIO15 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio15 (& mut self) -> DOUTTGL31_0_DIO15_W < DOUTTGL31_0_SPEC , 15 > { DOUTTGL31_0_DIO15_W :: new (self) } # [doc = "Bit 16 - This bit is used to toggle DIO16 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio16 (& mut self) -> DOUTTGL31_0_DIO16_W < DOUTTGL31_0_SPEC , 16 > { DOUTTGL31_0_DIO16_W :: new (self) } # [doc = "Bit 17 - This bit is used to toggle DIO17 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio17 (& mut self) -> DOUTTGL31_0_DIO17_W < DOUTTGL31_0_SPEC , 17 > { DOUTTGL31_0_DIO17_W :: new (self) } # [doc = "Bit 18 - This bit is used to toggle DIO18 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio18 (& mut self) -> DOUTTGL31_0_DIO18_W < DOUTTGL31_0_SPEC , 18 > { DOUTTGL31_0_DIO18_W :: new (self) } # [doc = "Bit 19 - This bit is used to toggle DIO19 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio19 (& mut self) -> DOUTTGL31_0_DIO19_W < DOUTTGL31_0_SPEC , 19 > { DOUTTGL31_0_DIO19_W :: new (self) } # [doc = "Bit 20 - This bit is used to toggle DIO20 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio20 (& mut self) -> DOUTTGL31_0_DIO20_W < DOUTTGL31_0_SPEC , 20 > { DOUTTGL31_0_DIO20_W :: new (self) } # [doc = "Bit 21 - This bit is used to toggle DIO21 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio21 (& mut self) -> DOUTTGL31_0_DIO21_W < DOUTTGL31_0_SPEC , 21 > { DOUTTGL31_0_DIO21_W :: new (self) } # [doc = "Bit 22 - This bit is used to toggle DIO22 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio22 (& mut self) -> DOUTTGL31_0_DIO22_W < DOUTTGL31_0_SPEC , 22 > { DOUTTGL31_0_DIO22_W :: new (self) } # [doc = "Bit 23 - This bit is used to toggle DIO23 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio23 (& mut self) -> DOUTTGL31_0_DIO23_W < DOUTTGL31_0_SPEC , 23 > { DOUTTGL31_0_DIO23_W :: new (self) } # [doc = "Bit 24 - This bit is used to toggle DIO24 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio24 (& mut self) -> DOUTTGL31_0_DIO24_W < DOUTTGL31_0_SPEC , 24 > { DOUTTGL31_0_DIO24_W :: new (self) } # [doc = "Bit 25 - This bit is used to toggle DIO25 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio25 (& mut self) -> DOUTTGL31_0_DIO25_W < DOUTTGL31_0_SPEC , 25 > { DOUTTGL31_0_DIO25_W :: new (self) } # [doc = "Bit 26 - This bit is used to toggle DIO26 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio26 (& mut self) -> DOUTTGL31_0_DIO26_W < DOUTTGL31_0_SPEC , 26 > { DOUTTGL31_0_DIO26_W :: new (self) } # [doc = "Bit 27 - This bit is used to toggle DIO27 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio27 (& mut self) -> DOUTTGL31_0_DIO27_W < DOUTTGL31_0_SPEC , 27 > { DOUTTGL31_0_DIO27_W :: new (self) } # [doc = "Bit 28 - This bit is used to toggle DIO28 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio28 (& mut self) -> DOUTTGL31_0_DIO28_W < DOUTTGL31_0_SPEC , 28 > { DOUTTGL31_0_DIO28_W :: new (self) } # [doc = "Bit 29 - This bit is used to toggle DIO29 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio29 (& mut self) -> DOUTTGL31_0_DIO29_W < DOUTTGL31_0_SPEC , 29 > { DOUTTGL31_0_DIO29_W :: new (self) } # [doc = "Bit 30 - This bit is used to toggle DIO30 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio30 (& mut self) -> DOUTTGL31_0_DIO30_W < DOUTTGL31_0_SPEC , 30 > { DOUTTGL31_0_DIO30_W :: new (self) } # [doc = "Bit 31 - This bit is used to toggle DIO31 output."]
# [inline (always)]
# [must_use]
pub fn douttgl31_0_dio31 (& mut self) -> DOUTTGL31_0_DIO31_W < DOUTTGL31_0_SPEC , 31 > { DOUTTGL31_0_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output toggle 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`douttgl31_0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOUTTGL31_0_SPEC ; impl crate :: RegisterSpec for DOUTTGL31_0_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`douttgl31_0::W`](W) writer structure"]
impl crate :: Writable for DOUTTGL31_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOUTTGL31_0 to value 0"]
impl crate :: Resettable for DOUTTGL31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOE31_0 (rw) register accessor: Data output enable 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doe31_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doe31_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doe31_0`]
module"]
pub type DOE31_0 = crate :: Reg < doe31_0 :: DOE31_0_SPEC > ; # [doc = "Data output enable 31 to 0"]
pub mod doe31_0 { # [doc = "Register `DOE31_0` reader"]
pub type R = crate :: R < DOE31_0_SPEC > ; # [doc = "Register `DOE31_0` writer"]
pub type W = crate :: W < DOE31_0_SPEC > ; # [doc = "Field `DOE31_0_DIO0` reader - Enables data output for DIO0."]
pub type DOE31_0_DIO0_R = crate :: BitReader < DOE31_0_DIO0_A > ; # [doc = "Enables data output for DIO0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO0_A { # [doc = "0: DISABLE"]
DOE31_0_DIO0_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO0_ENABLE = 1 , } impl From < DOE31_0_DIO0_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO0_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO0_A { match self . bits { false => DOE31_0_DIO0_A :: DOE31_0_DIO0_DISABLE , true => DOE31_0_DIO0_A :: DOE31_0_DIO0_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio0_disable (& self) -> bool { * self == DOE31_0_DIO0_A :: DOE31_0_DIO0_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio0_enable (& self) -> bool { * self == DOE31_0_DIO0_A :: DOE31_0_DIO0_ENABLE } } # [doc = "Field `DOE31_0_DIO0` writer - Enables data output for DIO0."]
pub type DOE31_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO0_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio0_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO0_A :: DOE31_0_DIO0_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio0_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO0_A :: DOE31_0_DIO0_ENABLE) } } # [doc = "Field `DOE31_0_DIO1` reader - Enables data output for DIO1."]
pub type DOE31_0_DIO1_R = crate :: BitReader < DOE31_0_DIO1_A > ; # [doc = "Enables data output for DIO1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO1_A { # [doc = "0: DISABLE"]
DOE31_0_DIO1_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO1_ENABLE = 1 , } impl From < DOE31_0_DIO1_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO1_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO1_A { match self . bits { false => DOE31_0_DIO1_A :: DOE31_0_DIO1_DISABLE , true => DOE31_0_DIO1_A :: DOE31_0_DIO1_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio1_disable (& self) -> bool { * self == DOE31_0_DIO1_A :: DOE31_0_DIO1_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio1_enable (& self) -> bool { * self == DOE31_0_DIO1_A :: DOE31_0_DIO1_ENABLE } } # [doc = "Field `DOE31_0_DIO1` writer - Enables data output for DIO1."]
pub type DOE31_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO1_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio1_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO1_A :: DOE31_0_DIO1_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio1_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO1_A :: DOE31_0_DIO1_ENABLE) } } # [doc = "Field `DOE31_0_DIO2` reader - Enables data output for DIO2."]
pub type DOE31_0_DIO2_R = crate :: BitReader < DOE31_0_DIO2_A > ; # [doc = "Enables data output for DIO2.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO2_A { # [doc = "0: DISABLE"]
DOE31_0_DIO2_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO2_ENABLE = 1 , } impl From < DOE31_0_DIO2_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO2_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO2_A { match self . bits { false => DOE31_0_DIO2_A :: DOE31_0_DIO2_DISABLE , true => DOE31_0_DIO2_A :: DOE31_0_DIO2_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio2_disable (& self) -> bool { * self == DOE31_0_DIO2_A :: DOE31_0_DIO2_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio2_enable (& self) -> bool { * self == DOE31_0_DIO2_A :: DOE31_0_DIO2_ENABLE } } # [doc = "Field `DOE31_0_DIO2` writer - Enables data output for DIO2."]
pub type DOE31_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO2_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio2_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO2_A :: DOE31_0_DIO2_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio2_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO2_A :: DOE31_0_DIO2_ENABLE) } } # [doc = "Field `DOE31_0_DIO3` reader - Enables data output for DIO3."]
pub type DOE31_0_DIO3_R = crate :: BitReader < DOE31_0_DIO3_A > ; # [doc = "Enables data output for DIO3.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO3_A { # [doc = "0: DISABLE"]
DOE31_0_DIO3_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO3_ENABLE = 1 , } impl From < DOE31_0_DIO3_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO3_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO3_A { match self . bits { false => DOE31_0_DIO3_A :: DOE31_0_DIO3_DISABLE , true => DOE31_0_DIO3_A :: DOE31_0_DIO3_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio3_disable (& self) -> bool { * self == DOE31_0_DIO3_A :: DOE31_0_DIO3_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio3_enable (& self) -> bool { * self == DOE31_0_DIO3_A :: DOE31_0_DIO3_ENABLE } } # [doc = "Field `DOE31_0_DIO3` writer - Enables data output for DIO3."]
pub type DOE31_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO3_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio3_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO3_A :: DOE31_0_DIO3_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio3_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO3_A :: DOE31_0_DIO3_ENABLE) } } # [doc = "Field `DOE31_0_DIO4` reader - Enables data output for DIO4."]
pub type DOE31_0_DIO4_R = crate :: BitReader < DOE31_0_DIO4_A > ; # [doc = "Enables data output for DIO4.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO4_A { # [doc = "0: DISABLE"]
DOE31_0_DIO4_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO4_ENABLE = 1 , } impl From < DOE31_0_DIO4_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO4_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO4_A { match self . bits { false => DOE31_0_DIO4_A :: DOE31_0_DIO4_DISABLE , true => DOE31_0_DIO4_A :: DOE31_0_DIO4_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio4_disable (& self) -> bool { * self == DOE31_0_DIO4_A :: DOE31_0_DIO4_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio4_enable (& self) -> bool { * self == DOE31_0_DIO4_A :: DOE31_0_DIO4_ENABLE } } # [doc = "Field `DOE31_0_DIO4` writer - Enables data output for DIO4."]
pub type DOE31_0_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO4_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio4_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO4_A :: DOE31_0_DIO4_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio4_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO4_A :: DOE31_0_DIO4_ENABLE) } } # [doc = "Field `DOE31_0_DIO5` reader - Enables data output for DIO5."]
pub type DOE31_0_DIO5_R = crate :: BitReader < DOE31_0_DIO5_A > ; # [doc = "Enables data output for DIO5.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO5_A { # [doc = "0: DISABLE"]
DOE31_0_DIO5_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO5_ENABLE = 1 , } impl From < DOE31_0_DIO5_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO5_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO5_A { match self . bits { false => DOE31_0_DIO5_A :: DOE31_0_DIO5_DISABLE , true => DOE31_0_DIO5_A :: DOE31_0_DIO5_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio5_disable (& self) -> bool { * self == DOE31_0_DIO5_A :: DOE31_0_DIO5_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio5_enable (& self) -> bool { * self == DOE31_0_DIO5_A :: DOE31_0_DIO5_ENABLE } } # [doc = "Field `DOE31_0_DIO5` writer - Enables data output for DIO5."]
pub type DOE31_0_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO5_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio5_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO5_A :: DOE31_0_DIO5_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio5_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO5_A :: DOE31_0_DIO5_ENABLE) } } # [doc = "Field `DOE31_0_DIO6` reader - Enables data output for DIO6."]
pub type DOE31_0_DIO6_R = crate :: BitReader < DOE31_0_DIO6_A > ; # [doc = "Enables data output for DIO6.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO6_A { # [doc = "0: DISABLE"]
DOE31_0_DIO6_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO6_ENABLE = 1 , } impl From < DOE31_0_DIO6_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO6_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO6_A { match self . bits { false => DOE31_0_DIO6_A :: DOE31_0_DIO6_DISABLE , true => DOE31_0_DIO6_A :: DOE31_0_DIO6_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio6_disable (& self) -> bool { * self == DOE31_0_DIO6_A :: DOE31_0_DIO6_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio6_enable (& self) -> bool { * self == DOE31_0_DIO6_A :: DOE31_0_DIO6_ENABLE } } # [doc = "Field `DOE31_0_DIO6` writer - Enables data output for DIO6."]
pub type DOE31_0_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO6_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio6_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO6_A :: DOE31_0_DIO6_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio6_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO6_A :: DOE31_0_DIO6_ENABLE) } } # [doc = "Field `DOE31_0_DIO7` reader - Enables data output for DIO7."]
pub type DOE31_0_DIO7_R = crate :: BitReader < DOE31_0_DIO7_A > ; # [doc = "Enables data output for DIO7.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO7_A { # [doc = "0: DISABLE"]
DOE31_0_DIO7_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO7_ENABLE = 1 , } impl From < DOE31_0_DIO7_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO7_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO7_A { match self . bits { false => DOE31_0_DIO7_A :: DOE31_0_DIO7_DISABLE , true => DOE31_0_DIO7_A :: DOE31_0_DIO7_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio7_disable (& self) -> bool { * self == DOE31_0_DIO7_A :: DOE31_0_DIO7_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio7_enable (& self) -> bool { * self == DOE31_0_DIO7_A :: DOE31_0_DIO7_ENABLE } } # [doc = "Field `DOE31_0_DIO7` writer - Enables data output for DIO7."]
pub type DOE31_0_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO7_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio7_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO7_A :: DOE31_0_DIO7_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio7_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO7_A :: DOE31_0_DIO7_ENABLE) } } # [doc = "Field `DOE31_0_DIO8` reader - Enables data output for DIO8."]
pub type DOE31_0_DIO8_R = crate :: BitReader < DOE31_0_DIO8_A > ; # [doc = "Enables data output for DIO8.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO8_A { # [doc = "0: DISABLE"]
DOE31_0_DIO8_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO8_ENABLE = 1 , } impl From < DOE31_0_DIO8_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO8_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO8_A { match self . bits { false => DOE31_0_DIO8_A :: DOE31_0_DIO8_DISABLE , true => DOE31_0_DIO8_A :: DOE31_0_DIO8_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio8_disable (& self) -> bool { * self == DOE31_0_DIO8_A :: DOE31_0_DIO8_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio8_enable (& self) -> bool { * self == DOE31_0_DIO8_A :: DOE31_0_DIO8_ENABLE } } # [doc = "Field `DOE31_0_DIO8` writer - Enables data output for DIO8."]
pub type DOE31_0_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO8_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio8_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO8_A :: DOE31_0_DIO8_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio8_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO8_A :: DOE31_0_DIO8_ENABLE) } } # [doc = "Field `DOE31_0_DIO9` reader - Enables data output for DIO9."]
pub type DOE31_0_DIO9_R = crate :: BitReader < DOE31_0_DIO9_A > ; # [doc = "Enables data output for DIO9.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO9_A { # [doc = "0: DISABLE"]
DOE31_0_DIO9_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO9_ENABLE = 1 , } impl From < DOE31_0_DIO9_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO9_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO9_A { match self . bits { false => DOE31_0_DIO9_A :: DOE31_0_DIO9_DISABLE , true => DOE31_0_DIO9_A :: DOE31_0_DIO9_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio9_disable (& self) -> bool { * self == DOE31_0_DIO9_A :: DOE31_0_DIO9_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio9_enable (& self) -> bool { * self == DOE31_0_DIO9_A :: DOE31_0_DIO9_ENABLE } } # [doc = "Field `DOE31_0_DIO9` writer - Enables data output for DIO9."]
pub type DOE31_0_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO9_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio9_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO9_A :: DOE31_0_DIO9_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio9_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO9_A :: DOE31_0_DIO9_ENABLE) } } # [doc = "Field `DOE31_0_DIO10` reader - Enables data output for DIO10."]
pub type DOE31_0_DIO10_R = crate :: BitReader < DOE31_0_DIO10_A > ; # [doc = "Enables data output for DIO10.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO10_A { # [doc = "0: DISABLE"]
DOE31_0_DIO10_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO10_ENABLE = 1 , } impl From < DOE31_0_DIO10_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO10_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO10_A { match self . bits { false => DOE31_0_DIO10_A :: DOE31_0_DIO10_DISABLE , true => DOE31_0_DIO10_A :: DOE31_0_DIO10_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio10_disable (& self) -> bool { * self == DOE31_0_DIO10_A :: DOE31_0_DIO10_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio10_enable (& self) -> bool { * self == DOE31_0_DIO10_A :: DOE31_0_DIO10_ENABLE } } # [doc = "Field `DOE31_0_DIO10` writer - Enables data output for DIO10."]
pub type DOE31_0_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO10_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio10_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO10_A :: DOE31_0_DIO10_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio10_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO10_A :: DOE31_0_DIO10_ENABLE) } } # [doc = "Field `DOE31_0_DIO11` reader - Enables data output for DIO11."]
pub type DOE31_0_DIO11_R = crate :: BitReader < DOE31_0_DIO11_A > ; # [doc = "Enables data output for DIO11.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO11_A { # [doc = "0: DISABLE"]
DOE31_0_DIO11_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO11_ENABLE = 1 , } impl From < DOE31_0_DIO11_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO11_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO11_A { match self . bits { false => DOE31_0_DIO11_A :: DOE31_0_DIO11_DISABLE , true => DOE31_0_DIO11_A :: DOE31_0_DIO11_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio11_disable (& self) -> bool { * self == DOE31_0_DIO11_A :: DOE31_0_DIO11_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio11_enable (& self) -> bool { * self == DOE31_0_DIO11_A :: DOE31_0_DIO11_ENABLE } } # [doc = "Field `DOE31_0_DIO11` writer - Enables data output for DIO11."]
pub type DOE31_0_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO11_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio11_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO11_A :: DOE31_0_DIO11_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio11_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO11_A :: DOE31_0_DIO11_ENABLE) } } # [doc = "Field `DOE31_0_DIO12` reader - Enables data output for DIO12."]
pub type DOE31_0_DIO12_R = crate :: BitReader < DOE31_0_DIO12_A > ; # [doc = "Enables data output for DIO12.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO12_A { # [doc = "0: DISABLE"]
DOE31_0_DIO12_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO12_ENABLE = 1 , } impl From < DOE31_0_DIO12_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO12_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO12_A { match self . bits { false => DOE31_0_DIO12_A :: DOE31_0_DIO12_DISABLE , true => DOE31_0_DIO12_A :: DOE31_0_DIO12_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio12_disable (& self) -> bool { * self == DOE31_0_DIO12_A :: DOE31_0_DIO12_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio12_enable (& self) -> bool { * self == DOE31_0_DIO12_A :: DOE31_0_DIO12_ENABLE } } # [doc = "Field `DOE31_0_DIO12` writer - Enables data output for DIO12."]
pub type DOE31_0_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO12_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio12_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO12_A :: DOE31_0_DIO12_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio12_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO12_A :: DOE31_0_DIO12_ENABLE) } } # [doc = "Field `DOE31_0_DIO13` reader - Enables data output for DIO13."]
pub type DOE31_0_DIO13_R = crate :: BitReader < DOE31_0_DIO13_A > ; # [doc = "Enables data output for DIO13.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO13_A { # [doc = "0: DISABLE"]
DOE31_0_DIO13_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO13_ENABLE = 1 , } impl From < DOE31_0_DIO13_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO13_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO13_A { match self . bits { false => DOE31_0_DIO13_A :: DOE31_0_DIO13_DISABLE , true => DOE31_0_DIO13_A :: DOE31_0_DIO13_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio13_disable (& self) -> bool { * self == DOE31_0_DIO13_A :: DOE31_0_DIO13_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio13_enable (& self) -> bool { * self == DOE31_0_DIO13_A :: DOE31_0_DIO13_ENABLE } } # [doc = "Field `DOE31_0_DIO13` writer - Enables data output for DIO13."]
pub type DOE31_0_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO13_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio13_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO13_A :: DOE31_0_DIO13_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio13_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO13_A :: DOE31_0_DIO13_ENABLE) } } # [doc = "Field `DOE31_0_DIO14` reader - Enables data output for DIO14."]
pub type DOE31_0_DIO14_R = crate :: BitReader < DOE31_0_DIO14_A > ; # [doc = "Enables data output for DIO14.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO14_A { # [doc = "0: DISABLE"]
DOE31_0_DIO14_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO14_ENABLE = 1 , } impl From < DOE31_0_DIO14_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO14_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO14_A { match self . bits { false => DOE31_0_DIO14_A :: DOE31_0_DIO14_DISABLE , true => DOE31_0_DIO14_A :: DOE31_0_DIO14_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio14_disable (& self) -> bool { * self == DOE31_0_DIO14_A :: DOE31_0_DIO14_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio14_enable (& self) -> bool { * self == DOE31_0_DIO14_A :: DOE31_0_DIO14_ENABLE } } # [doc = "Field `DOE31_0_DIO14` writer - Enables data output for DIO14."]
pub type DOE31_0_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO14_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio14_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO14_A :: DOE31_0_DIO14_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio14_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO14_A :: DOE31_0_DIO14_ENABLE) } } # [doc = "Field `DOE31_0_DIO15` reader - Enables data output for DIO15."]
pub type DOE31_0_DIO15_R = crate :: BitReader < DOE31_0_DIO15_A > ; # [doc = "Enables data output for DIO15.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO15_A { # [doc = "0: DISABLE"]
DOE31_0_DIO15_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO15_ENABLE = 1 , } impl From < DOE31_0_DIO15_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO15_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO15_A { match self . bits { false => DOE31_0_DIO15_A :: DOE31_0_DIO15_DISABLE , true => DOE31_0_DIO15_A :: DOE31_0_DIO15_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio15_disable (& self) -> bool { * self == DOE31_0_DIO15_A :: DOE31_0_DIO15_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio15_enable (& self) -> bool { * self == DOE31_0_DIO15_A :: DOE31_0_DIO15_ENABLE } } # [doc = "Field `DOE31_0_DIO15` writer - Enables data output for DIO15."]
pub type DOE31_0_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO15_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio15_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO15_A :: DOE31_0_DIO15_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio15_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO15_A :: DOE31_0_DIO15_ENABLE) } } # [doc = "Field `DOE31_0_DIO16` reader - Enables data output for DIO16."]
pub type DOE31_0_DIO16_R = crate :: BitReader < DOE31_0_DIO16_A > ; # [doc = "Enables data output for DIO16.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO16_A { # [doc = "0: DISABLE"]
DOE31_0_DIO16_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO16_ENABLE = 1 , } impl From < DOE31_0_DIO16_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO16_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO16_A { match self . bits { false => DOE31_0_DIO16_A :: DOE31_0_DIO16_DISABLE , true => DOE31_0_DIO16_A :: DOE31_0_DIO16_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio16_disable (& self) -> bool { * self == DOE31_0_DIO16_A :: DOE31_0_DIO16_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio16_enable (& self) -> bool { * self == DOE31_0_DIO16_A :: DOE31_0_DIO16_ENABLE } } # [doc = "Field `DOE31_0_DIO16` writer - Enables data output for DIO16."]
pub type DOE31_0_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO16_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio16_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO16_A :: DOE31_0_DIO16_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio16_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO16_A :: DOE31_0_DIO16_ENABLE) } } # [doc = "Field `DOE31_0_DIO17` reader - Enables data output for DIO17."]
pub type DOE31_0_DIO17_R = crate :: BitReader < DOE31_0_DIO17_A > ; # [doc = "Enables data output for DIO17.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO17_A { # [doc = "0: DISABLE"]
DOE31_0_DIO17_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO17_ENABLE = 1 , } impl From < DOE31_0_DIO17_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO17_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO17_A { match self . bits { false => DOE31_0_DIO17_A :: DOE31_0_DIO17_DISABLE , true => DOE31_0_DIO17_A :: DOE31_0_DIO17_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio17_disable (& self) -> bool { * self == DOE31_0_DIO17_A :: DOE31_0_DIO17_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio17_enable (& self) -> bool { * self == DOE31_0_DIO17_A :: DOE31_0_DIO17_ENABLE } } # [doc = "Field `DOE31_0_DIO17` writer - Enables data output for DIO17."]
pub type DOE31_0_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO17_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio17_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO17_A :: DOE31_0_DIO17_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio17_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO17_A :: DOE31_0_DIO17_ENABLE) } } # [doc = "Field `DOE31_0_DIO18` reader - Enables data output for DIO18."]
pub type DOE31_0_DIO18_R = crate :: BitReader < DOE31_0_DIO18_A > ; # [doc = "Enables data output for DIO18.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO18_A { # [doc = "0: DISABLE"]
DOE31_0_DIO18_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO18_ENABLE = 1 , } impl From < DOE31_0_DIO18_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO18_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO18_A { match self . bits { false => DOE31_0_DIO18_A :: DOE31_0_DIO18_DISABLE , true => DOE31_0_DIO18_A :: DOE31_0_DIO18_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio18_disable (& self) -> bool { * self == DOE31_0_DIO18_A :: DOE31_0_DIO18_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio18_enable (& self) -> bool { * self == DOE31_0_DIO18_A :: DOE31_0_DIO18_ENABLE } } # [doc = "Field `DOE31_0_DIO18` writer - Enables data output for DIO18."]
pub type DOE31_0_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO18_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio18_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO18_A :: DOE31_0_DIO18_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio18_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO18_A :: DOE31_0_DIO18_ENABLE) } } # [doc = "Field `DOE31_0_DIO19` reader - Enables data output for DIO19."]
pub type DOE31_0_DIO19_R = crate :: BitReader < DOE31_0_DIO19_A > ; # [doc = "Enables data output for DIO19.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO19_A { # [doc = "0: DISABLE"]
DOE31_0_DIO19_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO19_ENABLE = 1 , } impl From < DOE31_0_DIO19_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO19_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO19_A { match self . bits { false => DOE31_0_DIO19_A :: DOE31_0_DIO19_DISABLE , true => DOE31_0_DIO19_A :: DOE31_0_DIO19_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio19_disable (& self) -> bool { * self == DOE31_0_DIO19_A :: DOE31_0_DIO19_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio19_enable (& self) -> bool { * self == DOE31_0_DIO19_A :: DOE31_0_DIO19_ENABLE } } # [doc = "Field `DOE31_0_DIO19` writer - Enables data output for DIO19."]
pub type DOE31_0_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO19_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio19_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO19_A :: DOE31_0_DIO19_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio19_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO19_A :: DOE31_0_DIO19_ENABLE) } } # [doc = "Field `DOE31_0_DIO20` reader - Enables data output for DIO20."]
pub type DOE31_0_DIO20_R = crate :: BitReader < DOE31_0_DIO20_A > ; # [doc = "Enables data output for DIO20.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO20_A { # [doc = "0: DISABLE"]
DOE31_0_DIO20_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO20_ENABLE = 1 , } impl From < DOE31_0_DIO20_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO20_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO20_A { match self . bits { false => DOE31_0_DIO20_A :: DOE31_0_DIO20_DISABLE , true => DOE31_0_DIO20_A :: DOE31_0_DIO20_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio20_disable (& self) -> bool { * self == DOE31_0_DIO20_A :: DOE31_0_DIO20_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio20_enable (& self) -> bool { * self == DOE31_0_DIO20_A :: DOE31_0_DIO20_ENABLE } } # [doc = "Field `DOE31_0_DIO20` writer - Enables data output for DIO20."]
pub type DOE31_0_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO20_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio20_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO20_A :: DOE31_0_DIO20_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio20_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO20_A :: DOE31_0_DIO20_ENABLE) } } # [doc = "Field `DOE31_0_DIO21` reader - Enables data output for DIO21."]
pub type DOE31_0_DIO21_R = crate :: BitReader < DOE31_0_DIO21_A > ; # [doc = "Enables data output for DIO21.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO21_A { # [doc = "0: DISABLE"]
DOE31_0_DIO21_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO21_ENABLE = 1 , } impl From < DOE31_0_DIO21_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO21_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO21_A { match self . bits { false => DOE31_0_DIO21_A :: DOE31_0_DIO21_DISABLE , true => DOE31_0_DIO21_A :: DOE31_0_DIO21_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio21_disable (& self) -> bool { * self == DOE31_0_DIO21_A :: DOE31_0_DIO21_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio21_enable (& self) -> bool { * self == DOE31_0_DIO21_A :: DOE31_0_DIO21_ENABLE } } # [doc = "Field `DOE31_0_DIO21` writer - Enables data output for DIO21."]
pub type DOE31_0_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO21_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio21_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO21_A :: DOE31_0_DIO21_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio21_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO21_A :: DOE31_0_DIO21_ENABLE) } } # [doc = "Field `DOE31_0_DIO22` reader - Enables data output for DIO22."]
pub type DOE31_0_DIO22_R = crate :: BitReader < DOE31_0_DIO22_A > ; # [doc = "Enables data output for DIO22.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO22_A { # [doc = "0: DISABLE"]
DOE31_0_DIO22_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO22_ENABLE = 1 , } impl From < DOE31_0_DIO22_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO22_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO22_A { match self . bits { false => DOE31_0_DIO22_A :: DOE31_0_DIO22_DISABLE , true => DOE31_0_DIO22_A :: DOE31_0_DIO22_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio22_disable (& self) -> bool { * self == DOE31_0_DIO22_A :: DOE31_0_DIO22_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio22_enable (& self) -> bool { * self == DOE31_0_DIO22_A :: DOE31_0_DIO22_ENABLE } } # [doc = "Field `DOE31_0_DIO22` writer - Enables data output for DIO22."]
pub type DOE31_0_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO22_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio22_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO22_A :: DOE31_0_DIO22_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio22_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO22_A :: DOE31_0_DIO22_ENABLE) } } # [doc = "Field `DOE31_0_DIO23` reader - Enables data output for DIO23."]
pub type DOE31_0_DIO23_R = crate :: BitReader < DOE31_0_DIO23_A > ; # [doc = "Enables data output for DIO23.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO23_A { # [doc = "0: DISABLE"]
DOE31_0_DIO23_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO23_ENABLE = 1 , } impl From < DOE31_0_DIO23_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO23_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO23_A { match self . bits { false => DOE31_0_DIO23_A :: DOE31_0_DIO23_DISABLE , true => DOE31_0_DIO23_A :: DOE31_0_DIO23_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio23_disable (& self) -> bool { * self == DOE31_0_DIO23_A :: DOE31_0_DIO23_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio23_enable (& self) -> bool { * self == DOE31_0_DIO23_A :: DOE31_0_DIO23_ENABLE } } # [doc = "Field `DOE31_0_DIO23` writer - Enables data output for DIO23."]
pub type DOE31_0_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO23_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio23_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO23_A :: DOE31_0_DIO23_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio23_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO23_A :: DOE31_0_DIO23_ENABLE) } } # [doc = "Field `DOE31_0_DIO24` reader - Enables data output for DIO24."]
pub type DOE31_0_DIO24_R = crate :: BitReader < DOE31_0_DIO24_A > ; # [doc = "Enables data output for DIO24.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO24_A { # [doc = "0: DISABLE"]
DOE31_0_DIO24_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO24_ENABLE = 1 , } impl From < DOE31_0_DIO24_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO24_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO24_A { match self . bits { false => DOE31_0_DIO24_A :: DOE31_0_DIO24_DISABLE , true => DOE31_0_DIO24_A :: DOE31_0_DIO24_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio24_disable (& self) -> bool { * self == DOE31_0_DIO24_A :: DOE31_0_DIO24_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio24_enable (& self) -> bool { * self == DOE31_0_DIO24_A :: DOE31_0_DIO24_ENABLE } } # [doc = "Field `DOE31_0_DIO24` writer - Enables data output for DIO24."]
pub type DOE31_0_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO24_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio24_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO24_A :: DOE31_0_DIO24_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio24_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO24_A :: DOE31_0_DIO24_ENABLE) } } # [doc = "Field `DOE31_0_DIO25` reader - Enables data output for DIO25."]
pub type DOE31_0_DIO25_R = crate :: BitReader < DOE31_0_DIO25_A > ; # [doc = "Enables data output for DIO25.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO25_A { # [doc = "0: DISABLE"]
DOE31_0_DIO25_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO25_ENABLE = 1 , } impl From < DOE31_0_DIO25_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO25_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO25_A { match self . bits { false => DOE31_0_DIO25_A :: DOE31_0_DIO25_DISABLE , true => DOE31_0_DIO25_A :: DOE31_0_DIO25_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio25_disable (& self) -> bool { * self == DOE31_0_DIO25_A :: DOE31_0_DIO25_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio25_enable (& self) -> bool { * self == DOE31_0_DIO25_A :: DOE31_0_DIO25_ENABLE } } # [doc = "Field `DOE31_0_DIO25` writer - Enables data output for DIO25."]
pub type DOE31_0_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO25_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio25_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO25_A :: DOE31_0_DIO25_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio25_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO25_A :: DOE31_0_DIO25_ENABLE) } } # [doc = "Field `DOE31_0_DIO26` reader - Enables data output for DIO26."]
pub type DOE31_0_DIO26_R = crate :: BitReader < DOE31_0_DIO26_A > ; # [doc = "Enables data output for DIO26.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO26_A { # [doc = "0: DISABLE"]
DOE31_0_DIO26_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO26_ENABLE = 1 , } impl From < DOE31_0_DIO26_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO26_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO26_A { match self . bits { false => DOE31_0_DIO26_A :: DOE31_0_DIO26_DISABLE , true => DOE31_0_DIO26_A :: DOE31_0_DIO26_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio26_disable (& self) -> bool { * self == DOE31_0_DIO26_A :: DOE31_0_DIO26_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio26_enable (& self) -> bool { * self == DOE31_0_DIO26_A :: DOE31_0_DIO26_ENABLE } } # [doc = "Field `DOE31_0_DIO26` writer - Enables data output for DIO26."]
pub type DOE31_0_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO26_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio26_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO26_A :: DOE31_0_DIO26_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio26_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO26_A :: DOE31_0_DIO26_ENABLE) } } # [doc = "Field `DOE31_0_DIO27` reader - Enables data output for DIO27."]
pub type DOE31_0_DIO27_R = crate :: BitReader < DOE31_0_DIO27_A > ; # [doc = "Enables data output for DIO27.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO27_A { # [doc = "0: DISABLE"]
DOE31_0_DIO27_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO27_ENABLE = 1 , } impl From < DOE31_0_DIO27_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO27_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO27_A { match self . bits { false => DOE31_0_DIO27_A :: DOE31_0_DIO27_DISABLE , true => DOE31_0_DIO27_A :: DOE31_0_DIO27_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio27_disable (& self) -> bool { * self == DOE31_0_DIO27_A :: DOE31_0_DIO27_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio27_enable (& self) -> bool { * self == DOE31_0_DIO27_A :: DOE31_0_DIO27_ENABLE } } # [doc = "Field `DOE31_0_DIO27` writer - Enables data output for DIO27."]
pub type DOE31_0_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO27_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio27_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO27_A :: DOE31_0_DIO27_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio27_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO27_A :: DOE31_0_DIO27_ENABLE) } } # [doc = "Field `DOE31_0_DIO28` reader - Enables data output for DIO28."]
pub type DOE31_0_DIO28_R = crate :: BitReader < DOE31_0_DIO28_A > ; # [doc = "Enables data output for DIO28.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO28_A { # [doc = "0: DISABLE"]
DOE31_0_DIO28_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO28_ENABLE = 1 , } impl From < DOE31_0_DIO28_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO28_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO28_A { match self . bits { false => DOE31_0_DIO28_A :: DOE31_0_DIO28_DISABLE , true => DOE31_0_DIO28_A :: DOE31_0_DIO28_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio28_disable (& self) -> bool { * self == DOE31_0_DIO28_A :: DOE31_0_DIO28_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio28_enable (& self) -> bool { * self == DOE31_0_DIO28_A :: DOE31_0_DIO28_ENABLE } } # [doc = "Field `DOE31_0_DIO28` writer - Enables data output for DIO28."]
pub type DOE31_0_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO28_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio28_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO28_A :: DOE31_0_DIO28_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio28_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO28_A :: DOE31_0_DIO28_ENABLE) } } # [doc = "Field `DOE31_0_DIO29` reader - Enables data output for DIO29."]
pub type DOE31_0_DIO29_R = crate :: BitReader < DOE31_0_DIO29_A > ; # [doc = "Enables data output for DIO29.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO29_A { # [doc = "0: DISABLE"]
DOE31_0_DIO29_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO29_ENABLE = 1 , } impl From < DOE31_0_DIO29_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO29_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO29_A { match self . bits { false => DOE31_0_DIO29_A :: DOE31_0_DIO29_DISABLE , true => DOE31_0_DIO29_A :: DOE31_0_DIO29_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio29_disable (& self) -> bool { * self == DOE31_0_DIO29_A :: DOE31_0_DIO29_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio29_enable (& self) -> bool { * self == DOE31_0_DIO29_A :: DOE31_0_DIO29_ENABLE } } # [doc = "Field `DOE31_0_DIO29` writer - Enables data output for DIO29."]
pub type DOE31_0_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO29_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio29_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO29_A :: DOE31_0_DIO29_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio29_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO29_A :: DOE31_0_DIO29_ENABLE) } } # [doc = "Field `DOE31_0_DIO30` reader - Enables data output for DIO30."]
pub type DOE31_0_DIO30_R = crate :: BitReader < DOE31_0_DIO30_A > ; # [doc = "Enables data output for DIO30.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO30_A { # [doc = "0: DISABLE"]
DOE31_0_DIO30_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO30_ENABLE = 1 , } impl From < DOE31_0_DIO30_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO30_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO30_A { match self . bits { false => DOE31_0_DIO30_A :: DOE31_0_DIO30_DISABLE , true => DOE31_0_DIO30_A :: DOE31_0_DIO30_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio30_disable (& self) -> bool { * self == DOE31_0_DIO30_A :: DOE31_0_DIO30_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio30_enable (& self) -> bool { * self == DOE31_0_DIO30_A :: DOE31_0_DIO30_ENABLE } } # [doc = "Field `DOE31_0_DIO30` writer - Enables data output for DIO30."]
pub type DOE31_0_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO30_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio30_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO30_A :: DOE31_0_DIO30_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio30_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO30_A :: DOE31_0_DIO30_ENABLE) } } # [doc = "Field `DOE31_0_DIO31` reader - Enables data output for DIO31."]
pub type DOE31_0_DIO31_R = crate :: BitReader < DOE31_0_DIO31_A > ; # [doc = "Enables data output for DIO31.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOE31_0_DIO31_A { # [doc = "0: DISABLE"]
DOE31_0_DIO31_DISABLE = 0 , # [doc = "1: ENABLE"]
DOE31_0_DIO31_ENABLE = 1 , } impl From < DOE31_0_DIO31_A > for bool { # [inline (always)]
fn from (variant : DOE31_0_DIO31_A) -> Self { variant as u8 != 0 } } impl DOE31_0_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DOE31_0_DIO31_A { match self . bits { false => DOE31_0_DIO31_A :: DOE31_0_DIO31_DISABLE , true => DOE31_0_DIO31_A :: DOE31_0_DIO31_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_doe31_0_dio31_disable (& self) -> bool { * self == DOE31_0_DIO31_A :: DOE31_0_DIO31_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_doe31_0_dio31_enable (& self) -> bool { * self == DOE31_0_DIO31_A :: DOE31_0_DIO31_ENABLE } } # [doc = "Field `DOE31_0_DIO31` writer - Enables data output for DIO31."]
pub type DOE31_0_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOE31_0_DIO31_A > ; impl < 'a , REG , const O : u8 > DOE31_0_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn doe31_0_dio31_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO31_A :: DOE31_0_DIO31_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn doe31_0_dio31_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DOE31_0_DIO31_A :: DOE31_0_DIO31_ENABLE) } } impl R { # [doc = "Bit 0 - Enables data output for DIO0."]
# [inline (always)]
pub fn doe31_0_dio0 (& self) -> DOE31_0_DIO0_R { DOE31_0_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enables data output for DIO1."]
# [inline (always)]
pub fn doe31_0_dio1 (& self) -> DOE31_0_DIO1_R { DOE31_0_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enables data output for DIO2."]
# [inline (always)]
pub fn doe31_0_dio2 (& self) -> DOE31_0_DIO2_R { DOE31_0_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enables data output for DIO3."]
# [inline (always)]
pub fn doe31_0_dio3 (& self) -> DOE31_0_DIO3_R { DOE31_0_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enables data output for DIO4."]
# [inline (always)]
pub fn doe31_0_dio4 (& self) -> DOE31_0_DIO4_R { DOE31_0_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enables data output for DIO5."]
# [inline (always)]
pub fn doe31_0_dio5 (& self) -> DOE31_0_DIO5_R { DOE31_0_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enables data output for DIO6."]
# [inline (always)]
pub fn doe31_0_dio6 (& self) -> DOE31_0_DIO6_R { DOE31_0_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enables data output for DIO7."]
# [inline (always)]
pub fn doe31_0_dio7 (& self) -> DOE31_0_DIO7_R { DOE31_0_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enables data output for DIO8."]
# [inline (always)]
pub fn doe31_0_dio8 (& self) -> DOE31_0_DIO8_R { DOE31_0_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enables data output for DIO9."]
# [inline (always)]
pub fn doe31_0_dio9 (& self) -> DOE31_0_DIO9_R { DOE31_0_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enables data output for DIO10."]
# [inline (always)]
pub fn doe31_0_dio10 (& self) -> DOE31_0_DIO10_R { DOE31_0_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enables data output for DIO11."]
# [inline (always)]
pub fn doe31_0_dio11 (& self) -> DOE31_0_DIO11_R { DOE31_0_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enables data output for DIO12."]
# [inline (always)]
pub fn doe31_0_dio12 (& self) -> DOE31_0_DIO12_R { DOE31_0_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enables data output for DIO13."]
# [inline (always)]
pub fn doe31_0_dio13 (& self) -> DOE31_0_DIO13_R { DOE31_0_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enables data output for DIO14."]
# [inline (always)]
pub fn doe31_0_dio14 (& self) -> DOE31_0_DIO14_R { DOE31_0_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enables data output for DIO15."]
# [inline (always)]
pub fn doe31_0_dio15 (& self) -> DOE31_0_DIO15_R { DOE31_0_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enables data output for DIO16."]
# [inline (always)]
pub fn doe31_0_dio16 (& self) -> DOE31_0_DIO16_R { DOE31_0_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Enables data output for DIO17."]
# [inline (always)]
pub fn doe31_0_dio17 (& self) -> DOE31_0_DIO17_R { DOE31_0_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Enables data output for DIO18."]
# [inline (always)]
pub fn doe31_0_dio18 (& self) -> DOE31_0_DIO18_R { DOE31_0_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Enables data output for DIO19."]
# [inline (always)]
pub fn doe31_0_dio19 (& self) -> DOE31_0_DIO19_R { DOE31_0_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - Enables data output for DIO20."]
# [inline (always)]
pub fn doe31_0_dio20 (& self) -> DOE31_0_DIO20_R { DOE31_0_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Enables data output for DIO21."]
# [inline (always)]
pub fn doe31_0_dio21 (& self) -> DOE31_0_DIO21_R { DOE31_0_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Enables data output for DIO22."]
# [inline (always)]
pub fn doe31_0_dio22 (& self) -> DOE31_0_DIO22_R { DOE31_0_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Enables data output for DIO23."]
# [inline (always)]
pub fn doe31_0_dio23 (& self) -> DOE31_0_DIO23_R { DOE31_0_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - Enables data output for DIO24."]
# [inline (always)]
pub fn doe31_0_dio24 (& self) -> DOE31_0_DIO24_R { DOE31_0_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Enables data output for DIO25."]
# [inline (always)]
pub fn doe31_0_dio25 (& self) -> DOE31_0_DIO25_R { DOE31_0_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - Enables data output for DIO26."]
# [inline (always)]
pub fn doe31_0_dio26 (& self) -> DOE31_0_DIO26_R { DOE31_0_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Enables data output for DIO27."]
# [inline (always)]
pub fn doe31_0_dio27 (& self) -> DOE31_0_DIO27_R { DOE31_0_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Enables data output for DIO28."]
# [inline (always)]
pub fn doe31_0_dio28 (& self) -> DOE31_0_DIO28_R { DOE31_0_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Enables data output for DIO29."]
# [inline (always)]
pub fn doe31_0_dio29 (& self) -> DOE31_0_DIO29_R { DOE31_0_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Enables data output for DIO30."]
# [inline (always)]
pub fn doe31_0_dio30 (& self) -> DOE31_0_DIO30_R { DOE31_0_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Enables data output for DIO31."]
# [inline (always)]
pub fn doe31_0_dio31 (& self) -> DOE31_0_DIO31_R { DOE31_0_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enables data output for DIO0."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio0 (& mut self) -> DOE31_0_DIO0_W < DOE31_0_SPEC , 0 > { DOE31_0_DIO0_W :: new (self) } # [doc = "Bit 1 - Enables data output for DIO1."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio1 (& mut self) -> DOE31_0_DIO1_W < DOE31_0_SPEC , 1 > { DOE31_0_DIO1_W :: new (self) } # [doc = "Bit 2 - Enables data output for DIO2."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio2 (& mut self) -> DOE31_0_DIO2_W < DOE31_0_SPEC , 2 > { DOE31_0_DIO2_W :: new (self) } # [doc = "Bit 3 - Enables data output for DIO3."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio3 (& mut self) -> DOE31_0_DIO3_W < DOE31_0_SPEC , 3 > { DOE31_0_DIO3_W :: new (self) } # [doc = "Bit 4 - Enables data output for DIO4."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio4 (& mut self) -> DOE31_0_DIO4_W < DOE31_0_SPEC , 4 > { DOE31_0_DIO4_W :: new (self) } # [doc = "Bit 5 - Enables data output for DIO5."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio5 (& mut self) -> DOE31_0_DIO5_W < DOE31_0_SPEC , 5 > { DOE31_0_DIO5_W :: new (self) } # [doc = "Bit 6 - Enables data output for DIO6."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio6 (& mut self) -> DOE31_0_DIO6_W < DOE31_0_SPEC , 6 > { DOE31_0_DIO6_W :: new (self) } # [doc = "Bit 7 - Enables data output for DIO7."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio7 (& mut self) -> DOE31_0_DIO7_W < DOE31_0_SPEC , 7 > { DOE31_0_DIO7_W :: new (self) } # [doc = "Bit 8 - Enables data output for DIO8."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio8 (& mut self) -> DOE31_0_DIO8_W < DOE31_0_SPEC , 8 > { DOE31_0_DIO8_W :: new (self) } # [doc = "Bit 9 - Enables data output for DIO9."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio9 (& mut self) -> DOE31_0_DIO9_W < DOE31_0_SPEC , 9 > { DOE31_0_DIO9_W :: new (self) } # [doc = "Bit 10 - Enables data output for DIO10."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio10 (& mut self) -> DOE31_0_DIO10_W < DOE31_0_SPEC , 10 > { DOE31_0_DIO10_W :: new (self) } # [doc = "Bit 11 - Enables data output for DIO11."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio11 (& mut self) -> DOE31_0_DIO11_W < DOE31_0_SPEC , 11 > { DOE31_0_DIO11_W :: new (self) } # [doc = "Bit 12 - Enables data output for DIO12."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio12 (& mut self) -> DOE31_0_DIO12_W < DOE31_0_SPEC , 12 > { DOE31_0_DIO12_W :: new (self) } # [doc = "Bit 13 - Enables data output for DIO13."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio13 (& mut self) -> DOE31_0_DIO13_W < DOE31_0_SPEC , 13 > { DOE31_0_DIO13_W :: new (self) } # [doc = "Bit 14 - Enables data output for DIO14."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio14 (& mut self) -> DOE31_0_DIO14_W < DOE31_0_SPEC , 14 > { DOE31_0_DIO14_W :: new (self) } # [doc = "Bit 15 - Enables data output for DIO15."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio15 (& mut self) -> DOE31_0_DIO15_W < DOE31_0_SPEC , 15 > { DOE31_0_DIO15_W :: new (self) } # [doc = "Bit 16 - Enables data output for DIO16."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio16 (& mut self) -> DOE31_0_DIO16_W < DOE31_0_SPEC , 16 > { DOE31_0_DIO16_W :: new (self) } # [doc = "Bit 17 - Enables data output for DIO17."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio17 (& mut self) -> DOE31_0_DIO17_W < DOE31_0_SPEC , 17 > { DOE31_0_DIO17_W :: new (self) } # [doc = "Bit 18 - Enables data output for DIO18."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio18 (& mut self) -> DOE31_0_DIO18_W < DOE31_0_SPEC , 18 > { DOE31_0_DIO18_W :: new (self) } # [doc = "Bit 19 - Enables data output for DIO19."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio19 (& mut self) -> DOE31_0_DIO19_W < DOE31_0_SPEC , 19 > { DOE31_0_DIO19_W :: new (self) } # [doc = "Bit 20 - Enables data output for DIO20."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio20 (& mut self) -> DOE31_0_DIO20_W < DOE31_0_SPEC , 20 > { DOE31_0_DIO20_W :: new (self) } # [doc = "Bit 21 - Enables data output for DIO21."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio21 (& mut self) -> DOE31_0_DIO21_W < DOE31_0_SPEC , 21 > { DOE31_0_DIO21_W :: new (self) } # [doc = "Bit 22 - Enables data output for DIO22."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio22 (& mut self) -> DOE31_0_DIO22_W < DOE31_0_SPEC , 22 > { DOE31_0_DIO22_W :: new (self) } # [doc = "Bit 23 - Enables data output for DIO23."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio23 (& mut self) -> DOE31_0_DIO23_W < DOE31_0_SPEC , 23 > { DOE31_0_DIO23_W :: new (self) } # [doc = "Bit 24 - Enables data output for DIO24."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio24 (& mut self) -> DOE31_0_DIO24_W < DOE31_0_SPEC , 24 > { DOE31_0_DIO24_W :: new (self) } # [doc = "Bit 25 - Enables data output for DIO25."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio25 (& mut self) -> DOE31_0_DIO25_W < DOE31_0_SPEC , 25 > { DOE31_0_DIO25_W :: new (self) } # [doc = "Bit 26 - Enables data output for DIO26."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio26 (& mut self) -> DOE31_0_DIO26_W < DOE31_0_SPEC , 26 > { DOE31_0_DIO26_W :: new (self) } # [doc = "Bit 27 - Enables data output for DIO27."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio27 (& mut self) -> DOE31_0_DIO27_W < DOE31_0_SPEC , 27 > { DOE31_0_DIO27_W :: new (self) } # [doc = "Bit 28 - Enables data output for DIO28."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio28 (& mut self) -> DOE31_0_DIO28_W < DOE31_0_SPEC , 28 > { DOE31_0_DIO28_W :: new (self) } # [doc = "Bit 29 - Enables data output for DIO29."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio29 (& mut self) -> DOE31_0_DIO29_W < DOE31_0_SPEC , 29 > { DOE31_0_DIO29_W :: new (self) } # [doc = "Bit 30 - Enables data output for DIO30."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio30 (& mut self) -> DOE31_0_DIO30_W < DOE31_0_SPEC , 30 > { DOE31_0_DIO30_W :: new (self) } # [doc = "Bit 31 - Enables data output for DIO31."]
# [inline (always)]
# [must_use]
pub fn doe31_0_dio31 (& mut self) -> DOE31_0_DIO31_W < DOE31_0_SPEC , 31 > { DOE31_0_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output enable 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`doe31_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doe31_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOE31_0_SPEC ; impl crate :: RegisterSpec for DOE31_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`doe31_0::R`](R) reader structure"]
impl crate :: Readable for DOE31_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`doe31_0::W`](W) writer structure"]
impl crate :: Writable for DOE31_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOE31_0 to value 0"]
impl crate :: Resettable for DOE31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOESET31_0 (w) register accessor: Data output enable set 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeset31_0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doeset31_0`]
module"]
pub type DOESET31_0 = crate :: Reg < doeset31_0 :: DOESET31_0_SPEC > ; # [doc = "Data output enable set 31 to 0"]
pub mod doeset31_0 { # [doc = "Register `DOESET31_0` writer"]
pub type W = crate :: W < DOESET31_0_SPEC > ; # [doc = "Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO0_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO0_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO0_SET = 1 , } impl From < DOESET31_0_DIO0_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO0` writer - Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO0_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO0_AW :: DOESET31_0_DIO0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio0_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO0_AW :: DOESET31_0_DIO0_SET) } } # [doc = "Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO1_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO1_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO1_SET = 1 , } impl From < DOESET31_0_DIO1_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO1` writer - Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO1_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO1_AW :: DOESET31_0_DIO1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio1_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO1_AW :: DOESET31_0_DIO1_SET) } } # [doc = "Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO2_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO2_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO2_SET = 1 , } impl From < DOESET31_0_DIO2_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO2` writer - Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO2_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO2_AW :: DOESET31_0_DIO2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio2_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO2_AW :: DOESET31_0_DIO2_SET) } } # [doc = "Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO3_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO3_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO3_SET = 1 , } impl From < DOESET31_0_DIO3_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO3` writer - Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO3_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO3_AW :: DOESET31_0_DIO3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio3_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO3_AW :: DOESET31_0_DIO3_SET) } } # [doc = "Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO4_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO4_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO4_SET = 1 , } impl From < DOESET31_0_DIO4_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO4` writer - Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO4_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO4_AW :: DOESET31_0_DIO4_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio4_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO4_AW :: DOESET31_0_DIO4_SET) } } # [doc = "Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO5_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO5_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO5_SET = 1 , } impl From < DOESET31_0_DIO5_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO5` writer - Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO5_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO5_AW :: DOESET31_0_DIO5_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio5_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO5_AW :: DOESET31_0_DIO5_SET) } } # [doc = "Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO6_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO6_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO6_SET = 1 , } impl From < DOESET31_0_DIO6_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO6` writer - Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO6_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO6_AW :: DOESET31_0_DIO6_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio6_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO6_AW :: DOESET31_0_DIO6_SET) } } # [doc = "Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO7_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO7_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO7_SET = 1 , } impl From < DOESET31_0_DIO7_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO7` writer - Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO7_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO7_AW :: DOESET31_0_DIO7_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio7_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO7_AW :: DOESET31_0_DIO7_SET) } } # [doc = "Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO8_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO8_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO8_SET = 1 , } impl From < DOESET31_0_DIO8_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO8` writer - Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO8_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO8_AW :: DOESET31_0_DIO8_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio8_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO8_AW :: DOESET31_0_DIO8_SET) } } # [doc = "Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO9_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO9_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO9_SET = 1 , } impl From < DOESET31_0_DIO9_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO9` writer - Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO9_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO9_AW :: DOESET31_0_DIO9_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio9_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO9_AW :: DOESET31_0_DIO9_SET) } } # [doc = "Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO10_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO10_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO10_SET = 1 , } impl From < DOESET31_0_DIO10_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO10` writer - Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO10_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO10_AW :: DOESET31_0_DIO10_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio10_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO10_AW :: DOESET31_0_DIO10_SET) } } # [doc = "Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO11_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO11_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO11_SET = 1 , } impl From < DOESET31_0_DIO11_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO11` writer - Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO11_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO11_AW :: DOESET31_0_DIO11_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio11_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO11_AW :: DOESET31_0_DIO11_SET) } } # [doc = "Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO12_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO12_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO12_SET = 1 , } impl From < DOESET31_0_DIO12_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO12` writer - Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO12_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO12_AW :: DOESET31_0_DIO12_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio12_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO12_AW :: DOESET31_0_DIO12_SET) } } # [doc = "Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO13_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO13_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO13_SET = 1 , } impl From < DOESET31_0_DIO13_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO13` writer - Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO13_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO13_AW :: DOESET31_0_DIO13_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio13_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO13_AW :: DOESET31_0_DIO13_SET) } } # [doc = "Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO14_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO14_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO14_SET = 1 , } impl From < DOESET31_0_DIO14_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO14` writer - Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO14_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO14_AW :: DOESET31_0_DIO14_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio14_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO14_AW :: DOESET31_0_DIO14_SET) } } # [doc = "Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO15_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO15_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO15_SET = 1 , } impl From < DOESET31_0_DIO15_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO15` writer - Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO15_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO15_AW :: DOESET31_0_DIO15_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio15_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO15_AW :: DOESET31_0_DIO15_SET) } } # [doc = "Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO16_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO16_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO16_SET = 1 , } impl From < DOESET31_0_DIO16_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO16` writer - Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO16_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO16_AW :: DOESET31_0_DIO16_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio16_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO16_AW :: DOESET31_0_DIO16_SET) } } # [doc = "Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO17_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO17_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO17_SET = 1 , } impl From < DOESET31_0_DIO17_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO17` writer - Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO17_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO17_AW :: DOESET31_0_DIO17_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio17_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO17_AW :: DOESET31_0_DIO17_SET) } } # [doc = "Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO18_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO18_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO18_SET = 1 , } impl From < DOESET31_0_DIO18_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO18` writer - Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO18_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO18_AW :: DOESET31_0_DIO18_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio18_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO18_AW :: DOESET31_0_DIO18_SET) } } # [doc = "Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO19_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO19_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO19_SET = 1 , } impl From < DOESET31_0_DIO19_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO19` writer - Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO19_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO19_AW :: DOESET31_0_DIO19_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio19_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO19_AW :: DOESET31_0_DIO19_SET) } } # [doc = "Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO20_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO20_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO20_SET = 1 , } impl From < DOESET31_0_DIO20_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO20` writer - Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO20_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO20_AW :: DOESET31_0_DIO20_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio20_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO20_AW :: DOESET31_0_DIO20_SET) } } # [doc = "Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO21_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO21_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO21_SET = 1 , } impl From < DOESET31_0_DIO21_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO21` writer - Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO21_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO21_AW :: DOESET31_0_DIO21_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio21_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO21_AW :: DOESET31_0_DIO21_SET) } } # [doc = "Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO22_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO22_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO22_SET = 1 , } impl From < DOESET31_0_DIO22_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO22` writer - Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO22_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO22_AW :: DOESET31_0_DIO22_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio22_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO22_AW :: DOESET31_0_DIO22_SET) } } # [doc = "Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO23_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO23_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO23_SET = 1 , } impl From < DOESET31_0_DIO23_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO23` writer - Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO23_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO23_AW :: DOESET31_0_DIO23_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio23_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO23_AW :: DOESET31_0_DIO23_SET) } } # [doc = "Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO24_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO24_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO24_SET = 1 , } impl From < DOESET31_0_DIO24_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO24` writer - Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO24_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO24_AW :: DOESET31_0_DIO24_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio24_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO24_AW :: DOESET31_0_DIO24_SET) } } # [doc = "Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO25_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO25_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO25_SET = 1 , } impl From < DOESET31_0_DIO25_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO25` writer - Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO25_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO25_AW :: DOESET31_0_DIO25_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio25_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO25_AW :: DOESET31_0_DIO25_SET) } } # [doc = "Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO26_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO26_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO26_SET = 1 , } impl From < DOESET31_0_DIO26_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO26` writer - Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO26_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO26_AW :: DOESET31_0_DIO26_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio26_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO26_AW :: DOESET31_0_DIO26_SET) } } # [doc = "Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO27_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO27_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO27_SET = 1 , } impl From < DOESET31_0_DIO27_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO27` writer - Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO27_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO27_AW :: DOESET31_0_DIO27_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio27_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO27_AW :: DOESET31_0_DIO27_SET) } } # [doc = "Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO28_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO28_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO28_SET = 1 , } impl From < DOESET31_0_DIO28_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO28` writer - Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO28_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO28_AW :: DOESET31_0_DIO28_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio28_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO28_AW :: DOESET31_0_DIO28_SET) } } # [doc = "Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO29_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO29_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO29_SET = 1 , } impl From < DOESET31_0_DIO29_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO29` writer - Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO29_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO29_AW :: DOESET31_0_DIO29_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio29_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO29_AW :: DOESET31_0_DIO29_SET) } } # [doc = "Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO30_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO30_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO30_SET = 1 , } impl From < DOESET31_0_DIO30_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO30` writer - Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO30_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO30_AW :: DOESET31_0_DIO30_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio30_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO30_AW :: DOESET31_0_DIO30_SET) } } # [doc = "Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOESET31_0_DIO31_AW { # [doc = "0: NO_EFFECT"]
DOESET31_0_DIO31_NO_EFFECT = 0 , # [doc = "1: SET"]
DOESET31_0_DIO31_SET = 1 , } impl From < DOESET31_0_DIO31_AW > for bool { # [inline (always)]
fn from (variant : DOESET31_0_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOESET31_0_DIO31` writer - Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOESET31_0_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOESET31_0_DIO31_AW > ; impl < 'a , REG , const O : u8 > DOESET31_0_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeset31_0_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO31_AW :: DOESET31_0_DIO31_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn doeset31_0_dio31_set (self) -> & 'a mut crate :: W < REG > { self . variant (DOESET31_0_DIO31_AW :: DOESET31_0_DIO31_SET) } } impl W { # [doc = "Bit 0 - Writing 1 to this bit sets the DIO0 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio0 (& mut self) -> DOESET31_0_DIO0_W < DOESET31_0_SPEC , 0 > { DOESET31_0_DIO0_W :: new (self) } # [doc = "Bit 1 - Writing 1 to this bit sets the DIO1 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio1 (& mut self) -> DOESET31_0_DIO1_W < DOESET31_0_SPEC , 1 > { DOESET31_0_DIO1_W :: new (self) } # [doc = "Bit 2 - Writing 1 to this bit sets the DIO2 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio2 (& mut self) -> DOESET31_0_DIO2_W < DOESET31_0_SPEC , 2 > { DOESET31_0_DIO2_W :: new (self) } # [doc = "Bit 3 - Writing 1 to this bit sets the DIO3 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio3 (& mut self) -> DOESET31_0_DIO3_W < DOESET31_0_SPEC , 3 > { DOESET31_0_DIO3_W :: new (self) } # [doc = "Bit 4 - Writing 1 to this bit sets the DIO4 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio4 (& mut self) -> DOESET31_0_DIO4_W < DOESET31_0_SPEC , 4 > { DOESET31_0_DIO4_W :: new (self) } # [doc = "Bit 5 - Writing 1 to this bit sets the DIO5 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio5 (& mut self) -> DOESET31_0_DIO5_W < DOESET31_0_SPEC , 5 > { DOESET31_0_DIO5_W :: new (self) } # [doc = "Bit 6 - Writing 1 to this bit sets the DIO6 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio6 (& mut self) -> DOESET31_0_DIO6_W < DOESET31_0_SPEC , 6 > { DOESET31_0_DIO6_W :: new (self) } # [doc = "Bit 7 - Writing 1 to this bit sets the DIO7 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio7 (& mut self) -> DOESET31_0_DIO7_W < DOESET31_0_SPEC , 7 > { DOESET31_0_DIO7_W :: new (self) } # [doc = "Bit 8 - Writing 1 to this bit sets the DIO8 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio8 (& mut self) -> DOESET31_0_DIO8_W < DOESET31_0_SPEC , 8 > { DOESET31_0_DIO8_W :: new (self) } # [doc = "Bit 9 - Writing 1 to this bit sets the DIO9 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio9 (& mut self) -> DOESET31_0_DIO9_W < DOESET31_0_SPEC , 9 > { DOESET31_0_DIO9_W :: new (self) } # [doc = "Bit 10 - Writing 1 to this bit sets the DIO10 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio10 (& mut self) -> DOESET31_0_DIO10_W < DOESET31_0_SPEC , 10 > { DOESET31_0_DIO10_W :: new (self) } # [doc = "Bit 11 - Writing 1 to this bit sets the DIO11 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio11 (& mut self) -> DOESET31_0_DIO11_W < DOESET31_0_SPEC , 11 > { DOESET31_0_DIO11_W :: new (self) } # [doc = "Bit 12 - Writing 1 to this bit sets the DIO12 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio12 (& mut self) -> DOESET31_0_DIO12_W < DOESET31_0_SPEC , 12 > { DOESET31_0_DIO12_W :: new (self) } # [doc = "Bit 13 - Writing 1 to this bit sets the DIO13 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio13 (& mut self) -> DOESET31_0_DIO13_W < DOESET31_0_SPEC , 13 > { DOESET31_0_DIO13_W :: new (self) } # [doc = "Bit 14 - Writing 1 to this bit sets the DIO14 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio14 (& mut self) -> DOESET31_0_DIO14_W < DOESET31_0_SPEC , 14 > { DOESET31_0_DIO14_W :: new (self) } # [doc = "Bit 15 - Writing 1 to this bit sets the DIO15 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio15 (& mut self) -> DOESET31_0_DIO15_W < DOESET31_0_SPEC , 15 > { DOESET31_0_DIO15_W :: new (self) } # [doc = "Bit 16 - Writing 1 to this bit sets the DIO16 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio16 (& mut self) -> DOESET31_0_DIO16_W < DOESET31_0_SPEC , 16 > { DOESET31_0_DIO16_W :: new (self) } # [doc = "Bit 17 - Writing 1 to this bit sets the DIO17 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio17 (& mut self) -> DOESET31_0_DIO17_W < DOESET31_0_SPEC , 17 > { DOESET31_0_DIO17_W :: new (self) } # [doc = "Bit 18 - Writing 1 to this bit sets the DIO18 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio18 (& mut self) -> DOESET31_0_DIO18_W < DOESET31_0_SPEC , 18 > { DOESET31_0_DIO18_W :: new (self) } # [doc = "Bit 19 - Writing 1 to this bit sets the DIO19 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio19 (& mut self) -> DOESET31_0_DIO19_W < DOESET31_0_SPEC , 19 > { DOESET31_0_DIO19_W :: new (self) } # [doc = "Bit 20 - Writing 1 to this bit sets the DIO20 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio20 (& mut self) -> DOESET31_0_DIO20_W < DOESET31_0_SPEC , 20 > { DOESET31_0_DIO20_W :: new (self) } # [doc = "Bit 21 - Writing 1 to this bit sets the DIO21 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio21 (& mut self) -> DOESET31_0_DIO21_W < DOESET31_0_SPEC , 21 > { DOESET31_0_DIO21_W :: new (self) } # [doc = "Bit 22 - Writing 1 to this bit sets the DIO22 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio22 (& mut self) -> DOESET31_0_DIO22_W < DOESET31_0_SPEC , 22 > { DOESET31_0_DIO22_W :: new (self) } # [doc = "Bit 23 - Writing 1 to this bit sets the DIO23 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio23 (& mut self) -> DOESET31_0_DIO23_W < DOESET31_0_SPEC , 23 > { DOESET31_0_DIO23_W :: new (self) } # [doc = "Bit 24 - Writing 1 to this bit sets the DIO24 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio24 (& mut self) -> DOESET31_0_DIO24_W < DOESET31_0_SPEC , 24 > { DOESET31_0_DIO24_W :: new (self) } # [doc = "Bit 25 - Writing 1 to this bit sets the DIO25 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio25 (& mut self) -> DOESET31_0_DIO25_W < DOESET31_0_SPEC , 25 > { DOESET31_0_DIO25_W :: new (self) } # [doc = "Bit 26 - Writing 1 to this bit sets the DIO26 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio26 (& mut self) -> DOESET31_0_DIO26_W < DOESET31_0_SPEC , 26 > { DOESET31_0_DIO26_W :: new (self) } # [doc = "Bit 27 - Writing 1 to this bit sets the DIO27 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio27 (& mut self) -> DOESET31_0_DIO27_W < DOESET31_0_SPEC , 27 > { DOESET31_0_DIO27_W :: new (self) } # [doc = "Bit 28 - Writing 1 to this bit sets the DIO28 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio28 (& mut self) -> DOESET31_0_DIO28_W < DOESET31_0_SPEC , 28 > { DOESET31_0_DIO28_W :: new (self) } # [doc = "Bit 29 - Writing 1 to this bit sets the DIO29 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio29 (& mut self) -> DOESET31_0_DIO29_W < DOESET31_0_SPEC , 29 > { DOESET31_0_DIO29_W :: new (self) } # [doc = "Bit 30 - Writing 1 to this bit sets the DIO30 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio30 (& mut self) -> DOESET31_0_DIO30_W < DOESET31_0_SPEC , 30 > { DOESET31_0_DIO30_W :: new (self) } # [doc = "Bit 31 - Writing 1 to this bit sets the DIO31 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeset31_0_dio31 (& mut self) -> DOESET31_0_DIO31_W < DOESET31_0_SPEC , 31 > { DOESET31_0_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output enable set 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeset31_0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOESET31_0_SPEC ; impl crate :: RegisterSpec for DOESET31_0_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`doeset31_0::W`](W) writer structure"]
impl crate :: Writable for DOESET31_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOESET31_0 to value 0"]
impl crate :: Resettable for DOESET31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DOECLR31_0 (w) register accessor: Data output enable clear 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeclr31_0::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@doeclr31_0`]
module"]
pub type DOECLR31_0 = crate :: Reg < doeclr31_0 :: DOECLR31_0_SPEC > ; # [doc = "Data output enable clear 31 to 0"]
pub mod doeclr31_0 { # [doc = "Register `DOECLR31_0` writer"]
pub type W = crate :: W < DOECLR31_0_SPEC > ; # [doc = "Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO0_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO0_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO0_CLR = 1 , } impl From < DOECLR31_0_DIO0_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO0` writer - Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO0_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO0_AW :: DOECLR31_0_DIO0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO0_AW :: DOECLR31_0_DIO0_CLR) } } # [doc = "Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO1_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO1_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO1_CLR = 1 , } impl From < DOECLR31_0_DIO1_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO1` writer - Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO1_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO1_AW :: DOECLR31_0_DIO1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO1_AW :: DOECLR31_0_DIO1_CLR) } } # [doc = "Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO2_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO2_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO2_CLR = 1 , } impl From < DOECLR31_0_DIO2_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO2` writer - Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO2_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO2_AW :: DOECLR31_0_DIO2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO2_AW :: DOECLR31_0_DIO2_CLR) } } # [doc = "Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO3_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO3_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO3_CLR = 1 , } impl From < DOECLR31_0_DIO3_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO3` writer - Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO3_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO3_AW :: DOECLR31_0_DIO3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO3_AW :: DOECLR31_0_DIO3_CLR) } } # [doc = "Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO4_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO4_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO4_CLR = 1 , } impl From < DOECLR31_0_DIO4_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO4_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO4` writer - Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO4_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio4_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO4_AW :: DOECLR31_0_DIO4_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio4_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO4_AW :: DOECLR31_0_DIO4_CLR) } } # [doc = "Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO5_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO5_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO5_CLR = 1 , } impl From < DOECLR31_0_DIO5_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO5_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO5` writer - Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO5_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio5_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO5_AW :: DOECLR31_0_DIO5_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio5_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO5_AW :: DOECLR31_0_DIO5_CLR) } } # [doc = "Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO6_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO6_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO6_CLR = 1 , } impl From < DOECLR31_0_DIO6_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO6_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO6` writer - Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO6_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio6_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO6_AW :: DOECLR31_0_DIO6_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio6_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO6_AW :: DOECLR31_0_DIO6_CLR) } } # [doc = "Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO7_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO7_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO7_CLR = 1 , } impl From < DOECLR31_0_DIO7_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO7_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO7` writer - Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO7_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio7_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO7_AW :: DOECLR31_0_DIO7_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio7_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO7_AW :: DOECLR31_0_DIO7_CLR) } } # [doc = "Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO8_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO8_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO8_CLR = 1 , } impl From < DOECLR31_0_DIO8_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO8_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO8` writer - Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO8_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio8_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO8_AW :: DOECLR31_0_DIO8_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio8_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO8_AW :: DOECLR31_0_DIO8_CLR) } } # [doc = "Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO9_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO9_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO9_CLR = 1 , } impl From < DOECLR31_0_DIO9_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO9_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO9` writer - Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO9_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio9_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO9_AW :: DOECLR31_0_DIO9_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio9_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO9_AW :: DOECLR31_0_DIO9_CLR) } } # [doc = "Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO10_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO10_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO10_CLR = 1 , } impl From < DOECLR31_0_DIO10_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO10_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO10` writer - Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO10_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio10_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO10_AW :: DOECLR31_0_DIO10_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio10_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO10_AW :: DOECLR31_0_DIO10_CLR) } } # [doc = "Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO11_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO11_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO11_CLR = 1 , } impl From < DOECLR31_0_DIO11_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO11_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO11` writer - Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO11_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio11_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO11_AW :: DOECLR31_0_DIO11_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio11_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO11_AW :: DOECLR31_0_DIO11_CLR) } } # [doc = "Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO12_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO12_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO12_CLR = 1 , } impl From < DOECLR31_0_DIO12_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO12_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO12` writer - Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO12_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio12_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO12_AW :: DOECLR31_0_DIO12_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio12_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO12_AW :: DOECLR31_0_DIO12_CLR) } } # [doc = "Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO13_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO13_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO13_CLR = 1 , } impl From < DOECLR31_0_DIO13_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO13_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO13` writer - Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO13_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio13_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO13_AW :: DOECLR31_0_DIO13_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio13_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO13_AW :: DOECLR31_0_DIO13_CLR) } } # [doc = "Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO14_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO14_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO14_CLR = 1 , } impl From < DOECLR31_0_DIO14_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO14_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO14` writer - Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO14_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio14_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO14_AW :: DOECLR31_0_DIO14_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio14_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO14_AW :: DOECLR31_0_DIO14_CLR) } } # [doc = "Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO15_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO15_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO15_CLR = 1 , } impl From < DOECLR31_0_DIO15_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO15_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO15` writer - Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO15_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio15_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO15_AW :: DOECLR31_0_DIO15_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio15_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO15_AW :: DOECLR31_0_DIO15_CLR) } } # [doc = "Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO16_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO16_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO16_CLR = 1 , } impl From < DOECLR31_0_DIO16_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO16_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO16` writer - Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO16_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio16_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO16_AW :: DOECLR31_0_DIO16_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio16_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO16_AW :: DOECLR31_0_DIO16_CLR) } } # [doc = "Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO17_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO17_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO17_CLR = 1 , } impl From < DOECLR31_0_DIO17_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO17_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO17` writer - Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO17_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio17_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO17_AW :: DOECLR31_0_DIO17_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio17_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO17_AW :: DOECLR31_0_DIO17_CLR) } } # [doc = "Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO18_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO18_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO18_CLR = 1 , } impl From < DOECLR31_0_DIO18_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO18_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO18` writer - Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO18_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio18_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO18_AW :: DOECLR31_0_DIO18_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio18_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO18_AW :: DOECLR31_0_DIO18_CLR) } } # [doc = "Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO19_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO19_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO19_CLR = 1 , } impl From < DOECLR31_0_DIO19_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO19_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO19` writer - Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO19_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio19_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO19_AW :: DOECLR31_0_DIO19_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio19_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO19_AW :: DOECLR31_0_DIO19_CLR) } } # [doc = "Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO20_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO20_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO20_CLR = 1 , } impl From < DOECLR31_0_DIO20_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO20_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO20` writer - Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO20_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio20_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO20_AW :: DOECLR31_0_DIO20_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio20_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO20_AW :: DOECLR31_0_DIO20_CLR) } } # [doc = "Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO21_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO21_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO21_CLR = 1 , } impl From < DOECLR31_0_DIO21_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO21_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO21` writer - Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO21_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio21_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO21_AW :: DOECLR31_0_DIO21_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio21_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO21_AW :: DOECLR31_0_DIO21_CLR) } } # [doc = "Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO22_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO22_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO22_CLR = 1 , } impl From < DOECLR31_0_DIO22_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO22_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO22` writer - Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO22_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio22_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO22_AW :: DOECLR31_0_DIO22_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio22_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO22_AW :: DOECLR31_0_DIO22_CLR) } } # [doc = "Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO23_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO23_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO23_CLR = 1 , } impl From < DOECLR31_0_DIO23_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO23_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO23` writer - Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO23_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio23_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO23_AW :: DOECLR31_0_DIO23_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio23_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO23_AW :: DOECLR31_0_DIO23_CLR) } } # [doc = "Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO24_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO24_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO24_CLR = 1 , } impl From < DOECLR31_0_DIO24_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO24_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO24` writer - Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO24_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio24_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO24_AW :: DOECLR31_0_DIO24_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio24_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO24_AW :: DOECLR31_0_DIO24_CLR) } } # [doc = "Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO25_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO25_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO25_CLR = 1 , } impl From < DOECLR31_0_DIO25_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO25_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO25` writer - Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO25_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio25_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO25_AW :: DOECLR31_0_DIO25_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio25_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO25_AW :: DOECLR31_0_DIO25_CLR) } } # [doc = "Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO26_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO26_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO26_CLR = 1 , } impl From < DOECLR31_0_DIO26_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO26_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO26` writer - Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO26_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio26_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO26_AW :: DOECLR31_0_DIO26_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio26_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO26_AW :: DOECLR31_0_DIO26_CLR) } } # [doc = "Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO27_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO27_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO27_CLR = 1 , } impl From < DOECLR31_0_DIO27_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO27_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO27` writer - Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO27_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio27_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO27_AW :: DOECLR31_0_DIO27_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio27_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO27_AW :: DOECLR31_0_DIO27_CLR) } } # [doc = "Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO28_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO28_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO28_CLR = 1 , } impl From < DOECLR31_0_DIO28_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO28_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO28` writer - Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO28_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio28_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO28_AW :: DOECLR31_0_DIO28_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio28_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO28_AW :: DOECLR31_0_DIO28_CLR) } } # [doc = "Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO29_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO29_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO29_CLR = 1 , } impl From < DOECLR31_0_DIO29_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO29_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO29` writer - Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO29_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio29_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO29_AW :: DOECLR31_0_DIO29_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio29_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO29_AW :: DOECLR31_0_DIO29_CLR) } } # [doc = "Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO30_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO30_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO30_CLR = 1 , } impl From < DOECLR31_0_DIO30_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO30_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO30` writer - Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO30_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio30_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO30_AW :: DOECLR31_0_DIO30_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio30_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO30_AW :: DOECLR31_0_DIO30_CLR) } } # [doc = "Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DOECLR31_0_DIO31_AW { # [doc = "0: NO_EFFECT"]
DOECLR31_0_DIO31_NO_EFFECT = 0 , # [doc = "1: CLR"]
DOECLR31_0_DIO31_CLR = 1 , } impl From < DOECLR31_0_DIO31_AW > for bool { # [inline (always)]
fn from (variant : DOECLR31_0_DIO31_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `DOECLR31_0_DIO31` writer - Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect."]
pub type DOECLR31_0_DIO31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DOECLR31_0_DIO31_AW > ; impl < 'a , REG , const O : u8 > DOECLR31_0_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn doeclr31_0_dio31_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO31_AW :: DOECLR31_0_DIO31_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn doeclr31_0_dio31_clr (self) -> & 'a mut crate :: W < REG > { self . variant (DOECLR31_0_DIO31_AW :: DOECLR31_0_DIO31_CLR) } } impl W { # [doc = "Bit 0 - Writing 1 to this bit clears the DIO0 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio0 (& mut self) -> DOECLR31_0_DIO0_W < DOECLR31_0_SPEC , 0 > { DOECLR31_0_DIO0_W :: new (self) } # [doc = "Bit 1 - Writing 1 to this bit clears the DIO1 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio1 (& mut self) -> DOECLR31_0_DIO1_W < DOECLR31_0_SPEC , 1 > { DOECLR31_0_DIO1_W :: new (self) } # [doc = "Bit 2 - Writing 1 to this bit clears the DIO2 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio2 (& mut self) -> DOECLR31_0_DIO2_W < DOECLR31_0_SPEC , 2 > { DOECLR31_0_DIO2_W :: new (self) } # [doc = "Bit 3 - Writing 1 to this bit clears the DIO3 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio3 (& mut self) -> DOECLR31_0_DIO3_W < DOECLR31_0_SPEC , 3 > { DOECLR31_0_DIO3_W :: new (self) } # [doc = "Bit 4 - Writing 1 to this bit clears the DIO4 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio4 (& mut self) -> DOECLR31_0_DIO4_W < DOECLR31_0_SPEC , 4 > { DOECLR31_0_DIO4_W :: new (self) } # [doc = "Bit 5 - Writing 1 to this bit clears the DIO5 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio5 (& mut self) -> DOECLR31_0_DIO5_W < DOECLR31_0_SPEC , 5 > { DOECLR31_0_DIO5_W :: new (self) } # [doc = "Bit 6 - Writing 1 to this bit clears the DIO6 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio6 (& mut self) -> DOECLR31_0_DIO6_W < DOECLR31_0_SPEC , 6 > { DOECLR31_0_DIO6_W :: new (self) } # [doc = "Bit 7 - Writing 1 to this bit clears the DIO7 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio7 (& mut self) -> DOECLR31_0_DIO7_W < DOECLR31_0_SPEC , 7 > { DOECLR31_0_DIO7_W :: new (self) } # [doc = "Bit 8 - Writing 1 to this bit clears the DIO8 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio8 (& mut self) -> DOECLR31_0_DIO8_W < DOECLR31_0_SPEC , 8 > { DOECLR31_0_DIO8_W :: new (self) } # [doc = "Bit 9 - Writing 1 to this bit clears the DIO9 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio9 (& mut self) -> DOECLR31_0_DIO9_W < DOECLR31_0_SPEC , 9 > { DOECLR31_0_DIO9_W :: new (self) } # [doc = "Bit 10 - Writing 1 to this bit clears the DIO10 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio10 (& mut self) -> DOECLR31_0_DIO10_W < DOECLR31_0_SPEC , 10 > { DOECLR31_0_DIO10_W :: new (self) } # [doc = "Bit 11 - Writing 1 to this bit clears the DIO11 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio11 (& mut self) -> DOECLR31_0_DIO11_W < DOECLR31_0_SPEC , 11 > { DOECLR31_0_DIO11_W :: new (self) } # [doc = "Bit 12 - Writing 1 to this bit clears the DIO12 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio12 (& mut self) -> DOECLR31_0_DIO12_W < DOECLR31_0_SPEC , 12 > { DOECLR31_0_DIO12_W :: new (self) } # [doc = "Bit 13 - Writing 1 to this bit clears the DIO13 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio13 (& mut self) -> DOECLR31_0_DIO13_W < DOECLR31_0_SPEC , 13 > { DOECLR31_0_DIO13_W :: new (self) } # [doc = "Bit 14 - Writing 1 to this bit clears the DIO14 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio14 (& mut self) -> DOECLR31_0_DIO14_W < DOECLR31_0_SPEC , 14 > { DOECLR31_0_DIO14_W :: new (self) } # [doc = "Bit 15 - Writing 1 to this bit clears the DIO15 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio15 (& mut self) -> DOECLR31_0_DIO15_W < DOECLR31_0_SPEC , 15 > { DOECLR31_0_DIO15_W :: new (self) } # [doc = "Bit 16 - Writing 1 to this bit clears the DIO16 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio16 (& mut self) -> DOECLR31_0_DIO16_W < DOECLR31_0_SPEC , 16 > { DOECLR31_0_DIO16_W :: new (self) } # [doc = "Bit 17 - Writing 1 to this bit clears the DIO17 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio17 (& mut self) -> DOECLR31_0_DIO17_W < DOECLR31_0_SPEC , 17 > { DOECLR31_0_DIO17_W :: new (self) } # [doc = "Bit 18 - Writing 1 to this bit clears the DIO18 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio18 (& mut self) -> DOECLR31_0_DIO18_W < DOECLR31_0_SPEC , 18 > { DOECLR31_0_DIO18_W :: new (self) } # [doc = "Bit 19 - Writing 1 to this bit clears the DIO19 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio19 (& mut self) -> DOECLR31_0_DIO19_W < DOECLR31_0_SPEC , 19 > { DOECLR31_0_DIO19_W :: new (self) } # [doc = "Bit 20 - Writing 1 to this bit clears the DIO20 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio20 (& mut self) -> DOECLR31_0_DIO20_W < DOECLR31_0_SPEC , 20 > { DOECLR31_0_DIO20_W :: new (self) } # [doc = "Bit 21 - Writing 1 to this bit clears the DIO21 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio21 (& mut self) -> DOECLR31_0_DIO21_W < DOECLR31_0_SPEC , 21 > { DOECLR31_0_DIO21_W :: new (self) } # [doc = "Bit 22 - Writing 1 to this bit clears the DIO22 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio22 (& mut self) -> DOECLR31_0_DIO22_W < DOECLR31_0_SPEC , 22 > { DOECLR31_0_DIO22_W :: new (self) } # [doc = "Bit 23 - Writing 1 to this bit clears the DIO23 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio23 (& mut self) -> DOECLR31_0_DIO23_W < DOECLR31_0_SPEC , 23 > { DOECLR31_0_DIO23_W :: new (self) } # [doc = "Bit 24 - Writing 1 to this bit clears the DIO24 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio24 (& mut self) -> DOECLR31_0_DIO24_W < DOECLR31_0_SPEC , 24 > { DOECLR31_0_DIO24_W :: new (self) } # [doc = "Bit 25 - Writing 1 to this bit clears the DIO25 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio25 (& mut self) -> DOECLR31_0_DIO25_W < DOECLR31_0_SPEC , 25 > { DOECLR31_0_DIO25_W :: new (self) } # [doc = "Bit 26 - Writing 1 to this bit clears the DIO26 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio26 (& mut self) -> DOECLR31_0_DIO26_W < DOECLR31_0_SPEC , 26 > { DOECLR31_0_DIO26_W :: new (self) } # [doc = "Bit 27 - Writing 1 to this bit clears the DIO27 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio27 (& mut self) -> DOECLR31_0_DIO27_W < DOECLR31_0_SPEC , 27 > { DOECLR31_0_DIO27_W :: new (self) } # [doc = "Bit 28 - Writing 1 to this bit clears the DIO28 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio28 (& mut self) -> DOECLR31_0_DIO28_W < DOECLR31_0_SPEC , 28 > { DOECLR31_0_DIO28_W :: new (self) } # [doc = "Bit 29 - Writing 1 to this bit clears the DIO29 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio29 (& mut self) -> DOECLR31_0_DIO29_W < DOECLR31_0_SPEC , 29 > { DOECLR31_0_DIO29_W :: new (self) } # [doc = "Bit 30 - Writing 1 to this bit clears the DIO30 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio30 (& mut self) -> DOECLR31_0_DIO30_W < DOECLR31_0_SPEC , 30 > { DOECLR31_0_DIO30_W :: new (self) } # [doc = "Bit 31 - Writing 1 to this bit clears the DIO31 bit in the DOE31_0 register. Writing 0 has no effect."]
# [inline (always)]
# [must_use]
pub fn doeclr31_0_dio31 (& mut self) -> DOECLR31_0_DIO31_W < DOECLR31_0_SPEC , 31 > { DOECLR31_0_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Data output enable clear 31 to 0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`doeclr31_0::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DOECLR31_0_SPEC ; impl crate :: RegisterSpec for DOECLR31_0_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`doeclr31_0::W`](W) writer structure"]
impl crate :: Writable for DOECLR31_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DOECLR31_0 to value 0"]
impl crate :: Resettable for DOECLR31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN3_0 (r) register accessor: Data input 3 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din3_0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din3_0`]
module"]
pub type DIN3_0 = crate :: Reg < din3_0 :: DIN3_0_SPEC > ; # [doc = "Data input 3 to 0"]
pub mod din3_0 { # [doc = "Register `DIN3_0` reader"]
pub type R = crate :: R < DIN3_0_SPEC > ; # [doc = "Field `DIN3_0_DIO0` reader - This bit reads the data input value of DIO0."]
pub type DIN3_0_DIO0_R = crate :: BitReader < DIN3_0_DIO0_A > ; # [doc = "This bit reads the data input value of DIO0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN3_0_DIO0_A { # [doc = "0: ZERO"]
DIN3_0_DIO0_ZERO = 0 , # [doc = "1: ONE"]
DIN3_0_DIO0_ONE = 1 , } impl From < DIN3_0_DIO0_A > for bool { # [inline (always)]
fn from (variant : DIN3_0_DIO0_A) -> Self { variant as u8 != 0 } } impl DIN3_0_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN3_0_DIO0_A { match self . bits { false => DIN3_0_DIO0_A :: DIN3_0_DIO0_ZERO , true => DIN3_0_DIO0_A :: DIN3_0_DIO0_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din3_0_dio0_zero (& self) -> bool { * self == DIN3_0_DIO0_A :: DIN3_0_DIO0_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din3_0_dio0_one (& self) -> bool { * self == DIN3_0_DIO0_A :: DIN3_0_DIO0_ONE } } # [doc = "Field `DIN3_0_DIO1` reader - This bit reads the data input value of DIO1."]
pub type DIN3_0_DIO1_R = crate :: BitReader < DIN3_0_DIO1_A > ; # [doc = "This bit reads the data input value of DIO1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN3_0_DIO1_A { # [doc = "0: ZERO"]
DIN3_0_DIO1_ZERO = 0 , # [doc = "1: ONE"]
DIN3_0_DIO1_ONE = 1 , } impl From < DIN3_0_DIO1_A > for bool { # [inline (always)]
fn from (variant : DIN3_0_DIO1_A) -> Self { variant as u8 != 0 } } impl DIN3_0_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN3_0_DIO1_A { match self . bits { false => DIN3_0_DIO1_A :: DIN3_0_DIO1_ZERO , true => DIN3_0_DIO1_A :: DIN3_0_DIO1_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din3_0_dio1_zero (& self) -> bool { * self == DIN3_0_DIO1_A :: DIN3_0_DIO1_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din3_0_dio1_one (& self) -> bool { * self == DIN3_0_DIO1_A :: DIN3_0_DIO1_ONE } } # [doc = "Field `DIN3_0_DIO2` reader - This bit reads the data input value of DIO2."]
pub type DIN3_0_DIO2_R = crate :: BitReader < DIN3_0_DIO2_A > ; # [doc = "This bit reads the data input value of DIO2.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN3_0_DIO2_A { # [doc = "0: ZERO"]
DIN3_0_DIO2_ZERO = 0 , # [doc = "1: ONE"]
DIN3_0_DIO2_ONE = 1 , } impl From < DIN3_0_DIO2_A > for bool { # [inline (always)]
fn from (variant : DIN3_0_DIO2_A) -> Self { variant as u8 != 0 } } impl DIN3_0_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN3_0_DIO2_A { match self . bits { false => DIN3_0_DIO2_A :: DIN3_0_DIO2_ZERO , true => DIN3_0_DIO2_A :: DIN3_0_DIO2_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din3_0_dio2_zero (& self) -> bool { * self == DIN3_0_DIO2_A :: DIN3_0_DIO2_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din3_0_dio2_one (& self) -> bool { * self == DIN3_0_DIO2_A :: DIN3_0_DIO2_ONE } } # [doc = "Field `DIN3_0_DIO3` reader - This bit reads the data input value of DIO3."]
pub type DIN3_0_DIO3_R = crate :: BitReader < DIN3_0_DIO3_A > ; # [doc = "This bit reads the data input value of DIO3.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN3_0_DIO3_A { # [doc = "0: ZERO"]
DIN3_0_DIO3_ZERO = 0 , # [doc = "1: ONE"]
DIN3_0_DIO3_ONE = 1 , } impl From < DIN3_0_DIO3_A > for bool { # [inline (always)]
fn from (variant : DIN3_0_DIO3_A) -> Self { variant as u8 != 0 } } impl DIN3_0_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN3_0_DIO3_A { match self . bits { false => DIN3_0_DIO3_A :: DIN3_0_DIO3_ZERO , true => DIN3_0_DIO3_A :: DIN3_0_DIO3_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din3_0_dio3_zero (& self) -> bool { * self == DIN3_0_DIO3_A :: DIN3_0_DIO3_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din3_0_dio3_one (& self) -> bool { * self == DIN3_0_DIO3_A :: DIN3_0_DIO3_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO0."]
# [inline (always)]
pub fn din3_0_dio0 (& self) -> DIN3_0_DIO0_R { DIN3_0_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO1."]
# [inline (always)]
pub fn din3_0_dio1 (& self) -> DIN3_0_DIO1_R { DIN3_0_DIO1_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO2."]
# [inline (always)]
pub fn din3_0_dio2 (& self) -> DIN3_0_DIO2_R { DIN3_0_DIO2_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO3."]
# [inline (always)]
pub fn din3_0_dio3 (& self) -> DIN3_0_DIO3_R { DIN3_0_DIO3_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 3 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din3_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN3_0_SPEC ; impl crate :: RegisterSpec for DIN3_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din3_0::R`](R) reader structure"]
impl crate :: Readable for DIN3_0_SPEC { } # [doc = "`reset()` method sets DIN3_0 to value 0"]
impl crate :: Resettable for DIN3_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN7_4 (r) register accessor: Data input 7 to 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din7_4::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din7_4`]
module"]
pub type DIN7_4 = crate :: Reg < din7_4 :: DIN7_4_SPEC > ; # [doc = "Data input 7 to 4"]
pub mod din7_4 { # [doc = "Register `DIN7_4` reader"]
pub type R = crate :: R < DIN7_4_SPEC > ; # [doc = "Field `DIN7_4_DIO4` reader - This bit reads the data input value of DIO4."]
pub type DIN7_4_DIO4_R = crate :: BitReader < DIN7_4_DIO4_A > ; # [doc = "This bit reads the data input value of DIO4.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN7_4_DIO4_A { # [doc = "0: ZERO"]
DIN7_4_DIO4_ZERO = 0 , # [doc = "1: ONE"]
DIN7_4_DIO4_ONE = 1 , } impl From < DIN7_4_DIO4_A > for bool { # [inline (always)]
fn from (variant : DIN7_4_DIO4_A) -> Self { variant as u8 != 0 } } impl DIN7_4_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN7_4_DIO4_A { match self . bits { false => DIN7_4_DIO4_A :: DIN7_4_DIO4_ZERO , true => DIN7_4_DIO4_A :: DIN7_4_DIO4_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din7_4_dio4_zero (& self) -> bool { * self == DIN7_4_DIO4_A :: DIN7_4_DIO4_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din7_4_dio4_one (& self) -> bool { * self == DIN7_4_DIO4_A :: DIN7_4_DIO4_ONE } } # [doc = "Field `DIN7_4_DIO5` reader - This bit reads the data input value of DIO5."]
pub type DIN7_4_DIO5_R = crate :: BitReader < DIN7_4_DIO5_A > ; # [doc = "This bit reads the data input value of DIO5.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN7_4_DIO5_A { # [doc = "0: ZERO"]
DIN7_4_DIO5_ZERO = 0 , # [doc = "1: ONE"]
DIN7_4_DIO5_ONE = 1 , } impl From < DIN7_4_DIO5_A > for bool { # [inline (always)]
fn from (variant : DIN7_4_DIO5_A) -> Self { variant as u8 != 0 } } impl DIN7_4_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN7_4_DIO5_A { match self . bits { false => DIN7_4_DIO5_A :: DIN7_4_DIO5_ZERO , true => DIN7_4_DIO5_A :: DIN7_4_DIO5_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din7_4_dio5_zero (& self) -> bool { * self == DIN7_4_DIO5_A :: DIN7_4_DIO5_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din7_4_dio5_one (& self) -> bool { * self == DIN7_4_DIO5_A :: DIN7_4_DIO5_ONE } } # [doc = "Field `DIN7_4_DIO6` reader - This bit reads the data input value of DIO6."]
pub type DIN7_4_DIO6_R = crate :: BitReader < DIN7_4_DIO6_A > ; # [doc = "This bit reads the data input value of DIO6.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN7_4_DIO6_A { # [doc = "0: ZERO"]
DIN7_4_DIO6_ZERO = 0 , # [doc = "1: ONE"]
DIN7_4_DIO6_ONE = 1 , } impl From < DIN7_4_DIO6_A > for bool { # [inline (always)]
fn from (variant : DIN7_4_DIO6_A) -> Self { variant as u8 != 0 } } impl DIN7_4_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN7_4_DIO6_A { match self . bits { false => DIN7_4_DIO6_A :: DIN7_4_DIO6_ZERO , true => DIN7_4_DIO6_A :: DIN7_4_DIO6_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din7_4_dio6_zero (& self) -> bool { * self == DIN7_4_DIO6_A :: DIN7_4_DIO6_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din7_4_dio6_one (& self) -> bool { * self == DIN7_4_DIO6_A :: DIN7_4_DIO6_ONE } } # [doc = "Field `DIN7_4_DIO7` reader - This bit reads the data input value of DIO7."]
pub type DIN7_4_DIO7_R = crate :: BitReader < DIN7_4_DIO7_A > ; # [doc = "This bit reads the data input value of DIO7.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN7_4_DIO7_A { # [doc = "0: ZERO"]
DIN7_4_DIO7_ZERO = 0 , # [doc = "1: ONE"]
DIN7_4_DIO7_ONE = 1 , } impl From < DIN7_4_DIO7_A > for bool { # [inline (always)]
fn from (variant : DIN7_4_DIO7_A) -> Self { variant as u8 != 0 } } impl DIN7_4_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN7_4_DIO7_A { match self . bits { false => DIN7_4_DIO7_A :: DIN7_4_DIO7_ZERO , true => DIN7_4_DIO7_A :: DIN7_4_DIO7_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din7_4_dio7_zero (& self) -> bool { * self == DIN7_4_DIO7_A :: DIN7_4_DIO7_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din7_4_dio7_one (& self) -> bool { * self == DIN7_4_DIO7_A :: DIN7_4_DIO7_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO4."]
# [inline (always)]
pub fn din7_4_dio4 (& self) -> DIN7_4_DIO4_R { DIN7_4_DIO4_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO5."]
# [inline (always)]
pub fn din7_4_dio5 (& self) -> DIN7_4_DIO5_R { DIN7_4_DIO5_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO6."]
# [inline (always)]
pub fn din7_4_dio6 (& self) -> DIN7_4_DIO6_R { DIN7_4_DIO6_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO7."]
# [inline (always)]
pub fn din7_4_dio7 (& self) -> DIN7_4_DIO7_R { DIN7_4_DIO7_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 7 to 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din7_4::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN7_4_SPEC ; impl crate :: RegisterSpec for DIN7_4_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din7_4::R`](R) reader structure"]
impl crate :: Readable for DIN7_4_SPEC { } # [doc = "`reset()` method sets DIN7_4 to value 0"]
impl crate :: Resettable for DIN7_4_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN11_8 (r) register accessor: Data input 11 to 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din11_8::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din11_8`]
module"]
pub type DIN11_8 = crate :: Reg < din11_8 :: DIN11_8_SPEC > ; # [doc = "Data input 11 to 8"]
pub mod din11_8 { # [doc = "Register `DIN11_8` reader"]
pub type R = crate :: R < DIN11_8_SPEC > ; # [doc = "Field `DIN11_8_DIO8` reader - This bit reads the data input value of DIO8."]
pub type DIN11_8_DIO8_R = crate :: BitReader < DIN11_8_DIO8_A > ; # [doc = "This bit reads the data input value of DIO8.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN11_8_DIO8_A { # [doc = "0: ZERO"]
DIN11_8_DIO8_ZERO = 0 , # [doc = "1: ONE"]
DIN11_8_DIO8_ONE = 1 , } impl From < DIN11_8_DIO8_A > for bool { # [inline (always)]
fn from (variant : DIN11_8_DIO8_A) -> Self { variant as u8 != 0 } } impl DIN11_8_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN11_8_DIO8_A { match self . bits { false => DIN11_8_DIO8_A :: DIN11_8_DIO8_ZERO , true => DIN11_8_DIO8_A :: DIN11_8_DIO8_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din11_8_dio8_zero (& self) -> bool { * self == DIN11_8_DIO8_A :: DIN11_8_DIO8_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din11_8_dio8_one (& self) -> bool { * self == DIN11_8_DIO8_A :: DIN11_8_DIO8_ONE } } # [doc = "Field `DIN11_8_DIO9` reader - This bit reads the data input value of DIO9."]
pub type DIN11_8_DIO9_R = crate :: BitReader < DIN11_8_DIO9_A > ; # [doc = "This bit reads the data input value of DIO9.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN11_8_DIO9_A { # [doc = "0: ZERO"]
DIN11_8_DIO9_ZERO = 0 , # [doc = "1: ONE"]
DIN11_8_DIO9_ONE = 1 , } impl From < DIN11_8_DIO9_A > for bool { # [inline (always)]
fn from (variant : DIN11_8_DIO9_A) -> Self { variant as u8 != 0 } } impl DIN11_8_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN11_8_DIO9_A { match self . bits { false => DIN11_8_DIO9_A :: DIN11_8_DIO9_ZERO , true => DIN11_8_DIO9_A :: DIN11_8_DIO9_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din11_8_dio9_zero (& self) -> bool { * self == DIN11_8_DIO9_A :: DIN11_8_DIO9_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din11_8_dio9_one (& self) -> bool { * self == DIN11_8_DIO9_A :: DIN11_8_DIO9_ONE } } # [doc = "Field `DIN11_8_DIO10` reader - This bit reads the data input value of DIO10."]
pub type DIN11_8_DIO10_R = crate :: BitReader < DIN11_8_DIO10_A > ; # [doc = "This bit reads the data input value of DIO10.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN11_8_DIO10_A { # [doc = "0: ZERO"]
DIN11_8_DIO10_ZERO = 0 , # [doc = "1: ONE"]
DIN11_8_DIO10_ONE = 1 , } impl From < DIN11_8_DIO10_A > for bool { # [inline (always)]
fn from (variant : DIN11_8_DIO10_A) -> Self { variant as u8 != 0 } } impl DIN11_8_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN11_8_DIO10_A { match self . bits { false => DIN11_8_DIO10_A :: DIN11_8_DIO10_ZERO , true => DIN11_8_DIO10_A :: DIN11_8_DIO10_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din11_8_dio10_zero (& self) -> bool { * self == DIN11_8_DIO10_A :: DIN11_8_DIO10_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din11_8_dio10_one (& self) -> bool { * self == DIN11_8_DIO10_A :: DIN11_8_DIO10_ONE } } # [doc = "Field `DIN11_8_DIO11` reader - This bit reads the data input value of DIO11."]
pub type DIN11_8_DIO11_R = crate :: BitReader < DIN11_8_DIO11_A > ; # [doc = "This bit reads the data input value of DIO11.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN11_8_DIO11_A { # [doc = "0: ZERO"]
DIN11_8_DIO11_ZERO = 0 , # [doc = "1: ONE"]
DIN11_8_DIO11_ONE = 1 , } impl From < DIN11_8_DIO11_A > for bool { # [inline (always)]
fn from (variant : DIN11_8_DIO11_A) -> Self { variant as u8 != 0 } } impl DIN11_8_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN11_8_DIO11_A { match self . bits { false => DIN11_8_DIO11_A :: DIN11_8_DIO11_ZERO , true => DIN11_8_DIO11_A :: DIN11_8_DIO11_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din11_8_dio11_zero (& self) -> bool { * self == DIN11_8_DIO11_A :: DIN11_8_DIO11_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din11_8_dio11_one (& self) -> bool { * self == DIN11_8_DIO11_A :: DIN11_8_DIO11_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO8."]
# [inline (always)]
pub fn din11_8_dio8 (& self) -> DIN11_8_DIO8_R { DIN11_8_DIO8_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO9."]
# [inline (always)]
pub fn din11_8_dio9 (& self) -> DIN11_8_DIO9_R { DIN11_8_DIO9_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO10."]
# [inline (always)]
pub fn din11_8_dio10 (& self) -> DIN11_8_DIO10_R { DIN11_8_DIO10_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO11."]
# [inline (always)]
pub fn din11_8_dio11 (& self) -> DIN11_8_DIO11_R { DIN11_8_DIO11_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 11 to 8\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din11_8::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN11_8_SPEC ; impl crate :: RegisterSpec for DIN11_8_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din11_8::R`](R) reader structure"]
impl crate :: Readable for DIN11_8_SPEC { } # [doc = "`reset()` method sets DIN11_8 to value 0"]
impl crate :: Resettable for DIN11_8_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN15_12 (r) register accessor: Data input 15 to 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din15_12::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din15_12`]
module"]
pub type DIN15_12 = crate :: Reg < din15_12 :: DIN15_12_SPEC > ; # [doc = "Data input 15 to 12"]
pub mod din15_12 { # [doc = "Register `DIN15_12` reader"]
pub type R = crate :: R < DIN15_12_SPEC > ; # [doc = "Field `DIN15_12_DIO12` reader - This bit reads the data input value of DIO12."]
pub type DIN15_12_DIO12_R = crate :: BitReader < DIN15_12_DIO12_A > ; # [doc = "This bit reads the data input value of DIO12.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN15_12_DIO12_A { # [doc = "0: ZERO"]
DIN15_12_DIO12_ZERO = 0 , # [doc = "1: ONE"]
DIN15_12_DIO12_ONE = 1 , } impl From < DIN15_12_DIO12_A > for bool { # [inline (always)]
fn from (variant : DIN15_12_DIO12_A) -> Self { variant as u8 != 0 } } impl DIN15_12_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN15_12_DIO12_A { match self . bits { false => DIN15_12_DIO12_A :: DIN15_12_DIO12_ZERO , true => DIN15_12_DIO12_A :: DIN15_12_DIO12_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din15_12_dio12_zero (& self) -> bool { * self == DIN15_12_DIO12_A :: DIN15_12_DIO12_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din15_12_dio12_one (& self) -> bool { * self == DIN15_12_DIO12_A :: DIN15_12_DIO12_ONE } } # [doc = "Field `DIN15_12_DIO13` reader - This bit reads the data input value of DIO13."]
pub type DIN15_12_DIO13_R = crate :: BitReader < DIN15_12_DIO13_A > ; # [doc = "This bit reads the data input value of DIO13.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN15_12_DIO13_A { # [doc = "0: ZERO"]
DIN15_12_DIO13_ZERO = 0 , # [doc = "1: ONE"]
DIN15_12_DIO13_ONE = 1 , } impl From < DIN15_12_DIO13_A > for bool { # [inline (always)]
fn from (variant : DIN15_12_DIO13_A) -> Self { variant as u8 != 0 } } impl DIN15_12_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN15_12_DIO13_A { match self . bits { false => DIN15_12_DIO13_A :: DIN15_12_DIO13_ZERO , true => DIN15_12_DIO13_A :: DIN15_12_DIO13_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din15_12_dio13_zero (& self) -> bool { * self == DIN15_12_DIO13_A :: DIN15_12_DIO13_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din15_12_dio13_one (& self) -> bool { * self == DIN15_12_DIO13_A :: DIN15_12_DIO13_ONE } } # [doc = "Field `DIN15_12_DIO14` reader - This bit reads the data input value of DIO14."]
pub type DIN15_12_DIO14_R = crate :: BitReader < DIN15_12_DIO14_A > ; # [doc = "This bit reads the data input value of DIO14.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN15_12_DIO14_A { # [doc = "0: ZERO"]
DIN15_12_DIO14_ZERO = 0 , # [doc = "1: ONE"]
DIN15_12_DIO14_ONE = 1 , } impl From < DIN15_12_DIO14_A > for bool { # [inline (always)]
fn from (variant : DIN15_12_DIO14_A) -> Self { variant as u8 != 0 } } impl DIN15_12_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN15_12_DIO14_A { match self . bits { false => DIN15_12_DIO14_A :: DIN15_12_DIO14_ZERO , true => DIN15_12_DIO14_A :: DIN15_12_DIO14_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din15_12_dio14_zero (& self) -> bool { * self == DIN15_12_DIO14_A :: DIN15_12_DIO14_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din15_12_dio14_one (& self) -> bool { * self == DIN15_12_DIO14_A :: DIN15_12_DIO14_ONE } } # [doc = "Field `DIN15_12_DIO15` reader - This bit reads the data input value of DIO15."]
pub type DIN15_12_DIO15_R = crate :: BitReader < DIN15_12_DIO15_A > ; # [doc = "This bit reads the data input value of DIO15.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN15_12_DIO15_A { # [doc = "0: ZERO"]
DIN15_12_DIO15_ZERO = 0 , # [doc = "1: ONE"]
DIN15_12_DIO15_ONE = 1 , } impl From < DIN15_12_DIO15_A > for bool { # [inline (always)]
fn from (variant : DIN15_12_DIO15_A) -> Self { variant as u8 != 0 } } impl DIN15_12_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN15_12_DIO15_A { match self . bits { false => DIN15_12_DIO15_A :: DIN15_12_DIO15_ZERO , true => DIN15_12_DIO15_A :: DIN15_12_DIO15_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din15_12_dio15_zero (& self) -> bool { * self == DIN15_12_DIO15_A :: DIN15_12_DIO15_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din15_12_dio15_one (& self) -> bool { * self == DIN15_12_DIO15_A :: DIN15_12_DIO15_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO12."]
# [inline (always)]
pub fn din15_12_dio12 (& self) -> DIN15_12_DIO12_R { DIN15_12_DIO12_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO13."]
# [inline (always)]
pub fn din15_12_dio13 (& self) -> DIN15_12_DIO13_R { DIN15_12_DIO13_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO14."]
# [inline (always)]
pub fn din15_12_dio14 (& self) -> DIN15_12_DIO14_R { DIN15_12_DIO14_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO15."]
# [inline (always)]
pub fn din15_12_dio15 (& self) -> DIN15_12_DIO15_R { DIN15_12_DIO15_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 15 to 12\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din15_12::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN15_12_SPEC ; impl crate :: RegisterSpec for DIN15_12_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din15_12::R`](R) reader structure"]
impl crate :: Readable for DIN15_12_SPEC { } # [doc = "`reset()` method sets DIN15_12 to value 0"]
impl crate :: Resettable for DIN15_12_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN19_16 (r) register accessor: Data input 19 to 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din19_16::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din19_16`]
module"]
pub type DIN19_16 = crate :: Reg < din19_16 :: DIN19_16_SPEC > ; # [doc = "Data input 19 to 16"]
pub mod din19_16 { # [doc = "Register `DIN19_16` reader"]
pub type R = crate :: R < DIN19_16_SPEC > ; # [doc = "Field `DIN19_16_DIO16` reader - This bit reads the data input value of DIO16."]
pub type DIN19_16_DIO16_R = crate :: BitReader < DIN19_16_DIO16_A > ; # [doc = "This bit reads the data input value of DIO16.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN19_16_DIO16_A { # [doc = "0: ZERO"]
DIN19_16_DIO16_ZERO = 0 , # [doc = "1: ONE"]
DIN19_16_DIO16_ONE = 1 , } impl From < DIN19_16_DIO16_A > for bool { # [inline (always)]
fn from (variant : DIN19_16_DIO16_A) -> Self { variant as u8 != 0 } } impl DIN19_16_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN19_16_DIO16_A { match self . bits { false => DIN19_16_DIO16_A :: DIN19_16_DIO16_ZERO , true => DIN19_16_DIO16_A :: DIN19_16_DIO16_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din19_16_dio16_zero (& self) -> bool { * self == DIN19_16_DIO16_A :: DIN19_16_DIO16_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din19_16_dio16_one (& self) -> bool { * self == DIN19_16_DIO16_A :: DIN19_16_DIO16_ONE } } # [doc = "Field `DIN19_16_DIO17` reader - This bit reads the data input value of DIO17."]
pub type DIN19_16_DIO17_R = crate :: BitReader < DIN19_16_DIO17_A > ; # [doc = "This bit reads the data input value of DIO17.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN19_16_DIO17_A { # [doc = "0: ZERO"]
DIN19_16_DIO17_ZERO = 0 , # [doc = "1: ONE"]
DIN19_16_DIO17_ONE = 1 , } impl From < DIN19_16_DIO17_A > for bool { # [inline (always)]
fn from (variant : DIN19_16_DIO17_A) -> Self { variant as u8 != 0 } } impl DIN19_16_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN19_16_DIO17_A { match self . bits { false => DIN19_16_DIO17_A :: DIN19_16_DIO17_ZERO , true => DIN19_16_DIO17_A :: DIN19_16_DIO17_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din19_16_dio17_zero (& self) -> bool { * self == DIN19_16_DIO17_A :: DIN19_16_DIO17_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din19_16_dio17_one (& self) -> bool { * self == DIN19_16_DIO17_A :: DIN19_16_DIO17_ONE } } # [doc = "Field `DIN19_16_DIO18` reader - This bit reads the data input value of DIO18."]
pub type DIN19_16_DIO18_R = crate :: BitReader < DIN19_16_DIO18_A > ; # [doc = "This bit reads the data input value of DIO18.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN19_16_DIO18_A { # [doc = "0: ZERO"]
DIN19_16_DIO18_ZERO = 0 , # [doc = "1: ONE"]
DIN19_16_DIO18_ONE = 1 , } impl From < DIN19_16_DIO18_A > for bool { # [inline (always)]
fn from (variant : DIN19_16_DIO18_A) -> Self { variant as u8 != 0 } } impl DIN19_16_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN19_16_DIO18_A { match self . bits { false => DIN19_16_DIO18_A :: DIN19_16_DIO18_ZERO , true => DIN19_16_DIO18_A :: DIN19_16_DIO18_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din19_16_dio18_zero (& self) -> bool { * self == DIN19_16_DIO18_A :: DIN19_16_DIO18_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din19_16_dio18_one (& self) -> bool { * self == DIN19_16_DIO18_A :: DIN19_16_DIO18_ONE } } # [doc = "Field `DIN19_16_DIO19` reader - This bit reads the data input value of DIO19."]
pub type DIN19_16_DIO19_R = crate :: BitReader < DIN19_16_DIO19_A > ; # [doc = "This bit reads the data input value of DIO19.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN19_16_DIO19_A { # [doc = "0: ZERO"]
DIN19_16_DIO19_ZERO = 0 , # [doc = "1: ONE"]
DIN19_16_DIO19_ONE = 1 , } impl From < DIN19_16_DIO19_A > for bool { # [inline (always)]
fn from (variant : DIN19_16_DIO19_A) -> Self { variant as u8 != 0 } } impl DIN19_16_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN19_16_DIO19_A { match self . bits { false => DIN19_16_DIO19_A :: DIN19_16_DIO19_ZERO , true => DIN19_16_DIO19_A :: DIN19_16_DIO19_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din19_16_dio19_zero (& self) -> bool { * self == DIN19_16_DIO19_A :: DIN19_16_DIO19_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din19_16_dio19_one (& self) -> bool { * self == DIN19_16_DIO19_A :: DIN19_16_DIO19_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO16."]
# [inline (always)]
pub fn din19_16_dio16 (& self) -> DIN19_16_DIO16_R { DIN19_16_DIO16_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO17."]
# [inline (always)]
pub fn din19_16_dio17 (& self) -> DIN19_16_DIO17_R { DIN19_16_DIO17_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO18."]
# [inline (always)]
pub fn din19_16_dio18 (& self) -> DIN19_16_DIO18_R { DIN19_16_DIO18_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO19."]
# [inline (always)]
pub fn din19_16_dio19 (& self) -> DIN19_16_DIO19_R { DIN19_16_DIO19_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 19 to 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din19_16::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN19_16_SPEC ; impl crate :: RegisterSpec for DIN19_16_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din19_16::R`](R) reader structure"]
impl crate :: Readable for DIN19_16_SPEC { } # [doc = "`reset()` method sets DIN19_16 to value 0"]
impl crate :: Resettable for DIN19_16_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN23_20 (r) register accessor: Data input 23 to 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din23_20::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din23_20`]
module"]
pub type DIN23_20 = crate :: Reg < din23_20 :: DIN23_20_SPEC > ; # [doc = "Data input 23 to 20"]
pub mod din23_20 { # [doc = "Register `DIN23_20` reader"]
pub type R = crate :: R < DIN23_20_SPEC > ; # [doc = "Field `DIN23_20_DIO20` reader - This bit reads the data input value of DIO20."]
pub type DIN23_20_DIO20_R = crate :: BitReader < DIN23_20_DIO20_A > ; # [doc = "This bit reads the data input value of DIO20.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN23_20_DIO20_A { # [doc = "0: ZERO"]
DIN23_20_DIO20_ZERO = 0 , # [doc = "1: ONE"]
DIN23_20_DIO20_ONE = 1 , } impl From < DIN23_20_DIO20_A > for bool { # [inline (always)]
fn from (variant : DIN23_20_DIO20_A) -> Self { variant as u8 != 0 } } impl DIN23_20_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN23_20_DIO20_A { match self . bits { false => DIN23_20_DIO20_A :: DIN23_20_DIO20_ZERO , true => DIN23_20_DIO20_A :: DIN23_20_DIO20_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din23_20_dio20_zero (& self) -> bool { * self == DIN23_20_DIO20_A :: DIN23_20_DIO20_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din23_20_dio20_one (& self) -> bool { * self == DIN23_20_DIO20_A :: DIN23_20_DIO20_ONE } } # [doc = "Field `DIN23_20_DIO21` reader - This bit reads the data input value of DIO21."]
pub type DIN23_20_DIO21_R = crate :: BitReader < DIN23_20_DIO21_A > ; # [doc = "This bit reads the data input value of DIO21.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN23_20_DIO21_A { # [doc = "0: ZERO"]
DIN23_20_DIO21_ZERO = 0 , # [doc = "1: ONE"]
DIN23_20_DIO21_ONE = 1 , } impl From < DIN23_20_DIO21_A > for bool { # [inline (always)]
fn from (variant : DIN23_20_DIO21_A) -> Self { variant as u8 != 0 } } impl DIN23_20_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN23_20_DIO21_A { match self . bits { false => DIN23_20_DIO21_A :: DIN23_20_DIO21_ZERO , true => DIN23_20_DIO21_A :: DIN23_20_DIO21_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din23_20_dio21_zero (& self) -> bool { * self == DIN23_20_DIO21_A :: DIN23_20_DIO21_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din23_20_dio21_one (& self) -> bool { * self == DIN23_20_DIO21_A :: DIN23_20_DIO21_ONE } } # [doc = "Field `DIN23_20_DIO22` reader - This bit reads the data input value of DIO22."]
pub type DIN23_20_DIO22_R = crate :: BitReader < DIN23_20_DIO22_A > ; # [doc = "This bit reads the data input value of DIO22.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN23_20_DIO22_A { # [doc = "0: ZERO"]
DIN23_20_DIO22_ZERO = 0 , # [doc = "1: ONE"]
DIN23_20_DIO22_ONE = 1 , } impl From < DIN23_20_DIO22_A > for bool { # [inline (always)]
fn from (variant : DIN23_20_DIO22_A) -> Self { variant as u8 != 0 } } impl DIN23_20_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN23_20_DIO22_A { match self . bits { false => DIN23_20_DIO22_A :: DIN23_20_DIO22_ZERO , true => DIN23_20_DIO22_A :: DIN23_20_DIO22_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din23_20_dio22_zero (& self) -> bool { * self == DIN23_20_DIO22_A :: DIN23_20_DIO22_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din23_20_dio22_one (& self) -> bool { * self == DIN23_20_DIO22_A :: DIN23_20_DIO22_ONE } } # [doc = "Field `DIN23_20_DIO23` reader - This bit reads the data input value of DIO23."]
pub type DIN23_20_DIO23_R = crate :: BitReader < DIN23_20_DIO23_A > ; # [doc = "This bit reads the data input value of DIO23.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN23_20_DIO23_A { # [doc = "0: ZERO"]
DIN23_20_DIO23_ZERO = 0 , # [doc = "1: ONE"]
DIN23_20_DIO23_ONE = 1 , } impl From < DIN23_20_DIO23_A > for bool { # [inline (always)]
fn from (variant : DIN23_20_DIO23_A) -> Self { variant as u8 != 0 } } impl DIN23_20_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN23_20_DIO23_A { match self . bits { false => DIN23_20_DIO23_A :: DIN23_20_DIO23_ZERO , true => DIN23_20_DIO23_A :: DIN23_20_DIO23_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din23_20_dio23_zero (& self) -> bool { * self == DIN23_20_DIO23_A :: DIN23_20_DIO23_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din23_20_dio23_one (& self) -> bool { * self == DIN23_20_DIO23_A :: DIN23_20_DIO23_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO20."]
# [inline (always)]
pub fn din23_20_dio20 (& self) -> DIN23_20_DIO20_R { DIN23_20_DIO20_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO21."]
# [inline (always)]
pub fn din23_20_dio21 (& self) -> DIN23_20_DIO21_R { DIN23_20_DIO21_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO22."]
# [inline (always)]
pub fn din23_20_dio22 (& self) -> DIN23_20_DIO22_R { DIN23_20_DIO22_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO23."]
# [inline (always)]
pub fn din23_20_dio23 (& self) -> DIN23_20_DIO23_R { DIN23_20_DIO23_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 23 to 20\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din23_20::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN23_20_SPEC ; impl crate :: RegisterSpec for DIN23_20_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din23_20::R`](R) reader structure"]
impl crate :: Readable for DIN23_20_SPEC { } # [doc = "`reset()` method sets DIN23_20 to value 0"]
impl crate :: Resettable for DIN23_20_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN27_24 (r) register accessor: Data input 27 to 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din27_24::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din27_24`]
module"]
pub type DIN27_24 = crate :: Reg < din27_24 :: DIN27_24_SPEC > ; # [doc = "Data input 27 to 24"]
pub mod din27_24 { # [doc = "Register `DIN27_24` reader"]
pub type R = crate :: R < DIN27_24_SPEC > ; # [doc = "Field `DIN27_24_DIO24` reader - This bit reads the data input value of DIO24."]
pub type DIN27_24_DIO24_R = crate :: BitReader < DIN27_24_DIO24_A > ; # [doc = "This bit reads the data input value of DIO24.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN27_24_DIO24_A { # [doc = "0: ZERO"]
DIN27_24_DIO24_ZERO = 0 , # [doc = "1: ONE"]
DIN27_24_DIO24_ONE = 1 , } impl From < DIN27_24_DIO24_A > for bool { # [inline (always)]
fn from (variant : DIN27_24_DIO24_A) -> Self { variant as u8 != 0 } } impl DIN27_24_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN27_24_DIO24_A { match self . bits { false => DIN27_24_DIO24_A :: DIN27_24_DIO24_ZERO , true => DIN27_24_DIO24_A :: DIN27_24_DIO24_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din27_24_dio24_zero (& self) -> bool { * self == DIN27_24_DIO24_A :: DIN27_24_DIO24_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din27_24_dio24_one (& self) -> bool { * self == DIN27_24_DIO24_A :: DIN27_24_DIO24_ONE } } # [doc = "Field `DIN27_24_DIO25` reader - This bit reads the data input value of DIO25."]
pub type DIN27_24_DIO25_R = crate :: BitReader < DIN27_24_DIO25_A > ; # [doc = "This bit reads the data input value of DIO25.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN27_24_DIO25_A { # [doc = "0: ZERO"]
DIN27_24_DIO25_ZERO = 0 , # [doc = "1: ONE"]
DIN27_24_DIO25_ONE = 1 , } impl From < DIN27_24_DIO25_A > for bool { # [inline (always)]
fn from (variant : DIN27_24_DIO25_A) -> Self { variant as u8 != 0 } } impl DIN27_24_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN27_24_DIO25_A { match self . bits { false => DIN27_24_DIO25_A :: DIN27_24_DIO25_ZERO , true => DIN27_24_DIO25_A :: DIN27_24_DIO25_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din27_24_dio25_zero (& self) -> bool { * self == DIN27_24_DIO25_A :: DIN27_24_DIO25_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din27_24_dio25_one (& self) -> bool { * self == DIN27_24_DIO25_A :: DIN27_24_DIO25_ONE } } # [doc = "Field `DIN27_24_DIO26` reader - This bit reads the data input value of DIO26."]
pub type DIN27_24_DIO26_R = crate :: BitReader < DIN27_24_DIO26_A > ; # [doc = "This bit reads the data input value of DIO26.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN27_24_DIO26_A { # [doc = "0: ZERO"]
DIN27_24_DIO26_ZERO = 0 , # [doc = "1: ONE"]
DIN27_24_DIO26_ONE = 1 , } impl From < DIN27_24_DIO26_A > for bool { # [inline (always)]
fn from (variant : DIN27_24_DIO26_A) -> Self { variant as u8 != 0 } } impl DIN27_24_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN27_24_DIO26_A { match self . bits { false => DIN27_24_DIO26_A :: DIN27_24_DIO26_ZERO , true => DIN27_24_DIO26_A :: DIN27_24_DIO26_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din27_24_dio26_zero (& self) -> bool { * self == DIN27_24_DIO26_A :: DIN27_24_DIO26_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din27_24_dio26_one (& self) -> bool { * self == DIN27_24_DIO26_A :: DIN27_24_DIO26_ONE } } # [doc = "Field `DIN27_24_DIO27` reader - This bit reads the data input value of DIO27."]
pub type DIN27_24_DIO27_R = crate :: BitReader < DIN27_24_DIO27_A > ; # [doc = "This bit reads the data input value of DIO27.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN27_24_DIO27_A { # [doc = "0: ZERO"]
DIN27_24_DIO27_ZERO = 0 , # [doc = "1: ONE"]
DIN27_24_DIO27_ONE = 1 , } impl From < DIN27_24_DIO27_A > for bool { # [inline (always)]
fn from (variant : DIN27_24_DIO27_A) -> Self { variant as u8 != 0 } } impl DIN27_24_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN27_24_DIO27_A { match self . bits { false => DIN27_24_DIO27_A :: DIN27_24_DIO27_ZERO , true => DIN27_24_DIO27_A :: DIN27_24_DIO27_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din27_24_dio27_zero (& self) -> bool { * self == DIN27_24_DIO27_A :: DIN27_24_DIO27_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din27_24_dio27_one (& self) -> bool { * self == DIN27_24_DIO27_A :: DIN27_24_DIO27_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO24."]
# [inline (always)]
pub fn din27_24_dio24 (& self) -> DIN27_24_DIO24_R { DIN27_24_DIO24_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO25."]
# [inline (always)]
pub fn din27_24_dio25 (& self) -> DIN27_24_DIO25_R { DIN27_24_DIO25_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO26."]
# [inline (always)]
pub fn din27_24_dio26 (& self) -> DIN27_24_DIO26_R { DIN27_24_DIO26_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO27."]
# [inline (always)]
pub fn din27_24_dio27 (& self) -> DIN27_24_DIO27_R { DIN27_24_DIO27_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 27 to 24\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din27_24::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN27_24_SPEC ; impl crate :: RegisterSpec for DIN27_24_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din27_24::R`](R) reader structure"]
impl crate :: Readable for DIN27_24_SPEC { } # [doc = "`reset()` method sets DIN27_24 to value 0"]
impl crate :: Resettable for DIN27_24_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN31_28 (r) register accessor: Data input 31 to 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din31_28::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din31_28`]
module"]
pub type DIN31_28 = crate :: Reg < din31_28 :: DIN31_28_SPEC > ; # [doc = "Data input 31 to 28"]
pub mod din31_28 { # [doc = "Register `DIN31_28` reader"]
pub type R = crate :: R < DIN31_28_SPEC > ; # [doc = "Field `DIN31_28_DIO28` reader - This bit reads the data input value of DIO28."]
pub type DIN31_28_DIO28_R = crate :: BitReader < DIN31_28_DIO28_A > ; # [doc = "This bit reads the data input value of DIO28.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_28_DIO28_A { # [doc = "0: ZERO"]
DIN31_28_DIO28_ZERO = 0 , # [doc = "1: ONE"]
DIN31_28_DIO28_ONE = 1 , } impl From < DIN31_28_DIO28_A > for bool { # [inline (always)]
fn from (variant : DIN31_28_DIO28_A) -> Self { variant as u8 != 0 } } impl DIN31_28_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_28_DIO28_A { match self . bits { false => DIN31_28_DIO28_A :: DIN31_28_DIO28_ZERO , true => DIN31_28_DIO28_A :: DIN31_28_DIO28_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_28_dio28_zero (& self) -> bool { * self == DIN31_28_DIO28_A :: DIN31_28_DIO28_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_28_dio28_one (& self) -> bool { * self == DIN31_28_DIO28_A :: DIN31_28_DIO28_ONE } } # [doc = "Field `DIN31_28_DIO29` reader - This bit reads the data input value of DIO29."]
pub type DIN31_28_DIO29_R = crate :: BitReader < DIN31_28_DIO29_A > ; # [doc = "This bit reads the data input value of DIO29.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_28_DIO29_A { # [doc = "0: ZERO"]
DIN31_28_DIO29_ZERO = 0 , # [doc = "1: ONE"]
DIN31_28_DIO29_ONE = 1 , } impl From < DIN31_28_DIO29_A > for bool { # [inline (always)]
fn from (variant : DIN31_28_DIO29_A) -> Self { variant as u8 != 0 } } impl DIN31_28_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_28_DIO29_A { match self . bits { false => DIN31_28_DIO29_A :: DIN31_28_DIO29_ZERO , true => DIN31_28_DIO29_A :: DIN31_28_DIO29_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_28_dio29_zero (& self) -> bool { * self == DIN31_28_DIO29_A :: DIN31_28_DIO29_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_28_dio29_one (& self) -> bool { * self == DIN31_28_DIO29_A :: DIN31_28_DIO29_ONE } } # [doc = "Field `DIN31_28_DIO30` reader - This bit reads the data input value of DIO30."]
pub type DIN31_28_DIO30_R = crate :: BitReader < DIN31_28_DIO30_A > ; # [doc = "This bit reads the data input value of DIO30.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_28_DIO30_A { # [doc = "0: ZERO"]
DIN31_28_DIO30_ZERO = 0 , # [doc = "1: ONE"]
DIN31_28_DIO30_ONE = 1 , } impl From < DIN31_28_DIO30_A > for bool { # [inline (always)]
fn from (variant : DIN31_28_DIO30_A) -> Self { variant as u8 != 0 } } impl DIN31_28_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_28_DIO30_A { match self . bits { false => DIN31_28_DIO30_A :: DIN31_28_DIO30_ZERO , true => DIN31_28_DIO30_A :: DIN31_28_DIO30_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_28_dio30_zero (& self) -> bool { * self == DIN31_28_DIO30_A :: DIN31_28_DIO30_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_28_dio30_one (& self) -> bool { * self == DIN31_28_DIO30_A :: DIN31_28_DIO30_ONE } } # [doc = "Field `DIN31_28_DIO31` reader - This bit reads the data input value of DIO31."]
pub type DIN31_28_DIO31_R = crate :: BitReader < DIN31_28_DIO31_A > ; # [doc = "This bit reads the data input value of DIO31.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_28_DIO31_A { # [doc = "0: ZERO"]
DIN31_28_DIO31_ZERO = 0 , # [doc = "1: ONE"]
DIN31_28_DIO31_ONE = 1 , } impl From < DIN31_28_DIO31_A > for bool { # [inline (always)]
fn from (variant : DIN31_28_DIO31_A) -> Self { variant as u8 != 0 } } impl DIN31_28_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_28_DIO31_A { match self . bits { false => DIN31_28_DIO31_A :: DIN31_28_DIO31_ZERO , true => DIN31_28_DIO31_A :: DIN31_28_DIO31_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_28_dio31_zero (& self) -> bool { * self == DIN31_28_DIO31_A :: DIN31_28_DIO31_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_28_dio31_one (& self) -> bool { * self == DIN31_28_DIO31_A :: DIN31_28_DIO31_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO28."]
# [inline (always)]
pub fn din31_28_dio28 (& self) -> DIN31_28_DIO28_R { DIN31_28_DIO28_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO29."]
# [inline (always)]
pub fn din31_28_dio29 (& self) -> DIN31_28_DIO29_R { DIN31_28_DIO29_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO30."]
# [inline (always)]
pub fn din31_28_dio30 (& self) -> DIN31_28_DIO30_R { DIN31_28_DIO30_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO31."]
# [inline (always)]
pub fn din31_28_dio31 (& self) -> DIN31_28_DIO31_R { DIN31_28_DIO31_R :: new (((self . bits >> 24) & 1) != 0) } } # [doc = "Data input 31 to 28\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din31_28::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN31_28_SPEC ; impl crate :: RegisterSpec for DIN31_28_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din31_28::R`](R) reader structure"]
impl crate :: Readable for DIN31_28_SPEC { } # [doc = "`reset()` method sets DIN31_28 to value 0"]
impl crate :: Resettable for DIN31_28_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DIN31_0 (r) register accessor: Data input 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din31_0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@din31_0`]
module"]
pub type DIN31_0 = crate :: Reg < din31_0 :: DIN31_0_SPEC > ; # [doc = "Data input 31 to 0"]
pub mod din31_0 { # [doc = "Register `DIN31_0` reader"]
pub type R = crate :: R < DIN31_0_SPEC > ; # [doc = "Field `DIN31_0_DIO0` reader - This bit reads the data input value of DIO0."]
pub type DIN31_0_DIO0_R = crate :: BitReader < DIN31_0_DIO0_A > ; # [doc = "This bit reads the data input value of DIO0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO0_A { # [doc = "0: ZERO"]
DIN31_0_DIO0_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO0_ONE = 1 , } impl From < DIN31_0_DIO0_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO0_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO0_A { match self . bits { false => DIN31_0_DIO0_A :: DIN31_0_DIO0_ZERO , true => DIN31_0_DIO0_A :: DIN31_0_DIO0_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio0_zero (& self) -> bool { * self == DIN31_0_DIO0_A :: DIN31_0_DIO0_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio0_one (& self) -> bool { * self == DIN31_0_DIO0_A :: DIN31_0_DIO0_ONE } } # [doc = "Field `DIN31_0_DIO1` reader - This bit reads the data input value of DIO1."]
pub type DIN31_0_DIO1_R = crate :: BitReader < DIN31_0_DIO1_A > ; # [doc = "This bit reads the data input value of DIO1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO1_A { # [doc = "0: ZERO"]
DIN31_0_DIO1_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO1_ONE = 1 , } impl From < DIN31_0_DIO1_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO1_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO1_A { match self . bits { false => DIN31_0_DIO1_A :: DIN31_0_DIO1_ZERO , true => DIN31_0_DIO1_A :: DIN31_0_DIO1_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio1_zero (& self) -> bool { * self == DIN31_0_DIO1_A :: DIN31_0_DIO1_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio1_one (& self) -> bool { * self == DIN31_0_DIO1_A :: DIN31_0_DIO1_ONE } } # [doc = "Field `DIN31_0_DIO2` reader - This bit reads the data input value of DIO2."]
pub type DIN31_0_DIO2_R = crate :: BitReader < DIN31_0_DIO2_A > ; # [doc = "This bit reads the data input value of DIO2.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO2_A { # [doc = "0: ZERO"]
DIN31_0_DIO2_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO2_ONE = 1 , } impl From < DIN31_0_DIO2_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO2_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO2_A { match self . bits { false => DIN31_0_DIO2_A :: DIN31_0_DIO2_ZERO , true => DIN31_0_DIO2_A :: DIN31_0_DIO2_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio2_zero (& self) -> bool { * self == DIN31_0_DIO2_A :: DIN31_0_DIO2_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio2_one (& self) -> bool { * self == DIN31_0_DIO2_A :: DIN31_0_DIO2_ONE } } # [doc = "Field `DIN31_0_DIO3` reader - This bit reads the data input value of DIO3."]
pub type DIN31_0_DIO3_R = crate :: BitReader < DIN31_0_DIO3_A > ; # [doc = "This bit reads the data input value of DIO3.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO3_A { # [doc = "0: ZERO"]
DIN31_0_DIO3_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO3_ONE = 1 , } impl From < DIN31_0_DIO3_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO3_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO3_A { match self . bits { false => DIN31_0_DIO3_A :: DIN31_0_DIO3_ZERO , true => DIN31_0_DIO3_A :: DIN31_0_DIO3_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio3_zero (& self) -> bool { * self == DIN31_0_DIO3_A :: DIN31_0_DIO3_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio3_one (& self) -> bool { * self == DIN31_0_DIO3_A :: DIN31_0_DIO3_ONE } } # [doc = "Field `DIN31_0_DIO4` reader - This bit reads the data input value of DIO4."]
pub type DIN31_0_DIO4_R = crate :: BitReader < DIN31_0_DIO4_A > ; # [doc = "This bit reads the data input value of DIO4.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO4_A { # [doc = "0: ZERO"]
DIN31_0_DIO4_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO4_ONE = 1 , } impl From < DIN31_0_DIO4_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO4_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO4_A { match self . bits { false => DIN31_0_DIO4_A :: DIN31_0_DIO4_ZERO , true => DIN31_0_DIO4_A :: DIN31_0_DIO4_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio4_zero (& self) -> bool { * self == DIN31_0_DIO4_A :: DIN31_0_DIO4_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio4_one (& self) -> bool { * self == DIN31_0_DIO4_A :: DIN31_0_DIO4_ONE } } # [doc = "Field `DIN31_0_DIO5` reader - This bit reads the data input value of DIO5."]
pub type DIN31_0_DIO5_R = crate :: BitReader < DIN31_0_DIO5_A > ; # [doc = "This bit reads the data input value of DIO5.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO5_A { # [doc = "0: ZERO"]
DIN31_0_DIO5_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO5_ONE = 1 , } impl From < DIN31_0_DIO5_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO5_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO5_A { match self . bits { false => DIN31_0_DIO5_A :: DIN31_0_DIO5_ZERO , true => DIN31_0_DIO5_A :: DIN31_0_DIO5_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio5_zero (& self) -> bool { * self == DIN31_0_DIO5_A :: DIN31_0_DIO5_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio5_one (& self) -> bool { * self == DIN31_0_DIO5_A :: DIN31_0_DIO5_ONE } } # [doc = "Field `DIN31_0_DIO6` reader - This bit reads the data input value of DIO6."]
pub type DIN31_0_DIO6_R = crate :: BitReader < DIN31_0_DIO6_A > ; # [doc = "This bit reads the data input value of DIO6.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO6_A { # [doc = "0: ZERO"]
DIN31_0_DIO6_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO6_ONE = 1 , } impl From < DIN31_0_DIO6_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO6_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO6_A { match self . bits { false => DIN31_0_DIO6_A :: DIN31_0_DIO6_ZERO , true => DIN31_0_DIO6_A :: DIN31_0_DIO6_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio6_zero (& self) -> bool { * self == DIN31_0_DIO6_A :: DIN31_0_DIO6_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio6_one (& self) -> bool { * self == DIN31_0_DIO6_A :: DIN31_0_DIO6_ONE } } # [doc = "Field `DIN31_0_DIO7` reader - This bit reads the data input value of DIO7."]
pub type DIN31_0_DIO7_R = crate :: BitReader < DIN31_0_DIO7_A > ; # [doc = "This bit reads the data input value of DIO7.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO7_A { # [doc = "0: ZERO"]
DIN31_0_DIO7_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO7_ONE = 1 , } impl From < DIN31_0_DIO7_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO7_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO7_A { match self . bits { false => DIN31_0_DIO7_A :: DIN31_0_DIO7_ZERO , true => DIN31_0_DIO7_A :: DIN31_0_DIO7_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio7_zero (& self) -> bool { * self == DIN31_0_DIO7_A :: DIN31_0_DIO7_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio7_one (& self) -> bool { * self == DIN31_0_DIO7_A :: DIN31_0_DIO7_ONE } } # [doc = "Field `DIN31_0_DIO8` reader - This bit reads the data input value of DIO8."]
pub type DIN31_0_DIO8_R = crate :: BitReader < DIN31_0_DIO8_A > ; # [doc = "This bit reads the data input value of DIO8.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO8_A { # [doc = "0: ZERO"]
DIN31_0_DIO8_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO8_ONE = 1 , } impl From < DIN31_0_DIO8_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO8_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO8_A { match self . bits { false => DIN31_0_DIO8_A :: DIN31_0_DIO8_ZERO , true => DIN31_0_DIO8_A :: DIN31_0_DIO8_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio8_zero (& self) -> bool { * self == DIN31_0_DIO8_A :: DIN31_0_DIO8_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio8_one (& self) -> bool { * self == DIN31_0_DIO8_A :: DIN31_0_DIO8_ONE } } # [doc = "Field `DIN31_0_DIO9` reader - This bit reads the data input value of DIO9."]
pub type DIN31_0_DIO9_R = crate :: BitReader < DIN31_0_DIO9_A > ; # [doc = "This bit reads the data input value of DIO9.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO9_A { # [doc = "0: ZERO"]
DIN31_0_DIO9_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO9_ONE = 1 , } impl From < DIN31_0_DIO9_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO9_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO9_A { match self . bits { false => DIN31_0_DIO9_A :: DIN31_0_DIO9_ZERO , true => DIN31_0_DIO9_A :: DIN31_0_DIO9_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio9_zero (& self) -> bool { * self == DIN31_0_DIO9_A :: DIN31_0_DIO9_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio9_one (& self) -> bool { * self == DIN31_0_DIO9_A :: DIN31_0_DIO9_ONE } } # [doc = "Field `DIN31_0_DIO10` reader - This bit reads the data input value of DIO10."]
pub type DIN31_0_DIO10_R = crate :: BitReader < DIN31_0_DIO10_A > ; # [doc = "This bit reads the data input value of DIO10.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO10_A { # [doc = "0: ZERO"]
DIN31_0_DIO10_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO10_ONE = 1 , } impl From < DIN31_0_DIO10_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO10_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO10_A { match self . bits { false => DIN31_0_DIO10_A :: DIN31_0_DIO10_ZERO , true => DIN31_0_DIO10_A :: DIN31_0_DIO10_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio10_zero (& self) -> bool { * self == DIN31_0_DIO10_A :: DIN31_0_DIO10_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio10_one (& self) -> bool { * self == DIN31_0_DIO10_A :: DIN31_0_DIO10_ONE } } # [doc = "Field `DIN31_0_DIO11` reader - This bit reads the data input value of DIO11."]
pub type DIN31_0_DIO11_R = crate :: BitReader < DIN31_0_DIO11_A > ; # [doc = "This bit reads the data input value of DIO11.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO11_A { # [doc = "0: ZERO"]
DIN31_0_DIO11_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO11_ONE = 1 , } impl From < DIN31_0_DIO11_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO11_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO11_A { match self . bits { false => DIN31_0_DIO11_A :: DIN31_0_DIO11_ZERO , true => DIN31_0_DIO11_A :: DIN31_0_DIO11_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio11_zero (& self) -> bool { * self == DIN31_0_DIO11_A :: DIN31_0_DIO11_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio11_one (& self) -> bool { * self == DIN31_0_DIO11_A :: DIN31_0_DIO11_ONE } } # [doc = "Field `DIN31_0_DIO12` reader - This bit reads the data input value of DIO12."]
pub type DIN31_0_DIO12_R = crate :: BitReader < DIN31_0_DIO12_A > ; # [doc = "This bit reads the data input value of DIO12.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO12_A { # [doc = "0: ZERO"]
DIN31_0_DIO12_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO12_ONE = 1 , } impl From < DIN31_0_DIO12_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO12_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO12_A { match self . bits { false => DIN31_0_DIO12_A :: DIN31_0_DIO12_ZERO , true => DIN31_0_DIO12_A :: DIN31_0_DIO12_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio12_zero (& self) -> bool { * self == DIN31_0_DIO12_A :: DIN31_0_DIO12_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio12_one (& self) -> bool { * self == DIN31_0_DIO12_A :: DIN31_0_DIO12_ONE } } # [doc = "Field `DIN31_0_DIO13` reader - This bit reads the data input value of DIO13."]
pub type DIN31_0_DIO13_R = crate :: BitReader < DIN31_0_DIO13_A > ; # [doc = "This bit reads the data input value of DIO13.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO13_A { # [doc = "0: ZERO"]
DIN31_0_DIO13_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO13_ONE = 1 , } impl From < DIN31_0_DIO13_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO13_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO13_A { match self . bits { false => DIN31_0_DIO13_A :: DIN31_0_DIO13_ZERO , true => DIN31_0_DIO13_A :: DIN31_0_DIO13_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio13_zero (& self) -> bool { * self == DIN31_0_DIO13_A :: DIN31_0_DIO13_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio13_one (& self) -> bool { * self == DIN31_0_DIO13_A :: DIN31_0_DIO13_ONE } } # [doc = "Field `DIN31_0_DIO14` reader - This bit reads the data input value of DIO14."]
pub type DIN31_0_DIO14_R = crate :: BitReader < DIN31_0_DIO14_A > ; # [doc = "This bit reads the data input value of DIO14.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO14_A { # [doc = "0: ZERO"]
DIN31_0_DIO14_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO14_ONE = 1 , } impl From < DIN31_0_DIO14_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO14_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO14_A { match self . bits { false => DIN31_0_DIO14_A :: DIN31_0_DIO14_ZERO , true => DIN31_0_DIO14_A :: DIN31_0_DIO14_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio14_zero (& self) -> bool { * self == DIN31_0_DIO14_A :: DIN31_0_DIO14_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio14_one (& self) -> bool { * self == DIN31_0_DIO14_A :: DIN31_0_DIO14_ONE } } # [doc = "Field `DIN31_0_DIO15` reader - This bit reads the data input value of DIO15."]
pub type DIN31_0_DIO15_R = crate :: BitReader < DIN31_0_DIO15_A > ; # [doc = "This bit reads the data input value of DIO15.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO15_A { # [doc = "0: ZERO"]
DIN31_0_DIO15_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO15_ONE = 1 , } impl From < DIN31_0_DIO15_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO15_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO15_A { match self . bits { false => DIN31_0_DIO15_A :: DIN31_0_DIO15_ZERO , true => DIN31_0_DIO15_A :: DIN31_0_DIO15_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio15_zero (& self) -> bool { * self == DIN31_0_DIO15_A :: DIN31_0_DIO15_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio15_one (& self) -> bool { * self == DIN31_0_DIO15_A :: DIN31_0_DIO15_ONE } } # [doc = "Field `DIN31_0_DIO16` reader - This bit reads the data input value of DIO16."]
pub type DIN31_0_DIO16_R = crate :: BitReader < DIN31_0_DIO16_A > ; # [doc = "This bit reads the data input value of DIO16.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO16_A { # [doc = "0: ZERO"]
DIN31_0_DIO16_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO16_ONE = 1 , } impl From < DIN31_0_DIO16_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO16_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO16_A { match self . bits { false => DIN31_0_DIO16_A :: DIN31_0_DIO16_ZERO , true => DIN31_0_DIO16_A :: DIN31_0_DIO16_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio16_zero (& self) -> bool { * self == DIN31_0_DIO16_A :: DIN31_0_DIO16_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio16_one (& self) -> bool { * self == DIN31_0_DIO16_A :: DIN31_0_DIO16_ONE } } # [doc = "Field `DIN31_0_DIO17` reader - This bit reads the data input value of DIO17."]
pub type DIN31_0_DIO17_R = crate :: BitReader < DIN31_0_DIO17_A > ; # [doc = "This bit reads the data input value of DIO17.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO17_A { # [doc = "0: ZERO"]
DIN31_0_DIO17_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO17_ONE = 1 , } impl From < DIN31_0_DIO17_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO17_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO17_A { match self . bits { false => DIN31_0_DIO17_A :: DIN31_0_DIO17_ZERO , true => DIN31_0_DIO17_A :: DIN31_0_DIO17_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio17_zero (& self) -> bool { * self == DIN31_0_DIO17_A :: DIN31_0_DIO17_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio17_one (& self) -> bool { * self == DIN31_0_DIO17_A :: DIN31_0_DIO17_ONE } } # [doc = "Field `DIN31_0_DIO18` reader - This bit reads the data input value of DIO18."]
pub type DIN31_0_DIO18_R = crate :: BitReader < DIN31_0_DIO18_A > ; # [doc = "This bit reads the data input value of DIO18.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO18_A { # [doc = "0: ZERO"]
DIN31_0_DIO18_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO18_ONE = 1 , } impl From < DIN31_0_DIO18_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO18_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO18_A { match self . bits { false => DIN31_0_DIO18_A :: DIN31_0_DIO18_ZERO , true => DIN31_0_DIO18_A :: DIN31_0_DIO18_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio18_zero (& self) -> bool { * self == DIN31_0_DIO18_A :: DIN31_0_DIO18_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio18_one (& self) -> bool { * self == DIN31_0_DIO18_A :: DIN31_0_DIO18_ONE } } # [doc = "Field `DIN31_0_DIO19` reader - This bit reads the data input value of DIO19."]
pub type DIN31_0_DIO19_R = crate :: BitReader < DIN31_0_DIO19_A > ; # [doc = "This bit reads the data input value of DIO19.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO19_A { # [doc = "0: ZERO"]
DIN31_0_DIO19_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO19_ONE = 1 , } impl From < DIN31_0_DIO19_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO19_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO19_A { match self . bits { false => DIN31_0_DIO19_A :: DIN31_0_DIO19_ZERO , true => DIN31_0_DIO19_A :: DIN31_0_DIO19_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio19_zero (& self) -> bool { * self == DIN31_0_DIO19_A :: DIN31_0_DIO19_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio19_one (& self) -> bool { * self == DIN31_0_DIO19_A :: DIN31_0_DIO19_ONE } } # [doc = "Field `DIN31_0_DIO20` reader - This bit reads the data input value of DIO20."]
pub type DIN31_0_DIO20_R = crate :: BitReader < DIN31_0_DIO20_A > ; # [doc = "This bit reads the data input value of DIO20.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO20_A { # [doc = "0: ZERO"]
DIN31_0_DIO20_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO20_ONE = 1 , } impl From < DIN31_0_DIO20_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO20_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO20_A { match self . bits { false => DIN31_0_DIO20_A :: DIN31_0_DIO20_ZERO , true => DIN31_0_DIO20_A :: DIN31_0_DIO20_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio20_zero (& self) -> bool { * self == DIN31_0_DIO20_A :: DIN31_0_DIO20_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio20_one (& self) -> bool { * self == DIN31_0_DIO20_A :: DIN31_0_DIO20_ONE } } # [doc = "Field `DIN31_0_DIO21` reader - This bit reads the data input value of DIO21."]
pub type DIN31_0_DIO21_R = crate :: BitReader < DIN31_0_DIO21_A > ; # [doc = "This bit reads the data input value of DIO21.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO21_A { # [doc = "0: ZERO"]
DIN31_0_DIO21_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO21_ONE = 1 , } impl From < DIN31_0_DIO21_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO21_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO21_A { match self . bits { false => DIN31_0_DIO21_A :: DIN31_0_DIO21_ZERO , true => DIN31_0_DIO21_A :: DIN31_0_DIO21_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio21_zero (& self) -> bool { * self == DIN31_0_DIO21_A :: DIN31_0_DIO21_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio21_one (& self) -> bool { * self == DIN31_0_DIO21_A :: DIN31_0_DIO21_ONE } } # [doc = "Field `DIN31_0_DIO22` reader - This bit reads the data input value of DIO22."]
pub type DIN31_0_DIO22_R = crate :: BitReader < DIN31_0_DIO22_A > ; # [doc = "This bit reads the data input value of DIO22.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO22_A { # [doc = "0: ZERO"]
DIN31_0_DIO22_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO22_ONE = 1 , } impl From < DIN31_0_DIO22_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO22_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO22_A { match self . bits { false => DIN31_0_DIO22_A :: DIN31_0_DIO22_ZERO , true => DIN31_0_DIO22_A :: DIN31_0_DIO22_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio22_zero (& self) -> bool { * self == DIN31_0_DIO22_A :: DIN31_0_DIO22_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio22_one (& self) -> bool { * self == DIN31_0_DIO22_A :: DIN31_0_DIO22_ONE } } # [doc = "Field `DIN31_0_DIO23` reader - This bit reads the data input value of DIO23."]
pub type DIN31_0_DIO23_R = crate :: BitReader < DIN31_0_DIO23_A > ; # [doc = "This bit reads the data input value of DIO23.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO23_A { # [doc = "0: ZERO"]
DIN31_0_DIO23_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO23_ONE = 1 , } impl From < DIN31_0_DIO23_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO23_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO23_A { match self . bits { false => DIN31_0_DIO23_A :: DIN31_0_DIO23_ZERO , true => DIN31_0_DIO23_A :: DIN31_0_DIO23_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio23_zero (& self) -> bool { * self == DIN31_0_DIO23_A :: DIN31_0_DIO23_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio23_one (& self) -> bool { * self == DIN31_0_DIO23_A :: DIN31_0_DIO23_ONE } } # [doc = "Field `DIN31_0_DIO24` reader - This bit reads the data input value of DIO24."]
pub type DIN31_0_DIO24_R = crate :: BitReader < DIN31_0_DIO24_A > ; # [doc = "This bit reads the data input value of DIO24.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO24_A { # [doc = "0: ZERO"]
DIN31_0_DIO24_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO24_ONE = 1 , } impl From < DIN31_0_DIO24_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO24_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO24_A { match self . bits { false => DIN31_0_DIO24_A :: DIN31_0_DIO24_ZERO , true => DIN31_0_DIO24_A :: DIN31_0_DIO24_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio24_zero (& self) -> bool { * self == DIN31_0_DIO24_A :: DIN31_0_DIO24_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio24_one (& self) -> bool { * self == DIN31_0_DIO24_A :: DIN31_0_DIO24_ONE } } # [doc = "Field `DIN31_0_DIO25` reader - This bit reads the data input value of DIO25."]
pub type DIN31_0_DIO25_R = crate :: BitReader < DIN31_0_DIO25_A > ; # [doc = "This bit reads the data input value of DIO25.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO25_A { # [doc = "0: ZERO"]
DIN31_0_DIO25_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO25_ONE = 1 , } impl From < DIN31_0_DIO25_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO25_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO25_A { match self . bits { false => DIN31_0_DIO25_A :: DIN31_0_DIO25_ZERO , true => DIN31_0_DIO25_A :: DIN31_0_DIO25_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio25_zero (& self) -> bool { * self == DIN31_0_DIO25_A :: DIN31_0_DIO25_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio25_one (& self) -> bool { * self == DIN31_0_DIO25_A :: DIN31_0_DIO25_ONE } } # [doc = "Field `DIN31_0_DIO26` reader - This bit reads the data input value of DIO26."]
pub type DIN31_0_DIO26_R = crate :: BitReader < DIN31_0_DIO26_A > ; # [doc = "This bit reads the data input value of DIO26.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO26_A { # [doc = "0: ZERO"]
DIN31_0_DIO26_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO26_ONE = 1 , } impl From < DIN31_0_DIO26_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO26_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO26_A { match self . bits { false => DIN31_0_DIO26_A :: DIN31_0_DIO26_ZERO , true => DIN31_0_DIO26_A :: DIN31_0_DIO26_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio26_zero (& self) -> bool { * self == DIN31_0_DIO26_A :: DIN31_0_DIO26_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio26_one (& self) -> bool { * self == DIN31_0_DIO26_A :: DIN31_0_DIO26_ONE } } # [doc = "Field `DIN31_0_DIO27` reader - This bit reads the data input value of DIO27."]
pub type DIN31_0_DIO27_R = crate :: BitReader < DIN31_0_DIO27_A > ; # [doc = "This bit reads the data input value of DIO27.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO27_A { # [doc = "0: ZERO"]
DIN31_0_DIO27_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO27_ONE = 1 , } impl From < DIN31_0_DIO27_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO27_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO27_A { match self . bits { false => DIN31_0_DIO27_A :: DIN31_0_DIO27_ZERO , true => DIN31_0_DIO27_A :: DIN31_0_DIO27_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio27_zero (& self) -> bool { * self == DIN31_0_DIO27_A :: DIN31_0_DIO27_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio27_one (& self) -> bool { * self == DIN31_0_DIO27_A :: DIN31_0_DIO27_ONE } } # [doc = "Field `DIN31_0_DIO28` reader - This bit reads the data input value of DIO28."]
pub type DIN31_0_DIO28_R = crate :: BitReader < DIN31_0_DIO28_A > ; # [doc = "This bit reads the data input value of DIO28.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO28_A { # [doc = "0: ZERO"]
DIN31_0_DIO28_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO28_ONE = 1 , } impl From < DIN31_0_DIO28_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO28_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO28_A { match self . bits { false => DIN31_0_DIO28_A :: DIN31_0_DIO28_ZERO , true => DIN31_0_DIO28_A :: DIN31_0_DIO28_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio28_zero (& self) -> bool { * self == DIN31_0_DIO28_A :: DIN31_0_DIO28_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio28_one (& self) -> bool { * self == DIN31_0_DIO28_A :: DIN31_0_DIO28_ONE } } # [doc = "Field `DIN31_0_DIO29` reader - This bit reads the data input value of DIO29."]
pub type DIN31_0_DIO29_R = crate :: BitReader < DIN31_0_DIO29_A > ; # [doc = "This bit reads the data input value of DIO29.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO29_A { # [doc = "0: ZERO"]
DIN31_0_DIO29_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO29_ONE = 1 , } impl From < DIN31_0_DIO29_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO29_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO29_A { match self . bits { false => DIN31_0_DIO29_A :: DIN31_0_DIO29_ZERO , true => DIN31_0_DIO29_A :: DIN31_0_DIO29_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio29_zero (& self) -> bool { * self == DIN31_0_DIO29_A :: DIN31_0_DIO29_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio29_one (& self) -> bool { * self == DIN31_0_DIO29_A :: DIN31_0_DIO29_ONE } } # [doc = "Field `DIN31_0_DIO30` reader - This bit reads the data input value of DIO30."]
pub type DIN31_0_DIO30_R = crate :: BitReader < DIN31_0_DIO30_A > ; # [doc = "This bit reads the data input value of DIO30.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO30_A { # [doc = "0: ZERO"]
DIN31_0_DIO30_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO30_ONE = 1 , } impl From < DIN31_0_DIO30_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO30_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO30_A { match self . bits { false => DIN31_0_DIO30_A :: DIN31_0_DIO30_ZERO , true => DIN31_0_DIO30_A :: DIN31_0_DIO30_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio30_zero (& self) -> bool { * self == DIN31_0_DIO30_A :: DIN31_0_DIO30_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio30_one (& self) -> bool { * self == DIN31_0_DIO30_A :: DIN31_0_DIO30_ONE } } # [doc = "Field `DIN31_0_DIO31` reader - This bit reads the data input value of DIO31."]
pub type DIN31_0_DIO31_R = crate :: BitReader < DIN31_0_DIO31_A > ; # [doc = "This bit reads the data input value of DIO31.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DIN31_0_DIO31_A { # [doc = "0: ZERO"]
DIN31_0_DIO31_ZERO = 0 , # [doc = "1: ONE"]
DIN31_0_DIO31_ONE = 1 , } impl From < DIN31_0_DIO31_A > for bool { # [inline (always)]
fn from (variant : DIN31_0_DIO31_A) -> Self { variant as u8 != 0 } } impl DIN31_0_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DIN31_0_DIO31_A { match self . bits { false => DIN31_0_DIO31_A :: DIN31_0_DIO31_ZERO , true => DIN31_0_DIO31_A :: DIN31_0_DIO31_ONE , } } # [doc = "ZERO"]
# [inline (always)]
pub fn is_din31_0_dio31_zero (& self) -> bool { * self == DIN31_0_DIO31_A :: DIN31_0_DIO31_ZERO } # [doc = "ONE"]
# [inline (always)]
pub fn is_din31_0_dio31_one (& self) -> bool { * self == DIN31_0_DIO31_A :: DIN31_0_DIO31_ONE } } impl R { # [doc = "Bit 0 - This bit reads the data input value of DIO0."]
# [inline (always)]
pub fn din31_0_dio0 (& self) -> DIN31_0_DIO0_R { DIN31_0_DIO0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - This bit reads the data input value of DIO1."]
# [inline (always)]
pub fn din31_0_dio1 (& self) -> DIN31_0_DIO1_R { DIN31_0_DIO1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - This bit reads the data input value of DIO2."]
# [inline (always)]
pub fn din31_0_dio2 (& self) -> DIN31_0_DIO2_R { DIN31_0_DIO2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - This bit reads the data input value of DIO3."]
# [inline (always)]
pub fn din31_0_dio3 (& self) -> DIN31_0_DIO3_R { DIN31_0_DIO3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - This bit reads the data input value of DIO4."]
# [inline (always)]
pub fn din31_0_dio4 (& self) -> DIN31_0_DIO4_R { DIN31_0_DIO4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - This bit reads the data input value of DIO5."]
# [inline (always)]
pub fn din31_0_dio5 (& self) -> DIN31_0_DIO5_R { DIN31_0_DIO5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - This bit reads the data input value of DIO6."]
# [inline (always)]
pub fn din31_0_dio6 (& self) -> DIN31_0_DIO6_R { DIN31_0_DIO6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - This bit reads the data input value of DIO7."]
# [inline (always)]
pub fn din31_0_dio7 (& self) -> DIN31_0_DIO7_R { DIN31_0_DIO7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - This bit reads the data input value of DIO8."]
# [inline (always)]
pub fn din31_0_dio8 (& self) -> DIN31_0_DIO8_R { DIN31_0_DIO8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - This bit reads the data input value of DIO9."]
# [inline (always)]
pub fn din31_0_dio9 (& self) -> DIN31_0_DIO9_R { DIN31_0_DIO9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - This bit reads the data input value of DIO10."]
# [inline (always)]
pub fn din31_0_dio10 (& self) -> DIN31_0_DIO10_R { DIN31_0_DIO10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - This bit reads the data input value of DIO11."]
# [inline (always)]
pub fn din31_0_dio11 (& self) -> DIN31_0_DIO11_R { DIN31_0_DIO11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - This bit reads the data input value of DIO12."]
# [inline (always)]
pub fn din31_0_dio12 (& self) -> DIN31_0_DIO12_R { DIN31_0_DIO12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - This bit reads the data input value of DIO13."]
# [inline (always)]
pub fn din31_0_dio13 (& self) -> DIN31_0_DIO13_R { DIN31_0_DIO13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - This bit reads the data input value of DIO14."]
# [inline (always)]
pub fn din31_0_dio14 (& self) -> DIN31_0_DIO14_R { DIN31_0_DIO14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit reads the data input value of DIO15."]
# [inline (always)]
pub fn din31_0_dio15 (& self) -> DIN31_0_DIO15_R { DIN31_0_DIO15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - This bit reads the data input value of DIO16."]
# [inline (always)]
pub fn din31_0_dio16 (& self) -> DIN31_0_DIO16_R { DIN31_0_DIO16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - This bit reads the data input value of DIO17."]
# [inline (always)]
pub fn din31_0_dio17 (& self) -> DIN31_0_DIO17_R { DIN31_0_DIO17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - This bit reads the data input value of DIO18."]
# [inline (always)]
pub fn din31_0_dio18 (& self) -> DIN31_0_DIO18_R { DIN31_0_DIO18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - This bit reads the data input value of DIO19."]
# [inline (always)]
pub fn din31_0_dio19 (& self) -> DIN31_0_DIO19_R { DIN31_0_DIO19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - This bit reads the data input value of DIO20."]
# [inline (always)]
pub fn din31_0_dio20 (& self) -> DIN31_0_DIO20_R { DIN31_0_DIO20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - This bit reads the data input value of DIO21."]
# [inline (always)]
pub fn din31_0_dio21 (& self) -> DIN31_0_DIO21_R { DIN31_0_DIO21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - This bit reads the data input value of DIO22."]
# [inline (always)]
pub fn din31_0_dio22 (& self) -> DIN31_0_DIO22_R { DIN31_0_DIO22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - This bit reads the data input value of DIO23."]
# [inline (always)]
pub fn din31_0_dio23 (& self) -> DIN31_0_DIO23_R { DIN31_0_DIO23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - This bit reads the data input value of DIO24."]
# [inline (always)]
pub fn din31_0_dio24 (& self) -> DIN31_0_DIO24_R { DIN31_0_DIO24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - This bit reads the data input value of DIO25."]
# [inline (always)]
pub fn din31_0_dio25 (& self) -> DIN31_0_DIO25_R { DIN31_0_DIO25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - This bit reads the data input value of DIO26."]
# [inline (always)]
pub fn din31_0_dio26 (& self) -> DIN31_0_DIO26_R { DIN31_0_DIO26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - This bit reads the data input value of DIO27."]
# [inline (always)]
pub fn din31_0_dio27 (& self) -> DIN31_0_DIO27_R { DIN31_0_DIO27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - This bit reads the data input value of DIO28."]
# [inline (always)]
pub fn din31_0_dio28 (& self) -> DIN31_0_DIO28_R { DIN31_0_DIO28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - This bit reads the data input value of DIO29."]
# [inline (always)]
pub fn din31_0_dio29 (& self) -> DIN31_0_DIO29_R { DIN31_0_DIO29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - This bit reads the data input value of DIO30."]
# [inline (always)]
pub fn din31_0_dio30 (& self) -> DIN31_0_DIO30_R { DIN31_0_DIO30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - This bit reads the data input value of DIO31."]
# [inline (always)]
pub fn din31_0_dio31 (& self) -> DIN31_0_DIO31_R { DIN31_0_DIO31_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Data input 31 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`din31_0::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DIN31_0_SPEC ; impl crate :: RegisterSpec for DIN31_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`din31_0::R`](R) reader structure"]
impl crate :: Readable for DIN31_0_SPEC { } # [doc = "`reset()` method sets DIN31_0 to value 0"]
impl crate :: Resettable for DIN31_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "POLARITY15_0 (rw) register accessor: Polarity 15 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polarity15_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polarity15_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@polarity15_0`]
module"]
pub type POLARITY15_0 = crate :: Reg < polarity15_0 :: POLARITY15_0_SPEC > ; # [doc = "Polarity 15 to 0"]
pub mod polarity15_0 { # [doc = "Register `POLARITY15_0` reader"]
pub type R = crate :: R < POLARITY15_0_SPEC > ; # [doc = "Register `POLARITY15_0` writer"]
pub type W = crate :: W < POLARITY15_0_SPEC > ; # [doc = "Field `POLARITY15_0_DIO0` reader - Enables and configures edge detection polarity for DIO0."]
pub type POLARITY15_0_DIO0_R = crate :: FieldReader < POLARITY15_0_DIO0_A > ; # [doc = "Enables and configures edge detection polarity for DIO0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO0_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO0_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO0_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO0_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO0_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO0_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO0_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO0_A { type Ux = u8 ; } impl POLARITY15_0_DIO0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO0_A { match self . bits { 0 => POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_DISABLE , 1 => POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_RISE , 2 => POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_FALL , 3 => POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio0_disable (& self) -> bool { * self == POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio0_rise (& self) -> bool { * self == POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio0_fall (& self) -> bool { * self == POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio0_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO0` writer - Enables and configures edge detection polarity for DIO0."]
pub type POLARITY15_0_DIO0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO0_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio0_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio0_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio0_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio0_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO0_A :: POLARITY15_0_DIO0_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO1` reader - Enables and configures edge detection polarity for DIO1."]
pub type POLARITY15_0_DIO1_R = crate :: FieldReader < POLARITY15_0_DIO1_A > ; # [doc = "Enables and configures edge detection polarity for DIO1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO1_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO1_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO1_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO1_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO1_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO1_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO1_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO1_A { type Ux = u8 ; } impl POLARITY15_0_DIO1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO1_A { match self . bits { 0 => POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_DISABLE , 1 => POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_RISE , 2 => POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_FALL , 3 => POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio1_disable (& self) -> bool { * self == POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio1_rise (& self) -> bool { * self == POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio1_fall (& self) -> bool { * self == POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio1_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO1` writer - Enables and configures edge detection polarity for DIO1."]
pub type POLARITY15_0_DIO1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO1_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio1_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio1_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio1_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio1_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO1_A :: POLARITY15_0_DIO1_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO2` reader - Enables and configures edge detection polarity for DIO2."]
pub type POLARITY15_0_DIO2_R = crate :: FieldReader < POLARITY15_0_DIO2_A > ; # [doc = "Enables and configures edge detection polarity for DIO2.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO2_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO2_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO2_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO2_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO2_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO2_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO2_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO2_A { type Ux = u8 ; } impl POLARITY15_0_DIO2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO2_A { match self . bits { 0 => POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_DISABLE , 1 => POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_RISE , 2 => POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_FALL , 3 => POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio2_disable (& self) -> bool { * self == POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio2_rise (& self) -> bool { * self == POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio2_fall (& self) -> bool { * self == POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio2_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO2` writer - Enables and configures edge detection polarity for DIO2."]
pub type POLARITY15_0_DIO2_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO2_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio2_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio2_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio2_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio2_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO2_A :: POLARITY15_0_DIO2_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO3` reader - Enables and configures edge detection polarity for DIO3."]
pub type POLARITY15_0_DIO3_R = crate :: FieldReader < POLARITY15_0_DIO3_A > ; # [doc = "Enables and configures edge detection polarity for DIO3.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO3_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO3_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO3_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO3_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO3_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO3_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO3_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO3_A { type Ux = u8 ; } impl POLARITY15_0_DIO3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO3_A { match self . bits { 0 => POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_DISABLE , 1 => POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_RISE , 2 => POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_FALL , 3 => POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio3_disable (& self) -> bool { * self == POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio3_rise (& self) -> bool { * self == POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio3_fall (& self) -> bool { * self == POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio3_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO3` writer - Enables and configures edge detection polarity for DIO3."]
pub type POLARITY15_0_DIO3_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO3_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio3_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio3_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio3_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio3_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO3_A :: POLARITY15_0_DIO3_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO4` reader - Enables and configures edge detection polarity for DIO4."]
pub type POLARITY15_0_DIO4_R = crate :: FieldReader < POLARITY15_0_DIO4_A > ; # [doc = "Enables and configures edge detection polarity for DIO4.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO4_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO4_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO4_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO4_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO4_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO4_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO4_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO4_A { type Ux = u8 ; } impl POLARITY15_0_DIO4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO4_A { match self . bits { 0 => POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_DISABLE , 1 => POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_RISE , 2 => POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_FALL , 3 => POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio4_disable (& self) -> bool { * self == POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio4_rise (& self) -> bool { * self == POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio4_fall (& self) -> bool { * self == POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio4_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO4` writer - Enables and configures edge detection polarity for DIO4."]
pub type POLARITY15_0_DIO4_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO4_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio4_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio4_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio4_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio4_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO4_A :: POLARITY15_0_DIO4_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO5` reader - Enables and configures edge detection polarity for DIO5."]
pub type POLARITY15_0_DIO5_R = crate :: FieldReader < POLARITY15_0_DIO5_A > ; # [doc = "Enables and configures edge detection polarity for DIO5.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO5_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO5_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO5_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO5_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO5_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO5_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO5_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO5_A { type Ux = u8 ; } impl POLARITY15_0_DIO5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO5_A { match self . bits { 0 => POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_DISABLE , 1 => POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_RISE , 2 => POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_FALL , 3 => POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio5_disable (& self) -> bool { * self == POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio5_rise (& self) -> bool { * self == POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio5_fall (& self) -> bool { * self == POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio5_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO5` writer - Enables and configures edge detection polarity for DIO5."]
pub type POLARITY15_0_DIO5_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO5_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio5_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio5_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio5_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio5_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO5_A :: POLARITY15_0_DIO5_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO6` reader - Enables and configures edge detection polarity for DIO6."]
pub type POLARITY15_0_DIO6_R = crate :: FieldReader < POLARITY15_0_DIO6_A > ; # [doc = "Enables and configures edge detection polarity for DIO6.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO6_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO6_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO6_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO6_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO6_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO6_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO6_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO6_A { type Ux = u8 ; } impl POLARITY15_0_DIO6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO6_A { match self . bits { 0 => POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_DISABLE , 1 => POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_RISE , 2 => POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_FALL , 3 => POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio6_disable (& self) -> bool { * self == POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio6_rise (& self) -> bool { * self == POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio6_fall (& self) -> bool { * self == POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio6_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO6` writer - Enables and configures edge detection polarity for DIO6."]
pub type POLARITY15_0_DIO6_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO6_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio6_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio6_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio6_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio6_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO6_A :: POLARITY15_0_DIO6_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO7` reader - Enables and configures edge detection polarity for DIO7."]
pub type POLARITY15_0_DIO7_R = crate :: FieldReader < POLARITY15_0_DIO7_A > ; # [doc = "Enables and configures edge detection polarity for DIO7.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO7_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO7_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO7_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO7_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO7_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO7_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO7_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO7_A { type Ux = u8 ; } impl POLARITY15_0_DIO7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO7_A { match self . bits { 0 => POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_DISABLE , 1 => POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_RISE , 2 => POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_FALL , 3 => POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio7_disable (& self) -> bool { * self == POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio7_rise (& self) -> bool { * self == POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio7_fall (& self) -> bool { * self == POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio7_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO7` writer - Enables and configures edge detection polarity for DIO7."]
pub type POLARITY15_0_DIO7_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO7_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio7_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio7_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio7_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio7_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO7_A :: POLARITY15_0_DIO7_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO8` reader - Enables and configures edge detection polarity for DIO8."]
pub type POLARITY15_0_DIO8_R = crate :: FieldReader < POLARITY15_0_DIO8_A > ; # [doc = "Enables and configures edge detection polarity for DIO8.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO8_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO8_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO8_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO8_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO8_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO8_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO8_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO8_A { type Ux = u8 ; } impl POLARITY15_0_DIO8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO8_A { match self . bits { 0 => POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_DISABLE , 1 => POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_RISE , 2 => POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_FALL , 3 => POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio8_disable (& self) -> bool { * self == POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio8_rise (& self) -> bool { * self == POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio8_fall (& self) -> bool { * self == POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio8_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO8` writer - Enables and configures edge detection polarity for DIO8."]
pub type POLARITY15_0_DIO8_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO8_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio8_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio8_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio8_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio8_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO8_A :: POLARITY15_0_DIO8_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO9` reader - Enables and configures edge detection polarity for DIO9."]
pub type POLARITY15_0_DIO9_R = crate :: FieldReader < POLARITY15_0_DIO9_A > ; # [doc = "Enables and configures edge detection polarity for DIO9.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO9_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO9_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO9_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO9_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO9_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO9_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO9_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO9_A { type Ux = u8 ; } impl POLARITY15_0_DIO9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO9_A { match self . bits { 0 => POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_DISABLE , 1 => POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_RISE , 2 => POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_FALL , 3 => POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio9_disable (& self) -> bool { * self == POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio9_rise (& self) -> bool { * self == POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio9_fall (& self) -> bool { * self == POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio9_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO9` writer - Enables and configures edge detection polarity for DIO9."]
pub type POLARITY15_0_DIO9_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO9_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio9_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio9_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio9_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio9_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO9_A :: POLARITY15_0_DIO9_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO10` reader - Enables and configures edge detection polarity for DIO10."]
pub type POLARITY15_0_DIO10_R = crate :: FieldReader < POLARITY15_0_DIO10_A > ; # [doc = "Enables and configures edge detection polarity for DIO10.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO10_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO10_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO10_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO10_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO10_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO10_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO10_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO10_A { type Ux = u8 ; } impl POLARITY15_0_DIO10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO10_A { match self . bits { 0 => POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_DISABLE , 1 => POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_RISE , 2 => POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_FALL , 3 => POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio10_disable (& self) -> bool { * self == POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio10_rise (& self) -> bool { * self == POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio10_fall (& self) -> bool { * self == POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio10_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO10` writer - Enables and configures edge detection polarity for DIO10."]
pub type POLARITY15_0_DIO10_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO10_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio10_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio10_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio10_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio10_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO10_A :: POLARITY15_0_DIO10_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO11` reader - Enables and configures edge detection polarity for DIO11."]
pub type POLARITY15_0_DIO11_R = crate :: FieldReader < POLARITY15_0_DIO11_A > ; # [doc = "Enables and configures edge detection polarity for DIO11.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO11_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO11_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO11_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO11_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO11_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO11_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO11_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO11_A { type Ux = u8 ; } impl POLARITY15_0_DIO11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO11_A { match self . bits { 0 => POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_DISABLE , 1 => POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_RISE , 2 => POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_FALL , 3 => POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio11_disable (& self) -> bool { * self == POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio11_rise (& self) -> bool { * self == POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio11_fall (& self) -> bool { * self == POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio11_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO11` writer - Enables and configures edge detection polarity for DIO11."]
pub type POLARITY15_0_DIO11_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO11_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio11_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio11_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio11_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio11_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO11_A :: POLARITY15_0_DIO11_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO12` reader - Enables and configures edge detection polarity for DIO12."]
pub type POLARITY15_0_DIO12_R = crate :: FieldReader < POLARITY15_0_DIO12_A > ; # [doc = "Enables and configures edge detection polarity for DIO12.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO12_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO12_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO12_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO12_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO12_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO12_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO12_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO12_A { type Ux = u8 ; } impl POLARITY15_0_DIO12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO12_A { match self . bits { 0 => POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_DISABLE , 1 => POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_RISE , 2 => POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_FALL , 3 => POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio12_disable (& self) -> bool { * self == POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio12_rise (& self) -> bool { * self == POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio12_fall (& self) -> bool { * self == POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio12_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO12` writer - Enables and configures edge detection polarity for DIO12."]
pub type POLARITY15_0_DIO12_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO12_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio12_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio12_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio12_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio12_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO12_A :: POLARITY15_0_DIO12_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO13` reader - Enables and configures edge detection polarity for DIO13."]
pub type POLARITY15_0_DIO13_R = crate :: FieldReader < POLARITY15_0_DIO13_A > ; # [doc = "Enables and configures edge detection polarity for DIO13.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO13_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO13_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO13_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO13_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO13_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO13_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO13_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO13_A { type Ux = u8 ; } impl POLARITY15_0_DIO13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO13_A { match self . bits { 0 => POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_DISABLE , 1 => POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_RISE , 2 => POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_FALL , 3 => POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio13_disable (& self) -> bool { * self == POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio13_rise (& self) -> bool { * self == POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio13_fall (& self) -> bool { * self == POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio13_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO13` writer - Enables and configures edge detection polarity for DIO13."]
pub type POLARITY15_0_DIO13_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO13_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio13_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio13_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio13_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio13_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO13_A :: POLARITY15_0_DIO13_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO14` reader - Enables and configures edge detection polarity for DIO14."]
pub type POLARITY15_0_DIO14_R = crate :: FieldReader < POLARITY15_0_DIO14_A > ; # [doc = "Enables and configures edge detection polarity for DIO14.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO14_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO14_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO14_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO14_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO14_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO14_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO14_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO14_A { type Ux = u8 ; } impl POLARITY15_0_DIO14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO14_A { match self . bits { 0 => POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_DISABLE , 1 => POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_RISE , 2 => POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_FALL , 3 => POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio14_disable (& self) -> bool { * self == POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio14_rise (& self) -> bool { * self == POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio14_fall (& self) -> bool { * self == POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio14_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO14` writer - Enables and configures edge detection polarity for DIO14."]
pub type POLARITY15_0_DIO14_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO14_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio14_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio14_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio14_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio14_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO14_A :: POLARITY15_0_DIO14_RISE_FALL) } } # [doc = "Field `POLARITY15_0_DIO15` reader - Enables and configures edge detection polarity for DIO15."]
pub type POLARITY15_0_DIO15_R = crate :: FieldReader < POLARITY15_0_DIO15_A > ; # [doc = "Enables and configures edge detection polarity for DIO15.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY15_0_DIO15_A { # [doc = "0: DISABLE"]
POLARITY15_0_DIO15_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY15_0_DIO15_RISE = 1 , # [doc = "2: FALL"]
POLARITY15_0_DIO15_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY15_0_DIO15_RISE_FALL = 3 , } impl From < POLARITY15_0_DIO15_A > for u8 { # [inline (always)]
fn from (variant : POLARITY15_0_DIO15_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY15_0_DIO15_A { type Ux = u8 ; } impl POLARITY15_0_DIO15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY15_0_DIO15_A { match self . bits { 0 => POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_DISABLE , 1 => POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_RISE , 2 => POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_FALL , 3 => POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity15_0_dio15_disable (& self) -> bool { * self == POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity15_0_dio15_rise (& self) -> bool { * self == POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio15_fall (& self) -> bool { * self == POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity15_0_dio15_rise_fall (& self) -> bool { * self == POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_RISE_FALL } } # [doc = "Field `POLARITY15_0_DIO15` writer - Enables and configures edge detection polarity for DIO15."]
pub type POLARITY15_0_DIO15_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY15_0_DIO15_A > ; impl < 'a , REG , const O : u8 > POLARITY15_0_DIO15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity15_0_dio15_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity15_0_dio15_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity15_0_dio15_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity15_0_dio15_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY15_0_DIO15_A :: POLARITY15_0_DIO15_RISE_FALL) } } impl R { # [doc = "Bits 0:1 - Enables and configures edge detection polarity for DIO0."]
# [inline (always)]
pub fn polarity15_0_dio0 (& self) -> POLARITY15_0_DIO0_R { POLARITY15_0_DIO0_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Enables and configures edge detection polarity for DIO1."]
# [inline (always)]
pub fn polarity15_0_dio1 (& self) -> POLARITY15_0_DIO1_R { POLARITY15_0_DIO1_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Enables and configures edge detection polarity for DIO2."]
# [inline (always)]
pub fn polarity15_0_dio2 (& self) -> POLARITY15_0_DIO2_R { POLARITY15_0_DIO2_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - Enables and configures edge detection polarity for DIO3."]
# [inline (always)]
pub fn polarity15_0_dio3 (& self) -> POLARITY15_0_DIO3_R { POLARITY15_0_DIO3_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - Enables and configures edge detection polarity for DIO4."]
# [inline (always)]
pub fn polarity15_0_dio4 (& self) -> POLARITY15_0_DIO4_R { POLARITY15_0_DIO4_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Enables and configures edge detection polarity for DIO5."]
# [inline (always)]
pub fn polarity15_0_dio5 (& self) -> POLARITY15_0_DIO5_R { POLARITY15_0_DIO5_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Enables and configures edge detection polarity for DIO6."]
# [inline (always)]
pub fn polarity15_0_dio6 (& self) -> POLARITY15_0_DIO6_R { POLARITY15_0_DIO6_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - Enables and configures edge detection polarity for DIO7."]
# [inline (always)]
pub fn polarity15_0_dio7 (& self) -> POLARITY15_0_DIO7_R { POLARITY15_0_DIO7_R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - Enables and configures edge detection polarity for DIO8."]
# [inline (always)]
pub fn polarity15_0_dio8 (& self) -> POLARITY15_0_DIO8_R { POLARITY15_0_DIO8_R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - Enables and configures edge detection polarity for DIO9."]
# [inline (always)]
pub fn polarity15_0_dio9 (& self) -> POLARITY15_0_DIO9_R { POLARITY15_0_DIO9_R :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - Enables and configures edge detection polarity for DIO10."]
# [inline (always)]
pub fn polarity15_0_dio10 (& self) -> POLARITY15_0_DIO10_R { POLARITY15_0_DIO10_R :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - Enables and configures edge detection polarity for DIO11."]
# [inline (always)]
pub fn polarity15_0_dio11 (& self) -> POLARITY15_0_DIO11_R { POLARITY15_0_DIO11_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:25 - Enables and configures edge detection polarity for DIO12."]
# [inline (always)]
pub fn polarity15_0_dio12 (& self) -> POLARITY15_0_DIO12_R { POLARITY15_0_DIO12_R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:27 - Enables and configures edge detection polarity for DIO13."]
# [inline (always)]
pub fn polarity15_0_dio13 (& self) -> POLARITY15_0_DIO13_R { POLARITY15_0_DIO13_R :: new (((self . bits >> 26) & 3) as u8) } # [doc = "Bits 28:29 - Enables and configures edge detection polarity for DIO14."]
# [inline (always)]
pub fn polarity15_0_dio14 (& self) -> POLARITY15_0_DIO14_R { POLARITY15_0_DIO14_R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - Enables and configures edge detection polarity for DIO15."]
# [inline (always)]
pub fn polarity15_0_dio15 (& self) -> POLARITY15_0_DIO15_R { POLARITY15_0_DIO15_R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Enables and configures edge detection polarity for DIO0."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio0 (& mut self) -> POLARITY15_0_DIO0_W < POLARITY15_0_SPEC , 0 > { POLARITY15_0_DIO0_W :: new (self) } # [doc = "Bits 2:3 - Enables and configures edge detection polarity for DIO1."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio1 (& mut self) -> POLARITY15_0_DIO1_W < POLARITY15_0_SPEC , 2 > { POLARITY15_0_DIO1_W :: new (self) } # [doc = "Bits 4:5 - Enables and configures edge detection polarity for DIO2."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio2 (& mut self) -> POLARITY15_0_DIO2_W < POLARITY15_0_SPEC , 4 > { POLARITY15_0_DIO2_W :: new (self) } # [doc = "Bits 6:7 - Enables and configures edge detection polarity for DIO3."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio3 (& mut self) -> POLARITY15_0_DIO3_W < POLARITY15_0_SPEC , 6 > { POLARITY15_0_DIO3_W :: new (self) } # [doc = "Bits 8:9 - Enables and configures edge detection polarity for DIO4."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio4 (& mut self) -> POLARITY15_0_DIO4_W < POLARITY15_0_SPEC , 8 > { POLARITY15_0_DIO4_W :: new (self) } # [doc = "Bits 10:11 - Enables and configures edge detection polarity for DIO5."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio5 (& mut self) -> POLARITY15_0_DIO5_W < POLARITY15_0_SPEC , 10 > { POLARITY15_0_DIO5_W :: new (self) } # [doc = "Bits 12:13 - Enables and configures edge detection polarity for DIO6."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio6 (& mut self) -> POLARITY15_0_DIO6_W < POLARITY15_0_SPEC , 12 > { POLARITY15_0_DIO6_W :: new (self) } # [doc = "Bits 14:15 - Enables and configures edge detection polarity for DIO7."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio7 (& mut self) -> POLARITY15_0_DIO7_W < POLARITY15_0_SPEC , 14 > { POLARITY15_0_DIO7_W :: new (self) } # [doc = "Bits 16:17 - Enables and configures edge detection polarity for DIO8."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio8 (& mut self) -> POLARITY15_0_DIO8_W < POLARITY15_0_SPEC , 16 > { POLARITY15_0_DIO8_W :: new (self) } # [doc = "Bits 18:19 - Enables and configures edge detection polarity for DIO9."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio9 (& mut self) -> POLARITY15_0_DIO9_W < POLARITY15_0_SPEC , 18 > { POLARITY15_0_DIO9_W :: new (self) } # [doc = "Bits 20:21 - Enables and configures edge detection polarity for DIO10."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio10 (& mut self) -> POLARITY15_0_DIO10_W < POLARITY15_0_SPEC , 20 > { POLARITY15_0_DIO10_W :: new (self) } # [doc = "Bits 22:23 - Enables and configures edge detection polarity for DIO11."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio11 (& mut self) -> POLARITY15_0_DIO11_W < POLARITY15_0_SPEC , 22 > { POLARITY15_0_DIO11_W :: new (self) } # [doc = "Bits 24:25 - Enables and configures edge detection polarity for DIO12."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio12 (& mut self) -> POLARITY15_0_DIO12_W < POLARITY15_0_SPEC , 24 > { POLARITY15_0_DIO12_W :: new (self) } # [doc = "Bits 26:27 - Enables and configures edge detection polarity for DIO13."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio13 (& mut self) -> POLARITY15_0_DIO13_W < POLARITY15_0_SPEC , 26 > { POLARITY15_0_DIO13_W :: new (self) } # [doc = "Bits 28:29 - Enables and configures edge detection polarity for DIO14."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio14 (& mut self) -> POLARITY15_0_DIO14_W < POLARITY15_0_SPEC , 28 > { POLARITY15_0_DIO14_W :: new (self) } # [doc = "Bits 30:31 - Enables and configures edge detection polarity for DIO15."]
# [inline (always)]
# [must_use]
pub fn polarity15_0_dio15 (& mut self) -> POLARITY15_0_DIO15_W < POLARITY15_0_SPEC , 30 > { POLARITY15_0_DIO15_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Polarity 15 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polarity15_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polarity15_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct POLARITY15_0_SPEC ; impl crate :: RegisterSpec for POLARITY15_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`polarity15_0::R`](R) reader structure"]
impl crate :: Readable for POLARITY15_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`polarity15_0::W`](W) writer structure"]
impl crate :: Writable for POLARITY15_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets POLARITY15_0 to value 0"]
impl crate :: Resettable for POLARITY15_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "POLARITY31_16 (rw) register accessor: Polarity 31 to 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polarity31_16::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polarity31_16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@polarity31_16`]
module"]
pub type POLARITY31_16 = crate :: Reg < polarity31_16 :: POLARITY31_16_SPEC > ; # [doc = "Polarity 31 to 16"]
pub mod polarity31_16 { # [doc = "Register `POLARITY31_16` reader"]
pub type R = crate :: R < POLARITY31_16_SPEC > ; # [doc = "Register `POLARITY31_16` writer"]
pub type W = crate :: W < POLARITY31_16_SPEC > ; # [doc = "Field `POLARITY31_16_DIO16` reader - Enables and configures edge detection polarity for DIO16."]
pub type POLARITY31_16_DIO16_R = crate :: FieldReader < POLARITY31_16_DIO16_A > ; # [doc = "Enables and configures edge detection polarity for DIO16.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO16_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO16_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO16_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO16_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO16_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO16_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO16_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO16_A { type Ux = u8 ; } impl POLARITY31_16_DIO16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO16_A { match self . bits { 0 => POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_DISABLE , 1 => POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_RISE , 2 => POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_FALL , 3 => POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio16_disable (& self) -> bool { * self == POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio16_rise (& self) -> bool { * self == POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio16_fall (& self) -> bool { * self == POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio16_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO16` writer - Enables and configures edge detection polarity for DIO16."]
pub type POLARITY31_16_DIO16_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO16_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio16_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio16_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio16_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio16_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO16_A :: POLARITY31_16_DIO16_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO17` reader - Enables and configures edge detection polarity for DIO17."]
pub type POLARITY31_16_DIO17_R = crate :: FieldReader < POLARITY31_16_DIO17_A > ; # [doc = "Enables and configures edge detection polarity for DIO17.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO17_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO17_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO17_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO17_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO17_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO17_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO17_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO17_A { type Ux = u8 ; } impl POLARITY31_16_DIO17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO17_A { match self . bits { 0 => POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_DISABLE , 1 => POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_RISE , 2 => POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_FALL , 3 => POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio17_disable (& self) -> bool { * self == POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio17_rise (& self) -> bool { * self == POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio17_fall (& self) -> bool { * self == POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio17_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO17` writer - Enables and configures edge detection polarity for DIO17."]
pub type POLARITY31_16_DIO17_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO17_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio17_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio17_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio17_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio17_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO17_A :: POLARITY31_16_DIO17_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO18` reader - Enables and configures edge detection polarity for DIO18."]
pub type POLARITY31_16_DIO18_R = crate :: FieldReader < POLARITY31_16_DIO18_A > ; # [doc = "Enables and configures edge detection polarity for DIO18.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO18_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO18_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO18_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO18_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO18_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO18_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO18_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO18_A { type Ux = u8 ; } impl POLARITY31_16_DIO18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO18_A { match self . bits { 0 => POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_DISABLE , 1 => POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_RISE , 2 => POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_FALL , 3 => POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio18_disable (& self) -> bool { * self == POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio18_rise (& self) -> bool { * self == POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio18_fall (& self) -> bool { * self == POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio18_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO18` writer - Enables and configures edge detection polarity for DIO18."]
pub type POLARITY31_16_DIO18_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO18_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio18_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio18_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio18_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio18_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO18_A :: POLARITY31_16_DIO18_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO19` reader - Enables and configures edge detection polarity for DIO19."]
pub type POLARITY31_16_DIO19_R = crate :: FieldReader < POLARITY31_16_DIO19_A > ; # [doc = "Enables and configures edge detection polarity for DIO19.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO19_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO19_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO19_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO19_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO19_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO19_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO19_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO19_A { type Ux = u8 ; } impl POLARITY31_16_DIO19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO19_A { match self . bits { 0 => POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_DISABLE , 1 => POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_RISE , 2 => POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_FALL , 3 => POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio19_disable (& self) -> bool { * self == POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio19_rise (& self) -> bool { * self == POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio19_fall (& self) -> bool { * self == POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio19_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO19` writer - Enables and configures edge detection polarity for DIO19."]
pub type POLARITY31_16_DIO19_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO19_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio19_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio19_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio19_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio19_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO19_A :: POLARITY31_16_DIO19_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO20` reader - Enables and configures edge detection polarity for DIO20."]
pub type POLARITY31_16_DIO20_R = crate :: FieldReader < POLARITY31_16_DIO20_A > ; # [doc = "Enables and configures edge detection polarity for DIO20.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO20_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO20_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO20_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO20_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO20_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO20_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO20_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO20_A { type Ux = u8 ; } impl POLARITY31_16_DIO20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO20_A { match self . bits { 0 => POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_DISABLE , 1 => POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_RISE , 2 => POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_FALL , 3 => POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio20_disable (& self) -> bool { * self == POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio20_rise (& self) -> bool { * self == POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio20_fall (& self) -> bool { * self == POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio20_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO20` writer - Enables and configures edge detection polarity for DIO20."]
pub type POLARITY31_16_DIO20_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO20_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio20_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio20_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio20_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio20_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO20_A :: POLARITY31_16_DIO20_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO21` reader - Enables and configures edge detection polarity for DIO21."]
pub type POLARITY31_16_DIO21_R = crate :: FieldReader < POLARITY31_16_DIO21_A > ; # [doc = "Enables and configures edge detection polarity for DIO21.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO21_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO21_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO21_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO21_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO21_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO21_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO21_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO21_A { type Ux = u8 ; } impl POLARITY31_16_DIO21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO21_A { match self . bits { 0 => POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_DISABLE , 1 => POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_RISE , 2 => POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_FALL , 3 => POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio21_disable (& self) -> bool { * self == POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio21_rise (& self) -> bool { * self == POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio21_fall (& self) -> bool { * self == POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio21_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO21` writer - Enables and configures edge detection polarity for DIO21."]
pub type POLARITY31_16_DIO21_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO21_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio21_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio21_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio21_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio21_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO21_A :: POLARITY31_16_DIO21_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO22` reader - Enables and configures edge detection polarity for DIO22."]
pub type POLARITY31_16_DIO22_R = crate :: FieldReader < POLARITY31_16_DIO22_A > ; # [doc = "Enables and configures edge detection polarity for DIO22.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO22_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO22_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO22_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO22_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO22_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO22_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO22_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO22_A { type Ux = u8 ; } impl POLARITY31_16_DIO22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO22_A { match self . bits { 0 => POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_DISABLE , 1 => POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_RISE , 2 => POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_FALL , 3 => POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio22_disable (& self) -> bool { * self == POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio22_rise (& self) -> bool { * self == POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio22_fall (& self) -> bool { * self == POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio22_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO22` writer - Enables and configures edge detection polarity for DIO22."]
pub type POLARITY31_16_DIO22_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO22_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio22_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio22_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio22_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio22_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO22_A :: POLARITY31_16_DIO22_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO23` reader - Enables and configures edge detection polarity for DIO23."]
pub type POLARITY31_16_DIO23_R = crate :: FieldReader < POLARITY31_16_DIO23_A > ; # [doc = "Enables and configures edge detection polarity for DIO23.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO23_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO23_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO23_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO23_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO23_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO23_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO23_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO23_A { type Ux = u8 ; } impl POLARITY31_16_DIO23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO23_A { match self . bits { 0 => POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_DISABLE , 1 => POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_RISE , 2 => POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_FALL , 3 => POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio23_disable (& self) -> bool { * self == POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio23_rise (& self) -> bool { * self == POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio23_fall (& self) -> bool { * self == POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio23_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO23` writer - Enables and configures edge detection polarity for DIO23."]
pub type POLARITY31_16_DIO23_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO23_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio23_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio23_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio23_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio23_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO23_A :: POLARITY31_16_DIO23_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO24` reader - Enables and configures edge detection polarity for DIO24."]
pub type POLARITY31_16_DIO24_R = crate :: FieldReader < POLARITY31_16_DIO24_A > ; # [doc = "Enables and configures edge detection polarity for DIO24.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO24_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO24_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO24_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO24_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO24_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO24_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO24_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO24_A { type Ux = u8 ; } impl POLARITY31_16_DIO24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO24_A { match self . bits { 0 => POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_DISABLE , 1 => POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_RISE , 2 => POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_FALL , 3 => POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio24_disable (& self) -> bool { * self == POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio24_rise (& self) -> bool { * self == POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio24_fall (& self) -> bool { * self == POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio24_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO24` writer - Enables and configures edge detection polarity for DIO24."]
pub type POLARITY31_16_DIO24_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO24_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio24_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio24_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio24_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio24_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO24_A :: POLARITY31_16_DIO24_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO25` reader - Enables and configures edge detection polarity for DIO25."]
pub type POLARITY31_16_DIO25_R = crate :: FieldReader < POLARITY31_16_DIO25_A > ; # [doc = "Enables and configures edge detection polarity for DIO25.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO25_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO25_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO25_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO25_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO25_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO25_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO25_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO25_A { type Ux = u8 ; } impl POLARITY31_16_DIO25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO25_A { match self . bits { 0 => POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_DISABLE , 1 => POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_RISE , 2 => POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_FALL , 3 => POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio25_disable (& self) -> bool { * self == POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio25_rise (& self) -> bool { * self == POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio25_fall (& self) -> bool { * self == POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio25_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO25` writer - Enables and configures edge detection polarity for DIO25."]
pub type POLARITY31_16_DIO25_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO25_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio25_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio25_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio25_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio25_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO25_A :: POLARITY31_16_DIO25_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO26` reader - Enables and configures edge detection polarity for DIO26."]
pub type POLARITY31_16_DIO26_R = crate :: FieldReader < POLARITY31_16_DIO26_A > ; # [doc = "Enables and configures edge detection polarity for DIO26.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO26_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO26_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO26_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO26_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO26_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO26_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO26_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO26_A { type Ux = u8 ; } impl POLARITY31_16_DIO26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO26_A { match self . bits { 0 => POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_DISABLE , 1 => POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_RISE , 2 => POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_FALL , 3 => POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio26_disable (& self) -> bool { * self == POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio26_rise (& self) -> bool { * self == POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio26_fall (& self) -> bool { * self == POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio26_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO26` writer - Enables and configures edge detection polarity for DIO26."]
pub type POLARITY31_16_DIO26_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO26_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio26_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio26_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio26_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio26_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO26_A :: POLARITY31_16_DIO26_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO27` reader - Enables and configures edge detection polarity for DIO27."]
pub type POLARITY31_16_DIO27_R = crate :: FieldReader < POLARITY31_16_DIO27_A > ; # [doc = "Enables and configures edge detection polarity for DIO27.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO27_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO27_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO27_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO27_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO27_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO27_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO27_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO27_A { type Ux = u8 ; } impl POLARITY31_16_DIO27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO27_A { match self . bits { 0 => POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_DISABLE , 1 => POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_RISE , 2 => POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_FALL , 3 => POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio27_disable (& self) -> bool { * self == POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio27_rise (& self) -> bool { * self == POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio27_fall (& self) -> bool { * self == POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio27_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO27` writer - Enables and configures edge detection polarity for DIO27."]
pub type POLARITY31_16_DIO27_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO27_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio27_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio27_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio27_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio27_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO27_A :: POLARITY31_16_DIO27_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO28` reader - Enables and configures edge detection polarity for DIO28."]
pub type POLARITY31_16_DIO28_R = crate :: FieldReader < POLARITY31_16_DIO28_A > ; # [doc = "Enables and configures edge detection polarity for DIO28.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO28_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO28_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO28_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO28_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO28_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO28_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO28_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO28_A { type Ux = u8 ; } impl POLARITY31_16_DIO28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO28_A { match self . bits { 0 => POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_DISABLE , 1 => POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_RISE , 2 => POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_FALL , 3 => POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio28_disable (& self) -> bool { * self == POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio28_rise (& self) -> bool { * self == POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio28_fall (& self) -> bool { * self == POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio28_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO28` writer - Enables and configures edge detection polarity for DIO28."]
pub type POLARITY31_16_DIO28_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO28_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio28_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio28_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio28_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio28_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO28_A :: POLARITY31_16_DIO28_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO29` reader - Enables and configures edge detection polarity for DIO29."]
pub type POLARITY31_16_DIO29_R = crate :: FieldReader < POLARITY31_16_DIO29_A > ; # [doc = "Enables and configures edge detection polarity for DIO29.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO29_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO29_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO29_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO29_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO29_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO29_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO29_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO29_A { type Ux = u8 ; } impl POLARITY31_16_DIO29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO29_A { match self . bits { 0 => POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_DISABLE , 1 => POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_RISE , 2 => POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_FALL , 3 => POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio29_disable (& self) -> bool { * self == POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio29_rise (& self) -> bool { * self == POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio29_fall (& self) -> bool { * self == POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio29_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO29` writer - Enables and configures edge detection polarity for DIO29."]
pub type POLARITY31_16_DIO29_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO29_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio29_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio29_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio29_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio29_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO29_A :: POLARITY31_16_DIO29_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO30` reader - Enables and configures edge detection polarity for DIO30."]
pub type POLARITY31_16_DIO30_R = crate :: FieldReader < POLARITY31_16_DIO30_A > ; # [doc = "Enables and configures edge detection polarity for DIO30.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO30_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO30_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO30_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO30_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO30_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO30_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO30_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO30_A { type Ux = u8 ; } impl POLARITY31_16_DIO30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO30_A { match self . bits { 0 => POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_DISABLE , 1 => POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_RISE , 2 => POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_FALL , 3 => POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio30_disable (& self) -> bool { * self == POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio30_rise (& self) -> bool { * self == POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio30_fall (& self) -> bool { * self == POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio30_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO30` writer - Enables and configures edge detection polarity for DIO30."]
pub type POLARITY31_16_DIO30_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO30_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio30_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio30_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio30_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio30_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO30_A :: POLARITY31_16_DIO30_RISE_FALL) } } # [doc = "Field `POLARITY31_16_DIO31` reader - Enables and configures edge detection polarity for DIO31."]
pub type POLARITY31_16_DIO31_R = crate :: FieldReader < POLARITY31_16_DIO31_A > ; # [doc = "Enables and configures edge detection polarity for DIO31.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum POLARITY31_16_DIO31_A { # [doc = "0: DISABLE"]
POLARITY31_16_DIO31_DISABLE = 0 , # [doc = "1: RISE"]
POLARITY31_16_DIO31_RISE = 1 , # [doc = "2: FALL"]
POLARITY31_16_DIO31_FALL = 2 , # [doc = "3: RISE_FALL"]
POLARITY31_16_DIO31_RISE_FALL = 3 , } impl From < POLARITY31_16_DIO31_A > for u8 { # [inline (always)]
fn from (variant : POLARITY31_16_DIO31_A) -> Self { variant as _ } } impl crate :: FieldSpec for POLARITY31_16_DIO31_A { type Ux = u8 ; } impl POLARITY31_16_DIO31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> POLARITY31_16_DIO31_A { match self . bits { 0 => POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_DISABLE , 1 => POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_RISE , 2 => POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_FALL , 3 => POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_RISE_FALL , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_polarity31_16_dio31_disable (& self) -> bool { * self == POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_DISABLE } # [doc = "RISE"]
# [inline (always)]
pub fn is_polarity31_16_dio31_rise (& self) -> bool { * self == POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_RISE } # [doc = "FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio31_fall (& self) -> bool { * self == POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_FALL } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn is_polarity31_16_dio31_rise_fall (& self) -> bool { * self == POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_RISE_FALL } } # [doc = "Field `POLARITY31_16_DIO31` writer - Enables and configures edge detection polarity for DIO31."]
pub type POLARITY31_16_DIO31_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , POLARITY31_16_DIO31_A > ; impl < 'a , REG , const O : u8 > POLARITY31_16_DIO31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn polarity31_16_dio31_disable (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_DISABLE) } # [doc = "RISE"]
# [inline (always)]
pub fn polarity31_16_dio31_rise (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_RISE) } # [doc = "FALL"]
# [inline (always)]
pub fn polarity31_16_dio31_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_FALL) } # [doc = "RISE_FALL"]
# [inline (always)]
pub fn polarity31_16_dio31_rise_fall (self) -> & 'a mut crate :: W < REG > { self . variant (POLARITY31_16_DIO31_A :: POLARITY31_16_DIO31_RISE_FALL) } } impl R { # [doc = "Bits 0:1 - Enables and configures edge detection polarity for DIO16."]
# [inline (always)]
pub fn polarity31_16_dio16 (& self) -> POLARITY31_16_DIO16_R { POLARITY31_16_DIO16_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Enables and configures edge detection polarity for DIO17."]
# [inline (always)]
pub fn polarity31_16_dio17 (& self) -> POLARITY31_16_DIO17_R { POLARITY31_16_DIO17_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Enables and configures edge detection polarity for DIO18."]
# [inline (always)]
pub fn polarity31_16_dio18 (& self) -> POLARITY31_16_DIO18_R { POLARITY31_16_DIO18_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - Enables and configures edge detection polarity for DIO19."]
# [inline (always)]
pub fn polarity31_16_dio19 (& self) -> POLARITY31_16_DIO19_R { POLARITY31_16_DIO19_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - Enables and configures edge detection polarity for DIO20."]
# [inline (always)]
pub fn polarity31_16_dio20 (& self) -> POLARITY31_16_DIO20_R { POLARITY31_16_DIO20_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Enables and configures edge detection polarity for DIO21."]
# [inline (always)]
pub fn polarity31_16_dio21 (& self) -> POLARITY31_16_DIO21_R { POLARITY31_16_DIO21_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Enables and configures edge detection polarity for DIO22."]
# [inline (always)]
pub fn polarity31_16_dio22 (& self) -> POLARITY31_16_DIO22_R { POLARITY31_16_DIO22_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - Enables and configures edge detection polarity for DIO23."]
# [inline (always)]
pub fn polarity31_16_dio23 (& self) -> POLARITY31_16_DIO23_R { POLARITY31_16_DIO23_R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - Enables and configures edge detection polarity for DIO24."]
# [inline (always)]
pub fn polarity31_16_dio24 (& self) -> POLARITY31_16_DIO24_R { POLARITY31_16_DIO24_R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - Enables and configures edge detection polarity for DIO25."]
# [inline (always)]
pub fn polarity31_16_dio25 (& self) -> POLARITY31_16_DIO25_R { POLARITY31_16_DIO25_R :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - Enables and configures edge detection polarity for DIO26."]
# [inline (always)]
pub fn polarity31_16_dio26 (& self) -> POLARITY31_16_DIO26_R { POLARITY31_16_DIO26_R :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - Enables and configures edge detection polarity for DIO27."]
# [inline (always)]
pub fn polarity31_16_dio27 (& self) -> POLARITY31_16_DIO27_R { POLARITY31_16_DIO27_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:25 - Enables and configures edge detection polarity for DIO28."]
# [inline (always)]
pub fn polarity31_16_dio28 (& self) -> POLARITY31_16_DIO28_R { POLARITY31_16_DIO28_R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:27 - Enables and configures edge detection polarity for DIO29."]
# [inline (always)]
pub fn polarity31_16_dio29 (& self) -> POLARITY31_16_DIO29_R { POLARITY31_16_DIO29_R :: new (((self . bits >> 26) & 3) as u8) } # [doc = "Bits 28:29 - Enables and configures edge detection polarity for DIO30."]
# [inline (always)]
pub fn polarity31_16_dio30 (& self) -> POLARITY31_16_DIO30_R { POLARITY31_16_DIO30_R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - Enables and configures edge detection polarity for DIO31."]
# [inline (always)]
pub fn polarity31_16_dio31 (& self) -> POLARITY31_16_DIO31_R { POLARITY31_16_DIO31_R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Enables and configures edge detection polarity for DIO16."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio16 (& mut self) -> POLARITY31_16_DIO16_W < POLARITY31_16_SPEC , 0 > { POLARITY31_16_DIO16_W :: new (self) } # [doc = "Bits 2:3 - Enables and configures edge detection polarity for DIO17."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio17 (& mut self) -> POLARITY31_16_DIO17_W < POLARITY31_16_SPEC , 2 > { POLARITY31_16_DIO17_W :: new (self) } # [doc = "Bits 4:5 - Enables and configures edge detection polarity for DIO18."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio18 (& mut self) -> POLARITY31_16_DIO18_W < POLARITY31_16_SPEC , 4 > { POLARITY31_16_DIO18_W :: new (self) } # [doc = "Bits 6:7 - Enables and configures edge detection polarity for DIO19."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio19 (& mut self) -> POLARITY31_16_DIO19_W < POLARITY31_16_SPEC , 6 > { POLARITY31_16_DIO19_W :: new (self) } # [doc = "Bits 8:9 - Enables and configures edge detection polarity for DIO20."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio20 (& mut self) -> POLARITY31_16_DIO20_W < POLARITY31_16_SPEC , 8 > { POLARITY31_16_DIO20_W :: new (self) } # [doc = "Bits 10:11 - Enables and configures edge detection polarity for DIO21."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio21 (& mut self) -> POLARITY31_16_DIO21_W < POLARITY31_16_SPEC , 10 > { POLARITY31_16_DIO21_W :: new (self) } # [doc = "Bits 12:13 - Enables and configures edge detection polarity for DIO22."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio22 (& mut self) -> POLARITY31_16_DIO22_W < POLARITY31_16_SPEC , 12 > { POLARITY31_16_DIO22_W :: new (self) } # [doc = "Bits 14:15 - Enables and configures edge detection polarity for DIO23."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio23 (& mut self) -> POLARITY31_16_DIO23_W < POLARITY31_16_SPEC , 14 > { POLARITY31_16_DIO23_W :: new (self) } # [doc = "Bits 16:17 - Enables and configures edge detection polarity for DIO24."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio24 (& mut self) -> POLARITY31_16_DIO24_W < POLARITY31_16_SPEC , 16 > { POLARITY31_16_DIO24_W :: new (self) } # [doc = "Bits 18:19 - Enables and configures edge detection polarity for DIO25."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio25 (& mut self) -> POLARITY31_16_DIO25_W < POLARITY31_16_SPEC , 18 > { POLARITY31_16_DIO25_W :: new (self) } # [doc = "Bits 20:21 - Enables and configures edge detection polarity for DIO26."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio26 (& mut self) -> POLARITY31_16_DIO26_W < POLARITY31_16_SPEC , 20 > { POLARITY31_16_DIO26_W :: new (self) } # [doc = "Bits 22:23 - Enables and configures edge detection polarity for DIO27."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio27 (& mut self) -> POLARITY31_16_DIO27_W < POLARITY31_16_SPEC , 22 > { POLARITY31_16_DIO27_W :: new (self) } # [doc = "Bits 24:25 - Enables and configures edge detection polarity for DIO28."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio28 (& mut self) -> POLARITY31_16_DIO28_W < POLARITY31_16_SPEC , 24 > { POLARITY31_16_DIO28_W :: new (self) } # [doc = "Bits 26:27 - Enables and configures edge detection polarity for DIO29."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio29 (& mut self) -> POLARITY31_16_DIO29_W < POLARITY31_16_SPEC , 26 > { POLARITY31_16_DIO29_W :: new (self) } # [doc = "Bits 28:29 - Enables and configures edge detection polarity for DIO30."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio30 (& mut self) -> POLARITY31_16_DIO30_W < POLARITY31_16_SPEC , 28 > { POLARITY31_16_DIO30_W :: new (self) } # [doc = "Bits 30:31 - Enables and configures edge detection polarity for DIO31."]
# [inline (always)]
# [must_use]
pub fn polarity31_16_dio31 (& mut self) -> POLARITY31_16_DIO31_W < POLARITY31_16_SPEC , 30 > { POLARITY31_16_DIO31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Polarity 31 to 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`polarity31_16::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`polarity31_16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct POLARITY31_16_SPEC ; impl crate :: RegisterSpec for POLARITY31_16_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`polarity31_16::R`](R) reader structure"]
impl crate :: Readable for POLARITY31_16_SPEC { } # [doc = "`write(|w| ..)` method takes [`polarity31_16::W`](W) writer structure"]
impl crate :: Writable for POLARITY31_16_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets POLARITY31_16 to value 0"]
impl crate :: Resettable for POLARITY31_16_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL (rw) register accessor: FAST WAKE GLOBAL EN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`]
module"]
pub type CTL = crate :: Reg < ctl :: CTL_SPEC > ; # [doc = "FAST WAKE GLOBAL EN"]
pub mod ctl { # [doc = "Register `CTL` reader"]
pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"]
pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_FASTWAKEONLY` reader - FASTWAKEONLY for the global control of fastwake"]
pub type CTL_FASTWAKEONLY_R = crate :: BitReader < CTL_FASTWAKEONLY_A > ; # [doc = "FASTWAKEONLY for the global control of fastwake\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL_FASTWAKEONLY_A { # [doc = "0: NOT_GLOBAL_EN"]
CTL_FASTWAKEONLY_NOT_GLOBAL_EN = 0 , # [doc = "1: GLOBAL_EN"]
CTL_FASTWAKEONLY_GLOBAL_EN = 1 , } impl From < CTL_FASTWAKEONLY_A > for bool { # [inline (always)]
fn from (variant : CTL_FASTWAKEONLY_A) -> Self { variant as u8 != 0 } } impl CTL_FASTWAKEONLY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL_FASTWAKEONLY_A { match self . bits { false => CTL_FASTWAKEONLY_A :: CTL_FASTWAKEONLY_NOT_GLOBAL_EN , true => CTL_FASTWAKEONLY_A :: CTL_FASTWAKEONLY_GLOBAL_EN , } } # [doc = "NOT_GLOBAL_EN"]
# [inline (always)]
pub fn is_ctl_fastwakeonly_not_global_en (& self) -> bool { * self == CTL_FASTWAKEONLY_A :: CTL_FASTWAKEONLY_NOT_GLOBAL_EN } # [doc = "GLOBAL_EN"]
# [inline (always)]
pub fn is_ctl_fastwakeonly_global_en (& self) -> bool { * self == CTL_FASTWAKEONLY_A :: CTL_FASTWAKEONLY_GLOBAL_EN } } # [doc = "Field `CTL_FASTWAKEONLY` writer - FASTWAKEONLY for the global control of fastwake"]
pub type CTL_FASTWAKEONLY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_FASTWAKEONLY_A > ; impl < 'a , REG , const O : u8 > CTL_FASTWAKEONLY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOT_GLOBAL_EN"]
# [inline (always)]
pub fn ctl_fastwakeonly_not_global_en (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_FASTWAKEONLY_A :: CTL_FASTWAKEONLY_NOT_GLOBAL_EN) } # [doc = "GLOBAL_EN"]
# [inline (always)]
pub fn ctl_fastwakeonly_global_en (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_FASTWAKEONLY_A :: CTL_FASTWAKEONLY_GLOBAL_EN) } } impl R { # [doc = "Bit 0 - FASTWAKEONLY for the global control of fastwake"]
# [inline (always)]
pub fn ctl_fastwakeonly (& self) -> CTL_FASTWAKEONLY_R { CTL_FASTWAKEONLY_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - FASTWAKEONLY for the global control of fastwake"]
# [inline (always)]
# [must_use]
pub fn ctl_fastwakeonly (& mut self) -> CTL_FASTWAKEONLY_W < CTL_SPEC , 0 > { CTL_FASTWAKEONLY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "FAST WAKE GLOBAL EN\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"]
impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"]
impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0"]
impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FASTWAKE (rw) register accessor: FAST WAKE ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fastwake::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fastwake::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fastwake`]
module"]
pub type FASTWAKE = crate :: Reg < fastwake :: FASTWAKE_SPEC > ; # [doc = "FAST WAKE ENABLE"]
pub mod fastwake { # [doc = "Register `FASTWAKE` reader"]
pub type R = crate :: R < FASTWAKE_SPEC > ; # [doc = "Register `FASTWAKE` writer"]
pub type W = crate :: W < FASTWAKE_SPEC > ; # [doc = "Field `FASTWAKE_DIN0` reader - Enable fastwake feature for DIN0"]
pub type FASTWAKE_DIN0_R = crate :: BitReader < FASTWAKE_DIN0_A > ; # [doc = "Enable fastwake feature for DIN0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN0_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN0_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN0_ENABLE = 1 , } impl From < FASTWAKE_DIN0_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN0_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN0_A { match self . bits { false => FASTWAKE_DIN0_A :: FASTWAKE_DIN0_DISABLE , true => FASTWAKE_DIN0_A :: FASTWAKE_DIN0_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din0_disable (& self) -> bool { * self == FASTWAKE_DIN0_A :: FASTWAKE_DIN0_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din0_enable (& self) -> bool { * self == FASTWAKE_DIN0_A :: FASTWAKE_DIN0_ENABLE } } # [doc = "Field `FASTWAKE_DIN0` writer - Enable fastwake feature for DIN0"]
pub type FASTWAKE_DIN0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN0_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din0_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN0_A :: FASTWAKE_DIN0_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din0_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN0_A :: FASTWAKE_DIN0_ENABLE) } } # [doc = "Field `FASTWAKE_DIN1` reader - Enable fastwake feature for DIN1"]
pub type FASTWAKE_DIN1_R = crate :: BitReader < FASTWAKE_DIN1_A > ; # [doc = "Enable fastwake feature for DIN1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN1_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN1_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN1_ENABLE = 1 , } impl From < FASTWAKE_DIN1_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN1_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN1_A { match self . bits { false => FASTWAKE_DIN1_A :: FASTWAKE_DIN1_DISABLE , true => FASTWAKE_DIN1_A :: FASTWAKE_DIN1_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din1_disable (& self) -> bool { * self == FASTWAKE_DIN1_A :: FASTWAKE_DIN1_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din1_enable (& self) -> bool { * self == FASTWAKE_DIN1_A :: FASTWAKE_DIN1_ENABLE } } # [doc = "Field `FASTWAKE_DIN1` writer - Enable fastwake feature for DIN1"]
pub type FASTWAKE_DIN1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN1_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din1_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN1_A :: FASTWAKE_DIN1_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din1_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN1_A :: FASTWAKE_DIN1_ENABLE) } } # [doc = "Field `FASTWAKE_DIN2` reader - Enable fastwake feature for DIN2"]
pub type FASTWAKE_DIN2_R = crate :: BitReader < FASTWAKE_DIN2_A > ; # [doc = "Enable fastwake feature for DIN2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN2_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN2_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN2_ENABLE = 1 , } impl From < FASTWAKE_DIN2_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN2_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN2_A { match self . bits { false => FASTWAKE_DIN2_A :: FASTWAKE_DIN2_DISABLE , true => FASTWAKE_DIN2_A :: FASTWAKE_DIN2_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din2_disable (& self) -> bool { * self == FASTWAKE_DIN2_A :: FASTWAKE_DIN2_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din2_enable (& self) -> bool { * self == FASTWAKE_DIN2_A :: FASTWAKE_DIN2_ENABLE } } # [doc = "Field `FASTWAKE_DIN2` writer - Enable fastwake feature for DIN2"]
pub type FASTWAKE_DIN2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN2_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din2_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN2_A :: FASTWAKE_DIN2_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din2_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN2_A :: FASTWAKE_DIN2_ENABLE) } } # [doc = "Field `FASTWAKE_DIN3` reader - Enable fastwake feature for DIN3"]
pub type FASTWAKE_DIN3_R = crate :: BitReader < FASTWAKE_DIN3_A > ; # [doc = "Enable fastwake feature for DIN3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN3_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN3_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN3_ENABLE = 1 , } impl From < FASTWAKE_DIN3_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN3_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN3_A { match self . bits { false => FASTWAKE_DIN3_A :: FASTWAKE_DIN3_DISABLE , true => FASTWAKE_DIN3_A :: FASTWAKE_DIN3_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din3_disable (& self) -> bool { * self == FASTWAKE_DIN3_A :: FASTWAKE_DIN3_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din3_enable (& self) -> bool { * self == FASTWAKE_DIN3_A :: FASTWAKE_DIN3_ENABLE } } # [doc = "Field `FASTWAKE_DIN3` writer - Enable fastwake feature for DIN3"]
pub type FASTWAKE_DIN3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN3_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din3_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN3_A :: FASTWAKE_DIN3_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din3_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN3_A :: FASTWAKE_DIN3_ENABLE) } } # [doc = "Field `FASTWAKE_DIN4` reader - Enable fastwake feature for DIN4"]
pub type FASTWAKE_DIN4_R = crate :: BitReader < FASTWAKE_DIN4_A > ; # [doc = "Enable fastwake feature for DIN4\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN4_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN4_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN4_ENABLE = 1 , } impl From < FASTWAKE_DIN4_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN4_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN4_A { match self . bits { false => FASTWAKE_DIN4_A :: FASTWAKE_DIN4_DISABLE , true => FASTWAKE_DIN4_A :: FASTWAKE_DIN4_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din4_disable (& self) -> bool { * self == FASTWAKE_DIN4_A :: FASTWAKE_DIN4_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din4_enable (& self) -> bool { * self == FASTWAKE_DIN4_A :: FASTWAKE_DIN4_ENABLE } } # [doc = "Field `FASTWAKE_DIN4` writer - Enable fastwake feature for DIN4"]
pub type FASTWAKE_DIN4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN4_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din4_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN4_A :: FASTWAKE_DIN4_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din4_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN4_A :: FASTWAKE_DIN4_ENABLE) } } # [doc = "Field `FASTWAKE_DIN5` reader - Enable fastwake feature for DIN5"]
pub type FASTWAKE_DIN5_R = crate :: BitReader < FASTWAKE_DIN5_A > ; # [doc = "Enable fastwake feature for DIN5\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN5_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN5_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN5_ENABLE = 1 , } impl From < FASTWAKE_DIN5_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN5_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN5_A { match self . bits { false => FASTWAKE_DIN5_A :: FASTWAKE_DIN5_DISABLE , true => FASTWAKE_DIN5_A :: FASTWAKE_DIN5_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din5_disable (& self) -> bool { * self == FASTWAKE_DIN5_A :: FASTWAKE_DIN5_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din5_enable (& self) -> bool { * self == FASTWAKE_DIN5_A :: FASTWAKE_DIN5_ENABLE } } # [doc = "Field `FASTWAKE_DIN5` writer - Enable fastwake feature for DIN5"]
pub type FASTWAKE_DIN5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN5_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din5_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN5_A :: FASTWAKE_DIN5_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din5_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN5_A :: FASTWAKE_DIN5_ENABLE) } } # [doc = "Field `FASTWAKE_DIN6` reader - Enable fastwake feature for DIN6"]
pub type FASTWAKE_DIN6_R = crate :: BitReader < FASTWAKE_DIN6_A > ; # [doc = "Enable fastwake feature for DIN6\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN6_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN6_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN6_ENABLE = 1 , } impl From < FASTWAKE_DIN6_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN6_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN6_A { match self . bits { false => FASTWAKE_DIN6_A :: FASTWAKE_DIN6_DISABLE , true => FASTWAKE_DIN6_A :: FASTWAKE_DIN6_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din6_disable (& self) -> bool { * self == FASTWAKE_DIN6_A :: FASTWAKE_DIN6_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din6_enable (& self) -> bool { * self == FASTWAKE_DIN6_A :: FASTWAKE_DIN6_ENABLE } } # [doc = "Field `FASTWAKE_DIN6` writer - Enable fastwake feature for DIN6"]
pub type FASTWAKE_DIN6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN6_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din6_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN6_A :: FASTWAKE_DIN6_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din6_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN6_A :: FASTWAKE_DIN6_ENABLE) } } # [doc = "Field `FASTWAKE_DIN7` reader - Enable fastwake feature for DIN7"]
pub type FASTWAKE_DIN7_R = crate :: BitReader < FASTWAKE_DIN7_A > ; # [doc = "Enable fastwake feature for DIN7\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN7_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN7_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN7_ENABLE = 1 , } impl From < FASTWAKE_DIN7_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN7_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN7_A { match self . bits { false => FASTWAKE_DIN7_A :: FASTWAKE_DIN7_DISABLE , true => FASTWAKE_DIN7_A :: FASTWAKE_DIN7_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din7_disable (& self) -> bool { * self == FASTWAKE_DIN7_A :: FASTWAKE_DIN7_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din7_enable (& self) -> bool { * self == FASTWAKE_DIN7_A :: FASTWAKE_DIN7_ENABLE } } # [doc = "Field `FASTWAKE_DIN7` writer - Enable fastwake feature for DIN7"]
pub type FASTWAKE_DIN7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN7_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din7_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN7_A :: FASTWAKE_DIN7_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din7_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN7_A :: FASTWAKE_DIN7_ENABLE) } } # [doc = "Field `FASTWAKE_DIN8` reader - Enable fastwake feature for DIN8"]
pub type FASTWAKE_DIN8_R = crate :: BitReader < FASTWAKE_DIN8_A > ; # [doc = "Enable fastwake feature for DIN8\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN8_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN8_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN8_ENABLE = 1 , } impl From < FASTWAKE_DIN8_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN8_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN8_A { match self . bits { false => FASTWAKE_DIN8_A :: FASTWAKE_DIN8_DISABLE , true => FASTWAKE_DIN8_A :: FASTWAKE_DIN8_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din8_disable (& self) -> bool { * self == FASTWAKE_DIN8_A :: FASTWAKE_DIN8_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din8_enable (& self) -> bool { * self == FASTWAKE_DIN8_A :: FASTWAKE_DIN8_ENABLE } } # [doc = "Field `FASTWAKE_DIN8` writer - Enable fastwake feature for DIN8"]
pub type FASTWAKE_DIN8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN8_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din8_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN8_A :: FASTWAKE_DIN8_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din8_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN8_A :: FASTWAKE_DIN8_ENABLE) } } # [doc = "Field `FASTWAKE_DIN9` reader - Enable fastwake feature for DIN9"]
pub type FASTWAKE_DIN9_R = crate :: BitReader < FASTWAKE_DIN9_A > ; # [doc = "Enable fastwake feature for DIN9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN9_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN9_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN9_ENABLE = 1 , } impl From < FASTWAKE_DIN9_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN9_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN9_A { match self . bits { false => FASTWAKE_DIN9_A :: FASTWAKE_DIN9_DISABLE , true => FASTWAKE_DIN9_A :: FASTWAKE_DIN9_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din9_disable (& self) -> bool { * self == FASTWAKE_DIN9_A :: FASTWAKE_DIN9_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din9_enable (& self) -> bool { * self == FASTWAKE_DIN9_A :: FASTWAKE_DIN9_ENABLE } } # [doc = "Field `FASTWAKE_DIN9` writer - Enable fastwake feature for DIN9"]
pub type FASTWAKE_DIN9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN9_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din9_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN9_A :: FASTWAKE_DIN9_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din9_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN9_A :: FASTWAKE_DIN9_ENABLE) } } # [doc = "Field `FASTWAKE_DIN10` reader - Enable fastwake feature for DIN10"]
pub type FASTWAKE_DIN10_R = crate :: BitReader < FASTWAKE_DIN10_A > ; # [doc = "Enable fastwake feature for DIN10\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN10_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN10_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN10_ENABLE = 1 , } impl From < FASTWAKE_DIN10_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN10_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN10_A { match self . bits { false => FASTWAKE_DIN10_A :: FASTWAKE_DIN10_DISABLE , true => FASTWAKE_DIN10_A :: FASTWAKE_DIN10_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din10_disable (& self) -> bool { * self == FASTWAKE_DIN10_A :: FASTWAKE_DIN10_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din10_enable (& self) -> bool { * self == FASTWAKE_DIN10_A :: FASTWAKE_DIN10_ENABLE } } # [doc = "Field `FASTWAKE_DIN10` writer - Enable fastwake feature for DIN10"]
pub type FASTWAKE_DIN10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN10_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din10_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN10_A :: FASTWAKE_DIN10_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din10_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN10_A :: FASTWAKE_DIN10_ENABLE) } } # [doc = "Field `FASTWAKE_DIN11` reader - Enable fastwake feature for DIN11"]
pub type FASTWAKE_DIN11_R = crate :: BitReader < FASTWAKE_DIN11_A > ; # [doc = "Enable fastwake feature for DIN11\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN11_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN11_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN11_ENABLE = 1 , } impl From < FASTWAKE_DIN11_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN11_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN11_A { match self . bits { false => FASTWAKE_DIN11_A :: FASTWAKE_DIN11_DISABLE , true => FASTWAKE_DIN11_A :: FASTWAKE_DIN11_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din11_disable (& self) -> bool { * self == FASTWAKE_DIN11_A :: FASTWAKE_DIN11_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din11_enable (& self) -> bool { * self == FASTWAKE_DIN11_A :: FASTWAKE_DIN11_ENABLE } } # [doc = "Field `FASTWAKE_DIN11` writer - Enable fastwake feature for DIN11"]
pub type FASTWAKE_DIN11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN11_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din11_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN11_A :: FASTWAKE_DIN11_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din11_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN11_A :: FASTWAKE_DIN11_ENABLE) } } # [doc = "Field `FASTWAKE_DIN12` reader - Enable fastwake feature for DIN12"]
pub type FASTWAKE_DIN12_R = crate :: BitReader < FASTWAKE_DIN12_A > ; # [doc = "Enable fastwake feature for DIN12\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN12_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN12_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN12_ENABLE = 1 , } impl From < FASTWAKE_DIN12_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN12_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN12_A { match self . bits { false => FASTWAKE_DIN12_A :: FASTWAKE_DIN12_DISABLE , true => FASTWAKE_DIN12_A :: FASTWAKE_DIN12_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din12_disable (& self) -> bool { * self == FASTWAKE_DIN12_A :: FASTWAKE_DIN12_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din12_enable (& self) -> bool { * self == FASTWAKE_DIN12_A :: FASTWAKE_DIN12_ENABLE } } # [doc = "Field `FASTWAKE_DIN12` writer - Enable fastwake feature for DIN12"]
pub type FASTWAKE_DIN12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN12_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din12_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN12_A :: FASTWAKE_DIN12_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din12_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN12_A :: FASTWAKE_DIN12_ENABLE) } } # [doc = "Field `FASTWAKE_DIN13` reader - Enable fastwake feature for DIN13"]
pub type FASTWAKE_DIN13_R = crate :: BitReader < FASTWAKE_DIN13_A > ; # [doc = "Enable fastwake feature for DIN13\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN13_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN13_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN13_ENABLE = 1 , } impl From < FASTWAKE_DIN13_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN13_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN13_A { match self . bits { false => FASTWAKE_DIN13_A :: FASTWAKE_DIN13_DISABLE , true => FASTWAKE_DIN13_A :: FASTWAKE_DIN13_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din13_disable (& self) -> bool { * self == FASTWAKE_DIN13_A :: FASTWAKE_DIN13_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din13_enable (& self) -> bool { * self == FASTWAKE_DIN13_A :: FASTWAKE_DIN13_ENABLE } } # [doc = "Field `FASTWAKE_DIN13` writer - Enable fastwake feature for DIN13"]
pub type FASTWAKE_DIN13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN13_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din13_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN13_A :: FASTWAKE_DIN13_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din13_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN13_A :: FASTWAKE_DIN13_ENABLE) } } # [doc = "Field `FASTWAKE_DIN14` reader - Enable fastwake feature for DIN14"]
pub type FASTWAKE_DIN14_R = crate :: BitReader < FASTWAKE_DIN14_A > ; # [doc = "Enable fastwake feature for DIN14\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN14_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN14_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN14_ENABLE = 1 , } impl From < FASTWAKE_DIN14_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN14_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN14_A { match self . bits { false => FASTWAKE_DIN14_A :: FASTWAKE_DIN14_DISABLE , true => FASTWAKE_DIN14_A :: FASTWAKE_DIN14_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din14_disable (& self) -> bool { * self == FASTWAKE_DIN14_A :: FASTWAKE_DIN14_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din14_enable (& self) -> bool { * self == FASTWAKE_DIN14_A :: FASTWAKE_DIN14_ENABLE } } # [doc = "Field `FASTWAKE_DIN14` writer - Enable fastwake feature for DIN14"]
pub type FASTWAKE_DIN14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN14_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din14_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN14_A :: FASTWAKE_DIN14_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din14_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN14_A :: FASTWAKE_DIN14_ENABLE) } } # [doc = "Field `FASTWAKE_DIN15` reader - Enable fastwake feature for DIN15"]
pub type FASTWAKE_DIN15_R = crate :: BitReader < FASTWAKE_DIN15_A > ; # [doc = "Enable fastwake feature for DIN15\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN15_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN15_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN15_ENABLE = 1 , } impl From < FASTWAKE_DIN15_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN15_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN15_A { match self . bits { false => FASTWAKE_DIN15_A :: FASTWAKE_DIN15_DISABLE , true => FASTWAKE_DIN15_A :: FASTWAKE_DIN15_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din15_disable (& self) -> bool { * self == FASTWAKE_DIN15_A :: FASTWAKE_DIN15_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din15_enable (& self) -> bool { * self == FASTWAKE_DIN15_A :: FASTWAKE_DIN15_ENABLE } } # [doc = "Field `FASTWAKE_DIN15` writer - Enable fastwake feature for DIN15"]
pub type FASTWAKE_DIN15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN15_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din15_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN15_A :: FASTWAKE_DIN15_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din15_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN15_A :: FASTWAKE_DIN15_ENABLE) } } # [doc = "Field `FASTWAKE_DIN16` reader - Enable fastwake feature for DIN16"]
pub type FASTWAKE_DIN16_R = crate :: BitReader < FASTWAKE_DIN16_A > ; # [doc = "Enable fastwake feature for DIN16\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN16_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN16_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN16_ENABLE = 1 , } impl From < FASTWAKE_DIN16_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN16_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN16_A { match self . bits { false => FASTWAKE_DIN16_A :: FASTWAKE_DIN16_DISABLE , true => FASTWAKE_DIN16_A :: FASTWAKE_DIN16_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din16_disable (& self) -> bool { * self == FASTWAKE_DIN16_A :: FASTWAKE_DIN16_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din16_enable (& self) -> bool { * self == FASTWAKE_DIN16_A :: FASTWAKE_DIN16_ENABLE } } # [doc = "Field `FASTWAKE_DIN16` writer - Enable fastwake feature for DIN16"]
pub type FASTWAKE_DIN16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN16_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din16_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN16_A :: FASTWAKE_DIN16_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din16_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN16_A :: FASTWAKE_DIN16_ENABLE) } } # [doc = "Field `FASTWAKE_DIN17` reader - Enable fastwake feature for DIN17"]
pub type FASTWAKE_DIN17_R = crate :: BitReader < FASTWAKE_DIN17_A > ; # [doc = "Enable fastwake feature for DIN17\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN17_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN17_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN17_ENABLE = 1 , } impl From < FASTWAKE_DIN17_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN17_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN17_A { match self . bits { false => FASTWAKE_DIN17_A :: FASTWAKE_DIN17_DISABLE , true => FASTWAKE_DIN17_A :: FASTWAKE_DIN17_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din17_disable (& self) -> bool { * self == FASTWAKE_DIN17_A :: FASTWAKE_DIN17_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din17_enable (& self) -> bool { * self == FASTWAKE_DIN17_A :: FASTWAKE_DIN17_ENABLE } } # [doc = "Field `FASTWAKE_DIN17` writer - Enable fastwake feature for DIN17"]
pub type FASTWAKE_DIN17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN17_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din17_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN17_A :: FASTWAKE_DIN17_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din17_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN17_A :: FASTWAKE_DIN17_ENABLE) } } # [doc = "Field `FASTWAKE_DIN18` reader - Enable fastwake feature for DIN18"]
pub type FASTWAKE_DIN18_R = crate :: BitReader < FASTWAKE_DIN18_A > ; # [doc = "Enable fastwake feature for DIN18\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN18_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN18_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN18_ENABLE = 1 , } impl From < FASTWAKE_DIN18_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN18_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN18_A { match self . bits { false => FASTWAKE_DIN18_A :: FASTWAKE_DIN18_DISABLE , true => FASTWAKE_DIN18_A :: FASTWAKE_DIN18_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din18_disable (& self) -> bool { * self == FASTWAKE_DIN18_A :: FASTWAKE_DIN18_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din18_enable (& self) -> bool { * self == FASTWAKE_DIN18_A :: FASTWAKE_DIN18_ENABLE } } # [doc = "Field `FASTWAKE_DIN18` writer - Enable fastwake feature for DIN18"]
pub type FASTWAKE_DIN18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN18_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din18_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN18_A :: FASTWAKE_DIN18_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din18_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN18_A :: FASTWAKE_DIN18_ENABLE) } } # [doc = "Field `FASTWAKE_DIN19` reader - Enable fastwake feature for DIN19"]
pub type FASTWAKE_DIN19_R = crate :: BitReader < FASTWAKE_DIN19_A > ; # [doc = "Enable fastwake feature for DIN19\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN19_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN19_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN19_ENABLE = 1 , } impl From < FASTWAKE_DIN19_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN19_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN19_A { match self . bits { false => FASTWAKE_DIN19_A :: FASTWAKE_DIN19_DISABLE , true => FASTWAKE_DIN19_A :: FASTWAKE_DIN19_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din19_disable (& self) -> bool { * self == FASTWAKE_DIN19_A :: FASTWAKE_DIN19_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din19_enable (& self) -> bool { * self == FASTWAKE_DIN19_A :: FASTWAKE_DIN19_ENABLE } } # [doc = "Field `FASTWAKE_DIN19` writer - Enable fastwake feature for DIN19"]
pub type FASTWAKE_DIN19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN19_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din19_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN19_A :: FASTWAKE_DIN19_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din19_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN19_A :: FASTWAKE_DIN19_ENABLE) } } # [doc = "Field `FASTWAKE_DIN20` reader - Enable fastwake feature for DIN20"]
pub type FASTWAKE_DIN20_R = crate :: BitReader < FASTWAKE_DIN20_A > ; # [doc = "Enable fastwake feature for DIN20\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN20_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN20_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN20_ENABLE = 1 , } impl From < FASTWAKE_DIN20_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN20_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN20_A { match self . bits { false => FASTWAKE_DIN20_A :: FASTWAKE_DIN20_DISABLE , true => FASTWAKE_DIN20_A :: FASTWAKE_DIN20_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din20_disable (& self) -> bool { * self == FASTWAKE_DIN20_A :: FASTWAKE_DIN20_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din20_enable (& self) -> bool { * self == FASTWAKE_DIN20_A :: FASTWAKE_DIN20_ENABLE } } # [doc = "Field `FASTWAKE_DIN20` writer - Enable fastwake feature for DIN20"]
pub type FASTWAKE_DIN20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN20_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din20_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN20_A :: FASTWAKE_DIN20_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din20_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN20_A :: FASTWAKE_DIN20_ENABLE) } } # [doc = "Field `FASTWAKE_DIN21` reader - Enable fastwake feature for DIN21"]
pub type FASTWAKE_DIN21_R = crate :: BitReader < FASTWAKE_DIN21_A > ; # [doc = "Enable fastwake feature for DIN21\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN21_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN21_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN21_ENABLE = 1 , } impl From < FASTWAKE_DIN21_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN21_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN21_A { match self . bits { false => FASTWAKE_DIN21_A :: FASTWAKE_DIN21_DISABLE , true => FASTWAKE_DIN21_A :: FASTWAKE_DIN21_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din21_disable (& self) -> bool { * self == FASTWAKE_DIN21_A :: FASTWAKE_DIN21_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din21_enable (& self) -> bool { * self == FASTWAKE_DIN21_A :: FASTWAKE_DIN21_ENABLE } } # [doc = "Field `FASTWAKE_DIN21` writer - Enable fastwake feature for DIN21"]
pub type FASTWAKE_DIN21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN21_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din21_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN21_A :: FASTWAKE_DIN21_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din21_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN21_A :: FASTWAKE_DIN21_ENABLE) } } # [doc = "Field `FASTWAKE_DIN22` reader - Enable fastwake feature for DIN22"]
pub type FASTWAKE_DIN22_R = crate :: BitReader < FASTWAKE_DIN22_A > ; # [doc = "Enable fastwake feature for DIN22\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN22_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN22_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN22_ENABLE = 1 , } impl From < FASTWAKE_DIN22_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN22_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN22_A { match self . bits { false => FASTWAKE_DIN22_A :: FASTWAKE_DIN22_DISABLE , true => FASTWAKE_DIN22_A :: FASTWAKE_DIN22_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din22_disable (& self) -> bool { * self == FASTWAKE_DIN22_A :: FASTWAKE_DIN22_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din22_enable (& self) -> bool { * self == FASTWAKE_DIN22_A :: FASTWAKE_DIN22_ENABLE } } # [doc = "Field `FASTWAKE_DIN22` writer - Enable fastwake feature for DIN22"]
pub type FASTWAKE_DIN22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN22_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din22_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN22_A :: FASTWAKE_DIN22_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din22_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN22_A :: FASTWAKE_DIN22_ENABLE) } } # [doc = "Field `FASTWAKE_DIN23` reader - Enable fastwake feature for DIN23"]
pub type FASTWAKE_DIN23_R = crate :: BitReader < FASTWAKE_DIN23_A > ; # [doc = "Enable fastwake feature for DIN23\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN23_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN23_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN23_ENABLE = 1 , } impl From < FASTWAKE_DIN23_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN23_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN23_A { match self . bits { false => FASTWAKE_DIN23_A :: FASTWAKE_DIN23_DISABLE , true => FASTWAKE_DIN23_A :: FASTWAKE_DIN23_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din23_disable (& self) -> bool { * self == FASTWAKE_DIN23_A :: FASTWAKE_DIN23_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din23_enable (& self) -> bool { * self == FASTWAKE_DIN23_A :: FASTWAKE_DIN23_ENABLE } } # [doc = "Field `FASTWAKE_DIN23` writer - Enable fastwake feature for DIN23"]
pub type FASTWAKE_DIN23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN23_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din23_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN23_A :: FASTWAKE_DIN23_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din23_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN23_A :: FASTWAKE_DIN23_ENABLE) } } # [doc = "Field `FASTWAKE_DIN24` reader - Enable fastwake feature for DIN24"]
pub type FASTWAKE_DIN24_R = crate :: BitReader < FASTWAKE_DIN24_A > ; # [doc = "Enable fastwake feature for DIN24\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN24_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN24_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN24_ENABLE = 1 , } impl From < FASTWAKE_DIN24_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN24_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN24_A { match self . bits { false => FASTWAKE_DIN24_A :: FASTWAKE_DIN24_DISABLE , true => FASTWAKE_DIN24_A :: FASTWAKE_DIN24_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din24_disable (& self) -> bool { * self == FASTWAKE_DIN24_A :: FASTWAKE_DIN24_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din24_enable (& self) -> bool { * self == FASTWAKE_DIN24_A :: FASTWAKE_DIN24_ENABLE } } # [doc = "Field `FASTWAKE_DIN24` writer - Enable fastwake feature for DIN24"]
pub type FASTWAKE_DIN24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN24_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din24_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN24_A :: FASTWAKE_DIN24_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din24_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN24_A :: FASTWAKE_DIN24_ENABLE) } } # [doc = "Field `FASTWAKE_DIN25` reader - Enable fastwake feature for DIN25"]
pub type FASTWAKE_DIN25_R = crate :: BitReader < FASTWAKE_DIN25_A > ; # [doc = "Enable fastwake feature for DIN25\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN25_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN25_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN25_ENABLE = 1 , } impl From < FASTWAKE_DIN25_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN25_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN25_A { match self . bits { false => FASTWAKE_DIN25_A :: FASTWAKE_DIN25_DISABLE , true => FASTWAKE_DIN25_A :: FASTWAKE_DIN25_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din25_disable (& self) -> bool { * self == FASTWAKE_DIN25_A :: FASTWAKE_DIN25_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din25_enable (& self) -> bool { * self == FASTWAKE_DIN25_A :: FASTWAKE_DIN25_ENABLE } } # [doc = "Field `FASTWAKE_DIN25` writer - Enable fastwake feature for DIN25"]
pub type FASTWAKE_DIN25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN25_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din25_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN25_A :: FASTWAKE_DIN25_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din25_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN25_A :: FASTWAKE_DIN25_ENABLE) } } # [doc = "Field `FASTWAKE_DIN26` reader - Enable fastwake feature for DIN26"]
pub type FASTWAKE_DIN26_R = crate :: BitReader < FASTWAKE_DIN26_A > ; # [doc = "Enable fastwake feature for DIN26\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN26_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN26_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN26_ENABLE = 1 , } impl From < FASTWAKE_DIN26_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN26_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN26_A { match self . bits { false => FASTWAKE_DIN26_A :: FASTWAKE_DIN26_DISABLE , true => FASTWAKE_DIN26_A :: FASTWAKE_DIN26_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din26_disable (& self) -> bool { * self == FASTWAKE_DIN26_A :: FASTWAKE_DIN26_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din26_enable (& self) -> bool { * self == FASTWAKE_DIN26_A :: FASTWAKE_DIN26_ENABLE } } # [doc = "Field `FASTWAKE_DIN26` writer - Enable fastwake feature for DIN26"]
pub type FASTWAKE_DIN26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN26_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din26_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN26_A :: FASTWAKE_DIN26_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din26_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN26_A :: FASTWAKE_DIN26_ENABLE) } } # [doc = "Field `FASTWAKE_DIN27` reader - Enable fastwake feature for DIN27"]
pub type FASTWAKE_DIN27_R = crate :: BitReader < FASTWAKE_DIN27_A > ; # [doc = "Enable fastwake feature for DIN27\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN27_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN27_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN27_ENABLE = 1 , } impl From < FASTWAKE_DIN27_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN27_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN27_A { match self . bits { false => FASTWAKE_DIN27_A :: FASTWAKE_DIN27_DISABLE , true => FASTWAKE_DIN27_A :: FASTWAKE_DIN27_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din27_disable (& self) -> bool { * self == FASTWAKE_DIN27_A :: FASTWAKE_DIN27_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din27_enable (& self) -> bool { * self == FASTWAKE_DIN27_A :: FASTWAKE_DIN27_ENABLE } } # [doc = "Field `FASTWAKE_DIN27` writer - Enable fastwake feature for DIN27"]
pub type FASTWAKE_DIN27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN27_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din27_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN27_A :: FASTWAKE_DIN27_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din27_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN27_A :: FASTWAKE_DIN27_ENABLE) } } # [doc = "Field `FASTWAKE_DIN28` reader - Enable fastwake feature for DIN29"]
pub type FASTWAKE_DIN28_R = crate :: BitReader < FASTWAKE_DIN28_A > ; # [doc = "Enable fastwake feature for DIN29\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN28_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN28_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN28_ENABLE = 1 , } impl From < FASTWAKE_DIN28_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN28_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN28_A { match self . bits { false => FASTWAKE_DIN28_A :: FASTWAKE_DIN28_DISABLE , true => FASTWAKE_DIN28_A :: FASTWAKE_DIN28_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din28_disable (& self) -> bool { * self == FASTWAKE_DIN28_A :: FASTWAKE_DIN28_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din28_enable (& self) -> bool { * self == FASTWAKE_DIN28_A :: FASTWAKE_DIN28_ENABLE } } # [doc = "Field `FASTWAKE_DIN28` writer - Enable fastwake feature for DIN29"]
pub type FASTWAKE_DIN28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN28_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din28_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN28_A :: FASTWAKE_DIN28_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din28_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN28_A :: FASTWAKE_DIN28_ENABLE) } } # [doc = "Field `FASTWAKE_DIN29` reader - Enable fastwake feature for DIN29"]
pub type FASTWAKE_DIN29_R = crate :: BitReader < FASTWAKE_DIN29_A > ; # [doc = "Enable fastwake feature for DIN29\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN29_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN29_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN29_ENABLE = 1 , } impl From < FASTWAKE_DIN29_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN29_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN29_A { match self . bits { false => FASTWAKE_DIN29_A :: FASTWAKE_DIN29_DISABLE , true => FASTWAKE_DIN29_A :: FASTWAKE_DIN29_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din29_disable (& self) -> bool { * self == FASTWAKE_DIN29_A :: FASTWAKE_DIN29_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din29_enable (& self) -> bool { * self == FASTWAKE_DIN29_A :: FASTWAKE_DIN29_ENABLE } } # [doc = "Field `FASTWAKE_DIN29` writer - Enable fastwake feature for DIN29"]
pub type FASTWAKE_DIN29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN29_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din29_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN29_A :: FASTWAKE_DIN29_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din29_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN29_A :: FASTWAKE_DIN29_ENABLE) } } # [doc = "Field `FASTWAKE_DIN30` reader - Enable fastwake feature for DIN30"]
pub type FASTWAKE_DIN30_R = crate :: BitReader < FASTWAKE_DIN30_A > ; # [doc = "Enable fastwake feature for DIN30\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN30_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN30_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN30_ENABLE = 1 , } impl From < FASTWAKE_DIN30_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN30_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN30_A { match self . bits { false => FASTWAKE_DIN30_A :: FASTWAKE_DIN30_DISABLE , true => FASTWAKE_DIN30_A :: FASTWAKE_DIN30_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din30_disable (& self) -> bool { * self == FASTWAKE_DIN30_A :: FASTWAKE_DIN30_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din30_enable (& self) -> bool { * self == FASTWAKE_DIN30_A :: FASTWAKE_DIN30_ENABLE } } # [doc = "Field `FASTWAKE_DIN30` writer - Enable fastwake feature for DIN30"]
pub type FASTWAKE_DIN30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN30_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din30_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN30_A :: FASTWAKE_DIN30_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din30_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN30_A :: FASTWAKE_DIN30_ENABLE) } } # [doc = "Field `FASTWAKE_DIN31` reader - Enable fastwake feature for DIN31"]
pub type FASTWAKE_DIN31_R = crate :: BitReader < FASTWAKE_DIN31_A > ; # [doc = "Enable fastwake feature for DIN31\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FASTWAKE_DIN31_A { # [doc = "0: DISABLE"]
FASTWAKE_DIN31_DISABLE = 0 , # [doc = "1: ENABLE"]
FASTWAKE_DIN31_ENABLE = 1 , } impl From < FASTWAKE_DIN31_A > for bool { # [inline (always)]
fn from (variant : FASTWAKE_DIN31_A) -> Self { variant as u8 != 0 } } impl FASTWAKE_DIN31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FASTWAKE_DIN31_A { match self . bits { false => FASTWAKE_DIN31_A :: FASTWAKE_DIN31_DISABLE , true => FASTWAKE_DIN31_A :: FASTWAKE_DIN31_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_fastwake_din31_disable (& self) -> bool { * self == FASTWAKE_DIN31_A :: FASTWAKE_DIN31_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_fastwake_din31_enable (& self) -> bool { * self == FASTWAKE_DIN31_A :: FASTWAKE_DIN31_ENABLE } } # [doc = "Field `FASTWAKE_DIN31` writer - Enable fastwake feature for DIN31"]
pub type FASTWAKE_DIN31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FASTWAKE_DIN31_A > ; impl < 'a , REG , const O : u8 > FASTWAKE_DIN31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn fastwake_din31_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN31_A :: FASTWAKE_DIN31_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn fastwake_din31_enable (self) -> & 'a mut crate :: W < REG > { self . variant (FASTWAKE_DIN31_A :: FASTWAKE_DIN31_ENABLE) } } impl R { # [doc = "Bit 0 - Enable fastwake feature for DIN0"]
# [inline (always)]
pub fn fastwake_din0 (& self) -> FASTWAKE_DIN0_R { FASTWAKE_DIN0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable fastwake feature for DIN1"]
# [inline (always)]
pub fn fastwake_din1 (& self) -> FASTWAKE_DIN1_R { FASTWAKE_DIN1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable fastwake feature for DIN2"]
# [inline (always)]
pub fn fastwake_din2 (& self) -> FASTWAKE_DIN2_R { FASTWAKE_DIN2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable fastwake feature for DIN3"]
# [inline (always)]
pub fn fastwake_din3 (& self) -> FASTWAKE_DIN3_R { FASTWAKE_DIN3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable fastwake feature for DIN4"]
# [inline (always)]
pub fn fastwake_din4 (& self) -> FASTWAKE_DIN4_R { FASTWAKE_DIN4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable fastwake feature for DIN5"]
# [inline (always)]
pub fn fastwake_din5 (& self) -> FASTWAKE_DIN5_R { FASTWAKE_DIN5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable fastwake feature for DIN6"]
# [inline (always)]
pub fn fastwake_din6 (& self) -> FASTWAKE_DIN6_R { FASTWAKE_DIN6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable fastwake feature for DIN7"]
# [inline (always)]
pub fn fastwake_din7 (& self) -> FASTWAKE_DIN7_R { FASTWAKE_DIN7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable fastwake feature for DIN8"]
# [inline (always)]
pub fn fastwake_din8 (& self) -> FASTWAKE_DIN8_R { FASTWAKE_DIN8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable fastwake feature for DIN9"]
# [inline (always)]
pub fn fastwake_din9 (& self) -> FASTWAKE_DIN9_R { FASTWAKE_DIN9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Enable fastwake feature for DIN10"]
# [inline (always)]
pub fn fastwake_din10 (& self) -> FASTWAKE_DIN10_R { FASTWAKE_DIN10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable fastwake feature for DIN11"]
# [inline (always)]
pub fn fastwake_din11 (& self) -> FASTWAKE_DIN11_R { FASTWAKE_DIN11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable fastwake feature for DIN12"]
# [inline (always)]
pub fn fastwake_din12 (& self) -> FASTWAKE_DIN12_R { FASTWAKE_DIN12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable fastwake feature for DIN13"]
# [inline (always)]
pub fn fastwake_din13 (& self) -> FASTWAKE_DIN13_R { FASTWAKE_DIN13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable fastwake feature for DIN14"]
# [inline (always)]
pub fn fastwake_din14 (& self) -> FASTWAKE_DIN14_R { FASTWAKE_DIN14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable fastwake feature for DIN15"]
# [inline (always)]
pub fn fastwake_din15 (& self) -> FASTWAKE_DIN15_R { FASTWAKE_DIN15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable fastwake feature for DIN16"]
# [inline (always)]
pub fn fastwake_din16 (& self) -> FASTWAKE_DIN16_R { FASTWAKE_DIN16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Enable fastwake feature for DIN17"]
# [inline (always)]
pub fn fastwake_din17 (& self) -> FASTWAKE_DIN17_R { FASTWAKE_DIN17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Enable fastwake feature for DIN18"]
# [inline (always)]
pub fn fastwake_din18 (& self) -> FASTWAKE_DIN18_R { FASTWAKE_DIN18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Enable fastwake feature for DIN19"]
# [inline (always)]
pub fn fastwake_din19 (& self) -> FASTWAKE_DIN19_R { FASTWAKE_DIN19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - Enable fastwake feature for DIN20"]
# [inline (always)]
pub fn fastwake_din20 (& self) -> FASTWAKE_DIN20_R { FASTWAKE_DIN20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Enable fastwake feature for DIN21"]
# [inline (always)]
pub fn fastwake_din21 (& self) -> FASTWAKE_DIN21_R { FASTWAKE_DIN21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Enable fastwake feature for DIN22"]
# [inline (always)]
pub fn fastwake_din22 (& self) -> FASTWAKE_DIN22_R { FASTWAKE_DIN22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Enable fastwake feature for DIN23"]
# [inline (always)]
pub fn fastwake_din23 (& self) -> FASTWAKE_DIN23_R { FASTWAKE_DIN23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - Enable fastwake feature for DIN24"]
# [inline (always)]
pub fn fastwake_din24 (& self) -> FASTWAKE_DIN24_R { FASTWAKE_DIN24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Enable fastwake feature for DIN25"]
# [inline (always)]
pub fn fastwake_din25 (& self) -> FASTWAKE_DIN25_R { FASTWAKE_DIN25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - Enable fastwake feature for DIN26"]
# [inline (always)]
pub fn fastwake_din26 (& self) -> FASTWAKE_DIN26_R { FASTWAKE_DIN26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Enable fastwake feature for DIN27"]
# [inline (always)]
pub fn fastwake_din27 (& self) -> FASTWAKE_DIN27_R { FASTWAKE_DIN27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Enable fastwake feature for DIN29"]
# [inline (always)]
pub fn fastwake_din28 (& self) -> FASTWAKE_DIN28_R { FASTWAKE_DIN28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Enable fastwake feature for DIN29"]
# [inline (always)]
pub fn fastwake_din29 (& self) -> FASTWAKE_DIN29_R { FASTWAKE_DIN29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Enable fastwake feature for DIN30"]
# [inline (always)]
pub fn fastwake_din30 (& self) -> FASTWAKE_DIN30_R { FASTWAKE_DIN30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Enable fastwake feature for DIN31"]
# [inline (always)]
pub fn fastwake_din31 (& self) -> FASTWAKE_DIN31_R { FASTWAKE_DIN31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable fastwake feature for DIN0"]
# [inline (always)]
# [must_use]
pub fn fastwake_din0 (& mut self) -> FASTWAKE_DIN0_W < FASTWAKE_SPEC , 0 > { FASTWAKE_DIN0_W :: new (self) } # [doc = "Bit 1 - Enable fastwake feature for DIN1"]
# [inline (always)]
# [must_use]
pub fn fastwake_din1 (& mut self) -> FASTWAKE_DIN1_W < FASTWAKE_SPEC , 1 > { FASTWAKE_DIN1_W :: new (self) } # [doc = "Bit 2 - Enable fastwake feature for DIN2"]
# [inline (always)]
# [must_use]
pub fn fastwake_din2 (& mut self) -> FASTWAKE_DIN2_W < FASTWAKE_SPEC , 2 > { FASTWAKE_DIN2_W :: new (self) } # [doc = "Bit 3 - Enable fastwake feature for DIN3"]
# [inline (always)]
# [must_use]
pub fn fastwake_din3 (& mut self) -> FASTWAKE_DIN3_W < FASTWAKE_SPEC , 3 > { FASTWAKE_DIN3_W :: new (self) } # [doc = "Bit 4 - Enable fastwake feature for DIN4"]
# [inline (always)]
# [must_use]
pub fn fastwake_din4 (& mut self) -> FASTWAKE_DIN4_W < FASTWAKE_SPEC , 4 > { FASTWAKE_DIN4_W :: new (self) } # [doc = "Bit 5 - Enable fastwake feature for DIN5"]
# [inline (always)]
# [must_use]
pub fn fastwake_din5 (& mut self) -> FASTWAKE_DIN5_W < FASTWAKE_SPEC , 5 > { FASTWAKE_DIN5_W :: new (self) } # [doc = "Bit 6 - Enable fastwake feature for DIN6"]
# [inline (always)]
# [must_use]
pub fn fastwake_din6 (& mut self) -> FASTWAKE_DIN6_W < FASTWAKE_SPEC , 6 > { FASTWAKE_DIN6_W :: new (self) } # [doc = "Bit 7 - Enable fastwake feature for DIN7"]
# [inline (always)]
# [must_use]
pub fn fastwake_din7 (& mut self) -> FASTWAKE_DIN7_W < FASTWAKE_SPEC , 7 > { FASTWAKE_DIN7_W :: new (self) } # [doc = "Bit 8 - Enable fastwake feature for DIN8"]
# [inline (always)]
# [must_use]
pub fn fastwake_din8 (& mut self) -> FASTWAKE_DIN8_W < FASTWAKE_SPEC , 8 > { FASTWAKE_DIN8_W :: new (self) } # [doc = "Bit 9 - Enable fastwake feature for DIN9"]
# [inline (always)]
# [must_use]
pub fn fastwake_din9 (& mut self) -> FASTWAKE_DIN9_W < FASTWAKE_SPEC , 9 > { FASTWAKE_DIN9_W :: new (self) } # [doc = "Bit 10 - Enable fastwake feature for DIN10"]
# [inline (always)]
# [must_use]
pub fn fastwake_din10 (& mut self) -> FASTWAKE_DIN10_W < FASTWAKE_SPEC , 10 > { FASTWAKE_DIN10_W :: new (self) } # [doc = "Bit 11 - Enable fastwake feature for DIN11"]
# [inline (always)]
# [must_use]
pub fn fastwake_din11 (& mut self) -> FASTWAKE_DIN11_W < FASTWAKE_SPEC , 11 > { FASTWAKE_DIN11_W :: new (self) } # [doc = "Bit 12 - Enable fastwake feature for DIN12"]
# [inline (always)]
# [must_use]
pub fn fastwake_din12 (& mut self) -> FASTWAKE_DIN12_W < FASTWAKE_SPEC , 12 > { FASTWAKE_DIN12_W :: new (self) } # [doc = "Bit 13 - Enable fastwake feature for DIN13"]
# [inline (always)]
# [must_use]
pub fn fastwake_din13 (& mut self) -> FASTWAKE_DIN13_W < FASTWAKE_SPEC , 13 > { FASTWAKE_DIN13_W :: new (self) } # [doc = "Bit 14 - Enable fastwake feature for DIN14"]
# [inline (always)]
# [must_use]
pub fn fastwake_din14 (& mut self) -> FASTWAKE_DIN14_W < FASTWAKE_SPEC , 14 > { FASTWAKE_DIN14_W :: new (self) } # [doc = "Bit 15 - Enable fastwake feature for DIN15"]
# [inline (always)]
# [must_use]
pub fn fastwake_din15 (& mut self) -> FASTWAKE_DIN15_W < FASTWAKE_SPEC , 15 > { FASTWAKE_DIN15_W :: new (self) } # [doc = "Bit 16 - Enable fastwake feature for DIN16"]
# [inline (always)]
# [must_use]
pub fn fastwake_din16 (& mut self) -> FASTWAKE_DIN16_W < FASTWAKE_SPEC , 16 > { FASTWAKE_DIN16_W :: new (self) } # [doc = "Bit 17 - Enable fastwake feature for DIN17"]
# [inline (always)]
# [must_use]
pub fn fastwake_din17 (& mut self) -> FASTWAKE_DIN17_W < FASTWAKE_SPEC , 17 > { FASTWAKE_DIN17_W :: new (self) } # [doc = "Bit 18 - Enable fastwake feature for DIN18"]
# [inline (always)]
# [must_use]
pub fn fastwake_din18 (& mut self) -> FASTWAKE_DIN18_W < FASTWAKE_SPEC , 18 > { FASTWAKE_DIN18_W :: new (self) } # [doc = "Bit 19 - Enable fastwake feature for DIN19"]
# [inline (always)]
# [must_use]
pub fn fastwake_din19 (& mut self) -> FASTWAKE_DIN19_W < FASTWAKE_SPEC , 19 > { FASTWAKE_DIN19_W :: new (self) } # [doc = "Bit 20 - Enable fastwake feature for DIN20"]
# [inline (always)]
# [must_use]
pub fn fastwake_din20 (& mut self) -> FASTWAKE_DIN20_W < FASTWAKE_SPEC , 20 > { FASTWAKE_DIN20_W :: new (self) } # [doc = "Bit 21 - Enable fastwake feature for DIN21"]
# [inline (always)]
# [must_use]
pub fn fastwake_din21 (& mut self) -> FASTWAKE_DIN21_W < FASTWAKE_SPEC , 21 > { FASTWAKE_DIN21_W :: new (self) } # [doc = "Bit 22 - Enable fastwake feature for DIN22"]
# [inline (always)]
# [must_use]
pub fn fastwake_din22 (& mut self) -> FASTWAKE_DIN22_W < FASTWAKE_SPEC , 22 > { FASTWAKE_DIN22_W :: new (self) } # [doc = "Bit 23 - Enable fastwake feature for DIN23"]
# [inline (always)]
# [must_use]
pub fn fastwake_din23 (& mut self) -> FASTWAKE_DIN23_W < FASTWAKE_SPEC , 23 > { FASTWAKE_DIN23_W :: new (self) } # [doc = "Bit 24 - Enable fastwake feature for DIN24"]
# [inline (always)]
# [must_use]
pub fn fastwake_din24 (& mut self) -> FASTWAKE_DIN24_W < FASTWAKE_SPEC , 24 > { FASTWAKE_DIN24_W :: new (self) } # [doc = "Bit 25 - Enable fastwake feature for DIN25"]
# [inline (always)]
# [must_use]
pub fn fastwake_din25 (& mut self) -> FASTWAKE_DIN25_W < FASTWAKE_SPEC , 25 > { FASTWAKE_DIN25_W :: new (self) } # [doc = "Bit 26 - Enable fastwake feature for DIN26"]
# [inline (always)]
# [must_use]
pub fn fastwake_din26 (& mut self) -> FASTWAKE_DIN26_W < FASTWAKE_SPEC , 26 > { FASTWAKE_DIN26_W :: new (self) } # [doc = "Bit 27 - Enable fastwake feature for DIN27"]
# [inline (always)]
# [must_use]
pub fn fastwake_din27 (& mut self) -> FASTWAKE_DIN27_W < FASTWAKE_SPEC , 27 > { FASTWAKE_DIN27_W :: new (self) } # [doc = "Bit 28 - Enable fastwake feature for DIN29"]
# [inline (always)]
# [must_use]
pub fn fastwake_din28 (& mut self) -> FASTWAKE_DIN28_W < FASTWAKE_SPEC , 28 > { FASTWAKE_DIN28_W :: new (self) } # [doc = "Bit 29 - Enable fastwake feature for DIN29"]
# [inline (always)]
# [must_use]
pub fn fastwake_din29 (& mut self) -> FASTWAKE_DIN29_W < FASTWAKE_SPEC , 29 > { FASTWAKE_DIN29_W :: new (self) } # [doc = "Bit 30 - Enable fastwake feature for DIN30"]
# [inline (always)]
# [must_use]
pub fn fastwake_din30 (& mut self) -> FASTWAKE_DIN30_W < FASTWAKE_SPEC , 30 > { FASTWAKE_DIN30_W :: new (self) } # [doc = "Bit 31 - Enable fastwake feature for DIN31"]
# [inline (always)]
# [must_use]
pub fn fastwake_din31 (& mut self) -> FASTWAKE_DIN31_W < FASTWAKE_SPEC , 31 > { FASTWAKE_DIN31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "FAST WAKE ENABLE\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fastwake::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fastwake::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FASTWAKE_SPEC ; impl crate :: RegisterSpec for FASTWAKE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fastwake::R`](R) reader structure"]
impl crate :: Readable for FASTWAKE_SPEC { } # [doc = "`write(|w| ..)` method takes [`fastwake::W`](W) writer structure"]
impl crate :: Writable for FASTWAKE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FASTWAKE to value 0"]
impl crate :: Resettable for FASTWAKE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SUB0CFG (rw) register accessor: Subscriber 0 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sub0cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sub0cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub0cfg`]
module"]
pub type SUB0CFG = crate :: Reg < sub0cfg :: SUB0CFG_SPEC > ; # [doc = "Subscriber 0 configuration"]
pub mod sub0cfg { # [doc = "Register `SUB0CFG` reader"]
pub type R = crate :: R < SUB0CFG_SPEC > ; # [doc = "Register `SUB0CFG` writer"]
pub type W = crate :: W < SUB0CFG_SPEC > ; # [doc = "Field `SUB0CFG_ENABLE` reader - This bit is used to enable subscriber 0 event."]
pub type SUB0CFG_ENABLE_R = crate :: BitReader < SUB0CFG_ENABLE_A > ; # [doc = "This bit is used to enable subscriber 0 event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SUB0CFG_ENABLE_A { # [doc = "0: CLR"]
SUB0CFG_ENABLE_CLR = 0 , # [doc = "1: SET"]
SUB0CFG_ENABLE_SET = 1 , } impl From < SUB0CFG_ENABLE_A > for bool { # [inline (always)]
fn from (variant : SUB0CFG_ENABLE_A) -> Self { variant as u8 != 0 } } impl SUB0CFG_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SUB0CFG_ENABLE_A { match self . bits { false => SUB0CFG_ENABLE_A :: SUB0CFG_ENABLE_CLR , true => SUB0CFG_ENABLE_A :: SUB0CFG_ENABLE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_sub0cfg_enable_clr (& self) -> bool { * self == SUB0CFG_ENABLE_A :: SUB0CFG_ENABLE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_sub0cfg_enable_set (& self) -> bool { * self == SUB0CFG_ENABLE_A :: SUB0CFG_ENABLE_SET } } # [doc = "Field `SUB0CFG_ENABLE` writer - This bit is used to enable subscriber 0 event."]
pub type SUB0CFG_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SUB0CFG_ENABLE_A > ; impl < 'a , REG , const O : u8 > SUB0CFG_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn sub0cfg_enable_clr (self) -> & 'a mut crate :: W < REG > { self . variant (SUB0CFG_ENABLE_A :: SUB0CFG_ENABLE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn sub0cfg_enable_set (self) -> & 'a mut crate :: W < REG > { self . variant (SUB0CFG_ENABLE_A :: SUB0CFG_ENABLE_SET) } } # [doc = "Field `SUB0CFG_OUTPOLICY` reader - These bits configure the output policy for subscriber 0 event."]
pub type SUB0CFG_OUTPOLICY_R = crate :: FieldReader < SUB0CFG_OUTPOLICY_A > ; # [doc = "These bits configure the output policy for subscriber 0 event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SUB0CFG_OUTPOLICY_A { # [doc = "0: SET"]
SUB0CFG_OUTPOLICY_SET = 0 , # [doc = "1: CLR"]
SUB0CFG_OUTPOLICY_CLR = 1 , # [doc = "2: TOGGLE"]
SUB0CFG_OUTPOLICY_TOGGLE = 2 , } impl From < SUB0CFG_OUTPOLICY_A > for u8 { # [inline (always)]
fn from (variant : SUB0CFG_OUTPOLICY_A) -> Self { variant as _ } } impl crate :: FieldSpec for SUB0CFG_OUTPOLICY_A { type Ux = u8 ; } impl SUB0CFG_OUTPOLICY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SUB0CFG_OUTPOLICY_A > { match self . bits { 0 => Some (SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_SET) , 1 => Some (SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_CLR) , 2 => Some (SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_TOGGLE) , _ => None , } } # [doc = "SET"]
# [inline (always)]
pub fn is_sub0cfg_outpolicy_set (& self) -> bool { * self == SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_SET } # [doc = "CLR"]
# [inline (always)]
pub fn is_sub0cfg_outpolicy_clr (& self) -> bool { * self == SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_CLR } # [doc = "TOGGLE"]
# [inline (always)]
pub fn is_sub0cfg_outpolicy_toggle (& self) -> bool { * self == SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_TOGGLE } } # [doc = "Field `SUB0CFG_OUTPOLICY` writer - These bits configure the output policy for subscriber 0 event."]
pub type SUB0CFG_OUTPOLICY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , SUB0CFG_OUTPOLICY_A > ; impl < 'a , REG , const O : u8 > SUB0CFG_OUTPOLICY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SET"]
# [inline (always)]
pub fn sub0cfg_outpolicy_set (self) -> & 'a mut crate :: W < REG > { self . variant (SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_SET) } # [doc = "CLR"]
# [inline (always)]
pub fn sub0cfg_outpolicy_clr (self) -> & 'a mut crate :: W < REG > { self . variant (SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_CLR) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn sub0cfg_outpolicy_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (SUB0CFG_OUTPOLICY_A :: SUB0CFG_OUTPOLICY_TOGGLE) } } # [doc = "Field `SUB0CFG_INDEX` reader - Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"]
pub type SUB0CFG_INDEX_R = crate :: FieldReader < SUB0CFG_INDEX_A > ; # [doc = "Indicates the specific bit among lower 16 bits that is targeted by the subscriber action\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SUB0CFG_INDEX_A { # [doc = "0: MIN"]
SUB0CFG_INDEX_MIN = 0 , # [doc = "15: MAX"]
SUB0CFG_INDEX_MAX = 15 , } impl From < SUB0CFG_INDEX_A > for u8 { # [inline (always)]
fn from (variant : SUB0CFG_INDEX_A) -> Self { variant as _ } } impl crate :: FieldSpec for SUB0CFG_INDEX_A { type Ux = u8 ; } impl SUB0CFG_INDEX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SUB0CFG_INDEX_A > { match self . bits { 0 => Some (SUB0CFG_INDEX_A :: SUB0CFG_INDEX_MIN) , 15 => Some (SUB0CFG_INDEX_A :: SUB0CFG_INDEX_MAX) , _ => None , } } # [doc = "MIN"]
# [inline (always)]
pub fn is_sub0cfg_index_min (& self) -> bool { * self == SUB0CFG_INDEX_A :: SUB0CFG_INDEX_MIN } # [doc = "MAX"]
# [inline (always)]
pub fn is_sub0cfg_index_max (& self) -> bool { * self == SUB0CFG_INDEX_A :: SUB0CFG_INDEX_MAX } } # [doc = "Field `SUB0CFG_INDEX` writer - Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"]
pub type SUB0CFG_INDEX_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , SUB0CFG_INDEX_A > ; impl < 'a , REG , const O : u8 > SUB0CFG_INDEX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "MIN"]
# [inline (always)]
pub fn sub0cfg_index_min (self) -> & 'a mut crate :: W < REG > { self . variant (SUB0CFG_INDEX_A :: SUB0CFG_INDEX_MIN) } # [doc = "MAX"]
# [inline (always)]
pub fn sub0cfg_index_max (self) -> & 'a mut crate :: W < REG > { self . variant (SUB0CFG_INDEX_A :: SUB0CFG_INDEX_MAX) } } impl R { # [doc = "Bit 0 - This bit is used to enable subscriber 0 event."]
# [inline (always)]
pub fn sub0cfg_enable (& self) -> SUB0CFG_ENABLE_R { SUB0CFG_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 8:9 - These bits configure the output policy for subscriber 0 event."]
# [inline (always)]
pub fn sub0cfg_outpolicy (& self) -> SUB0CFG_OUTPOLICY_R { SUB0CFG_OUTPOLICY_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 16:19 - Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"]
# [inline (always)]
pub fn sub0cfg_index (& self) -> SUB0CFG_INDEX_R { SUB0CFG_INDEX_R :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - This bit is used to enable subscriber 0 event."]
# [inline (always)]
# [must_use]
pub fn sub0cfg_enable (& mut self) -> SUB0CFG_ENABLE_W < SUB0CFG_SPEC , 0 > { SUB0CFG_ENABLE_W :: new (self) } # [doc = "Bits 8:9 - These bits configure the output policy for subscriber 0 event."]
# [inline (always)]
# [must_use]
pub fn sub0cfg_outpolicy (& mut self) -> SUB0CFG_OUTPOLICY_W < SUB0CFG_SPEC , 8 > { SUB0CFG_OUTPOLICY_W :: new (self) } # [doc = "Bits 16:19 - Indicates the specific bit among lower 16 bits that is targeted by the subscriber action"]
# [inline (always)]
# [must_use]
pub fn sub0cfg_index (& mut self) -> SUB0CFG_INDEX_W < SUB0CFG_SPEC , 16 > { SUB0CFG_INDEX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber 0 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sub0cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sub0cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SUB0CFG_SPEC ; impl crate :: RegisterSpec for SUB0CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sub0cfg::R`](R) reader structure"]
impl crate :: Readable for SUB0CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`sub0cfg::W`](W) writer structure"]
impl crate :: Writable for SUB0CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SUB0CFG to value 0"]
impl crate :: Resettable for SUB0CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FILTEREN15_0 (rw) register accessor: Filter Enable 15 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filteren15_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filteren15_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filteren15_0`]
module"]
pub type FILTEREN15_0 = crate :: Reg < filteren15_0 :: FILTEREN15_0_SPEC > ; # [doc = "Filter Enable 15 to 0"]
pub mod filteren15_0 { # [doc = "Register `FILTEREN15_0` reader"]
pub type R = crate :: R < FILTEREN15_0_SPEC > ; # [doc = "Register `FILTEREN15_0` writer"]
pub type W = crate :: W < FILTEREN15_0_SPEC > ; # [doc = "Field `FILTEREN15_0_DIN0` reader - Programmable counter length of digital glitch filter for DIN0"]
pub type FILTEREN15_0_DIN0_R = crate :: FieldReader < FILTEREN15_0_DIN0_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN0_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN0_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN0_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN0_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN0_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN0_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN0_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN0_A { type Ux = u8 ; } impl FILTEREN15_0_DIN0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN0_A { match self . bits { 0 => FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_DISABLE , 1 => FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_ONE_CYCLE , 2 => FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_THREE_CYCLE , 3 => FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din0_disable (& self) -> bool { * self == FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din0_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din0_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din0_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN0` writer - Programmable counter length of digital glitch filter for DIN0"]
pub type FILTEREN15_0_DIN0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN0_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din0_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din0_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din0_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din0_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN0_A :: FILTEREN15_0_DIN0_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN1` reader - Programmable counter length of digital glitch filter for DIN1"]
pub type FILTEREN15_0_DIN1_R = crate :: FieldReader < FILTEREN15_0_DIN1_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN1_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN1_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN1_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN1_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN1_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN1_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN1_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN1_A { type Ux = u8 ; } impl FILTEREN15_0_DIN1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN1_A { match self . bits { 0 => FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_DISABLE , 1 => FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_ONE_CYCLE , 2 => FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_THREE_CYCLE , 3 => FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din1_disable (& self) -> bool { * self == FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din1_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din1_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din1_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN1` writer - Programmable counter length of digital glitch filter for DIN1"]
pub type FILTEREN15_0_DIN1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN1_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din1_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din1_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din1_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din1_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN1_A :: FILTEREN15_0_DIN1_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN2` reader - Programmable counter length of digital glitch filter for DIN2"]
pub type FILTEREN15_0_DIN2_R = crate :: FieldReader < FILTEREN15_0_DIN2_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN2_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN2_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN2_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN2_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN2_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN2_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN2_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN2_A { type Ux = u8 ; } impl FILTEREN15_0_DIN2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN2_A { match self . bits { 0 => FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_DISABLE , 1 => FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_ONE_CYCLE , 2 => FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_THREE_CYCLE , 3 => FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din2_disable (& self) -> bool { * self == FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din2_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din2_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din2_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN2` writer - Programmable counter length of digital glitch filter for DIN2"]
pub type FILTEREN15_0_DIN2_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN2_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din2_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din2_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din2_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din2_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN2_A :: FILTEREN15_0_DIN2_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN3` reader - Programmable counter length of digital glitch filter for DIN3"]
pub type FILTEREN15_0_DIN3_R = crate :: FieldReader < FILTEREN15_0_DIN3_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN3_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN3_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN3_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN3_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN3_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN3_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN3_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN3_A { type Ux = u8 ; } impl FILTEREN15_0_DIN3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN3_A { match self . bits { 0 => FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_DISABLE , 1 => FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_ONE_CYCLE , 2 => FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_THREE_CYCLE , 3 => FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din3_disable (& self) -> bool { * self == FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din3_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din3_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din3_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN3` writer - Programmable counter length of digital glitch filter for DIN3"]
pub type FILTEREN15_0_DIN3_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN3_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din3_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din3_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din3_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din3_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN3_A :: FILTEREN15_0_DIN3_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN4` reader - Programmable counter length of digital glitch filter for DIN4"]
pub type FILTEREN15_0_DIN4_R = crate :: FieldReader < FILTEREN15_0_DIN4_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN4\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN4_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN4_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN4_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN4_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN4_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN4_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN4_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN4_A { type Ux = u8 ; } impl FILTEREN15_0_DIN4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN4_A { match self . bits { 0 => FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_DISABLE , 1 => FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_ONE_CYCLE , 2 => FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_THREE_CYCLE , 3 => FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din4_disable (& self) -> bool { * self == FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din4_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din4_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din4_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN4` writer - Programmable counter length of digital glitch filter for DIN4"]
pub type FILTEREN15_0_DIN4_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN4_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din4_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din4_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din4_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din4_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN4_A :: FILTEREN15_0_DIN4_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN5` reader - Programmable counter length of digital glitch filter for DIN5"]
pub type FILTEREN15_0_DIN5_R = crate :: FieldReader < FILTEREN15_0_DIN5_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN5\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN5_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN5_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN5_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN5_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN5_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN5_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN5_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN5_A { type Ux = u8 ; } impl FILTEREN15_0_DIN5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN5_A { match self . bits { 0 => FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_DISABLE , 1 => FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_ONE_CYCLE , 2 => FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_THREE_CYCLE , 3 => FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din5_disable (& self) -> bool { * self == FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din5_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din5_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din5_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN5` writer - Programmable counter length of digital glitch filter for DIN5"]
pub type FILTEREN15_0_DIN5_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN5_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din5_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din5_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din5_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din5_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN5_A :: FILTEREN15_0_DIN5_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN6` reader - Programmable counter length of digital glitch filter for DIN6"]
pub type FILTEREN15_0_DIN6_R = crate :: FieldReader < FILTEREN15_0_DIN6_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN6\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN6_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN6_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN6_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN6_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN6_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN6_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN6_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN6_A { type Ux = u8 ; } impl FILTEREN15_0_DIN6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN6_A { match self . bits { 0 => FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_DISABLE , 1 => FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_ONE_CYCLE , 2 => FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_THREE_CYCLE , 3 => FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din6_disable (& self) -> bool { * self == FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din6_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din6_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din6_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN6` writer - Programmable counter length of digital glitch filter for DIN6"]
pub type FILTEREN15_0_DIN6_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN6_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din6_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din6_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din6_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din6_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN6_A :: FILTEREN15_0_DIN6_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN7` reader - Programmable counter length of digital glitch filter for DIN7"]
pub type FILTEREN15_0_DIN7_R = crate :: FieldReader < FILTEREN15_0_DIN7_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN7\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN7_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN7_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN7_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN7_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN7_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN7_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN7_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN7_A { type Ux = u8 ; } impl FILTEREN15_0_DIN7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN7_A { match self . bits { 0 => FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_DISABLE , 1 => FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_ONE_CYCLE , 2 => FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_THREE_CYCLE , 3 => FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din7_disable (& self) -> bool { * self == FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din7_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din7_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din7_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN7` writer - Programmable counter length of digital glitch filter for DIN7"]
pub type FILTEREN15_0_DIN7_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN7_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din7_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din7_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din7_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din7_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN7_A :: FILTEREN15_0_DIN7_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN8` reader - Programmable counter length of digital glitch filter for DIN8"]
pub type FILTEREN15_0_DIN8_R = crate :: FieldReader < FILTEREN15_0_DIN8_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN8\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN8_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN8_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN8_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN8_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN8_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN8_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN8_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN8_A { type Ux = u8 ; } impl FILTEREN15_0_DIN8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN8_A { match self . bits { 0 => FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_DISABLE , 1 => FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_ONE_CYCLE , 2 => FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_THREE_CYCLE , 3 => FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din8_disable (& self) -> bool { * self == FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din8_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din8_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din8_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN8` writer - Programmable counter length of digital glitch filter for DIN8"]
pub type FILTEREN15_0_DIN8_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN8_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din8_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din8_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din8_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din8_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN8_A :: FILTEREN15_0_DIN8_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN9` reader - Programmable counter length of digital glitch filter for DIN9"]
pub type FILTEREN15_0_DIN9_R = crate :: FieldReader < FILTEREN15_0_DIN9_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN9_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN9_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN9_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN9_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN9_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN9_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN9_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN9_A { type Ux = u8 ; } impl FILTEREN15_0_DIN9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN9_A { match self . bits { 0 => FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_DISABLE , 1 => FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_ONE_CYCLE , 2 => FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_THREE_CYCLE , 3 => FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din9_disable (& self) -> bool { * self == FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din9_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din9_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din9_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN9` writer - Programmable counter length of digital glitch filter for DIN9"]
pub type FILTEREN15_0_DIN9_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN9_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din9_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din9_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din9_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din9_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN9_A :: FILTEREN15_0_DIN9_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN10` reader - Programmable counter length of digital glitch filter for DIN10"]
pub type FILTEREN15_0_DIN10_R = crate :: FieldReader < FILTEREN15_0_DIN10_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN10\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN10_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN10_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN10_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN10_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN10_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN10_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN10_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN10_A { type Ux = u8 ; } impl FILTEREN15_0_DIN10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN10_A { match self . bits { 0 => FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_DISABLE , 1 => FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_ONE_CYCLE , 2 => FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_THREE_CYCLE , 3 => FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din10_disable (& self) -> bool { * self == FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din10_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din10_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din10_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN10` writer - Programmable counter length of digital glitch filter for DIN10"]
pub type FILTEREN15_0_DIN10_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN10_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din10_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din10_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din10_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din10_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN10_A :: FILTEREN15_0_DIN10_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN11` reader - Programmable counter length of digital glitch filter for DIN11"]
pub type FILTEREN15_0_DIN11_R = crate :: FieldReader < FILTEREN15_0_DIN11_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN11\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN11_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN11_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN11_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN11_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN11_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN11_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN11_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN11_A { type Ux = u8 ; } impl FILTEREN15_0_DIN11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN11_A { match self . bits { 0 => FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_DISABLE , 1 => FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_ONE_CYCLE , 2 => FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_THREE_CYCLE , 3 => FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din11_disable (& self) -> bool { * self == FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din11_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din11_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din11_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN11` writer - Programmable counter length of digital glitch filter for DIN11"]
pub type FILTEREN15_0_DIN11_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN11_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din11_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din11_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din11_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din11_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN11_A :: FILTEREN15_0_DIN11_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN12` reader - Programmable counter length of digital glitch filter for DIN12"]
pub type FILTEREN15_0_DIN12_R = crate :: FieldReader < FILTEREN15_0_DIN12_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN12\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN12_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN12_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN12_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN12_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN12_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN12_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN12_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN12_A { type Ux = u8 ; } impl FILTEREN15_0_DIN12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN12_A { match self . bits { 0 => FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_DISABLE , 1 => FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_ONE_CYCLE , 2 => FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_THREE_CYCLE , 3 => FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din12_disable (& self) -> bool { * self == FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din12_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din12_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din12_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN12` writer - Programmable counter length of digital glitch filter for DIN12"]
pub type FILTEREN15_0_DIN12_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN12_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din12_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din12_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din12_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din12_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN12_A :: FILTEREN15_0_DIN12_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN13` reader - Programmable counter length of digital glitch filter for DIN13"]
pub type FILTEREN15_0_DIN13_R = crate :: FieldReader < FILTEREN15_0_DIN13_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN13\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN13_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN13_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN13_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN13_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN13_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN13_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN13_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN13_A { type Ux = u8 ; } impl FILTEREN15_0_DIN13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN13_A { match self . bits { 0 => FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_DISABLE , 1 => FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_ONE_CYCLE , 2 => FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_THREE_CYCLE , 3 => FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din13_disable (& self) -> bool { * self == FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din13_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din13_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din13_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN13` writer - Programmable counter length of digital glitch filter for DIN13"]
pub type FILTEREN15_0_DIN13_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN13_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din13_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din13_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din13_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din13_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN13_A :: FILTEREN15_0_DIN13_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN14` reader - Programmable counter length of digital glitch filter for DIN14"]
pub type FILTEREN15_0_DIN14_R = crate :: FieldReader < FILTEREN15_0_DIN14_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN14\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN14_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN14_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN14_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN14_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN14_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN14_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN14_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN14_A { type Ux = u8 ; } impl FILTEREN15_0_DIN14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN14_A { match self . bits { 0 => FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_DISABLE , 1 => FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_ONE_CYCLE , 2 => FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_THREE_CYCLE , 3 => FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din14_disable (& self) -> bool { * self == FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din14_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din14_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din14_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN14` writer - Programmable counter length of digital glitch filter for DIN14"]
pub type FILTEREN15_0_DIN14_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN14_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din14_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din14_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din14_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din14_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN14_A :: FILTEREN15_0_DIN14_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN15_0_DIN15` reader - Programmable counter length of digital glitch filter for DIN15"]
pub type FILTEREN15_0_DIN15_R = crate :: FieldReader < FILTEREN15_0_DIN15_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN15\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN15_0_DIN15_A { # [doc = "0: DISABLE"]
FILTEREN15_0_DIN15_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN15_0_DIN15_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN15_0_DIN15_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN15_0_DIN15_EIGHT_CYCLE = 3 , } impl From < FILTEREN15_0_DIN15_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN15_0_DIN15_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN15_0_DIN15_A { type Ux = u8 ; } impl FILTEREN15_0_DIN15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN15_0_DIN15_A { match self . bits { 0 => FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_DISABLE , 1 => FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_ONE_CYCLE , 2 => FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_THREE_CYCLE , 3 => FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren15_0_din15_disable (& self) -> bool { * self == FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din15_one_cycle (& self) -> bool { * self == FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din15_three_cycle (& self) -> bool { * self == FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren15_0_din15_eight_cycle (& self) -> bool { * self == FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_EIGHT_CYCLE } } # [doc = "Field `FILTEREN15_0_DIN15` writer - Programmable counter length of digital glitch filter for DIN15"]
pub type FILTEREN15_0_DIN15_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN15_0_DIN15_A > ; impl < 'a , REG , const O : u8 > FILTEREN15_0_DIN15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren15_0_din15_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din15_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din15_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren15_0_din15_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN15_0_DIN15_A :: FILTEREN15_0_DIN15_EIGHT_CYCLE) } } impl R { # [doc = "Bits 0:1 - Programmable counter length of digital glitch filter for DIN0"]
# [inline (always)]
pub fn filteren15_0_din0 (& self) -> FILTEREN15_0_DIN0_R { FILTEREN15_0_DIN0_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Programmable counter length of digital glitch filter for DIN1"]
# [inline (always)]
pub fn filteren15_0_din1 (& self) -> FILTEREN15_0_DIN1_R { FILTEREN15_0_DIN1_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Programmable counter length of digital glitch filter for DIN2"]
# [inline (always)]
pub fn filteren15_0_din2 (& self) -> FILTEREN15_0_DIN2_R { FILTEREN15_0_DIN2_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - Programmable counter length of digital glitch filter for DIN3"]
# [inline (always)]
pub fn filteren15_0_din3 (& self) -> FILTEREN15_0_DIN3_R { FILTEREN15_0_DIN3_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - Programmable counter length of digital glitch filter for DIN4"]
# [inline (always)]
pub fn filteren15_0_din4 (& self) -> FILTEREN15_0_DIN4_R { FILTEREN15_0_DIN4_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Programmable counter length of digital glitch filter for DIN5"]
# [inline (always)]
pub fn filteren15_0_din5 (& self) -> FILTEREN15_0_DIN5_R { FILTEREN15_0_DIN5_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Programmable counter length of digital glitch filter for DIN6"]
# [inline (always)]
pub fn filteren15_0_din6 (& self) -> FILTEREN15_0_DIN6_R { FILTEREN15_0_DIN6_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - Programmable counter length of digital glitch filter for DIN7"]
# [inline (always)]
pub fn filteren15_0_din7 (& self) -> FILTEREN15_0_DIN7_R { FILTEREN15_0_DIN7_R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - Programmable counter length of digital glitch filter for DIN8"]
# [inline (always)]
pub fn filteren15_0_din8 (& self) -> FILTEREN15_0_DIN8_R { FILTEREN15_0_DIN8_R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - Programmable counter length of digital glitch filter for DIN9"]
# [inline (always)]
pub fn filteren15_0_din9 (& self) -> FILTEREN15_0_DIN9_R { FILTEREN15_0_DIN9_R :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - Programmable counter length of digital glitch filter for DIN10"]
# [inline (always)]
pub fn filteren15_0_din10 (& self) -> FILTEREN15_0_DIN10_R { FILTEREN15_0_DIN10_R :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - Programmable counter length of digital glitch filter for DIN11"]
# [inline (always)]
pub fn filteren15_0_din11 (& self) -> FILTEREN15_0_DIN11_R { FILTEREN15_0_DIN11_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:25 - Programmable counter length of digital glitch filter for DIN12"]
# [inline (always)]
pub fn filteren15_0_din12 (& self) -> FILTEREN15_0_DIN12_R { FILTEREN15_0_DIN12_R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:27 - Programmable counter length of digital glitch filter for DIN13"]
# [inline (always)]
pub fn filteren15_0_din13 (& self) -> FILTEREN15_0_DIN13_R { FILTEREN15_0_DIN13_R :: new (((self . bits >> 26) & 3) as u8) } # [doc = "Bits 28:29 - Programmable counter length of digital glitch filter for DIN14"]
# [inline (always)]
pub fn filteren15_0_din14 (& self) -> FILTEREN15_0_DIN14_R { FILTEREN15_0_DIN14_R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - Programmable counter length of digital glitch filter for DIN15"]
# [inline (always)]
pub fn filteren15_0_din15 (& self) -> FILTEREN15_0_DIN15_R { FILTEREN15_0_DIN15_R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Programmable counter length of digital glitch filter for DIN0"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din0 (& mut self) -> FILTEREN15_0_DIN0_W < FILTEREN15_0_SPEC , 0 > { FILTEREN15_0_DIN0_W :: new (self) } # [doc = "Bits 2:3 - Programmable counter length of digital glitch filter for DIN1"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din1 (& mut self) -> FILTEREN15_0_DIN1_W < FILTEREN15_0_SPEC , 2 > { FILTEREN15_0_DIN1_W :: new (self) } # [doc = "Bits 4:5 - Programmable counter length of digital glitch filter for DIN2"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din2 (& mut self) -> FILTEREN15_0_DIN2_W < FILTEREN15_0_SPEC , 4 > { FILTEREN15_0_DIN2_W :: new (self) } # [doc = "Bits 6:7 - Programmable counter length of digital glitch filter for DIN3"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din3 (& mut self) -> FILTEREN15_0_DIN3_W < FILTEREN15_0_SPEC , 6 > { FILTEREN15_0_DIN3_W :: new (self) } # [doc = "Bits 8:9 - Programmable counter length of digital glitch filter for DIN4"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din4 (& mut self) -> FILTEREN15_0_DIN4_W < FILTEREN15_0_SPEC , 8 > { FILTEREN15_0_DIN4_W :: new (self) } # [doc = "Bits 10:11 - Programmable counter length of digital glitch filter for DIN5"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din5 (& mut self) -> FILTEREN15_0_DIN5_W < FILTEREN15_0_SPEC , 10 > { FILTEREN15_0_DIN5_W :: new (self) } # [doc = "Bits 12:13 - Programmable counter length of digital glitch filter for DIN6"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din6 (& mut self) -> FILTEREN15_0_DIN6_W < FILTEREN15_0_SPEC , 12 > { FILTEREN15_0_DIN6_W :: new (self) } # [doc = "Bits 14:15 - Programmable counter length of digital glitch filter for DIN7"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din7 (& mut self) -> FILTEREN15_0_DIN7_W < FILTEREN15_0_SPEC , 14 > { FILTEREN15_0_DIN7_W :: new (self) } # [doc = "Bits 16:17 - Programmable counter length of digital glitch filter for DIN8"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din8 (& mut self) -> FILTEREN15_0_DIN8_W < FILTEREN15_0_SPEC , 16 > { FILTEREN15_0_DIN8_W :: new (self) } # [doc = "Bits 18:19 - Programmable counter length of digital glitch filter for DIN9"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din9 (& mut self) -> FILTEREN15_0_DIN9_W < FILTEREN15_0_SPEC , 18 > { FILTEREN15_0_DIN9_W :: new (self) } # [doc = "Bits 20:21 - Programmable counter length of digital glitch filter for DIN10"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din10 (& mut self) -> FILTEREN15_0_DIN10_W < FILTEREN15_0_SPEC , 20 > { FILTEREN15_0_DIN10_W :: new (self) } # [doc = "Bits 22:23 - Programmable counter length of digital glitch filter for DIN11"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din11 (& mut self) -> FILTEREN15_0_DIN11_W < FILTEREN15_0_SPEC , 22 > { FILTEREN15_0_DIN11_W :: new (self) } # [doc = "Bits 24:25 - Programmable counter length of digital glitch filter for DIN12"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din12 (& mut self) -> FILTEREN15_0_DIN12_W < FILTEREN15_0_SPEC , 24 > { FILTEREN15_0_DIN12_W :: new (self) } # [doc = "Bits 26:27 - Programmable counter length of digital glitch filter for DIN13"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din13 (& mut self) -> FILTEREN15_0_DIN13_W < FILTEREN15_0_SPEC , 26 > { FILTEREN15_0_DIN13_W :: new (self) } # [doc = "Bits 28:29 - Programmable counter length of digital glitch filter for DIN14"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din14 (& mut self) -> FILTEREN15_0_DIN14_W < FILTEREN15_0_SPEC , 28 > { FILTEREN15_0_DIN14_W :: new (self) } # [doc = "Bits 30:31 - Programmable counter length of digital glitch filter for DIN15"]
# [inline (always)]
# [must_use]
pub fn filteren15_0_din15 (& mut self) -> FILTEREN15_0_DIN15_W < FILTEREN15_0_SPEC , 30 > { FILTEREN15_0_DIN15_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Filter Enable 15 to 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filteren15_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filteren15_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FILTEREN15_0_SPEC ; impl crate :: RegisterSpec for FILTEREN15_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`filteren15_0::R`](R) reader structure"]
impl crate :: Readable for FILTEREN15_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`filteren15_0::W`](W) writer structure"]
impl crate :: Writable for FILTEREN15_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FILTEREN15_0 to value 0"]
impl crate :: Resettable for FILTEREN15_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FILTEREN31_16 (rw) register accessor: Filter Enable 31 to 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filteren31_16::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filteren31_16::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@filteren31_16`]
module"]
pub type FILTEREN31_16 = crate :: Reg < filteren31_16 :: FILTEREN31_16_SPEC > ; # [doc = "Filter Enable 31 to 16"]
pub mod filteren31_16 { # [doc = "Register `FILTEREN31_16` reader"]
pub type R = crate :: R < FILTEREN31_16_SPEC > ; # [doc = "Register `FILTEREN31_16` writer"]
pub type W = crate :: W < FILTEREN31_16_SPEC > ; # [doc = "Field `FILTEREN31_16_DIN16` reader - Programmable counter length of digital glitch filter for DIN16"]
pub type FILTEREN31_16_DIN16_R = crate :: FieldReader < FILTEREN31_16_DIN16_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN16\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN16_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN16_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN16_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN16_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN16_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN16_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN16_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN16_A { type Ux = u8 ; } impl FILTEREN31_16_DIN16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN16_A { match self . bits { 0 => FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_DISABLE , 1 => FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_ONE_CYCLE , 2 => FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_THREE_CYCLE , 3 => FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din16_disable (& self) -> bool { * self == FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din16_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din16_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din16_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN16` writer - Programmable counter length of digital glitch filter for DIN16"]
pub type FILTEREN31_16_DIN16_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN16_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din16_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din16_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din16_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din16_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN16_A :: FILTEREN31_16_DIN16_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN17` reader - Programmable counter length of digital glitch filter for DIN17"]
pub type FILTEREN31_16_DIN17_R = crate :: FieldReader < FILTEREN31_16_DIN17_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN17\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN17_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN17_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN17_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN17_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN17_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN17_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN17_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN17_A { type Ux = u8 ; } impl FILTEREN31_16_DIN17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN17_A { match self . bits { 0 => FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_DISABLE , 1 => FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_ONE_CYCLE , 2 => FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_THREE_CYCLE , 3 => FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din17_disable (& self) -> bool { * self == FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din17_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din17_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din17_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN17` writer - Programmable counter length of digital glitch filter for DIN17"]
pub type FILTEREN31_16_DIN17_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN17_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din17_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din17_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din17_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din17_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN17_A :: FILTEREN31_16_DIN17_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN18` reader - Programmable counter length of digital glitch filter for DIN18"]
pub type FILTEREN31_16_DIN18_R = crate :: FieldReader < FILTEREN31_16_DIN18_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN18\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN18_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN18_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN18_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN18_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN18_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN18_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN18_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN18_A { type Ux = u8 ; } impl FILTEREN31_16_DIN18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN18_A { match self . bits { 0 => FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_DISABLE , 1 => FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_ONE_CYCLE , 2 => FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_THREE_CYCLE , 3 => FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din18_disable (& self) -> bool { * self == FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din18_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din18_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din18_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN18` writer - Programmable counter length of digital glitch filter for DIN18"]
pub type FILTEREN31_16_DIN18_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN18_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din18_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din18_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din18_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din18_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN18_A :: FILTEREN31_16_DIN18_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN19` reader - Programmable counter length of digital glitch filter for DIN19"]
pub type FILTEREN31_16_DIN19_R = crate :: FieldReader < FILTEREN31_16_DIN19_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN19\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN19_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN19_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN19_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN19_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN19_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN19_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN19_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN19_A { type Ux = u8 ; } impl FILTEREN31_16_DIN19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN19_A { match self . bits { 0 => FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_DISABLE , 1 => FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_ONE_CYCLE , 2 => FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_THREE_CYCLE , 3 => FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din19_disable (& self) -> bool { * self == FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din19_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din19_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din19_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN19` writer - Programmable counter length of digital glitch filter for DIN19"]
pub type FILTEREN31_16_DIN19_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN19_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din19_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din19_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din19_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din19_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN19_A :: FILTEREN31_16_DIN19_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN20` reader - Programmable counter length of digital glitch filter for DIN20"]
pub type FILTEREN31_16_DIN20_R = crate :: FieldReader < FILTEREN31_16_DIN20_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN20\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN20_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN20_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN20_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN20_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN20_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN20_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN20_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN20_A { type Ux = u8 ; } impl FILTEREN31_16_DIN20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN20_A { match self . bits { 0 => FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_DISABLE , 1 => FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_ONE_CYCLE , 2 => FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_THREE_CYCLE , 3 => FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din20_disable (& self) -> bool { * self == FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din20_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din20_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din20_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN20` writer - Programmable counter length of digital glitch filter for DIN20"]
pub type FILTEREN31_16_DIN20_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN20_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din20_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din20_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din20_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din20_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN20_A :: FILTEREN31_16_DIN20_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN21` reader - Programmable counter length of digital glitch filter for DIN21"]
pub type FILTEREN31_16_DIN21_R = crate :: FieldReader < FILTEREN31_16_DIN21_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN21\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN21_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN21_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN21_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN21_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN21_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN21_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN21_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN21_A { type Ux = u8 ; } impl FILTEREN31_16_DIN21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN21_A { match self . bits { 0 => FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_DISABLE , 1 => FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_ONE_CYCLE , 2 => FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_THREE_CYCLE , 3 => FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din21_disable (& self) -> bool { * self == FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din21_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din21_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din21_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN21` writer - Programmable counter length of digital glitch filter for DIN21"]
pub type FILTEREN31_16_DIN21_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN21_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din21_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din21_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din21_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din21_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN21_A :: FILTEREN31_16_DIN21_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN22` reader - Programmable counter length of digital glitch filter for DIN22"]
pub type FILTEREN31_16_DIN22_R = crate :: FieldReader < FILTEREN31_16_DIN22_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN22\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN22_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN22_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN22_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN22_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN22_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN22_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN22_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN22_A { type Ux = u8 ; } impl FILTEREN31_16_DIN22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN22_A { match self . bits { 0 => FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_DISABLE , 1 => FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_ONE_CYCLE , 2 => FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_THREE_CYCLE , 3 => FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din22_disable (& self) -> bool { * self == FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din22_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din22_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din22_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN22` writer - Programmable counter length of digital glitch filter for DIN22"]
pub type FILTEREN31_16_DIN22_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN22_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din22_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din22_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din22_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din22_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN22_A :: FILTEREN31_16_DIN22_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN23` reader - Programmable counter length of digital glitch filter for DIN23"]
pub type FILTEREN31_16_DIN23_R = crate :: FieldReader < FILTEREN31_16_DIN23_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN23\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN23_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN23_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN23_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN23_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN23_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN23_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN23_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN23_A { type Ux = u8 ; } impl FILTEREN31_16_DIN23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN23_A { match self . bits { 0 => FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_DISABLE , 1 => FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_ONE_CYCLE , 2 => FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_THREE_CYCLE , 3 => FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din23_disable (& self) -> bool { * self == FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din23_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din23_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din23_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN23` writer - Programmable counter length of digital glitch filter for DIN23"]
pub type FILTEREN31_16_DIN23_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN23_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din23_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din23_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din23_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din23_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN23_A :: FILTEREN31_16_DIN23_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN24` reader - Programmable counter length of digital glitch filter for DIN24"]
pub type FILTEREN31_16_DIN24_R = crate :: FieldReader < FILTEREN31_16_DIN24_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN24\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN24_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN24_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN24_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN24_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN24_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN24_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN24_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN24_A { type Ux = u8 ; } impl FILTEREN31_16_DIN24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN24_A { match self . bits { 0 => FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_DISABLE , 1 => FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_ONE_CYCLE , 2 => FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_THREE_CYCLE , 3 => FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din24_disable (& self) -> bool { * self == FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din24_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din24_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din24_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN24` writer - Programmable counter length of digital glitch filter for DIN24"]
pub type FILTEREN31_16_DIN24_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN24_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din24_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din24_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din24_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din24_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN24_A :: FILTEREN31_16_DIN24_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN25` reader - Programmable counter length of digital glitch filter for DIN25"]
pub type FILTEREN31_16_DIN25_R = crate :: FieldReader < FILTEREN31_16_DIN25_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN25\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN25_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN25_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN25_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN25_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN25_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN25_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN25_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN25_A { type Ux = u8 ; } impl FILTEREN31_16_DIN25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN25_A { match self . bits { 0 => FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_DISABLE , 1 => FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_ONE_CYCLE , 2 => FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_THREE_CYCLE , 3 => FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din25_disable (& self) -> bool { * self == FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din25_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din25_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din25_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN25` writer - Programmable counter length of digital glitch filter for DIN25"]
pub type FILTEREN31_16_DIN25_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN25_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din25_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din25_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din25_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din25_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN25_A :: FILTEREN31_16_DIN25_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN26` reader - Programmable counter length of digital glitch filter for DIN26"]
pub type FILTEREN31_16_DIN26_R = crate :: FieldReader < FILTEREN31_16_DIN26_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN26\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN26_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN26_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN26_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN26_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN26_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN26_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN26_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN26_A { type Ux = u8 ; } impl FILTEREN31_16_DIN26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN26_A { match self . bits { 0 => FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_DISABLE , 1 => FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_ONE_CYCLE , 2 => FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_THREE_CYCLE , 3 => FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din26_disable (& self) -> bool { * self == FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din26_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din26_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din26_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN26` writer - Programmable counter length of digital glitch filter for DIN26"]
pub type FILTEREN31_16_DIN26_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN26_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din26_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din26_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din26_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din26_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN26_A :: FILTEREN31_16_DIN26_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN27` reader - Programmable counter length of digital glitch filter for DIN27"]
pub type FILTEREN31_16_DIN27_R = crate :: FieldReader < FILTEREN31_16_DIN27_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN27\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN27_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN27_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN27_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN27_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN27_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN27_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN27_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN27_A { type Ux = u8 ; } impl FILTEREN31_16_DIN27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN27_A { match self . bits { 0 => FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_DISABLE , 1 => FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_ONE_CYCLE , 2 => FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_THREE_CYCLE , 3 => FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din27_disable (& self) -> bool { * self == FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din27_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din27_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din27_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN27` writer - Programmable counter length of digital glitch filter for DIN27"]
pub type FILTEREN31_16_DIN27_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN27_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din27_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din27_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din27_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din27_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN27_A :: FILTEREN31_16_DIN27_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN28` reader - Programmable counter length of digital glitch filter for DIN28"]
pub type FILTEREN31_16_DIN28_R = crate :: FieldReader < FILTEREN31_16_DIN28_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN28\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN28_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN28_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN28_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN28_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN28_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN28_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN28_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN28_A { type Ux = u8 ; } impl FILTEREN31_16_DIN28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN28_A { match self . bits { 0 => FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_DISABLE , 1 => FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_ONE_CYCLE , 2 => FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_THREE_CYCLE , 3 => FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din28_disable (& self) -> bool { * self == FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din28_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din28_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din28_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN28` writer - Programmable counter length of digital glitch filter for DIN28"]
pub type FILTEREN31_16_DIN28_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN28_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din28_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din28_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din28_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din28_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN28_A :: FILTEREN31_16_DIN28_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN29` reader - Programmable counter length of digital glitch filter for DIN29"]
pub type FILTEREN31_16_DIN29_R = crate :: FieldReader < FILTEREN31_16_DIN29_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN29\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN29_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN29_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN29_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN29_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN29_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN29_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN29_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN29_A { type Ux = u8 ; } impl FILTEREN31_16_DIN29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN29_A { match self . bits { 0 => FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_DISABLE , 1 => FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_ONE_CYCLE , 2 => FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_THREE_CYCLE , 3 => FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din29_disable (& self) -> bool { * self == FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din29_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din29_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din29_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN29` writer - Programmable counter length of digital glitch filter for DIN29"]
pub type FILTEREN31_16_DIN29_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN29_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din29_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din29_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din29_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din29_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN29_A :: FILTEREN31_16_DIN29_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN30` reader - Programmable counter length of digital glitch filter for DIN30"]
pub type FILTEREN31_16_DIN30_R = crate :: FieldReader < FILTEREN31_16_DIN30_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN30\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN30_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN30_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN30_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN30_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN30_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN30_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN30_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN30_A { type Ux = u8 ; } impl FILTEREN31_16_DIN30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN30_A { match self . bits { 0 => FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_DISABLE , 1 => FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_ONE_CYCLE , 2 => FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_THREE_CYCLE , 3 => FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din30_disable (& self) -> bool { * self == FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din30_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din30_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din30_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN30` writer - Programmable counter length of digital glitch filter for DIN30"]
pub type FILTEREN31_16_DIN30_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN30_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din30_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din30_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din30_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din30_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN30_A :: FILTEREN31_16_DIN30_EIGHT_CYCLE) } } # [doc = "Field `FILTEREN31_16_DIN31` reader - Programmable counter length of digital glitch filter for DIN31"]
pub type FILTEREN31_16_DIN31_R = crate :: FieldReader < FILTEREN31_16_DIN31_A > ; # [doc = "Programmable counter length of digital glitch filter for DIN31\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FILTEREN31_16_DIN31_A { # [doc = "0: DISABLE"]
FILTEREN31_16_DIN31_DISABLE = 0 , # [doc = "1: ONE_CYCLE"]
FILTEREN31_16_DIN31_ONE_CYCLE = 1 , # [doc = "2: THREE_CYCLE"]
FILTEREN31_16_DIN31_THREE_CYCLE = 2 , # [doc = "3: EIGHT_CYCLE"]
FILTEREN31_16_DIN31_EIGHT_CYCLE = 3 , } impl From < FILTEREN31_16_DIN31_A > for u8 { # [inline (always)]
fn from (variant : FILTEREN31_16_DIN31_A) -> Self { variant as _ } } impl crate :: FieldSpec for FILTEREN31_16_DIN31_A { type Ux = u8 ; } impl FILTEREN31_16_DIN31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> FILTEREN31_16_DIN31_A { match self . bits { 0 => FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_DISABLE , 1 => FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_ONE_CYCLE , 2 => FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_THREE_CYCLE , 3 => FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_EIGHT_CYCLE , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_filteren31_16_din31_disable (& self) -> bool { * self == FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_DISABLE } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din31_one_cycle (& self) -> bool { * self == FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_ONE_CYCLE } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din31_three_cycle (& self) -> bool { * self == FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_THREE_CYCLE } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn is_filteren31_16_din31_eight_cycle (& self) -> bool { * self == FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_EIGHT_CYCLE } } # [doc = "Field `FILTEREN31_16_DIN31` writer - Programmable counter length of digital glitch filter for DIN31"]
pub type FILTEREN31_16_DIN31_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , FILTEREN31_16_DIN31_A > ; impl < 'a , REG , const O : u8 > FILTEREN31_16_DIN31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn filteren31_16_din31_disable (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_DISABLE) } # [doc = "ONE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din31_one_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_ONE_CYCLE) } # [doc = "THREE_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din31_three_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_THREE_CYCLE) } # [doc = "EIGHT_CYCLE"]
# [inline (always)]
pub fn filteren31_16_din31_eight_cycle (self) -> & 'a mut crate :: W < REG > { self . variant (FILTEREN31_16_DIN31_A :: FILTEREN31_16_DIN31_EIGHT_CYCLE) } } impl R { # [doc = "Bits 0:1 - Programmable counter length of digital glitch filter for DIN16"]
# [inline (always)]
pub fn filteren31_16_din16 (& self) -> FILTEREN31_16_DIN16_R { FILTEREN31_16_DIN16_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Programmable counter length of digital glitch filter for DIN17"]
# [inline (always)]
pub fn filteren31_16_din17 (& self) -> FILTEREN31_16_DIN17_R { FILTEREN31_16_DIN17_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Programmable counter length of digital glitch filter for DIN18"]
# [inline (always)]
pub fn filteren31_16_din18 (& self) -> FILTEREN31_16_DIN18_R { FILTEREN31_16_DIN18_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 6:7 - Programmable counter length of digital glitch filter for DIN19"]
# [inline (always)]
pub fn filteren31_16_din19 (& self) -> FILTEREN31_16_DIN19_R { FILTEREN31_16_DIN19_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 8:9 - Programmable counter length of digital glitch filter for DIN20"]
# [inline (always)]
pub fn filteren31_16_din20 (& self) -> FILTEREN31_16_DIN20_R { FILTEREN31_16_DIN20_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - Programmable counter length of digital glitch filter for DIN21"]
# [inline (always)]
pub fn filteren31_16_din21 (& self) -> FILTEREN31_16_DIN21_R { FILTEREN31_16_DIN21_R :: new (((self . bits >> 10) & 3) as u8) } # [doc = "Bits 12:13 - Programmable counter length of digital glitch filter for DIN22"]
# [inline (always)]
pub fn filteren31_16_din22 (& self) -> FILTEREN31_16_DIN22_R { FILTEREN31_16_DIN22_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 14:15 - Programmable counter length of digital glitch filter for DIN23"]
# [inline (always)]
pub fn filteren31_16_din23 (& self) -> FILTEREN31_16_DIN23_R { FILTEREN31_16_DIN23_R :: new (((self . bits >> 14) & 3) as u8) } # [doc = "Bits 16:17 - Programmable counter length of digital glitch filter for DIN24"]
# [inline (always)]
pub fn filteren31_16_din24 (& self) -> FILTEREN31_16_DIN24_R { FILTEREN31_16_DIN24_R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bits 18:19 - Programmable counter length of digital glitch filter for DIN25"]
# [inline (always)]
pub fn filteren31_16_din25 (& self) -> FILTEREN31_16_DIN25_R { FILTEREN31_16_DIN25_R :: new (((self . bits >> 18) & 3) as u8) } # [doc = "Bits 20:21 - Programmable counter length of digital glitch filter for DIN26"]
# [inline (always)]
pub fn filteren31_16_din26 (& self) -> FILTEREN31_16_DIN26_R { FILTEREN31_16_DIN26_R :: new (((self . bits >> 20) & 3) as u8) } # [doc = "Bits 22:23 - Programmable counter length of digital glitch filter for DIN27"]
# [inline (always)]
pub fn filteren31_16_din27 (& self) -> FILTEREN31_16_DIN27_R { FILTEREN31_16_DIN27_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:25 - Programmable counter length of digital glitch filter for DIN28"]
# [inline (always)]
pub fn filteren31_16_din28 (& self) -> FILTEREN31_16_DIN28_R { FILTEREN31_16_DIN28_R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 26:27 - Programmable counter length of digital glitch filter for DIN29"]
# [inline (always)]
pub fn filteren31_16_din29 (& self) -> FILTEREN31_16_DIN29_R { FILTEREN31_16_DIN29_R :: new (((self . bits >> 26) & 3) as u8) } # [doc = "Bits 28:29 - Programmable counter length of digital glitch filter for DIN30"]
# [inline (always)]
pub fn filteren31_16_din30 (& self) -> FILTEREN31_16_DIN30_R { FILTEREN31_16_DIN30_R :: new (((self . bits >> 28) & 3) as u8) } # [doc = "Bits 30:31 - Programmable counter length of digital glitch filter for DIN31"]
# [inline (always)]
pub fn filteren31_16_din31 (& self) -> FILTEREN31_16_DIN31_R { FILTEREN31_16_DIN31_R :: new (((self . bits >> 30) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - Programmable counter length of digital glitch filter for DIN16"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din16 (& mut self) -> FILTEREN31_16_DIN16_W < FILTEREN31_16_SPEC , 0 > { FILTEREN31_16_DIN16_W :: new (self) } # [doc = "Bits 2:3 - Programmable counter length of digital glitch filter for DIN17"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din17 (& mut self) -> FILTEREN31_16_DIN17_W < FILTEREN31_16_SPEC , 2 > { FILTEREN31_16_DIN17_W :: new (self) } # [doc = "Bits 4:5 - Programmable counter length of digital glitch filter for DIN18"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din18 (& mut self) -> FILTEREN31_16_DIN18_W < FILTEREN31_16_SPEC , 4 > { FILTEREN31_16_DIN18_W :: new (self) } # [doc = "Bits 6:7 - Programmable counter length of digital glitch filter for DIN19"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din19 (& mut self) -> FILTEREN31_16_DIN19_W < FILTEREN31_16_SPEC , 6 > { FILTEREN31_16_DIN19_W :: new (self) } # [doc = "Bits 8:9 - Programmable counter length of digital glitch filter for DIN20"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din20 (& mut self) -> FILTEREN31_16_DIN20_W < FILTEREN31_16_SPEC , 8 > { FILTEREN31_16_DIN20_W :: new (self) } # [doc = "Bits 10:11 - Programmable counter length of digital glitch filter for DIN21"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din21 (& mut self) -> FILTEREN31_16_DIN21_W < FILTEREN31_16_SPEC , 10 > { FILTEREN31_16_DIN21_W :: new (self) } # [doc = "Bits 12:13 - Programmable counter length of digital glitch filter for DIN22"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din22 (& mut self) -> FILTEREN31_16_DIN22_W < FILTEREN31_16_SPEC , 12 > { FILTEREN31_16_DIN22_W :: new (self) } # [doc = "Bits 14:15 - Programmable counter length of digital glitch filter for DIN23"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din23 (& mut self) -> FILTEREN31_16_DIN23_W < FILTEREN31_16_SPEC , 14 > { FILTEREN31_16_DIN23_W :: new (self) } # [doc = "Bits 16:17 - Programmable counter length of digital glitch filter for DIN24"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din24 (& mut self) -> FILTEREN31_16_DIN24_W < FILTEREN31_16_SPEC , 16 > { FILTEREN31_16_DIN24_W :: new (self) } # [doc = "Bits 18:19 - Programmable counter length of digital glitch filter for DIN25"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din25 (& mut self) -> FILTEREN31_16_DIN25_W < FILTEREN31_16_SPEC , 18 > { FILTEREN31_16_DIN25_W :: new (self) } # [doc = "Bits 20:21 - Programmable counter length of digital glitch filter for DIN26"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din26 (& mut self) -> FILTEREN31_16_DIN26_W < FILTEREN31_16_SPEC , 20 > { FILTEREN31_16_DIN26_W :: new (self) } # [doc = "Bits 22:23 - Programmable counter length of digital glitch filter for DIN27"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din27 (& mut self) -> FILTEREN31_16_DIN27_W < FILTEREN31_16_SPEC , 22 > { FILTEREN31_16_DIN27_W :: new (self) } # [doc = "Bits 24:25 - Programmable counter length of digital glitch filter for DIN28"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din28 (& mut self) -> FILTEREN31_16_DIN28_W < FILTEREN31_16_SPEC , 24 > { FILTEREN31_16_DIN28_W :: new (self) } # [doc = "Bits 26:27 - Programmable counter length of digital glitch filter for DIN29"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din29 (& mut self) -> FILTEREN31_16_DIN29_W < FILTEREN31_16_SPEC , 26 > { FILTEREN31_16_DIN29_W :: new (self) } # [doc = "Bits 28:29 - Programmable counter length of digital glitch filter for DIN30"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din30 (& mut self) -> FILTEREN31_16_DIN30_W < FILTEREN31_16_SPEC , 28 > { FILTEREN31_16_DIN30_W :: new (self) } # [doc = "Bits 30:31 - Programmable counter length of digital glitch filter for DIN31"]
# [inline (always)]
# [must_use]
pub fn filteren31_16_din31 (& mut self) -> FILTEREN31_16_DIN31_W < FILTEREN31_16_SPEC , 30 > { FILTEREN31_16_DIN31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Filter Enable 31 to 16\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`filteren31_16::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`filteren31_16::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FILTEREN31_16_SPEC ; impl crate :: RegisterSpec for FILTEREN31_16_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`filteren31_16::R`](R) reader structure"]
impl crate :: Readable for FILTEREN31_16_SPEC { } # [doc = "`write(|w| ..)` method takes [`filteren31_16::W`](W) writer structure"]
impl crate :: Writable for FILTEREN31_16_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FILTEREN31_16 to value 0"]
impl crate :: Resettable for FILTEREN31_16_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DMAMASK (rw) register accessor: DMA Write MASK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmamask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmamask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmamask`]
module"]
pub type DMAMASK = crate :: Reg < dmamask :: DMAMASK_SPEC > ; # [doc = "DMA Write MASK"]
pub mod dmamask { # [doc = "Register `DMAMASK` reader"]
pub type R = crate :: R < DMAMASK_SPEC > ; # [doc = "Register `DMAMASK` writer"]
pub type W = crate :: W < DMAMASK_SPEC > ; # [doc = "Field `DMAMASK_DOUT0` reader - DMA is allowed to modify DOUT0"]
pub type DMAMASK_DOUT0_R = crate :: BitReader < DMAMASK_DOUT0_A > ; # [doc = "DMA is allowed to modify DOUT0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT0_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT0_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT0_ENABLE = 1 , } impl From < DMAMASK_DOUT0_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT0_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT0_A { match self . bits { false => DMAMASK_DOUT0_A :: DMAMASK_DOUT0_DISABLE , true => DMAMASK_DOUT0_A :: DMAMASK_DOUT0_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout0_disable (& self) -> bool { * self == DMAMASK_DOUT0_A :: DMAMASK_DOUT0_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout0_enable (& self) -> bool { * self == DMAMASK_DOUT0_A :: DMAMASK_DOUT0_ENABLE } } # [doc = "Field `DMAMASK_DOUT0` writer - DMA is allowed to modify DOUT0"]
pub type DMAMASK_DOUT0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT0_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout0_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT0_A :: DMAMASK_DOUT0_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout0_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT0_A :: DMAMASK_DOUT0_ENABLE) } } # [doc = "Field `DMAMASK_DOUT1` reader - DMA is allowed to modify DOUT1"]
pub type DMAMASK_DOUT1_R = crate :: BitReader < DMAMASK_DOUT1_A > ; # [doc = "DMA is allowed to modify DOUT1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT1_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT1_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT1_ENABLE = 1 , } impl From < DMAMASK_DOUT1_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT1_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT1_A { match self . bits { false => DMAMASK_DOUT1_A :: DMAMASK_DOUT1_DISABLE , true => DMAMASK_DOUT1_A :: DMAMASK_DOUT1_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout1_disable (& self) -> bool { * self == DMAMASK_DOUT1_A :: DMAMASK_DOUT1_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout1_enable (& self) -> bool { * self == DMAMASK_DOUT1_A :: DMAMASK_DOUT1_ENABLE } } # [doc = "Field `DMAMASK_DOUT1` writer - DMA is allowed to modify DOUT1"]
pub type DMAMASK_DOUT1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT1_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout1_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT1_A :: DMAMASK_DOUT1_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout1_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT1_A :: DMAMASK_DOUT1_ENABLE) } } # [doc = "Field `DMAMASK_DOUT2` reader - DMA is allowed to modify DOUT2"]
pub type DMAMASK_DOUT2_R = crate :: BitReader < DMAMASK_DOUT2_A > ; # [doc = "DMA is allowed to modify DOUT2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT2_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT2_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT2_ENABLE = 1 , } impl From < DMAMASK_DOUT2_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT2_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT2_A { match self . bits { false => DMAMASK_DOUT2_A :: DMAMASK_DOUT2_DISABLE , true => DMAMASK_DOUT2_A :: DMAMASK_DOUT2_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout2_disable (& self) -> bool { * self == DMAMASK_DOUT2_A :: DMAMASK_DOUT2_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout2_enable (& self) -> bool { * self == DMAMASK_DOUT2_A :: DMAMASK_DOUT2_ENABLE } } # [doc = "Field `DMAMASK_DOUT2` writer - DMA is allowed to modify DOUT2"]
pub type DMAMASK_DOUT2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT2_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout2_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT2_A :: DMAMASK_DOUT2_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout2_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT2_A :: DMAMASK_DOUT2_ENABLE) } } # [doc = "Field `DMAMASK_DOUT3` reader - DMA is allowed to modify DOUT3"]
pub type DMAMASK_DOUT3_R = crate :: BitReader < DMAMASK_DOUT3_A > ; # [doc = "DMA is allowed to modify DOUT3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT3_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT3_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT3_ENABLE = 1 , } impl From < DMAMASK_DOUT3_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT3_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT3_A { match self . bits { false => DMAMASK_DOUT3_A :: DMAMASK_DOUT3_DISABLE , true => DMAMASK_DOUT3_A :: DMAMASK_DOUT3_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout3_disable (& self) -> bool { * self == DMAMASK_DOUT3_A :: DMAMASK_DOUT3_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout3_enable (& self) -> bool { * self == DMAMASK_DOUT3_A :: DMAMASK_DOUT3_ENABLE } } # [doc = "Field `DMAMASK_DOUT3` writer - DMA is allowed to modify DOUT3"]
pub type DMAMASK_DOUT3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT3_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout3_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT3_A :: DMAMASK_DOUT3_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout3_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT3_A :: DMAMASK_DOUT3_ENABLE) } } # [doc = "Field `DMAMASK_DOUT4` reader - DMA is allowed to modify DOUT4"]
pub type DMAMASK_DOUT4_R = crate :: BitReader < DMAMASK_DOUT4_A > ; # [doc = "DMA is allowed to modify DOUT4\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT4_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT4_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT4_ENABLE = 1 , } impl From < DMAMASK_DOUT4_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT4_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT4_A { match self . bits { false => DMAMASK_DOUT4_A :: DMAMASK_DOUT4_DISABLE , true => DMAMASK_DOUT4_A :: DMAMASK_DOUT4_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout4_disable (& self) -> bool { * self == DMAMASK_DOUT4_A :: DMAMASK_DOUT4_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout4_enable (& self) -> bool { * self == DMAMASK_DOUT4_A :: DMAMASK_DOUT4_ENABLE } } # [doc = "Field `DMAMASK_DOUT4` writer - DMA is allowed to modify DOUT4"]
pub type DMAMASK_DOUT4_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT4_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT4_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout4_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT4_A :: DMAMASK_DOUT4_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout4_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT4_A :: DMAMASK_DOUT4_ENABLE) } } # [doc = "Field `DMAMASK_DOUT5` reader - DMA is allowed to modify DOUT5"]
pub type DMAMASK_DOUT5_R = crate :: BitReader < DMAMASK_DOUT5_A > ; # [doc = "DMA is allowed to modify DOUT5\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT5_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT5_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT5_ENABLE = 1 , } impl From < DMAMASK_DOUT5_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT5_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT5_A { match self . bits { false => DMAMASK_DOUT5_A :: DMAMASK_DOUT5_DISABLE , true => DMAMASK_DOUT5_A :: DMAMASK_DOUT5_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout5_disable (& self) -> bool { * self == DMAMASK_DOUT5_A :: DMAMASK_DOUT5_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout5_enable (& self) -> bool { * self == DMAMASK_DOUT5_A :: DMAMASK_DOUT5_ENABLE } } # [doc = "Field `DMAMASK_DOUT5` writer - DMA is allowed to modify DOUT5"]
pub type DMAMASK_DOUT5_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT5_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT5_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout5_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT5_A :: DMAMASK_DOUT5_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout5_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT5_A :: DMAMASK_DOUT5_ENABLE) } } # [doc = "Field `DMAMASK_DOUT6` reader - DMA is allowed to modify DOUT6"]
pub type DMAMASK_DOUT6_R = crate :: BitReader < DMAMASK_DOUT6_A > ; # [doc = "DMA is allowed to modify DOUT6\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT6_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT6_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT6_ENABLE = 1 , } impl From < DMAMASK_DOUT6_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT6_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT6_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT6_A { match self . bits { false => DMAMASK_DOUT6_A :: DMAMASK_DOUT6_DISABLE , true => DMAMASK_DOUT6_A :: DMAMASK_DOUT6_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout6_disable (& self) -> bool { * self == DMAMASK_DOUT6_A :: DMAMASK_DOUT6_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout6_enable (& self) -> bool { * self == DMAMASK_DOUT6_A :: DMAMASK_DOUT6_ENABLE } } # [doc = "Field `DMAMASK_DOUT6` writer - DMA is allowed to modify DOUT6"]
pub type DMAMASK_DOUT6_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT6_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT6_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout6_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT6_A :: DMAMASK_DOUT6_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout6_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT6_A :: DMAMASK_DOUT6_ENABLE) } } # [doc = "Field `DMAMASK_DOUT7` reader - DMA is allowed to modify DOUT7"]
pub type DMAMASK_DOUT7_R = crate :: BitReader < DMAMASK_DOUT7_A > ; # [doc = "DMA is allowed to modify DOUT7\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT7_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT7_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT7_ENABLE = 1 , } impl From < DMAMASK_DOUT7_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT7_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT7_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT7_A { match self . bits { false => DMAMASK_DOUT7_A :: DMAMASK_DOUT7_DISABLE , true => DMAMASK_DOUT7_A :: DMAMASK_DOUT7_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout7_disable (& self) -> bool { * self == DMAMASK_DOUT7_A :: DMAMASK_DOUT7_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout7_enable (& self) -> bool { * self == DMAMASK_DOUT7_A :: DMAMASK_DOUT7_ENABLE } } # [doc = "Field `DMAMASK_DOUT7` writer - DMA is allowed to modify DOUT7"]
pub type DMAMASK_DOUT7_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT7_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT7_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout7_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT7_A :: DMAMASK_DOUT7_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout7_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT7_A :: DMAMASK_DOUT7_ENABLE) } } # [doc = "Field `DMAMASK_DOUT8` reader - DMA is allowed to modify DOUT8"]
pub type DMAMASK_DOUT8_R = crate :: BitReader < DMAMASK_DOUT8_A > ; # [doc = "DMA is allowed to modify DOUT8\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT8_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT8_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT8_ENABLE = 1 , } impl From < DMAMASK_DOUT8_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT8_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT8_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT8_A { match self . bits { false => DMAMASK_DOUT8_A :: DMAMASK_DOUT8_DISABLE , true => DMAMASK_DOUT8_A :: DMAMASK_DOUT8_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout8_disable (& self) -> bool { * self == DMAMASK_DOUT8_A :: DMAMASK_DOUT8_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout8_enable (& self) -> bool { * self == DMAMASK_DOUT8_A :: DMAMASK_DOUT8_ENABLE } } # [doc = "Field `DMAMASK_DOUT8` writer - DMA is allowed to modify DOUT8"]
pub type DMAMASK_DOUT8_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT8_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT8_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout8_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT8_A :: DMAMASK_DOUT8_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout8_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT8_A :: DMAMASK_DOUT8_ENABLE) } } # [doc = "Field `DMAMASK_DOUT9` reader - DMA is allowed to modify DOUT9"]
pub type DMAMASK_DOUT9_R = crate :: BitReader < DMAMASK_DOUT9_A > ; # [doc = "DMA is allowed to modify DOUT9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT9_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT9_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT9_ENABLE = 1 , } impl From < DMAMASK_DOUT9_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT9_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT9_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT9_A { match self . bits { false => DMAMASK_DOUT9_A :: DMAMASK_DOUT9_DISABLE , true => DMAMASK_DOUT9_A :: DMAMASK_DOUT9_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout9_disable (& self) -> bool { * self == DMAMASK_DOUT9_A :: DMAMASK_DOUT9_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout9_enable (& self) -> bool { * self == DMAMASK_DOUT9_A :: DMAMASK_DOUT9_ENABLE } } # [doc = "Field `DMAMASK_DOUT9` writer - DMA is allowed to modify DOUT9"]
pub type DMAMASK_DOUT9_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT9_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT9_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout9_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT9_A :: DMAMASK_DOUT9_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout9_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT9_A :: DMAMASK_DOUT9_ENABLE) } } # [doc = "Field `DMAMASK_DOUT10` reader - DMA is allowed to modify DOUT10"]
pub type DMAMASK_DOUT10_R = crate :: BitReader < DMAMASK_DOUT10_A > ; # [doc = "DMA is allowed to modify DOUT10\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT10_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT10_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT10_ENABLE = 1 , } impl From < DMAMASK_DOUT10_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT10_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT10_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT10_A { match self . bits { false => DMAMASK_DOUT10_A :: DMAMASK_DOUT10_DISABLE , true => DMAMASK_DOUT10_A :: DMAMASK_DOUT10_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout10_disable (& self) -> bool { * self == DMAMASK_DOUT10_A :: DMAMASK_DOUT10_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout10_enable (& self) -> bool { * self == DMAMASK_DOUT10_A :: DMAMASK_DOUT10_ENABLE } } # [doc = "Field `DMAMASK_DOUT10` writer - DMA is allowed to modify DOUT10"]
pub type DMAMASK_DOUT10_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT10_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT10_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout10_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT10_A :: DMAMASK_DOUT10_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout10_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT10_A :: DMAMASK_DOUT10_ENABLE) } } # [doc = "Field `DMAMASK_DOUT11` reader - DMA is allowed to modify DOUT11"]
pub type DMAMASK_DOUT11_R = crate :: BitReader < DMAMASK_DOUT11_A > ; # [doc = "DMA is allowed to modify DOUT11\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT11_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT11_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT11_ENABLE = 1 , } impl From < DMAMASK_DOUT11_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT11_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT11_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT11_A { match self . bits { false => DMAMASK_DOUT11_A :: DMAMASK_DOUT11_DISABLE , true => DMAMASK_DOUT11_A :: DMAMASK_DOUT11_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout11_disable (& self) -> bool { * self == DMAMASK_DOUT11_A :: DMAMASK_DOUT11_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout11_enable (& self) -> bool { * self == DMAMASK_DOUT11_A :: DMAMASK_DOUT11_ENABLE } } # [doc = "Field `DMAMASK_DOUT11` writer - DMA is allowed to modify DOUT11"]
pub type DMAMASK_DOUT11_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT11_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT11_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout11_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT11_A :: DMAMASK_DOUT11_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout11_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT11_A :: DMAMASK_DOUT11_ENABLE) } } # [doc = "Field `DMAMASK_DOUT12` reader - DMA is allowed to modify DOUT12"]
pub type DMAMASK_DOUT12_R = crate :: BitReader < DMAMASK_DOUT12_A > ; # [doc = "DMA is allowed to modify DOUT12\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT12_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT12_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT12_ENABLE = 1 , } impl From < DMAMASK_DOUT12_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT12_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT12_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT12_A { match self . bits { false => DMAMASK_DOUT12_A :: DMAMASK_DOUT12_DISABLE , true => DMAMASK_DOUT12_A :: DMAMASK_DOUT12_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout12_disable (& self) -> bool { * self == DMAMASK_DOUT12_A :: DMAMASK_DOUT12_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout12_enable (& self) -> bool { * self == DMAMASK_DOUT12_A :: DMAMASK_DOUT12_ENABLE } } # [doc = "Field `DMAMASK_DOUT12` writer - DMA is allowed to modify DOUT12"]
pub type DMAMASK_DOUT12_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT12_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT12_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout12_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT12_A :: DMAMASK_DOUT12_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout12_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT12_A :: DMAMASK_DOUT12_ENABLE) } } # [doc = "Field `DMAMASK_DOUT13` reader - DMA is allowed to modify DOUT13"]
pub type DMAMASK_DOUT13_R = crate :: BitReader < DMAMASK_DOUT13_A > ; # [doc = "DMA is allowed to modify DOUT13\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT13_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT13_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT13_ENABLE = 1 , } impl From < DMAMASK_DOUT13_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT13_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT13_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT13_A { match self . bits { false => DMAMASK_DOUT13_A :: DMAMASK_DOUT13_DISABLE , true => DMAMASK_DOUT13_A :: DMAMASK_DOUT13_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout13_disable (& self) -> bool { * self == DMAMASK_DOUT13_A :: DMAMASK_DOUT13_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout13_enable (& self) -> bool { * self == DMAMASK_DOUT13_A :: DMAMASK_DOUT13_ENABLE } } # [doc = "Field `DMAMASK_DOUT13` writer - DMA is allowed to modify DOUT13"]
pub type DMAMASK_DOUT13_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT13_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT13_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout13_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT13_A :: DMAMASK_DOUT13_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout13_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT13_A :: DMAMASK_DOUT13_ENABLE) } } # [doc = "Field `DMAMASK_DOUT14` reader - DMA is allowed to modify DOUT14"]
pub type DMAMASK_DOUT14_R = crate :: BitReader < DMAMASK_DOUT14_A > ; # [doc = "DMA is allowed to modify DOUT14\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT14_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT14_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT14_ENABLE = 1 , } impl From < DMAMASK_DOUT14_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT14_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT14_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT14_A { match self . bits { false => DMAMASK_DOUT14_A :: DMAMASK_DOUT14_DISABLE , true => DMAMASK_DOUT14_A :: DMAMASK_DOUT14_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout14_disable (& self) -> bool { * self == DMAMASK_DOUT14_A :: DMAMASK_DOUT14_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout14_enable (& self) -> bool { * self == DMAMASK_DOUT14_A :: DMAMASK_DOUT14_ENABLE } } # [doc = "Field `DMAMASK_DOUT14` writer - DMA is allowed to modify DOUT14"]
pub type DMAMASK_DOUT14_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT14_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT14_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout14_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT14_A :: DMAMASK_DOUT14_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout14_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT14_A :: DMAMASK_DOUT14_ENABLE) } } # [doc = "Field `DMAMASK_DOUT15` reader - DMA is allowed to modify DOUT15"]
pub type DMAMASK_DOUT15_R = crate :: BitReader < DMAMASK_DOUT15_A > ; # [doc = "DMA is allowed to modify DOUT15\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT15_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT15_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT15_ENABLE = 1 , } impl From < DMAMASK_DOUT15_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT15_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT15_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT15_A { match self . bits { false => DMAMASK_DOUT15_A :: DMAMASK_DOUT15_DISABLE , true => DMAMASK_DOUT15_A :: DMAMASK_DOUT15_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout15_disable (& self) -> bool { * self == DMAMASK_DOUT15_A :: DMAMASK_DOUT15_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout15_enable (& self) -> bool { * self == DMAMASK_DOUT15_A :: DMAMASK_DOUT15_ENABLE } } # [doc = "Field `DMAMASK_DOUT15` writer - DMA is allowed to modify DOUT15"]
pub type DMAMASK_DOUT15_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT15_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT15_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout15_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT15_A :: DMAMASK_DOUT15_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout15_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT15_A :: DMAMASK_DOUT15_ENABLE) } } # [doc = "Field `DMAMASK_DOUT16` reader - DMA is allowed to modify DOUT16"]
pub type DMAMASK_DOUT16_R = crate :: BitReader < DMAMASK_DOUT16_A > ; # [doc = "DMA is allowed to modify DOUT16\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT16_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT16_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT16_ENABLE = 1 , } impl From < DMAMASK_DOUT16_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT16_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT16_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT16_A { match self . bits { false => DMAMASK_DOUT16_A :: DMAMASK_DOUT16_DISABLE , true => DMAMASK_DOUT16_A :: DMAMASK_DOUT16_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout16_disable (& self) -> bool { * self == DMAMASK_DOUT16_A :: DMAMASK_DOUT16_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout16_enable (& self) -> bool { * self == DMAMASK_DOUT16_A :: DMAMASK_DOUT16_ENABLE } } # [doc = "Field `DMAMASK_DOUT16` writer - DMA is allowed to modify DOUT16"]
pub type DMAMASK_DOUT16_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT16_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT16_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout16_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT16_A :: DMAMASK_DOUT16_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout16_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT16_A :: DMAMASK_DOUT16_ENABLE) } } # [doc = "Field `DMAMASK_DOUT17` reader - DMA is allowed to modify DOUT17"]
pub type DMAMASK_DOUT17_R = crate :: BitReader < DMAMASK_DOUT17_A > ; # [doc = "DMA is allowed to modify DOUT17\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT17_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT17_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT17_ENABLE = 1 , } impl From < DMAMASK_DOUT17_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT17_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT17_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT17_A { match self . bits { false => DMAMASK_DOUT17_A :: DMAMASK_DOUT17_DISABLE , true => DMAMASK_DOUT17_A :: DMAMASK_DOUT17_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout17_disable (& self) -> bool { * self == DMAMASK_DOUT17_A :: DMAMASK_DOUT17_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout17_enable (& self) -> bool { * self == DMAMASK_DOUT17_A :: DMAMASK_DOUT17_ENABLE } } # [doc = "Field `DMAMASK_DOUT17` writer - DMA is allowed to modify DOUT17"]
pub type DMAMASK_DOUT17_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT17_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT17_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout17_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT17_A :: DMAMASK_DOUT17_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout17_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT17_A :: DMAMASK_DOUT17_ENABLE) } } # [doc = "Field `DMAMASK_DOUT18` reader - DMA is allowed to modify DOUT18"]
pub type DMAMASK_DOUT18_R = crate :: BitReader < DMAMASK_DOUT18_A > ; # [doc = "DMA is allowed to modify DOUT18\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT18_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT18_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT18_ENABLE = 1 , } impl From < DMAMASK_DOUT18_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT18_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT18_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT18_A { match self . bits { false => DMAMASK_DOUT18_A :: DMAMASK_DOUT18_DISABLE , true => DMAMASK_DOUT18_A :: DMAMASK_DOUT18_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout18_disable (& self) -> bool { * self == DMAMASK_DOUT18_A :: DMAMASK_DOUT18_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout18_enable (& self) -> bool { * self == DMAMASK_DOUT18_A :: DMAMASK_DOUT18_ENABLE } } # [doc = "Field `DMAMASK_DOUT18` writer - DMA is allowed to modify DOUT18"]
pub type DMAMASK_DOUT18_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT18_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT18_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout18_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT18_A :: DMAMASK_DOUT18_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout18_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT18_A :: DMAMASK_DOUT18_ENABLE) } } # [doc = "Field `DMAMASK_DOUT19` reader - DMA is allowed to modify DOUT19"]
pub type DMAMASK_DOUT19_R = crate :: BitReader < DMAMASK_DOUT19_A > ; # [doc = "DMA is allowed to modify DOUT19\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT19_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT19_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT19_ENABLE = 1 , } impl From < DMAMASK_DOUT19_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT19_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT19_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT19_A { match self . bits { false => DMAMASK_DOUT19_A :: DMAMASK_DOUT19_DISABLE , true => DMAMASK_DOUT19_A :: DMAMASK_DOUT19_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout19_disable (& self) -> bool { * self == DMAMASK_DOUT19_A :: DMAMASK_DOUT19_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout19_enable (& self) -> bool { * self == DMAMASK_DOUT19_A :: DMAMASK_DOUT19_ENABLE } } # [doc = "Field `DMAMASK_DOUT19` writer - DMA is allowed to modify DOUT19"]
pub type DMAMASK_DOUT19_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT19_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT19_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout19_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT19_A :: DMAMASK_DOUT19_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout19_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT19_A :: DMAMASK_DOUT19_ENABLE) } } # [doc = "Field `DMAMASK_DOUT20` reader - DMA is allowed to modify DOUT20"]
pub type DMAMASK_DOUT20_R = crate :: BitReader < DMAMASK_DOUT20_A > ; # [doc = "DMA is allowed to modify DOUT20\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT20_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT20_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT20_ENABLE = 1 , } impl From < DMAMASK_DOUT20_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT20_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT20_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT20_A { match self . bits { false => DMAMASK_DOUT20_A :: DMAMASK_DOUT20_DISABLE , true => DMAMASK_DOUT20_A :: DMAMASK_DOUT20_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout20_disable (& self) -> bool { * self == DMAMASK_DOUT20_A :: DMAMASK_DOUT20_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout20_enable (& self) -> bool { * self == DMAMASK_DOUT20_A :: DMAMASK_DOUT20_ENABLE } } # [doc = "Field `DMAMASK_DOUT20` writer - DMA is allowed to modify DOUT20"]
pub type DMAMASK_DOUT20_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT20_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT20_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout20_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT20_A :: DMAMASK_DOUT20_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout20_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT20_A :: DMAMASK_DOUT20_ENABLE) } } # [doc = "Field `DMAMASK_DOUT21` reader - DMA is allowed to modify DOUT21"]
pub type DMAMASK_DOUT21_R = crate :: BitReader < DMAMASK_DOUT21_A > ; # [doc = "DMA is allowed to modify DOUT21\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT21_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT21_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT21_ENABLE = 1 , } impl From < DMAMASK_DOUT21_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT21_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT21_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT21_A { match self . bits { false => DMAMASK_DOUT21_A :: DMAMASK_DOUT21_DISABLE , true => DMAMASK_DOUT21_A :: DMAMASK_DOUT21_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout21_disable (& self) -> bool { * self == DMAMASK_DOUT21_A :: DMAMASK_DOUT21_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout21_enable (& self) -> bool { * self == DMAMASK_DOUT21_A :: DMAMASK_DOUT21_ENABLE } } # [doc = "Field `DMAMASK_DOUT21` writer - DMA is allowed to modify DOUT21"]
pub type DMAMASK_DOUT21_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT21_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT21_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout21_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT21_A :: DMAMASK_DOUT21_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout21_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT21_A :: DMAMASK_DOUT21_ENABLE) } } # [doc = "Field `DMAMASK_DOUT22` reader - DMA is allowed to modify DOUT22"]
pub type DMAMASK_DOUT22_R = crate :: BitReader < DMAMASK_DOUT22_A > ; # [doc = "DMA is allowed to modify DOUT22\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT22_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT22_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT22_ENABLE = 1 , } impl From < DMAMASK_DOUT22_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT22_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT22_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT22_A { match self . bits { false => DMAMASK_DOUT22_A :: DMAMASK_DOUT22_DISABLE , true => DMAMASK_DOUT22_A :: DMAMASK_DOUT22_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout22_disable (& self) -> bool { * self == DMAMASK_DOUT22_A :: DMAMASK_DOUT22_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout22_enable (& self) -> bool { * self == DMAMASK_DOUT22_A :: DMAMASK_DOUT22_ENABLE } } # [doc = "Field `DMAMASK_DOUT22` writer - DMA is allowed to modify DOUT22"]
pub type DMAMASK_DOUT22_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT22_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT22_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout22_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT22_A :: DMAMASK_DOUT22_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout22_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT22_A :: DMAMASK_DOUT22_ENABLE) } } # [doc = "Field `DMAMASK_DOUT23` reader - DMA is allowed to modify DOUT23"]
pub type DMAMASK_DOUT23_R = crate :: BitReader < DMAMASK_DOUT23_A > ; # [doc = "DMA is allowed to modify DOUT23\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT23_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT23_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT23_ENABLE = 1 , } impl From < DMAMASK_DOUT23_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT23_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT23_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT23_A { match self . bits { false => DMAMASK_DOUT23_A :: DMAMASK_DOUT23_DISABLE , true => DMAMASK_DOUT23_A :: DMAMASK_DOUT23_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout23_disable (& self) -> bool { * self == DMAMASK_DOUT23_A :: DMAMASK_DOUT23_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout23_enable (& self) -> bool { * self == DMAMASK_DOUT23_A :: DMAMASK_DOUT23_ENABLE } } # [doc = "Field `DMAMASK_DOUT23` writer - DMA is allowed to modify DOUT23"]
pub type DMAMASK_DOUT23_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT23_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT23_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout23_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT23_A :: DMAMASK_DOUT23_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout23_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT23_A :: DMAMASK_DOUT23_ENABLE) } } # [doc = "Field `DMAMASK_DOUT24` reader - DMA is allowed to modify DOUT24"]
pub type DMAMASK_DOUT24_R = crate :: BitReader < DMAMASK_DOUT24_A > ; # [doc = "DMA is allowed to modify DOUT24\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT24_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT24_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT24_ENABLE = 1 , } impl From < DMAMASK_DOUT24_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT24_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT24_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT24_A { match self . bits { false => DMAMASK_DOUT24_A :: DMAMASK_DOUT24_DISABLE , true => DMAMASK_DOUT24_A :: DMAMASK_DOUT24_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout24_disable (& self) -> bool { * self == DMAMASK_DOUT24_A :: DMAMASK_DOUT24_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout24_enable (& self) -> bool { * self == DMAMASK_DOUT24_A :: DMAMASK_DOUT24_ENABLE } } # [doc = "Field `DMAMASK_DOUT24` writer - DMA is allowed to modify DOUT24"]
pub type DMAMASK_DOUT24_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT24_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT24_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout24_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT24_A :: DMAMASK_DOUT24_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout24_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT24_A :: DMAMASK_DOUT24_ENABLE) } } # [doc = "Field `DMAMASK_DOUT25` reader - DMA is allowed to modify DOUT25"]
pub type DMAMASK_DOUT25_R = crate :: BitReader < DMAMASK_DOUT25_A > ; # [doc = "DMA is allowed to modify DOUT25\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT25_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT25_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT25_ENABLE = 1 , } impl From < DMAMASK_DOUT25_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT25_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT25_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT25_A { match self . bits { false => DMAMASK_DOUT25_A :: DMAMASK_DOUT25_DISABLE , true => DMAMASK_DOUT25_A :: DMAMASK_DOUT25_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout25_disable (& self) -> bool { * self == DMAMASK_DOUT25_A :: DMAMASK_DOUT25_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout25_enable (& self) -> bool { * self == DMAMASK_DOUT25_A :: DMAMASK_DOUT25_ENABLE } } # [doc = "Field `DMAMASK_DOUT25` writer - DMA is allowed to modify DOUT25"]
pub type DMAMASK_DOUT25_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT25_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT25_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout25_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT25_A :: DMAMASK_DOUT25_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout25_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT25_A :: DMAMASK_DOUT25_ENABLE) } } # [doc = "Field `DMAMASK_DOUT26` reader - DMA is allowed to modify DOUT26"]
pub type DMAMASK_DOUT26_R = crate :: BitReader < DMAMASK_DOUT26_A > ; # [doc = "DMA is allowed to modify DOUT26\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT26_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT26_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT26_ENABLE = 1 , } impl From < DMAMASK_DOUT26_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT26_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT26_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT26_A { match self . bits { false => DMAMASK_DOUT26_A :: DMAMASK_DOUT26_DISABLE , true => DMAMASK_DOUT26_A :: DMAMASK_DOUT26_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout26_disable (& self) -> bool { * self == DMAMASK_DOUT26_A :: DMAMASK_DOUT26_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout26_enable (& self) -> bool { * self == DMAMASK_DOUT26_A :: DMAMASK_DOUT26_ENABLE } } # [doc = "Field `DMAMASK_DOUT26` writer - DMA is allowed to modify DOUT26"]
pub type DMAMASK_DOUT26_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT26_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT26_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout26_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT26_A :: DMAMASK_DOUT26_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout26_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT26_A :: DMAMASK_DOUT26_ENABLE) } } # [doc = "Field `DMAMASK_DOUT27` reader - DMA is allowed to modify DOUT27"]
pub type DMAMASK_DOUT27_R = crate :: BitReader < DMAMASK_DOUT27_A > ; # [doc = "DMA is allowed to modify DOUT27\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT27_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT27_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT27_ENABLE = 1 , } impl From < DMAMASK_DOUT27_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT27_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT27_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT27_A { match self . bits { false => DMAMASK_DOUT27_A :: DMAMASK_DOUT27_DISABLE , true => DMAMASK_DOUT27_A :: DMAMASK_DOUT27_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout27_disable (& self) -> bool { * self == DMAMASK_DOUT27_A :: DMAMASK_DOUT27_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout27_enable (& self) -> bool { * self == DMAMASK_DOUT27_A :: DMAMASK_DOUT27_ENABLE } } # [doc = "Field `DMAMASK_DOUT27` writer - DMA is allowed to modify DOUT27"]
pub type DMAMASK_DOUT27_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT27_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT27_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout27_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT27_A :: DMAMASK_DOUT27_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout27_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT27_A :: DMAMASK_DOUT27_ENABLE) } } # [doc = "Field `DMAMASK_DOUT28` reader - DMA is allowed to modify DOUT28"]
pub type DMAMASK_DOUT28_R = crate :: BitReader < DMAMASK_DOUT28_A > ; # [doc = "DMA is allowed to modify DOUT28\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT28_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT28_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT28_ENABLE = 1 , } impl From < DMAMASK_DOUT28_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT28_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT28_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT28_A { match self . bits { false => DMAMASK_DOUT28_A :: DMAMASK_DOUT28_DISABLE , true => DMAMASK_DOUT28_A :: DMAMASK_DOUT28_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout28_disable (& self) -> bool { * self == DMAMASK_DOUT28_A :: DMAMASK_DOUT28_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout28_enable (& self) -> bool { * self == DMAMASK_DOUT28_A :: DMAMASK_DOUT28_ENABLE } } # [doc = "Field `DMAMASK_DOUT28` writer - DMA is allowed to modify DOUT28"]
pub type DMAMASK_DOUT28_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT28_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT28_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout28_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT28_A :: DMAMASK_DOUT28_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout28_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT28_A :: DMAMASK_DOUT28_ENABLE) } } # [doc = "Field `DMAMASK_DOUT29` reader - DMA is allowed to modify DOUT29"]
pub type DMAMASK_DOUT29_R = crate :: BitReader < DMAMASK_DOUT29_A > ; # [doc = "DMA is allowed to modify DOUT29\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT29_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT29_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT29_ENABLE = 1 , } impl From < DMAMASK_DOUT29_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT29_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT29_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT29_A { match self . bits { false => DMAMASK_DOUT29_A :: DMAMASK_DOUT29_DISABLE , true => DMAMASK_DOUT29_A :: DMAMASK_DOUT29_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout29_disable (& self) -> bool { * self == DMAMASK_DOUT29_A :: DMAMASK_DOUT29_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout29_enable (& self) -> bool { * self == DMAMASK_DOUT29_A :: DMAMASK_DOUT29_ENABLE } } # [doc = "Field `DMAMASK_DOUT29` writer - DMA is allowed to modify DOUT29"]
pub type DMAMASK_DOUT29_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT29_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT29_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout29_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT29_A :: DMAMASK_DOUT29_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout29_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT29_A :: DMAMASK_DOUT29_ENABLE) } } # [doc = "Field `DMAMASK_DOUT30` reader - DMA is allowed to modify DOUT30"]
pub type DMAMASK_DOUT30_R = crate :: BitReader < DMAMASK_DOUT30_A > ; # [doc = "DMA is allowed to modify DOUT30\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT30_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT30_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT30_ENABLE = 1 , } impl From < DMAMASK_DOUT30_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT30_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT30_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT30_A { match self . bits { false => DMAMASK_DOUT30_A :: DMAMASK_DOUT30_DISABLE , true => DMAMASK_DOUT30_A :: DMAMASK_DOUT30_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout30_disable (& self) -> bool { * self == DMAMASK_DOUT30_A :: DMAMASK_DOUT30_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout30_enable (& self) -> bool { * self == DMAMASK_DOUT30_A :: DMAMASK_DOUT30_ENABLE } } # [doc = "Field `DMAMASK_DOUT30` writer - DMA is allowed to modify DOUT30"]
pub type DMAMASK_DOUT30_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT30_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT30_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout30_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT30_A :: DMAMASK_DOUT30_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout30_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT30_A :: DMAMASK_DOUT30_ENABLE) } } # [doc = "Field `DMAMASK_DOUT31` reader - DMA is allowed to modify DOUT31"]
pub type DMAMASK_DOUT31_R = crate :: BitReader < DMAMASK_DOUT31_A > ; # [doc = "DMA is allowed to modify DOUT31\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAMASK_DOUT31_A { # [doc = "0: DISABLE"]
DMAMASK_DOUT31_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAMASK_DOUT31_ENABLE = 1 , } impl From < DMAMASK_DOUT31_A > for bool { # [inline (always)]
fn from (variant : DMAMASK_DOUT31_A) -> Self { variant as u8 != 0 } } impl DMAMASK_DOUT31_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAMASK_DOUT31_A { match self . bits { false => DMAMASK_DOUT31_A :: DMAMASK_DOUT31_DISABLE , true => DMAMASK_DOUT31_A :: DMAMASK_DOUT31_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmamask_dout31_disable (& self) -> bool { * self == DMAMASK_DOUT31_A :: DMAMASK_DOUT31_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmamask_dout31_enable (& self) -> bool { * self == DMAMASK_DOUT31_A :: DMAMASK_DOUT31_ENABLE } } # [doc = "Field `DMAMASK_DOUT31` writer - DMA is allowed to modify DOUT31"]
pub type DMAMASK_DOUT31_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAMASK_DOUT31_A > ; impl < 'a , REG , const O : u8 > DMAMASK_DOUT31_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmamask_dout31_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT31_A :: DMAMASK_DOUT31_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmamask_dout31_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAMASK_DOUT31_A :: DMAMASK_DOUT31_ENABLE) } } impl R { # [doc = "Bit 0 - DMA is allowed to modify DOUT0"]
# [inline (always)]
pub fn dmamask_dout0 (& self) -> DMAMASK_DOUT0_R { DMAMASK_DOUT0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DMA is allowed to modify DOUT1"]
# [inline (always)]
pub fn dmamask_dout1 (& self) -> DMAMASK_DOUT1_R { DMAMASK_DOUT1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DMA is allowed to modify DOUT2"]
# [inline (always)]
pub fn dmamask_dout2 (& self) -> DMAMASK_DOUT2_R { DMAMASK_DOUT2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - DMA is allowed to modify DOUT3"]
# [inline (always)]
pub fn dmamask_dout3 (& self) -> DMAMASK_DOUT3_R { DMAMASK_DOUT3_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - DMA is allowed to modify DOUT4"]
# [inline (always)]
pub fn dmamask_dout4 (& self) -> DMAMASK_DOUT4_R { DMAMASK_DOUT4_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - DMA is allowed to modify DOUT5"]
# [inline (always)]
pub fn dmamask_dout5 (& self) -> DMAMASK_DOUT5_R { DMAMASK_DOUT5_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - DMA is allowed to modify DOUT6"]
# [inline (always)]
pub fn dmamask_dout6 (& self) -> DMAMASK_DOUT6_R { DMAMASK_DOUT6_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - DMA is allowed to modify DOUT7"]
# [inline (always)]
pub fn dmamask_dout7 (& self) -> DMAMASK_DOUT7_R { DMAMASK_DOUT7_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - DMA is allowed to modify DOUT8"]
# [inline (always)]
pub fn dmamask_dout8 (& self) -> DMAMASK_DOUT8_R { DMAMASK_DOUT8_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DMA is allowed to modify DOUT9"]
# [inline (always)]
pub fn dmamask_dout9 (& self) -> DMAMASK_DOUT9_R { DMAMASK_DOUT9_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DMA is allowed to modify DOUT10"]
# [inline (always)]
pub fn dmamask_dout10 (& self) -> DMAMASK_DOUT10_R { DMAMASK_DOUT10_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA is allowed to modify DOUT11"]
# [inline (always)]
pub fn dmamask_dout11 (& self) -> DMAMASK_DOUT11_R { DMAMASK_DOUT11_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA is allowed to modify DOUT12"]
# [inline (always)]
pub fn dmamask_dout12 (& self) -> DMAMASK_DOUT12_R { DMAMASK_DOUT12_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - DMA is allowed to modify DOUT13"]
# [inline (always)]
pub fn dmamask_dout13 (& self) -> DMAMASK_DOUT13_R { DMAMASK_DOUT13_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - DMA is allowed to modify DOUT14"]
# [inline (always)]
pub fn dmamask_dout14 (& self) -> DMAMASK_DOUT14_R { DMAMASK_DOUT14_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DMA is allowed to modify DOUT15"]
# [inline (always)]
pub fn dmamask_dout15 (& self) -> DMAMASK_DOUT15_R { DMAMASK_DOUT15_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DMA is allowed to modify DOUT16"]
# [inline (always)]
pub fn dmamask_dout16 (& self) -> DMAMASK_DOUT16_R { DMAMASK_DOUT16_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - DMA is allowed to modify DOUT17"]
# [inline (always)]
pub fn dmamask_dout17 (& self) -> DMAMASK_DOUT17_R { DMAMASK_DOUT17_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - DMA is allowed to modify DOUT18"]
# [inline (always)]
pub fn dmamask_dout18 (& self) -> DMAMASK_DOUT18_R { DMAMASK_DOUT18_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - DMA is allowed to modify DOUT19"]
# [inline (always)]
pub fn dmamask_dout19 (& self) -> DMAMASK_DOUT19_R { DMAMASK_DOUT19_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - DMA is allowed to modify DOUT20"]
# [inline (always)]
pub fn dmamask_dout20 (& self) -> DMAMASK_DOUT20_R { DMAMASK_DOUT20_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - DMA is allowed to modify DOUT21"]
# [inline (always)]
pub fn dmamask_dout21 (& self) -> DMAMASK_DOUT21_R { DMAMASK_DOUT21_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - DMA is allowed to modify DOUT22"]
# [inline (always)]
pub fn dmamask_dout22 (& self) -> DMAMASK_DOUT22_R { DMAMASK_DOUT22_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - DMA is allowed to modify DOUT23"]
# [inline (always)]
pub fn dmamask_dout23 (& self) -> DMAMASK_DOUT23_R { DMAMASK_DOUT23_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - DMA is allowed to modify DOUT24"]
# [inline (always)]
pub fn dmamask_dout24 (& self) -> DMAMASK_DOUT24_R { DMAMASK_DOUT24_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA is allowed to modify DOUT25"]
# [inline (always)]
pub fn dmamask_dout25 (& self) -> DMAMASK_DOUT25_R { DMAMASK_DOUT25_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DMA is allowed to modify DOUT26"]
# [inline (always)]
pub fn dmamask_dout26 (& self) -> DMAMASK_DOUT26_R { DMAMASK_DOUT26_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - DMA is allowed to modify DOUT27"]
# [inline (always)]
pub fn dmamask_dout27 (& self) -> DMAMASK_DOUT27_R { DMAMASK_DOUT27_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - DMA is allowed to modify DOUT28"]
# [inline (always)]
pub fn dmamask_dout28 (& self) -> DMAMASK_DOUT28_R { DMAMASK_DOUT28_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - DMA is allowed to modify DOUT29"]
# [inline (always)]
pub fn dmamask_dout29 (& self) -> DMAMASK_DOUT29_R { DMAMASK_DOUT29_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - DMA is allowed to modify DOUT30"]
# [inline (always)]
pub fn dmamask_dout30 (& self) -> DMAMASK_DOUT30_R { DMAMASK_DOUT30_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - DMA is allowed to modify DOUT31"]
# [inline (always)]
pub fn dmamask_dout31 (& self) -> DMAMASK_DOUT31_R { DMAMASK_DOUT31_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - DMA is allowed to modify DOUT0"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout0 (& mut self) -> DMAMASK_DOUT0_W < DMAMASK_SPEC , 0 > { DMAMASK_DOUT0_W :: new (self) } # [doc = "Bit 1 - DMA is allowed to modify DOUT1"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout1 (& mut self) -> DMAMASK_DOUT1_W < DMAMASK_SPEC , 1 > { DMAMASK_DOUT1_W :: new (self) } # [doc = "Bit 2 - DMA is allowed to modify DOUT2"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout2 (& mut self) -> DMAMASK_DOUT2_W < DMAMASK_SPEC , 2 > { DMAMASK_DOUT2_W :: new (self) } # [doc = "Bit 3 - DMA is allowed to modify DOUT3"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout3 (& mut self) -> DMAMASK_DOUT3_W < DMAMASK_SPEC , 3 > { DMAMASK_DOUT3_W :: new (self) } # [doc = "Bit 4 - DMA is allowed to modify DOUT4"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout4 (& mut self) -> DMAMASK_DOUT4_W < DMAMASK_SPEC , 4 > { DMAMASK_DOUT4_W :: new (self) } # [doc = "Bit 5 - DMA is allowed to modify DOUT5"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout5 (& mut self) -> DMAMASK_DOUT5_W < DMAMASK_SPEC , 5 > { DMAMASK_DOUT5_W :: new (self) } # [doc = "Bit 6 - DMA is allowed to modify DOUT6"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout6 (& mut self) -> DMAMASK_DOUT6_W < DMAMASK_SPEC , 6 > { DMAMASK_DOUT6_W :: new (self) } # [doc = "Bit 7 - DMA is allowed to modify DOUT7"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout7 (& mut self) -> DMAMASK_DOUT7_W < DMAMASK_SPEC , 7 > { DMAMASK_DOUT7_W :: new (self) } # [doc = "Bit 8 - DMA is allowed to modify DOUT8"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout8 (& mut self) -> DMAMASK_DOUT8_W < DMAMASK_SPEC , 8 > { DMAMASK_DOUT8_W :: new (self) } # [doc = "Bit 9 - DMA is allowed to modify DOUT9"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout9 (& mut self) -> DMAMASK_DOUT9_W < DMAMASK_SPEC , 9 > { DMAMASK_DOUT9_W :: new (self) } # [doc = "Bit 10 - DMA is allowed to modify DOUT10"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout10 (& mut self) -> DMAMASK_DOUT10_W < DMAMASK_SPEC , 10 > { DMAMASK_DOUT10_W :: new (self) } # [doc = "Bit 11 - DMA is allowed to modify DOUT11"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout11 (& mut self) -> DMAMASK_DOUT11_W < DMAMASK_SPEC , 11 > { DMAMASK_DOUT11_W :: new (self) } # [doc = "Bit 12 - DMA is allowed to modify DOUT12"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout12 (& mut self) -> DMAMASK_DOUT12_W < DMAMASK_SPEC , 12 > { DMAMASK_DOUT12_W :: new (self) } # [doc = "Bit 13 - DMA is allowed to modify DOUT13"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout13 (& mut self) -> DMAMASK_DOUT13_W < DMAMASK_SPEC , 13 > { DMAMASK_DOUT13_W :: new (self) } # [doc = "Bit 14 - DMA is allowed to modify DOUT14"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout14 (& mut self) -> DMAMASK_DOUT14_W < DMAMASK_SPEC , 14 > { DMAMASK_DOUT14_W :: new (self) } # [doc = "Bit 15 - DMA is allowed to modify DOUT15"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout15 (& mut self) -> DMAMASK_DOUT15_W < DMAMASK_SPEC , 15 > { DMAMASK_DOUT15_W :: new (self) } # [doc = "Bit 16 - DMA is allowed to modify DOUT16"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout16 (& mut self) -> DMAMASK_DOUT16_W < DMAMASK_SPEC , 16 > { DMAMASK_DOUT16_W :: new (self) } # [doc = "Bit 17 - DMA is allowed to modify DOUT17"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout17 (& mut self) -> DMAMASK_DOUT17_W < DMAMASK_SPEC , 17 > { DMAMASK_DOUT17_W :: new (self) } # [doc = "Bit 18 - DMA is allowed to modify DOUT18"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout18 (& mut self) -> DMAMASK_DOUT18_W < DMAMASK_SPEC , 18 > { DMAMASK_DOUT18_W :: new (self) } # [doc = "Bit 19 - DMA is allowed to modify DOUT19"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout19 (& mut self) -> DMAMASK_DOUT19_W < DMAMASK_SPEC , 19 > { DMAMASK_DOUT19_W :: new (self) } # [doc = "Bit 20 - DMA is allowed to modify DOUT20"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout20 (& mut self) -> DMAMASK_DOUT20_W < DMAMASK_SPEC , 20 > { DMAMASK_DOUT20_W :: new (self) } # [doc = "Bit 21 - DMA is allowed to modify DOUT21"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout21 (& mut self) -> DMAMASK_DOUT21_W < DMAMASK_SPEC , 21 > { DMAMASK_DOUT21_W :: new (self) } # [doc = "Bit 22 - DMA is allowed to modify DOUT22"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout22 (& mut self) -> DMAMASK_DOUT22_W < DMAMASK_SPEC , 22 > { DMAMASK_DOUT22_W :: new (self) } # [doc = "Bit 23 - DMA is allowed to modify DOUT23"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout23 (& mut self) -> DMAMASK_DOUT23_W < DMAMASK_SPEC , 23 > { DMAMASK_DOUT23_W :: new (self) } # [doc = "Bit 24 - DMA is allowed to modify DOUT24"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout24 (& mut self) -> DMAMASK_DOUT24_W < DMAMASK_SPEC , 24 > { DMAMASK_DOUT24_W :: new (self) } # [doc = "Bit 25 - DMA is allowed to modify DOUT25"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout25 (& mut self) -> DMAMASK_DOUT25_W < DMAMASK_SPEC , 25 > { DMAMASK_DOUT25_W :: new (self) } # [doc = "Bit 26 - DMA is allowed to modify DOUT26"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout26 (& mut self) -> DMAMASK_DOUT26_W < DMAMASK_SPEC , 26 > { DMAMASK_DOUT26_W :: new (self) } # [doc = "Bit 27 - DMA is allowed to modify DOUT27"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout27 (& mut self) -> DMAMASK_DOUT27_W < DMAMASK_SPEC , 27 > { DMAMASK_DOUT27_W :: new (self) } # [doc = "Bit 28 - DMA is allowed to modify DOUT28"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout28 (& mut self) -> DMAMASK_DOUT28_W < DMAMASK_SPEC , 28 > { DMAMASK_DOUT28_W :: new (self) } # [doc = "Bit 29 - DMA is allowed to modify DOUT29"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout29 (& mut self) -> DMAMASK_DOUT29_W < DMAMASK_SPEC , 29 > { DMAMASK_DOUT29_W :: new (self) } # [doc = "Bit 30 - DMA is allowed to modify DOUT30"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout30 (& mut self) -> DMAMASK_DOUT30_W < DMAMASK_SPEC , 30 > { DMAMASK_DOUT30_W :: new (self) } # [doc = "Bit 31 - DMA is allowed to modify DOUT31"]
# [inline (always)]
# [must_use]
pub fn dmamask_dout31 (& mut self) -> DMAMASK_DOUT31_W < DMAMASK_SPEC , 31 > { DMAMASK_DOUT31_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA Write MASK\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmamask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmamask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMAMASK_SPEC ; impl crate :: RegisterSpec for DMAMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmamask::R`](R) reader structure"]
impl crate :: Readable for DMAMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmamask::W`](W) writer structure"]
impl crate :: Writable for DMAMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DMAMASK to value 0"]
impl crate :: Resettable for DMAMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SUB1CFG (rw) register accessor: Subscriber 1 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sub1cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sub1cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sub1cfg`]
module"]
pub type SUB1CFG = crate :: Reg < sub1cfg :: SUB1CFG_SPEC > ; # [doc = "Subscriber 1 configuration"]
pub mod sub1cfg { # [doc = "Register `SUB1CFG` reader"]
pub type R = crate :: R < SUB1CFG_SPEC > ; # [doc = "Register `SUB1CFG` writer"]
pub type W = crate :: W < SUB1CFG_SPEC > ; # [doc = "Field `SUB1CFG_ENABLE` reader - This bit is used to enable subscriber 1 event."]
pub type SUB1CFG_ENABLE_R = crate :: BitReader < SUB1CFG_ENABLE_A > ; # [doc = "This bit is used to enable subscriber 1 event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SUB1CFG_ENABLE_A { # [doc = "0: CLR"]
SUB1CFG_ENABLE_CLR = 0 , # [doc = "1: SET"]
SUB1CFG_ENABLE_SET = 1 , } impl From < SUB1CFG_ENABLE_A > for bool { # [inline (always)]
fn from (variant : SUB1CFG_ENABLE_A) -> Self { variant as u8 != 0 } } impl SUB1CFG_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SUB1CFG_ENABLE_A { match self . bits { false => SUB1CFG_ENABLE_A :: SUB1CFG_ENABLE_CLR , true => SUB1CFG_ENABLE_A :: SUB1CFG_ENABLE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_sub1cfg_enable_clr (& self) -> bool { * self == SUB1CFG_ENABLE_A :: SUB1CFG_ENABLE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_sub1cfg_enable_set (& self) -> bool { * self == SUB1CFG_ENABLE_A :: SUB1CFG_ENABLE_SET } } # [doc = "Field `SUB1CFG_ENABLE` writer - This bit is used to enable subscriber 1 event."]
pub type SUB1CFG_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SUB1CFG_ENABLE_A > ; impl < 'a , REG , const O : u8 > SUB1CFG_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn sub1cfg_enable_clr (self) -> & 'a mut crate :: W < REG > { self . variant (SUB1CFG_ENABLE_A :: SUB1CFG_ENABLE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn sub1cfg_enable_set (self) -> & 'a mut crate :: W < REG > { self . variant (SUB1CFG_ENABLE_A :: SUB1CFG_ENABLE_SET) } } # [doc = "Field `SUB1CFG_OUTPOLICY` reader - These bits configure the output policy for subscriber 1 event."]
pub type SUB1CFG_OUTPOLICY_R = crate :: FieldReader < SUB1CFG_OUTPOLICY_A > ; # [doc = "These bits configure the output policy for subscriber 1 event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SUB1CFG_OUTPOLICY_A { # [doc = "0: SET"]
SUB1CFG_OUTPOLICY_SET = 0 , # [doc = "1: CLR"]
SUB1CFG_OUTPOLICY_CLR = 1 , # [doc = "2: TOGGLE"]
SUB1CFG_OUTPOLICY_TOGGLE = 2 , } impl From < SUB1CFG_OUTPOLICY_A > for u8 { # [inline (always)]
fn from (variant : SUB1CFG_OUTPOLICY_A) -> Self { variant as _ } } impl crate :: FieldSpec for SUB1CFG_OUTPOLICY_A { type Ux = u8 ; } impl SUB1CFG_OUTPOLICY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SUB1CFG_OUTPOLICY_A > { match self . bits { 0 => Some (SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_SET) , 1 => Some (SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_CLR) , 2 => Some (SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_TOGGLE) , _ => None , } } # [doc = "SET"]
# [inline (always)]
pub fn is_sub1cfg_outpolicy_set (& self) -> bool { * self == SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_SET } # [doc = "CLR"]
# [inline (always)]
pub fn is_sub1cfg_outpolicy_clr (& self) -> bool { * self == SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_CLR } # [doc = "TOGGLE"]
# [inline (always)]
pub fn is_sub1cfg_outpolicy_toggle (& self) -> bool { * self == SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_TOGGLE } } # [doc = "Field `SUB1CFG_OUTPOLICY` writer - These bits configure the output policy for subscriber 1 event."]
pub type SUB1CFG_OUTPOLICY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , SUB1CFG_OUTPOLICY_A > ; impl < 'a , REG , const O : u8 > SUB1CFG_OUTPOLICY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SET"]
# [inline (always)]
pub fn sub1cfg_outpolicy_set (self) -> & 'a mut crate :: W < REG > { self . variant (SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_SET) } # [doc = "CLR"]
# [inline (always)]
pub fn sub1cfg_outpolicy_clr (self) -> & 'a mut crate :: W < REG > { self . variant (SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_CLR) } # [doc = "TOGGLE"]
# [inline (always)]
pub fn sub1cfg_outpolicy_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (SUB1CFG_OUTPOLICY_A :: SUB1CFG_OUTPOLICY_TOGGLE) } } # [doc = "Field `SUB1CFG_INDEX` reader - indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"]
pub type SUB1CFG_INDEX_R = crate :: FieldReader < SUB1CFG_INDEX_A > ; # [doc = "indicates the specific bit in the upper 16 bits that is targeted by the subscriber action\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SUB1CFG_INDEX_A { # [doc = "0: MIN"]
SUB1CFG_INDEX_MIN = 0 , # [doc = "15: MAX"]
SUB1CFG_INDEX_MAX = 15 , } impl From < SUB1CFG_INDEX_A > for u8 { # [inline (always)]
fn from (variant : SUB1CFG_INDEX_A) -> Self { variant as _ } } impl crate :: FieldSpec for SUB1CFG_INDEX_A { type Ux = u8 ; } impl SUB1CFG_INDEX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SUB1CFG_INDEX_A > { match self . bits { 0 => Some (SUB1CFG_INDEX_A :: SUB1CFG_INDEX_MIN) , 15 => Some (SUB1CFG_INDEX_A :: SUB1CFG_INDEX_MAX) , _ => None , } } # [doc = "MIN"]
# [inline (always)]
pub fn is_sub1cfg_index_min (& self) -> bool { * self == SUB1CFG_INDEX_A :: SUB1CFG_INDEX_MIN } # [doc = "MAX"]
# [inline (always)]
pub fn is_sub1cfg_index_max (& self) -> bool { * self == SUB1CFG_INDEX_A :: SUB1CFG_INDEX_MAX } } # [doc = "Field `SUB1CFG_INDEX` writer - indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"]
pub type SUB1CFG_INDEX_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , SUB1CFG_INDEX_A > ; impl < 'a , REG , const O : u8 > SUB1CFG_INDEX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "MIN"]
# [inline (always)]
pub fn sub1cfg_index_min (self) -> & 'a mut crate :: W < REG > { self . variant (SUB1CFG_INDEX_A :: SUB1CFG_INDEX_MIN) } # [doc = "MAX"]
# [inline (always)]
pub fn sub1cfg_index_max (self) -> & 'a mut crate :: W < REG > { self . variant (SUB1CFG_INDEX_A :: SUB1CFG_INDEX_MAX) } } impl R { # [doc = "Bit 0 - This bit is used to enable subscriber 1 event."]
# [inline (always)]
pub fn sub1cfg_enable (& self) -> SUB1CFG_ENABLE_R { SUB1CFG_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 8:9 - These bits configure the output policy for subscriber 1 event."]
# [inline (always)]
pub fn sub1cfg_outpolicy (& self) -> SUB1CFG_OUTPOLICY_R { SUB1CFG_OUTPOLICY_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 16:19 - indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"]
# [inline (always)]
pub fn sub1cfg_index (& self) -> SUB1CFG_INDEX_R { SUB1CFG_INDEX_R :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - This bit is used to enable subscriber 1 event."]
# [inline (always)]
# [must_use]
pub fn sub1cfg_enable (& mut self) -> SUB1CFG_ENABLE_W < SUB1CFG_SPEC , 0 > { SUB1CFG_ENABLE_W :: new (self) } # [doc = "Bits 8:9 - These bits configure the output policy for subscriber 1 event."]
# [inline (always)]
# [must_use]
pub fn sub1cfg_outpolicy (& mut self) -> SUB1CFG_OUTPOLICY_W < SUB1CFG_SPEC , 8 > { SUB1CFG_OUTPOLICY_W :: new (self) } # [doc = "Bits 16:19 - indicates the specific bit in the upper 16 bits that is targeted by the subscriber action"]
# [inline (always)]
# [must_use]
pub fn sub1cfg_index (& mut self) -> SUB1CFG_INDEX_W < SUB1CFG_SPEC , 16 > { SUB1CFG_INDEX_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber 1 configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sub1cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sub1cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SUB1CFG_SPEC ; impl crate :: RegisterSpec for SUB1CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sub1cfg::R`](R) reader structure"]
impl crate :: Readable for SUB1CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`sub1cfg::W`](W) writer structure"]
impl crate :: Writable for SUB1CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SUB1CFG to value 0"]
impl crate :: Resettable for SUB1CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct UART1 { _marker : PhantomData < * const () > } unsafe impl Send for UART1 { } impl UART1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const uart1 :: RegisterBlock = 0x4010_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const uart1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for UART1 { type Target = uart1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for UART1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("UART1") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod uart1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , # [doc = "0x808 - Peripheral Clock Configuration Register"]
pub clkcfg : CLKCFG , _reserved3 : [u8 ; 0x08]
, # [doc = "0x814 - Status Register"]
pub gprcm_stat : GPRCM_STAT , _reserved4 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1008 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved6 : [u8 ; 0x0c]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub int_event0_iidx : INT_EVENT0_IIDX , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub int_event0_imask : INT_EVENT0_IMASK , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub int_event0_ris : INT_EVENT0_RIS , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub int_event0_mis : INT_EVENT0_MIS , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub int_event0_iset : INT_EVENT0_ISET , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub int_event0_iclr : INT_EVENT0_ICLR , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1050 - Interrupt index"]
pub int_event1_iidx : INT_EVENT1_IIDX , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1058 - Interrupt mask"]
pub int_event1_imask : INT_EVENT1_IMASK , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1060 - Raw interrupt status"]
pub int_event1_ris : INT_EVENT1_RIS , _reserved16 : [u8 ; 0x04]
, # [doc = "0x1068 - Masked interrupt status"]
pub int_event1_mis : INT_EVENT1_MIS , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1070 - Interrupt set"]
pub int_event1_iset : INT_EVENT1_ISET , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1078 - Interrupt clear"]
pub int_event1_iclr : INT_EVENT1_ICLR , _reserved19 : [u8 ; 0x04]
, # [doc = "0x1080 - Interrupt index"]
pub int_event2_iidx : INT_EVENT2_IIDX , _reserved20 : [u8 ; 0x04]
, # [doc = "0x1088 - Interrupt mask"]
pub int_event2_imask : INT_EVENT2_IMASK , _reserved21 : [u8 ; 0x04]
, # [doc = "0x1090 - Raw interrupt status"]
pub int_event2_ris : INT_EVENT2_RIS , _reserved22 : [u8 ; 0x04]
, # [doc = "0x1098 - Masked interrupt status"]
pub int_event2_mis : INT_EVENT2_MIS , _reserved23 : [u8 ; 0x04]
, # [doc = "0x10a0 - Interrupt set"]
pub int_event2_iset : INT_EVENT2_ISET , _reserved24 : [u8 ; 0x04]
, # [doc = "0x10a8 - Interrupt clear"]
pub int_event2_iclr : INT_EVENT2_ICLR , _reserved25 : [u8 ; 0x34]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved26 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - UART Control Register 0"]
pub ctl0 : CTL0 , # [doc = "0x1104 - UART Line Control Register"]
pub lcrh : LCRH , # [doc = "0x1108 - UART Status Register"]
pub stat : STAT , # [doc = "0x110c - UART Interrupt FIFO Level Select Register"]
pub ifls : IFLS , # [doc = "0x1110 - UART Integer Baud-Rate Divisor Register"]
pub ibrd : IBRD , # [doc = "0x1114 - UART Fractional Baud-Rate Divisor Register"]
pub fbrd : FBRD , # [doc = "0x1118 - Glitch Filter Control"]
pub gfctl : GFCTL , _reserved34 : [u8 ; 0x04]
, # [doc = "0x1120 - UART Transmit Data Register"]
pub txdata : TXDATA , # [doc = "0x1124 - UART Receive Data Register"]
pub rxdata : RXDATA , _reserved36 : [u8 ; 0x20]
, # [doc = "0x1148 - Self Address Mask Register"]
pub amask : AMASK , # [doc = "0x114c - Self Address Register"]
pub addr : ADDR , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKCFG (rw) register accessor: Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkcfg`]
module"]
pub type CLKCFG = crate :: Reg < clkcfg :: CLKCFG_SPEC > ; # [doc = "Peripheral Clock Configuration Register"]
pub mod clkcfg { # [doc = "Register `CLKCFG` reader"]
pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"]
pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"]
CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"]
CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"]
pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"]
# [inline (always)]
pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
# [must_use]
pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"]
# [inline (always)]
# [must_use]
pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"]
impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"]
impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"]
impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GPRCM_STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gprcm_stat`]
module"]
pub type GPRCM_STAT = crate :: Reg < gprcm_stat :: GPRCM_STAT_SPEC > ; # [doc = "Status Register"]
pub mod gprcm_stat { # [doc = "Register `GPRCM_STAT` reader"]
pub type R = crate :: R < GPRCM_STAT_SPEC > ; # [doc = "Field `GPRCM_STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type GPRCM_STAT_RESETSTKY_R = crate :: BitReader < GPRCM_STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GPRCM_STAT_RESETSTKY_A { # [doc = "0: NORES"]
GPRCM_STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
GPRCM_STAT_RESETSTKY_RESET = 1 , } impl From < GPRCM_STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : GPRCM_STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl GPRCM_STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GPRCM_STAT_RESETSTKY_A { match self . bits { false => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES , true => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_nores (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_reset (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn gprcm_stat_resetstky (& self) -> GPRCM_STAT_RESETSTKY_R { GPRCM_STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GPRCM_STAT_SPEC ; impl crate :: RegisterSpec for GPRCM_STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gprcm_stat::R`](R) reader structure"]
impl crate :: Readable for GPRCM_STAT_SPEC { } # [doc = "`reset()` method sets GPRCM_STAT to value 0"]
impl crate :: Resettable for GPRCM_STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUS CLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUS CLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUS CLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUS CLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iidx`]
module"]
pub type INT_EVENT0_IIDX = crate :: Reg < int_event0_iidx :: INT_EVENT0_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event0_iidx { # [doc = "Register `INT_EVENT0_IIDX` reader"]
pub type R = crate :: R < INT_EVENT0_IIDX_SPEC > ; # [doc = "Field `INT_EVENT0_IIDX_STAT` reader - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
pub type INT_EVENT0_IIDX_STAT_R = crate :: FieldReader < INT_EVENT0_IIDX_STAT_A > ; # [doc = "UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: RTFG"]
INT_EVENT0_IIDX_STAT_RTFG = 1 , # [doc = "2: FEFG"]
INT_EVENT0_IIDX_STAT_FEFG = 2 , # [doc = "3: PEFG"]
INT_EVENT0_IIDX_STAT_PEFG = 3 , # [doc = "4: BEFG"]
INT_EVENT0_IIDX_STAT_BEFG = 4 , # [doc = "5: OEFG"]
INT_EVENT0_IIDX_STAT_OEFG = 5 , # [doc = "6: RXNE"]
INT_EVENT0_IIDX_STAT_RXNE = 6 , # [doc = "7: RXPE"]
INT_EVENT0_IIDX_STAT_RXPE = 7 , # [doc = "8: LINC0"]
INT_EVENT0_IIDX_STAT_LINC0 = 8 , # [doc = "9: LINC1"]
INT_EVENT0_IIDX_STAT_LINC1 = 9 , # [doc = "10: LINOVF"]
INT_EVENT0_IIDX_STAT_LINOVF = 10 , # [doc = "11: RXIFG"]
INT_EVENT0_IIDX_STAT_RXIFG = 11 , # [doc = "12: TXIFG"]
INT_EVENT0_IIDX_STAT_TXIFG = 12 , # [doc = "13: EOT"]
INT_EVENT0_IIDX_STAT_EOT = 13 , # [doc = "14: MODE_9B"]
INT_EVENT0_IIDX_STAT_MODE_9B = 14 , # [doc = "15: CTS"]
INT_EVENT0_IIDX_STAT_CTS = 15 , # [doc = "16: DMA_DONE_RX"]
INT_EVENT0_IIDX_STAT_DMA_DONE_RX = 16 , # [doc = "17: DMA_DONE_TX"]
INT_EVENT0_IIDX_STAT_DMA_DONE_TX = 17 , # [doc = "18: NERR_EVT"]
INT_EVENT0_IIDX_STAT_NERR_EVT = 18 , } impl From < INT_EVENT0_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT0_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RTFG) , 2 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_FEFG) , 3 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_PEFG) , 4 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_BEFG) , 5 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_OEFG) , 6 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXNE) , 7 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXPE) , 8 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC0) , 9 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC1) , 10 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINOVF) , 11 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXIFG) , 12 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TXIFG) , 13 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_EOT) , 14 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MODE_9B) , 15 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_CTS) , 16 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_RX) , 17 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_TX) , 18 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NERR_EVT) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR } # [doc = "RTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rtfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RTFG } # [doc = "FEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_fefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_FEFG } # [doc = "PEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_pefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_PEFG } # [doc = "BEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_befg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_BEFG } # [doc = "OEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_oefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_OEFG } # [doc = "RXNE"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxne (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXNE } # [doc = "RXPE"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxpe (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXPE } # [doc = "LINC0"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_linc0 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC0 } # [doc = "LINC1"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_linc1 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINC1 } # [doc = "LINOVF"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_linovf (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LINOVF } # [doc = "RXIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_rxifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_RXIFG } # [doc = "TXIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_txifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TXIFG } # [doc = "EOT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_eot (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_EOT } # [doc = "MODE_9B"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mode_9b (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MODE_9B } # [doc = "CTS"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_cts (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_CTS } # [doc = "DMA_DONE_RX"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dma_done_rx (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_RX } # [doc = "DMA_DONE_TX"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dma_done_tx (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMA_DONE_TX } # [doc = "NERR_EVT"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_nerr_evt (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NERR_EVT } } impl R { # [doc = "Bits 0:7 - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event0_iidx_stat (& self) -> INT_EVENT0_IIDX_STAT_R { INT_EVENT0_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_imask`]
module"]
pub type INT_EVENT0_IMASK = crate :: Reg < int_event0_imask :: INT_EVENT0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event0_imask { # [doc = "Register `INT_EVENT0_IMASK` reader"]
pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"]
pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT0_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT0_IMASK_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RTOUT_A { match self . bits { false => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR , true => INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rtout_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rtout_set (& self) -> bool { * self == INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RTOUT_A :: INT_EVENT0_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` reader - Enable UART Framing Error Interrupt."]
pub type INT_EVENT0_IMASK_FRMERR_R = crate :: BitReader < INT_EVENT0_IMASK_FRMERR_A > ; # [doc = "Enable UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_FRMERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_FRMERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_FRMERR_SET = 1 , } impl From < INT_EVENT0_IMASK_FRMERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_FRMERR_A { match self . bits { false => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR , true => INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_frmerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_frmerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_FRMERR` writer - Enable UART Framing Error Interrupt."]
pub type INT_EVENT0_IMASK_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_FRMERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_FRMERR_A :: INT_EVENT0_IMASK_FRMERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` reader - Enable UART Parity Error Interrupt."]
pub type INT_EVENT0_IMASK_PARERR_R = crate :: BitReader < INT_EVENT0_IMASK_PARERR_A > ; # [doc = "Enable UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_PARERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_PARERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_PARERR_SET = 1 , } impl From < INT_EVENT0_IMASK_PARERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_PARERR_A { match self . bits { false => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR , true => INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_parerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_parerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_PARERR` writer - Enable UART Parity Error Interrupt."]
pub type INT_EVENT0_IMASK_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_PARERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_PARERR_A :: INT_EVENT0_IMASK_PARERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` reader - Enable UART Break Error Interrupt."]
pub type INT_EVENT0_IMASK_BRKERR_R = crate :: BitReader < INT_EVENT0_IMASK_BRKERR_A > ; # [doc = "Enable UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_BRKERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_BRKERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_BRKERR_SET = 1 , } impl From < INT_EVENT0_IMASK_BRKERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_BRKERR_A { match self . bits { false => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR , true => INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_brkerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_brkerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_BRKERR` writer - Enable UART Break Error Interrupt."]
pub type INT_EVENT0_IMASK_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_BRKERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_BRKERR_A :: INT_EVENT0_IMASK_BRKERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` reader - Enable UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_IMASK_OVRERR_R = crate :: BitReader < INT_EVENT0_IMASK_OVRERR_A > ; # [doc = "Enable UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_OVRERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_OVRERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_OVRERR_SET = 1 , } impl From < INT_EVENT0_IMASK_OVRERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_OVRERR_A { match self . bits { false => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR , true => INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_ovrerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVRERR` writer - Enable UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_IMASK_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVRERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVRERR_A :: INT_EVENT0_IMASK_OVRERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` reader - Enable Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXNE_R = crate :: BitReader < INT_EVENT0_IMASK_RXNE_A > ; # [doc = "Enable Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXNE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXNE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXNE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXNE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXNE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXNE_A { match self . bits { false => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR , true => INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxne_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxne_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXNE` writer - Enable Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXNE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXNE_A :: INT_EVENT0_IMASK_RXNE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` reader - Enable Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXPE_R = crate :: BitReader < INT_EVENT0_IMASK_RXPE_A > ; # [doc = "Enable Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXPE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXPE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXPE_SET = 1 , } impl From < INT_EVENT0_IMASK_RXPE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXPE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXPE_A { match self . bits { false => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR , true => INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxpe_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxpe_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXPE` writer - Enable Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_IMASK_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXPE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXPE_A :: INT_EVENT0_IMASK_RXPE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` reader - Enable UART Receive Interrupt."]
pub type INT_EVENT0_IMASK_RXINT_R = crate :: BitReader < INT_EVENT0_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_RXINT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_RXINT_A { match self . bits { false => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR , true => INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_rxint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_rxint_set (& self) -> bool { * self == INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_RXINT` writer - Enable UART Receive Interrupt."]
pub type INT_EVENT0_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_RXINT_A :: INT_EVENT0_IMASK_RXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` reader - Enable UART Transmit Interrupt."]
pub type INT_EVENT0_IMASK_TXINT_R = crate :: BitReader < INT_EVENT0_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TXINT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT0_IMASK_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TXINT_A { match self . bits { false => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR , true => INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_txint_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_txint_set (& self) -> bool { * self == INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT0_IMASK_TXINT` writer - Enable UART Transmit Interrupt."]
pub type INT_EVENT0_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TXINT_A :: INT_EVENT0_IMASK_TXINT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_EOT` reader - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_IMASK_EOT_R = crate :: BitReader < INT_EVENT0_IMASK_EOT_A > ; # [doc = "Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_EOT_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_EOT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_EOT_SET = 1 , } impl From < INT_EVENT0_IMASK_EOT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_EOT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_EOT_A { match self . bits { false => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR , true => INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_eot_clr (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_eot_set (& self) -> bool { * self == INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET } } # [doc = "Field `INT_EVENT0_IMASK_EOT` writer - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_IMASK_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_EOT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_EOT_A :: INT_EVENT0_IMASK_EOT_SET) } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` reader - Enable Address Match Interrupt."]
pub type INT_EVENT0_IMASK_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_IMASK_ADDR_MATCH_A > ; # [doc = "Enable Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_ADDR_MATCH_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_IMASK_ADDR_MATCH_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_ADDR_MATCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR , true => INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_addr_match_clr (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_addr_match_set (& self) -> bool { * self == INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_IMASK_ADDR_MATCH` writer - Enable Address Match Interrupt."]
pub type INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_ADDR_MATCH_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_ADDR_MATCH_A :: INT_EVENT0_IMASK_ADDR_MATCH_SET) } } # [doc = "Field `INT_EVENT0_IMASK_CTS` reader - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_IMASK_CTS_R = crate :: BitReader < INT_EVENT0_IMASK_CTS_A > ; # [doc = "Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_CTS_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_CTS_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_CTS_SET = 1 , } impl From < INT_EVENT0_IMASK_CTS_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_CTS_A { match self . bits { false => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR , true => INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_cts_clr (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_cts_set (& self) -> bool { * self == INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET } } # [doc = "Field `INT_EVENT0_IMASK_CTS` writer - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_IMASK_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_CTS_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_CTS_A :: INT_EVENT0_IMASK_CTS_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` reader - Enable DMA Done on RX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_RX_A > ; # [doc = "Enable DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_RX` writer - Enable DMA Done on RX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_RX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_RX_A :: INT_EVENT0_IMASK_DMA_DONE_RX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` reader - Enable DMA Done on TX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_IMASK_DMA_DONE_TX_A > ; # [doc = "Enable DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_IMASK_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR , true => INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMA_DONE_TX` writer - Enable DMA Done on TX Event Channel"]
pub type INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMA_DONE_TX_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMA_DONE_TX_A :: INT_EVENT0_IMASK_DMA_DONE_TX_SET) } } # [doc = "Field `INT_EVENT0_IMASK_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_IMASK_NERR_R = crate :: BitReader < INT_EVENT0_IMASK_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_NERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_NERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_NERR_SET = 1 , } impl From < INT_EVENT0_IMASK_NERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_NERR_A { match self . bits { false => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR , true => INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_nerr_clr (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_nerr_set (& self) -> bool { * self == INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_IMASK_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_NERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_NERR_A :: INT_EVENT0_IMASK_NERR_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rtout (& self) -> INT_EVENT0_IMASK_RTOUT_R { INT_EVENT0_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_frmerr (& self) -> INT_EVENT0_IMASK_FRMERR_R { INT_EVENT0_IMASK_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_parerr (& self) -> INT_EVENT0_IMASK_PARERR_R { INT_EVENT0_IMASK_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_brkerr (& self) -> INT_EVENT0_IMASK_BRKERR_R { INT_EVENT0_IMASK_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."]
# [inline (always)]
pub fn int_event0_imask_ovrerr (& self) -> INT_EVENT0_IMASK_OVRERR_R { INT_EVENT0_IMASK_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rxne (& self) -> INT_EVENT0_IMASK_RXNE_R { INT_EVENT0_IMASK_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rxpe (& self) -> INT_EVENT0_IMASK_RXPE_R { INT_EVENT0_IMASK_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
pub fn int_event0_imask_rxint (& self) -> INT_EVENT0_IMASK_RXINT_R { INT_EVENT0_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event0_imask_txint (& self) -> INT_EVENT0_IMASK_TXINT_R { INT_EVENT0_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
pub fn int_event0_imask_eot (& self) -> INT_EVENT0_IMASK_EOT_R { INT_EVENT0_IMASK_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable Address Match Interrupt."]
# [inline (always)]
pub fn int_event0_imask_addr_match (& self) -> INT_EVENT0_IMASK_ADDR_MATCH_R { INT_EVENT0_IMASK_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
pub fn int_event0_imask_cts (& self) -> INT_EVENT0_IMASK_CTS_R { INT_EVENT0_IMASK_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"]
# [inline (always)]
pub fn int_event0_imask_dma_done_rx (& self) -> INT_EVENT0_IMASK_DMA_DONE_RX_R { INT_EVENT0_IMASK_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"]
# [inline (always)]
pub fn int_event0_imask_dma_done_tx (& self) -> INT_EVENT0_IMASK_DMA_DONE_TX_R { INT_EVENT0_IMASK_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
pub fn int_event0_imask_nerr (& self) -> INT_EVENT0_IMASK_NERR_R { INT_EVENT0_IMASK_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rtout (& mut self) -> INT_EVENT0_IMASK_RTOUT_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 1 - Enable UART Framing Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_frmerr (& mut self) -> INT_EVENT0_IMASK_FRMERR_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_FRMERR_W :: new (self) } # [doc = "Bit 2 - Enable UART Parity Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_parerr (& mut self) -> INT_EVENT0_IMASK_PARERR_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_PARERR_W :: new (self) } # [doc = "Bit 3 - Enable UART Break Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_brkerr (& mut self) -> INT_EVENT0_IMASK_BRKERR_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_BRKERR_W :: new (self) } # [doc = "Bit 4 - Enable UART Receive Overrun Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_ovrerr (& mut self) -> INT_EVENT0_IMASK_OVRERR_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_OVRERR_W :: new (self) } # [doc = "Bit 5 - Enable Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxne (& mut self) -> INT_EVENT0_IMASK_RXNE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_RXNE_W :: new (self) } # [doc = "Bit 6 - Enable Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxpe (& mut self) -> INT_EVENT0_IMASK_RXPE_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_RXPE_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_rxint (& mut self) -> INT_EVENT0_IMASK_RXINT_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_RXINT_W :: new (self) } # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_txint (& mut self) -> INT_EVENT0_IMASK_TXINT_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_TXINT_W :: new (self) } # [doc = "Bit 12 - Enable UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_eot (& mut self) -> INT_EVENT0_IMASK_EOT_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_EOT_W :: new (self) } # [doc = "Bit 13 - Enable Address Match Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_addr_match (& mut self) -> INT_EVENT0_IMASK_ADDR_MATCH_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Enable UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_cts (& mut self) -> INT_EVENT0_IMASK_CTS_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_CTS_W :: new (self) } # [doc = "Bit 15 - Enable DMA Done on RX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dma_done_rx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_RX_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Enable DMA Done on TX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dma_done_tx (& mut self) -> INT_EVENT0_IMASK_DMA_DONE_TX_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_nerr (& mut self) -> INT_EVENT0_IMASK_NERR_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_ris`]
module"]
pub type INT_EVENT0_RIS = crate :: Reg < int_event0_ris :: INT_EVENT0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event0_ris { # [doc = "Register `INT_EVENT0_RIS` reader"]
pub type R = crate :: R < INT_EVENT0_RIS_SPEC > ; # [doc = "Field `INT_EVENT0_RIS_RTOUT` reader - UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_RIS_RTOUT_R = crate :: BitReader < INT_EVENT0_RIS_RTOUT_A > ; # [doc = "UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RTOUT_SET = 1 , } impl From < INT_EVENT0_RIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RTOUT_A { match self . bits { false => INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_CLR , true => INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rtout_clr (& self) -> bool { * self == INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rtout_set (& self) -> bool { * self == INT_EVENT0_RIS_RTOUT_A :: INT_EVENT0_RIS_RTOUT_SET } } # [doc = "Field `INT_EVENT0_RIS_FRMERR` reader - UART Framing Error Interrupt."]
pub type INT_EVENT0_RIS_FRMERR_R = crate :: BitReader < INT_EVENT0_RIS_FRMERR_A > ; # [doc = "UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_FRMERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_FRMERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_FRMERR_SET = 1 , } impl From < INT_EVENT0_RIS_FRMERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_FRMERR_A { match self . bits { false => INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_CLR , true => INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_frmerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_frmerr_set (& self) -> bool { * self == INT_EVENT0_RIS_FRMERR_A :: INT_EVENT0_RIS_FRMERR_SET } } # [doc = "Field `INT_EVENT0_RIS_PARERR` reader - UART Parity Error Interrupt."]
pub type INT_EVENT0_RIS_PARERR_R = crate :: BitReader < INT_EVENT0_RIS_PARERR_A > ; # [doc = "UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_PARERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_PARERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_PARERR_SET = 1 , } impl From < INT_EVENT0_RIS_PARERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_PARERR_A { match self . bits { false => INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_CLR , true => INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_parerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_parerr_set (& self) -> bool { * self == INT_EVENT0_RIS_PARERR_A :: INT_EVENT0_RIS_PARERR_SET } } # [doc = "Field `INT_EVENT0_RIS_BRKERR` reader - UART Break Error Interrupt."]
pub type INT_EVENT0_RIS_BRKERR_R = crate :: BitReader < INT_EVENT0_RIS_BRKERR_A > ; # [doc = "UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_BRKERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_BRKERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_BRKERR_SET = 1 , } impl From < INT_EVENT0_RIS_BRKERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_BRKERR_A { match self . bits { false => INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_CLR , true => INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_brkerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_brkerr_set (& self) -> bool { * self == INT_EVENT0_RIS_BRKERR_A :: INT_EVENT0_RIS_BRKERR_SET } } # [doc = "Field `INT_EVENT0_RIS_OVRERR` reader - UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_RIS_OVRERR_R = crate :: BitReader < INT_EVENT0_RIS_OVRERR_A > ; # [doc = "UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_OVRERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_OVRERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_OVRERR_SET = 1 , } impl From < INT_EVENT0_RIS_OVRERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_OVRERR_A { match self . bits { false => INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_CLR , true => INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_ovrerr_set (& self) -> bool { * self == INT_EVENT0_RIS_OVRERR_A :: INT_EVENT0_RIS_OVRERR_SET } } # [doc = "Field `INT_EVENT0_RIS_RXNE` reader - Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_RIS_RXNE_R = crate :: BitReader < INT_EVENT0_RIS_RXNE_A > ; # [doc = "Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXNE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXNE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXNE_SET = 1 , } impl From < INT_EVENT0_RIS_RXNE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXNE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXNE_A { match self . bits { false => INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_CLR , true => INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxne_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxne_set (& self) -> bool { * self == INT_EVENT0_RIS_RXNE_A :: INT_EVENT0_RIS_RXNE_SET } } # [doc = "Field `INT_EVENT0_RIS_RXPE` reader - Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_RIS_RXPE_R = crate :: BitReader < INT_EVENT0_RIS_RXPE_A > ; # [doc = "Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXPE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXPE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXPE_SET = 1 , } impl From < INT_EVENT0_RIS_RXPE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXPE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXPE_A { match self . bits { false => INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_CLR , true => INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxpe_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxpe_set (& self) -> bool { * self == INT_EVENT0_RIS_RXPE_A :: INT_EVENT0_RIS_RXPE_SET } } # [doc = "Field `INT_EVENT0_RIS_RXINT` reader - UART Receive Interrupt."]
pub type INT_EVENT0_RIS_RXINT_R = crate :: BitReader < INT_EVENT0_RIS_RXINT_A > ; # [doc = "UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_RXINT_SET = 1 , } impl From < INT_EVENT0_RIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_RXINT_A { match self . bits { false => INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_CLR , true => INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_rxint_clr (& self) -> bool { * self == INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_rxint_set (& self) -> bool { * self == INT_EVENT0_RIS_RXINT_A :: INT_EVENT0_RIS_RXINT_SET } } # [doc = "Field `INT_EVENT0_RIS_TXINT` reader - UART Transmit Interrupt."]
pub type INT_EVENT0_RIS_TXINT_R = crate :: BitReader < INT_EVENT0_RIS_TXINT_A > ; # [doc = "UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TXINT_SET = 1 , } impl From < INT_EVENT0_RIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TXINT_A { match self . bits { false => INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_CLR , true => INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_txint_clr (& self) -> bool { * self == INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_txint_set (& self) -> bool { * self == INT_EVENT0_RIS_TXINT_A :: INT_EVENT0_RIS_TXINT_SET } } # [doc = "Field `INT_EVENT0_RIS_EOT` reader - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_RIS_EOT_R = crate :: BitReader < INT_EVENT0_RIS_EOT_A > ; # [doc = "UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_EOT_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_EOT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_EOT_SET = 1 , } impl From < INT_EVENT0_RIS_EOT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_EOT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_EOT_A { match self . bits { false => INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_CLR , true => INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_eot_clr (& self) -> bool { * self == INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_eot_set (& self) -> bool { * self == INT_EVENT0_RIS_EOT_A :: INT_EVENT0_RIS_EOT_SET } } # [doc = "Field `INT_EVENT0_RIS_ADDR_MATCH` reader - Address Match Interrupt."]
pub type INT_EVENT0_RIS_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_RIS_ADDR_MATCH_A > ; # [doc = "Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_ADDR_MATCH_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_RIS_ADDR_MATCH_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_ADDR_MATCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_CLR , true => INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_addr_match_clr (& self) -> bool { * self == INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_addr_match_set (& self) -> bool { * self == INT_EVENT0_RIS_ADDR_MATCH_A :: INT_EVENT0_RIS_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_RIS_CTS` reader - UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_RIS_CTS_R = crate :: BitReader < INT_EVENT0_RIS_CTS_A > ; # [doc = "UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_CTS_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_CTS_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_CTS_SET = 1 , } impl From < INT_EVENT0_RIS_CTS_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_CTS_A { match self . bits { false => INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_CLR , true => INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_cts_clr (& self) -> bool { * self == INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_cts_set (& self) -> bool { * self == INT_EVENT0_RIS_CTS_A :: INT_EVENT0_RIS_CTS_SET } } # [doc = "Field `INT_EVENT0_RIS_DMA_DONE_RX` reader - DMA Done on RX Event Channel"]
pub type INT_EVENT0_RIS_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_RIS_DMA_DONE_RX_A > ; # [doc = "DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_RIS_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_CLR , true => INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_RX_A :: INT_EVENT0_RIS_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_RIS_DMA_DONE_TX` reader - DMA Done on TX Event Channel"]
pub type INT_EVENT0_RIS_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_RIS_DMA_DONE_TX_A > ; # [doc = "DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_RIS_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_CLR , true => INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_RIS_DMA_DONE_TX_A :: INT_EVENT0_RIS_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_RIS_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_RIS_NERR_R = crate :: BitReader < INT_EVENT0_RIS_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_NERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_NERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_NERR_SET = 1 , } impl From < INT_EVENT0_RIS_NERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_NERR_A { match self . bits { false => INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_CLR , true => INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_nerr_clr (& self) -> bool { * self == INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_nerr_set (& self) -> bool { * self == INT_EVENT0_RIS_NERR_A :: INT_EVENT0_RIS_NERR_SET } } impl R { # [doc = "Bit 0 - UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rtout (& self) -> INT_EVENT0_RIS_RTOUT_R { INT_EVENT0_RIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - UART Framing Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_frmerr (& self) -> INT_EVENT0_RIS_FRMERR_R { INT_EVENT0_RIS_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - UART Parity Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_parerr (& self) -> INT_EVENT0_RIS_PARERR_R { INT_EVENT0_RIS_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Break Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_brkerr (& self) -> INT_EVENT0_RIS_BRKERR_R { INT_EVENT0_RIS_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Receive Overrun Error Interrupt."]
# [inline (always)]
pub fn int_event0_ris_ovrerr (& self) -> INT_EVENT0_RIS_OVRERR_R { INT_EVENT0_RIS_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rxne (& self) -> INT_EVENT0_RIS_RXNE_R { INT_EVENT0_RIS_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rxpe (& self) -> INT_EVENT0_RIS_RXPE_R { INT_EVENT0_RIS_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - UART Receive Interrupt."]
# [inline (always)]
pub fn int_event0_ris_rxint (& self) -> INT_EVENT0_RIS_RXINT_R { INT_EVENT0_RIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event0_ris_txint (& self) -> INT_EVENT0_RIS_TXINT_R { INT_EVENT0_RIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
pub fn int_event0_ris_eot (& self) -> INT_EVENT0_RIS_EOT_R { INT_EVENT0_RIS_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Address Match Interrupt."]
# [inline (always)]
pub fn int_event0_ris_addr_match (& self) -> INT_EVENT0_RIS_ADDR_MATCH_R { INT_EVENT0_RIS_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
pub fn int_event0_ris_cts (& self) -> INT_EVENT0_RIS_CTS_R { INT_EVENT0_RIS_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - DMA Done on RX Event Channel"]
# [inline (always)]
pub fn int_event0_ris_dma_done_rx (& self) -> INT_EVENT0_RIS_DMA_DONE_RX_R { INT_EVENT0_RIS_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - DMA Done on TX Event Channel"]
# [inline (always)]
pub fn int_event0_ris_dma_done_tx (& self) -> INT_EVENT0_RIS_DMA_DONE_TX_R { INT_EVENT0_RIS_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
pub fn int_event0_ris_nerr (& self) -> INT_EVENT0_RIS_NERR_R { INT_EVENT0_RIS_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_RIS to value 0"]
impl crate :: Resettable for INT_EVENT0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_mis`]
module"]
pub type INT_EVENT0_MIS = crate :: Reg < int_event0_mis :: INT_EVENT0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event0_mis { # [doc = "Register `INT_EVENT0_MIS` reader"]
pub type R = crate :: R < INT_EVENT0_MIS_SPEC > ; # [doc = "Field `INT_EVENT0_MIS_RTOUT` reader - Masked UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_MIS_RTOUT_R = crate :: BitReader < INT_EVENT0_MIS_RTOUT_A > ; # [doc = "Masked UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RTOUT_SET = 1 , } impl From < INT_EVENT0_MIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RTOUT_A { match self . bits { false => INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_CLR , true => INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rtout_clr (& self) -> bool { * self == INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rtout_set (& self) -> bool { * self == INT_EVENT0_MIS_RTOUT_A :: INT_EVENT0_MIS_RTOUT_SET } } # [doc = "Field `INT_EVENT0_MIS_FRMERR` reader - Masked UART Framing Error Interrupt."]
pub type INT_EVENT0_MIS_FRMERR_R = crate :: BitReader < INT_EVENT0_MIS_FRMERR_A > ; # [doc = "Masked UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_FRMERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_FRMERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_FRMERR_SET = 1 , } impl From < INT_EVENT0_MIS_FRMERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_FRMERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_FRMERR_A { match self . bits { false => INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_CLR , true => INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_frmerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_frmerr_set (& self) -> bool { * self == INT_EVENT0_MIS_FRMERR_A :: INT_EVENT0_MIS_FRMERR_SET } } # [doc = "Field `INT_EVENT0_MIS_PARERR` reader - Masked UART Parity Error Interrupt."]
pub type INT_EVENT0_MIS_PARERR_R = crate :: BitReader < INT_EVENT0_MIS_PARERR_A > ; # [doc = "Masked UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_PARERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_PARERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_PARERR_SET = 1 , } impl From < INT_EVENT0_MIS_PARERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_PARERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_PARERR_A { match self . bits { false => INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_CLR , true => INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_parerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_parerr_set (& self) -> bool { * self == INT_EVENT0_MIS_PARERR_A :: INT_EVENT0_MIS_PARERR_SET } } # [doc = "Field `INT_EVENT0_MIS_BRKERR` reader - Masked UART Break Error Interrupt."]
pub type INT_EVENT0_MIS_BRKERR_R = crate :: BitReader < INT_EVENT0_MIS_BRKERR_A > ; # [doc = "Masked UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_BRKERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_BRKERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_BRKERR_SET = 1 , } impl From < INT_EVENT0_MIS_BRKERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_BRKERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_BRKERR_A { match self . bits { false => INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_CLR , true => INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_brkerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_brkerr_set (& self) -> bool { * self == INT_EVENT0_MIS_BRKERR_A :: INT_EVENT0_MIS_BRKERR_SET } } # [doc = "Field `INT_EVENT0_MIS_OVRERR` reader - Masked UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_MIS_OVRERR_R = crate :: BitReader < INT_EVENT0_MIS_OVRERR_A > ; # [doc = "Masked UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_OVRERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_OVRERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_OVRERR_SET = 1 , } impl From < INT_EVENT0_MIS_OVRERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_OVRERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_OVRERR_A { match self . bits { false => INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_CLR , true => INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_ovrerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_ovrerr_set (& self) -> bool { * self == INT_EVENT0_MIS_OVRERR_A :: INT_EVENT0_MIS_OVRERR_SET } } # [doc = "Field `INT_EVENT0_MIS_RXNE` reader - Masked Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_MIS_RXNE_R = crate :: BitReader < INT_EVENT0_MIS_RXNE_A > ; # [doc = "Masked Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXNE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXNE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXNE_SET = 1 , } impl From < INT_EVENT0_MIS_RXNE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXNE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXNE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXNE_A { match self . bits { false => INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_CLR , true => INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxne_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxne_set (& self) -> bool { * self == INT_EVENT0_MIS_RXNE_A :: INT_EVENT0_MIS_RXNE_SET } } # [doc = "Field `INT_EVENT0_MIS_RXPE` reader - Masked Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_MIS_RXPE_R = crate :: BitReader < INT_EVENT0_MIS_RXPE_A > ; # [doc = "Masked Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXPE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXPE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXPE_SET = 1 , } impl From < INT_EVENT0_MIS_RXPE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXPE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXPE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXPE_A { match self . bits { false => INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_CLR , true => INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxpe_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxpe_set (& self) -> bool { * self == INT_EVENT0_MIS_RXPE_A :: INT_EVENT0_MIS_RXPE_SET } } # [doc = "Field `INT_EVENT0_MIS_RXINT` reader - Masked UART Receive Interrupt."]
pub type INT_EVENT0_MIS_RXINT_R = crate :: BitReader < INT_EVENT0_MIS_RXINT_A > ; # [doc = "Masked UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_RXINT_SET = 1 , } impl From < INT_EVENT0_MIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_RXINT_A { match self . bits { false => INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_CLR , true => INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_rxint_clr (& self) -> bool { * self == INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_rxint_set (& self) -> bool { * self == INT_EVENT0_MIS_RXINT_A :: INT_EVENT0_MIS_RXINT_SET } } # [doc = "Field `INT_EVENT0_MIS_TXINT` reader - Masked UART Transmit Interrupt."]
pub type INT_EVENT0_MIS_TXINT_R = crate :: BitReader < INT_EVENT0_MIS_TXINT_A > ; # [doc = "Masked UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TXINT_SET = 1 , } impl From < INT_EVENT0_MIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TXINT_A { match self . bits { false => INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_CLR , true => INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_txint_clr (& self) -> bool { * self == INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_txint_set (& self) -> bool { * self == INT_EVENT0_MIS_TXINT_A :: INT_EVENT0_MIS_TXINT_SET } } # [doc = "Field `INT_EVENT0_MIS_EOT` reader - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_MIS_EOT_R = crate :: BitReader < INT_EVENT0_MIS_EOT_A > ; # [doc = "UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_EOT_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_EOT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_EOT_SET = 1 , } impl From < INT_EVENT0_MIS_EOT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_EOT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_EOT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_EOT_A { match self . bits { false => INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_CLR , true => INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_eot_clr (& self) -> bool { * self == INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_eot_set (& self) -> bool { * self == INT_EVENT0_MIS_EOT_A :: INT_EVENT0_MIS_EOT_SET } } # [doc = "Field `INT_EVENT0_MIS_ADDR_MATCH` reader - Masked Address Match Interrupt."]
pub type INT_EVENT0_MIS_ADDR_MATCH_R = crate :: BitReader < INT_EVENT0_MIS_ADDR_MATCH_A > ; # [doc = "Masked Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_ADDR_MATCH_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_ADDR_MATCH_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_MIS_ADDR_MATCH_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_ADDR_MATCH_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_ADDR_MATCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_ADDR_MATCH_A { match self . bits { false => INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_CLR , true => INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_addr_match_clr (& self) -> bool { * self == INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_addr_match_set (& self) -> bool { * self == INT_EVENT0_MIS_ADDR_MATCH_A :: INT_EVENT0_MIS_ADDR_MATCH_SET } } # [doc = "Field `INT_EVENT0_MIS_CTS` reader - Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_MIS_CTS_R = crate :: BitReader < INT_EVENT0_MIS_CTS_A > ; # [doc = "Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_CTS_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_CTS_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_CTS_SET = 1 , } impl From < INT_EVENT0_MIS_CTS_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_CTS_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_CTS_A { match self . bits { false => INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_CLR , true => INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_cts_clr (& self) -> bool { * self == INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_cts_set (& self) -> bool { * self == INT_EVENT0_MIS_CTS_A :: INT_EVENT0_MIS_CTS_SET } } # [doc = "Field `INT_EVENT0_MIS_DMA_DONE_RX` reader - Masked DMA Done on RX Event Channel"]
pub type INT_EVENT0_MIS_DMA_DONE_RX_R = crate :: BitReader < INT_EVENT0_MIS_DMA_DONE_RX_A > ; # [doc = "Masked DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DMA_DONE_RX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DMA_DONE_RX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_MIS_DMA_DONE_RX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DMA_DONE_RX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DMA_DONE_RX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DMA_DONE_RX_A { match self . bits { false => INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_CLR , true => INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_rx_clr (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_rx_set (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_RX_A :: INT_EVENT0_MIS_DMA_DONE_RX_SET } } # [doc = "Field `INT_EVENT0_MIS_DMA_DONE_TX` reader - Masked DMA Done on TX Event Channel"]
pub type INT_EVENT0_MIS_DMA_DONE_TX_R = crate :: BitReader < INT_EVENT0_MIS_DMA_DONE_TX_A > ; # [doc = "Masked DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DMA_DONE_TX_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DMA_DONE_TX_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_MIS_DMA_DONE_TX_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DMA_DONE_TX_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DMA_DONE_TX_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DMA_DONE_TX_A { match self . bits { false => INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_CLR , true => INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_tx_clr (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dma_done_tx_set (& self) -> bool { * self == INT_EVENT0_MIS_DMA_DONE_TX_A :: INT_EVENT0_MIS_DMA_DONE_TX_SET } } # [doc = "Field `INT_EVENT0_MIS_NERR` reader - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_MIS_NERR_R = crate :: BitReader < INT_EVENT0_MIS_NERR_A > ; # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_NERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_NERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_NERR_SET = 1 , } impl From < INT_EVENT0_MIS_NERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_NERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_NERR_A { match self . bits { false => INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_CLR , true => INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_nerr_clr (& self) -> bool { * self == INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_nerr_set (& self) -> bool { * self == INT_EVENT0_MIS_NERR_A :: INT_EVENT0_MIS_NERR_SET } } impl R { # [doc = "Bit 0 - Masked UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rtout (& self) -> INT_EVENT0_MIS_RTOUT_R { INT_EVENT0_MIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masked UART Framing Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_frmerr (& self) -> INT_EVENT0_MIS_FRMERR_R { INT_EVENT0_MIS_FRMERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masked UART Parity Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_parerr (& self) -> INT_EVENT0_MIS_PARERR_R { INT_EVENT0_MIS_PARERR_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masked UART Break Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_brkerr (& self) -> INT_EVENT0_MIS_BRKERR_R { INT_EVENT0_MIS_BRKERR_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Masked UART Receive Overrun Error Interrupt."]
# [inline (always)]
pub fn int_event0_mis_ovrerr (& self) -> INT_EVENT0_MIS_OVRERR_R { INT_EVENT0_MIS_OVRERR_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Masked Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rxne (& self) -> INT_EVENT0_MIS_RXNE_R { INT_EVENT0_MIS_RXNE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Masked Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rxpe (& self) -> INT_EVENT0_MIS_RXPE_R { INT_EVENT0_MIS_RXPE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 10 - Masked UART Receive Interrupt."]
# [inline (always)]
pub fn int_event0_mis_rxint (& self) -> INT_EVENT0_MIS_RXINT_R { INT_EVENT0_MIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Masked UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event0_mis_txint (& self) -> INT_EVENT0_MIS_TXINT_R { INT_EVENT0_MIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
pub fn int_event0_mis_eot (& self) -> INT_EVENT0_MIS_EOT_R { INT_EVENT0_MIS_EOT_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Masked Address Match Interrupt."]
# [inline (always)]
pub fn int_event0_mis_addr_match (& self) -> INT_EVENT0_MIS_ADDR_MATCH_R { INT_EVENT0_MIS_ADDR_MATCH_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Masked UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
pub fn int_event0_mis_cts (& self) -> INT_EVENT0_MIS_CTS_R { INT_EVENT0_MIS_CTS_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Masked DMA Done on RX Event Channel"]
# [inline (always)]
pub fn int_event0_mis_dma_done_rx (& self) -> INT_EVENT0_MIS_DMA_DONE_RX_R { INT_EVENT0_MIS_DMA_DONE_RX_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Masked DMA Done on TX Event Channel"]
# [inline (always)]
pub fn int_event0_mis_dma_done_tx (& self) -> INT_EVENT0_MIS_DMA_DONE_TX_R { INT_EVENT0_MIS_DMA_DONE_TX_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
pub fn int_event0_mis_nerr (& self) -> INT_EVENT0_MIS_NERR_R { INT_EVENT0_MIS_NERR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_MIS to value 0"]
impl crate :: Resettable for INT_EVENT0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iset`]
module"]
pub type INT_EVENT0_ISET = crate :: Reg < int_event0_iset :: INT_EVENT0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event0_iset { # [doc = "Register `INT_EVENT0_ISET` writer"]
pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT0_ISET_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RTOUT_AW :: INT_EVENT0_ISET_RTOUT_SET) } } # [doc = "Set UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_FRMERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_FRMERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_FRMERR_SET = 1 , } impl From < INT_EVENT0_ISET_FRMERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_FRMERR` writer - Set UART Framing Error Interrupt."]
pub type INT_EVENT0_ISET_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_frmerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_FRMERR_AW :: INT_EVENT0_ISET_FRMERR_SET) } } # [doc = "Set UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_PARERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_PARERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_PARERR_SET = 1 , } impl From < INT_EVENT0_ISET_PARERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_PARERR` writer - Set UART Parity Error Interrupt."]
pub type INT_EVENT0_ISET_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_parerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_PARERR_AW :: INT_EVENT0_ISET_PARERR_SET) } } # [doc = "Set UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_BRKERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_BRKERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_BRKERR_SET = 1 , } impl From < INT_EVENT0_ISET_BRKERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_BRKERR` writer - Set UART Break Error Interrupt."]
pub type INT_EVENT0_ISET_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_brkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_BRKERR_AW :: INT_EVENT0_ISET_BRKERR_SET) } } # [doc = "Set UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_OVRERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_OVRERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_OVRERR_SET = 1 , } impl From < INT_EVENT0_ISET_OVRERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVRERR` writer - Set UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_ISET_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_ovrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVRERR_AW :: INT_EVENT0_ISET_OVRERR_SET) } } # [doc = "Set Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXNE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXNE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXNE_SET = 1 , } impl From < INT_EVENT0_ISET_RXNE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXNE` writer - Set Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ISET_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxne_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXNE_AW :: INT_EVENT0_ISET_RXNE_SET) } } # [doc = "Set Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXPE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXPE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXPE_SET = 1 , } impl From < INT_EVENT0_ISET_RXPE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXPE` writer - Set Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ISET_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxpe_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXPE_AW :: INT_EVENT0_ISET_RXPE_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_RXINT_SET = 1 , } impl From < INT_EVENT0_ISET_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_RXINT` writer - Set UART Receive Interrupt."]
pub type INT_EVENT0_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_RXINT_AW :: INT_EVENT0_ISET_RXINT_SET) } } # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TXINT_SET = 1 , } impl From < INT_EVENT0_ISET_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TXINT` writer - Set UART Transmit Interrupt."]
pub type INT_EVENT0_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TXINT_AW :: INT_EVENT0_ISET_TXINT_SET) } } # [doc = "Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_EOT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_EOT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_EOT_SET = 1 , } impl From < INT_EVENT0_ISET_EOT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_EOT` writer - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_ISET_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_eot_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_EOT_AW :: INT_EVENT0_ISET_EOT_SET) } } # [doc = "Set Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_ADDR_MATCH_SET = 1 , } impl From < INT_EVENT0_ISET_ADDR_MATCH_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_ADDR_MATCH` writer - Set Address Match Interrupt."]
pub type INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_addr_match_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_ADDR_MATCH_AW :: INT_EVENT0_ISET_ADDR_MATCH_SET) } } # [doc = "Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_CTS_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_CTS_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_CTS_SET = 1 , } impl From < INT_EVENT0_ISET_CTS_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_CTS` writer - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_ISET_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_cts_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_CTS_AW :: INT_EVENT0_ISET_CTS_SET) } } # [doc = "Set DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DMA_DONE_RX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_RX` writer - Set DMA Done on RX Event Channel"]
pub type INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dma_done_rx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_RX_AW :: INT_EVENT0_ISET_DMA_DONE_RX_SET) } } # [doc = "Set DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DMA_DONE_TX_SET = 1 , } impl From < INT_EVENT0_ISET_DMA_DONE_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMA_DONE_TX` writer - Set DMA Done on TX Event Channel"]
pub type INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dma_done_tx_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMA_DONE_TX_AW :: INT_EVENT0_ISET_DMA_DONE_TX_SET) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_NERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_NERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_NERR_SET = 1 , } impl From < INT_EVENT0_ISET_NERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_ISET_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_nerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_NERR_AW :: INT_EVENT0_ISET_NERR_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rtout (& mut self) -> INT_EVENT0_ISET_RTOUT_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_RTOUT_W :: new (self) } # [doc = "Bit 1 - Set UART Framing Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_frmerr (& mut self) -> INT_EVENT0_ISET_FRMERR_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_FRMERR_W :: new (self) } # [doc = "Bit 2 - Set UART Parity Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_parerr (& mut self) -> INT_EVENT0_ISET_PARERR_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_PARERR_W :: new (self) } # [doc = "Bit 3 - Set UART Break Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_brkerr (& mut self) -> INT_EVENT0_ISET_BRKERR_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_BRKERR_W :: new (self) } # [doc = "Bit 4 - Set UART Receive Overrun Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_ovrerr (& mut self) -> INT_EVENT0_ISET_OVRERR_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_OVRERR_W :: new (self) } # [doc = "Bit 5 - Set Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxne (& mut self) -> INT_EVENT0_ISET_RXNE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_RXNE_W :: new (self) } # [doc = "Bit 6 - Set Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxpe (& mut self) -> INT_EVENT0_ISET_RXPE_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_RXPE_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_rxint (& mut self) -> INT_EVENT0_ISET_RXINT_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_RXINT_W :: new (self) } # [doc = "Bit 11 - Set UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_txint (& mut self) -> INT_EVENT0_ISET_TXINT_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_TXINT_W :: new (self) } # [doc = "Bit 12 - Set UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_eot (& mut self) -> INT_EVENT0_ISET_EOT_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_EOT_W :: new (self) } # [doc = "Bit 13 - Set Address Match Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_addr_match (& mut self) -> INT_EVENT0_ISET_ADDR_MATCH_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Set UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_cts (& mut self) -> INT_EVENT0_ISET_CTS_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_CTS_W :: new (self) } # [doc = "Bit 15 - Set DMA Done on RX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dma_done_rx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_RX_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Set DMA Done on TX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dma_done_tx (& mut self) -> INT_EVENT0_ISET_DMA_DONE_TX_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_nerr (& mut self) -> INT_EVENT0_ISET_NERR_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"]
impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iclr`]
module"]
pub type INT_EVENT0_ICLR = crate :: Reg < int_event0_iclr :: INT_EVENT0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event0_iclr { # [doc = "Register `INT_EVENT0_ICLR` writer"]
pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT0_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RTOUT_AW :: INT_EVENT0_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Framing Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_FRMERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_FRMERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_FRMERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_FRMERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_FRMERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_FRMERR` writer - Clear UART Framing Error Interrupt."]
pub type INT_EVENT0_ICLR_FRMERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_FRMERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_FRMERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_frmerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_frmerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_FRMERR_AW :: INT_EVENT0_ICLR_FRMERR_CLR) } } # [doc = "Clear UART Parity Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_PARERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_PARERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_PARERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_PARERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_PARERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_PARERR` writer - Clear UART Parity Error Interrupt."]
pub type INT_EVENT0_ICLR_PARERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_PARERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_PARERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_parerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_parerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_PARERR_AW :: INT_EVENT0_ICLR_PARERR_CLR) } } # [doc = "Clear UART Break Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_BRKERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_BRKERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_BRKERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_BRKERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_BRKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_BRKERR` writer - Clear UART Break Error Interrupt."]
pub type INT_EVENT0_ICLR_BRKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_BRKERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_BRKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_brkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_brkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_BRKERR_AW :: INT_EVENT0_ICLR_BRKERR_CLR) } } # [doc = "Clear UART Receive Overrun Error Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_OVRERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_OVRERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_OVRERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVRERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_OVRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVRERR` writer - Clear UART Receive Overrun Error Interrupt."]
pub type INT_EVENT0_ICLR_OVRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVRERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_ovrerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_ovrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVRERR_AW :: INT_EVENT0_ICLR_OVRERR_CLR) } } # [doc = "Clear Negative Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXNE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXNE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXNE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXNE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXNE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXNE` writer - Clear Negative Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ICLR_RXNE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXNE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXNE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxne_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxne_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXNE_AW :: INT_EVENT0_ICLR_RXNE_CLR) } } # [doc = "Clear Positive Edge on UARTxRXD Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXPE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXPE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXPE_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXPE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXPE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXPE` writer - Clear Positive Edge on UARTxRXD Interrupt."]
pub type INT_EVENT0_ICLR_RXPE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXPE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXPE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxpe_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxpe_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXPE_AW :: INT_EVENT0_ICLR_RXPE_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_RXINT` writer - Clear UART Receive Interrupt."]
pub type INT_EVENT0_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_RXINT_AW :: INT_EVENT0_ICLR_RXINT_CLR) } } # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT0_ICLR_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TXINT` writer - Clear UART Transmit Interrupt."]
pub type INT_EVENT0_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TXINT_AW :: INT_EVENT0_ICLR_TXINT_CLR) } } # [doc = "Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_EOT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_EOT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_EOT_CLR = 1 , } impl From < INT_EVENT0_ICLR_EOT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_EOT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_EOT` writer - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
pub type INT_EVENT0_ICLR_EOT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_EOT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_EOT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_eot_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_eot_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_EOT_AW :: INT_EVENT0_ICLR_EOT_CLR) } } # [doc = "Clear Address Match Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_ADDR_MATCH_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_ADDR_MATCH_CLR = 1 , } impl From < INT_EVENT0_ICLR_ADDR_MATCH_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_ADDR_MATCH_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_ADDR_MATCH` writer - Clear Address Match Interrupt."]
pub type INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_ADDR_MATCH_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_ADDR_MATCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_addr_match_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_addr_match_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_ADDR_MATCH_AW :: INT_EVENT0_ICLR_ADDR_MATCH_CLR) } } # [doc = "Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_CTS_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_CTS_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_CTS_CLR = 1 , } impl From < INT_EVENT0_ICLR_CTS_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_CTS_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_CTS` writer - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
pub type INT_EVENT0_ICLR_CTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_CTS_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_CTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_cts_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_cts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_CTS_AW :: INT_EVENT0_ICLR_CTS_CLR) } } # [doc = "Clear DMA Done on RX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DMA_DONE_RX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DMA_DONE_RX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_RX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DMA_DONE_RX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_RX` writer - Clear DMA Done on RX Event Channel"]
pub type INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_RX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_RX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_rx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_rx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_RX_AW :: INT_EVENT0_ICLR_DMA_DONE_RX_CLR) } } # [doc = "Clear DMA Done on TX Event Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DMA_DONE_TX_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DMA_DONE_TX_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMA_DONE_TX_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DMA_DONE_TX_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMA_DONE_TX` writer - Clear DMA Done on TX Event Channel"]
pub type INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMA_DONE_TX_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMA_DONE_TX_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_tx_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dma_done_tx_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMA_DONE_TX_AW :: INT_EVENT0_ICLR_DMA_DONE_TX_CLR) } } # [doc = "Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_NERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_NERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_NERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_NERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_NERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_NERR` writer - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
pub type INT_EVENT0_ICLR_NERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_NERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_NERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_nerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_nerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_NERR_AW :: INT_EVENT0_ICLR_NERR_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rtout (& mut self) -> INT_EVENT0_ICLR_RTOUT_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 1 - Clear UART Framing Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_frmerr (& mut self) -> INT_EVENT0_ICLR_FRMERR_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_FRMERR_W :: new (self) } # [doc = "Bit 2 - Clear UART Parity Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_parerr (& mut self) -> INT_EVENT0_ICLR_PARERR_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_PARERR_W :: new (self) } # [doc = "Bit 3 - Clear UART Break Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_brkerr (& mut self) -> INT_EVENT0_ICLR_BRKERR_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_BRKERR_W :: new (self) } # [doc = "Bit 4 - Clear UART Receive Overrun Error Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_ovrerr (& mut self) -> INT_EVENT0_ICLR_OVRERR_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_OVRERR_W :: new (self) } # [doc = "Bit 5 - Clear Negative Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxne (& mut self) -> INT_EVENT0_ICLR_RXNE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_RXNE_W :: new (self) } # [doc = "Bit 6 - Clear Positive Edge on UARTxRXD Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxpe (& mut self) -> INT_EVENT0_ICLR_RXPE_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_RXPE_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_rxint (& mut self) -> INT_EVENT0_ICLR_RXINT_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_RXINT_W :: new (self) } # [doc = "Bit 11 - Clear UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_txint (& mut self) -> INT_EVENT0_ICLR_TXINT_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_TXINT_W :: new (self) } # [doc = "Bit 12 - Clear UART End of Transmission Interrupt Indicates that the last bit of all transmitted data and flags has left the serializer and without any further Data in the TX Fifo or Buffer."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_eot (& mut self) -> INT_EVENT0_ICLR_EOT_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_EOT_W :: new (self) } # [doc = "Bit 13 - Clear Address Match Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_addr_match (& mut self) -> INT_EVENT0_ICLR_ADDR_MATCH_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_ADDR_MATCH_W :: new (self) } # [doc = "Bit 14 - Clear UART Clear to Send Modem Interrupt. 0 = Interrupt disabled"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_cts (& mut self) -> INT_EVENT0_ICLR_CTS_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_CTS_W :: new (self) } # [doc = "Bit 15 - Clear DMA Done on RX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dma_done_rx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_RX_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_DMA_DONE_RX_W :: new (self) } # [doc = "Bit 16 - Clear DMA Done on TX Event Channel"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dma_done_tx (& mut self) -> INT_EVENT0_ICLR_DMA_DONE_TX_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_DMA_DONE_TX_W :: new (self) } # [doc = "Bit 17 - Noise Error on triple voting. Asserted when the 3 samples of majority voting are not equal"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_nerr (& mut self) -> INT_EVENT0_ICLR_NERR_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_NERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iidx`]
module"]
pub type INT_EVENT1_IIDX = crate :: Reg < int_event1_iidx :: INT_EVENT1_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event1_iidx { # [doc = "Register `INT_EVENT1_IIDX` reader"]
pub type R = crate :: R < INT_EVENT1_IIDX_SPEC > ; # [doc = "Field `INT_EVENT1_IIDX_STAT` reader - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
pub type INT_EVENT1_IIDX_STAT_R = crate :: FieldReader < INT_EVENT1_IIDX_STAT_A > ; # [doc = "UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT1_IIDX_STAT_NO_INTR = 0 , # [doc = "1: RTFG"]
INT_EVENT1_IIDX_STAT_RTFG = 1 , # [doc = "11: RXIFG"]
INT_EVENT1_IIDX_STAT_RXIFG = 11 , } impl From < INT_EVENT1_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT1_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RTFG) , 11 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RXIFG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR } # [doc = "RTFG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_rtfg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RTFG } # [doc = "RXIFG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_rxifg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_RXIFG } } impl R { # [doc = "Bits 0:7 - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event1_iidx_stat (& self) -> INT_EVENT1_IIDX_STAT_R { INT_EVENT1_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_imask`]
module"]
pub type INT_EVENT1_IMASK = crate :: Reg < int_event1_imask :: INT_EVENT1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event1_imask { # [doc = "Register `INT_EVENT1_IMASK` reader"]
pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"]
pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_RTOUT` reader - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_IMASK_RTOUT_R = crate :: BitReader < INT_EVENT1_IMASK_RTOUT_A > ; # [doc = "Enable UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_RTOUT_SET = 1 , } impl From < INT_EVENT1_IMASK_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_RTOUT_A { match self . bits { false => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR , true => INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_rtout_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_rtout_set (& self) -> bool { * self == INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RTOUT` writer - Enable UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_IMASK_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RTOUT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RTOUT_A :: INT_EVENT1_IMASK_RTOUT_SET) } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` reader - Enable UART Receive Interrupt."]
pub type INT_EVENT1_IMASK_RXINT_R = crate :: BitReader < INT_EVENT1_IMASK_RXINT_A > ; # [doc = "Enable UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_RXINT_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_RXINT_SET = 1 , } impl From < INT_EVENT1_IMASK_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_RXINT_A { match self . bits { false => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR , true => INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_rxint_clr (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_rxint_set (& self) -> bool { * self == INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET } } # [doc = "Field `INT_EVENT1_IMASK_RXINT` writer - Enable UART Receive Interrupt."]
pub type INT_EVENT1_IMASK_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_RXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_RXINT_A :: INT_EVENT1_IMASK_RXINT_SET) } } impl R { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event1_imask_rtout (& self) -> INT_EVENT1_IMASK_RTOUT_R { INT_EVENT1_IMASK_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
pub fn int_event1_imask_rxint (& self) -> INT_EVENT1_IMASK_RXINT_R { INT_EVENT1_IMASK_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_rtout (& mut self) -> INT_EVENT1_IMASK_RTOUT_W < INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_RTOUT_W :: new (self) } # [doc = "Bit 10 - Enable UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_rxint (& mut self) -> INT_EVENT1_IMASK_RXINT_W < INT_EVENT1_IMASK_SPEC , 10 > { INT_EVENT1_IMASK_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_ris`]
module"]
pub type INT_EVENT1_RIS = crate :: Reg < int_event1_ris :: INT_EVENT1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event1_ris { # [doc = "Register `INT_EVENT1_RIS` reader"]
pub type R = crate :: R < INT_EVENT1_RIS_SPEC > ; # [doc = "Field `INT_EVENT1_RIS_RTOUT` reader - UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_RIS_RTOUT_R = crate :: BitReader < INT_EVENT1_RIS_RTOUT_A > ; # [doc = "UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_RTOUT_SET = 1 , } impl From < INT_EVENT1_RIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_RTOUT_A { match self . bits { false => INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_CLR , true => INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_rtout_clr (& self) -> bool { * self == INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_rtout_set (& self) -> bool { * self == INT_EVENT1_RIS_RTOUT_A :: INT_EVENT1_RIS_RTOUT_SET } } # [doc = "Field `INT_EVENT1_RIS_RXINT` reader - UART Receive Interrupt."]
pub type INT_EVENT1_RIS_RXINT_R = crate :: BitReader < INT_EVENT1_RIS_RXINT_A > ; # [doc = "UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_RXINT_SET = 1 , } impl From < INT_EVENT1_RIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_RXINT_A { match self . bits { false => INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_CLR , true => INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_rxint_clr (& self) -> bool { * self == INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_rxint_set (& self) -> bool { * self == INT_EVENT1_RIS_RXINT_A :: INT_EVENT1_RIS_RXINT_SET } } impl R { # [doc = "Bit 0 - UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event1_ris_rtout (& self) -> INT_EVENT1_RIS_RTOUT_R { INT_EVENT1_RIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - UART Receive Interrupt."]
# [inline (always)]
pub fn int_event1_ris_rxint (& self) -> INT_EVENT1_RIS_RXINT_R { INT_EVENT1_RIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_RIS to value 0"]
impl crate :: Resettable for INT_EVENT1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_mis`]
module"]
pub type INT_EVENT1_MIS = crate :: Reg < int_event1_mis :: INT_EVENT1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event1_mis { # [doc = "Register `INT_EVENT1_MIS` reader"]
pub type R = crate :: R < INT_EVENT1_MIS_SPEC > ; # [doc = "Field `INT_EVENT1_MIS_RTOUT` reader - Masked UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_MIS_RTOUT_R = crate :: BitReader < INT_EVENT1_MIS_RTOUT_A > ; # [doc = "Masked UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_RTOUT_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_RTOUT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_RTOUT_SET = 1 , } impl From < INT_EVENT1_MIS_RTOUT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_RTOUT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_RTOUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_RTOUT_A { match self . bits { false => INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_CLR , true => INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_rtout_clr (& self) -> bool { * self == INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_rtout_set (& self) -> bool { * self == INT_EVENT1_MIS_RTOUT_A :: INT_EVENT1_MIS_RTOUT_SET } } # [doc = "Field `INT_EVENT1_MIS_RXINT` reader - Masked UART Receive Interrupt."]
pub type INT_EVENT1_MIS_RXINT_R = crate :: BitReader < INT_EVENT1_MIS_RXINT_A > ; # [doc = "Masked UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_RXINT_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_RXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_RXINT_SET = 1 , } impl From < INT_EVENT1_MIS_RXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_RXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_RXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_RXINT_A { match self . bits { false => INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_CLR , true => INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_rxint_clr (& self) -> bool { * self == INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_rxint_set (& self) -> bool { * self == INT_EVENT1_MIS_RXINT_A :: INT_EVENT1_MIS_RXINT_SET } } impl R { # [doc = "Bit 0 - Masked UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
pub fn int_event1_mis_rtout (& self) -> INT_EVENT1_MIS_RTOUT_R { INT_EVENT1_MIS_RTOUT_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 10 - Masked UART Receive Interrupt."]
# [inline (always)]
pub fn int_event1_mis_rxint (& self) -> INT_EVENT1_MIS_RXINT_R { INT_EVENT1_MIS_RXINT_R :: new (((self . bits >> 10) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_MIS to value 0"]
impl crate :: Resettable for INT_EVENT1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iset`]
module"]
pub type INT_EVENT1_ISET = crate :: Reg < int_event1_iset :: INT_EVENT1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event1_iset { # [doc = "Register `INT_EVENT1_ISET` writer"]
pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Set UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_RTOUT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_RTOUT_SET = 1 , } impl From < INT_EVENT1_ISET_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RTOUT` writer - Set UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_ISET_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_rtout_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RTOUT_AW :: INT_EVENT1_ISET_RTOUT_SET) } } # [doc = "Set UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_RXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_RXINT_SET = 1 , } impl From < INT_EVENT1_ISET_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_RXINT` writer - Set UART Receive Interrupt."]
pub type INT_EVENT1_ISET_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_rxint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_RXINT_AW :: INT_EVENT1_ISET_RXINT_SET) } } impl W { # [doc = "Bit 0 - Set UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_rtout (& mut self) -> INT_EVENT1_ISET_RTOUT_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_RTOUT_W :: new (self) } # [doc = "Bit 10 - Set UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_rxint (& mut self) -> INT_EVENT1_ISET_RXINT_W < INT_EVENT1_ISET_SPEC , 10 > { INT_EVENT1_ISET_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"]
impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iclr`]
module"]
pub type INT_EVENT1_ICLR = crate :: Reg < int_event1_iclr :: INT_EVENT1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event1_iclr { # [doc = "Register `INT_EVENT1_ICLR` writer"]
pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Clear UARTOUT Receive Time-Out Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_RTOUT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_RTOUT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_RTOUT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RTOUT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_RTOUT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RTOUT` writer - Clear UARTOUT Receive Time-Out Interrupt."]
pub type INT_EVENT1_ICLR_RTOUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RTOUT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RTOUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_rtout_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_rtout_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RTOUT_AW :: INT_EVENT1_ICLR_RTOUT_CLR) } } # [doc = "Clear UART Receive Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_RXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_RXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_RXINT_CLR = 1 , } impl From < INT_EVENT1_ICLR_RXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_RXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_RXINT` writer - Clear UART Receive Interrupt."]
pub type INT_EVENT1_ICLR_RXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_RXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_RXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_rxint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_rxint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_RXINT_AW :: INT_EVENT1_ICLR_RXINT_CLR) } } impl W { # [doc = "Bit 0 - Clear UARTOUT Receive Time-Out Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_rtout (& mut self) -> INT_EVENT1_ICLR_RTOUT_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_RTOUT_W :: new (self) } # [doc = "Bit 10 - Clear UART Receive Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_rxint (& mut self) -> INT_EVENT1_ICLR_RXINT_W < INT_EVENT1_ICLR_SPEC , 10 > { INT_EVENT1_ICLR_RXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iidx`]
module"]
pub type INT_EVENT2_IIDX = crate :: Reg < int_event2_iidx :: INT_EVENT2_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event2_iidx { # [doc = "Register `INT_EVENT2_IIDX` reader"]
pub type R = crate :: R < INT_EVENT2_IIDX_SPEC > ; # [doc = "Field `INT_EVENT2_IIDX_STAT` reader - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
pub type INT_EVENT2_IIDX_STAT_R = crate :: FieldReader < INT_EVENT2_IIDX_STAT_A > ; # [doc = "UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT2_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT2_IIDX_STAT_NO_INTR = 0 , # [doc = "12: TXIFG"]
INT_EVENT2_IIDX_STAT_TXIFG = 12 , } impl From < INT_EVENT2_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT2_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT2_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT2_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT2_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR) , 12 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_TXIFG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR } # [doc = "TXIFG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_txifg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_TXIFG } } impl R { # [doc = "Bits 0:7 - UART Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in UARTRIS and UARTMISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event2_iidx_stat (& self) -> INT_EVENT2_IIDX_STAT_R { INT_EVENT2_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT2_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_imask`]
module"]
pub type INT_EVENT2_IMASK = crate :: Reg < int_event2_imask :: INT_EVENT2_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event2_imask { # [doc = "Register `INT_EVENT2_IMASK` reader"]
pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"]
pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_TXINT` reader - Enable UART Transmit Interrupt."]
pub type INT_EVENT2_IMASK_TXINT_R = crate :: BitReader < INT_EVENT2_IMASK_TXINT_A > ; # [doc = "Enable UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_TXINT_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_TXINT_SET = 1 , } impl From < INT_EVENT2_IMASK_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_TXINT_A { match self . bits { false => INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR , true => INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_txint_clr (& self) -> bool { * self == INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_txint_set (& self) -> bool { * self == INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET } } # [doc = "Field `INT_EVENT2_IMASK_TXINT` writer - Enable UART Transmit Interrupt."]
pub type INT_EVENT2_IMASK_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_TXINT_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_TXINT_A :: INT_EVENT2_IMASK_TXINT_SET) } } impl R { # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event2_imask_txint (& self) -> INT_EVENT2_IMASK_TXINT_R { INT_EVENT2_IMASK_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 11 - Enable UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_txint (& mut self) -> INT_EVENT2_IMASK_TXINT_W < INT_EVENT2_IMASK_SPEC , 11 > { INT_EVENT2_IMASK_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_ris`]
module"]
pub type INT_EVENT2_RIS = crate :: Reg < int_event2_ris :: INT_EVENT2_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event2_ris { # [doc = "Register `INT_EVENT2_RIS` reader"]
pub type R = crate :: R < INT_EVENT2_RIS_SPEC > ; # [doc = "Field `INT_EVENT2_RIS_TXINT` reader - UART Transmit Interrupt."]
pub type INT_EVENT2_RIS_TXINT_R = crate :: BitReader < INT_EVENT2_RIS_TXINT_A > ; # [doc = "UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_TXINT_SET = 1 , } impl From < INT_EVENT2_RIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_TXINT_A { match self . bits { false => INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_CLR , true => INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_txint_clr (& self) -> bool { * self == INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_txint_set (& self) -> bool { * self == INT_EVENT2_RIS_TXINT_A :: INT_EVENT2_RIS_TXINT_SET } } impl R { # [doc = "Bit 11 - UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event2_ris_txint (& self) -> INT_EVENT2_RIS_TXINT_R { INT_EVENT2_RIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_RIS to value 0"]
impl crate :: Resettable for INT_EVENT2_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_mis`]
module"]
pub type INT_EVENT2_MIS = crate :: Reg < int_event2_mis :: INT_EVENT2_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event2_mis { # [doc = "Register `INT_EVENT2_MIS` reader"]
pub type R = crate :: R < INT_EVENT2_MIS_SPEC > ; # [doc = "Field `INT_EVENT2_MIS_TXINT` reader - Masked UART Transmit Interrupt."]
pub type INT_EVENT2_MIS_TXINT_R = crate :: BitReader < INT_EVENT2_MIS_TXINT_A > ; # [doc = "Masked UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_TXINT_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_TXINT_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_TXINT_SET = 1 , } impl From < INT_EVENT2_MIS_TXINT_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_TXINT_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_TXINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_TXINT_A { match self . bits { false => INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_CLR , true => INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_txint_clr (& self) -> bool { * self == INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_txint_set (& self) -> bool { * self == INT_EVENT2_MIS_TXINT_A :: INT_EVENT2_MIS_TXINT_SET } } impl R { # [doc = "Bit 11 - Masked UART Transmit Interrupt."]
# [inline (always)]
pub fn int_event2_mis_txint (& self) -> INT_EVENT2_MIS_TXINT_R { INT_EVENT2_MIS_TXINT_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_MIS to value 0"]
impl crate :: Resettable for INT_EVENT2_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iset`]
module"]
pub type INT_EVENT2_ISET = crate :: Reg < int_event2_iset :: INT_EVENT2_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event2_iset { # [doc = "Register `INT_EVENT2_ISET` writer"]
pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Set UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_TXINT_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_TXINT_SET = 1 , } impl From < INT_EVENT2_ISET_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_TXINT` writer - Set UART Transmit Interrupt."]
pub type INT_EVENT2_ISET_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TXINT_AW :: INT_EVENT2_ISET_TXINT_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_txint_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_TXINT_AW :: INT_EVENT2_ISET_TXINT_SET) } } impl W { # [doc = "Bit 11 - Set UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_txint (& mut self) -> INT_EVENT2_ISET_TXINT_W < INT_EVENT2_ISET_SPEC , 11 > { INT_EVENT2_ISET_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"]
impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iclr`]
module"]
pub type INT_EVENT2_ICLR = crate :: Reg < int_event2_iclr :: INT_EVENT2_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event2_iclr { # [doc = "Register `INT_EVENT2_ICLR` writer"]
pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "Clear UART Transmit Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_TXINT_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_TXINT_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_TXINT_CLR = 1 , } impl From < INT_EVENT2_ICLR_TXINT_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_TXINT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_TXINT` writer - Clear UART Transmit Interrupt."]
pub type INT_EVENT2_ICLR_TXINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_TXINT_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_TXINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_txint_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TXINT_AW :: INT_EVENT2_ICLR_TXINT_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_txint_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_TXINT_AW :: INT_EVENT2_ICLR_TXINT_CLR) } } impl W { # [doc = "Bit 11 - Clear UART Transmit Interrupt."]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_txint (& mut self) -> INT_EVENT2_ICLR_TXINT_W < INT_EVENT2_ICLR_SPEC , 11 > { INT_EVENT2_ICLR_TXINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL0 (rw) register accessor: UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl0`]
module"]
pub type CTL0 = crate :: Reg < ctl0 :: CTL0_SPEC > ; # [doc = "UART Control Register 0"]
pub mod ctl0 { # [doc = "Register `CTL0` reader"]
pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"]
pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"]
CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_LBE` reader - UART Loop Back Enable"]
pub type CTL0_LBE_R = crate :: BitReader < CTL0_LBE_A > ; # [doc = "UART Loop Back Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_LBE_A { # [doc = "0: DISABLE"]
CTL0_LBE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_LBE_ENABLE = 1 , } impl From < CTL0_LBE_A > for bool { # [inline (always)]
fn from (variant : CTL0_LBE_A) -> Self { variant as u8 != 0 } } impl CTL0_LBE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_LBE_A { match self . bits { false => CTL0_LBE_A :: CTL0_LBE_DISABLE , true => CTL0_LBE_A :: CTL0_LBE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_lbe_disable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_lbe_enable (& self) -> bool { * self == CTL0_LBE_A :: CTL0_LBE_ENABLE } } # [doc = "Field `CTL0_LBE` writer - UART Loop Back Enable"]
pub type CTL0_LBE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_LBE_A > ; impl < 'a , REG , const O : u8 > CTL0_LBE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_lbe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_lbe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_LBE_A :: CTL0_LBE_ENABLE) } } # [doc = "Field `CTL0_RXE` reader - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
pub type CTL0_RXE_R = crate :: BitReader < CTL0_RXE_A > ; # [doc = "UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_RXE_A { # [doc = "0: DISABLE"]
CTL0_RXE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_RXE_ENABLE = 1 , } impl From < CTL0_RXE_A > for bool { # [inline (always)]
fn from (variant : CTL0_RXE_A) -> Self { variant as u8 != 0 } } impl CTL0_RXE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_RXE_A { match self . bits { false => CTL0_RXE_A :: CTL0_RXE_DISABLE , true => CTL0_RXE_A :: CTL0_RXE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_rxe_disable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_rxe_enable (& self) -> bool { * self == CTL0_RXE_A :: CTL0_RXE_ENABLE } } # [doc = "Field `CTL0_RXE` writer - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
pub type CTL0_RXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RXE_A > ; impl < 'a , REG , const O : u8 > CTL0_RXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_rxe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_rxe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RXE_A :: CTL0_RXE_ENABLE) } } # [doc = "Field `CTL0_TXE` reader - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
pub type CTL0_TXE_R = crate :: BitReader < CTL0_TXE_A > ; # [doc = "UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_TXE_A { # [doc = "0: DISABLE"]
CTL0_TXE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_TXE_ENABLE = 1 , } impl From < CTL0_TXE_A > for bool { # [inline (always)]
fn from (variant : CTL0_TXE_A) -> Self { variant as u8 != 0 } } impl CTL0_TXE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_TXE_A { match self . bits { false => CTL0_TXE_A :: CTL0_TXE_DISABLE , true => CTL0_TXE_A :: CTL0_TXE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_txe_disable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_txe_enable (& self) -> bool { * self == CTL0_TXE_A :: CTL0_TXE_ENABLE } } # [doc = "Field `CTL0_TXE` writer - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
pub type CTL0_TXE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXE_A > ; impl < 'a , REG , const O : u8 > CTL0_TXE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_txe_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_txe_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXE_A :: CTL0_TXE_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT_EN` reader - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
pub type CTL0_TXD_OUT_EN_R = crate :: BitReader < CTL0_TXD_OUT_EN_A > ; # [doc = "TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_TXD_OUT_EN_A { # [doc = "0: DISABLE"]
CTL0_TXD_OUT_EN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_TXD_OUT_EN_ENABLE = 1 , } impl From < CTL0_TXD_OUT_EN_A > for bool { # [inline (always)]
fn from (variant : CTL0_TXD_OUT_EN_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_TXD_OUT_EN_A { match self . bits { false => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE , true => CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_txd_out_en_disable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_txd_out_en_enable (& self) -> bool { * self == CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE } } # [doc = "Field `CTL0_TXD_OUT_EN` writer - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
pub type CTL0_TXD_OUT_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_EN_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_txd_out_en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_txd_out_en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_EN_A :: CTL0_TXD_OUT_EN_ENABLE) } } # [doc = "Field `CTL0_TXD_OUT` reader - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
pub type CTL0_TXD_OUT_R = crate :: BitReader < CTL0_TXD_OUT_A > ; # [doc = "TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_TXD_OUT_A { # [doc = "0: LOW"]
CTL0_TXD_OUT_LOW = 0 , # [doc = "1: HIGH"]
CTL0_TXD_OUT_HIGH = 1 , } impl From < CTL0_TXD_OUT_A > for bool { # [inline (always)]
fn from (variant : CTL0_TXD_OUT_A) -> Self { variant as u8 != 0 } } impl CTL0_TXD_OUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_TXD_OUT_A { match self . bits { false => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW , true => CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_ctl0_txd_out_low (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_ctl0_txd_out_high (& self) -> bool { * self == CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH } } # [doc = "Field `CTL0_TXD_OUT` writer - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
pub type CTL0_TXD_OUT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_TXD_OUT_A > ; impl < 'a , REG , const O : u8 > CTL0_TXD_OUT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"]
# [inline (always)]
pub fn ctl0_txd_out_low (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_LOW) } # [doc = "HIGH"]
# [inline (always)]
pub fn ctl0_txd_out_high (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_TXD_OUT_A :: CTL0_TXD_OUT_HIGH) } } # [doc = "Field `CTL0_MODE` reader - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
pub type CTL0_MODE_R = crate :: FieldReader < CTL0_MODE_A > ; # [doc = "Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_MODE_A { # [doc = "0: UART"]
CTL0_MODE_UART = 0 , # [doc = "1: RS485"]
CTL0_MODE_RS485 = 1 , # [doc = "2: IDLELINE"]
CTL0_MODE_IDLELINE = 2 , # [doc = "3: ADDR9BIT"]
CTL0_MODE_ADDR9BIT = 3 , # [doc = "4: SMART"]
CTL0_MODE_SMART = 4 , # [doc = "5: DALI"]
CTL0_MODE_DALI = 5 , } impl From < CTL0_MODE_A > for u8 { # [inline (always)]
fn from (variant : CTL0_MODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_MODE_A { type Ux = u8 ; } impl CTL0_MODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL0_MODE_A > { match self . bits { 0 => Some (CTL0_MODE_A :: CTL0_MODE_UART) , 1 => Some (CTL0_MODE_A :: CTL0_MODE_RS485) , 2 => Some (CTL0_MODE_A :: CTL0_MODE_IDLELINE) , 3 => Some (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) , 4 => Some (CTL0_MODE_A :: CTL0_MODE_SMART) , 5 => Some (CTL0_MODE_A :: CTL0_MODE_DALI) , _ => None , } } # [doc = "UART"]
# [inline (always)]
pub fn is_ctl0_mode_uart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_UART } # [doc = "RS485"]
# [inline (always)]
pub fn is_ctl0_mode_rs485 (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_RS485 } # [doc = "IDLELINE"]
# [inline (always)]
pub fn is_ctl0_mode_idleline (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_IDLELINE } # [doc = "ADDR9BIT"]
# [inline (always)]
pub fn is_ctl0_mode_addr9bit (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_ADDR9BIT } # [doc = "SMART"]
# [inline (always)]
pub fn is_ctl0_mode_smart (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_SMART } # [doc = "DALI"]
# [inline (always)]
pub fn is_ctl0_mode_dali (& self) -> bool { * self == CTL0_MODE_A :: CTL0_MODE_DALI } } # [doc = "Field `CTL0_MODE` writer - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
pub type CTL0_MODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL0_MODE_A > ; impl < 'a , REG , const O : u8 > CTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UART"]
# [inline (always)]
pub fn ctl0_mode_uart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_UART) } # [doc = "RS485"]
# [inline (always)]
pub fn ctl0_mode_rs485 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_RS485) } # [doc = "IDLELINE"]
# [inline (always)]
pub fn ctl0_mode_idleline (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_IDLELINE) } # [doc = "ADDR9BIT"]
# [inline (always)]
pub fn ctl0_mode_addr9bit (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_ADDR9BIT) } # [doc = "SMART"]
# [inline (always)]
pub fn ctl0_mode_smart (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_SMART) } # [doc = "DALI"]
# [inline (always)]
pub fn ctl0_mode_dali (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MODE_A :: CTL0_MODE_DALI) } } # [doc = "Field `CTL0_RTS` reader - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
pub type CTL0_RTS_R = crate :: BitReader < CTL0_RTS_A > ; # [doc = "Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_RTS_A { # [doc = "0: CLR"]
CTL0_RTS_CLR = 0 , # [doc = "1: SET"]
CTL0_RTS_SET = 1 , } impl From < CTL0_RTS_A > for bool { # [inline (always)]
fn from (variant : CTL0_RTS_A) -> Self { variant as u8 != 0 } } impl CTL0_RTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_RTS_A { match self . bits { false => CTL0_RTS_A :: CTL0_RTS_CLR , true => CTL0_RTS_A :: CTL0_RTS_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ctl0_rts_clr (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ctl0_rts_set (& self) -> bool { * self == CTL0_RTS_A :: CTL0_RTS_SET } } # [doc = "Field `CTL0_RTS` writer - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
pub type CTL0_RTS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTS_A > ; impl < 'a , REG , const O : u8 > CTL0_RTS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn ctl0_rts_clr (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn ctl0_rts_set (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTS_A :: CTL0_RTS_SET) } } # [doc = "Field `CTL0_RTSEN` reader - Enable hardware controlled Request to Send"]
pub type CTL0_RTSEN_R = crate :: BitReader < CTL0_RTSEN_A > ; # [doc = "Enable hardware controlled Request to Send\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_RTSEN_A { # [doc = "0: DISABLE"]
CTL0_RTSEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_RTSEN_ENABLE = 1 , } impl From < CTL0_RTSEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_RTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_RTSEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_RTSEN_A { match self . bits { false => CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE , true => CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_rtsen_disable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_rtsen_enable (& self) -> bool { * self == CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE } } # [doc = "Field `CTL0_RTSEN` writer - Enable hardware controlled Request to Send"]
pub type CTL0_RTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_RTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_RTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_rtsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_rtsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_RTSEN_A :: CTL0_RTSEN_ENABLE) } } # [doc = "Field `CTL0_CTSEN` reader - Enable Clear To Send"]
pub type CTL0_CTSEN_R = crate :: BitReader < CTL0_CTSEN_A > ; # [doc = "Enable Clear To Send\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_CTSEN_A { # [doc = "0: DISABLE"]
CTL0_CTSEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_CTSEN_ENABLE = 1 , } impl From < CTL0_CTSEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_CTSEN_A) -> Self { variant as u8 != 0 } } impl CTL0_CTSEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_CTSEN_A { match self . bits { false => CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE , true => CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_ctsen_disable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_ctsen_enable (& self) -> bool { * self == CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE } } # [doc = "Field `CTL0_CTSEN` writer - Enable Clear To Send"]
pub type CTL0_CTSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_CTSEN_A > ; impl < 'a , REG , const O : u8 > CTL0_CTSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_ctsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_ctsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_CTSEN_A :: CTL0_CTSEN_ENABLE) } } # [doc = "Field `CTL0_HSE` reader - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
pub type CTL0_HSE_R = crate :: FieldReader < CTL0_HSE_A > ; # [doc = "High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_HSE_A { # [doc = "0: OVS16"]
CTL0_HSE_OVS16 = 0 , # [doc = "1: OVS8"]
CTL0_HSE_OVS8 = 1 , # [doc = "2: OVS3"]
CTL0_HSE_OVS3 = 2 , } impl From < CTL0_HSE_A > for u8 { # [inline (always)]
fn from (variant : CTL0_HSE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_HSE_A { type Ux = u8 ; } impl CTL0_HSE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL0_HSE_A > { match self . bits { 0 => Some (CTL0_HSE_A :: CTL0_HSE_OVS16) , 1 => Some (CTL0_HSE_A :: CTL0_HSE_OVS8) , 2 => Some (CTL0_HSE_A :: CTL0_HSE_OVS3) , _ => None , } } # [doc = "OVS16"]
# [inline (always)]
pub fn is_ctl0_hse_ovs16 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS16 } # [doc = "OVS8"]
# [inline (always)]
pub fn is_ctl0_hse_ovs8 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS8 } # [doc = "OVS3"]
# [inline (always)]
pub fn is_ctl0_hse_ovs3 (& self) -> bool { * self == CTL0_HSE_A :: CTL0_HSE_OVS3 } } # [doc = "Field `CTL0_HSE` writer - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
pub type CTL0_HSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL0_HSE_A > ; impl < 'a , REG , const O : u8 > CTL0_HSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OVS16"]
# [inline (always)]
pub fn ctl0_hse_ovs16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS16) } # [doc = "OVS8"]
# [inline (always)]
pub fn ctl0_hse_ovs8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS8) } # [doc = "OVS3"]
# [inline (always)]
pub fn ctl0_hse_ovs3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_HSE_A :: CTL0_HSE_OVS3) } } # [doc = "Field `CTL0_FEN` reader - UART Enable FIFOs"]
pub type CTL0_FEN_R = crate :: BitReader < CTL0_FEN_A > ; # [doc = "UART Enable FIFOs\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_FEN_A { # [doc = "0: DISABLE"]
CTL0_FEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_FEN_ENABLE = 1 , } impl From < CTL0_FEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_FEN_A) -> Self { variant as u8 != 0 } } impl CTL0_FEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_FEN_A { match self . bits { false => CTL0_FEN_A :: CTL0_FEN_DISABLE , true => CTL0_FEN_A :: CTL0_FEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_fen_disable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_fen_enable (& self) -> bool { * self == CTL0_FEN_A :: CTL0_FEN_ENABLE } } # [doc = "Field `CTL0_FEN` writer - UART Enable FIFOs"]
pub type CTL0_FEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_FEN_A > ; impl < 'a , REG , const O : u8 > CTL0_FEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_fen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_fen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_FEN_A :: CTL0_FEN_ENABLE) } } # [doc = "Field `CTL0_MAJVOTE` reader - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
pub type CTL0_MAJVOTE_R = crate :: BitReader < CTL0_MAJVOTE_A > ; # [doc = "When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_MAJVOTE_A { # [doc = "0: DISABLE"]
CTL0_MAJVOTE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_MAJVOTE_ENABLE = 1 , } impl From < CTL0_MAJVOTE_A > for bool { # [inline (always)]
fn from (variant : CTL0_MAJVOTE_A) -> Self { variant as u8 != 0 } } impl CTL0_MAJVOTE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_MAJVOTE_A { match self . bits { false => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE , true => CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_majvote_disable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_majvote_enable (& self) -> bool { * self == CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE } } # [doc = "Field `CTL0_MAJVOTE` writer - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
pub type CTL0_MAJVOTE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MAJVOTE_A > ; impl < 'a , REG , const O : u8 > CTL0_MAJVOTE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_majvote_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_majvote_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MAJVOTE_A :: CTL0_MAJVOTE_ENABLE) } } # [doc = "Field `CTL0_MSBFIRST` reader - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
pub type CTL0_MSBFIRST_R = crate :: BitReader < CTL0_MSBFIRST_A > ; # [doc = "Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_MSBFIRST_A { # [doc = "0: DISABLE"]
CTL0_MSBFIRST_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_MSBFIRST_ENABLE = 1 , } impl From < CTL0_MSBFIRST_A > for bool { # [inline (always)]
fn from (variant : CTL0_MSBFIRST_A) -> Self { variant as u8 != 0 } } impl CTL0_MSBFIRST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_MSBFIRST_A { match self . bits { false => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE , true => CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_msbfirst_disable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_msbfirst_enable (& self) -> bool { * self == CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE } } # [doc = "Field `CTL0_MSBFIRST` writer - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
pub type CTL0_MSBFIRST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_MSBFIRST_A > ; impl < 'a , REG , const O : u8 > CTL0_MSBFIRST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_msbfirst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_msbfirst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_MSBFIRST_A :: CTL0_MSBFIRST_ENABLE) } } impl R { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
# [inline (always)]
pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Loop Back Enable"]
# [inline (always)]
pub fn ctl0_lbe (& self) -> CTL0_LBE_R { CTL0_LBE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
# [inline (always)]
pub fn ctl0_rxe (& self) -> CTL0_RXE_R { CTL0_RXE_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
# [inline (always)]
pub fn ctl0_txe (& self) -> CTL0_TXE_R { CTL0_TXE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
# [inline (always)]
pub fn ctl0_txd_out_en (& self) -> CTL0_TXD_OUT_EN_R { CTL0_TXD_OUT_EN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
# [inline (always)]
pub fn ctl0_txd_out (& self) -> CTL0_TXD_OUT_R { CTL0_TXD_OUT_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
# [inline (always)]
pub fn ctl0_mode (& self) -> CTL0_MODE_R { CTL0_MODE_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
# [inline (always)]
pub fn ctl0_rts (& self) -> CTL0_RTS_R { CTL0_RTS_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"]
# [inline (always)]
pub fn ctl0_rtsen (& self) -> CTL0_RTSEN_R { CTL0_RTSEN_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Enable Clear To Send"]
# [inline (always)]
pub fn ctl0_ctsen (& self) -> CTL0_CTSEN_R { CTL0_CTSEN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
# [inline (always)]
pub fn ctl0_hse (& self) -> CTL0_HSE_R { CTL0_HSE_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bit 17 - UART Enable FIFOs"]
# [inline (always)]
pub fn ctl0_fen (& self) -> CTL0_FEN_R { CTL0_FEN_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
# [inline (always)]
pub fn ctl0_majvote (& self) -> CTL0_MAJVOTE_R { CTL0_MAJVOTE_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
# [inline (always)]
pub fn ctl0_msbfirst (& self) -> CTL0_MSBFIRST_R { CTL0_MSBFIRST_R :: new (((self . bits >> 19) & 1) != 0) } } impl W { # [doc = "Bit 0 - UART Module Enable. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. If the ENABLE bit is not set, all registers can still be accessed and updated. It is recommended to setup and change the UART operation mode with having the ENABLE bit cleared to avoid unpredictable behavior during the setup or update. If disabled the UART module will not send or receive any data and the logic is held in reset state."]
# [inline (always)]
# [must_use]
pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 2 - UART Loop Back Enable"]
# [inline (always)]
# [must_use]
pub fn ctl0_lbe (& mut self) -> CTL0_LBE_W < CTL0_SPEC , 2 > { CTL0_LBE_W :: new (self) } # [doc = "Bit 3 - UART Receive Enable If the UART is disabled in the middle of a receive, it completes the current character before stopping. #b#NOTE:#/b# To enable reception, the UARTEN bit must be set."]
# [inline (always)]
# [must_use]
pub fn ctl0_rxe (& mut self) -> CTL0_RXE_W < CTL0_SPEC , 3 > { CTL0_RXE_W :: new (self) } # [doc = "Bit 4 - UART Transmit Enable If the UART is disabled in the middle of a transmission, it completes the current character before stopping. #b#NOTE:#/b# To enable transmission, the UARTEN bit must be set."]
# [inline (always)]
# [must_use]
pub fn ctl0_txe (& mut self) -> CTL0_TXE_W < CTL0_SPEC , 4 > { CTL0_TXE_W :: new (self) } # [doc = "Bit 5 - TXD Pin Control Enable. When the transmit section of the UART is disabled (TXE = 0), the TXD pin can be controlled by the TXD_OUT bit. 1 = UARTxTXD pin can be controlled by TXD_OUT, if TXE = 0"]
# [inline (always)]
# [must_use]
pub fn ctl0_txd_out_en (& mut self) -> CTL0_TXD_OUT_EN_W < CTL0_SPEC , 5 > { CTL0_TXD_OUT_EN_W :: new (self) } # [doc = "Bit 6 - TXD Pin Control Controls the TXD pin when TXD_OUT_EN = 1 and TXE = 0."]
# [inline (always)]
# [must_use]
pub fn ctl0_txd_out (& mut self) -> CTL0_TXD_OUT_W < CTL0_SPEC , 6 > { CTL0_TXD_OUT_W :: new (self) } # [doc = "Bits 8:10 - Set the communication mode and protocol used. (Not defined settings uses the default setting: 0)"]
# [inline (always)]
# [must_use]
pub fn ctl0_mode (& mut self) -> CTL0_MODE_W < CTL0_SPEC , 8 > { CTL0_MODE_W :: new (self) } # [doc = "Bit 12 - Request to Send If RTSEN is set the RTS output signals is controlled by the hardware logic using the FIFO fill level or TXDATA buffer. If RTSEN is cleared the RTS output is controlled by the RTS bit. The bit is the complement of the UART request to send, RTS modem status output."]
# [inline (always)]
# [must_use]
pub fn ctl0_rts (& mut self) -> CTL0_RTS_W < CTL0_SPEC , 12 > { CTL0_RTS_W :: new (self) } # [doc = "Bit 13 - Enable hardware controlled Request to Send"]
# [inline (always)]
# [must_use]
pub fn ctl0_rtsen (& mut self) -> CTL0_RTSEN_W < CTL0_SPEC , 13 > { CTL0_RTSEN_W :: new (self) } # [doc = "Bit 14 - Enable Clear To Send"]
# [inline (always)]
# [must_use]
pub fn ctl0_ctsen (& mut self) -> CTL0_CTSEN_W < CTL0_SPEC , 14 > { CTL0_CTSEN_W :: new (self) } # [doc = "Bits 15:16 - High-Speed Bit Oversampling Enable #b#NOTE:#/b# The bit oversampling influences the UART baud-rate configuration (see and ). The state of this bit has no effect on clock generation in ISO7816 smart card mode (the SMART bit is set)."]
# [inline (always)]
# [must_use]
pub fn ctl0_hse (& mut self) -> CTL0_HSE_W < CTL0_SPEC , 15 > { CTL0_HSE_W :: new (self) } # [doc = "Bit 17 - UART Enable FIFOs"]
# [inline (always)]
# [must_use]
pub fn ctl0_fen (& mut self) -> CTL0_FEN_W < CTL0_SPEC , 17 > { CTL0_FEN_W :: new (self) } # [doc = "Bit 18 - When enabled with oversmapling of 16, samples samples 7, 8, and 9 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values do not match, RIS.NERR bit is set along with RDR.NERR When enabled with oversmapling of 8, samples samples 3, 4, and 5 are majority voted to decide the sampled bit value. The value correspond to al least 2 of the 3 samples is considered to be the received value. In case the 3 values donot match, RIS.NERR bit is set along with RDR.NERR When disabled, only a single sample of received bit is taken."]
# [inline (always)]
# [must_use]
pub fn ctl0_majvote (& mut self) -> CTL0_MAJVOTE_W < CTL0_SPEC , 18 > { CTL0_MAJVOTE_W :: new (self) } # [doc = "Bit 19 - Most Significant Bit First This bit has effect both on the way protocol byte is transmitted and received. Notes: User needs to match the protocol to the correct value of this bit to send MSb or LSb first. The hardware engine will send the byte entirely based on this bit."]
# [inline (always)]
# [must_use]
pub fn ctl0_msbfirst (& mut self) -> CTL0_MSBFIRST_W < CTL0_SPEC , 19 > { CTL0_MSBFIRST_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0x38"]
impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x38 ; } } # [doc = "LCRH (rw) register accessor: UART Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcrh::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcrh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lcrh`]
module"]
pub type LCRH = crate :: Reg < lcrh :: LCRH_SPEC > ; # [doc = "UART Line Control Register"]
pub mod lcrh { # [doc = "Register `LCRH` reader"]
pub type R = crate :: R < LCRH_SPEC > ; # [doc = "Register `LCRH` writer"]
pub type W = crate :: W < LCRH_SPEC > ; # [doc = "Field `LCRH_BRK` reader - UART Send Break (for LIN Protocol)"]
pub type LCRH_BRK_R = crate :: BitReader < LCRH_BRK_A > ; # [doc = "UART Send Break (for LIN Protocol)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_BRK_A { # [doc = "0: DISABLE"]
LCRH_BRK_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_BRK_ENABLE = 1 , } impl From < LCRH_BRK_A > for bool { # [inline (always)]
fn from (variant : LCRH_BRK_A) -> Self { variant as u8 != 0 } } impl LCRH_BRK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_BRK_A { match self . bits { false => LCRH_BRK_A :: LCRH_BRK_DISABLE , true => LCRH_BRK_A :: LCRH_BRK_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_brk_disable (& self) -> bool { * self == LCRH_BRK_A :: LCRH_BRK_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_brk_enable (& self) -> bool { * self == LCRH_BRK_A :: LCRH_BRK_ENABLE } } # [doc = "Field `LCRH_BRK` writer - UART Send Break (for LIN Protocol)"]
pub type LCRH_BRK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_BRK_A > ; impl < 'a , REG , const O : u8 > LCRH_BRK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_brk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_BRK_A :: LCRH_BRK_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_brk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_BRK_A :: LCRH_BRK_ENABLE) } } # [doc = "Field `LCRH_PEN` reader - UART Parity Enable"]
pub type LCRH_PEN_R = crate :: BitReader < LCRH_PEN_A > ; # [doc = "UART Parity Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_PEN_A { # [doc = "0: DISABLE"]
LCRH_PEN_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_PEN_ENABLE = 1 , } impl From < LCRH_PEN_A > for bool { # [inline (always)]
fn from (variant : LCRH_PEN_A) -> Self { variant as u8 != 0 } } impl LCRH_PEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_PEN_A { match self . bits { false => LCRH_PEN_A :: LCRH_PEN_DISABLE , true => LCRH_PEN_A :: LCRH_PEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_pen_disable (& self) -> bool { * self == LCRH_PEN_A :: LCRH_PEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_pen_enable (& self) -> bool { * self == LCRH_PEN_A :: LCRH_PEN_ENABLE } } # [doc = "Field `LCRH_PEN` writer - UART Parity Enable"]
pub type LCRH_PEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_PEN_A > ; impl < 'a , REG , const O : u8 > LCRH_PEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_pen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_PEN_A :: LCRH_PEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_pen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_PEN_A :: LCRH_PEN_ENABLE) } } # [doc = "Field `LCRH_EPS` reader - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
pub type LCRH_EPS_R = crate :: BitReader < LCRH_EPS_A > ; # [doc = "UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_EPS_A { # [doc = "0: ODD"]
LCRH_EPS_ODD = 0 , # [doc = "1: EVEN"]
LCRH_EPS_EVEN = 1 , } impl From < LCRH_EPS_A > for bool { # [inline (always)]
fn from (variant : LCRH_EPS_A) -> Self { variant as u8 != 0 } } impl LCRH_EPS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_EPS_A { match self . bits { false => LCRH_EPS_A :: LCRH_EPS_ODD , true => LCRH_EPS_A :: LCRH_EPS_EVEN , } } # [doc = "ODD"]
# [inline (always)]
pub fn is_lcrh_eps_odd (& self) -> bool { * self == LCRH_EPS_A :: LCRH_EPS_ODD } # [doc = "EVEN"]
# [inline (always)]
pub fn is_lcrh_eps_even (& self) -> bool { * self == LCRH_EPS_A :: LCRH_EPS_EVEN } } # [doc = "Field `LCRH_EPS` writer - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
pub type LCRH_EPS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_EPS_A > ; impl < 'a , REG , const O : u8 > LCRH_EPS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "ODD"]
# [inline (always)]
pub fn lcrh_eps_odd (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_EPS_A :: LCRH_EPS_ODD) } # [doc = "EVEN"]
# [inline (always)]
pub fn lcrh_eps_even (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_EPS_A :: LCRH_EPS_EVEN) } } # [doc = "Field `LCRH_STP2` reader - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
pub type LCRH_STP2_R = crate :: BitReader < LCRH_STP2_A > ; # [doc = "UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_STP2_A { # [doc = "0: DISABLE"]
LCRH_STP2_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_STP2_ENABLE = 1 , } impl From < LCRH_STP2_A > for bool { # [inline (always)]
fn from (variant : LCRH_STP2_A) -> Self { variant as u8 != 0 } } impl LCRH_STP2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_STP2_A { match self . bits { false => LCRH_STP2_A :: LCRH_STP2_DISABLE , true => LCRH_STP2_A :: LCRH_STP2_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_stp2_disable (& self) -> bool { * self == LCRH_STP2_A :: LCRH_STP2_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_stp2_enable (& self) -> bool { * self == LCRH_STP2_A :: LCRH_STP2_ENABLE } } # [doc = "Field `LCRH_STP2` writer - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
pub type LCRH_STP2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_STP2_A > ; impl < 'a , REG , const O : u8 > LCRH_STP2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_stp2_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_STP2_A :: LCRH_STP2_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_stp2_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_STP2_A :: LCRH_STP2_ENABLE) } } # [doc = "Field `LCRH_WLEN` reader - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
pub type LCRH_WLEN_R = crate :: FieldReader < LCRH_WLEN_A > ; # [doc = "UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum LCRH_WLEN_A { # [doc = "0: DATABIT5"]
LCRH_WLEN_DATABIT5 = 0 , # [doc = "1: DATABIT6"]
LCRH_WLEN_DATABIT6 = 1 , # [doc = "2: DATABIT7"]
LCRH_WLEN_DATABIT7 = 2 , # [doc = "3: DATABIT8"]
LCRH_WLEN_DATABIT8 = 3 , } impl From < LCRH_WLEN_A > for u8 { # [inline (always)]
fn from (variant : LCRH_WLEN_A) -> Self { variant as _ } } impl crate :: FieldSpec for LCRH_WLEN_A { type Ux = u8 ; } impl LCRH_WLEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_WLEN_A { match self . bits { 0 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT5 , 1 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT6 , 2 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT7 , 3 => LCRH_WLEN_A :: LCRH_WLEN_DATABIT8 , _ => unreachable ! () , } } # [doc = "DATABIT5"]
# [inline (always)]
pub fn is_lcrh_wlen_databit5 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT5 } # [doc = "DATABIT6"]
# [inline (always)]
pub fn is_lcrh_wlen_databit6 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT6 } # [doc = "DATABIT7"]
# [inline (always)]
pub fn is_lcrh_wlen_databit7 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT7 } # [doc = "DATABIT8"]
# [inline (always)]
pub fn is_lcrh_wlen_databit8 (& self) -> bool { * self == LCRH_WLEN_A :: LCRH_WLEN_DATABIT8 } } # [doc = "Field `LCRH_WLEN` writer - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
pub type LCRH_WLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , LCRH_WLEN_A > ; impl < 'a , REG , const O : u8 > LCRH_WLEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DATABIT5"]
# [inline (always)]
pub fn lcrh_wlen_databit5 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT5) } # [doc = "DATABIT6"]
# [inline (always)]
pub fn lcrh_wlen_databit6 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT6) } # [doc = "DATABIT7"]
# [inline (always)]
pub fn lcrh_wlen_databit7 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT7) } # [doc = "DATABIT8"]
# [inline (always)]
pub fn lcrh_wlen_databit8 (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_WLEN_A :: LCRH_WLEN_DATABIT8) } } # [doc = "Field `LCRH_SPS` reader - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
pub type LCRH_SPS_R = crate :: BitReader < LCRH_SPS_A > ; # [doc = "UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_SPS_A { # [doc = "0: DISABLE"]
LCRH_SPS_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_SPS_ENABLE = 1 , } impl From < LCRH_SPS_A > for bool { # [inline (always)]
fn from (variant : LCRH_SPS_A) -> Self { variant as u8 != 0 } } impl LCRH_SPS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_SPS_A { match self . bits { false => LCRH_SPS_A :: LCRH_SPS_DISABLE , true => LCRH_SPS_A :: LCRH_SPS_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_sps_disable (& self) -> bool { * self == LCRH_SPS_A :: LCRH_SPS_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_sps_enable (& self) -> bool { * self == LCRH_SPS_A :: LCRH_SPS_ENABLE } } # [doc = "Field `LCRH_SPS` writer - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
pub type LCRH_SPS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_SPS_A > ; impl < 'a , REG , const O : u8 > LCRH_SPS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_sps_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SPS_A :: LCRH_SPS_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_sps_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SPS_A :: LCRH_SPS_ENABLE) } } # [doc = "Field `LCRH_SENDIDLE` reader - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
pub type LCRH_SENDIDLE_R = crate :: BitReader < LCRH_SENDIDLE_A > ; # [doc = "UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum LCRH_SENDIDLE_A { # [doc = "0: DISABLE"]
LCRH_SENDIDLE_DISABLE = 0 , # [doc = "1: ENABLE"]
LCRH_SENDIDLE_ENABLE = 1 , } impl From < LCRH_SENDIDLE_A > for bool { # [inline (always)]
fn from (variant : LCRH_SENDIDLE_A) -> Self { variant as u8 != 0 } } impl LCRH_SENDIDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> LCRH_SENDIDLE_A { match self . bits { false => LCRH_SENDIDLE_A :: LCRH_SENDIDLE_DISABLE , true => LCRH_SENDIDLE_A :: LCRH_SENDIDLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_lcrh_sendidle_disable (& self) -> bool { * self == LCRH_SENDIDLE_A :: LCRH_SENDIDLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_lcrh_sendidle_enable (& self) -> bool { * self == LCRH_SENDIDLE_A :: LCRH_SENDIDLE_ENABLE } } # [doc = "Field `LCRH_SENDIDLE` writer - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
pub type LCRH_SENDIDLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , LCRH_SENDIDLE_A > ; impl < 'a , REG , const O : u8 > LCRH_SENDIDLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn lcrh_sendidle_disable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SENDIDLE_A :: LCRH_SENDIDLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn lcrh_sendidle_enable (self) -> & 'a mut crate :: W < REG > { self . variant (LCRH_SENDIDLE_A :: LCRH_SENDIDLE_ENABLE) } } # [doc = "Field `LCRH_EXTDIR_SETUP` reader - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
pub type LCRH_EXTDIR_SETUP_R = crate :: FieldReader ; # [doc = "Field `LCRH_EXTDIR_SETUP` writer - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
pub type LCRH_EXTDIR_SETUP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O > ; # [doc = "Field `LCRH_EXTDIR_HOLD` reader - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
pub type LCRH_EXTDIR_HOLD_R = crate :: FieldReader ; # [doc = "Field `LCRH_EXTDIR_HOLD` writer - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
pub type LCRH_EXTDIR_HOLD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O > ; impl R { # [doc = "Bit 0 - UART Send Break (for LIN Protocol)"]
# [inline (always)]
pub fn lcrh_brk (& self) -> LCRH_BRK_R { LCRH_BRK_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - UART Parity Enable"]
# [inline (always)]
pub fn lcrh_pen (& self) -> LCRH_PEN_R { LCRH_PEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
# [inline (always)]
pub fn lcrh_eps (& self) -> LCRH_EPS_R { LCRH_EPS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
# [inline (always)]
pub fn lcrh_stp2 (& self) -> LCRH_STP2_R { LCRH_STP2_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bits 4:5 - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
# [inline (always)]
pub fn lcrh_wlen (& self) -> LCRH_WLEN_R { LCRH_WLEN_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
# [inline (always)]
pub fn lcrh_sps (& self) -> LCRH_SPS_R { LCRH_SPS_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
# [inline (always)]
pub fn lcrh_sendidle (& self) -> LCRH_SENDIDLE_R { LCRH_SENDIDLE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:20 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
# [inline (always)]
pub fn lcrh_extdir_setup (& self) -> LCRH_EXTDIR_SETUP_R { LCRH_EXTDIR_SETUP_R :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 21:25 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
# [inline (always)]
pub fn lcrh_extdir_hold (& self) -> LCRH_EXTDIR_HOLD_R { LCRH_EXTDIR_HOLD_R :: new (((self . bits >> 21) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - UART Send Break (for LIN Protocol)"]
# [inline (always)]
# [must_use]
pub fn lcrh_brk (& mut self) -> LCRH_BRK_W < LCRH_SPEC , 0 > { LCRH_BRK_W :: new (self) } # [doc = "Bit 1 - UART Parity Enable"]
# [inline (always)]
# [must_use]
pub fn lcrh_pen (& mut self) -> LCRH_PEN_W < LCRH_SPEC , 1 > { LCRH_PEN_W :: new (self) } # [doc = "Bit 2 - UART Even Parity Select This bit has no effect when parity is disabled by the PEN bit. For 9-Bit UART Mode transmissions, this bit controls the address byte and data byte indication (9th bit). 0 = The transferred byte is a data byte 1 = The transferred byte is an address byte"]
# [inline (always)]
# [must_use]
pub fn lcrh_eps (& mut self) -> LCRH_EPS_W < LCRH_SPEC , 2 > { LCRH_EPS_W :: new (self) } # [doc = "Bit 3 - UART Two Stop Bits Select When in 7816 smart card mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2."]
# [inline (always)]
# [must_use]
pub fn lcrh_stp2 (& mut self) -> LCRH_STP2_W < LCRH_SPEC , 3 > { LCRH_STP2_W :: new (self) } # [doc = "Bits 4:5 - UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows:"]
# [inline (always)]
# [must_use]
pub fn lcrh_wlen (& mut self) -> LCRH_WLEN_W < LCRH_SPEC , 4 > { LCRH_WLEN_W :: new (self) } # [doc = "Bit 6 - UART Stick Parity Select The Stick Parity Select (SPS) bit is used to set either a permanent '1' or a permanent '0' as parity when transmitting or receiving data. Its purpose is to typically indicate the first byte of a package or to mark an address byte, for example in a multi-drop RS-485 network. 0h = Stick parity is disabled 1h = Stick parity is enabled. When bits PEN, EPS, and SPS of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits PEN and SPS are set and EPS is cleared, the parity bit is transmitted and checked as a 1."]
# [inline (always)]
# [must_use]
pub fn lcrh_sps (& mut self) -> LCRH_SPS_W < LCRH_SPEC , 6 > { LCRH_SPS_W :: new (self) } # [doc = "Bit 7 - UART send IDLE pattern. When this bit is set an SENDIDLE period of 11 bit times will be sent on the TX line. The bit is cleared by hardware afterwards."]
# [inline (always)]
# [must_use]
pub fn lcrh_sendidle (& mut self) -> LCRH_SENDIDLE_W < LCRH_SPEC , 7 > { LCRH_SENDIDLE_W :: new (self) } # [doc = "Bits 16:20 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be set before the START bit is send"]
# [inline (always)]
# [must_use]
pub fn lcrh_extdir_setup (& mut self) -> LCRH_EXTDIR_SETUP_W < LCRH_SPEC , 16 > { LCRH_EXTDIR_SETUP_W :: new (self) } # [doc = "Bits 21:25 - Defines the number of UARTclk ticks the signal to control the external driver for the RS485 will be reset after the beginning of the stop bit. (If 2 STOP bits are enabled the beginning of the 2nd STOP bit.)"]
# [inline (always)]
# [must_use]
pub fn lcrh_extdir_hold (& mut self) -> LCRH_EXTDIR_HOLD_W < LCRH_SPEC , 21 > { LCRH_EXTDIR_HOLD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Line Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lcrh::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lcrh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LCRH_SPEC ; impl crate :: RegisterSpec for LCRH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`lcrh::R`](R) reader structure"]
impl crate :: Readable for LCRH_SPEC { } # [doc = "`write(|w| ..)` method takes [`lcrh::W`](W) writer structure"]
impl crate :: Writable for LCRH_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LCRH to value 0"]
impl crate :: Resettable for LCRH_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "UART Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_BUSY` reader - UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation."]
pub type STAT_BUSY_R = crate :: BitReader < STAT_BUSY_A > ; # [doc = "UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_BUSY_A { # [doc = "0: CLEARED"]
STAT_BUSY_CLEARED = 0 , # [doc = "1: SET"]
STAT_BUSY_SET = 1 , } impl From < STAT_BUSY_A > for bool { # [inline (always)]
fn from (variant : STAT_BUSY_A) -> Self { variant as u8 != 0 } } impl STAT_BUSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_BUSY_A { match self . bits { false => STAT_BUSY_A :: STAT_BUSY_CLEARED , true => STAT_BUSY_A :: STAT_BUSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_busy_cleared (& self) -> bool { * self == STAT_BUSY_A :: STAT_BUSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_busy_set (& self) -> bool { * self == STAT_BUSY_A :: STAT_BUSY_SET } } # [doc = "Field `STAT_RXFE` reader - UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_RXFE_R = crate :: BitReader < STAT_RXFE_A > ; # [doc = "UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RXFE_A { # [doc = "0: CLEARED"]
STAT_RXFE_CLEARED = 0 , # [doc = "1: SET"]
STAT_RXFE_SET = 1 , } impl From < STAT_RXFE_A > for bool { # [inline (always)]
fn from (variant : STAT_RXFE_A) -> Self { variant as u8 != 0 } } impl STAT_RXFE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RXFE_A { match self . bits { false => STAT_RXFE_A :: STAT_RXFE_CLEARED , true => STAT_RXFE_A :: STAT_RXFE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_rxfe_cleared (& self) -> bool { * self == STAT_RXFE_A :: STAT_RXFE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_rxfe_set (& self) -> bool { * self == STAT_RXFE_A :: STAT_RXFE_SET } } # [doc = "Field `STAT_RXFF` reader - UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_RXFF_R = crate :: BitReader < STAT_RXFF_A > ; # [doc = "UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RXFF_A { # [doc = "0: CLEARED"]
STAT_RXFF_CLEARED = 0 , # [doc = "1: SET"]
STAT_RXFF_SET = 1 , } impl From < STAT_RXFF_A > for bool { # [inline (always)]
fn from (variant : STAT_RXFF_A) -> Self { variant as u8 != 0 } } impl STAT_RXFF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RXFF_A { match self . bits { false => STAT_RXFF_A :: STAT_RXFF_CLEARED , true => STAT_RXFF_A :: STAT_RXFF_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_rxff_cleared (& self) -> bool { * self == STAT_RXFF_A :: STAT_RXFF_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_rxff_set (& self) -> bool { * self == STAT_RXFF_A :: STAT_RXFF_SET } } # [doc = "Field `STAT_TXFE` reader - UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_TXFE_R = crate :: BitReader < STAT_TXFE_A > ; # [doc = "UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_TXFE_A { # [doc = "0: CLEARED"]
STAT_TXFE_CLEARED = 0 , # [doc = "1: SET"]
STAT_TXFE_SET = 1 , } impl From < STAT_TXFE_A > for bool { # [inline (always)]
fn from (variant : STAT_TXFE_A) -> Self { variant as u8 != 0 } } impl STAT_TXFE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_TXFE_A { match self . bits { false => STAT_TXFE_A :: STAT_TXFE_CLEARED , true => STAT_TXFE_A :: STAT_TXFE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_txfe_cleared (& self) -> bool { * self == STAT_TXFE_A :: STAT_TXFE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_txfe_set (& self) -> bool { * self == STAT_TXFE_A :: STAT_TXFE_SET } } # [doc = "Field `STAT_TXFF` reader - UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
pub type STAT_TXFF_R = crate :: BitReader < STAT_TXFF_A > ; # [doc = "UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_TXFF_A { # [doc = "0: CLEARED"]
STAT_TXFF_CLEARED = 0 , # [doc = "1: SET"]
STAT_TXFF_SET = 1 , } impl From < STAT_TXFF_A > for bool { # [inline (always)]
fn from (variant : STAT_TXFF_A) -> Self { variant as u8 != 0 } } impl STAT_TXFF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_TXFF_A { match self . bits { false => STAT_TXFF_A :: STAT_TXFF_CLEARED , true => STAT_TXFF_A :: STAT_TXFF_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_txff_cleared (& self) -> bool { * self == STAT_TXFF_A :: STAT_TXFF_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_txff_set (& self) -> bool { * self == STAT_TXFF_A :: STAT_TXFF_SET } } # [doc = "Field `STAT_CTS` reader - Clear To Send"]
pub type STAT_CTS_R = crate :: BitReader < STAT_CTS_A > ; # [doc = "Clear To Send\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_CTS_A { # [doc = "0: CLEARED"]
STAT_CTS_CLEARED = 0 , # [doc = "1: SET"]
STAT_CTS_SET = 1 , } impl From < STAT_CTS_A > for bool { # [inline (always)]
fn from (variant : STAT_CTS_A) -> Self { variant as u8 != 0 } } impl STAT_CTS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_CTS_A { match self . bits { false => STAT_CTS_A :: STAT_CTS_CLEARED , true => STAT_CTS_A :: STAT_CTS_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_cts_cleared (& self) -> bool { * self == STAT_CTS_A :: STAT_CTS_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_cts_set (& self) -> bool { * self == STAT_CTS_A :: STAT_CTS_SET } } # [doc = "Field `STAT_IDLE` reader - IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address."]
pub type STAT_IDLE_R = crate :: BitReader < STAT_IDLE_A > ; # [doc = "IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_IDLE_A { # [doc = "0: CLEARED"]
STAT_IDLE_CLEARED = 0 , # [doc = "1: SET"]
STAT_IDLE_SET = 1 , } impl From < STAT_IDLE_A > for bool { # [inline (always)]
fn from (variant : STAT_IDLE_A) -> Self { variant as u8 != 0 } } impl STAT_IDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_IDLE_A { match self . bits { false => STAT_IDLE_A :: STAT_IDLE_CLEARED , true => STAT_IDLE_A :: STAT_IDLE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_stat_idle_cleared (& self) -> bool { * self == STAT_IDLE_A :: STAT_IDLE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_stat_idle_set (& self) -> bool { * self == STAT_IDLE_A :: STAT_IDLE_SET } } impl R { # [doc = "Bit 0 - UART Busy This bit is set as soon as the transmit FIFO or TXBuffer becomes non-empty (regardless of whether UART is enabled) or if a receive data is currently ongoing (after the start edge have been detected until a complete byte, including all stop bits, has been received by the shift register). In IDLE_Line mode the Busy signal also stays set during the idle time generation."]
# [inline (always)]
pub fn stat_busy (& self) -> STAT_BUSY_R { STAT_BUSY_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_rxfe (& self) -> STAT_RXFE_R { STAT_RXFE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_rxff (& self) -> STAT_RXFF_R { STAT_RXFF_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 6 - UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_txfe (& self) -> STAT_TXFE_R { STAT_TXFE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the CTL0 register."]
# [inline (always)]
pub fn stat_txff (& self) -> STAT_TXFF_R { STAT_TXFF_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Clear To Send"]
# [inline (always)]
pub fn stat_cts (& self) -> STAT_CTS_R { STAT_CTS_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - IDLE mode has been detected in Idleline-Mulitprocessor-Mode. The IDLE bit is used as an address tag for each block of characters. In idle-line multiprocessor format, this bit is set when a received character is an address."]
# [inline (always)]
pub fn stat_idle (& self) -> STAT_IDLE_R { STAT_IDLE_R :: new (((self . bits >> 9) & 1) != 0) } } # [doc = "UART Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IFLS (rw) register accessor: UART Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifls`]
module"]
pub type IFLS = crate :: Reg < ifls :: IFLS_SPEC > ; # [doc = "UART Interrupt FIFO Level Select Register"]
pub mod ifls { # [doc = "Register `IFLS` reader"]
pub type R = crate :: R < IFLS_SPEC > ; # [doc = "Register `IFLS` writer"]
pub type W = crate :: W < IFLS_SPEC > ; # [doc = "Field `IFLS_TXIFLSEL` reader - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
pub type IFLS_TXIFLSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_TXIFLSEL` writer - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
pub type IFLS_TXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `IFLS_RXIFLSEL` reader - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
pub type IFLS_RXIFLSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_RXIFLSEL` writer - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
pub type IFLS_RXIFLSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `IFLS_RXTOSEL` reader - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
pub type IFLS_RXTOSEL_R = crate :: FieldReader ; # [doc = "Field `IFLS_RXTOSEL` writer - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
pub type IFLS_RXTOSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bits 0:2 - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
# [inline (always)]
pub fn ifls_txiflsel (& self) -> IFLS_TXIFLSEL_R { IFLS_TXIFLSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
# [inline (always)]
pub fn ifls_rxiflsel (& self) -> IFLS_RXIFLSEL_R { IFLS_RXIFLSEL_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:11 - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
# [inline (always)]
pub fn ifls_rxtosel (& self) -> IFLS_RXTOSEL_R { IFLS_RXTOSEL_R :: new (((self . bits >> 8) & 0x0f) as u8) } } impl W { # [doc = "Bits 0:2 - UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Note: for undefined settings the default configuration is used."]
# [inline (always)]
# [must_use]
pub fn ifls_txiflsel (& mut self) -> IFLS_TXIFLSEL_W < IFLS_SPEC , 0 > { IFLS_TXIFLSEL_W :: new (self) } # [doc = "Bits 4:6 - UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Note: In ULP domain the trigger levels are used for: 0: LVL_1_4 4: LVL_FULL For undefined settings the default configuration is used."]
# [inline (always)]
# [must_use]
pub fn ifls_rxiflsel (& mut self) -> IFLS_RXIFLSEL_W < IFLS_SPEC , 4 > { IFLS_RXIFLSEL_W :: new (self) } # [doc = "Bits 8:11 - UART Receive Interrupt Timeout Select. When receiving no start edge for an additional character within the set bittimes a RX interrupt is set even if the FIFO level is not reached. A value of 0 disables this function."]
# [inline (always)]
# [must_use]
pub fn ifls_rxtosel (& mut self) -> IFLS_RXTOSEL_W < IFLS_SPEC , 8 > { IFLS_RXTOSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Interrupt FIFO Level Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifls::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifls::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IFLS_SPEC ; impl crate :: RegisterSpec for IFLS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifls::R`](R) reader structure"]
impl crate :: Readable for IFLS_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifls::W`](W) writer structure"]
impl crate :: Writable for IFLS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFLS to value 0x22"]
impl crate :: Resettable for IFLS_SPEC { const RESET_VALUE : Self :: Ux = 0x22 ; } } # [doc = "IBRD (rw) register accessor: UART Integer Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ibrd`]
module"]
pub type IBRD = crate :: Reg < ibrd :: IBRD_SPEC > ; # [doc = "UART Integer Baud-Rate Divisor Register"]
pub mod ibrd { # [doc = "Register `IBRD` reader"]
pub type R = crate :: R < IBRD_SPEC > ; # [doc = "Register `IBRD` writer"]
pub type W = crate :: W < IBRD_SPEC > ; # [doc = "Field `IBRD_DIVINT` reader - Integer Baud-Rate Divisor"]
pub type IBRD_DIVINT_R = crate :: FieldReader < u16 > ; # [doc = "Field `IBRD_DIVINT` writer - Integer Baud-Rate Divisor"]
pub type IBRD_DIVINT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Integer Baud-Rate Divisor"]
# [inline (always)]
pub fn ibrd_divint (& self) -> IBRD_DIVINT_R { IBRD_DIVINT_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Integer Baud-Rate Divisor"]
# [inline (always)]
# [must_use]
pub fn ibrd_divint (& mut self) -> IBRD_DIVINT_W < IBRD_SPEC , 0 > { IBRD_DIVINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Integer Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ibrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ibrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IBRD_SPEC ; impl crate :: RegisterSpec for IBRD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ibrd::R`](R) reader structure"]
impl crate :: Readable for IBRD_SPEC { } # [doc = "`write(|w| ..)` method takes [`ibrd::W`](W) writer structure"]
impl crate :: Writable for IBRD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IBRD to value 0"]
impl crate :: Resettable for IBRD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FBRD (rw) register accessor: UART Fractional Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fbrd`]
module"]
pub type FBRD = crate :: Reg < fbrd :: FBRD_SPEC > ; # [doc = "UART Fractional Baud-Rate Divisor Register"]
pub mod fbrd { # [doc = "Register `FBRD` reader"]
pub type R = crate :: R < FBRD_SPEC > ; # [doc = "Register `FBRD` writer"]
pub type W = crate :: W < FBRD_SPEC > ; # [doc = "Field `FBRD_DIVFRAC` reader - Fractional Baud-Rate Divisor"]
pub type FBRD_DIVFRAC_R = crate :: FieldReader ; # [doc = "Field `FBRD_DIVFRAC` writer - Fractional Baud-Rate Divisor"]
pub type FBRD_DIVFRAC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O > ; impl R { # [doc = "Bits 0:5 - Fractional Baud-Rate Divisor"]
# [inline (always)]
pub fn fbrd_divfrac (& self) -> FBRD_DIVFRAC_R { FBRD_DIVFRAC_R :: new ((self . bits & 0x3f) as u8) } } impl W { # [doc = "Bits 0:5 - Fractional Baud-Rate Divisor"]
# [inline (always)]
# [must_use]
pub fn fbrd_divfrac (& mut self) -> FBRD_DIVFRAC_W < FBRD_SPEC , 0 > { FBRD_DIVFRAC_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Fractional Baud-Rate Divisor Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fbrd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fbrd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FBRD_SPEC ; impl crate :: RegisterSpec for FBRD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fbrd::R`](R) reader structure"]
impl crate :: Readable for FBRD_SPEC { } # [doc = "`write(|w| ..)` method takes [`fbrd::W`](W) writer structure"]
impl crate :: Writable for FBRD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FBRD to value 0"]
impl crate :: Resettable for FBRD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GFCTL (rw) register accessor: Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gfctl`]
module"]
pub type GFCTL = crate :: Reg < gfctl :: GFCTL_SPEC > ; # [doc = "Glitch Filter Control"]
pub mod gfctl { # [doc = "Register `GFCTL` reader"]
pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"]
pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"]
GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"]
GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)]
fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"]
GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"]
GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"]
GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"]
GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)]
fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } impl R { # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
# [inline (always)]
pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } } impl W { # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on the RX line. See device datasheet for exact values. (ULP UART only)"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"]
impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"]
impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"]
impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TXDATA (rw) register accessor: UART Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdata::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txdata`]
module"]
pub type TXDATA = crate :: Reg < txdata :: TXDATA_SPEC > ; # [doc = "UART Transmit Data Register"]
pub mod txdata { # [doc = "Register `TXDATA` reader"]
pub type R = crate :: R < TXDATA_SPEC > ; # [doc = "Register `TXDATA` writer"]
pub type W = crate :: W < TXDATA_SPEC > ; # [doc = "Field `TXDATA_DATA` reader - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
pub type TXDATA_DATA_R = crate :: FieldReader ; # [doc = "Field `TXDATA_DATA` writer - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
pub type TXDATA_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
# [inline (always)]
pub fn txdata_data (& self) -> TXDATA_DATA_R { TXDATA_DATA_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
# [inline (always)]
# [must_use]
pub fn txdata_data (& mut self) -> TXDATA_DATA_W < TXDATA_SPEC , 0 > { TXDATA_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "UART Transmit Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TXDATA_SPEC ; impl crate :: RegisterSpec for TXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`txdata::R`](R) reader structure"]
impl crate :: Readable for TXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`txdata::W`](W) writer structure"]
impl crate :: Writable for TXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TXDATA to value 0"]
impl crate :: Resettable for TXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RXDATA (r) register accessor: UART Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxdata`]
module"]
pub type RXDATA = crate :: Reg < rxdata :: RXDATA_SPEC > ; # [doc = "UART Receive Data Register"]
pub mod rxdata { # [doc = "Register `RXDATA` reader"]
pub type R = crate :: R < RXDATA_SPEC > ; # [doc = "Field `RXDATA_DATA` reader - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
pub type RXDATA_DATA_R = crate :: FieldReader ; # [doc = "Field `RXDATA_FRMERR` reader - UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO."]
pub type RXDATA_FRMERR_R = crate :: BitReader < RXDATA_FRMERR_A > ; # [doc = "UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_FRMERR_A { # [doc = "0: CLR"]
RXDATA_FRMERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_FRMERR_SET = 1 , } impl From < RXDATA_FRMERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_FRMERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_FRMERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_FRMERR_A { match self . bits { false => RXDATA_FRMERR_A :: RXDATA_FRMERR_CLR , true => RXDATA_FRMERR_A :: RXDATA_FRMERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_frmerr_clr (& self) -> bool { * self == RXDATA_FRMERR_A :: RXDATA_FRMERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_frmerr_set (& self) -> bool { * self == RXDATA_FRMERR_A :: RXDATA_FRMERR_SET } } # [doc = "Field `RXDATA_PARERR` reader - UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register."]
pub type RXDATA_PARERR_R = crate :: BitReader < RXDATA_PARERR_A > ; # [doc = "UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_PARERR_A { # [doc = "0: CLR"]
RXDATA_PARERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_PARERR_SET = 1 , } impl From < RXDATA_PARERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_PARERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_PARERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_PARERR_A { match self . bits { false => RXDATA_PARERR_A :: RXDATA_PARERR_CLR , true => RXDATA_PARERR_A :: RXDATA_PARERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_parerr_clr (& self) -> bool { * self == RXDATA_PARERR_A :: RXDATA_PARERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_parerr_set (& self) -> bool { * self == RXDATA_PARERR_A :: RXDATA_PARERR_SET } } # [doc = "Field `RXDATA_BRKERR` reader - UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
pub type RXDATA_BRKERR_R = crate :: BitReader < RXDATA_BRKERR_A > ; # [doc = "UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_BRKERR_A { # [doc = "0: CLR"]
RXDATA_BRKERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_BRKERR_SET = 1 , } impl From < RXDATA_BRKERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_BRKERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_BRKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_BRKERR_A { match self . bits { false => RXDATA_BRKERR_A :: RXDATA_BRKERR_CLR , true => RXDATA_BRKERR_A :: RXDATA_BRKERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_brkerr_clr (& self) -> bool { * self == RXDATA_BRKERR_A :: RXDATA_BRKERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_brkerr_set (& self) -> bool { * self == RXDATA_BRKERR_A :: RXDATA_BRKERR_SET } } # [doc = "Field `RXDATA_OVRERR` reader - UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO."]
pub type RXDATA_OVRERR_R = crate :: BitReader < RXDATA_OVRERR_A > ; # [doc = "UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_OVRERR_A { # [doc = "0: CLR"]
RXDATA_OVRERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_OVRERR_SET = 1 , } impl From < RXDATA_OVRERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_OVRERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_OVRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_OVRERR_A { match self . bits { false => RXDATA_OVRERR_A :: RXDATA_OVRERR_CLR , true => RXDATA_OVRERR_A :: RXDATA_OVRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_ovrerr_clr (& self) -> bool { * self == RXDATA_OVRERR_A :: RXDATA_OVRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_ovrerr_set (& self) -> bool { * self == RXDATA_OVRERR_A :: RXDATA_OVRERR_SET } } # [doc = "Field `RXDATA_NERR` reader - Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register."]
pub type RXDATA_NERR_R = crate :: BitReader < RXDATA_NERR_A > ; # [doc = "Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXDATA_NERR_A { # [doc = "0: CLR"]
RXDATA_NERR_CLR = 0 , # [doc = "1: SET"]
RXDATA_NERR_SET = 1 , } impl From < RXDATA_NERR_A > for bool { # [inline (always)]
fn from (variant : RXDATA_NERR_A) -> Self { variant as u8 != 0 } } impl RXDATA_NERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXDATA_NERR_A { match self . bits { false => RXDATA_NERR_A :: RXDATA_NERR_CLR , true => RXDATA_NERR_A :: RXDATA_NERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_rxdata_nerr_clr (& self) -> bool { * self == RXDATA_NERR_A :: RXDATA_NERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_rxdata_nerr_set (& self) -> bool { * self == RXDATA_NERR_A :: RXDATA_NERR_SET } } impl R { # [doc = "Bits 0:7 - Data Transmitted or Received Data that is to be transmitted via the UART is written to this field. When read, this field contains the data that was received by the UART."]
# [inline (always)]
pub fn rxdata_data (& self) -> RXDATA_DATA_R { RXDATA_DATA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 8 - UART Framing Error Writing to this bit has no effect. The flag is cleared by writing 1 to the FRMERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO."]
# [inline (always)]
pub fn rxdata_frmerr (& self) -> RXDATA_FRMERR_R { RXDATA_FRMERR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - UART Parity Error Writing to this bit has no effect. The flag is cleared by writing 1 to the PARERR bit in the UART EVENT ICLR register."]
# [inline (always)]
pub fn rxdata_parerr (& self) -> RXDATA_PARERR_R { RXDATA_PARERR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - UART Break Error Writing to this bit has no effect. The flag is cleared by writing 1 to the BRKERR bit in the UART EVENT ICLR register. This error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received."]
# [inline (always)]
pub fn rxdata_brkerr (& self) -> RXDATA_BRKERR_R { RXDATA_BRKERR_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - UART Receive Overrun Error Writing to this bit has no effect. The flag is cleared by writing 1 to the OVRERR bit in the UART EVENT ICLR register. In case of a receive FIFO overflow, the FIFO contents remain valid because no further data is written when the FIFO is full. Only the contents of the shift register are overwritten. The CPU must read the data in order to empty the FIFO."]
# [inline (always)]
pub fn rxdata_ovrerr (& self) -> RXDATA_OVRERR_R { RXDATA_OVRERR_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Noise Error. Writing to this bit has no effect. The flag is cleared by writing 1 to the NERR bit in the UART EVENT ICLR register."]
# [inline (always)]
pub fn rxdata_nerr (& self) -> RXDATA_NERR_R { RXDATA_NERR_R :: new (((self . bits >> 12) & 1) != 0) } } # [doc = "UART Receive Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RXDATA_SPEC ; impl crate :: RegisterSpec for RXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rxdata::R`](R) reader structure"]
impl crate :: Readable for RXDATA_SPEC { } # [doc = "`reset()` method sets RXDATA to value 0"]
impl crate :: Resettable for RXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "AMASK (rw) register accessor: Self Address Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@amask`]
module"]
pub type AMASK = crate :: Reg < amask :: AMASK_SPEC > ; # [doc = "Self Address Mask Register"]
pub mod amask { # [doc = "Register `AMASK` reader"]
pub type R = crate :: R < AMASK_SPEC > ; # [doc = "Register `AMASK` writer"]
pub type W = crate :: W < AMASK_SPEC > ; # [doc = "Field `AMASK_VALUE` reader - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
pub type AMASK_VALUE_R = crate :: FieldReader ; # [doc = "Field `AMASK_VALUE` writer - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
pub type AMASK_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
# [inline (always)]
pub fn amask_value (& self) -> AMASK_VALUE_R { AMASK_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Self Address Mask for 9-Bit Mode This field contains the address mask that creates a set of addresses that should be matched. A 0 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register is don't care. A 1 bit in the MSK bitfield configures, that the corresponding bit in the ADDR bitfield of the UART9BITADDR register must match."]
# [inline (always)]
# [must_use]
pub fn amask_value (& mut self) -> AMASK_VALUE_W < AMASK_SPEC , 0 > { AMASK_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Self Address Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`amask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`amask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct AMASK_SPEC ; impl crate :: RegisterSpec for AMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`amask::R`](R) reader structure"]
impl crate :: Readable for AMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`amask::W`](W) writer structure"]
impl crate :: Writable for AMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets AMASK to value 0xff"]
impl crate :: Resettable for AMASK_SPEC { const RESET_VALUE : Self :: Ux = 0xff ; } } # [doc = "ADDR (rw) register accessor: Self Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
module"]
pub type ADDR = crate :: Reg < addr :: ADDR_SPEC > ; # [doc = "Self Address Register"]
pub mod addr { # [doc = "Register `ADDR` reader"]
pub type R = crate :: R < ADDR_SPEC > ; # [doc = "Register `ADDR` writer"]
pub type W = crate :: W < ADDR_SPEC > ; # [doc = "Field `ADDR_VALUE` reader - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
pub type ADDR_VALUE_R = crate :: FieldReader ; # [doc = "Field `ADDR_VALUE` writer - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
pub type ADDR_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
# [inline (always)]
pub fn addr_value (& self) -> ADDR_VALUE_R { ADDR_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Self Address for 9-Bit Mode This field contains the address that should be matched when UART9BITAMASK is FFh."]
# [inline (always)]
# [must_use]
pub fn addr_value (& mut self) -> ADDR_VALUE_W < ADDR_SPEC , 0 > { ADDR_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Self Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ADDR_SPEC ; impl crate :: RegisterSpec for ADDR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`addr::R`](R) reader structure"]
impl crate :: Readable for ADDR_SPEC { } # [doc = "`write(|w| ..)` method takes [`addr::W`](W) writer structure"]
impl crate :: Writable for ADDR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ADDR to value 0"]
impl crate :: Resettable for ADDR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "WWDT"]
pub struct WWDT0 { _marker : PhantomData < * const () > } unsafe impl Send for WWDT0 { } impl WWDT0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const wwdt0 :: RegisterBlock = 0x4008_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const wwdt0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for WWDT0 { type Target = wwdt0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for WWDT0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("WWDT0") . finish () } } # [doc = "WWDT"]
pub mod wwdt0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved2 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved3 : [u8 ; 0x0800]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved4 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved6 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved10 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved11 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - Window Watchdog Timer Control Register 0"]
pub wwdtctl0 : WWDTCTL0 , # [doc = "0x1104 - Window Watchdog Timer Control Register 0"]
pub wwdtctl1 : WWDTCTL1 , # [doc = "0x1108 - Window Watchdog Timer Counter Reset Register"]
pub wwdtcntrst : WWDTCNTRST , # [doc = "0x110c - Window Watchdog Timer Status Register"]
pub wwdtstat : WWDTSTAT , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power Note: For safety devices the power cannot be disabled once enabled."]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power Note: For safety devices the power cannot be disabled once enabled.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power Note: For safety devices the power cannot be disabled once enabled."]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power Note: For safety devices the power cannot be disabled once enabled."]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power Note: For safety devices the power cannot be disabled once enabled."]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible."]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear \\[GPRCM.STAT.RESETSTKY\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear \\[GPRCM.STAT.RESETSTKY\\]"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral Note: For safety devices a watchdog reset by software is not possible."]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear \\[GPRCM.STAT.RESETSTKY\\]"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC."]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: INTTIM"]
IIDX_STAT_INTTIM = 1 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_INTTIM) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "INTTIM"]
# [inline (always)]
pub fn is_iidx_stat_inttim (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_INTTIM } } impl R { # [doc = "Bits 0:4 - Module Interrupt Vector Value. This register provides the highest priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC."]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 0x1f) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_INTTIM` reader - Interval Timer Interrupt."]
pub type IMASK_INTTIM_R = crate :: BitReader < IMASK_INTTIM_A > ; # [doc = "Interval Timer Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_INTTIM_A { # [doc = "0: CLR"]
IMASK_INTTIM_CLR = 0 , # [doc = "1: SET"]
IMASK_INTTIM_SET = 1 , } impl From < IMASK_INTTIM_A > for bool { # [inline (always)]
fn from (variant : IMASK_INTTIM_A) -> Self { variant as u8 != 0 } } impl IMASK_INTTIM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_INTTIM_A { match self . bits { false => IMASK_INTTIM_A :: IMASK_INTTIM_CLR , true => IMASK_INTTIM_A :: IMASK_INTTIM_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_inttim_clr (& self) -> bool { * self == IMASK_INTTIM_A :: IMASK_INTTIM_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_inttim_set (& self) -> bool { * self == IMASK_INTTIM_A :: IMASK_INTTIM_SET } } # [doc = "Field `IMASK_INTTIM` writer - Interval Timer Interrupt."]
pub type IMASK_INTTIM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_INTTIM_A > ; impl < 'a , REG , const O : u8 > IMASK_INTTIM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_inttim_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_INTTIM_A :: IMASK_INTTIM_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_inttim_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_INTTIM_A :: IMASK_INTTIM_SET) } } impl R { # [doc = "Bit 0 - Interval Timer Interrupt."]
# [inline (always)]
pub fn imask_inttim (& self) -> IMASK_INTTIM_R { IMASK_INTTIM_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Interval Timer Interrupt."]
# [inline (always)]
# [must_use]
pub fn imask_inttim (& mut self) -> IMASK_INTTIM_W < IMASK_SPEC , 0 > { IMASK_INTTIM_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_INTTIM` reader - Interval Timer Interrupt."]
pub type RIS_INTTIM_R = crate :: BitReader < RIS_INTTIM_A > ; # [doc = "Interval Timer Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_INTTIM_A { # [doc = "0: CLR"]
RIS_INTTIM_CLR = 0 , # [doc = "1: SET"]
RIS_INTTIM_SET = 1 , } impl From < RIS_INTTIM_A > for bool { # [inline (always)]
fn from (variant : RIS_INTTIM_A) -> Self { variant as u8 != 0 } } impl RIS_INTTIM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_INTTIM_A { match self . bits { false => RIS_INTTIM_A :: RIS_INTTIM_CLR , true => RIS_INTTIM_A :: RIS_INTTIM_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_inttim_clr (& self) -> bool { * self == RIS_INTTIM_A :: RIS_INTTIM_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_inttim_set (& self) -> bool { * self == RIS_INTTIM_A :: RIS_INTTIM_SET } } impl R { # [doc = "Bit 0 - Interval Timer Interrupt."]
# [inline (always)]
pub fn ris_inttim (& self) -> RIS_INTTIM_R { RIS_INTTIM_R :: new ((self . bits & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_INTTIM` reader - Interval Timer Interrupt."]
pub type MIS_INTTIM_R = crate :: BitReader < MIS_INTTIM_A > ; # [doc = "Interval Timer Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_INTTIM_A { # [doc = "0: CLR"]
MIS_INTTIM_CLR = 0 , # [doc = "1: SET"]
MIS_INTTIM_SET = 1 , } impl From < MIS_INTTIM_A > for bool { # [inline (always)]
fn from (variant : MIS_INTTIM_A) -> Self { variant as u8 != 0 } } impl MIS_INTTIM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_INTTIM_A { match self . bits { false => MIS_INTTIM_A :: MIS_INTTIM_CLR , true => MIS_INTTIM_A :: MIS_INTTIM_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_inttim_clr (& self) -> bool { * self == MIS_INTTIM_A :: MIS_INTTIM_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_inttim_set (& self) -> bool { * self == MIS_INTTIM_A :: MIS_INTTIM_SET } } impl R { # [doc = "Bit 0 - Interval Timer Interrupt."]
# [inline (always)]
pub fn mis_inttim (& self) -> MIS_INTTIM_R { MIS_INTTIM_R :: new ((self . bits & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Interval Timer Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_INTTIM_AW { # [doc = "0: NO_EFFECT"]
ISET_INTTIM_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_INTTIM_SET = 1 , } impl From < ISET_INTTIM_AW > for bool { # [inline (always)]
fn from (variant : ISET_INTTIM_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_INTTIM` writer - Interval Timer Interrupt."]
pub type ISET_INTTIM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_INTTIM_AW > ; impl < 'a , REG , const O : u8 > ISET_INTTIM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_inttim_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_INTTIM_AW :: ISET_INTTIM_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_inttim_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_INTTIM_AW :: ISET_INTTIM_SET) } } impl W { # [doc = "Bit 0 - Interval Timer Interrupt."]
# [inline (always)]
# [must_use]
pub fn iset_inttim (& mut self) -> ISET_INTTIM_W < ISET_SPEC , 0 > { ISET_INTTIM_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Interval Timer Interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_INTTIM_AW { # [doc = "0: NO_EFFECT"]
ICLR_INTTIM_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_INTTIM_CLR = 1 , } impl From < ICLR_INTTIM_AW > for bool { # [inline (always)]
fn from (variant : ICLR_INTTIM_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_INTTIM` writer - Interval Timer Interrupt."]
pub type ICLR_INTTIM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_INTTIM_AW > ; impl < 'a , REG , const O : u8 > ICLR_INTTIM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_inttim_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_INTTIM_AW :: ICLR_INTTIM_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_inttim_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_INTTIM_AW :: ICLR_INTTIM_CLR) } } impl W { # [doc = "Bit 0 - Interval Timer Interrupt."]
# [inline (always)]
# [must_use]
pub fn iclr_inttim (& mut self) -> ICLR_INTTIM_W < ICLR_SPEC , 0 > { ICLR_INTTIM_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "WWDTCTL0 (rw) register accessor: Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wwdtctl0`]
module"]
pub type WWDTCTL0 = crate :: Reg < wwdtctl0 :: WWDTCTL0_SPEC > ; # [doc = "Window Watchdog Timer Control Register 0"]
pub mod wwdtctl0 { # [doc = "Register `WWDTCTL0` reader"]
pub type R = crate :: R < WWDTCTL0_SPEC > ; # [doc = "Register `WWDTCTL0` writer"]
pub type W = crate :: W < WWDTCTL0_SPEC > ; # [doc = "Field `WWDTCTL0_CLKDIV` reader - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."]
pub type WWDTCTL0_CLKDIV_R = crate :: FieldReader ; # [doc = "Field `WWDTCTL0_CLKDIV` writer - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."]
pub type WWDTCTL0_CLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `WWDTCTL0_PER` reader - Timer Period of the WWDT. These bits select the total watchdog timer count."]
pub type WWDTCTL0_PER_R = crate :: FieldReader < WWDTCTL0_PER_A > ; # [doc = "Timer Period of the WWDT. These bits select the total watchdog timer count.\n\nValue on reset: 4"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum WWDTCTL0_PER_A { # [doc = "0: EN_25"]
WWDTCTL0_PER_EN_25 = 0 , # [doc = "1: EN_21"]
WWDTCTL0_PER_EN_21 = 1 , # [doc = "2: EN_18"]
WWDTCTL0_PER_EN_18 = 2 , # [doc = "3: EN_15"]
WWDTCTL0_PER_EN_15 = 3 , # [doc = "4: EN_12"]
WWDTCTL0_PER_EN_12 = 4 , # [doc = "5: EN_10"]
WWDTCTL0_PER_EN_10 = 5 , # [doc = "6: EN_8"]
WWDTCTL0_PER_EN_8 = 6 , # [doc = "7: EN_6"]
WWDTCTL0_PER_EN_6 = 7 , } impl From < WWDTCTL0_PER_A > for u8 { # [inline (always)]
fn from (variant : WWDTCTL0_PER_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_PER_A { type Ux = u8 ; } impl WWDTCTL0_PER_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WWDTCTL0_PER_A { match self . bits { 0 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 , 1 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 , 2 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 , 3 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 , 4 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 , 5 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 , 6 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 , 7 => WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 , _ => unreachable ! () , } } # [doc = "EN_25"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_25 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25 } # [doc = "EN_21"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_21 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21 } # [doc = "EN_18"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_18 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18 } # [doc = "EN_15"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_15 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15 } # [doc = "EN_12"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_12 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12 } # [doc = "EN_10"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_10 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10 } # [doc = "EN_8"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_8 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8 } # [doc = "EN_6"]
# [inline (always)]
pub fn is_wwdtctl0_per_en_6 (& self) -> bool { * self == WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6 } } # [doc = "Field `WWDTCTL0_PER` writer - Timer Period of the WWDT. These bits select the total watchdog timer count."]
pub type WWDTCTL0_PER_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_PER_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_PER_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "EN_25"]
# [inline (always)]
pub fn wwdtctl0_per_en_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_25) } # [doc = "EN_21"]
# [inline (always)]
pub fn wwdtctl0_per_en_21 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_21) } # [doc = "EN_18"]
# [inline (always)]
pub fn wwdtctl0_per_en_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_18) } # [doc = "EN_15"]
# [inline (always)]
pub fn wwdtctl0_per_en_15 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_15) } # [doc = "EN_12"]
# [inline (always)]
pub fn wwdtctl0_per_en_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_12) } # [doc = "EN_10"]
# [inline (always)]
pub fn wwdtctl0_per_en_10 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_10) } # [doc = "EN_8"]
# [inline (always)]
pub fn wwdtctl0_per_en_8 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_8) } # [doc = "EN_6"]
# [inline (always)]
pub fn wwdtctl0_per_en_6 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_PER_A :: WWDTCTL0_PER_EN_6) } } # [doc = "Field `WWDTCTL0_WINDOW0` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
pub type WWDTCTL0_WINDOW0_R = crate :: FieldReader < WWDTCTL0_WINDOW0_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum WWDTCTL0_WINDOW0_A { # [doc = "0: SIZE_0"]
WWDTCTL0_WINDOW0_SIZE_0 = 0 , # [doc = "1: SIZE_12"]
WWDTCTL0_WINDOW0_SIZE_12 = 1 , # [doc = "2: SIZE_18"]
WWDTCTL0_WINDOW0_SIZE_18 = 2 , # [doc = "3: SIZE_25"]
WWDTCTL0_WINDOW0_SIZE_25 = 3 , # [doc = "4: SIZE_50"]
WWDTCTL0_WINDOW0_SIZE_50 = 4 , # [doc = "5: SIZE_75"]
WWDTCTL0_WINDOW0_SIZE_75 = 5 , # [doc = "6: SIZE_81"]
WWDTCTL0_WINDOW0_SIZE_81 = 6 , # [doc = "7: SIZE_87"]
WWDTCTL0_WINDOW0_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW0_A > for u8 { # [inline (always)]
fn from (variant : WWDTCTL0_WINDOW0_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW0_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WWDTCTL0_WINDOW0_A { match self . bits { 0 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 , 1 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 , 2 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 , 3 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 , 4 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 , 5 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 , 6 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 , 7 => WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0 } # [doc = "SIZE_12"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12 } # [doc = "SIZE_18"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18 } # [doc = "SIZE_25"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25 } # [doc = "SIZE_50"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50 } # [doc = "SIZE_75"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75 } # [doc = "SIZE_81"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81 } # [doc = "SIZE_87"]
# [inline (always)]
pub fn is_wwdtctl0_window0_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW0` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
pub type WWDTCTL0_WINDOW0_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW0_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"]
# [inline (always)]
pub fn wwdtctl0_window0_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_0) } # [doc = "SIZE_12"]
# [inline (always)]
pub fn wwdtctl0_window0_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_12) } # [doc = "SIZE_18"]
# [inline (always)]
pub fn wwdtctl0_window0_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_18) } # [doc = "SIZE_25"]
# [inline (always)]
pub fn wwdtctl0_window0_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_25) } # [doc = "SIZE_50"]
# [inline (always)]
pub fn wwdtctl0_window0_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_50) } # [doc = "SIZE_75"]
# [inline (always)]
pub fn wwdtctl0_window0_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_75) } # [doc = "SIZE_81"]
# [inline (always)]
pub fn wwdtctl0_window0_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_81) } # [doc = "SIZE_87"]
# [inline (always)]
pub fn wwdtctl0_window0_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW0_A :: WWDTCTL0_WINDOW0_SIZE_87) } } # [doc = "Field `WWDTCTL0_WINDOW1` reader - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
pub type WWDTCTL0_WINDOW1_R = crate :: FieldReader < WWDTCTL0_WINDOW1_A > ; # [doc = "Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum WWDTCTL0_WINDOW1_A { # [doc = "0: SIZE_0"]
WWDTCTL0_WINDOW1_SIZE_0 = 0 , # [doc = "1: SIZE_12"]
WWDTCTL0_WINDOW1_SIZE_12 = 1 , # [doc = "2: SIZE_18"]
WWDTCTL0_WINDOW1_SIZE_18 = 2 , # [doc = "3: SIZE_25"]
WWDTCTL0_WINDOW1_SIZE_25 = 3 , # [doc = "4: SIZE_50"]
WWDTCTL0_WINDOW1_SIZE_50 = 4 , # [doc = "5: SIZE_75"]
WWDTCTL0_WINDOW1_SIZE_75 = 5 , # [doc = "6: SIZE_81"]
WWDTCTL0_WINDOW1_SIZE_81 = 6 , # [doc = "7: SIZE_87"]
WWDTCTL0_WINDOW1_SIZE_87 = 7 , } impl From < WWDTCTL0_WINDOW1_A > for u8 { # [inline (always)]
fn from (variant : WWDTCTL0_WINDOW1_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_WINDOW1_A { type Ux = u8 ; } impl WWDTCTL0_WINDOW1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WWDTCTL0_WINDOW1_A { match self . bits { 0 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 , 1 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 , 2 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 , 3 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 , 4 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 , 5 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 , 6 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 , 7 => WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 , _ => unreachable ! () , } } # [doc = "SIZE_0"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_0 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0 } # [doc = "SIZE_12"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_12 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12 } # [doc = "SIZE_18"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_18 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18 } # [doc = "SIZE_25"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_25 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25 } # [doc = "SIZE_50"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_50 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50 } # [doc = "SIZE_75"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_75 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75 } # [doc = "SIZE_81"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_81 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81 } # [doc = "SIZE_87"]
# [inline (always)]
pub fn is_wwdtctl0_window1_size_87 (& self) -> bool { * self == WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87 } } # [doc = "Field `WWDTCTL0_WINDOW1` writer - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
pub type WWDTCTL0_WINDOW1_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , WWDTCTL0_WINDOW1_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_WINDOW1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SIZE_0"]
# [inline (always)]
pub fn wwdtctl0_window1_size_0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_0) } # [doc = "SIZE_12"]
# [inline (always)]
pub fn wwdtctl0_window1_size_12 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_12) } # [doc = "SIZE_18"]
# [inline (always)]
pub fn wwdtctl0_window1_size_18 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_18) } # [doc = "SIZE_25"]
# [inline (always)]
pub fn wwdtctl0_window1_size_25 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_25) } # [doc = "SIZE_50"]
# [inline (always)]
pub fn wwdtctl0_window1_size_50 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_50) } # [doc = "SIZE_75"]
# [inline (always)]
pub fn wwdtctl0_window1_size_75 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_75) } # [doc = "SIZE_81"]
# [inline (always)]
pub fn wwdtctl0_window1_size_81 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_81) } # [doc = "SIZE_87"]
# [inline (always)]
pub fn wwdtctl0_window1_size_87 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_WINDOW1_A :: WWDTCTL0_WINDOW1_SIZE_87) } } # [doc = "Field `WWDTCTL0_MODE` reader - Window Watchdog Timer Mode"]
pub type WWDTCTL0_MODE_R = crate :: BitReader < WWDTCTL0_MODE_A > ; # [doc = "Window Watchdog Timer Mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum WWDTCTL0_MODE_A { # [doc = "0: WINDOW"]
WWDTCTL0_MODE_WINDOW = 0 , # [doc = "1: INTERVAL"]
WWDTCTL0_MODE_INTERVAL = 1 , } impl From < WWDTCTL0_MODE_A > for bool { # [inline (always)]
fn from (variant : WWDTCTL0_MODE_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_MODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WWDTCTL0_MODE_A { match self . bits { false => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW , true => WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL , } } # [doc = "WINDOW"]
# [inline (always)]
pub fn is_wwdtctl0_mode_window (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW } # [doc = "INTERVAL"]
# [inline (always)]
pub fn is_wwdtctl0_mode_interval (& self) -> bool { * self == WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL } } # [doc = "Field `WWDTCTL0_MODE` writer - Window Watchdog Timer Mode"]
pub type WWDTCTL0_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_MODE_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WINDOW"]
# [inline (always)]
pub fn wwdtctl0_mode_window (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_WINDOW) } # [doc = "INTERVAL"]
# [inline (always)]
pub fn wwdtctl0_mode_interval (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_MODE_A :: WWDTCTL0_MODE_INTERVAL) } } # [doc = "Field `WWDTCTL0_STISM` reader - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."]
pub type WWDTCTL0_STISM_R = crate :: BitReader < WWDTCTL0_STISM_A > ; # [doc = "Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum WWDTCTL0_STISM_A { # [doc = "0: CONT"]
WWDTCTL0_STISM_CONT = 0 , # [doc = "1: STOP"]
WWDTCTL0_STISM_STOP = 1 , } impl From < WWDTCTL0_STISM_A > for bool { # [inline (always)]
fn from (variant : WWDTCTL0_STISM_A) -> Self { variant as u8 != 0 } } impl WWDTCTL0_STISM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WWDTCTL0_STISM_A { match self . bits { false => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT , true => WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP , } } # [doc = "CONT"]
# [inline (always)]
pub fn is_wwdtctl0_stism_cont (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT } # [doc = "STOP"]
# [inline (always)]
pub fn is_wwdtctl0_stism_stop (& self) -> bool { * self == WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP } } # [doc = "Field `WWDTCTL0_STISM` writer - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."]
pub type WWDTCTL0_STISM_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL0_STISM_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_STISM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONT"]
# [inline (always)]
pub fn wwdtctl0_stism_cont (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_CONT) } # [doc = "STOP"]
# [inline (always)]
pub fn wwdtctl0_stism_stop (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_STISM_A :: WWDTCTL0_STISM_STOP) } } # [doc = "Field `WWDTCTL0_KEY` reader - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."]
pub type WWDTCTL0_KEY_R = crate :: FieldReader < WWDTCTL0_KEY_A > ; # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum WWDTCTL0_KEY_A { # [doc = "201: _TO_UNLOCK_W_"]
WWDTCTL0_KEY_UNLOCK_W = 201 , } impl From < WWDTCTL0_KEY_A > for u8 { # [inline (always)]
fn from (variant : WWDTCTL0_KEY_A) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL0_KEY_A { type Ux = u8 ; } impl WWDTCTL0_KEY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < WWDTCTL0_KEY_A > { match self . bits { 201 => Some (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) , _ => None , } } # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn is_wwdtctl0_key_unlock_w (& self) -> bool { * self == WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W } } # [doc = "Field `WWDTCTL0_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."]
pub type WWDTCTL0_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL0_KEY_A > ; impl < 'a , REG , const O : u8 > WWDTCTL0_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn wwdtctl0_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL0_KEY_A :: WWDTCTL0_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."]
# [inline (always)]
pub fn wwdtctl0_clkdiv (& self) -> WWDTCTL0_CLKDIV_R { WWDTCTL0_CLKDIV_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."]
# [inline (always)]
pub fn wwdtctl0_per (& self) -> WWDTCTL0_PER_R { WWDTCTL0_PER_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
# [inline (always)]
pub fn wwdtctl0_window0 (& self) -> WWDTCTL0_WINDOW0_R { WWDTCTL0_WINDOW0_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
# [inline (always)]
pub fn wwdtctl0_window1 (& self) -> WWDTCTL0_WINDOW1_R { WWDTCTL0_WINDOW1_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 16 - Window Watchdog Timer Mode"]
# [inline (always)]
pub fn wwdtctl0_mode (& self) -> WWDTCTL0_MODE_R { WWDTCTL0_MODE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."]
# [inline (always)]
pub fn wwdtctl0_stism (& self) -> WWDTCTL0_STISM_R { WWDTCTL0_STISM_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."]
# [inline (always)]
pub fn wwdtctl0_key (& self) -> WWDTCTL0_KEY_R { WWDTCTL0_KEY_R :: new (((self . bits >> 24) & 0xff) as u8) } } impl W { # [doc = "Bits 0:2 - Module Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible. The clock divider is currently 4 bits. Bit 4 has no effect and should always be written with 0."]
# [inline (always)]
# [must_use]
pub fn wwdtctl0_clkdiv (& mut self) -> WWDTCTL0_CLKDIV_W < WWDTCTL0_SPEC , 0 > { WWDTCTL0_CLKDIV_W :: new (self) } # [doc = "Bits 4:6 - Timer Period of the WWDT. These bits select the total watchdog timer count."]
# [inline (always)]
# [must_use]
pub fn wwdtctl0_per (& mut self) -> WWDTCTL0_PER_W < WWDTCTL0_SPEC , 4 > { WWDTCTL0_PER_W :: new (self) } # [doc = "Bits 8:10 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
# [inline (always)]
# [must_use]
pub fn wwdtctl0_window0 (& mut self) -> WWDTCTL0_WINDOW0_W < WWDTCTL0_SPEC , 8 > { WWDTCTL0_WINDOW0_W :: new (self) } # [doc = "Bits 12:14 - Closed window period in percentage of the timer interval. WWDTCTL1.WINSEL determines the active window setting (WWDTCTL0.WINDOW0 or WWDTCTL0.WINDOW1)."]
# [inline (always)]
# [must_use]
pub fn wwdtctl0_window1 (& mut self) -> WWDTCTL0_WINDOW1_W < WWDTCTL0_SPEC , 12 > { WWDTCTL0_WINDOW1_W :: new (self) } # [doc = "Bit 16 - Window Watchdog Timer Mode"]
# [inline (always)]
# [must_use]
pub fn wwdtctl0_mode (& mut self) -> WWDTCTL0_MODE_W < WWDTCTL0_SPEC , 16 > { WWDTCTL0_MODE_W :: new (self) } # [doc = "Bit 17 - Stop In Sleep Mode. The functionality of this bit requires that POLICY.HWCEN = 0. If POLICY.HWCEN = 1 the WWDT resets during sleep and needs re-configuration. Note: This bit has no effect for the global Window Watchdog as Sleep Mode is not supported."]
# [inline (always)]
# [must_use]
pub fn wwdtctl0_stism (& mut self) -> WWDTCTL0_STISM_W < WWDTCTL0_SPEC , 17 > { WWDTCTL0_STISM_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."]
# [inline (always)]
# [must_use]
pub fn wwdtctl0_key (& mut self) -> WWDTCTL0_KEY_W < WWDTCTL0_SPEC , 24 > { WWDTCTL0_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WWDTCTL0_SPEC ; impl crate :: RegisterSpec for WWDTCTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl0::R`](R) reader structure"]
impl crate :: Readable for WWDTCTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl0::W`](W) writer structure"]
impl crate :: Writable for WWDTCTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL0 to value 0x43"]
impl crate :: Resettable for WWDTCTL0_SPEC { const RESET_VALUE : Self :: Ux = 0x43 ; } } # [doc = "WWDTCTL1 (rw) register accessor: Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wwdtctl1`]
module"]
pub type WWDTCTL1 = crate :: Reg < wwdtctl1 :: WWDTCTL1_SPEC > ; # [doc = "Window Watchdog Timer Control Register 0"]
pub mod wwdtctl1 { # [doc = "Register `WWDTCTL1` reader"]
pub type R = crate :: R < WWDTCTL1_SPEC > ; # [doc = "Register `WWDTCTL1` writer"]
pub type W = crate :: W < WWDTCTL1_SPEC > ; # [doc = "Field `WWDTCTL1_WINSEL` reader - Close Window Select"]
pub type WWDTCTL1_WINSEL_R = crate :: BitReader < WWDTCTL1_WINSEL_A > ; # [doc = "Close Window Select\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum WWDTCTL1_WINSEL_A { # [doc = "0: WIN0"]
WWDTCTL1_WINSEL_WIN0 = 0 , # [doc = "1: WIN1"]
WWDTCTL1_WINSEL_WIN1 = 1 , } impl From < WWDTCTL1_WINSEL_A > for bool { # [inline (always)]
fn from (variant : WWDTCTL1_WINSEL_A) -> Self { variant as u8 != 0 } } impl WWDTCTL1_WINSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WWDTCTL1_WINSEL_A { match self . bits { false => WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0 , true => WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1 , } } # [doc = "WIN0"]
# [inline (always)]
pub fn is_wwdtctl1_winsel_win0 (& self) -> bool { * self == WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0 } # [doc = "WIN1"]
# [inline (always)]
pub fn is_wwdtctl1_winsel_win1 (& self) -> bool { * self == WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1 } } # [doc = "Field `WWDTCTL1_WINSEL` writer - Close Window Select"]
pub type WWDTCTL1_WINSEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WWDTCTL1_WINSEL_A > ; impl < 'a , REG , const O : u8 > WWDTCTL1_WINSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "WIN0"]
# [inline (always)]
pub fn wwdtctl1_winsel_win0 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN0) } # [doc = "WIN1"]
# [inline (always)]
pub fn wwdtctl1_winsel_win1 (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_WINSEL_A :: WWDTCTL1_WINSEL_WIN1) } } # [doc = "KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum WWDTCTL1_KEY_AW { # [doc = "190: _TO_UNLOCK_W_"]
WWDTCTL1_KEY_UNLOCK_W = 190 , } impl From < WWDTCTL1_KEY_AW > for u8 { # [inline (always)]
fn from (variant : WWDTCTL1_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for WWDTCTL1_KEY_AW { type Ux = u8 ; } # [doc = "Field `WWDTCTL1_KEY` writer - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."]
pub type WWDTCTL1_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , WWDTCTL1_KEY_AW > ; impl < 'a , REG , const O : u8 > WWDTCTL1_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn wwdtctl1_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (WWDTCTL1_KEY_AW :: WWDTCTL1_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Close Window Select"]
# [inline (always)]
pub fn wwdtctl1_winsel (& self) -> WWDTCTL1_WINSEL_R { WWDTCTL1_WINSEL_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Close Window Select"]
# [inline (always)]
# [must_use]
pub fn wwdtctl1_winsel (& mut self) -> WWDTCTL1_WINSEL_W < WWDTCTL1_SPEC , 0 > { WWDTCTL1_WINSEL_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow write access to this register. Writing to this register with an incorrect key activates the WWDT error signal to the ESM. Read as 0."]
# [inline (always)]
# [must_use]
pub fn wwdtctl1_key (& mut self) -> WWDTCTL1_KEY_W < WWDTCTL1_SPEC , 24 > { WWDTCTL1_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WWDTCTL1_SPEC ; impl crate :: RegisterSpec for WWDTCTL1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtctl1::R`](R) reader structure"]
impl crate :: Readable for WWDTCTL1_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtctl1::W`](W) writer structure"]
impl crate :: Writable for WWDTCTL1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCTL1 to value 0"]
impl crate :: Resettable for WWDTCTL1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "WWDTCNTRST (rw) register accessor: Window Watchdog Timer Counter Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtcntrst::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtcntrst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wwdtcntrst`]
module"]
pub type WWDTCNTRST = crate :: Reg < wwdtcntrst :: WWDTCNTRST_SPEC > ; # [doc = "Window Watchdog Timer Counter Reset Register"]
pub mod wwdtcntrst { # [doc = "Register `WWDTCNTRST` reader"]
pub type R = crate :: R < WWDTCNTRST_SPEC > ; # [doc = "Register `WWDTCNTRST` writer"]
pub type W = crate :: W < WWDTCNTRST_SPEC > ; # [doc = "Field `WWDTCNTRST_RESTART` reader - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."]
pub type WWDTCNTRST_RESTART_R = crate :: FieldReader < u32 > ; # [doc = "Field `WWDTCNTRST_RESTART` writer - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."]
pub type WWDTCNTRST_RESTART_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."]
# [inline (always)]
pub fn wwdtcntrst_restart (& self) -> WWDTCNTRST_RESTART_R { WWDTCNTRST_RESTART_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Window Watchdog Timer Counter Restart Writing 00A7h to this register restarts the WWDT Counter. Writing any other value causes an error generation to the ESM. Read as 0."]
# [inline (always)]
# [must_use]
pub fn wwdtcntrst_restart (& mut self) -> WWDTCNTRST_RESTART_W < WWDTCNTRST_SPEC , 0 > { WWDTCNTRST_RESTART_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Watchdog Timer Counter Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtcntrst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wwdtcntrst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WWDTCNTRST_SPEC ; impl crate :: RegisterSpec for WWDTCNTRST_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtcntrst::R`](R) reader structure"]
impl crate :: Readable for WWDTCNTRST_SPEC { } # [doc = "`write(|w| ..)` method takes [`wwdtcntrst::W`](W) writer structure"]
impl crate :: Writable for WWDTCNTRST_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WWDTCNTRST to value 0"]
impl crate :: Resettable for WWDTCNTRST_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "WWDTSTAT (r) register accessor: Window Watchdog Timer Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtstat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wwdtstat`]
module"]
pub type WWDTSTAT = crate :: Reg < wwdtstat :: WWDTSTAT_SPEC > ; # [doc = "Window Watchdog Timer Status Register"]
pub mod wwdtstat { # [doc = "Register `WWDTSTAT` reader"]
pub type R = crate :: R < WWDTSTAT_SPEC > ; # [doc = "Field `WWDTSTAT_RUN` reader - Watchdog running status flag."]
pub type WWDTSTAT_RUN_R = crate :: BitReader < WWDTSTAT_RUN_A > ; # [doc = "Watchdog running status flag.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum WWDTSTAT_RUN_A { # [doc = "0: OFF"]
WWDTSTAT_RUN_OFF = 0 , # [doc = "1: ON"]
WWDTSTAT_RUN_ON = 1 , } impl From < WWDTSTAT_RUN_A > for bool { # [inline (always)]
fn from (variant : WWDTSTAT_RUN_A) -> Self { variant as u8 != 0 } } impl WWDTSTAT_RUN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WWDTSTAT_RUN_A { match self . bits { false => WWDTSTAT_RUN_A :: WWDTSTAT_RUN_OFF , true => WWDTSTAT_RUN_A :: WWDTSTAT_RUN_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_wwdtstat_run_off (& self) -> bool { * self == WWDTSTAT_RUN_A :: WWDTSTAT_RUN_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_wwdtstat_run_on (& self) -> bool { * self == WWDTSTAT_RUN_A :: WWDTSTAT_RUN_ON } } impl R { # [doc = "Bit 0 - Watchdog running status flag."]
# [inline (always)]
pub fn wwdtstat_run (& self) -> WWDTSTAT_RUN_R { WWDTSTAT_RUN_R :: new ((self . bits & 1) != 0) } } # [doc = "Window Watchdog Timer Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wwdtstat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WWDTSTAT_SPEC ; impl crate :: RegisterSpec for WWDTSTAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wwdtstat::R`](R) reader structure"]
impl crate :: Readable for WWDTSTAT_SPEC { } # [doc = "`reset()` method sets WWDTSTAT to value 0"]
impl crate :: Resettable for WWDTSTAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "DSSM"]
pub struct DEBUGSS { _marker : PhantomData < * const () > } unsafe impl Send for DEBUGSS { } impl DEBUGSS { # [doc = r"Pointer to the register block"]
pub const PTR : * const debugss :: RegisterBlock = 0x400c_7000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const debugss :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for DEBUGSS { type Target = debugss :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for DEBUGSS { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("DEBUGSS") . finish () } } # [doc = "DSSM"]
pub mod debugss { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x1020]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved1 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved2 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved3 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved4 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved6 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved7 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - Transmit data register"]
pub txd : TXD , # [doc = "0x1104 - Transmit control register"]
pub txctl : TXCTL , # [doc = "0x1108 - Receive data register"]
pub rxd : RXD , # [doc = "0x110c - Receive control register"]
pub rxctl : RXCTL , _reserved12 : [u8 ; 0xf0]
, # [doc = "0x1200 - Special enable authorization register"]
pub special_auth : SPECIAL_AUTH , _reserved13 : [u8 ; 0x0c]
, # [doc = "0x1210 - Application CPU0 authorization register"]
pub app_auth : APP_AUTH , } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Interrupt index status"]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: TXIFG"]
IIDX_STAT_TXIFG = 1 , # [doc = "2: RXIFG"]
IIDX_STAT_RXIFG = 2 , # [doc = "3: PWRUP"]
IIDX_STAT_PWRUP = 3 , # [doc = "4: PWRDWN"]
IIDX_STAT_PWRDWN = 4 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_TXIFG) , 2 => Some (IIDX_STAT_A :: IIDX_STAT_RXIFG) , 3 => Some (IIDX_STAT_A :: IIDX_STAT_PWRUP) , 4 => Some (IIDX_STAT_A :: IIDX_STAT_PWRDWN) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "TXIFG"]
# [inline (always)]
pub fn is_iidx_stat_txifg (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_TXIFG } # [doc = "RXIFG"]
# [inline (always)]
pub fn is_iidx_stat_rxifg (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_RXIFG } # [doc = "PWRUP"]
# [inline (always)]
pub fn is_iidx_stat_pwrup (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PWRUP } # [doc = "PWRDWN"]
# [inline (always)]
pub fn is_iidx_stat_pwrdwn (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PWRDWN } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_TXIFG` reader - Masks TXIFG in MIS register"]
pub type IMASK_TXIFG_R = crate :: BitReader < IMASK_TXIFG_A > ; # [doc = "Masks TXIFG in MIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_TXIFG_A { # [doc = "0: CLR"]
IMASK_TXIFG_CLR = 0 , # [doc = "1: SET"]
IMASK_TXIFG_SET = 1 , } impl From < IMASK_TXIFG_A > for bool { # [inline (always)]
fn from (variant : IMASK_TXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_TXIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_TXIFG_A { match self . bits { false => IMASK_TXIFG_A :: IMASK_TXIFG_CLR , true => IMASK_TXIFG_A :: IMASK_TXIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_txifg_clr (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_txifg_set (& self) -> bool { * self == IMASK_TXIFG_A :: IMASK_TXIFG_SET } } # [doc = "Field `IMASK_TXIFG` writer - Masks TXIFG in MIS register"]
pub type IMASK_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_txifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_txifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TXIFG_A :: IMASK_TXIFG_SET) } } # [doc = "Field `IMASK_RXIFG` reader - Masks RXIFG in MIS register"]
pub type IMASK_RXIFG_R = crate :: BitReader < IMASK_RXIFG_A > ; # [doc = "Masks RXIFG in MIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_RXIFG_A { # [doc = "0: CLR"]
IMASK_RXIFG_CLR = 0 , # [doc = "1: SET"]
IMASK_RXIFG_SET = 1 , } impl From < IMASK_RXIFG_A > for bool { # [inline (always)]
fn from (variant : IMASK_RXIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_RXIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_RXIFG_A { match self . bits { false => IMASK_RXIFG_A :: IMASK_RXIFG_CLR , true => IMASK_RXIFG_A :: IMASK_RXIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_rxifg_clr (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_rxifg_set (& self) -> bool { * self == IMASK_RXIFG_A :: IMASK_RXIFG_SET } } # [doc = "Field `IMASK_RXIFG` writer - Masks RXIFG in MIS register"]
pub type IMASK_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_RXIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_rxifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_rxifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_RXIFG_A :: IMASK_RXIFG_SET) } } # [doc = "Field `IMASK_PWRUPIFG` reader - Masks PWRUPIFG in MIS register"]
pub type IMASK_PWRUPIFG_R = crate :: BitReader < IMASK_PWRUPIFG_A > ; # [doc = "Masks PWRUPIFG in MIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_PWRUPIFG_A { # [doc = "0: CLR"]
IMASK_PWRUPIFG_CLR = 0 , # [doc = "1: SET"]
IMASK_PWRUPIFG_SET = 1 , } impl From < IMASK_PWRUPIFG_A > for bool { # [inline (always)]
fn from (variant : IMASK_PWRUPIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRUPIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_PWRUPIFG_A { match self . bits { false => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR , true => IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_pwrupifg_clr (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_pwrupifg_set (& self) -> bool { * self == IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET } } # [doc = "Field `IMASK_PWRUPIFG` writer - Masks PWRUPIFG in MIS register"]
pub type IMASK_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRUPIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_pwrupifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_pwrupifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRUPIFG_A :: IMASK_PWRUPIFG_SET) } } # [doc = "Field `IMASK_PWRDWNIFG` reader - Masks PWRDWNIFG in MIS register"]
pub type IMASK_PWRDWNIFG_R = crate :: BitReader < IMASK_PWRDWNIFG_A > ; # [doc = "Masks PWRDWNIFG in MIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_PWRDWNIFG_A { # [doc = "0: CLR"]
IMASK_PWRDWNIFG_CLR = 0 , # [doc = "1: SET"]
IMASK_PWRDWNIFG_SET = 1 , } impl From < IMASK_PWRDWNIFG_A > for bool { # [inline (always)]
fn from (variant : IMASK_PWRDWNIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_PWRDWNIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_PWRDWNIFG_A { match self . bits { false => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR , true => IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_pwrdwnifg_clr (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_pwrdwnifg_set (& self) -> bool { * self == IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET } } # [doc = "Field `IMASK_PWRDWNIFG` writer - Masks PWRDWNIFG in MIS register"]
pub type IMASK_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PWRDWNIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_pwrdwnifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_pwrdwnifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PWRDWNIFG_A :: IMASK_PWRDWNIFG_SET) } } impl R { # [doc = "Bit 0 - Masks TXIFG in MIS register"]
# [inline (always)]
pub fn imask_txifg (& self) -> IMASK_TXIFG_R { IMASK_TXIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masks RXIFG in MIS register"]
# [inline (always)]
pub fn imask_rxifg (& self) -> IMASK_RXIFG_R { IMASK_RXIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"]
# [inline (always)]
pub fn imask_pwrupifg (& self) -> IMASK_PWRUPIFG_R { IMASK_PWRUPIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"]
# [inline (always)]
pub fn imask_pwrdwnifg (& self) -> IMASK_PWRDWNIFG_R { IMASK_PWRDWNIFG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Masks TXIFG in MIS register"]
# [inline (always)]
# [must_use]
pub fn imask_txifg (& mut self) -> IMASK_TXIFG_W < IMASK_SPEC , 0 > { IMASK_TXIFG_W :: new (self) } # [doc = "Bit 1 - Masks RXIFG in MIS register"]
# [inline (always)]
# [must_use]
pub fn imask_rxifg (& mut self) -> IMASK_RXIFG_W < IMASK_SPEC , 1 > { IMASK_RXIFG_W :: new (self) } # [doc = "Bit 2 - Masks PWRUPIFG in MIS register"]
# [inline (always)]
# [must_use]
pub fn imask_pwrupifg (& mut self) -> IMASK_PWRUPIFG_W < IMASK_SPEC , 2 > { IMASK_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Masks PWRDWNIFG in MIS register"]
# [inline (always)]
# [must_use]
pub fn imask_pwrdwnifg (& mut self) -> IMASK_PWRDWNIFG_W < IMASK_SPEC , 3 > { IMASK_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_TXIFG` reader - Raw interrupt status for TXIFG"]
pub type RIS_TXIFG_R = crate :: BitReader < RIS_TXIFG_A > ; # [doc = "Raw interrupt status for TXIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_TXIFG_A { # [doc = "0: CLR"]
RIS_TXIFG_CLR = 0 , # [doc = "1: SET"]
RIS_TXIFG_SET = 1 , } impl From < RIS_TXIFG_A > for bool { # [inline (always)]
fn from (variant : RIS_TXIFG_A) -> Self { variant as u8 != 0 } } impl RIS_TXIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_TXIFG_A { match self . bits { false => RIS_TXIFG_A :: RIS_TXIFG_CLR , true => RIS_TXIFG_A :: RIS_TXIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_txifg_clr (& self) -> bool { * self == RIS_TXIFG_A :: RIS_TXIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_txifg_set (& self) -> bool { * self == RIS_TXIFG_A :: RIS_TXIFG_SET } } # [doc = "Field `RIS_RXIFG` reader - Raw interrupt status for RXIFG"]
pub type RIS_RXIFG_R = crate :: BitReader < RIS_RXIFG_A > ; # [doc = "Raw interrupt status for RXIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_RXIFG_A { # [doc = "0: CLR"]
RIS_RXIFG_CLR = 0 , # [doc = "1: SET"]
RIS_RXIFG_SET = 1 , } impl From < RIS_RXIFG_A > for bool { # [inline (always)]
fn from (variant : RIS_RXIFG_A) -> Self { variant as u8 != 0 } } impl RIS_RXIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_RXIFG_A { match self . bits { false => RIS_RXIFG_A :: RIS_RXIFG_CLR , true => RIS_RXIFG_A :: RIS_RXIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_rxifg_clr (& self) -> bool { * self == RIS_RXIFG_A :: RIS_RXIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_rxifg_set (& self) -> bool { * self == RIS_RXIFG_A :: RIS_RXIFG_SET } } # [doc = "Field `RIS_PWRUPIFG` reader - Raw interrupt status for PWRUPIFG"]
pub type RIS_PWRUPIFG_R = crate :: BitReader < RIS_PWRUPIFG_A > ; # [doc = "Raw interrupt status for PWRUPIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_PWRUPIFG_A { # [doc = "0: CLR"]
RIS_PWRUPIFG_CLR = 0 , # [doc = "1: SET"]
RIS_PWRUPIFG_SET = 1 , } impl From < RIS_PWRUPIFG_A > for bool { # [inline (always)]
fn from (variant : RIS_PWRUPIFG_A) -> Self { variant as u8 != 0 } } impl RIS_PWRUPIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_PWRUPIFG_A { match self . bits { false => RIS_PWRUPIFG_A :: RIS_PWRUPIFG_CLR , true => RIS_PWRUPIFG_A :: RIS_PWRUPIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_pwrupifg_clr (& self) -> bool { * self == RIS_PWRUPIFG_A :: RIS_PWRUPIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_pwrupifg_set (& self) -> bool { * self == RIS_PWRUPIFG_A :: RIS_PWRUPIFG_SET } } # [doc = "Field `RIS_PWRDWNIFG` reader - Raw interrupt status for PWRDWNIFG"]
pub type RIS_PWRDWNIFG_R = crate :: BitReader < RIS_PWRDWNIFG_A > ; # [doc = "Raw interrupt status for PWRDWNIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_PWRDWNIFG_A { # [doc = "0: CLR"]
RIS_PWRDWNIFG_CLR = 0 , # [doc = "1: SET"]
RIS_PWRDWNIFG_SET = 1 , } impl From < RIS_PWRDWNIFG_A > for bool { # [inline (always)]
fn from (variant : RIS_PWRDWNIFG_A) -> Self { variant as u8 != 0 } } impl RIS_PWRDWNIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_PWRDWNIFG_A { match self . bits { false => RIS_PWRDWNIFG_A :: RIS_PWRDWNIFG_CLR , true => RIS_PWRDWNIFG_A :: RIS_PWRDWNIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_pwrdwnifg_clr (& self) -> bool { * self == RIS_PWRDWNIFG_A :: RIS_PWRDWNIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_pwrdwnifg_set (& self) -> bool { * self == RIS_PWRDWNIFG_A :: RIS_PWRDWNIFG_SET } } impl R { # [doc = "Bit 0 - Raw interrupt status for TXIFG"]
# [inline (always)]
pub fn ris_txifg (& self) -> RIS_TXIFG_R { RIS_TXIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Raw interrupt status for RXIFG"]
# [inline (always)]
pub fn ris_rxifg (& self) -> RIS_RXIFG_R { RIS_RXIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Raw interrupt status for PWRUPIFG"]
# [inline (always)]
pub fn ris_pwrupifg (& self) -> RIS_PWRUPIFG_R { RIS_PWRUPIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt status for PWRDWNIFG"]
# [inline (always)]
pub fn ris_pwrdwnifg (& self) -> RIS_PWRDWNIFG_R { RIS_PWRDWNIFG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_TXIFG` reader - Masked interrupt status for TXIFG"]
pub type MIS_TXIFG_R = crate :: BitReader < MIS_TXIFG_A > ; # [doc = "Masked interrupt status for TXIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_TXIFG_A { # [doc = "0: CLR"]
MIS_TXIFG_CLR = 0 , # [doc = "1: SET"]
MIS_TXIFG_SET = 1 , } impl From < MIS_TXIFG_A > for bool { # [inline (always)]
fn from (variant : MIS_TXIFG_A) -> Self { variant as u8 != 0 } } impl MIS_TXIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_TXIFG_A { match self . bits { false => MIS_TXIFG_A :: MIS_TXIFG_CLR , true => MIS_TXIFG_A :: MIS_TXIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_txifg_clr (& self) -> bool { * self == MIS_TXIFG_A :: MIS_TXIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_txifg_set (& self) -> bool { * self == MIS_TXIFG_A :: MIS_TXIFG_SET } } # [doc = "Field `MIS_RXIFG` reader - Masked interrupt status for RXIFG"]
pub type MIS_RXIFG_R = crate :: BitReader < MIS_RXIFG_A > ; # [doc = "Masked interrupt status for RXIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_RXIFG_A { # [doc = "0: CLR"]
MIS_RXIFG_CLR = 0 , # [doc = "1: SET"]
MIS_RXIFG_SET = 1 , } impl From < MIS_RXIFG_A > for bool { # [inline (always)]
fn from (variant : MIS_RXIFG_A) -> Self { variant as u8 != 0 } } impl MIS_RXIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_RXIFG_A { match self . bits { false => MIS_RXIFG_A :: MIS_RXIFG_CLR , true => MIS_RXIFG_A :: MIS_RXIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_rxifg_clr (& self) -> bool { * self == MIS_RXIFG_A :: MIS_RXIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_rxifg_set (& self) -> bool { * self == MIS_RXIFG_A :: MIS_RXIFG_SET } } # [doc = "Field `MIS_PWRUPIFG` reader - Masked interrupt status for PWRUPIFG"]
pub type MIS_PWRUPIFG_R = crate :: BitReader < MIS_PWRUPIFG_A > ; # [doc = "Masked interrupt status for PWRUPIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_PWRUPIFG_A { # [doc = "0: CLR"]
MIS_PWRUPIFG_CLR = 0 , # [doc = "1: SET"]
MIS_PWRUPIFG_SET = 1 , } impl From < MIS_PWRUPIFG_A > for bool { # [inline (always)]
fn from (variant : MIS_PWRUPIFG_A) -> Self { variant as u8 != 0 } } impl MIS_PWRUPIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_PWRUPIFG_A { match self . bits { false => MIS_PWRUPIFG_A :: MIS_PWRUPIFG_CLR , true => MIS_PWRUPIFG_A :: MIS_PWRUPIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_pwrupifg_clr (& self) -> bool { * self == MIS_PWRUPIFG_A :: MIS_PWRUPIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_pwrupifg_set (& self) -> bool { * self == MIS_PWRUPIFG_A :: MIS_PWRUPIFG_SET } } # [doc = "Field `MIS_PWRDWNIFG` reader - Masked interrupt status for PWRDWNIFG"]
pub type MIS_PWRDWNIFG_R = crate :: BitReader < MIS_PWRDWNIFG_A > ; # [doc = "Masked interrupt status for PWRDWNIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_PWRDWNIFG_A { # [doc = "0: CLR"]
MIS_PWRDWNIFG_CLR = 0 , # [doc = "1: SET"]
MIS_PWRDWNIFG_SET = 1 , } impl From < MIS_PWRDWNIFG_A > for bool { # [inline (always)]
fn from (variant : MIS_PWRDWNIFG_A) -> Self { variant as u8 != 0 } } impl MIS_PWRDWNIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_PWRDWNIFG_A { match self . bits { false => MIS_PWRDWNIFG_A :: MIS_PWRDWNIFG_CLR , true => MIS_PWRDWNIFG_A :: MIS_PWRDWNIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_pwrdwnifg_clr (& self) -> bool { * self == MIS_PWRDWNIFG_A :: MIS_PWRDWNIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_pwrdwnifg_set (& self) -> bool { * self == MIS_PWRDWNIFG_A :: MIS_PWRDWNIFG_SET } } impl R { # [doc = "Bit 0 - Masked interrupt status for TXIFG"]
# [inline (always)]
pub fn mis_txifg (& self) -> MIS_TXIFG_R { MIS_TXIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Masked interrupt status for RXIFG"]
# [inline (always)]
pub fn mis_rxifg (& self) -> MIS_RXIFG_R { MIS_RXIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masked interrupt status for PWRUPIFG"]
# [inline (always)]
pub fn mis_pwrupifg (& self) -> MIS_PWRUPIFG_R { MIS_PWRUPIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masked interrupt status for PWRDWNIFG"]
# [inline (always)]
pub fn mis_pwrdwnifg (& self) -> MIS_PWRDWNIFG_R { MIS_PWRDWNIFG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Sets TXIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_TXIFG_AW { # [doc = "0: NO_EFFECT"]
ISET_TXIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_TXIFG_SET = 1 , } impl From < ISET_TXIFG_AW > for bool { # [inline (always)]
fn from (variant : ISET_TXIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_TXIFG` writer - Sets TXIFG in RIS register"]
pub type ISET_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_TXIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_txifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TXIFG_AW :: ISET_TXIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_txifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TXIFG_AW :: ISET_TXIFG_SET) } } # [doc = "Sets RXIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_RXIFG_AW { # [doc = "0: NO_EFFECT"]
ISET_RXIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_RXIFG_SET = 1 , } impl From < ISET_RXIFG_AW > for bool { # [inline (always)]
fn from (variant : ISET_RXIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_RXIFG` writer - Sets RXIFG in RIS register"]
pub type ISET_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_RXIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_rxifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_RXIFG_AW :: ISET_RXIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_rxifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_RXIFG_AW :: ISET_RXIFG_SET) } } # [doc = "Sets PWRUPIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_PWRUPIFG_AW { # [doc = "0: NO_EFFECT"]
ISET_PWRUPIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_PWRUPIFG_SET = 1 , } impl From < ISET_PWRUPIFG_AW > for bool { # [inline (always)]
fn from (variant : ISET_PWRUPIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_PWRUPIFG` writer - Sets PWRUPIFG in RIS register"]
pub type ISET_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_PWRUPIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_pwrupifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRUPIFG_AW :: ISET_PWRUPIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_pwrupifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRUPIFG_AW :: ISET_PWRUPIFG_SET) } } # [doc = "Sets PWRDWNIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_PWRDWNIFG_AW { # [doc = "0: NO_EFFECT"]
ISET_PWRDWNIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_PWRDWNIFG_SET = 1 , } impl From < ISET_PWRDWNIFG_AW > for bool { # [inline (always)]
fn from (variant : ISET_PWRDWNIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_PWRDWNIFG` writer - Sets PWRDWNIFG in RIS register"]
pub type ISET_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_PWRDWNIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_pwrdwnifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRDWNIFG_AW :: ISET_PWRDWNIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_pwrdwnifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PWRDWNIFG_AW :: ISET_PWRDWNIFG_SET) } } impl W { # [doc = "Bit 0 - Sets TXIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_txifg (& mut self) -> ISET_TXIFG_W < ISET_SPEC , 0 > { ISET_TXIFG_W :: new (self) } # [doc = "Bit 1 - Sets RXIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_rxifg (& mut self) -> ISET_RXIFG_W < ISET_SPEC , 1 > { ISET_RXIFG_W :: new (self) } # [doc = "Bit 2 - Sets PWRUPIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_pwrupifg (& mut self) -> ISET_PWRUPIFG_W < ISET_SPEC , 2 > { ISET_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Sets PWRDWNIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_pwrdwnifg (& mut self) -> ISET_PWRDWNIFG_W < ISET_SPEC , 3 > { ISET_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Clears TXIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_TXIFG_AW { # [doc = "0: NO_EFFECT"]
ICLR_TXIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_TXIFG_CLR = 1 , } impl From < ICLR_TXIFG_AW > for bool { # [inline (always)]
fn from (variant : ICLR_TXIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_TXIFG` writer - Clears TXIFG in RIS register"]
pub type ICLR_TXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_TXIFG_AW > ; impl < 'a , REG , const O : u8 > ICLR_TXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_txifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TXIFG_AW :: ICLR_TXIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_txifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TXIFG_AW :: ICLR_TXIFG_CLR) } } # [doc = "Clears RXIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_RXIFG_AW { # [doc = "0: NO_EFFECT"]
ICLR_RXIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_RXIFG_CLR = 1 , } impl From < ICLR_RXIFG_AW > for bool { # [inline (always)]
fn from (variant : ICLR_RXIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_RXIFG` writer - Clears RXIFG in RIS register"]
pub type ICLR_RXIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_RXIFG_AW > ; impl < 'a , REG , const O : u8 > ICLR_RXIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_rxifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_RXIFG_AW :: ICLR_RXIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_rxifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_RXIFG_AW :: ICLR_RXIFG_CLR) } } # [doc = "Clears PWRUPIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_PWRUPIFG_AW { # [doc = "0: NO_EFFECT"]
ICLR_PWRUPIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_PWRUPIFG_CLR = 1 , } impl From < ICLR_PWRUPIFG_AW > for bool { # [inline (always)]
fn from (variant : ICLR_PWRUPIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_PWRUPIFG` writer - Clears PWRUPIFG in RIS register"]
pub type ICLR_PWRUPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_PWRUPIFG_AW > ; impl < 'a , REG , const O : u8 > ICLR_PWRUPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_pwrupifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_PWRUPIFG_AW :: ICLR_PWRUPIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_pwrupifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_PWRUPIFG_AW :: ICLR_PWRUPIFG_CLR) } } # [doc = "Clears PWRDWNIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_PWRDWNIFG_AW { # [doc = "0: NO_EFFECT"]
ICLR_PWRDWNIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_PWRDWNIFG_CLR = 1 , } impl From < ICLR_PWRDWNIFG_AW > for bool { # [inline (always)]
fn from (variant : ICLR_PWRDWNIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_PWRDWNIFG` writer - Clears PWRDWNIFG in RIS register"]
pub type ICLR_PWRDWNIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_PWRDWNIFG_AW > ; impl < 'a , REG , const O : u8 > ICLR_PWRDWNIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_pwrdwnifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_PWRDWNIFG_AW :: ICLR_PWRDWNIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_pwrdwnifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_PWRDWNIFG_AW :: ICLR_PWRDWNIFG_CLR) } } impl W { # [doc = "Bit 0 - Clears TXIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_txifg (& mut self) -> ICLR_TXIFG_W < ICLR_SPEC , 0 > { ICLR_TXIFG_W :: new (self) } # [doc = "Bit 1 - Clears RXIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_rxifg (& mut self) -> ICLR_RXIFG_W < ICLR_SPEC , 1 > { ICLR_RXIFG_W :: new (self) } # [doc = "Bit 2 - Clears PWRUPIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_pwrupifg (& mut self) -> ICLR_PWRUPIFG_W < ICLR_SPEC , 2 > { ICLR_PWRUPIFG_W :: new (self) } # [doc = "Bit 3 - Clears PWRDWNIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_pwrdwnifg (& mut self) -> ICLR_PWRDWNIFG_W < ICLR_SPEC , 3 > { ICLR_PWRDWNIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (r) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for peripheral events"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for peripheral events\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for peripheral events"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TXD (r) register accessor: Transmit data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txd::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txd`]
module"]
pub type TXD = crate :: Reg < txd :: TXD_SPEC > ; # [doc = "Transmit data register"]
pub mod txd { # [doc = "Register `TXD` reader"]
pub type R = crate :: R < TXD_SPEC > ; # [doc = "Field `TXD_TX_DATA` reader - Contains data written by an external debug tool to the SEC-AP TXDATA register"]
pub type TXD_TX_DATA_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 0:31 - Contains data written by an external debug tool to the SEC-AP TXDATA register"]
# [inline (always)]
pub fn txd_tx_data (& self) -> TXD_TX_DATA_R { TXD_TX_DATA_R :: new (self . bits) } } # [doc = "Transmit data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txd::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TXD_SPEC ; impl crate :: RegisterSpec for TXD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`txd::R`](R) reader structure"]
impl crate :: Readable for TXD_SPEC { } # [doc = "`reset()` method sets TXD to value 0"]
impl crate :: Resettable for TXD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TXCTL (r) register accessor: Transmit control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txctl::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txctl`]
module"]
pub type TXCTL = crate :: Reg < txctl :: TXCTL_SPEC > ; # [doc = "Transmit control register"]
pub mod txctl { # [doc = "Register `TXCTL` reader"]
pub type R = crate :: R < TXCTL_SPEC > ; # [doc = "Field `TXCTL_TRANSMIT` reader - Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field."]
pub type TXCTL_TRANSMIT_R = crate :: BitReader < TXCTL_TRANSMIT_A > ; # [doc = "Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TXCTL_TRANSMIT_A { # [doc = "0: EMPTY"]
TXCTL_TRANSMIT_EMPTY = 0 , # [doc = "1: FULL"]
TXCTL_TRANSMIT_FULL = 1 , } impl From < TXCTL_TRANSMIT_A > for bool { # [inline (always)]
fn from (variant : TXCTL_TRANSMIT_A) -> Self { variant as u8 != 0 } } impl TXCTL_TRANSMIT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TXCTL_TRANSMIT_A { match self . bits { false => TXCTL_TRANSMIT_A :: TXCTL_TRANSMIT_EMPTY , true => TXCTL_TRANSMIT_A :: TXCTL_TRANSMIT_FULL , } } # [doc = "EMPTY"]
# [inline (always)]
pub fn is_txctl_transmit_empty (& self) -> bool { * self == TXCTL_TRANSMIT_A :: TXCTL_TRANSMIT_EMPTY } # [doc = "FULL"]
# [inline (always)]
pub fn is_txctl_transmit_full (& self) -> bool { * self == TXCTL_TRANSMIT_A :: TXCTL_TRANSMIT_FULL } } # [doc = "Field `TXCTL_TRANSMIT_FLAGS` reader - Generic TX flags that can be set by external debug tool. Functionality is defined by SW."]
pub type TXCTL_TRANSMIT_FLAGS_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bit 0 - Indicates data request in DSSM.TXD, set on write via Debug AP to DSSM.TXD. A read of the DSSM.TXD register by SW will clear the TX field. The tool can check that TXD is empty by reading this field."]
# [inline (always)]
pub fn txctl_transmit (& self) -> TXCTL_TRANSMIT_R { TXCTL_TRANSMIT_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:31 - Generic TX flags that can be set by external debug tool. Functionality is defined by SW."]
# [inline (always)]
pub fn txctl_transmit_flags (& self) -> TXCTL_TRANSMIT_FLAGS_R { TXCTL_TRANSMIT_FLAGS_R :: new ((self . bits >> 1) & 0x7fff_ffff) } } # [doc = "Transmit control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txctl::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TXCTL_SPEC ; impl crate :: RegisterSpec for TXCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`txctl::R`](R) reader structure"]
impl crate :: Readable for TXCTL_SPEC { } # [doc = "`reset()` method sets TXCTL to value 0"]
impl crate :: Resettable for TXCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RXD (rw) register accessor: Receive data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxd`]
module"]
pub type RXD = crate :: Reg < rxd :: RXD_SPEC > ; # [doc = "Receive data register"]
pub mod rxd { # [doc = "Register `RXD` reader"]
pub type R = crate :: R < RXD_SPEC > ; # [doc = "Register `RXD` writer"]
pub type W = crate :: W < RXD_SPEC > ; # [doc = "Field `RXD_RX_DATA` reader - Contains data written by SM/OW."]
pub type RXD_RX_DATA_R = crate :: FieldReader < u32 > ; # [doc = "Field `RXD_RX_DATA` writer - Contains data written by SM/OW."]
pub type RXD_RX_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - Contains data written by SM/OW."]
# [inline (always)]
pub fn rxd_rx_data (& self) -> RXD_RX_DATA_R { RXD_RX_DATA_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - Contains data written by SM/OW."]
# [inline (always)]
# [must_use]
pub fn rxd_rx_data (& mut self) -> RXD_RX_DATA_W < RXD_SPEC , 0 > { RXD_RX_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Receive data register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RXD_SPEC ; impl crate :: RegisterSpec for RXD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rxd::R`](R) reader structure"]
impl crate :: Readable for RXD_SPEC { } # [doc = "`write(|w| ..)` method takes [`rxd::W`](W) writer structure"]
impl crate :: Writable for RXD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RXD to value 0"]
impl crate :: Resettable for RXD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RXCTL (rw) register accessor: Receive control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxctl`]
module"]
pub type RXCTL = crate :: Reg < rxctl :: RXCTL_SPEC > ; # [doc = "Receive control register"]
pub mod rxctl { # [doc = "Register `RXCTL` reader"]
pub type R = crate :: R < RXCTL_SPEC > ; # [doc = "Register `RXCTL` writer"]
pub type W = crate :: W < RXCTL_SPEC > ; # [doc = "Field `RXCTL_RECEIVE` reader - Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field."]
pub type RXCTL_RECEIVE_R = crate :: BitReader < RXCTL_RECEIVE_A > ; # [doc = "Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RXCTL_RECEIVE_A { # [doc = "0: EMPTY"]
RXCTL_RECEIVE_EMPTY = 0 , # [doc = "1: FULL"]
RXCTL_RECEIVE_FULL = 1 , } impl From < RXCTL_RECEIVE_A > for bool { # [inline (always)]
fn from (variant : RXCTL_RECEIVE_A) -> Self { variant as u8 != 0 } } impl RXCTL_RECEIVE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RXCTL_RECEIVE_A { match self . bits { false => RXCTL_RECEIVE_A :: RXCTL_RECEIVE_EMPTY , true => RXCTL_RECEIVE_A :: RXCTL_RECEIVE_FULL , } } # [doc = "EMPTY"]
# [inline (always)]
pub fn is_rxctl_receive_empty (& self) -> bool { * self == RXCTL_RECEIVE_A :: RXCTL_RECEIVE_EMPTY } # [doc = "FULL"]
# [inline (always)]
pub fn is_rxctl_receive_full (& self) -> bool { * self == RXCTL_RECEIVE_A :: RXCTL_RECEIVE_FULL } } # [doc = "Field `RXCTL_RECEIVE_FLAGS` reader - Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW."]
pub type RXCTL_RECEIVE_FLAGS_R = crate :: FieldReader ; # [doc = "Field `RXCTL_RECEIVE_FLAGS` writer - Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW."]
pub type RXCTL_RECEIVE_FLAGS_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bit 0 - Indicates SW write to the DSSM.RXD register. A read of the DSSM.RXD register by SWD Access Port will clear the RX field."]
# [inline (always)]
pub fn rxctl_receive (& self) -> RXCTL_RECEIVE_R { RXCTL_RECEIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:7 - Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW."]
# [inline (always)]
pub fn rxctl_receive_flags (& self) -> RXCTL_RECEIVE_FLAGS_R { RXCTL_RECEIVE_FLAGS_R :: new (((self . bits >> 1) & 0x7f) as u8) } } impl W { # [doc = "Bits 1:7 - Generic RX flags that can be set by SW and read by external debug tool. Functionality is defined by SW."]
# [inline (always)]
# [must_use]
pub fn rxctl_receive_flags (& mut self) -> RXCTL_RECEIVE_FLAGS_W < RXCTL_SPEC , 1 > { RXCTL_RECEIVE_FLAGS_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Receive control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RXCTL_SPEC ; impl crate :: RegisterSpec for RXCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rxctl::R`](R) reader structure"]
impl crate :: Readable for RXCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`rxctl::W`](W) writer structure"]
impl crate :: Writable for RXCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RXCTL to value 0"]
impl crate :: Resettable for RXCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SPECIAL_AUTH (r) register accessor: Special enable authorization register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`special_auth::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@special_auth`]
module"]
pub type SPECIAL_AUTH = crate :: Reg < special_auth :: SPECIAL_AUTH_SPEC > ; # [doc = "Special enable authorization register"]
pub mod special_auth { # [doc = "Register `SPECIAL_AUTH` reader"]
pub type R = crate :: R < SPECIAL_AUTH_SPEC > ; # [doc = "Field `SPECIAL_AUTH_SECAPEN` reader - An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP."]
pub type SPECIAL_AUTH_SECAPEN_R = crate :: BitReader < SPECIAL_AUTH_SECAPEN_A > ; # [doc = "An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SPECIAL_AUTH_SECAPEN_A { # [doc = "0: DISABLE"]
SPECIAL_AUTH_SECAPEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SPECIAL_AUTH_SECAPEN_ENABLE = 1 , } impl From < SPECIAL_AUTH_SECAPEN_A > for bool { # [inline (always)]
fn from (variant : SPECIAL_AUTH_SECAPEN_A) -> Self { variant as u8 != 0 } } impl SPECIAL_AUTH_SECAPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SPECIAL_AUTH_SECAPEN_A { match self . bits { false => SPECIAL_AUTH_SECAPEN_A :: SPECIAL_AUTH_SECAPEN_DISABLE , true => SPECIAL_AUTH_SECAPEN_A :: SPECIAL_AUTH_SECAPEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_special_auth_secapen_disable (& self) -> bool { * self == SPECIAL_AUTH_SECAPEN_A :: SPECIAL_AUTH_SECAPEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_special_auth_secapen_enable (& self) -> bool { * self == SPECIAL_AUTH_SECAPEN_A :: SPECIAL_AUTH_SECAPEN_ENABLE } } # [doc = "Field `SPECIAL_AUTH_SWDPORTEN` reader - When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access."]
pub type SPECIAL_AUTH_SWDPORTEN_R = crate :: BitReader < SPECIAL_AUTH_SWDPORTEN_A > ; # [doc = "When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SPECIAL_AUTH_SWDPORTEN_A { # [doc = "0: DISABLE"]
SPECIAL_AUTH_SWDPORTEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SPECIAL_AUTH_SWDPORTEN_ENABLE = 1 , } impl From < SPECIAL_AUTH_SWDPORTEN_A > for bool { # [inline (always)]
fn from (variant : SPECIAL_AUTH_SWDPORTEN_A) -> Self { variant as u8 != 0 } } impl SPECIAL_AUTH_SWDPORTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SPECIAL_AUTH_SWDPORTEN_A { match self . bits { false => SPECIAL_AUTH_SWDPORTEN_A :: SPECIAL_AUTH_SWDPORTEN_DISABLE , true => SPECIAL_AUTH_SWDPORTEN_A :: SPECIAL_AUTH_SWDPORTEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_special_auth_swdporten_disable (& self) -> bool { * self == SPECIAL_AUTH_SWDPORTEN_A :: SPECIAL_AUTH_SWDPORTEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_special_auth_swdporten_enable (& self) -> bool { * self == SPECIAL_AUTH_SWDPORTEN_A :: SPECIAL_AUTH_SWDPORTEN_ENABLE } } # [doc = "Field `SPECIAL_AUTH_DFTAPEN` reader - An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access."]
pub type SPECIAL_AUTH_DFTAPEN_R = crate :: BitReader < SPECIAL_AUTH_DFTAPEN_A > ; # [doc = "An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SPECIAL_AUTH_DFTAPEN_A { # [doc = "0: DISABLE"]
SPECIAL_AUTH_DFTAPEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SPECIAL_AUTH_DFTAPEN_ENABLE = 1 , } impl From < SPECIAL_AUTH_DFTAPEN_A > for bool { # [inline (always)]
fn from (variant : SPECIAL_AUTH_DFTAPEN_A) -> Self { variant as u8 != 0 } } impl SPECIAL_AUTH_DFTAPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SPECIAL_AUTH_DFTAPEN_A { match self . bits { false => SPECIAL_AUTH_DFTAPEN_A :: SPECIAL_AUTH_DFTAPEN_DISABLE , true => SPECIAL_AUTH_DFTAPEN_A :: SPECIAL_AUTH_DFTAPEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_special_auth_dftapen_disable (& self) -> bool { * self == SPECIAL_AUTH_DFTAPEN_A :: SPECIAL_AUTH_DFTAPEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_special_auth_dftapen_enable (& self) -> bool { * self == SPECIAL_AUTH_DFTAPEN_A :: SPECIAL_AUTH_DFTAPEN_ENABLE } } # [doc = "Field `SPECIAL_AUTH_ETAPEN` reader - An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access."]
pub type SPECIAL_AUTH_ETAPEN_R = crate :: BitReader < SPECIAL_AUTH_ETAPEN_A > ; # [doc = "An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SPECIAL_AUTH_ETAPEN_A { # [doc = "0: DISABLE"]
SPECIAL_AUTH_ETAPEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SPECIAL_AUTH_ETAPEN_ENABLE = 1 , } impl From < SPECIAL_AUTH_ETAPEN_A > for bool { # [inline (always)]
fn from (variant : SPECIAL_AUTH_ETAPEN_A) -> Self { variant as u8 != 0 } } impl SPECIAL_AUTH_ETAPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SPECIAL_AUTH_ETAPEN_A { match self . bits { false => SPECIAL_AUTH_ETAPEN_A :: SPECIAL_AUTH_ETAPEN_DISABLE , true => SPECIAL_AUTH_ETAPEN_A :: SPECIAL_AUTH_ETAPEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_special_auth_etapen_disable (& self) -> bool { * self == SPECIAL_AUTH_ETAPEN_A :: SPECIAL_AUTH_ETAPEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_special_auth_etapen_enable (& self) -> bool { * self == SPECIAL_AUTH_ETAPEN_A :: SPECIAL_AUTH_ETAPEN_ENABLE } } # [doc = "Field `SPECIAL_AUTH_CFGAPEN` reader - An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP."]
pub type SPECIAL_AUTH_CFGAPEN_R = crate :: BitReader < SPECIAL_AUTH_CFGAPEN_A > ; # [doc = "An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SPECIAL_AUTH_CFGAPEN_A { # [doc = "0: DISABLE"]
SPECIAL_AUTH_CFGAPEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SPECIAL_AUTH_CFGAPEN_ENABLE = 1 , } impl From < SPECIAL_AUTH_CFGAPEN_A > for bool { # [inline (always)]
fn from (variant : SPECIAL_AUTH_CFGAPEN_A) -> Self { variant as u8 != 0 } } impl SPECIAL_AUTH_CFGAPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SPECIAL_AUTH_CFGAPEN_A { match self . bits { false => SPECIAL_AUTH_CFGAPEN_A :: SPECIAL_AUTH_CFGAPEN_DISABLE , true => SPECIAL_AUTH_CFGAPEN_A :: SPECIAL_AUTH_CFGAPEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_special_auth_cfgapen_disable (& self) -> bool { * self == SPECIAL_AUTH_CFGAPEN_A :: SPECIAL_AUTH_CFGAPEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_special_auth_cfgapen_enable (& self) -> bool { * self == SPECIAL_AUTH_CFGAPEN_A :: SPECIAL_AUTH_CFGAPEN_ENABLE } } # [doc = "Field `SPECIAL_AUTH_AHBAPEN` reader - Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation."]
pub type SPECIAL_AUTH_AHBAPEN_R = crate :: BitReader < SPECIAL_AUTH_AHBAPEN_A > ; # [doc = "Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SPECIAL_AUTH_AHBAPEN_A { # [doc = "0: DISABLE"]
SPECIAL_AUTH_AHBAPEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SPECIAL_AUTH_AHBAPEN_ENABLE = 1 , } impl From < SPECIAL_AUTH_AHBAPEN_A > for bool { # [inline (always)]
fn from (variant : SPECIAL_AUTH_AHBAPEN_A) -> Self { variant as u8 != 0 } } impl SPECIAL_AUTH_AHBAPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SPECIAL_AUTH_AHBAPEN_A { match self . bits { false => SPECIAL_AUTH_AHBAPEN_A :: SPECIAL_AUTH_AHBAPEN_DISABLE , true => SPECIAL_AUTH_AHBAPEN_A :: SPECIAL_AUTH_AHBAPEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_special_auth_ahbapen_disable (& self) -> bool { * self == SPECIAL_AUTH_AHBAPEN_A :: SPECIAL_AUTH_AHBAPEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_special_auth_ahbapen_enable (& self) -> bool { * self == SPECIAL_AUTH_AHBAPEN_A :: SPECIAL_AUTH_AHBAPEN_ENABLE } } # [doc = "Field `SPECIAL_AUTH_PWRAPEN` reader - An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access."]
pub type SPECIAL_AUTH_PWRAPEN_R = crate :: BitReader < SPECIAL_AUTH_PWRAPEN_A > ; # [doc = "An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SPECIAL_AUTH_PWRAPEN_A { # [doc = "0: DISABLE"]
SPECIAL_AUTH_PWRAPEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SPECIAL_AUTH_PWRAPEN_ENABLE = 1 , } impl From < SPECIAL_AUTH_PWRAPEN_A > for bool { # [inline (always)]
fn from (variant : SPECIAL_AUTH_PWRAPEN_A) -> Self { variant as u8 != 0 } } impl SPECIAL_AUTH_PWRAPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SPECIAL_AUTH_PWRAPEN_A { match self . bits { false => SPECIAL_AUTH_PWRAPEN_A :: SPECIAL_AUTH_PWRAPEN_DISABLE , true => SPECIAL_AUTH_PWRAPEN_A :: SPECIAL_AUTH_PWRAPEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_special_auth_pwrapen_disable (& self) -> bool { * self == SPECIAL_AUTH_PWRAPEN_A :: SPECIAL_AUTH_PWRAPEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_special_auth_pwrapen_enable (& self) -> bool { * self == SPECIAL_AUTH_PWRAPEN_A :: SPECIAL_AUTH_PWRAPEN_ENABLE } } impl R { # [doc = "Bit 0 - An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Security-AP to communicate with security control logic. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Security-AP."]
# [inline (always)]
pub fn special_auth_secapen (& self) -> SPECIAL_AUTH_SECAPEN_R { SPECIAL_AUTH_SECAPEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - When asserted, the SW-DP functions normally. When deasserted, the SW-DP effectively disables all external debug access."]
# [inline (always)]
pub fn special_auth_swdporten (& self) -> SPECIAL_AUTH_SWDPORTEN_R { SPECIAL_AUTH_SWDPORTEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the DFT-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access."]
# [inline (always)]
pub fn special_auth_dftapen (& self) -> SPECIAL_AUTH_DFTAPEN_R { SPECIAL_AUTH_DFTAPEN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - An active high input. When asserted (and SWD access is also permitted), the debug tools can then access an ET-AP external to the DebugSS lite. When deasserted, a DAPBUS firewall will isolate the AP and prevent access."]
# [inline (always)]
pub fn special_auth_etapen (& self) -> SPECIAL_AUTH_ETAPEN_R { SPECIAL_AUTH_ETAPEN_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - An active high input. When asserted (and SWD access is also permitted), the debug tools can use the Config-AP to read device configuration information. When deasserted, a DAPBUS firewall will isolate the AP and prevent access to the Config-AP."]
# [inline (always)]
pub fn special_auth_cfgapen (& self) -> SPECIAL_AUTH_CFGAPEN_R { SPECIAL_AUTH_CFGAPEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Disabling / enabling debug access to the M0+ Core via the AHB-AP DAP bus isolation."]
# [inline (always)]
pub fn special_auth_ahbapen (& self) -> SPECIAL_AUTH_AHBAPEN_R { SPECIAL_AUTH_AHBAPEN_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - An active high input. When asserted (and SWD access is also permitted), the debug tools can then access the PWR-AP to power and reset state of the CPU. When deasserted, a DAPBUS firewall will isolate the AP and prevent access."]
# [inline (always)]
pub fn special_auth_pwrapen (& self) -> SPECIAL_AUTH_PWRAPEN_R { SPECIAL_AUTH_PWRAPEN_R :: new (((self . bits >> 6) & 1) != 0) } } # [doc = "Special enable authorization register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`special_auth::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SPECIAL_AUTH_SPEC ; impl crate :: RegisterSpec for SPECIAL_AUTH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`special_auth::R`](R) reader structure"]
impl crate :: Readable for SPECIAL_AUTH_SPEC { } # [doc = "`reset()` method sets SPECIAL_AUTH to value 0x13"]
impl crate :: Resettable for SPECIAL_AUTH_SPEC { const RESET_VALUE : Self :: Ux = 0x13 ; } } # [doc = "APP_AUTH (r) register accessor: Application CPU0 authorization register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_auth::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_auth`]
module"]
pub type APP_AUTH = crate :: Reg < app_auth :: APP_AUTH_SPEC > ; # [doc = "Application CPU0 authorization register"]
pub mod app_auth { # [doc = "Register `APP_AUTH` reader"]
pub type R = crate :: R < APP_AUTH_SPEC > ; # [doc = "Field `APP_AUTH_DBGEN` reader - Controls invasive debug enable."]
pub type APP_AUTH_DBGEN_R = crate :: BitReader < APP_AUTH_DBGEN_A > ; # [doc = "Controls invasive debug enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum APP_AUTH_DBGEN_A { # [doc = "0: DISABLE"]
APP_AUTH_DBGEN_DISABLE = 0 , # [doc = "1: ENABLE"]
APP_AUTH_DBGEN_ENABLE = 1 , } impl From < APP_AUTH_DBGEN_A > for bool { # [inline (always)]
fn from (variant : APP_AUTH_DBGEN_A) -> Self { variant as u8 != 0 } } impl APP_AUTH_DBGEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> APP_AUTH_DBGEN_A { match self . bits { false => APP_AUTH_DBGEN_A :: APP_AUTH_DBGEN_DISABLE , true => APP_AUTH_DBGEN_A :: APP_AUTH_DBGEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_app_auth_dbgen_disable (& self) -> bool { * self == APP_AUTH_DBGEN_A :: APP_AUTH_DBGEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_app_auth_dbgen_enable (& self) -> bool { * self == APP_AUTH_DBGEN_A :: APP_AUTH_DBGEN_ENABLE } } # [doc = "Field `APP_AUTH_NIDEN` reader - Controls non-invasive debug enable."]
pub type APP_AUTH_NIDEN_R = crate :: BitReader < APP_AUTH_NIDEN_A > ; # [doc = "Controls non-invasive debug enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum APP_AUTH_NIDEN_A { # [doc = "0: DISABLE"]
APP_AUTH_NIDEN_DISABLE = 0 , # [doc = "1: ENABLE"]
APP_AUTH_NIDEN_ENABLE = 1 , } impl From < APP_AUTH_NIDEN_A > for bool { # [inline (always)]
fn from (variant : APP_AUTH_NIDEN_A) -> Self { variant as u8 != 0 } } impl APP_AUTH_NIDEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> APP_AUTH_NIDEN_A { match self . bits { false => APP_AUTH_NIDEN_A :: APP_AUTH_NIDEN_DISABLE , true => APP_AUTH_NIDEN_A :: APP_AUTH_NIDEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_app_auth_niden_disable (& self) -> bool { * self == APP_AUTH_NIDEN_A :: APP_AUTH_NIDEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_app_auth_niden_enable (& self) -> bool { * self == APP_AUTH_NIDEN_A :: APP_AUTH_NIDEN_ENABLE } } # [doc = "Field `APP_AUTH_SPIDEN` reader - Secure invasive debug enable."]
pub type APP_AUTH_SPIDEN_R = crate :: BitReader < APP_AUTH_SPIDEN_A > ; # [doc = "Secure invasive debug enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum APP_AUTH_SPIDEN_A { # [doc = "0: DISABLE"]
APP_AUTH_SPIDEN_DISABLE = 0 , # [doc = "1: ENABLE"]
APP_AUTH_SPIDEN_ENABLE = 1 , } impl From < APP_AUTH_SPIDEN_A > for bool { # [inline (always)]
fn from (variant : APP_AUTH_SPIDEN_A) -> Self { variant as u8 != 0 } } impl APP_AUTH_SPIDEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> APP_AUTH_SPIDEN_A { match self . bits { false => APP_AUTH_SPIDEN_A :: APP_AUTH_SPIDEN_DISABLE , true => APP_AUTH_SPIDEN_A :: APP_AUTH_SPIDEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_app_auth_spiden_disable (& self) -> bool { * self == APP_AUTH_SPIDEN_A :: APP_AUTH_SPIDEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_app_auth_spiden_enable (& self) -> bool { * self == APP_AUTH_SPIDEN_A :: APP_AUTH_SPIDEN_ENABLE } } # [doc = "Field `APP_AUTH_SPNIDEN` reader - Secure non-invasive debug enable."]
pub type APP_AUTH_SPNIDEN_R = crate :: BitReader < APP_AUTH_SPNIDEN_A > ; # [doc = "Secure non-invasive debug enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum APP_AUTH_SPNIDEN_A { # [doc = "0: DISABLE"]
APP_AUTH_SPNIDEN_DISABLE = 0 , # [doc = "1: ENABLE"]
APP_AUTH_SPNIDEN_ENABLE = 1 , } impl From < APP_AUTH_SPNIDEN_A > for bool { # [inline (always)]
fn from (variant : APP_AUTH_SPNIDEN_A) -> Self { variant as u8 != 0 } } impl APP_AUTH_SPNIDEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> APP_AUTH_SPNIDEN_A { match self . bits { false => APP_AUTH_SPNIDEN_A :: APP_AUTH_SPNIDEN_DISABLE , true => APP_AUTH_SPNIDEN_A :: APP_AUTH_SPNIDEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_app_auth_spniden_disable (& self) -> bool { * self == APP_AUTH_SPNIDEN_A :: APP_AUTH_SPNIDEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_app_auth_spniden_enable (& self) -> bool { * self == APP_AUTH_SPNIDEN_A :: APP_AUTH_SPNIDEN_ENABLE } } impl R { # [doc = "Bit 0 - Controls invasive debug enable."]
# [inline (always)]
pub fn app_auth_dbgen (& self) -> APP_AUTH_DBGEN_R { APP_AUTH_DBGEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Controls non-invasive debug enable."]
# [inline (always)]
pub fn app_auth_niden (& self) -> APP_AUTH_NIDEN_R { APP_AUTH_NIDEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Secure invasive debug enable."]
# [inline (always)]
pub fn app_auth_spiden (& self) -> APP_AUTH_SPIDEN_R { APP_AUTH_SPIDEN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Secure non-invasive debug enable."]
# [inline (always)]
pub fn app_auth_spniden (& self) -> APP_AUTH_SPNIDEN_R { APP_AUTH_SPNIDEN_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Application CPU0 authorization register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`app_auth::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct APP_AUTH_SPEC ; impl crate :: RegisterSpec for APP_AUTH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`app_auth::R`](R) reader structure"]
impl crate :: Readable for APP_AUTH_SPEC { } # [doc = "`reset()` method sets APP_AUTH to value 0"]
impl crate :: Resettable for APP_AUTH_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct VREF { _marker : PhantomData < * const () > } unsafe impl Send for VREF { } impl VREF { # [doc = r"Pointer to the register block"]
pub const PTR : * const vref :: RegisterBlock = 0x4003_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const vref :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for VREF { type Target = vref :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for VREF { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("VREF") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod vref { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved2 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved3 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , _reserved4 : [u8 ; 0x04]
, # [doc = "0x1008 - Clock Selection"]
pub clksel : CLKSEL , _reserved5 : [u8 ; 0xf0]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - Control 0"]
pub ctl0 : CTL0 , # [doc = "0x1104 - Control 1"]
pub ctl1 : CTL1 , # [doc = "0x1108 - Control 2"]
pub ctl2 : CTL2 , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader ; # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Selection"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader ; # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader ; # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader ; # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL0 (rw) register accessor: Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl0`]
module"]
pub type CTL0 = crate :: Reg < ctl0 :: CTL0_SPEC > ; # [doc = "Control 0"]
pub mod ctl0 { # [doc = "Register `CTL0` reader"]
pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"]
pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENABLE` reader - This bit enables the VREF module."]
pub type CTL0_ENABLE_R = crate :: BitReader < CTL0_ENABLE_A > ; # [doc = "This bit enables the VREF module.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_ENABLE_A { # [doc = "0: DISABLE"]
CTL0_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_ENABLE_ENABLE = 1 , } impl From < CTL0_ENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL0_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_ENABLE_A { match self . bits { false => CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE , true => CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_enable_disable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_enable_enable (& self) -> bool { * self == CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE } } # [doc = "Field `CTL0_ENABLE` writer - This bit enables the VREF module."]
pub type CTL0_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLE_A :: CTL0_ENABLE_ENABLE) } } # [doc = "Field `CTL0_ENABLEBIAS` reader - This bit enables the VREF Bias."]
pub type CTL0_ENABLEBIAS_R = crate :: BitReader < CTL0_ENABLEBIAS_A > ; # [doc = "This bit enables the VREF Bias.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_ENABLEBIAS_A { # [doc = "0: DISABLE"]
CTL0_ENABLEBIAS_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_ENABLEBIAS_ENABLE = 1 , } impl From < CTL0_ENABLEBIAS_A > for bool { # [inline (always)]
fn from (variant : CTL0_ENABLEBIAS_A) -> Self { variant as u8 != 0 } } impl CTL0_ENABLEBIAS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_ENABLEBIAS_A { match self . bits { false => CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_DISABLE , true => CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_enablebias_disable (& self) -> bool { * self == CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_enablebias_enable (& self) -> bool { * self == CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_ENABLE } } # [doc = "Field `CTL0_ENABLEBIAS` writer - This bit enables the VREF Bias."]
pub type CTL0_ENABLEBIAS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENABLEBIAS_A > ; impl < 'a , REG , const O : u8 > CTL0_ENABLEBIAS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_enablebias_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_enablebias_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENABLEBIAS_A :: CTL0_ENABLEBIAS_ENABLE) } } # [doc = "Field `CTL0_IBPROG` reader - There bits configure current bias."]
pub type CTL0_IBPROG_R = crate :: FieldReader < CTL0_IBPROG_A > ; # [doc = "There bits configure current bias.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_IBPROG_A { # [doc = "0: NOMIBIAS"]
CTL0_IBPROG_NOMIBIAS = 0 , # [doc = "1: IBPROG01"]
CTL0_IBPROG_IBPROG01 = 1 , # [doc = "2: IBPROG10"]
CTL0_IBPROG_IBPROG10 = 2 , # [doc = "3: IBPROG11"]
CTL0_IBPROG_IBPROG11 = 3 , } impl From < CTL0_IBPROG_A > for u8 { # [inline (always)]
fn from (variant : CTL0_IBPROG_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_IBPROG_A { type Ux = u8 ; } impl CTL0_IBPROG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_IBPROG_A { match self . bits { 0 => CTL0_IBPROG_A :: CTL0_IBPROG_NOMIBIAS , 1 => CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG01 , 2 => CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG10 , 3 => CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG11 , _ => unreachable ! () , } } # [doc = "NOMIBIAS"]
# [inline (always)]
pub fn is_ctl0_ibprog_nomibias (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_NOMIBIAS } # [doc = "IBPROG01"]
# [inline (always)]
pub fn is_ctl0_ibprog_ibprog01 (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG01 } # [doc = "IBPROG10"]
# [inline (always)]
pub fn is_ctl0_ibprog_ibprog10 (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG10 } # [doc = "IBPROG11"]
# [inline (always)]
pub fn is_ctl0_ibprog_ibprog11 (& self) -> bool { * self == CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG11 } } # [doc = "Field `CTL0_IBPROG` writer - There bits configure current bias."]
pub type CTL0_IBPROG_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL0_IBPROG_A > ; impl < 'a , REG , const O : u8 > CTL0_IBPROG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOMIBIAS"]
# [inline (always)]
pub fn ctl0_ibprog_nomibias (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_NOMIBIAS) } # [doc = "IBPROG01"]
# [inline (always)]
pub fn ctl0_ibprog_ibprog01 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG01) } # [doc = "IBPROG10"]
# [inline (always)]
pub fn ctl0_ibprog_ibprog10 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG10) } # [doc = "IBPROG11"]
# [inline (always)]
pub fn ctl0_ibprog_ibprog11 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IBPROG_A :: CTL0_IBPROG_IBPROG11) } } # [doc = "Field `CTL0_BUFCONFIG` reader - These bits configure output buffer."]
pub type CTL0_BUFCONFIG_R = crate :: BitReader < CTL0_BUFCONFIG_A > ; # [doc = "These bits configure output buffer.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_BUFCONFIG_A { # [doc = "0: HV"]
CTL0_BUFCONFIG_OUTPUT2P5V = 0 , # [doc = "1: LV"]
CTL0_BUFCONFIG_OUTPUT1P4V = 1 , } impl From < CTL0_BUFCONFIG_A > for bool { # [inline (always)]
fn from (variant : CTL0_BUFCONFIG_A) -> Self { variant as u8 != 0 } } impl CTL0_BUFCONFIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_BUFCONFIG_A { match self . bits { false => CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT2P5V , true => CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT1P4V , } } # [doc = "HV"]
# [inline (always)]
pub fn is_ctl0_bufconfig_output2p5v (& self) -> bool { * self == CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT2P5V } # [doc = "LV"]
# [inline (always)]
pub fn is_ctl0_bufconfig_output1p4v (& self) -> bool { * self == CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT1P4V } } # [doc = "Field `CTL0_BUFCONFIG` writer - These bits configure output buffer."]
pub type CTL0_BUFCONFIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_BUFCONFIG_A > ; impl < 'a , REG , const O : u8 > CTL0_BUFCONFIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "HV"]
# [inline (always)]
pub fn ctl0_bufconfig_output2p5v (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT2P5V) } # [doc = "LV"]
# [inline (always)]
pub fn ctl0_bufconfig_output1p4v (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_BUFCONFIG_A :: CTL0_BUFCONFIG_OUTPUT1P4V) } } # [doc = "Field `CTL0_SHMODE` reader - This bit enable sample and hold mode"]
pub type CTL0_SHMODE_R = crate :: BitReader < CTL0_SHMODE_A > ; # [doc = "This bit enable sample and hold mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_SHMODE_A { # [doc = "0: DISABLE"]
CTL0_SHMODE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_SHMODE_ENABLE = 1 , } impl From < CTL0_SHMODE_A > for bool { # [inline (always)]
fn from (variant : CTL0_SHMODE_A) -> Self { variant as u8 != 0 } } impl CTL0_SHMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_SHMODE_A { match self . bits { false => CTL0_SHMODE_A :: CTL0_SHMODE_DISABLE , true => CTL0_SHMODE_A :: CTL0_SHMODE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_shmode_disable (& self) -> bool { * self == CTL0_SHMODE_A :: CTL0_SHMODE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_shmode_enable (& self) -> bool { * self == CTL0_SHMODE_A :: CTL0_SHMODE_ENABLE } } # [doc = "Field `CTL0_SHMODE` writer - This bit enable sample and hold mode"]
pub type CTL0_SHMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_SHMODE_A > ; impl < 'a , REG , const O : u8 > CTL0_SHMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_shmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SHMODE_A :: CTL0_SHMODE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_shmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SHMODE_A :: CTL0_SHMODE_ENABLE) } } # [doc = "Field `CTL0_SPARE` reader - These bits are reserved"]
pub type CTL0_SPARE_R = crate :: FieldReader ; # [doc = "Field `CTL0_SPARE` writer - These bits are reserved"]
pub type CTL0_SPARE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; impl R { # [doc = "Bit 0 - This bit enables the VREF module."]
# [inline (always)]
pub fn ctl0_enable (& self) -> CTL0_ENABLE_R { CTL0_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - This bit enables the VREF Bias."]
# [inline (always)]
pub fn ctl0_enablebias (& self) -> CTL0_ENABLEBIAS_R { CTL0_ENABLEBIAS_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - There bits configure current bias."]
# [inline (always)]
pub fn ctl0_ibprog (& self) -> CTL0_IBPROG_R { CTL0_IBPROG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bit 7 - These bits configure output buffer."]
# [inline (always)]
pub fn ctl0_bufconfig (& self) -> CTL0_BUFCONFIG_R { CTL0_BUFCONFIG_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - This bit enable sample and hold mode"]
# [inline (always)]
pub fn ctl0_shmode (& self) -> CTL0_SHMODE_R { CTL0_SHMODE_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:12 - These bits are reserved"]
# [inline (always)]
pub fn ctl0_spare (& self) -> CTL0_SPARE_R { CTL0_SPARE_R :: new (((self . bits >> 9) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - This bit enables the VREF module."]
# [inline (always)]
# [must_use]
pub fn ctl0_enable (& mut self) -> CTL0_ENABLE_W < CTL0_SPEC , 0 > { CTL0_ENABLE_W :: new (self) } # [doc = "Bit 1 - This bit enables the VREF Bias."]
# [inline (always)]
# [must_use]
pub fn ctl0_enablebias (& mut self) -> CTL0_ENABLEBIAS_W < CTL0_SPEC , 1 > { CTL0_ENABLEBIAS_W :: new (self) } # [doc = "Bits 2:3 - There bits configure current bias."]
# [inline (always)]
# [must_use]
pub fn ctl0_ibprog (& mut self) -> CTL0_IBPROG_W < CTL0_SPEC , 2 > { CTL0_IBPROG_W :: new (self) } # [doc = "Bit 7 - These bits configure output buffer."]
# [inline (always)]
# [must_use]
pub fn ctl0_bufconfig (& mut self) -> CTL0_BUFCONFIG_W < CTL0_SPEC , 7 > { CTL0_BUFCONFIG_W :: new (self) } # [doc = "Bit 8 - This bit enable sample and hold mode"]
# [inline (always)]
# [must_use]
pub fn ctl0_shmode (& mut self) -> CTL0_SHMODE_W < CTL0_SPEC , 8 > { CTL0_SHMODE_W :: new (self) } # [doc = "Bits 9:12 - These bits are reserved"]
# [inline (always)]
# [must_use]
pub fn ctl0_spare (& mut self) -> CTL0_SPARE_W < CTL0_SPEC , 9 > { CTL0_SPARE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0"]
impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL1 (rw) register accessor: Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl1`]
module"]
pub type CTL1 = crate :: Reg < ctl1 :: CTL1_SPEC > ; # [doc = "Control 1"]
pub mod ctl1 { # [doc = "Register `CTL1` reader"]
pub type R = crate :: R < CTL1_SPEC > ; # [doc = "Register `CTL1` writer"]
pub type W = crate :: W < CTL1_SPEC > ; # [doc = "Field `CTL1_READY` reader - These bits defines status of VREF"]
pub type CTL1_READY_R = crate :: BitReader < CTL1_READY_A > ; # [doc = "These bits defines status of VREF\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_READY_A { # [doc = "0: NOTRDY"]
CTL1_READY_NOTRDY = 0 , # [doc = "1: RDY"]
CTL1_READY_RDY = 1 , } impl From < CTL1_READY_A > for bool { # [inline (always)]
fn from (variant : CTL1_READY_A) -> Self { variant as u8 != 0 } } impl CTL1_READY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_READY_A { match self . bits { false => CTL1_READY_A :: CTL1_READY_NOTRDY , true => CTL1_READY_A :: CTL1_READY_RDY , } } # [doc = "NOTRDY"]
# [inline (always)]
pub fn is_ctl1_ready_notrdy (& self) -> bool { * self == CTL1_READY_A :: CTL1_READY_NOTRDY } # [doc = "RDY"]
# [inline (always)]
pub fn is_ctl1_ready_rdy (& self) -> bool { * self == CTL1_READY_A :: CTL1_READY_RDY } } # [doc = "Field `CTL1_VREFLOSEL` reader - This bit select VREFLO pin"]
pub type CTL1_VREFLOSEL_R = crate :: BitReader ; # [doc = "Field `CTL1_VREFLOSEL` writer - This bit select VREFLO pin"]
pub type CTL1_VREFLOSEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; impl R { # [doc = "Bit 0 - These bits defines status of VREF"]
# [inline (always)]
pub fn ctl1_ready (& self) -> CTL1_READY_R { CTL1_READY_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - This bit select VREFLO pin"]
# [inline (always)]
pub fn ctl1_vreflosel (& self) -> CTL1_VREFLOSEL_R { CTL1_VREFLOSEL_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 1 - This bit select VREFLO pin"]
# [inline (always)]
# [must_use]
pub fn ctl1_vreflosel (& mut self) -> CTL1_VREFLOSEL_W < CTL1_SPEC , 1 > { CTL1_VREFLOSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL1_SPEC ; impl crate :: RegisterSpec for CTL1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl1::R`](R) reader structure"]
impl crate :: Readable for CTL1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl1::W`](W) writer structure"]
impl crate :: Writable for CTL1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL1 to value 0"]
impl crate :: Resettable for CTL1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL2 (rw) register accessor: Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl2`]
module"]
pub type CTL2 = crate :: Reg < ctl2 :: CTL2_SPEC > ; # [doc = "Control 2"]
pub mod ctl2 { # [doc = "Register `CTL2` reader"]
pub type R = crate :: R < CTL2_SPEC > ; # [doc = "Register `CTL2` writer"]
pub type W = crate :: W < CTL2_SPEC > ; # [doc = "Field `CTL2_SHCYCLE` reader - Sample and hold cycle count"]
pub type CTL2_SHCYCLE_R = crate :: FieldReader < u16 > ; # [doc = "Field `CTL2_SHCYCLE` writer - Sample and hold cycle count"]
pub type CTL2_SHCYCLE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; # [doc = "Field `CTL2_HCYCLE` reader - Hold cycle count"]
pub type CTL2_HCYCLE_R = crate :: FieldReader < u16 > ; # [doc = "Field `CTL2_HCYCLE` writer - Hold cycle count"]
pub type CTL2_HCYCLE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Sample and hold cycle count"]
# [inline (always)]
pub fn ctl2_shcycle (& self) -> CTL2_SHCYCLE_R { CTL2_SHCYCLE_R :: new ((self . bits & 0xffff) as u16) } # [doc = "Bits 16:31 - Hold cycle count"]
# [inline (always)]
pub fn ctl2_hcycle (& self) -> CTL2_HCYCLE_R { CTL2_HCYCLE_R :: new (((self . bits >> 16) & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Sample and hold cycle count"]
# [inline (always)]
# [must_use]
pub fn ctl2_shcycle (& mut self) -> CTL2_SHCYCLE_W < CTL2_SPEC , 0 > { CTL2_SHCYCLE_W :: new (self) } # [doc = "Bits 16:31 - Hold cycle count"]
# [inline (always)]
# [must_use]
pub fn ctl2_hcycle (& mut self) -> CTL2_HCYCLE_W < CTL2_SPEC , 16 > { CTL2_HCYCLE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL2_SPEC ; impl crate :: RegisterSpec for CTL2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl2::R`](R) reader structure"]
impl crate :: Readable for CTL2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl2::W`](W) writer structure"]
impl crate :: Writable for CTL2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL2 to value 0"]
impl crate :: Resettable for CTL2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct CRC { _marker : PhantomData < * const () > } unsafe impl Send for CRC { } impl CRC { # [doc = r"Pointer to the register block"]
pub const PTR : * const crc :: RegisterBlock = 0x4044_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const crc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for CRC { type Target = crc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for CRC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("CRC") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod crc { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved2 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved3 : [u8 ; 0x08e4]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - CRC Control Register"]
pub crcctrl : CRCCTRL , # [doc = "0x1104 - CRC Seed Register"]
pub crcseed : CRCSEED , # [doc = "0x1108 - CRC Input Data Register"]
pub crcin : CRCIN , # [doc = "0x110c - CRC Output Result Register"]
pub crcout : CRCOUT , _reserved8 : [u8 ; 0x06f0]
, # [doc = "0x1800..0x2000 - CRC Input Data Array Register"]
pub crcin_idx : [CRCIN_IDX ; 512]
, } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CRCCTRL (rw) register accessor: CRC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcctrl`]
module"]
pub type CRCCTRL = crate :: Reg < crcctrl :: CRCCTRL_SPEC > ; # [doc = "CRC Control Register"]
pub mod crcctrl { # [doc = "Register `CRCCTRL` reader"]
pub type R = crate :: R < CRCCTRL_SPEC > ; # [doc = "Register `CRCCTRL` writer"]
pub type W = crate :: W < CRCCTRL_SPEC > ; # [doc = "Field `CRCCTRL_POLYSIZE` reader - This bit indicates which CRC calculation is performed by the generator."]
pub type CRCCTRL_POLYSIZE_R = crate :: BitReader < CRCCTRL_POLYSIZE_A > ; # [doc = "This bit indicates which CRC calculation is performed by the generator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CRCCTRL_POLYSIZE_A { # [doc = "0: CRC32"]
CRCCTRL_POLYSIZE_CRC32 = 0 , # [doc = "1: CRC16"]
CRCCTRL_POLYSIZE_CRC16 = 1 , } impl From < CRCCTRL_POLYSIZE_A > for bool { # [inline (always)]
fn from (variant : CRCCTRL_POLYSIZE_A) -> Self { variant as u8 != 0 } } impl CRCCTRL_POLYSIZE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CRCCTRL_POLYSIZE_A { match self . bits { false => CRCCTRL_POLYSIZE_A :: CRCCTRL_POLYSIZE_CRC32 , true => CRCCTRL_POLYSIZE_A :: CRCCTRL_POLYSIZE_CRC16 , } } # [doc = "CRC32"]
# [inline (always)]
pub fn is_crcctrl_polysize_crc32 (& self) -> bool { * self == CRCCTRL_POLYSIZE_A :: CRCCTRL_POLYSIZE_CRC32 } # [doc = "CRC16"]
# [inline (always)]
pub fn is_crcctrl_polysize_crc16 (& self) -> bool { * self == CRCCTRL_POLYSIZE_A :: CRCCTRL_POLYSIZE_CRC16 } } # [doc = "Field `CRCCTRL_POLYSIZE` writer - This bit indicates which CRC calculation is performed by the generator."]
pub type CRCCTRL_POLYSIZE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CRCCTRL_POLYSIZE_A > ; impl < 'a , REG , const O : u8 > CRCCTRL_POLYSIZE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CRC32"]
# [inline (always)]
pub fn crcctrl_polysize_crc32 (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_POLYSIZE_A :: CRCCTRL_POLYSIZE_CRC32) } # [doc = "CRC16"]
# [inline (always)]
pub fn crcctrl_polysize_crc16 (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_POLYSIZE_A :: CRCCTRL_POLYSIZE_CRC16) } } # [doc = "Field `CRCCTRL_BITREVERSE` reader - CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT."]
pub type CRCCTRL_BITREVERSE_R = crate :: BitReader < CRCCTRL_BITREVERSE_A > ; # [doc = "CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CRCCTRL_BITREVERSE_A { # [doc = "0: NOT_REVERSED"]
CRCCTRL_BITREVERSE_NOT_REVERSED = 0 , # [doc = "1: REVERSED"]
CRCCTRL_BITREVERSE_REVERSED = 1 , } impl From < CRCCTRL_BITREVERSE_A > for bool { # [inline (always)]
fn from (variant : CRCCTRL_BITREVERSE_A) -> Self { variant as u8 != 0 } } impl CRCCTRL_BITREVERSE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CRCCTRL_BITREVERSE_A { match self . bits { false => CRCCTRL_BITREVERSE_A :: CRCCTRL_BITREVERSE_NOT_REVERSED , true => CRCCTRL_BITREVERSE_A :: CRCCTRL_BITREVERSE_REVERSED , } } # [doc = "NOT_REVERSED"]
# [inline (always)]
pub fn is_crcctrl_bitreverse_not_reversed (& self) -> bool { * self == CRCCTRL_BITREVERSE_A :: CRCCTRL_BITREVERSE_NOT_REVERSED } # [doc = "REVERSED"]
# [inline (always)]
pub fn is_crcctrl_bitreverse_reversed (& self) -> bool { * self == CRCCTRL_BITREVERSE_A :: CRCCTRL_BITREVERSE_REVERSED } } # [doc = "Field `CRCCTRL_BITREVERSE` writer - CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT."]
pub type CRCCTRL_BITREVERSE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CRCCTRL_BITREVERSE_A > ; impl < 'a , REG , const O : u8 > CRCCTRL_BITREVERSE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOT_REVERSED"]
# [inline (always)]
pub fn crcctrl_bitreverse_not_reversed (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_BITREVERSE_A :: CRCCTRL_BITREVERSE_NOT_REVERSED) } # [doc = "REVERSED"]
# [inline (always)]
pub fn crcctrl_bitreverse_reversed (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_BITREVERSE_A :: CRCCTRL_BITREVERSE_REVERSED) } } # [doc = "Field `CRCCTRL_INPUT_ENDIANNESS` reader - CRC Endian. This bit indicates the byte order within a word or half word of input data."]
pub type CRCCTRL_INPUT_ENDIANNESS_R = crate :: BitReader < CRCCTRL_INPUT_ENDIANNESS_A > ; # [doc = "CRC Endian. This bit indicates the byte order within a word or half word of input data.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CRCCTRL_INPUT_ENDIANNESS_A { # [doc = "0: LITTLE_ENDIAN"]
CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN = 0 , # [doc = "1: BIG_ENDIAN"]
CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN = 1 , } impl From < CRCCTRL_INPUT_ENDIANNESS_A > for bool { # [inline (always)]
fn from (variant : CRCCTRL_INPUT_ENDIANNESS_A) -> Self { variant as u8 != 0 } } impl CRCCTRL_INPUT_ENDIANNESS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CRCCTRL_INPUT_ENDIANNESS_A { match self . bits { false => CRCCTRL_INPUT_ENDIANNESS_A :: CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN , true => CRCCTRL_INPUT_ENDIANNESS_A :: CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN , } } # [doc = "LITTLE_ENDIAN"]
# [inline (always)]
pub fn is_crcctrl_input_endianness_little_endian (& self) -> bool { * self == CRCCTRL_INPUT_ENDIANNESS_A :: CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN } # [doc = "BIG_ENDIAN"]
# [inline (always)]
pub fn is_crcctrl_input_endianness_big_endian (& self) -> bool { * self == CRCCTRL_INPUT_ENDIANNESS_A :: CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN } } # [doc = "Field `CRCCTRL_INPUT_ENDIANNESS` writer - CRC Endian. This bit indicates the byte order within a word or half word of input data."]
pub type CRCCTRL_INPUT_ENDIANNESS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CRCCTRL_INPUT_ENDIANNESS_A > ; impl < 'a , REG , const O : u8 > CRCCTRL_INPUT_ENDIANNESS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LITTLE_ENDIAN"]
# [inline (always)]
pub fn crcctrl_input_endianness_little_endian (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_INPUT_ENDIANNESS_A :: CRCCTRL_INPUT_ENDIANNESS_LITTLE_ENDIAN) } # [doc = "BIG_ENDIAN"]
# [inline (always)]
pub fn crcctrl_input_endianness_big_endian (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_INPUT_ENDIANNESS_A :: CRCCTRL_INPUT_ENDIANNESS_BIG_ENDIAN) } } # [doc = "Field `CRCCTRL_OUTPUT_BYTESWAP` reader - CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0"]
pub type CRCCTRL_OUTPUT_BYTESWAP_R = crate :: BitReader < CRCCTRL_OUTPUT_BYTESWAP_A > ; # [doc = "CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CRCCTRL_OUTPUT_BYTESWAP_A { # [doc = "0: DISABLE"]
CRCCTRL_OUTPUT_BYTESWAP_DISABLE = 0 , # [doc = "1: ENABLE"]
CRCCTRL_OUTPUT_BYTESWAP_ENABLE = 1 , } impl From < CRCCTRL_OUTPUT_BYTESWAP_A > for bool { # [inline (always)]
fn from (variant : CRCCTRL_OUTPUT_BYTESWAP_A) -> Self { variant as u8 != 0 } } impl CRCCTRL_OUTPUT_BYTESWAP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CRCCTRL_OUTPUT_BYTESWAP_A { match self . bits { false => CRCCTRL_OUTPUT_BYTESWAP_A :: CRCCTRL_OUTPUT_BYTESWAP_DISABLE , true => CRCCTRL_OUTPUT_BYTESWAP_A :: CRCCTRL_OUTPUT_BYTESWAP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_crcctrl_output_byteswap_disable (& self) -> bool { * self == CRCCTRL_OUTPUT_BYTESWAP_A :: CRCCTRL_OUTPUT_BYTESWAP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_crcctrl_output_byteswap_enable (& self) -> bool { * self == CRCCTRL_OUTPUT_BYTESWAP_A :: CRCCTRL_OUTPUT_BYTESWAP_ENABLE } } # [doc = "Field `CRCCTRL_OUTPUT_BYTESWAP` writer - CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0"]
pub type CRCCTRL_OUTPUT_BYTESWAP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CRCCTRL_OUTPUT_BYTESWAP_A > ; impl < 'a , REG , const O : u8 > CRCCTRL_OUTPUT_BYTESWAP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn crcctrl_output_byteswap_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_OUTPUT_BYTESWAP_A :: CRCCTRL_OUTPUT_BYTESWAP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn crcctrl_output_byteswap_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CRCCTRL_OUTPUT_BYTESWAP_A :: CRCCTRL_OUTPUT_BYTESWAP_ENABLE) } } impl R { # [doc = "Bit 0 - This bit indicates which CRC calculation is performed by the generator."]
# [inline (always)]
pub fn crcctrl_polysize (& self) -> CRCCTRL_POLYSIZE_R { CRCCTRL_POLYSIZE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT."]
# [inline (always)]
pub fn crcctrl_bitreverse (& self) -> CRCCTRL_BITREVERSE_R { CRCCTRL_BITREVERSE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - CRC Endian. This bit indicates the byte order within a word or half word of input data."]
# [inline (always)]
pub fn crcctrl_input_endianness (& self) -> CRCCTRL_INPUT_ENDIANNESS_R { CRCCTRL_INPUT_ENDIANNESS_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 4 - CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0"]
# [inline (always)]
pub fn crcctrl_output_byteswap (& self) -> CRCCTRL_OUTPUT_BYTESWAP_R { CRCCTRL_OUTPUT_BYTESWAP_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - This bit indicates which CRC calculation is performed by the generator."]
# [inline (always)]
# [must_use]
pub fn crcctrl_polysize (& mut self) -> CRCCTRL_POLYSIZE_W < CRCCTRL_SPEC , 0 > { CRCCTRL_POLYSIZE_W :: new (self) } # [doc = "Bit 1 - CRC Bit Input and output Reverse. This bit indictes that the bit order of each input byte used for the CRC calculation is reversed before it is passed to the generator, and that the bit order of the calculated CRC is be reversed when read from CRC_RESULT."]
# [inline (always)]
# [must_use]
pub fn crcctrl_bitreverse (& mut self) -> CRCCTRL_BITREVERSE_W < CRCCTRL_SPEC , 1 > { CRCCTRL_BITREVERSE_W :: new (self) } # [doc = "Bit 2 - CRC Endian. This bit indicates the byte order within a word or half word of input data."]
# [inline (always)]
# [must_use]
pub fn crcctrl_input_endianness (& mut self) -> CRCCTRL_INPUT_ENDIANNESS_W < CRCCTRL_SPEC , 2 > { CRCCTRL_INPUT_ENDIANNESS_W :: new (self) } # [doc = "Bit 4 - CRC Output Byteswap Enable. This bit controls whether the output is byte-swapped upon a read of the CRCOUT register. If CRCOUT is accessed as a half-word, and the OUTPUT_BYTESWAP is set to to 1, then the two bytes in the 16-bit access are swapped and returned. B1 is returned as B0 B0 is returned as B1 If CRCOUT is accessed as a word, and the OUTPUT_BYTESWAP is set to 1, then the four bytes in the 32-bit read are swapped. B3 is returned as B0 B2 is returned as B1 B1 is returned as B2 B0 is returned as B3 Note that if the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP enabled, then the output is: MSB LSB 0x0 0x0 B0 B1 If the CRC POLYSIZE is 16-bit and a 32-bit read of CRCOUT is performed with OUTPUT_BYTESWAP disabled, then the output is: MSB LSB 0x0 0x0 B1 B0"]
# [inline (always)]
# [must_use]
pub fn crcctrl_output_byteswap (& mut self) -> CRCCTRL_OUTPUT_BYTESWAP_W < CRCCTRL_SPEC , 4 > { CRCCTRL_OUTPUT_BYTESWAP_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CRC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CRCCTRL_SPEC ; impl crate :: RegisterSpec for CRCCTRL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`crcctrl::R`](R) reader structure"]
impl crate :: Readable for CRCCTRL_SPEC { } # [doc = "`write(|w| ..)` method takes [`crcctrl::W`](W) writer structure"]
impl crate :: Writable for CRCCTRL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CRCCTRL to value 0"]
impl crate :: Resettable for CRCCTRL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CRCSEED (w) register accessor: CRC Seed Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcseed::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcseed`]
module"]
pub type CRCSEED = crate :: Reg < crcseed :: CRCSEED_SPEC > ; # [doc = "CRC Seed Register"]
pub mod crcseed { # [doc = "Register `CRCSEED` writer"]
pub type W = crate :: W < CRCSEED_SPEC > ; # [doc = "Field `CRCSEED_SEED` writer - Seed Data"]
pub type CRCSEED_SEED_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl W { # [doc = "Bits 0:31 - Seed Data"]
# [inline (always)]
# [must_use]
pub fn crcseed_seed (& mut self) -> CRCSEED_SEED_W < CRCSEED_SPEC , 0 > { CRCSEED_SEED_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CRC Seed Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcseed::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CRCSEED_SPEC ; impl crate :: RegisterSpec for CRCSEED_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`crcseed::W`](W) writer structure"]
impl crate :: Writable for CRCSEED_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CRCSEED to value 0"]
impl crate :: Resettable for CRCSEED_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CRCIN (w) register accessor: CRC Input Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcin::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcin`]
module"]
pub type CRCIN = crate :: Reg < crcin :: CRCIN_SPEC > ; # [doc = "CRC Input Data Register"]
pub mod crcin { # [doc = "Register `CRCIN` writer"]
pub type W = crate :: W < CRCIN_SPEC > ; # [doc = "Field `CRCIN_DATA` writer - Input Data"]
pub type CRCIN_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl W { # [doc = "Bits 0:31 - Input Data"]
# [inline (always)]
# [must_use]
pub fn crcin_data (& mut self) -> CRCIN_DATA_W < CRCIN_SPEC , 0 > { CRCIN_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CRC Input Data Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcin::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CRCIN_SPEC ; impl crate :: RegisterSpec for CRCIN_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`crcin::W`](W) writer structure"]
impl crate :: Writable for CRCIN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CRCIN to value 0"]
impl crate :: Resettable for CRCIN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CRCOUT (r) register accessor: CRC Output Result Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcout::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcout`]
module"]
pub type CRCOUT = crate :: Reg < crcout :: CRCOUT_SPEC > ; # [doc = "CRC Output Result Register"]
pub mod crcout { # [doc = "Register `CRCOUT` reader"]
pub type R = crate :: R < CRCOUT_SPEC > ; # [doc = "Field `CRCOUT_RESULT` reader - Result"]
pub type CRCOUT_RESULT_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 0:31 - Result"]
# [inline (always)]
pub fn crcout_result (& self) -> CRCOUT_RESULT_R { CRCOUT_RESULT_R :: new (self . bits) } } # [doc = "CRC Output Result Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`crcout::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CRCOUT_SPEC ; impl crate :: RegisterSpec for CRCOUT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`crcout::R`](R) reader structure"]
impl crate :: Readable for CRCOUT_SPEC { } # [doc = "`reset()` method sets CRCOUT to value 0"]
impl crate :: Resettable for CRCOUT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CRCIN_IDX (w) register accessor: CRC Input Data Array Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcin_idx::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@crcin_idx`]
module"]
pub type CRCIN_IDX = crate :: Reg < crcin_idx :: CRCIN_IDX_SPEC > ; # [doc = "CRC Input Data Array Register"]
pub mod crcin_idx { # [doc = "Register `CRCIN_IDX[%s]` writer"]
pub type W = crate :: W < CRCIN_IDX_SPEC > ; # [doc = "Field `CRCIN_IDX_DATA` writer - Input Data"]
pub type CRCIN_IDX_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl W { # [doc = "Bits 0:31 - Input Data"]
# [inline (always)]
# [must_use]
pub fn crcin_idx_data (& mut self) -> CRCIN_IDX_DATA_W < CRCIN_IDX_SPEC , 0 > { CRCIN_IDX_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CRC Input Data Array Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`crcin_idx::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CRCIN_IDX_SPEC ; impl crate :: RegisterSpec for CRCIN_IDX_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`crcin_idx::W`](W) writer structure"]
impl crate :: Writable for CRCIN_IDX_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CRCIN_IDX[%s]
to value 0"]
impl crate :: Resettable for CRCIN_IDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct OPA0 { _marker : PhantomData < * const () > } unsafe impl Send for OPA0 { } impl OPA0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const opa0 :: RegisterBlock = 0x4002_0000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const opa0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for OPA0 { type Target = opa0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for OPA0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("OPA0") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod opa0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved2 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub gprcm_stat : GPRCM_STAT , _reserved3 : [u8 ; 0x07f8]
, # [doc = "0x1010 - Clock Override"]
pub clkovr : CLKOVR , _reserved4 : [u8 ; 0x08]
, # [doc = "0x101c - Power Control"]
pub pwrctl : PWRCTL , _reserved5 : [u8 ; 0xe0]
, # [doc = "0x1100 - Control Register"]
pub ctl : CTL , # [doc = "0x1104 - Configuration Base Register"]
pub cfgbase : CFGBASE , # [doc = "0x1108 - Configuration Register"]
pub cfg : CFG , _reserved8 : [u8 ; 0x0c]
, # [doc = "0x1118 - Status Register"]
pub stat : STAT , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GPRCM_STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gprcm_stat`]
module"]
pub type GPRCM_STAT = crate :: Reg < gprcm_stat :: GPRCM_STAT_SPEC > ; # [doc = "Status Register"]
pub mod gprcm_stat { # [doc = "Register `GPRCM_STAT` reader"]
pub type R = crate :: R < GPRCM_STAT_SPEC > ; # [doc = "Field `GPRCM_STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type GPRCM_STAT_RESETSTKY_R = crate :: BitReader < GPRCM_STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GPRCM_STAT_RESETSTKY_A { # [doc = "0: NORES"]
GPRCM_STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
GPRCM_STAT_RESETSTKY_RESET = 1 , } impl From < GPRCM_STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : GPRCM_STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl GPRCM_STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GPRCM_STAT_RESETSTKY_A { match self . bits { false => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES , true => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_nores (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_reset (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn gprcm_stat_resetstky (& self) -> GPRCM_STAT_RESETSTKY_R { GPRCM_STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GPRCM_STAT_SPEC ; impl crate :: RegisterSpec for GPRCM_STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gprcm_stat::R`](R) reader structure"]
impl crate :: Readable for GPRCM_STAT_SPEC { } # [doc = "`reset()` method sets GPRCM_STAT to value 0"]
impl crate :: Resettable for GPRCM_STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKOVR (rw) register accessor: Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkovr`]
module"]
pub type CLKOVR = crate :: Reg < clkovr :: CLKOVR_SPEC > ; # [doc = "Clock Override"]
pub mod clkovr { # [doc = "Register `CLKOVR` reader"]
pub type R = crate :: R < CLKOVR_SPEC > ; # [doc = "Register `CLKOVR` writer"]
pub type W = crate :: W < CLKOVR_SPEC > ; # [doc = "Field `CLKOVR_OVERRIDE` reader - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
pub type CLKOVR_OVERRIDE_R = crate :: BitReader < CLKOVR_OVERRIDE_A > ; # [doc = "Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKOVR_OVERRIDE_A { # [doc = "0: DISABLED"]
CLKOVR_OVERRIDE_DISABLED = 0 , # [doc = "1: ENABLED"]
CLKOVR_OVERRIDE_ENABLED = 1 , } impl From < CLKOVR_OVERRIDE_A > for bool { # [inline (always)]
fn from (variant : CLKOVR_OVERRIDE_A) -> Self { variant as u8 != 0 } } impl CLKOVR_OVERRIDE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKOVR_OVERRIDE_A { match self . bits { false => CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED , true => CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_clkovr_override_disabled (& self) -> bool { * self == CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_clkovr_override_enabled (& self) -> bool { * self == CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED } } # [doc = "Field `CLKOVR_OVERRIDE` writer - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
pub type CLKOVR_OVERRIDE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKOVR_OVERRIDE_A > ; impl < 'a , REG , const O : u8 > CLKOVR_OVERRIDE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn clkovr_override_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn clkovr_override_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED) } } # [doc = "Field `CLKOVR_RUN_STOP` reader - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
pub type CLKOVR_RUN_STOP_R = crate :: BitReader < CLKOVR_RUN_STOP_A > ; # [doc = "If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKOVR_RUN_STOP_A { # [doc = "0: RUN"]
CLKOVR_RUN_STOP_RUN = 0 , # [doc = "1: STOP"]
CLKOVR_RUN_STOP_STOP = 1 , } impl From < CLKOVR_RUN_STOP_A > for bool { # [inline (always)]
fn from (variant : CLKOVR_RUN_STOP_A) -> Self { variant as u8 != 0 } } impl CLKOVR_RUN_STOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKOVR_RUN_STOP_A { match self . bits { false => CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN , true => CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP , } } # [doc = "RUN"]
# [inline (always)]
pub fn is_clkovr_run_stop_run (& self) -> bool { * self == CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN } # [doc = "STOP"]
# [inline (always)]
pub fn is_clkovr_run_stop_stop (& self) -> bool { * self == CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP } } # [doc = "Field `CLKOVR_RUN_STOP` writer - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
pub type CLKOVR_RUN_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKOVR_RUN_STOP_A > ; impl < 'a , REG , const O : u8 > CLKOVR_RUN_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RUN"]
# [inline (always)]
pub fn clkovr_run_stop_run (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN) } # [doc = "STOP"]
# [inline (always)]
pub fn clkovr_run_stop_stop (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP) } } impl R { # [doc = "Bit 0 - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
# [inline (always)]
pub fn clkovr_override (& self) -> CLKOVR_OVERRIDE_R { CLKOVR_OVERRIDE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
# [inline (always)]
pub fn clkovr_run_stop (& self) -> CLKOVR_RUN_STOP_R { CLKOVR_RUN_STOP_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
# [inline (always)]
# [must_use]
pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W < CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
# [inline (always)]
# [must_use]
pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W < CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKOVR_SPEC ; impl crate :: RegisterSpec for CLKOVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkovr::R`](R) reader structure"]
impl crate :: Readable for CLKOVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkovr::W`](W) writer structure"]
impl crate :: Writable for CLKOVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKOVR to value 0"]
impl crate :: Resettable for CLKOVR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWRCTL (rw) register accessor: Power Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwrctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwrctl`]
module"]
pub type PWRCTL = crate :: Reg < pwrctl :: PWRCTL_SPEC > ; # [doc = "Power Control"]
pub mod pwrctl { # [doc = "Register `PWRCTL` reader"]
pub type R = crate :: R < PWRCTL_SPEC > ; # [doc = "Register `PWRCTL` writer"]
pub type W = crate :: W < PWRCTL_SPEC > ; # [doc = "Field `PWRCTL_AUTO_OFF` reader - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
pub type PWRCTL_AUTO_OFF_R = crate :: BitReader < PWRCTL_AUTO_OFF_A > ; # [doc = "When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWRCTL_AUTO_OFF_A { # [doc = "0: DISABLE"]
PWRCTL_AUTO_OFF_DISABLE = 0 , # [doc = "1: ENABLE"]
PWRCTL_AUTO_OFF_ENABLE = 1 , } impl From < PWRCTL_AUTO_OFF_A > for bool { # [inline (always)]
fn from (variant : PWRCTL_AUTO_OFF_A) -> Self { variant as u8 != 0 } } impl PWRCTL_AUTO_OFF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWRCTL_AUTO_OFF_A { match self . bits { false => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE , true => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwrctl_auto_off_disable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwrctl_auto_off_enable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE } } # [doc = "Field `PWRCTL_AUTO_OFF` writer - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
pub type PWRCTL_AUTO_OFF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWRCTL_AUTO_OFF_A > ; impl < 'a , REG , const O : u8 > PWRCTL_AUTO_OFF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwrctl_auto_off_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwrctl_auto_off_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE) } } impl R { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
# [inline (always)]
pub fn pwrctl_auto_off (& self) -> PWRCTL_AUTO_OFF_R { PWRCTL_AUTO_OFF_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
# [inline (always)]
# [must_use]
pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W < PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwrctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWRCTL_SPEC ; impl crate :: RegisterSpec for PWRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwrctl::R`](R) reader structure"]
impl crate :: Readable for PWRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwrctl::W`](W) writer structure"]
impl crate :: Writable for PWRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWRCTL to value 0"]
impl crate :: Resettable for PWRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`]
module"]
pub type CTL = crate :: Reg < ctl :: CTL_SPEC > ; # [doc = "Control Register"]
pub mod ctl { # [doc = "Register `CTL` reader"]
pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"]
pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_ENABLE` reader - OAxn Enable."]
pub type CTL_ENABLE_R = crate :: BitReader < CTL_ENABLE_A > ; # [doc = "OAxn Enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL_ENABLE_A { # [doc = "0: OFF"]
CTL_ENABLE_OFF = 0 , # [doc = "1: ON"]
CTL_ENABLE_ON = 1 , } impl From < CTL_ENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL_ENABLE_A { match self . bits { false => CTL_ENABLE_A :: CTL_ENABLE_OFF , true => CTL_ENABLE_A :: CTL_ENABLE_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_ctl_enable_off (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_ctl_enable_on (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_ON } } # [doc = "Field `CTL_ENABLE` writer - OAxn Enable."]
pub type CTL_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"]
# [inline (always)]
pub fn ctl_enable_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn ctl_enable_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_ON) } } impl R { # [doc = "Bit 0 - OAxn Enable."]
# [inline (always)]
pub fn ctl_enable (& self) -> CTL_ENABLE_R { CTL_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - OAxn Enable."]
# [inline (always)]
# [must_use]
pub fn ctl_enable (& mut self) -> CTL_ENABLE_W < CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"]
impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"]
impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0"]
impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CFGBASE (rw) register accessor: Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgbase`]
module"]
pub type CFGBASE = crate :: Reg < cfgbase :: CFGBASE_SPEC > ; # [doc = "Configuration Base Register"]
pub mod cfgbase { # [doc = "Register `CFGBASE` reader"]
pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"]
pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"]
CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"]
CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)]
fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"]
# [inline (always)]
pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"]
# [inline (always)]
pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"]
# [inline (always)]
pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"]
# [inline (always)]
pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CFGBASE_RRI_A { # [doc = "0: OFF"]
CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"]
CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)]
fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"]
# [inline (always)]
pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
# [inline (always)]
pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
# [inline (always)]
pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
# [inline (always)]
# [must_use]
pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
# [inline (always)]
# [must_use]
pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"]
impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"]
impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"]
impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CFG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub type CFG = crate :: Reg < cfg :: CFG_SPEC > ; # [doc = "Configuration Register"]
pub mod cfg { # [doc = "Register `CFG` reader"]
pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"]
pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."]
pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_CHOP_A { # [doc = "0: OFF"]
CFG_CHOP_OFF = 0 , # [doc = "1: ON"]
CFG_CHOP_ON = 1 , # [doc = "2: AVGON"]
CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)]
fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"]
# [inline (always)]
pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."]
pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"]
# [inline (always)]
pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"]
# [inline (always)]
pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"]
pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"]
CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"]
CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)]
fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"]
pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_PSEL_A { # [doc = "0: NC"]
CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"]
CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"]
CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"]
CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"]
CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"]
CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"]
CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"]
CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"]
CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)]
fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"]
# [inline (always)]
pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"]
# [inline (always)]
pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"]
# [inline (always)]
pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"]
# [inline (always)]
pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"]
# [inline (always)]
pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"]
# [inline (always)]
pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"]
# [inline (always)]
pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"]
# [inline (always)]
pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"]
# [inline (always)]
pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"]
# [inline (always)]
pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_NSEL_A { # [doc = "0: NC"]
CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"]
CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"]
CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"]
CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"]
CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"]
CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"]
CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)]
fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"]
# [inline (always)]
pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"]
# [inline (always)]
pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"]
# [inline (always)]
pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"]
# [inline (always)]
pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"]
# [inline (always)]
pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"]
# [inline (always)]
pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"]
# [inline (always)]
pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"]
# [inline (always)]
pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"]
# [inline (always)]
pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"]
# [inline (always)]
pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_MSEL_A { # [doc = "0: NC"]
CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"]
CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"]
CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"]
CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"]
CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)]
fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"]
# [inline (always)]
pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"]
# [inline (always)]
pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"]
# [inline (always)]
pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"]
# [inline (always)]
pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"]
# [inline (always)]
pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"]
# [inline (always)]
pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."]
pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."]
pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."]
# [inline (always)]
pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"]
# [inline (always)]
pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."]
# [inline (always)]
pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."]
# [inline (always)]
# [must_use]
pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"]
# [inline (always)]
# [must_use]
pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
# [must_use]
pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
# [must_use]
pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
# [must_use]
pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."]
# [inline (always)]
# [must_use]
pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"]
impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"]
impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RDY` reader - OA ready status."]
pub type STAT_RDY_R = crate :: BitReader < STAT_RDY_A > ; # [doc = "OA ready status.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RDY_A { # [doc = "0: FALSE"]
STAT_RDY_FALSE = 0 , # [doc = "1: TRUE"]
STAT_RDY_TRUE = 1 , } impl From < STAT_RDY_A > for bool { # [inline (always)]
fn from (variant : STAT_RDY_A) -> Self { variant as u8 != 0 } } impl STAT_RDY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RDY_A { match self . bits { false => STAT_RDY_A :: STAT_RDY_FALSE , true => STAT_RDY_A :: STAT_RDY_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_stat_rdy_false (& self) -> bool { * self == STAT_RDY_A :: STAT_RDY_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_stat_rdy_true (& self) -> bool { * self == STAT_RDY_A :: STAT_RDY_TRUE } } impl R { # [doc = "Bit 0 - OA ready status."]
# [inline (always)]
pub fn stat_rdy (& self) -> STAT_RDY_R { STAT_RDY_R :: new ((self . bits & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct TIMG1 { _marker : PhantomData < * const () > } unsafe impl Send for TIMG1 { } impl TIMG1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const timg1 :: RegisterBlock = 0x4008_6000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const timg1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIMG1 { type Target = timg1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIMG1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIMG1") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod timg1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subsciber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , _reserved2 : [u8 ; 0x3c]
, # [doc = "0x444 - Publisher Port 0"]
pub fpub_0 : FPUB_0 , # [doc = "0x448 - Publisher Port 1"]
pub fpub_1 : FPUB_1 , _reserved4 : [u8 ; 0x03b4]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved6 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved7 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1008 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved9 : [u8 ; 0x0c]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved16 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved17 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - CCP Direction"]
pub ccpd : CCPD , # [doc = "0x1104 - Output Disable"]
pub odis : ODIS , # [doc = "0x1108 - Counter Clock Control Register"]
pub cclkctl : CCLKCTL , # [doc = "0x110c - Clock Prescale Register"]
pub cps : CPS , # [doc = "0x1110 - Clock prescale count status register"]
pub cpsv : CPSV , # [doc = "0x1114 - Timer Cross Trigger Control Register"]
pub cttrigctl : CTTRIGCTL , _reserved24 : [u8 ; 0x04]
, # [doc = "0x111c - Timer Cross Trigger Register"]
pub cttrig : CTTRIG , _reserved25 : [u8 ; 0x06e0]
, # [doc = "0x1800 - Counter Register"]
pub ctr : CTR , # [doc = "0x1804 - Counter Control Register"]
pub ctrctl : CTRCTL , # [doc = "0x1808 - Load Register"]
pub load : LOAD , _reserved28 : [u8 ; 0x04]
, # [doc = "0x1810..0x1818 - Capture or Compare Register 0 to Capture or Compare Register 1"]
pub cc_01 : [CC_01 ; 2]
, _reserved29 : [u8 ; 0x18]
, # [doc = "0x1830..0x1838 - Capture or Compare Control Registers"]
pub ccctl_01 : [CCCTL_01 ; 2]
, _reserved30 : [u8 ; 0x18]
, # [doc = "0x1850..0x1858 - CCP Output Control Registers"]
pub octl_01 : [OCTL_01 ; 2]
, _reserved31 : [u8 ; 0x18]
, # [doc = "0x1870..0x1878 - Capture or Compare Action Registers"]
pub ccact_01 : [CCACT_01 ; 2]
, _reserved32 : [u8 ; 0x08]
, # [doc = "0x1880..0x1888 - Input Filter Control Register"]
pub ifctl_01 : [IFCTL_01 ; 2]
, _reserved33 : [u8 ; 0x28]
, # [doc = "0x18b0 - Trigger Select"]
pub tsel : TSEL , } # [doc = "FSUB_0 (rw) register accessor: Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subsciber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_0 (rw) register accessor: Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_0`]
module"]
pub type FPUB_0 = crate :: Reg < fpub_0 :: FPUB_0_SPEC > ; # [doc = "Publisher Port 0"]
pub mod fpub_0 { # [doc = "Register `FPUB_0` reader"]
pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"]
pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"]
impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"]
impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"]
impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher Port 1"]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Interrupt index status"]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: Z"]
IIDX_STAT_Z = 1 , # [doc = "2: L"]
IIDX_STAT_L = 2 , # [doc = "5: CCD0"]
IIDX_STAT_CCD0 = 5 , # [doc = "6: CCD1"]
IIDX_STAT_CCD1 = 6 , # [doc = "7: CCD2"]
IIDX_STAT_CCD2 = 7 , # [doc = "8: CCD3"]
IIDX_STAT_CCD3 = 8 , # [doc = "9: CCU0"]
IIDX_STAT_CCU0 = 9 , # [doc = "10: CCU1"]
IIDX_STAT_CCU1 = 10 , # [doc = "11: CCU2"]
IIDX_STAT_CCU2 = 11 , # [doc = "12: CCU3"]
IIDX_STAT_CCU3 = 12 , # [doc = "13: CCD4"]
IIDX_STAT_CCD4 = 13 , # [doc = "14: CCD5"]
IIDX_STAT_CCD5 = 14 , # [doc = "15: CCU4"]
IIDX_STAT_CCU4 = 15 , # [doc = "16: CCU5"]
IIDX_STAT_CCU5 = 16 , # [doc = "25: F"]
IIDX_STAT_F = 25 , # [doc = "26: TOV"]
IIDX_STAT_TOV = 26 , # [doc = "27: REPC"]
IIDX_STAT_REPC = 27 , # [doc = "28: DC"]
IIDX_STAT_DC = 28 , # [doc = "29: QEIERR"]
IIDX_STAT_QEIERR = 29 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_Z) , 2 => Some (IIDX_STAT_A :: IIDX_STAT_L) , 5 => Some (IIDX_STAT_A :: IIDX_STAT_CCD0) , 6 => Some (IIDX_STAT_A :: IIDX_STAT_CCD1) , 7 => Some (IIDX_STAT_A :: IIDX_STAT_CCD2) , 8 => Some (IIDX_STAT_A :: IIDX_STAT_CCD3) , 9 => Some (IIDX_STAT_A :: IIDX_STAT_CCU0) , 10 => Some (IIDX_STAT_A :: IIDX_STAT_CCU1) , 11 => Some (IIDX_STAT_A :: IIDX_STAT_CCU2) , 12 => Some (IIDX_STAT_A :: IIDX_STAT_CCU3) , 13 => Some (IIDX_STAT_A :: IIDX_STAT_CCD4) , 14 => Some (IIDX_STAT_A :: IIDX_STAT_CCD5) , 15 => Some (IIDX_STAT_A :: IIDX_STAT_CCU4) , 16 => Some (IIDX_STAT_A :: IIDX_STAT_CCU5) , 25 => Some (IIDX_STAT_A :: IIDX_STAT_F) , 26 => Some (IIDX_STAT_A :: IIDX_STAT_TOV) , 27 => Some (IIDX_STAT_A :: IIDX_STAT_REPC) , 28 => Some (IIDX_STAT_A :: IIDX_STAT_DC) , 29 => Some (IIDX_STAT_A :: IIDX_STAT_QEIERR) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "Z"]
# [inline (always)]
pub fn is_iidx_stat_z (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_Z } # [doc = "L"]
# [inline (always)]
pub fn is_iidx_stat_l (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_iidx_stat_ccd0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_iidx_stat_ccd1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_iidx_stat_ccd2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_iidx_stat_ccd3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_iidx_stat_ccu0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_iidx_stat_ccu1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_iidx_stat_ccu2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_iidx_stat_ccu3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU3 } # [doc = "CCD4"]
# [inline (always)]
pub fn is_iidx_stat_ccd4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD4 } # [doc = "CCD5"]
# [inline (always)]
pub fn is_iidx_stat_ccd5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD5 } # [doc = "CCU4"]
# [inline (always)]
pub fn is_iidx_stat_ccu4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU4 } # [doc = "CCU5"]
# [inline (always)]
pub fn is_iidx_stat_ccu5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU5 } # [doc = "F"]
# [inline (always)]
pub fn is_iidx_stat_f (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_F } # [doc = "TOV"]
# [inline (always)]
pub fn is_iidx_stat_tov (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_TOV } # [doc = "REPC"]
# [inline (always)]
pub fn is_iidx_stat_repc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_REPC } # [doc = "DC"]
# [inline (always)]
pub fn is_iidx_stat_dc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DC } # [doc = "QEIERR"]
# [inline (always)]
pub fn is_iidx_stat_qeierr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_QEIERR } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_Z` reader - Zero Event mask"]
pub type IMASK_Z_R = crate :: BitReader < IMASK_Z_A > ; # [doc = "Zero Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_Z_A { # [doc = "0: CLR"]
IMASK_Z_CLR = 0 , # [doc = "1: SET"]
IMASK_Z_SET = 1 , } impl From < IMASK_Z_A > for bool { # [inline (always)]
fn from (variant : IMASK_Z_A) -> Self { variant as u8 != 0 } } impl IMASK_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_Z_A { match self . bits { false => IMASK_Z_A :: IMASK_Z_CLR , true => IMASK_Z_A :: IMASK_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_z_clr (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_z_set (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_SET } } # [doc = "Field `IMASK_Z` writer - Zero Event mask"]
pub type IMASK_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_Z_A > ; impl < 'a , REG , const O : u8 > IMASK_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_SET) } } # [doc = "Field `IMASK_L` reader - Load Event mask"]
pub type IMASK_L_R = crate :: BitReader < IMASK_L_A > ; # [doc = "Load Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_L_A { # [doc = "0: CLR"]
IMASK_L_CLR = 0 , # [doc = "1: SET"]
IMASK_L_SET = 1 , } impl From < IMASK_L_A > for bool { # [inline (always)]
fn from (variant : IMASK_L_A) -> Self { variant as u8 != 0 } } impl IMASK_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_L_A { match self . bits { false => IMASK_L_A :: IMASK_L_CLR , true => IMASK_L_A :: IMASK_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_l_clr (& self) -> bool { * self == IMASK_L_A :: IMASK_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_l_set (& self) -> bool { * self == IMASK_L_A :: IMASK_L_SET } } # [doc = "Field `IMASK_L` writer - Load Event mask"]
pub type IMASK_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_L_A > ; impl < 'a , REG , const O : u8 > IMASK_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_SET) } } # [doc = "Field `IMASK_CCD0` reader - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_R = crate :: BitReader < IMASK_CCD0_A > ; # [doc = "Capture or Compare DN event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD0_A { # [doc = "0: CLR"]
IMASK_CCD0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD0_SET = 1 , } impl From < IMASK_CCD0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD0_A { match self . bits { false => IMASK_CCD0_A :: IMASK_CCD0_CLR , true => IMASK_CCD0_A :: IMASK_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd0_clr (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd0_set (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_SET } } # [doc = "Field `IMASK_CCD0` writer - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_SET) } } # [doc = "Field `IMASK_CCD1` reader - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_R = crate :: BitReader < IMASK_CCD1_A > ; # [doc = "Capture or Compare DN event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD1_A { # [doc = "0: CLR"]
IMASK_CCD1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD1_SET = 1 , } impl From < IMASK_CCD1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD1_A { match self . bits { false => IMASK_CCD1_A :: IMASK_CCD1_CLR , true => IMASK_CCD1_A :: IMASK_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd1_clr (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd1_set (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_SET } } # [doc = "Field `IMASK_CCD1` writer - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_SET) } } # [doc = "Field `IMASK_CCU0` reader - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_R = crate :: BitReader < IMASK_CCU0_A > ; # [doc = "Capture or Compare UP event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU0_A { # [doc = "0: CLR"]
IMASK_CCU0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU0_SET = 1 , } impl From < IMASK_CCU0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU0_A { match self . bits { false => IMASK_CCU0_A :: IMASK_CCU0_CLR , true => IMASK_CCU0_A :: IMASK_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu0_clr (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu0_set (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_SET } } # [doc = "Field `IMASK_CCU0` writer - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_SET) } } # [doc = "Field `IMASK_CCU1` reader - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_R = crate :: BitReader < IMASK_CCU1_A > ; # [doc = "Capture or Compare UP event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU1_A { # [doc = "0: CLR"]
IMASK_CCU1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU1_SET = 1 , } impl From < IMASK_CCU1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU1_A { match self . bits { false => IMASK_CCU1_A :: IMASK_CCU1_CLR , true => IMASK_CCU1_A :: IMASK_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu1_clr (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu1_set (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_SET } } # [doc = "Field `IMASK_CCU1` writer - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_SET) } } # [doc = "Field `IMASK_TOV` reader - Trigger Overflow Event mask"]
pub type IMASK_TOV_R = crate :: BitReader < IMASK_TOV_A > ; # [doc = "Trigger Overflow Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_TOV_A { # [doc = "0: CLR"]
IMASK_TOV_CLR = 0 , # [doc = "1: SET"]
IMASK_TOV_SET = 1 , } impl From < IMASK_TOV_A > for bool { # [inline (always)]
fn from (variant : IMASK_TOV_A) -> Self { variant as u8 != 0 } } impl IMASK_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_TOV_A { match self . bits { false => IMASK_TOV_A :: IMASK_TOV_CLR , true => IMASK_TOV_A :: IMASK_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_tov_clr (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_tov_set (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_SET } } # [doc = "Field `IMASK_TOV` writer - Trigger Overflow Event mask"]
pub type IMASK_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TOV_A > ; impl < 'a , REG , const O : u8 > IMASK_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_SET) } } impl R { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
pub fn imask_z (& self) -> IMASK_Z_R { IMASK_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
pub fn imask_l (& self) -> IMASK_L_R { IMASK_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
pub fn imask_ccd0 (& self) -> IMASK_CCD0_R { IMASK_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
pub fn imask_ccd1 (& self) -> IMASK_CCD1_R { IMASK_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
pub fn imask_ccu0 (& self) -> IMASK_CCU0_R { IMASK_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
pub fn imask_ccu1 (& self) -> IMASK_CCU1_R { IMASK_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
pub fn imask_tov (& self) -> IMASK_TOV_R { IMASK_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_z (& mut self) -> IMASK_Z_W < IMASK_SPEC , 0 > { IMASK_Z_W :: new (self) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_l (& mut self) -> IMASK_L_W < IMASK_SPEC , 1 > { IMASK_L_W :: new (self) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccd0 (& mut self) -> IMASK_CCD0_W < IMASK_SPEC , 4 > { IMASK_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccd1 (& mut self) -> IMASK_CCD1_W < IMASK_SPEC , 5 > { IMASK_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccu0 (& mut self) -> IMASK_CCU0_W < IMASK_SPEC , 8 > { IMASK_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccu1 (& mut self) -> IMASK_CCU1_W < IMASK_SPEC , 9 > { IMASK_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_tov (& mut self) -> IMASK_TOV_W < IMASK_SPEC , 25 > { IMASK_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_Z` reader - Zero event generated an interrupt."]
pub type RIS_Z_R = crate :: BitReader < RIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_Z_A { # [doc = "0: CLR"]
RIS_Z_CLR = 0 , # [doc = "1: SET"]
RIS_Z_SET = 1 , } impl From < RIS_Z_A > for bool { # [inline (always)]
fn from (variant : RIS_Z_A) -> Self { variant as u8 != 0 } } impl RIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_Z_A { match self . bits { false => RIS_Z_A :: RIS_Z_CLR , true => RIS_Z_A :: RIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_z_clr (& self) -> bool { * self == RIS_Z_A :: RIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_z_set (& self) -> bool { * self == RIS_Z_A :: RIS_Z_SET } } # [doc = "Field `RIS_L` reader - Load event generated an interrupt."]
pub type RIS_L_R = crate :: BitReader < RIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_L_A { # [doc = "0: CLR"]
RIS_L_CLR = 0 , # [doc = "1: SET"]
RIS_L_SET = 1 , } impl From < RIS_L_A > for bool { # [inline (always)]
fn from (variant : RIS_L_A) -> Self { variant as u8 != 0 } } impl RIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_L_A { match self . bits { false => RIS_L_A :: RIS_L_CLR , true => RIS_L_A :: RIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_l_clr (& self) -> bool { * self == RIS_L_A :: RIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_l_set (& self) -> bool { * self == RIS_L_A :: RIS_L_SET } } # [doc = "Field `RIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type RIS_CCD0_R = crate :: BitReader < RIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD0_A { # [doc = "0: CLR"]
RIS_CCD0_CLR = 0 , # [doc = "1: SET"]
RIS_CCD0_SET = 1 , } impl From < RIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD0_A) -> Self { variant as u8 != 0 } } impl RIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD0_A { match self . bits { false => RIS_CCD0_A :: RIS_CCD0_CLR , true => RIS_CCD0_A :: RIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd0_clr (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd0_set (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_SET } } # [doc = "Field `RIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type RIS_CCD1_R = crate :: BitReader < RIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD1_A { # [doc = "0: CLR"]
RIS_CCD1_CLR = 0 , # [doc = "1: SET"]
RIS_CCD1_SET = 1 , } impl From < RIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD1_A) -> Self { variant as u8 != 0 } } impl RIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD1_A { match self . bits { false => RIS_CCD1_A :: RIS_CCD1_CLR , true => RIS_CCD1_A :: RIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd1_clr (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd1_set (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_SET } } # [doc = "Field `RIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type RIS_CCU0_R = crate :: BitReader < RIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU0_A { # [doc = "0: CLR"]
RIS_CCU0_CLR = 0 , # [doc = "1: SET"]
RIS_CCU0_SET = 1 , } impl From < RIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU0_A) -> Self { variant as u8 != 0 } } impl RIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU0_A { match self . bits { false => RIS_CCU0_A :: RIS_CCU0_CLR , true => RIS_CCU0_A :: RIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu0_clr (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu0_set (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_SET } } # [doc = "Field `RIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type RIS_CCU1_R = crate :: BitReader < RIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU1_A { # [doc = "0: CLR"]
RIS_CCU1_CLR = 0 , # [doc = "1: SET"]
RIS_CCU1_SET = 1 , } impl From < RIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU1_A) -> Self { variant as u8 != 0 } } impl RIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU1_A { match self . bits { false => RIS_CCU1_A :: RIS_CCU1_CLR , true => RIS_CCU1_A :: RIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu1_clr (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu1_set (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_SET } } # [doc = "Field `RIS_TOV` reader - Trigger overflow"]
pub type RIS_TOV_R = crate :: BitReader < RIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_TOV_A { # [doc = "0: CLR"]
RIS_TOV_CLR = 0 , # [doc = "1: SET"]
RIS_TOV_SET = 1 , } impl From < RIS_TOV_A > for bool { # [inline (always)]
fn from (variant : RIS_TOV_A) -> Self { variant as u8 != 0 } } impl RIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_TOV_A { match self . bits { false => RIS_TOV_A :: RIS_TOV_CLR , true => RIS_TOV_A :: RIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_tov_clr (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_tov_set (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn ris_z (& self) -> RIS_Z_R { RIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn ris_l (& self) -> RIS_L_R { RIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccd0 (& self) -> RIS_CCD0_R { RIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccd1 (& self) -> RIS_CCD1_R { RIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccu0 (& self) -> RIS_CCU0_R { RIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccu1 (& self) -> RIS_CCU1_R { RIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn ris_tov (& self) -> RIS_TOV_R { RIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_Z` reader - Zero event generated an interrupt."]
pub type MIS_Z_R = crate :: BitReader < MIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_Z_A { # [doc = "0: CLR"]
MIS_Z_CLR = 0 , # [doc = "1: SET"]
MIS_Z_SET = 1 , } impl From < MIS_Z_A > for bool { # [inline (always)]
fn from (variant : MIS_Z_A) -> Self { variant as u8 != 0 } } impl MIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_Z_A { match self . bits { false => MIS_Z_A :: MIS_Z_CLR , true => MIS_Z_A :: MIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_z_clr (& self) -> bool { * self == MIS_Z_A :: MIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_z_set (& self) -> bool { * self == MIS_Z_A :: MIS_Z_SET } } # [doc = "Field `MIS_L` reader - Load event generated an interrupt."]
pub type MIS_L_R = crate :: BitReader < MIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_L_A { # [doc = "0: CLR"]
MIS_L_CLR = 0 , # [doc = "1: SET"]
MIS_L_SET = 1 , } impl From < MIS_L_A > for bool { # [inline (always)]
fn from (variant : MIS_L_A) -> Self { variant as u8 != 0 } } impl MIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_L_A { match self . bits { false => MIS_L_A :: MIS_L_CLR , true => MIS_L_A :: MIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_l_clr (& self) -> bool { * self == MIS_L_A :: MIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_l_set (& self) -> bool { * self == MIS_L_A :: MIS_L_SET } } # [doc = "Field `MIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type MIS_CCD0_R = crate :: BitReader < MIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD0_A { # [doc = "0: CLR"]
MIS_CCD0_CLR = 0 , # [doc = "1: SET"]
MIS_CCD0_SET = 1 , } impl From < MIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD0_A) -> Self { variant as u8 != 0 } } impl MIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD0_A { match self . bits { false => MIS_CCD0_A :: MIS_CCD0_CLR , true => MIS_CCD0_A :: MIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd0_clr (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd0_set (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_SET } } # [doc = "Field `MIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type MIS_CCD1_R = crate :: BitReader < MIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD1_A { # [doc = "0: CLR"]
MIS_CCD1_CLR = 0 , # [doc = "1: SET"]
MIS_CCD1_SET = 1 , } impl From < MIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD1_A) -> Self { variant as u8 != 0 } } impl MIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD1_A { match self . bits { false => MIS_CCD1_A :: MIS_CCD1_CLR , true => MIS_CCD1_A :: MIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd1_clr (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd1_set (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_SET } } # [doc = "Field `MIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type MIS_CCU0_R = crate :: BitReader < MIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU0_A { # [doc = "0: CLR"]
MIS_CCU0_CLR = 0 , # [doc = "1: SET"]
MIS_CCU0_SET = 1 , } impl From < MIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU0_A) -> Self { variant as u8 != 0 } } impl MIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU0_A { match self . bits { false => MIS_CCU0_A :: MIS_CCU0_CLR , true => MIS_CCU0_A :: MIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu0_clr (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu0_set (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_SET } } # [doc = "Field `MIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type MIS_CCU1_R = crate :: BitReader < MIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU1_A { # [doc = "0: CLR"]
MIS_CCU1_CLR = 0 , # [doc = "1: SET"]
MIS_CCU1_SET = 1 , } impl From < MIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU1_A) -> Self { variant as u8 != 0 } } impl MIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU1_A { match self . bits { false => MIS_CCU1_A :: MIS_CCU1_CLR , true => MIS_CCU1_A :: MIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu1_clr (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu1_set (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_SET } } # [doc = "Field `MIS_TOV` reader - Trigger overflow"]
pub type MIS_TOV_R = crate :: BitReader < MIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_TOV_A { # [doc = "0: CLR"]
MIS_TOV_CLR = 0 , # [doc = "1: SET"]
MIS_TOV_SET = 1 , } impl From < MIS_TOV_A > for bool { # [inline (always)]
fn from (variant : MIS_TOV_A) -> Self { variant as u8 != 0 } } impl MIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_TOV_A { match self . bits { false => MIS_TOV_A :: MIS_TOV_CLR , true => MIS_TOV_A :: MIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_tov_clr (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_tov_set (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn mis_z (& self) -> MIS_Z_R { MIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn mis_l (& self) -> MIS_L_R { MIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccd0 (& self) -> MIS_CCD0_R { MIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccd1 (& self) -> MIS_CCD1_R { MIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccu0 (& self) -> MIS_CCU0_R { MIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccu1 (& self) -> MIS_CCU1_R { MIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn mis_tov (& self) -> MIS_TOV_R { MIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Zero event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_Z_AW { # [doc = "0: NO_EFFECT"]
ISET_Z_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_Z_SET = 1 , } impl From < ISET_Z_AW > for bool { # [inline (always)]
fn from (variant : ISET_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_Z` writer - Zero event SET"]
pub type ISET_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_Z_AW > ; impl < 'a , REG , const O : u8 > ISET_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_SET) } } # [doc = "Load event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_L_AW { # [doc = "0: NO_EFFECT"]
ISET_L_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_L_SET = 1 , } impl From < ISET_L_AW > for bool { # [inline (always)]
fn from (variant : ISET_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_L` writer - Load event SET"]
pub type ISET_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_L_AW > ; impl < 'a , REG , const O : u8 > ISET_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD0_SET = 1 , } impl From < ISET_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD0` writer - Capture or compare down event SET"]
pub type ISET_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD1_SET = 1 , } impl From < ISET_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD1` writer - Capture or compare down event SET"]
pub type ISET_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU0_SET = 1 , } impl From < ISET_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU0` writer - Capture or compare up event SET"]
pub type ISET_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU1_SET = 1 , } impl From < ISET_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU1` writer - Capture or compare up event SET"]
pub type ISET_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_SET) } } # [doc = "Trigger Overflow event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_TOV_AW { # [doc = "0: NO_EFFECT"]
ISET_TOV_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_TOV_SET = 1 , } impl From < ISET_TOV_AW > for bool { # [inline (always)]
fn from (variant : ISET_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_TOV` writer - Trigger Overflow event SET"]
pub type ISET_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_TOV_AW > ; impl < 'a , REG , const O : u8 > ISET_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_SET) } } impl W { # [doc = "Bit 0 - Zero event SET"]
# [inline (always)]
# [must_use]
pub fn iset_z (& mut self) -> ISET_Z_W < ISET_SPEC , 0 > { ISET_Z_W :: new (self) } # [doc = "Bit 1 - Load event SET"]
# [inline (always)]
# [must_use]
pub fn iset_l (& mut self) -> ISET_L_W < ISET_SPEC , 1 > { ISET_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd0 (& mut self) -> ISET_CCD0_W < ISET_SPEC , 4 > { ISET_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd1 (& mut self) -> ISET_CCD1_W < ISET_SPEC , 5 > { ISET_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu0 (& mut self) -> ISET_CCU0_W < ISET_SPEC , 8 > { ISET_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu1 (& mut self) -> ISET_CCU1_W < ISET_SPEC , 9 > { ISET_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event SET"]
# [inline (always)]
# [must_use]
pub fn iset_tov (& mut self) -> ISET_TOV_W < ISET_SPEC , 25 > { ISET_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Zero event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_Z_AW { # [doc = "0: NO_EFFECT"]
ICLR_Z_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_Z_CLR = 1 , } impl From < ICLR_Z_AW > for bool { # [inline (always)]
fn from (variant : ICLR_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_Z` writer - Zero event CLEAR"]
pub type ICLR_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_Z_AW > ; impl < 'a , REG , const O : u8 > ICLR_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_CLR) } } # [doc = "Load event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_L_AW { # [doc = "0: NO_EFFECT"]
ICLR_L_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_L_CLR = 1 , } impl From < ICLR_L_AW > for bool { # [inline (always)]
fn from (variant : ICLR_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_L` writer - Load event CLEAR"]
pub type ICLR_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_L_AW > ; impl < 'a , REG , const O : u8 > ICLR_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD0_CLR = 1 , } impl From < ICLR_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD0` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD1_CLR = 1 , } impl From < ICLR_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD1` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU0_CLR = 1 , } impl From < ICLR_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU0` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU1_CLR = 1 , } impl From < ICLR_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU1` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_CLR) } } # [doc = "Trigger Overflow event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_TOV_AW { # [doc = "0: NO_EFFECT"]
ICLR_TOV_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_TOV_CLR = 1 , } impl From < ICLR_TOV_AW > for bool { # [inline (always)]
fn from (variant : ICLR_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_TOV` writer - Trigger Overflow event CLEAR"]
pub type ICLR_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_TOV_AW > ; impl < 'a , REG , const O : u8 > ICLR_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_CLR) } } impl W { # [doc = "Bit 0 - Zero event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_z (& mut self) -> ICLR_Z_W < ICLR_SPEC , 0 > { ICLR_Z_W :: new (self) } # [doc = "Bit 1 - Load event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_l (& mut self) -> ICLR_L_W < ICLR_SPEC , 1 > { ICLR_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd0 (& mut self) -> ICLR_CCD0_W < ICLR_SPEC , 4 > { ICLR_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd1 (& mut self) -> ICLR_CCD1_W < ICLR_SPEC , 5 > { ICLR_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu0 (& mut self) -> ICLR_CCU0_W < ICLR_SPEC , 8 > { ICLR_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu1 (& mut self) -> ICLR_CCU1_W < ICLR_SPEC , 9 > { ICLR_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_tov (& mut self) -> ICLR_TOV_W < ICLR_SPEC , 25 > { ICLR_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_EVT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
pub type EVT_MODE_EVT0_CFG_R = crate :: FieldReader < EVT_MODE_EVT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_software (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
# [inline (always)]
pub fn evt_mode_evt0_cfg (& self) -> EVT_MODE_EVT0_CFG_R { EVT_MODE_EVT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0x29"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0x29 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCPD (rw) register accessor: CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccpd`]
module"]
pub type CCPD = crate :: Reg < ccpd :: CCPD_SPEC > ; # [doc = "CCP Direction"]
pub mod ccpd { # [doc = "Register `CCPD` reader"]
pub type R = crate :: R < CCPD_SPEC > ; # [doc = "Register `CCPD` writer"]
pub type W = crate :: W < CCPD_SPEC > ; # [doc = "Field `CCPD_C0CCP0` reader - Counter CCP0"]
pub type CCPD_C0CCP0_R = crate :: BitReader < CCPD_C0CCP0_A > ; # [doc = "Counter CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP0_A { # [doc = "0: INPUT"]
CCPD_C0CCP0_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP0_OUTPUT = 1 , } impl From < CCPD_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP0_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP0_A { match self . bits { false => CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT , true => CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_input (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_output (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT } } # [doc = "Field `CCPD_C0CCP0` writer - Counter CCP0"]
pub type CCPD_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP0_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT) } } # [doc = "Field `CCPD_C0CCP1` reader - Counter CCP1"]
pub type CCPD_C0CCP1_R = crate :: BitReader < CCPD_C0CCP1_A > ; # [doc = "Counter CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP1_A { # [doc = "0: INPUT"]
CCPD_C0CCP1_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP1_OUTPUT = 1 , } impl From < CCPD_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP1_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP1_A { match self . bits { false => CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT , true => CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_input (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_output (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT } } # [doc = "Field `CCPD_C0CCP1` writer - Counter CCP1"]
pub type CCPD_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP1_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT) } } impl R { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
pub fn ccpd_c0ccp0 (& self) -> CCPD_C0CCP0_R { CCPD_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
pub fn ccpd_c0ccp1 (& self) -> CCPD_C0CCP1_R { CCPD_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp0 (& mut self) -> CCPD_C0CCP0_W < CCPD_SPEC , 0 > { CCPD_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp1 (& mut self) -> CCPD_C0CCP1_W < CCPD_SPEC , 1 > { CCPD_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCPD_SPEC ; impl crate :: RegisterSpec for CCPD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccpd::R`](R) reader structure"]
impl crate :: Readable for CCPD_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccpd::W`](W) writer structure"]
impl crate :: Writable for CCPD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCPD to value 0"]
impl crate :: Resettable for CCPD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ODIS (rw) register accessor: Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@odis`]
module"]
pub type ODIS = crate :: Reg < odis :: ODIS_SPEC > ; # [doc = "Output Disable"]
pub mod odis { # [doc = "Register `ODIS` reader"]
pub type R = crate :: R < ODIS_SPEC > ; # [doc = "Register `ODIS` writer"]
pub type W = crate :: W < ODIS_SPEC > ; # [doc = "Field `ODIS_C0CCP0` reader - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_R = crate :: BitReader < ODIS_C0CCP0_A > ; # [doc = "Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP0_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP0_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP0_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP0_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP0_A { match self . bits { false => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL , true => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP0` writer - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP0_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW) } } # [doc = "Field `ODIS_C0CCP1` reader - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_R = crate :: BitReader < ODIS_C0CCP1_A > ; # [doc = "Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP1_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP1_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP1_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP1_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP1_A { match self . bits { false => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL , true => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP1` writer - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP1_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW) } } impl R { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp0 (& self) -> ODIS_C0CCP0_R { ODIS_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp1 (& self) -> ODIS_C0CCP1_R { ODIS_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp0 (& mut self) -> ODIS_C0CCP0_W < ODIS_SPEC , 0 > { ODIS_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp1 (& mut self) -> ODIS_C0CCP1_W < ODIS_SPEC , 1 > { ODIS_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ODIS_SPEC ; impl crate :: RegisterSpec for ODIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`odis::R`](R) reader structure"]
impl crate :: Readable for ODIS_SPEC { } # [doc = "`write(|w| ..)` method takes [`odis::W`](W) writer structure"]
impl crate :: Writable for ODIS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ODIS to value 0"]
impl crate :: Resettable for ODIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCLKCTL (rw) register accessor: Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cclkctl`]
module"]
pub type CCLKCTL = crate :: Reg < cclkctl :: CCLKCTL_SPEC > ; # [doc = "Counter Clock Control Register"]
pub mod cclkctl { # [doc = "Register `CCLKCTL` reader"]
pub type R = crate :: R < CCLKCTL_SPEC > ; # [doc = "Register `CCLKCTL` writer"]
pub type W = crate :: W < CCLKCTL_SPEC > ; # [doc = "Field `CCLKCTL_CLKEN` reader - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_R = crate :: BitReader < CCLKCTL_CLKEN_A > ; # [doc = "Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCLKCTL_CLKEN_A { # [doc = "0: DISABLED"]
CCLKCTL_CLKEN_DISABLED = 0 , # [doc = "1: ENABLED"]
CCLKCTL_CLKEN_ENABLED = 1 , } impl From < CCLKCTL_CLKEN_A > for bool { # [inline (always)]
fn from (variant : CCLKCTL_CLKEN_A) -> Self { variant as u8 != 0 } } impl CCLKCTL_CLKEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCLKCTL_CLKEN_A { match self . bits { false => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED , true => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_disabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_enabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED } } # [doc = "Field `CCLKCTL_CLKEN` writer - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCLKCTL_CLKEN_A > ; impl < 'a , REG , const O : u8 > CCLKCTL_CLKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cclkctl_clken_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn cclkctl_clken_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED) } } impl R { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
pub fn cclkctl_clken (& self) -> CCLKCTL_CLKEN_R { CCLKCTL_CLKEN_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
# [must_use]
pub fn cclkctl_clken (& mut self) -> CCLKCTL_CLKEN_W < CCLKCTL_SPEC , 0 > { CCLKCTL_CLKEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCLKCTL_SPEC ; impl crate :: RegisterSpec for CCLKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cclkctl::R`](R) reader structure"]
impl crate :: Readable for CCLKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cclkctl::W`](W) writer structure"]
impl crate :: Writable for CCLKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCLKCTL to value 0"]
impl crate :: Resettable for CCLKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPS (rw) register accessor: Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cps`]
module"]
pub type CPS = crate :: Reg < cps :: CPS_SPEC > ; # [doc = "Clock Prescale Register"]
pub mod cps { # [doc = "Register `CPS` reader"]
pub type R = crate :: R < CPS_SPEC > ; # [doc = "Register `CPS` writer"]
pub type W = crate :: W < CPS_SPEC > ; # [doc = "Field `CPS_PCNT` reader - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_R = crate :: FieldReader ; # [doc = "Field `CPS_PCNT` writer - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
pub fn cps_pcnt (& self) -> CPS_PCNT_R { CPS_PCNT_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
# [must_use]
pub fn cps_pcnt (& mut self) -> CPS_PCNT_W < CPS_SPEC , 0 > { CPS_PCNT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPS_SPEC ; impl crate :: RegisterSpec for CPS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cps::R`](R) reader structure"]
impl crate :: Readable for CPS_SPEC { } # [doc = "`write(|w| ..)` method takes [`cps::W`](W) writer structure"]
impl crate :: Writable for CPS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CPS to value 0"]
impl crate :: Resettable for CPS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPSV (r) register accessor: Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpsv`]
module"]
pub type CPSV = crate :: Reg < cpsv :: CPSV_SPEC > ; # [doc = "Clock prescale count status register"]
pub mod cpsv { # [doc = "Register `CPSV` reader"]
pub type R = crate :: R < CPSV_SPEC > ; # [doc = "Field `CPSV_CPSVAL` reader - Current Prescale Count Value"]
pub type CPSV_CPSVAL_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Current Prescale Count Value"]
# [inline (always)]
pub fn cpsv_cpsval (& self) -> CPSV_CPSVAL_R { CPSV_CPSVAL_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPSV_SPEC ; impl crate :: RegisterSpec for CPSV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cpsv::R`](R) reader structure"]
impl crate :: Readable for CPSV_SPEC { } # [doc = "`reset()` method sets CPSV to value 0"]
impl crate :: Resettable for CPSV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIGCTL (rw) register accessor: Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrigctl`]
module"]
pub type CTTRIGCTL = crate :: Reg < cttrigctl :: CTTRIGCTL_SPEC > ; # [doc = "Timer Cross Trigger Control Register"]
pub mod cttrigctl { # [doc = "Register `CTTRIGCTL` reader"]
pub type R = crate :: R < CTTRIGCTL_SPEC > ; # [doc = "Register `CTTRIGCTL` writer"]
pub type W = crate :: W < CTTRIGCTL_SPEC > ; # [doc = "Field `CTTRIGCTL_CTEN` reader - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_R = crate :: BitReader < CTTRIGCTL_CTEN_A > ; # [doc = "Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_CTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_CTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_CTEN_ENABLE = 1 , } impl From < CTTRIGCTL_CTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_CTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_CTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_CTEN_A { match self . bits { false => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED , true => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_cten_disabled (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_cten_enable (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_CTEN` writer - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_CTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_CTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_cten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_cten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTEN` reader - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_R = crate :: BitReader < CTTRIGCTL_EVTCTEN_A > ; # [doc = "Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_EVTCTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_EVTCTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_EVTCTEN_ENABLE = 1 , } impl From < CTTRIGCTL_EVTCTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_EVTCTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_EVTCTEN_A { match self . bits { false => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED , true => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_disabled (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_enable (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_EVTCTEN` writer - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_EVTCTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_evtcten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_evtcten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` reader - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_R = crate :: FieldReader < CTTRIGCTL_EVTCTTRIGSEL_A > ; # [doc = "Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTTRIGCTL_EVTCTTRIGSEL_A { # [doc = "0: FSUB0"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB0 = 0 , # [doc = "1: FSUB1"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB1 = 1 , # [doc = "2: Z"]
CTTRIGCTL_EVTCTTRIGSEL_Z = 2 , # [doc = "3: L"]
CTTRIGCTL_EVTCTTRIGSEL_L = 3 , # [doc = "4: CCD0"]
CTTRIGCTL_EVTCTTRIGSEL_CCD0 = 4 , # [doc = "5: CCD1"]
CTTRIGCTL_EVTCTTRIGSEL_CCD1 = 5 , # [doc = "6: CCD2"]
CTTRIGCTL_EVTCTTRIGSEL_CCD2 = 6 , # [doc = "7: CCD3"]
CTTRIGCTL_EVTCTTRIGSEL_CCD3 = 7 , # [doc = "8: CCU0"]
CTTRIGCTL_EVTCTTRIGSEL_CCU0 = 8 , # [doc = "9: CCU1"]
CTTRIGCTL_EVTCTTRIGSEL_CCU1 = 9 , # [doc = "10: CCU2"]
CTTRIGCTL_EVTCTTRIGSEL_CCU2 = 10 , # [doc = "11: CCU3"]
CTTRIGCTL_EVTCTTRIGSEL_CCU3 = 11 , } impl From < CTTRIGCTL_EVTCTTRIGSEL_A > for u8 { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTTRIGSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTTRIGCTL_EVTCTTRIGSEL_A { type Ux = u8 ; } impl CTTRIGCTL_EVTCTTRIGSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTTRIGCTL_EVTCTTRIGSEL_A > { match self . bits { 0 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) , 1 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) , 2 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) , 3 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) , 4 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) , 5 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) , 6 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) , 7 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) , 8 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) , 9 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) , 10 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) , 11 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) , _ => None , } } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1 } # [doc = "Z"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_z (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z } # [doc = "L"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_l (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3 } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` writer - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CTTRIGCTL_EVTCTTRIGSEL_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FSUB0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) } # [doc = "Z"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_z (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) } # [doc = "L"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_l (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) } # [doc = "CCD0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) } # [doc = "CCD1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) } # [doc = "CCD2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) } # [doc = "CCD3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) } # [doc = "CCU0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) } # [doc = "CCU1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) } # [doc = "CCU2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) } # [doc = "CCU3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) } } impl R { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
pub fn cttrigctl_cten (& self) -> CTTRIGCTL_CTEN_R { CTTRIGCTL_CTEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcten (& self) -> CTTRIGCTL_EVTCTEN_R { CTTRIGCTL_EVTCTEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel (& self) -> CTTRIGCTL_EVTCTTRIGSEL_R { CTTRIGCTL_EVTCTTRIGSEL_R :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
# [must_use]
pub fn cttrigctl_cten (& mut self) -> CTTRIGCTL_CTEN_W < CTTRIGCTL_SPEC , 0 > { CTTRIGCTL_CTEN_W :: new (self) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcten (& mut self) -> CTTRIGCTL_EVTCTEN_W < CTTRIGCTL_SPEC , 1 > { CTTRIGCTL_EVTCTEN_W :: new (self) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcttrigsel (& mut self) -> CTTRIGCTL_EVTCTTRIGSEL_W < CTTRIGCTL_SPEC , 16 > { CTTRIGCTL_EVTCTTRIGSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIGCTL_SPEC ; impl crate :: RegisterSpec for CTTRIGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cttrigctl::R`](R) reader structure"]
impl crate :: Readable for CTTRIGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cttrigctl::W`](W) writer structure"]
impl crate :: Writable for CTTRIGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIGCTL to value 0"]
impl crate :: Resettable for CTTRIGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIG (w) register accessor: Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrig`]
module"]
pub type CTTRIG = crate :: Reg < cttrig :: CTTRIG_SPEC > ; # [doc = "Timer Cross Trigger Register"]
pub mod cttrig { # [doc = "Register `CTTRIG` writer"]
pub type W = crate :: W < CTTRIG_SPEC > ; # [doc = "Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIG_TRIG_AW { # [doc = "0: DISABLED"]
CTTRIG_TRIG_DISABLED = 0 , # [doc = "1: GENERATE"]
CTTRIG_TRIG_GENERATE = 1 , } impl From < CTTRIG_TRIG_AW > for bool { # [inline (always)]
fn from (variant : CTTRIG_TRIG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `CTTRIG_TRIG` writer - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
pub type CTTRIG_TRIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIG_TRIG_AW > ; impl < 'a , REG , const O : u8 > CTTRIG_TRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrig_trig_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_DISABLED) } # [doc = "GENERATE"]
# [inline (always)]
pub fn cttrig_trig_generate (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_GENERATE) } } impl W { # [doc = "Bit 0 - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
# [inline (always)]
# [must_use]
pub fn cttrig_trig (& mut self) -> CTTRIG_TRIG_W < CTTRIG_SPEC , 0 > { CTTRIG_TRIG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIG_SPEC ; impl crate :: RegisterSpec for CTTRIG_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`cttrig::W`](W) writer structure"]
impl crate :: Writable for CTTRIG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIG to value 0"]
impl crate :: Resettable for CTTRIG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTR (rw) register accessor: Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`]
module"]
pub type CTR = crate :: Reg < ctr :: CTR_SPEC > ; # [doc = "Counter Register"]
pub mod ctr { # [doc = "Register `CTR` reader"]
pub type R = crate :: R < CTR_SPEC > ; # [doc = "Register `CTR` writer"]
pub type W = crate :: W < CTR_SPEC > ; # [doc = "Field `CTR_CCTR` reader - Current Counter value"]
pub type CTR_CCTR_R = crate :: FieldReader < u16 > ; # [doc = "Field `CTR_CCTR` writer - Current Counter value"]
pub type CTR_CCTR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
pub fn ctr_cctr (& self) -> CTR_CCTR_R { CTR_CCTR_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
# [must_use]
pub fn ctr_cctr (& mut self) -> CTR_CCTR_W < CTR_SPEC , 0 > { CTR_CCTR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTR_SPEC ; impl crate :: RegisterSpec for CTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctr::R`](R) reader structure"]
impl crate :: Readable for CTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
impl crate :: Writable for CTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTR to value 0"]
impl crate :: Resettable for CTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTRCTL (rw) register accessor: Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrctl`]
module"]
pub type CTRCTL = crate :: Reg < ctrctl :: CTRCTL_SPEC > ; # [doc = "Counter Control Register"]
pub mod ctrctl { # [doc = "Register `CTRCTL` reader"]
pub type R = crate :: R < CTRCTL_SPEC > ; # [doc = "Register `CTRCTL` writer"]
pub type W = crate :: W < CTRCTL_SPEC > ; # [doc = "Field `CTRCTL_EN` reader - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_R = crate :: BitReader < CTRCTL_EN_A > ; # [doc = "Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_EN_A { # [doc = "0: DISABLED"]
CTRCTL_EN_DISABLED = 0 , # [doc = "1: ENABLED"]
CTRCTL_EN_ENABLED = 1 , } impl From < CTRCTL_EN_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_EN_A) -> Self { variant as u8 != 0 } } impl CTRCTL_EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_EN_A { match self . bits { false => CTRCTL_EN_A :: CTRCTL_EN_DISABLED , true => CTRCTL_EN_A :: CTRCTL_EN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ctrctl_en_disabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ctrctl_en_enabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_ENABLED } } # [doc = "Field `CTRCTL_EN` writer - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_EN_A > ; impl < 'a , REG , const O : u8 > CTRCTL_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ctrctl_en_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ctrctl_en_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_ENABLED) } } # [doc = "Field `CTRCTL_REPEAT` reader - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_R = crate :: FieldReader < CTRCTL_REPEAT_A > ; # [doc = "Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_REPEAT_A { # [doc = "0: REPEAT_0"]
CTRCTL_REPEAT_REPEAT_0 = 0 , # [doc = "1: REPEAT_1"]
CTRCTL_REPEAT_REPEAT_1 = 1 , # [doc = "2: REPEAT_2"]
CTRCTL_REPEAT_REPEAT_2 = 2 , # [doc = "3: REPEAT_3"]
CTRCTL_REPEAT_REPEAT_3 = 3 , # [doc = "4: REPEAT_4"]
CTRCTL_REPEAT_REPEAT_4 = 4 , } impl From < CTRCTL_REPEAT_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_REPEAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_REPEAT_A { type Ux = u8 ; } impl CTRCTL_REPEAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_REPEAT_A > { match self . bits { 0 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) , 1 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) , 2 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) , 3 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) , 4 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) , _ => None , } } # [doc = "REPEAT_0"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_0 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0 } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_1 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1 } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_2 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2 } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_3 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3 } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_4 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4 } } # [doc = "Field `CTRCTL_REPEAT` writer - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_REPEAT_A > ; impl < 'a , REG , const O : u8 > CTRCTL_REPEAT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "REPEAT_0"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) } } # [doc = "Field `CTRCTL_CM` reader - Count Mode"]
pub type CTRCTL_CM_R = crate :: FieldReader < CTRCTL_CM_A > ; # [doc = "Count Mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CM_A { # [doc = "0: DOWN"]
CTRCTL_CM_DOWN = 0 , # [doc = "1: UP_DOWN"]
CTRCTL_CM_UP_DOWN = 1 , # [doc = "2: UP"]
CTRCTL_CM_UP = 2 , } impl From < CTRCTL_CM_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CM_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CM_A { type Ux = u8 ; } impl CTRCTL_CM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CM_A > { match self . bits { 0 => Some (CTRCTL_CM_A :: CTRCTL_CM_DOWN) , 1 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) , 2 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP) , _ => None , } } # [doc = "DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_DOWN } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_up_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN } # [doc = "UP"]
# [inline (always)]
pub fn is_ctrctl_cm_up (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP } } # [doc = "Field `CTRCTL_CM` writer - Count Mode"]
pub type CTRCTL_CM_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CM_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DOWN"]
# [inline (always)]
pub fn ctrctl_cm_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_DOWN) } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn ctrctl_cm_up_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) } # [doc = "UP"]
# [inline (always)]
pub fn ctrctl_cm_up (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP) } } # [doc = "Field `CTRCTL_CLC` reader - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_R = crate :: FieldReader < CTRCTL_CLC_A > ; # [doc = "Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CLC_A { # [doc = "0: CCCTL0_LCOND"]
CTRCTL_CLC_CCCTL0_LCOND = 0 , # [doc = "1: CCCTL1_LCOND"]
CTRCTL_CLC_CCCTL1_LCOND = 1 , # [doc = "2: CCCTL2_LCOND"]
CTRCTL_CLC_CCCTL2_LCOND = 2 , # [doc = "3: CCCTL3_LCOND"]
CTRCTL_CLC_CCCTL3_LCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CLC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CLC_QEI_3INP = 5 , } impl From < CTRCTL_CLC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CLC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CLC_A { type Ux = u8 ; } impl CTRCTL_CLC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CLC_A > { match self . bits { 0 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) , 1 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) , 2 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) , 3 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) , 4 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) , 5 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl0_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl1_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl2_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl3_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_2inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_3inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP } } # [doc = "Field `CTRCTL_CLC` writer - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CLC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CLC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl0_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl1_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl2_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl3_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) } } # [doc = "Field `CTRCTL_CAC` reader - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_R = crate :: FieldReader < CTRCTL_CAC_A > ; # [doc = "Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CAC_A { # [doc = "0: CCCTL0_ACOND"]
CTRCTL_CAC_CCCTL0_ACOND = 0 , # [doc = "1: CCCTL1_ACOND"]
CTRCTL_CAC_CCCTL1_ACOND = 1 , # [doc = "2: CCCTL2_ACOND"]
CTRCTL_CAC_CCCTL2_ACOND = 2 , # [doc = "3: CCCTL3_ACOND"]
CTRCTL_CAC_CCCTL3_ACOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CAC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CAC_QEI_3INP = 5 , } impl From < CTRCTL_CAC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CAC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CAC_A { type Ux = u8 ; } impl CTRCTL_CAC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CAC_A > { match self . bits { 0 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) , 1 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) , 2 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) , 3 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) , 4 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) , 5 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl0_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl1_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl2_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl3_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_2inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_3inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP } } # [doc = "Field `CTRCTL_CAC` writer - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CAC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CAC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl0_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl1_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl2_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl3_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) } } # [doc = "Field `CTRCTL_CZC` reader - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_R = crate :: FieldReader < CTRCTL_CZC_A > ; # [doc = "Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CZC_A { # [doc = "0: CCCTL0_ZCOND"]
CTRCTL_CZC_CCCTL0_ZCOND = 0 , # [doc = "1: CCCTL1_ZCOND"]
CTRCTL_CZC_CCCTL1_ZCOND = 1 , # [doc = "2: CCCTL2_ZCOND"]
CTRCTL_CZC_CCCTL2_ZCOND = 2 , # [doc = "3: CCCTL3_ZCOND"]
CTRCTL_CZC_CCCTL3_ZCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CZC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CZC_QEI_3INP = 5 , } impl From < CTRCTL_CZC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CZC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CZC_A { type Ux = u8 ; } impl CTRCTL_CZC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CZC_A > { match self . bits { 0 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) , 1 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) , 2 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) , 3 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) , 4 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) , 5 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl0_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl1_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl2_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl3_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_2inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_3inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP } } # [doc = "Field `CTRCTL_CZC` writer - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CZC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CZC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl0_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl1_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl2_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl3_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) } } # [doc = "Field `CTRCTL_DRB` reader - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_R = crate :: BitReader < CTRCTL_DRB_A > ; # [doc = "Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_DRB_A { # [doc = "0: RESUME"]
CTRCTL_DRB_RESUME = 0 , # [doc = "1: CVAE_ACTION"]
CTRCTL_DRB_CVAE_ACTION = 1 , } impl From < CTRCTL_DRB_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_DRB_A) -> Self { variant as u8 != 0 } } impl CTRCTL_DRB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_DRB_A { match self . bits { false => CTRCTL_DRB_A :: CTRCTL_DRB_RESUME , true => CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION , } } # [doc = "RESUME"]
# [inline (always)]
pub fn is_ctrctl_drb_resume (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_RESUME } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn is_ctrctl_drb_cvae_action (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION } } # [doc = "Field `CTRCTL_DRB` writer - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_DRB_A > ; impl < 'a , REG , const O : u8 > CTRCTL_DRB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RESUME"]
# [inline (always)]
pub fn ctrctl_drb_resume (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_RESUME) } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn ctrctl_drb_cvae_action (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION) } } # [doc = "Field `CTRCTL_CVAE` reader - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_R = crate :: FieldReader < CTRCTL_CVAE_A > ; # [doc = "Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CVAE_A { # [doc = "0: LDVAL"]
CTRCTL_CVAE_LDVAL = 0 , # [doc = "1: NOCHANGE"]
CTRCTL_CVAE_NOCHANGE = 1 , # [doc = "2: ZEROVAL"]
CTRCTL_CVAE_ZEROVAL = 2 , } impl From < CTRCTL_CVAE_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CVAE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CVAE_A { type Ux = u8 ; } impl CTRCTL_CVAE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CVAE_A > { match self . bits { 0 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) , 1 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) , 2 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) , _ => None , } } # [doc = "LDVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_ldval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn is_ctrctl_cvae_nochange (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_zeroval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL } } # [doc = "Field `CTRCTL_CVAE` writer - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CVAE_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CVAE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LDVAL"]
# [inline (always)]
pub fn ctrctl_cvae_ldval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn ctrctl_cvae_nochange (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn ctrctl_cvae_zeroval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) } } impl R { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
pub fn ctrctl_en (& self) -> CTRCTL_EN_R { CTRCTL_EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
pub fn ctrctl_repeat (& self) -> CTRCTL_REPEAT_R { CTRCTL_REPEAT_R :: new (((self . bits >> 1) & 7) as u8) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
pub fn ctrctl_cm (& self) -> CTRCTL_CM_R { CTRCTL_CM_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_clc (& self) -> CTRCTL_CLC_R { CTRCTL_CLC_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_cac (& self) -> CTRCTL_CAC_R { CTRCTL_CAC_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_czc (& self) -> CTRCTL_CZC_R { CTRCTL_CZC_R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
pub fn ctrctl_drb (& self) -> CTRCTL_DRB_R { CTRCTL_DRB_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
pub fn ctrctl_cvae (& self) -> CTRCTL_CVAE_R { CTRCTL_CVAE_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
# [must_use]
pub fn ctrctl_en (& mut self) -> CTRCTL_EN_W < CTRCTL_SPEC , 0 > { CTRCTL_EN_W :: new (self) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
# [must_use]
pub fn ctrctl_repeat (& mut self) -> CTRCTL_REPEAT_W < CTRCTL_SPEC , 1 > { CTRCTL_REPEAT_W :: new (self) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
# [must_use]
pub fn ctrctl_cm (& mut self) -> CTRCTL_CM_W < CTRCTL_SPEC , 4 > { CTRCTL_CM_W :: new (self) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_clc (& mut self) -> CTRCTL_CLC_W < CTRCTL_SPEC , 7 > { CTRCTL_CLC_W :: new (self) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cac (& mut self) -> CTRCTL_CAC_W < CTRCTL_SPEC , 10 > { CTRCTL_CAC_W :: new (self) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_czc (& mut self) -> CTRCTL_CZC_W < CTRCTL_SPEC , 13 > { CTRCTL_CZC_W :: new (self) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
# [must_use]
pub fn ctrctl_drb (& mut self) -> CTRCTL_DRB_W < CTRCTL_SPEC , 17 > { CTRCTL_DRB_W :: new (self) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cvae (& mut self) -> CTRCTL_CVAE_W < CTRCTL_SPEC , 28 > { CTRCTL_CVAE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRCTL_SPEC ; impl crate :: RegisterSpec for CTRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctrctl::R`](R) reader structure"]
impl crate :: Readable for CTRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctrctl::W`](W) writer structure"]
impl crate :: Writable for CTRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTRCTL to value 0xff80"]
impl crate :: Resettable for CTRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0xff80 ; } } # [doc = "LOAD (rw) register accessor: Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load`]
module"]
pub type LOAD = crate :: Reg < load :: LOAD_SPEC > ; # [doc = "Load Register"]
pub mod load { # [doc = "Register `LOAD` reader"]
pub type R = crate :: R < LOAD_SPEC > ; # [doc = "Register `LOAD` writer"]
pub type W = crate :: W < LOAD_SPEC > ; # [doc = "Field `LOAD_LD` reader - Load Value"]
pub type LOAD_LD_R = crate :: FieldReader < u16 > ; # [doc = "Field `LOAD_LD` writer - Load Value"]
pub type LOAD_LD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
pub fn load_ld (& self) -> LOAD_LD_R { LOAD_LD_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
# [must_use]
pub fn load_ld (& mut self) -> LOAD_LD_W < LOAD_SPEC , 0 > { LOAD_LD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LOAD_SPEC ; impl crate :: RegisterSpec for LOAD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`load::R`](R) reader structure"]
impl crate :: Readable for LOAD_SPEC { } # [doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"]
impl crate :: Writable for LOAD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LOAD to value 0"]
impl crate :: Resettable for LOAD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CC_01 (rw) register accessor: Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cc_01`]
module"]
pub type CC_01 = crate :: Reg < cc_01 :: CC_01_SPEC > ; # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1"]
pub mod cc_01 { # [doc = "Register `CC_01[%s]` reader"]
pub type R = crate :: R < CC_01_SPEC > ; # [doc = "Register `CC_01[%s]` writer"]
pub type W = crate :: W < CC_01_SPEC > ; # [doc = "Field `CC_01_CCVAL` reader - Capture or compare value"]
pub type CC_01_CCVAL_R = crate :: FieldReader < u16 > ; # [doc = "Field `CC_01_CCVAL` writer - Capture or compare value"]
pub type CC_01_CCVAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
pub fn cc_01_ccval (& self) -> CC_01_CCVAL_R { CC_01_CCVAL_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
# [must_use]
pub fn cc_01_ccval (& mut self) -> CC_01_CCVAL_W < CC_01_SPEC , 0 > { CC_01_CCVAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CC_01_SPEC ; impl crate :: RegisterSpec for CC_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cc_01::R`](R) reader structure"]
impl crate :: Readable for CC_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`cc_01::W`](W) writer structure"]
impl crate :: Writable for CC_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CC_01[%s]
to value 0"]
impl crate :: Resettable for CC_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCCTL_01 (rw) register accessor: Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccctl_01`]
module"]
pub type CCCTL_01 = crate :: Reg < ccctl_01 :: CCCTL_01_SPEC > ; # [doc = "Capture or Compare Control Registers"]
pub mod ccctl_01 { # [doc = "Register `CCCTL_01[%s]` reader"]
pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"]
pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"]
CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"]
CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"]
CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"]
# [inline (always)]
pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"]
# [inline (always)]
pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"]
CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"]
CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)]
fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"]
# [inline (always)]
pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"]
# [inline (always)]
pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"]
# [inline (always)]
pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"]
CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"]
CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"]
CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"]
CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"]
CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"]
CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"]
CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"]
CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"]
CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"]
CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"]
CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"]
# [inline (always)]
pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"]
CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"]
CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"]
CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"]
CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"]
CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"]
CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"]
impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"]
impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s]
to value 0"]
impl crate :: Resettable for CCCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "OCTL_01 (rw) register accessor: CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@octl_01`]
module"]
pub type OCTL_01 = crate :: Reg < octl_01 :: OCTL_01_SPEC > ; # [doc = "CCP Output Control Registers"]
pub mod octl_01 { # [doc = "Register `OCTL_01[%s]` reader"]
pub type R = crate :: R < OCTL_01_SPEC > ; # [doc = "Register `OCTL_01[%s]` writer"]
pub type W = crate :: W < OCTL_01_SPEC > ; # [doc = "Field `OCTL_01_CCPO` reader - CCP Output Source"]
pub type OCTL_01_CCPO_R = crate :: FieldReader < OCTL_01_CCPO_A > ; # [doc = "CCP Output Source\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum OCTL_01_CCPO_A { # [doc = "0: FUNCVAL"]
OCTL_01_CCPO_FUNCVAL = 0 , # [doc = "1: LOAD"]
OCTL_01_CCPO_LOAD = 1 , # [doc = "2: CMPVAL"]
OCTL_01_CCPO_CMPVAL = 2 , # [doc = "4: ZERO"]
OCTL_01_CCPO_ZERO = 4 , # [doc = "5: CAPCOND"]
OCTL_01_CCPO_CAPCOND = 5 , # [doc = "6: FAULTCOND"]
OCTL_01_CCPO_FAULTCOND = 6 , # [doc = "8: CC0_MIRROR_ALL"]
OCTL_01_CCPO_CC0_MIRROR_ALL = 8 , # [doc = "9: CC1_MIRROR_ALL"]
OCTL_01_CCPO_CC1_MIRROR_ALL = 9 , # [doc = "12: DEADBAND"]
OCTL_01_CCPO_DEADBAND = 12 , # [doc = "13: CNTDIR"]
OCTL_01_CCPO_CNTDIR = 13 , } impl From < OCTL_01_CCPO_A > for u8 { # [inline (always)]
fn from (variant : OCTL_01_CCPO_A) -> Self { variant as _ } } impl crate :: FieldSpec for OCTL_01_CCPO_A { type Ux = u8 ; } impl OCTL_01_CCPO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < OCTL_01_CCPO_A > { match self . bits { 0 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) , 1 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) , 2 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) , 4 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) , 5 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) , 6 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) , 8 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) , 9 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) , 12 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) , 13 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) , _ => None , } } # [doc = "FUNCVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_funcval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL } # [doc = "LOAD"]
# [inline (always)]
pub fn is_octl_01_ccpo_load (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD } # [doc = "CMPVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cmpval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL } # [doc = "ZERO"]
# [inline (always)]
pub fn is_octl_01_ccpo_zero (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO } # [doc = "CAPCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_capcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_faultcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc0_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc1_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL } # [doc = "DEADBAND"]
# [inline (always)]
pub fn is_octl_01_ccpo_deadband (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND } # [doc = "CNTDIR"]
# [inline (always)]
pub fn is_octl_01_ccpo_cntdir (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR } } # [doc = "Field `OCTL_01_CCPO` writer - CCP Output Source"]
pub type OCTL_01_CCPO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , OCTL_01_CCPO_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FUNCVAL"]
# [inline (always)]
pub fn octl_01_ccpo_funcval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) } # [doc = "LOAD"]
# [inline (always)]
pub fn octl_01_ccpo_load (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) } # [doc = "CMPVAL"]
# [inline (always)]
pub fn octl_01_ccpo_cmpval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) } # [doc = "ZERO"]
# [inline (always)]
pub fn octl_01_ccpo_zero (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) } # [doc = "CAPCOND"]
# [inline (always)]
pub fn octl_01_ccpo_capcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn octl_01_ccpo_faultcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc0_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc1_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) } # [doc = "DEADBAND"]
# [inline (always)]
pub fn octl_01_ccpo_deadband (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) } # [doc = "CNTDIR"]
# [inline (always)]
pub fn octl_01_ccpo_cntdir (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) } } # [doc = "Field `OCTL_01_CCPOINV` reader - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_R = crate :: BitReader < OCTL_01_CCPOINV_A > ; # [doc = "CCP Output Invert The output as selected by CCPO is conditionally inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPOINV_A { # [doc = "0: NOINV"]
OCTL_01_CCPOINV_NOINV = 0 , # [doc = "1: INV"]
OCTL_01_CCPOINV_INV = 1 , } impl From < OCTL_01_CCPOINV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPOINV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPOINV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPOINV_A { match self . bits { false => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV , true => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV , } } # [doc = "NOINV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_noinv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV } # [doc = "INV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_inv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV } } # [doc = "Field `OCTL_01_CCPOINV` writer - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPOINV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPOINV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINV"]
# [inline (always)]
pub fn octl_01_ccpoinv_noinv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV) } # [doc = "INV"]
# [inline (always)]
pub fn octl_01_ccpoinv_inv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV) } } # [doc = "Field `OCTL_01_CCPIV` reader - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_R = crate :: BitReader < OCTL_01_CCPIV_A > ; # [doc = "CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPIV_A { # [doc = "0: LOW"]
OCTL_01_CCPIV_LOW = 0 , # [doc = "1: HIGH"]
OCTL_01_CCPIV_HIGH = 1 , } impl From < OCTL_01_CCPIV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPIV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPIV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPIV_A { match self . bits { false => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW , true => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_octl_01_ccpiv_low (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_octl_01_ccpiv_high (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH } } # [doc = "Field `OCTL_01_CCPIV` writer - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPIV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"]
# [inline (always)]
pub fn octl_01_ccpiv_low (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW) } # [doc = "HIGH"]
# [inline (always)]
pub fn octl_01_ccpiv_high (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH) } } impl R { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
pub fn octl_01_ccpo (& self) -> OCTL_01_CCPO_R { OCTL_01_CCPO_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
pub fn octl_01_ccpoinv (& self) -> OCTL_01_CCPOINV_R { OCTL_01_CCPOINV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
pub fn octl_01_ccpiv (& self) -> OCTL_01_CCPIV_R { OCTL_01_CCPIV_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W < OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W < OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W < OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OCTL_01_SPEC ; impl crate :: RegisterSpec for OCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octl_01::R`](R) reader structure"]
impl crate :: Readable for OCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`octl_01::W`](W) writer structure"]
impl crate :: Writable for OCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets OCTL_01[%s]
to value 0"]
impl crate :: Resettable for OCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCACT_01 (rw) register accessor: Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccact_01`]
module"]
pub type CCACT_01 = crate :: Reg < ccact_01 :: CCACT_01_SPEC > ; # [doc = "Capture or Compare Action Registers"]
pub mod ccact_01 { # [doc = "Register `CCACT_01[%s]` reader"]
pub type R = crate :: R < CCACT_01_SPEC > ; # [doc = "Register `CCACT_01[%s]` writer"]
pub type W = crate :: W < CCACT_01_SPEC > ; # [doc = "Field `CCACT_01_ZACT` reader - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_R = crate :: FieldReader < CCACT_01_ZACT_A > ; # [doc = "CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_ZACT_A { # [doc = "0: DISABLED"]
CCACT_01_ZACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_ZACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_ZACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_ZACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_ZACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_ZACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_ZACT_A { type Ux = u8 ; } impl CCACT_01_ZACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_ZACT_A { match self . bits { 0 => CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED , 1 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH , 2 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW , 3 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_zact_disabled (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_high (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_low (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_toggle (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_ZACT` writer - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_ZACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_ZACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_zact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_zact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_zact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_zact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_LACT` reader - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_R = crate :: FieldReader < CCACT_01_LACT_A > ; # [doc = "CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_LACT_A { # [doc = "0: DISABLED"]
CCACT_01_LACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_LACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_LACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_LACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_LACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_LACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_LACT_A { type Ux = u8 ; } impl CCACT_01_LACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_LACT_A { match self . bits { 0 => CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED , 1 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH , 2 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW , 3 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_lact_disabled (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_high (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_low (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_toggle (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_LACT` writer - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_LACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_LACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_lact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_lact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_lact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_lact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CDACT` reader - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_R = crate :: FieldReader < CCACT_01_CDACT_A > ; # [doc = "CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CDACT_A { # [doc = "0: DISABLED"]
CCACT_01_CDACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CDACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CDACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CDACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CDACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CDACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CDACT_A { type Ux = u8 ; } impl CCACT_01_CDACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CDACT_A { match self . bits { 0 => CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED , 1 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH , 2 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW , 3 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cdact_disabled (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_high (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_low (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_toggle (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CDACT` writer - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CDACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CDACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cdact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CUACT` reader - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_R = crate :: FieldReader < CCACT_01_CUACT_A > ; # [doc = "CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CUACT_A { # [doc = "0: DISABLED"]
CCACT_01_CUACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CUACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CUACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CUACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CUACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CUACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CUACT_A { type Ux = u8 ; } impl CCACT_01_CUACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CUACT_A { match self . bits { 0 => CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED , 1 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH , 2 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW , 3 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cuact_disabled (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_high (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_low (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_toggle (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CUACT` writer - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CUACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CUACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cuact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2DACT` reader - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_R = crate :: FieldReader < CCACT_01_CC2DACT_A > ; # [doc = "CCP Output Action on CC2D event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2DACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2DACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2DACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2DACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2DACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2DACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2DACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2DACT_A { type Ux = u8 ; } impl CCACT_01_CC2DACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2DACT_A { match self . bits { 0 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED , 1 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH , 2 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW , 3 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_disabled (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_high (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_low (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2DACT` writer - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2DACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2DACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2dact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2UACT` reader - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_R = crate :: FieldReader < CCACT_01_CC2UACT_A > ; # [doc = "CCP Output Action on CC2U event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2UACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2UACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2UACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2UACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2UACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2UACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2UACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2UACT_A { type Ux = u8 ; } impl CCACT_01_CC2UACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2UACT_A { match self . bits { 0 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED , 1 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH , 2 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW , 3 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_disabled (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_high (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_low (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2UACT` writer - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2UACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2UACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2uact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_SWFRCACT` reader - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_R = crate :: FieldReader < CCACT_01_SWFRCACT_A > ; # [doc = "CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_SWFRCACT_A { # [doc = "0: DISABLED"]
CCACT_01_SWFRCACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_SWFRCACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_SWFRCACT_CCP_LOW = 2 , } impl From < CCACT_01_SWFRCACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_SWFRCACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_SWFRCACT_A { type Ux = u8 ; } impl CCACT_01_SWFRCACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCACT_01_SWFRCACT_A > { match self . bits { 0 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) , 1 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) , 2 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) , _ => None , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_disabled (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_high (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_low (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW } } # [doc = "Field `CCACT_01_SWFRCACT` writer - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CCACT_01_SWFRCACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_SWFRCACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_swfrcact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) } } impl R { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
pub fn ccact_01_zact (& self) -> CCACT_01_ZACT_R { CCACT_01_ZACT_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
pub fn ccact_01_lact (& self) -> CCACT_01_LACT_R { CCACT_01_LACT_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
pub fn ccact_01_cdact (& self) -> CCACT_01_CDACT_R { CCACT_01_CDACT_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
pub fn ccact_01_cuact (& self) -> CCACT_01_CUACT_R { CCACT_01_CUACT_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
pub fn ccact_01_cc2dact (& self) -> CCACT_01_CC2DACT_R { CCACT_01_CC2DACT_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
pub fn ccact_01_cc2uact (& self) -> CCACT_01_CC2UACT_R { CCACT_01_CC2UACT_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
pub fn ccact_01_swfrcact (& self) -> CCACT_01_SWFRCACT_R { CCACT_01_SWFRCACT_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W < CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W < CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W < CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cuact (& mut self) -> CCACT_01_CUACT_W < CCACT_01_SPEC , 9 > { CCACT_01_CUACT_W :: new (self) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2dact (& mut self) -> CCACT_01_CC2DACT_W < CCACT_01_SPEC , 12 > { CCACT_01_CC2DACT_W :: new (self) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2uact (& mut self) -> CCACT_01_CC2UACT_W < CCACT_01_SPEC , 15 > { CCACT_01_CC2UACT_W :: new (self) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
# [must_use]
pub fn ccact_01_swfrcact (& mut self) -> CCACT_01_SWFRCACT_W < CCACT_01_SPEC , 28 > { CCACT_01_SWFRCACT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCACT_01_SPEC ; impl crate :: RegisterSpec for CCACT_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccact_01::R`](R) reader structure"]
impl crate :: Readable for CCACT_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccact_01::W`](W) writer structure"]
impl crate :: Writable for CCACT_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCACT_01[%s]
to value 0"]
impl crate :: Resettable for CCACT_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IFCTL_01 (rw) register accessor: Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifctl_01`]
module"]
pub type IFCTL_01 = crate :: Reg < ifctl_01 :: IFCTL_01_SPEC > ; # [doc = "Input Filter Control Register"]
pub mod ifctl_01 { # [doc = "Register `IFCTL_01[%s]` reader"]
pub type R = crate :: R < IFCTL_01_SPEC > ; # [doc = "Register `IFCTL_01[%s]` writer"]
pub type W = crate :: W < IFCTL_01_SPEC > ; # [doc = "Field `IFCTL_01_ISEL` reader - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_R = crate :: FieldReader < IFCTL_01_ISEL_A > ; # [doc = "Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_ISEL_A { # [doc = "0: CCPX_INPUT"]
IFCTL_01_ISEL_CCPX_INPUT = 0 , # [doc = "1: CCPX_INPUT_PAIR"]
IFCTL_01_ISEL_CCPX_INPUT_PAIR = 1 , # [doc = "2: CCP0_INPUT"]
IFCTL_01_ISEL_CCP0_INPUT = 2 , # [doc = "3: TRIG_INPUT"]
IFCTL_01_ISEL_TRIG_INPUT = 3 , # [doc = "4: CCP_XOR"]
IFCTL_01_ISEL_CCP_XOR = 4 , # [doc = "5: FSUB0"]
IFCTL_01_ISEL_FSUB0 = 5 , # [doc = "6: FSUB1"]
IFCTL_01_ISEL_FSUB1 = 6 , # [doc = "7: COMP0"]
IFCTL_01_ISEL_COMP0 = 7 , # [doc = "8: COMP1"]
IFCTL_01_ISEL_COMP1 = 8 , # [doc = "9: COMP2"]
IFCTL_01_ISEL_COMP2 = 9 , } impl From < IFCTL_01_ISEL_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_ISEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_ISEL_A { type Ux = u8 ; } impl IFCTL_01_ISEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_ISEL_A > { match self . bits { 0 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) , 1 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) , 2 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) , 3 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) , 4 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) , 5 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) , 6 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) , 7 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) , 8 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) , 9 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) , _ => None , } } # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input_pair (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp0_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_trig_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp_xor (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1 } # [doc = "COMP0"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0 } # [doc = "COMP1"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1 } # [doc = "COMP2"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp2 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2 } } # [doc = "Field `IFCTL_01_ISEL` writer - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , IFCTL_01_ISEL_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_ISEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input_pair (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_trig_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn ifctl_01_isel_ccp_xor (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) } # [doc = "FSUB0"]
# [inline (always)]
pub fn ifctl_01_isel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn ifctl_01_isel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) } # [doc = "COMP0"]
# [inline (always)]
pub fn ifctl_01_isel_comp0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) } # [doc = "COMP1"]
# [inline (always)]
pub fn ifctl_01_isel_comp1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) } # [doc = "COMP2"]
# [inline (always)]
pub fn ifctl_01_isel_comp2 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) } } # [doc = "Field `IFCTL_01_INV` reader - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_R = crate :: BitReader < IFCTL_01_INV_A > ; # [doc = "Input Inversion This bit controls whether the selected input is inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_INV_A { # [doc = "0: NOINVERT"]
IFCTL_01_INV_NOINVERT = 0 , # [doc = "1: INVERT"]
IFCTL_01_INV_INVERT = 1 , } impl From < IFCTL_01_INV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_INV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_INV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_INV_A { match self . bits { false => IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT , true => IFCTL_01_INV_A :: IFCTL_01_INV_INVERT , } } # [doc = "NOINVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_noinvert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT } # [doc = "INVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_invert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_INVERT } } # [doc = "Field `IFCTL_01_INV` writer - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_INV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_INV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINVERT"]
# [inline (always)]
pub fn ifctl_01_inv_noinvert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT) } # [doc = "INVERT"]
# [inline (always)]
pub fn ifctl_01_inv_invert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_INVERT) } } # [doc = "Field `IFCTL_01_FP` reader - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_R = crate :: FieldReader < IFCTL_01_FP_A > ; # [doc = "Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_FP_A { # [doc = "0: _3"]
IFCTL_01_FP__3 = 0 , # [doc = "1: _5"]
IFCTL_01_FP__5 = 1 , # [doc = "2: _8"]
IFCTL_01_FP__8 = 2 , } impl From < IFCTL_01_FP_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_FP_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_FP_A { type Ux = u8 ; } impl IFCTL_01_FP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_FP_A > { match self . bits { 0 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__3) , 1 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__5) , 2 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__8) , _ => None , } } # [doc = "_3"]
# [inline (always)]
pub fn is_ifctl_01_fp__3 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__3 } # [doc = "_5"]
# [inline (always)]
pub fn is_ifctl_01_fp__5 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__5 } # [doc = "_8"]
# [inline (always)]
pub fn is_ifctl_01_fp__8 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__8 } } # [doc = "Field `IFCTL_01_FP` writer - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , IFCTL_01_FP_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_3"]
# [inline (always)]
pub fn ifctl_01_fp__3 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__3) } # [doc = "_5"]
# [inline (always)]
pub fn ifctl_01_fp__5 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__5) } # [doc = "_8"]
# [inline (always)]
pub fn ifctl_01_fp__8 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__8) } } # [doc = "Field `IFCTL_01_CPV` reader - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_R = crate :: BitReader < IFCTL_01_CPV_A > ; # [doc = "Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_CPV_A { # [doc = "0: CONSECUTIVE"]
IFCTL_01_CPV_CONSECUTIVE = 0 , # [doc = "1: VOTING"]
IFCTL_01_CPV_VOTING = 1 , } impl From < IFCTL_01_CPV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_CPV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_CPV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_CPV_A { match self . bits { false => IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE , true => IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING , } } # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn is_ifctl_01_cpv_consecutive (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE } # [doc = "VOTING"]
# [inline (always)]
pub fn is_ifctl_01_cpv_voting (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING } } # [doc = "Field `IFCTL_01_CPV` writer - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_CPV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_CPV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn ifctl_01_cpv_consecutive (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE) } # [doc = "VOTING"]
# [inline (always)]
pub fn ifctl_01_cpv_voting (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING) } } # [doc = "Field `IFCTL_01_FE` reader - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_R = crate :: BitReader < IFCTL_01_FE_A > ; # [doc = "Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_FE_A { # [doc = "0: DISABLED"]
IFCTL_01_FE_DISABLED = 0 , # [doc = "1: ENABLED"]
IFCTL_01_FE_ENABLED = 1 , } impl From < IFCTL_01_FE_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_FE_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_FE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_FE_A { match self . bits { false => IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED , true => IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_disabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_enabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED } } # [doc = "Field `IFCTL_01_FE` writer - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_FE_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ifctl_01_fe_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ifctl_01_fe_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED) } } impl R { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
pub fn ifctl_01_isel (& self) -> IFCTL_01_ISEL_R { IFCTL_01_ISEL_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
pub fn ifctl_01_inv (& self) -> IFCTL_01_INV_R { IFCTL_01_INV_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
pub fn ifctl_01_fp (& self) -> IFCTL_01_FP_R { IFCTL_01_FP_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
pub fn ifctl_01_cpv (& self) -> IFCTL_01_CPV_R { IFCTL_01_CPV_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
pub fn ifctl_01_fe (& self) -> IFCTL_01_FE_R { IFCTL_01_FE_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
# [must_use]
pub fn ifctl_01_isel (& mut self) -> IFCTL_01_ISEL_W < IFCTL_01_SPEC , 0 > { IFCTL_01_ISEL_W :: new (self) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_inv (& mut self) -> IFCTL_01_INV_W < IFCTL_01_SPEC , 7 > { IFCTL_01_INV_W :: new (self) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fp (& mut self) -> IFCTL_01_FP_W < IFCTL_01_SPEC , 8 > { IFCTL_01_FP_W :: new (self) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_cpv (& mut self) -> IFCTL_01_CPV_W < IFCTL_01_SPEC , 11 > { IFCTL_01_CPV_W :: new (self) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fe (& mut self) -> IFCTL_01_FE_W < IFCTL_01_SPEC , 12 > { IFCTL_01_FE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IFCTL_01_SPEC ; impl crate :: RegisterSpec for IFCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifctl_01::R`](R) reader structure"]
impl crate :: Readable for IFCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifctl_01::W`](W) writer structure"]
impl crate :: Writable for IFCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFCTL_01[%s]
to value 0"]
impl crate :: Resettable for IFCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TSEL (rw) register accessor: Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsel`]
module"]
pub type TSEL = crate :: Reg < tsel :: TSEL_SPEC > ; # [doc = "Trigger Select"]
pub mod tsel { # [doc = "Register `TSEL` reader"]
pub type R = crate :: R < TSEL_SPEC > ; # [doc = "Register `TSEL` writer"]
pub type W = crate :: W < TSEL_SPEC > ; # [doc = "Field `TSEL_ETSEL` reader - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_R = crate :: FieldReader < TSEL_ETSEL_A > ; # [doc = "External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum TSEL_ETSEL_A { # [doc = "0: TRIG0"]
TSEL_ETSEL_TRIG0 = 0 , # [doc = "1: TRIG1"]
TSEL_ETSEL_TRIG1 = 1 , # [doc = "2: TRIG2"]
TSEL_ETSEL_TRIG2 = 2 , # [doc = "3: TRIG3"]
TSEL_ETSEL_TRIG3 = 3 , # [doc = "4: TRIG4"]
TSEL_ETSEL_TRIG4 = 4 , # [doc = "5: TRIG5"]
TSEL_ETSEL_TRIG5 = 5 , # [doc = "6: TRIG6"]
TSEL_ETSEL_TRIG6 = 6 , # [doc = "7: TRIG7"]
TSEL_ETSEL_TRIG7 = 7 , # [doc = "8: TRIG8"]
TSEL_ETSEL_TRIG8 = 8 , # [doc = "9: TRIG9"]
TSEL_ETSEL_TRIG9 = 9 , # [doc = "10: TRIG10"]
TSEL_ETSEL_TRIG10 = 10 , # [doc = "11: TRIG11"]
TSEL_ETSEL_TRIG11 = 11 , # [doc = "12: TRIG12"]
TSEL_ETSEL_TRIG12 = 12 , # [doc = "13: TRIG13"]
TSEL_ETSEL_TRIG13 = 13 , # [doc = "14: TRIG14"]
TSEL_ETSEL_TRIG14 = 14 , # [doc = "15: TRIG15"]
TSEL_ETSEL_TRIG15 = 15 , # [doc = "16: TRIG_SUB0"]
TSEL_ETSEL_TRIG_SUB0 = 16 , # [doc = "17: TRIG_SUB1"]
TSEL_ETSEL_TRIG_SUB1 = 17 , } impl From < TSEL_ETSEL_A > for u8 { # [inline (always)]
fn from (variant : TSEL_ETSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for TSEL_ETSEL_A { type Ux = u8 ; } impl TSEL_ETSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < TSEL_ETSEL_A > { match self . bits { 0 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) , 1 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) , 2 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) , 3 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) , 4 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) , 5 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) , 6 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) , 7 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) , 8 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) , 9 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) , 10 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) , 11 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) , 12 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) , 13 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) , 14 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) , 15 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) , 16 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) , 17 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) , _ => None , } } # [doc = "TRIG0"]
# [inline (always)]
pub fn is_tsel_etsel_trig0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0 } # [doc = "TRIG1"]
# [inline (always)]
pub fn is_tsel_etsel_trig1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1 } # [doc = "TRIG2"]
# [inline (always)]
pub fn is_tsel_etsel_trig2 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2 } # [doc = "TRIG3"]
# [inline (always)]
pub fn is_tsel_etsel_trig3 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3 } # [doc = "TRIG4"]
# [inline (always)]
pub fn is_tsel_etsel_trig4 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4 } # [doc = "TRIG5"]
# [inline (always)]
pub fn is_tsel_etsel_trig5 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5 } # [doc = "TRIG6"]
# [inline (always)]
pub fn is_tsel_etsel_trig6 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6 } # [doc = "TRIG7"]
# [inline (always)]
pub fn is_tsel_etsel_trig7 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7 } # [doc = "TRIG8"]
# [inline (always)]
pub fn is_tsel_etsel_trig8 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8 } # [doc = "TRIG9"]
# [inline (always)]
pub fn is_tsel_etsel_trig9 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9 } # [doc = "TRIG10"]
# [inline (always)]
pub fn is_tsel_etsel_trig10 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10 } # [doc = "TRIG11"]
# [inline (always)]
pub fn is_tsel_etsel_trig11 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11 } # [doc = "TRIG12"]
# [inline (always)]
pub fn is_tsel_etsel_trig12 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12 } # [doc = "TRIG13"]
# [inline (always)]
pub fn is_tsel_etsel_trig13 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13 } # [doc = "TRIG14"]
# [inline (always)]
pub fn is_tsel_etsel_trig14 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14 } # [doc = "TRIG15"]
# [inline (always)]
pub fn is_tsel_etsel_trig15 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15 } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0 } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1 } } # [doc = "Field `TSEL_ETSEL` writer - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , TSEL_ETSEL_A > ; impl < 'a , REG , const O : u8 > TSEL_ETSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TRIG0"]
# [inline (always)]
pub fn tsel_etsel_trig0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) } # [doc = "TRIG1"]
# [inline (always)]
pub fn tsel_etsel_trig1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) } # [doc = "TRIG2"]
# [inline (always)]
pub fn tsel_etsel_trig2 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) } # [doc = "TRIG3"]
# [inline (always)]
pub fn tsel_etsel_trig3 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) } # [doc = "TRIG4"]
# [inline (always)]
pub fn tsel_etsel_trig4 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) } # [doc = "TRIG5"]
# [inline (always)]
pub fn tsel_etsel_trig5 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) } # [doc = "TRIG6"]
# [inline (always)]
pub fn tsel_etsel_trig6 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) } # [doc = "TRIG7"]
# [inline (always)]
pub fn tsel_etsel_trig7 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) } # [doc = "TRIG8"]
# [inline (always)]
pub fn tsel_etsel_trig8 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) } # [doc = "TRIG9"]
# [inline (always)]
pub fn tsel_etsel_trig9 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) } # [doc = "TRIG10"]
# [inline (always)]
pub fn tsel_etsel_trig10 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) } # [doc = "TRIG11"]
# [inline (always)]
pub fn tsel_etsel_trig11 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) } # [doc = "TRIG12"]
# [inline (always)]
pub fn tsel_etsel_trig12 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) } # [doc = "TRIG13"]
# [inline (always)]
pub fn tsel_etsel_trig13 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) } # [doc = "TRIG14"]
# [inline (always)]
pub fn tsel_etsel_trig14 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) } # [doc = "TRIG15"]
# [inline (always)]
pub fn tsel_etsel_trig15 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn tsel_etsel_trig_sub0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn tsel_etsel_trig_sub1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) } } # [doc = "Field `TSEL_TE` reader - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_R = crate :: BitReader < TSEL_TE_A > ; # [doc = "Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TSEL_TE_A { # [doc = "0: DISABLED"]
TSEL_TE_DISABLED = 0 , # [doc = "1: ENABLED"]
TSEL_TE_ENABLED = 1 , } impl From < TSEL_TE_A > for bool { # [inline (always)]
fn from (variant : TSEL_TE_A) -> Self { variant as u8 != 0 } } impl TSEL_TE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TSEL_TE_A { match self . bits { false => TSEL_TE_A :: TSEL_TE_DISABLED , true => TSEL_TE_A :: TSEL_TE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_tsel_te_disabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_tsel_te_enabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_ENABLED } } # [doc = "Field `TSEL_TE` writer - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TSEL_TE_A > ; impl < 'a , REG , const O : u8 > TSEL_TE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn tsel_te_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn tsel_te_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_ENABLED) } } impl R { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
pub fn tsel_etsel (& self) -> TSEL_ETSEL_R { TSEL_ETSEL_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
pub fn tsel_te (& self) -> TSEL_TE_R { TSEL_TE_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
# [must_use]
pub fn tsel_etsel (& mut self) -> TSEL_ETSEL_W < TSEL_SPEC , 0 > { TSEL_ETSEL_W :: new (self) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
# [must_use]
pub fn tsel_te (& mut self) -> TSEL_TE_W < TSEL_SPEC , 9 > { TSEL_TE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TSEL_SPEC ; impl crate :: RegisterSpec for TSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`tsel::R`](R) reader structure"]
impl crate :: Readable for TSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`tsel::W`](W) writer structure"]
impl crate :: Writable for TSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TSEL to value 0"]
impl crate :: Resettable for TSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct DMA { _marker : PhantomData < * const () > } unsafe impl Send for DMA { } impl DMA { # [doc = r"Pointer to the register block"]
pub const PTR : * const dma :: RegisterBlock = 0x4042_a000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const dma :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for DMA { type Target = dma :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for DMA { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("DMA") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod dma { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subscriber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , _reserved2 : [u8 ; 0x3c]
, # [doc = "0x444 - Publisher Port 0"]
pub fpub_1 : FPUB_1 , _reserved3 : [u8 ; 0x0bd0]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved4 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved6 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved10 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved11 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - DMA Channel Priority Control"]
pub dmaprio : DMAPRIO , _reserved13 : [u8 ; 0x0c]
, # [doc = "0x1110 - DMA Trigger Select"]
pub dmatctl : DMATCTL , _reserved14 : [u8 ; 0xec]
, # [doc = "0x1200 - DMA Channel Control"]
pub dmactl : DMACTL , # [doc = "0x1204 - DMA Channel Source Address"]
pub dmasa : DMASA , # [doc = "0x1208 - DMA Channel Destination Address"]
pub dmada : DMADA , # [doc = "0x120c - DMA Channel Size"]
pub dmasz : DMASZ , } # [doc = "FSUB_0 (rw) register accessor: Subscriber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subscriber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-255 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-255 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher Port 0"]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-255 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-255 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Interrupt index status"]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: DMACH0"]
IIDX_STAT_DMACH0 = 1 , # [doc = "2: DMACH1"]
IIDX_STAT_DMACH1 = 2 , # [doc = "3: DMACH2"]
IIDX_STAT_DMACH2 = 3 , # [doc = "4: DMACH3"]
IIDX_STAT_DMACH3 = 4 , # [doc = "5: DMACH4"]
IIDX_STAT_DMACH4 = 5 , # [doc = "6: DMACH5"]
IIDX_STAT_DMACH5 = 6 , # [doc = "7: DMACH6"]
IIDX_STAT_DMACH6 = 7 , # [doc = "8: DMACH7"]
IIDX_STAT_DMACH7 = 8 , # [doc = "9: DMACH8"]
IIDX_STAT_DMACH8 = 9 , # [doc = "10: DMACH9"]
IIDX_STAT_DMACH9 = 10 , # [doc = "11: DMACH10"]
IIDX_STAT_DMACH10 = 11 , # [doc = "12: DMACH11"]
IIDX_STAT_DMACH11 = 12 , # [doc = "13: DMACH12"]
IIDX_STAT_DMACH12 = 13 , # [doc = "14: DMACH13"]
IIDX_STAT_DMACH13 = 14 , # [doc = "15: DMACH14"]
IIDX_STAT_DMACH14 = 15 , # [doc = "16: DMACH15"]
IIDX_STAT_DMACH15 = 16 , # [doc = "17: PREIRQCH0"]
IIDX_STAT_PREIRQCH0 = 17 , # [doc = "18: PREIRQCH1"]
IIDX_STAT_PREIRQCH1 = 18 , # [doc = "19: PREIRQCH2"]
IIDX_STAT_PREIRQCH2 = 19 , # [doc = "20: PREIRQCH3"]
IIDX_STAT_PREIRQCH3 = 20 , # [doc = "21: PREIRQCH4"]
IIDX_STAT_PREIRQCH4 = 21 , # [doc = "22: PREIRQCH5"]
IIDX_STAT_PREIRQCH5 = 22 , # [doc = "23: PREIRQCH6"]
IIDX_STAT_PREIRQCH6 = 23 , # [doc = "24: PREIRQCH7"]
IIDX_STAT_PREIRQCH7 = 24 , # [doc = "25: ADDRERR"]
IIDX_STAT_ADDRERR = 25 , # [doc = "26: DATAERR"]
IIDX_STAT_DATAERR = 26 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH0) , 2 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH1) , 3 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH2) , 4 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH3) , 5 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH4) , 6 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH5) , 7 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH6) , 8 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH7) , 9 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH8) , 10 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH9) , 11 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH10) , 12 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH11) , 13 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH12) , 14 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH13) , 15 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH14) , 16 => Some (IIDX_STAT_A :: IIDX_STAT_DMACH15) , 17 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH0) , 18 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH1) , 19 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH2) , 20 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH3) , 21 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH4) , 22 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH5) , 23 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH6) , 24 => Some (IIDX_STAT_A :: IIDX_STAT_PREIRQCH7) , 25 => Some (IIDX_STAT_A :: IIDX_STAT_ADDRERR) , 26 => Some (IIDX_STAT_A :: IIDX_STAT_DATAERR) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "DMACH0"]
# [inline (always)]
pub fn is_iidx_stat_dmach0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH0 } # [doc = "DMACH1"]
# [inline (always)]
pub fn is_iidx_stat_dmach1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH1 } # [doc = "DMACH2"]
# [inline (always)]
pub fn is_iidx_stat_dmach2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH2 } # [doc = "DMACH3"]
# [inline (always)]
pub fn is_iidx_stat_dmach3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH3 } # [doc = "DMACH4"]
# [inline (always)]
pub fn is_iidx_stat_dmach4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH4 } # [doc = "DMACH5"]
# [inline (always)]
pub fn is_iidx_stat_dmach5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH5 } # [doc = "DMACH6"]
# [inline (always)]
pub fn is_iidx_stat_dmach6 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH6 } # [doc = "DMACH7"]
# [inline (always)]
pub fn is_iidx_stat_dmach7 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH7 } # [doc = "DMACH8"]
# [inline (always)]
pub fn is_iidx_stat_dmach8 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH8 } # [doc = "DMACH9"]
# [inline (always)]
pub fn is_iidx_stat_dmach9 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH9 } # [doc = "DMACH10"]
# [inline (always)]
pub fn is_iidx_stat_dmach10 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH10 } # [doc = "DMACH11"]
# [inline (always)]
pub fn is_iidx_stat_dmach11 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH11 } # [doc = "DMACH12"]
# [inline (always)]
pub fn is_iidx_stat_dmach12 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH12 } # [doc = "DMACH13"]
# [inline (always)]
pub fn is_iidx_stat_dmach13 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH13 } # [doc = "DMACH14"]
# [inline (always)]
pub fn is_iidx_stat_dmach14 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH14 } # [doc = "DMACH15"]
# [inline (always)]
pub fn is_iidx_stat_dmach15 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DMACH15 } # [doc = "PREIRQCH0"]
# [inline (always)]
pub fn is_iidx_stat_preirqch0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH0 } # [doc = "PREIRQCH1"]
# [inline (always)]
pub fn is_iidx_stat_preirqch1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH1 } # [doc = "PREIRQCH2"]
# [inline (always)]
pub fn is_iidx_stat_preirqch2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH2 } # [doc = "PREIRQCH3"]
# [inline (always)]
pub fn is_iidx_stat_preirqch3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH3 } # [doc = "PREIRQCH4"]
# [inline (always)]
pub fn is_iidx_stat_preirqch4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH4 } # [doc = "PREIRQCH5"]
# [inline (always)]
pub fn is_iidx_stat_preirqch5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH5 } # [doc = "PREIRQCH6"]
# [inline (always)]
pub fn is_iidx_stat_preirqch6 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH6 } # [doc = "PREIRQCH7"]
# [inline (always)]
pub fn is_iidx_stat_preirqch7 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_PREIRQCH7 } # [doc = "ADDRERR"]
# [inline (always)]
pub fn is_iidx_stat_addrerr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_ADDRERR } # [doc = "DATAERR"]
# [inline (always)]
pub fn is_iidx_stat_dataerr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DATAERR } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_DMACH0` reader - DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)."]
pub type IMASK_DMACH0_R = crate :: BitReader < IMASK_DMACH0_A > ; # [doc = "DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_DMACH0_A { # [doc = "0: CLR"]
IMASK_DMACH0_CLR = 0 , # [doc = "1: SET"]
IMASK_DMACH0_SET = 1 , } impl From < IMASK_DMACH0_A > for bool { # [inline (always)]
fn from (variant : IMASK_DMACH0_A) -> Self { variant as u8 != 0 } } impl IMASK_DMACH0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_DMACH0_A { match self . bits { false => IMASK_DMACH0_A :: IMASK_DMACH0_CLR , true => IMASK_DMACH0_A :: IMASK_DMACH0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_dmach0_clr (& self) -> bool { * self == IMASK_DMACH0_A :: IMASK_DMACH0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_dmach0_set (& self) -> bool { * self == IMASK_DMACH0_A :: IMASK_DMACH0_SET } } # [doc = "Field `IMASK_DMACH0` writer - DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)."]
pub type IMASK_DMACH0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_DMACH0_A > ; impl < 'a , REG , const O : u8 > IMASK_DMACH0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_dmach0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DMACH0_A :: IMASK_DMACH0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_dmach0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DMACH0_A :: IMASK_DMACH0_SET) } } # [doc = "Field `IMASK_DMACH1` reader - DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)."]
pub type IMASK_DMACH1_R = crate :: BitReader < IMASK_DMACH1_A > ; # [doc = "DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_DMACH1_A { # [doc = "0: CLR"]
IMASK_DMACH1_CLR = 0 , # [doc = "1: SET"]
IMASK_DMACH1_SET = 1 , } impl From < IMASK_DMACH1_A > for bool { # [inline (always)]
fn from (variant : IMASK_DMACH1_A) -> Self { variant as u8 != 0 } } impl IMASK_DMACH1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_DMACH1_A { match self . bits { false => IMASK_DMACH1_A :: IMASK_DMACH1_CLR , true => IMASK_DMACH1_A :: IMASK_DMACH1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_dmach1_clr (& self) -> bool { * self == IMASK_DMACH1_A :: IMASK_DMACH1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_dmach1_set (& self) -> bool { * self == IMASK_DMACH1_A :: IMASK_DMACH1_SET } } # [doc = "Field `IMASK_DMACH1` writer - DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)."]
pub type IMASK_DMACH1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_DMACH1_A > ; impl < 'a , REG , const O : u8 > IMASK_DMACH1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_dmach1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DMACH1_A :: IMASK_DMACH1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_dmach1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DMACH1_A :: IMASK_DMACH1_SET) } } # [doc = "Field `IMASK_DMACH2` reader - DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)."]
pub type IMASK_DMACH2_R = crate :: BitReader < IMASK_DMACH2_A > ; # [doc = "DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_DMACH2_A { # [doc = "0: CLR"]
IMASK_DMACH2_CLR = 0 , # [doc = "1: SET"]
IMASK_DMACH2_SET = 1 , } impl From < IMASK_DMACH2_A > for bool { # [inline (always)]
fn from (variant : IMASK_DMACH2_A) -> Self { variant as u8 != 0 } } impl IMASK_DMACH2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_DMACH2_A { match self . bits { false => IMASK_DMACH2_A :: IMASK_DMACH2_CLR , true => IMASK_DMACH2_A :: IMASK_DMACH2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_dmach2_clr (& self) -> bool { * self == IMASK_DMACH2_A :: IMASK_DMACH2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_dmach2_set (& self) -> bool { * self == IMASK_DMACH2_A :: IMASK_DMACH2_SET } } # [doc = "Field `IMASK_DMACH2` writer - DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)."]
pub type IMASK_DMACH2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_DMACH2_A > ; impl < 'a , REG , const O : u8 > IMASK_DMACH2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_dmach2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DMACH2_A :: IMASK_DMACH2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_dmach2_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DMACH2_A :: IMASK_DMACH2_SET) } } # [doc = "Field `IMASK_PREIRQCH0` reader - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
pub type IMASK_PREIRQCH0_R = crate :: BitReader < IMASK_PREIRQCH0_A > ; # [doc = "Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_PREIRQCH0_A { # [doc = "0: CLR"]
IMASK_PREIRQCH0_CLR = 0 , # [doc = "1: SET"]
IMASK_PREIRQCH0_SET = 1 , } impl From < IMASK_PREIRQCH0_A > for bool { # [inline (always)]
fn from (variant : IMASK_PREIRQCH0_A) -> Self { variant as u8 != 0 } } impl IMASK_PREIRQCH0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_PREIRQCH0_A { match self . bits { false => IMASK_PREIRQCH0_A :: IMASK_PREIRQCH0_CLR , true => IMASK_PREIRQCH0_A :: IMASK_PREIRQCH0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_preirqch0_clr (& self) -> bool { * self == IMASK_PREIRQCH0_A :: IMASK_PREIRQCH0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_preirqch0_set (& self) -> bool { * self == IMASK_PREIRQCH0_A :: IMASK_PREIRQCH0_SET } } # [doc = "Field `IMASK_PREIRQCH0` writer - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
pub type IMASK_PREIRQCH0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_PREIRQCH0_A > ; impl < 'a , REG , const O : u8 > IMASK_PREIRQCH0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_preirqch0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PREIRQCH0_A :: IMASK_PREIRQCH0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_preirqch0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_PREIRQCH0_A :: IMASK_PREIRQCH0_SET) } } # [doc = "Field `IMASK_ADDRERR` reader - DMA address error, SRC address not reachable."]
pub type IMASK_ADDRERR_R = crate :: BitReader < IMASK_ADDRERR_A > ; # [doc = "DMA address error, SRC address not reachable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_ADDRERR_A { # [doc = "0: CLR"]
IMASK_ADDRERR_CLR = 0 , # [doc = "1: SET"]
IMASK_ADDRERR_SET = 1 , } impl From < IMASK_ADDRERR_A > for bool { # [inline (always)]
fn from (variant : IMASK_ADDRERR_A) -> Self { variant as u8 != 0 } } impl IMASK_ADDRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_ADDRERR_A { match self . bits { false => IMASK_ADDRERR_A :: IMASK_ADDRERR_CLR , true => IMASK_ADDRERR_A :: IMASK_ADDRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_addrerr_clr (& self) -> bool { * self == IMASK_ADDRERR_A :: IMASK_ADDRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_addrerr_set (& self) -> bool { * self == IMASK_ADDRERR_A :: IMASK_ADDRERR_SET } } # [doc = "Field `IMASK_ADDRERR` writer - DMA address error, SRC address not reachable."]
pub type IMASK_ADDRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_ADDRERR_A > ; impl < 'a , REG , const O : u8 > IMASK_ADDRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_addrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ADDRERR_A :: IMASK_ADDRERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_addrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ADDRERR_A :: IMASK_ADDRERR_SET) } } # [doc = "Field `IMASK_DATAERR` reader - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
pub type IMASK_DATAERR_R = crate :: BitReader < IMASK_DATAERR_A > ; # [doc = "DMA data error, SRC data might be corrupted (PAR or ECC error).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_DATAERR_A { # [doc = "0: CLR"]
IMASK_DATAERR_CLR = 0 , # [doc = "1: SET"]
IMASK_DATAERR_SET = 1 , } impl From < IMASK_DATAERR_A > for bool { # [inline (always)]
fn from (variant : IMASK_DATAERR_A) -> Self { variant as u8 != 0 } } impl IMASK_DATAERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_DATAERR_A { match self . bits { false => IMASK_DATAERR_A :: IMASK_DATAERR_CLR , true => IMASK_DATAERR_A :: IMASK_DATAERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_dataerr_clr (& self) -> bool { * self == IMASK_DATAERR_A :: IMASK_DATAERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_dataerr_set (& self) -> bool { * self == IMASK_DATAERR_A :: IMASK_DATAERR_SET } } # [doc = "Field `IMASK_DATAERR` writer - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
pub type IMASK_DATAERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_DATAERR_A > ; impl < 'a , REG , const O : u8 > IMASK_DATAERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_dataerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DATAERR_A :: IMASK_DATAERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_dataerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_DATAERR_A :: IMASK_DATAERR_SET) } } impl R { # [doc = "Bit 0 - DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn imask_dmach0 (& self) -> IMASK_DMACH0_R { IMASK_DMACH0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn imask_dmach1 (& self) -> IMASK_DMACH1_R { IMASK_DMACH1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn imask_dmach2 (& self) -> IMASK_DMACH2_R { IMASK_DMACH2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 16 - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
# [inline (always)]
pub fn imask_preirqch0 (& self) -> IMASK_PREIRQCH0_R { IMASK_PREIRQCH0_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - DMA address error, SRC address not reachable."]
# [inline (always)]
pub fn imask_addrerr (& self) -> IMASK_ADDRERR_R { IMASK_ADDRERR_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
# [inline (always)]
pub fn imask_dataerr (& self) -> IMASK_DATAERR_R { IMASK_DATAERR_R :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - DMA Channel 0 interrupt signal. Size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn imask_dmach0 (& mut self) -> IMASK_DMACH0_W < IMASK_SPEC , 0 > { IMASK_DMACH0_W :: new (self) } # [doc = "Bit 1 - DMA Channel 1 interrupt signal. Size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn imask_dmach1 (& mut self) -> IMASK_DMACH1_W < IMASK_SPEC , 1 > { IMASK_DMACH1_W :: new (self) } # [doc = "Bit 2 - DMA Channel 2 interrupt signal. Size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn imask_dmach2 (& mut self) -> IMASK_DMACH2_W < IMASK_SPEC , 2 > { IMASK_DMACH2_W :: new (self) } # [doc = "Bit 16 - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
# [inline (always)]
# [must_use]
pub fn imask_preirqch0 (& mut self) -> IMASK_PREIRQCH0_W < IMASK_SPEC , 16 > { IMASK_PREIRQCH0_W :: new (self) } # [doc = "Bit 24 - DMA address error, SRC address not reachable."]
# [inline (always)]
# [must_use]
pub fn imask_addrerr (& mut self) -> IMASK_ADDRERR_W < IMASK_SPEC , 24 > { IMASK_ADDRERR_W :: new (self) } # [doc = "Bit 25 - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
# [inline (always)]
# [must_use]
pub fn imask_dataerr (& mut self) -> IMASK_DATAERR_W < IMASK_SPEC , 25 > { IMASK_DATAERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_DMACH0` reader - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type RIS_DMACH0_R = crate :: BitReader < RIS_DMACH0_A > ; # [doc = "DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_DMACH0_A { # [doc = "0: CLR"]
RIS_DMACH0_CLR = 0 , # [doc = "1: SET"]
RIS_DMACH0_SET = 1 , } impl From < RIS_DMACH0_A > for bool { # [inline (always)]
fn from (variant : RIS_DMACH0_A) -> Self { variant as u8 != 0 } } impl RIS_DMACH0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_DMACH0_A { match self . bits { false => RIS_DMACH0_A :: RIS_DMACH0_CLR , true => RIS_DMACH0_A :: RIS_DMACH0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_dmach0_clr (& self) -> bool { * self == RIS_DMACH0_A :: RIS_DMACH0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_dmach0_set (& self) -> bool { * self == RIS_DMACH0_A :: RIS_DMACH0_SET } } # [doc = "Field `RIS_DMACH1` reader - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type RIS_DMACH1_R = crate :: BitReader < RIS_DMACH1_A > ; # [doc = "DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_DMACH1_A { # [doc = "0: CLR"]
RIS_DMACH1_CLR = 0 , # [doc = "1: SET"]
RIS_DMACH1_SET = 1 , } impl From < RIS_DMACH1_A > for bool { # [inline (always)]
fn from (variant : RIS_DMACH1_A) -> Self { variant as u8 != 0 } } impl RIS_DMACH1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_DMACH1_A { match self . bits { false => RIS_DMACH1_A :: RIS_DMACH1_CLR , true => RIS_DMACH1_A :: RIS_DMACH1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_dmach1_clr (& self) -> bool { * self == RIS_DMACH1_A :: RIS_DMACH1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_dmach1_set (& self) -> bool { * self == RIS_DMACH1_A :: RIS_DMACH1_SET } } # [doc = "Field `RIS_DMACH2` reader - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type RIS_DMACH2_R = crate :: BitReader < RIS_DMACH2_A > ; # [doc = "DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_DMACH2_A { # [doc = "0: CLR"]
RIS_DMACH2_CLR = 0 , # [doc = "1: SET"]
RIS_DMACH2_SET = 1 , } impl From < RIS_DMACH2_A > for bool { # [inline (always)]
fn from (variant : RIS_DMACH2_A) -> Self { variant as u8 != 0 } } impl RIS_DMACH2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_DMACH2_A { match self . bits { false => RIS_DMACH2_A :: RIS_DMACH2_CLR , true => RIS_DMACH2_A :: RIS_DMACH2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_dmach2_clr (& self) -> bool { * self == RIS_DMACH2_A :: RIS_DMACH2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_dmach2_set (& self) -> bool { * self == RIS_DMACH2_A :: RIS_DMACH2_SET } } # [doc = "Field `RIS_PREIRQCH0` reader - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
pub type RIS_PREIRQCH0_R = crate :: BitReader < RIS_PREIRQCH0_A > ; # [doc = "Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_PREIRQCH0_A { # [doc = "0: CLR"]
RIS_PREIRQCH0_CLR = 0 , # [doc = "1: SET"]
RIS_PREIRQCH0_SET = 1 , } impl From < RIS_PREIRQCH0_A > for bool { # [inline (always)]
fn from (variant : RIS_PREIRQCH0_A) -> Self { variant as u8 != 0 } } impl RIS_PREIRQCH0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_PREIRQCH0_A { match self . bits { false => RIS_PREIRQCH0_A :: RIS_PREIRQCH0_CLR , true => RIS_PREIRQCH0_A :: RIS_PREIRQCH0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_preirqch0_clr (& self) -> bool { * self == RIS_PREIRQCH0_A :: RIS_PREIRQCH0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_preirqch0_set (& self) -> bool { * self == RIS_PREIRQCH0_A :: RIS_PREIRQCH0_SET } } # [doc = "Field `RIS_ADDRERR` reader - DMA address error, SRC address not reachable."]
pub type RIS_ADDRERR_R = crate :: BitReader < RIS_ADDRERR_A > ; # [doc = "DMA address error, SRC address not reachable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_ADDRERR_A { # [doc = "0: CLR"]
RIS_ADDRERR_CLR = 0 , # [doc = "1: SET"]
RIS_ADDRERR_SET = 1 , } impl From < RIS_ADDRERR_A > for bool { # [inline (always)]
fn from (variant : RIS_ADDRERR_A) -> Self { variant as u8 != 0 } } impl RIS_ADDRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_ADDRERR_A { match self . bits { false => RIS_ADDRERR_A :: RIS_ADDRERR_CLR , true => RIS_ADDRERR_A :: RIS_ADDRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_addrerr_clr (& self) -> bool { * self == RIS_ADDRERR_A :: RIS_ADDRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_addrerr_set (& self) -> bool { * self == RIS_ADDRERR_A :: RIS_ADDRERR_SET } } # [doc = "Field `RIS_DATAERR` reader - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
pub type RIS_DATAERR_R = crate :: BitReader < RIS_DATAERR_A > ; # [doc = "DMA data error, SRC data might be corrupted (PAR or ECC error).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_DATAERR_A { # [doc = "0: CLR"]
RIS_DATAERR_CLR = 0 , # [doc = "1: SET"]
RIS_DATAERR_SET = 1 , } impl From < RIS_DATAERR_A > for bool { # [inline (always)]
fn from (variant : RIS_DATAERR_A) -> Self { variant as u8 != 0 } } impl RIS_DATAERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_DATAERR_A { match self . bits { false => RIS_DATAERR_A :: RIS_DATAERR_CLR , true => RIS_DATAERR_A :: RIS_DATAERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_dataerr_clr (& self) -> bool { * self == RIS_DATAERR_A :: RIS_DATAERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_dataerr_set (& self) -> bool { * self == RIS_DATAERR_A :: RIS_DATAERR_SET } } impl R { # [doc = "Bit 0 - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn ris_dmach0 (& self) -> RIS_DMACH0_R { RIS_DMACH0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn ris_dmach1 (& self) -> RIS_DMACH1_R { RIS_DMACH1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn ris_dmach2 (& self) -> RIS_DMACH2_R { RIS_DMACH2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 16 - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
# [inline (always)]
pub fn ris_preirqch0 (& self) -> RIS_PREIRQCH0_R { RIS_PREIRQCH0_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - DMA address error, SRC address not reachable."]
# [inline (always)]
pub fn ris_addrerr (& self) -> RIS_ADDRERR_R { RIS_ADDRERR_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
# [inline (always)]
pub fn ris_dataerr (& self) -> RIS_DATAERR_R { RIS_DATAERR_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_DMACH0` reader - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type MIS_DMACH0_R = crate :: BitReader < MIS_DMACH0_A > ; # [doc = "DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_DMACH0_A { # [doc = "0: CLR"]
MIS_DMACH0_CLR = 0 , # [doc = "1: SET"]
MIS_DMACH0_SET = 1 , } impl From < MIS_DMACH0_A > for bool { # [inline (always)]
fn from (variant : MIS_DMACH0_A) -> Self { variant as u8 != 0 } } impl MIS_DMACH0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_DMACH0_A { match self . bits { false => MIS_DMACH0_A :: MIS_DMACH0_CLR , true => MIS_DMACH0_A :: MIS_DMACH0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_dmach0_clr (& self) -> bool { * self == MIS_DMACH0_A :: MIS_DMACH0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_dmach0_set (& self) -> bool { * self == MIS_DMACH0_A :: MIS_DMACH0_SET } } # [doc = "Field `MIS_DMACH1` reader - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type MIS_DMACH1_R = crate :: BitReader < MIS_DMACH1_A > ; # [doc = "DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_DMACH1_A { # [doc = "0: CLR"]
MIS_DMACH1_CLR = 0 , # [doc = "1: SET"]
MIS_DMACH1_SET = 1 , } impl From < MIS_DMACH1_A > for bool { # [inline (always)]
fn from (variant : MIS_DMACH1_A) -> Self { variant as u8 != 0 } } impl MIS_DMACH1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_DMACH1_A { match self . bits { false => MIS_DMACH1_A :: MIS_DMACH1_CLR , true => MIS_DMACH1_A :: MIS_DMACH1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_dmach1_clr (& self) -> bool { * self == MIS_DMACH1_A :: MIS_DMACH1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_dmach1_set (& self) -> bool { * self == MIS_DMACH1_A :: MIS_DMACH1_SET } } # [doc = "Field `MIS_DMACH2` reader - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type MIS_DMACH2_R = crate :: BitReader < MIS_DMACH2_A > ; # [doc = "DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_DMACH2_A { # [doc = "0: CLR"]
MIS_DMACH2_CLR = 0 , # [doc = "1: SET"]
MIS_DMACH2_SET = 1 , } impl From < MIS_DMACH2_A > for bool { # [inline (always)]
fn from (variant : MIS_DMACH2_A) -> Self { variant as u8 != 0 } } impl MIS_DMACH2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_DMACH2_A { match self . bits { false => MIS_DMACH2_A :: MIS_DMACH2_CLR , true => MIS_DMACH2_A :: MIS_DMACH2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_dmach2_clr (& self) -> bool { * self == MIS_DMACH2_A :: MIS_DMACH2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_dmach2_set (& self) -> bool { * self == MIS_DMACH2_A :: MIS_DMACH2_SET } } # [doc = "Field `MIS_PREIRQCH0` reader - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
pub type MIS_PREIRQCH0_R = crate :: BitReader < MIS_PREIRQCH0_A > ; # [doc = "Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_PREIRQCH0_A { # [doc = "0: CLR"]
MIS_PREIRQCH0_CLR = 0 , # [doc = "1: SET"]
MIS_PREIRQCH0_SET = 1 , } impl From < MIS_PREIRQCH0_A > for bool { # [inline (always)]
fn from (variant : MIS_PREIRQCH0_A) -> Self { variant as u8 != 0 } } impl MIS_PREIRQCH0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_PREIRQCH0_A { match self . bits { false => MIS_PREIRQCH0_A :: MIS_PREIRQCH0_CLR , true => MIS_PREIRQCH0_A :: MIS_PREIRQCH0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_preirqch0_clr (& self) -> bool { * self == MIS_PREIRQCH0_A :: MIS_PREIRQCH0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_preirqch0_set (& self) -> bool { * self == MIS_PREIRQCH0_A :: MIS_PREIRQCH0_SET } } # [doc = "Field `MIS_ADDRERR` reader - DMA address error, SRC address not reachable."]
pub type MIS_ADDRERR_R = crate :: BitReader < MIS_ADDRERR_A > ; # [doc = "DMA address error, SRC address not reachable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_ADDRERR_A { # [doc = "0: CLR"]
MIS_ADDRERR_CLR = 0 , # [doc = "1: SET"]
MIS_ADDRERR_SET = 1 , } impl From < MIS_ADDRERR_A > for bool { # [inline (always)]
fn from (variant : MIS_ADDRERR_A) -> Self { variant as u8 != 0 } } impl MIS_ADDRERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_ADDRERR_A { match self . bits { false => MIS_ADDRERR_A :: MIS_ADDRERR_CLR , true => MIS_ADDRERR_A :: MIS_ADDRERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_addrerr_clr (& self) -> bool { * self == MIS_ADDRERR_A :: MIS_ADDRERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_addrerr_set (& self) -> bool { * self == MIS_ADDRERR_A :: MIS_ADDRERR_SET } } # [doc = "Field `MIS_DATAERR` reader - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
pub type MIS_DATAERR_R = crate :: BitReader < MIS_DATAERR_A > ; # [doc = "DMA data error, SRC data might be corrupted (PAR or ECC error).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_DATAERR_A { # [doc = "0: CLR"]
MIS_DATAERR_CLR = 0 , # [doc = "1: SET"]
MIS_DATAERR_SET = 1 , } impl From < MIS_DATAERR_A > for bool { # [inline (always)]
fn from (variant : MIS_DATAERR_A) -> Self { variant as u8 != 0 } } impl MIS_DATAERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_DATAERR_A { match self . bits { false => MIS_DATAERR_A :: MIS_DATAERR_CLR , true => MIS_DATAERR_A :: MIS_DATAERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_dataerr_clr (& self) -> bool { * self == MIS_DATAERR_A :: MIS_DATAERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_dataerr_set (& self) -> bool { * self == MIS_DATAERR_A :: MIS_DATAERR_SET } } impl R { # [doc = "Bit 0 - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn mis_dmach0 (& self) -> MIS_DMACH0_R { MIS_DMACH0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn mis_dmach1 (& self) -> MIS_DMACH1_R { MIS_DMACH1_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
pub fn mis_dmach2 (& self) -> MIS_DMACH2_R { MIS_DMACH2_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 16 - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
# [inline (always)]
pub fn mis_preirqch0 (& self) -> MIS_PREIRQCH0_R { MIS_PREIRQCH0_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 24 - DMA address error, SRC address not reachable."]
# [inline (always)]
pub fn mis_addrerr (& self) -> MIS_ADDRERR_R { MIS_ADDRERR_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
# [inline (always)]
pub fn mis_dataerr (& self) -> MIS_DATAERR_R { MIS_DATAERR_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_DMACH0_AW { # [doc = "0: NO_EFFECT"]
ISET_DMACH0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_DMACH0_SET = 1 , } impl From < ISET_DMACH0_AW > for bool { # [inline (always)]
fn from (variant : ISET_DMACH0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_DMACH0` writer - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type ISET_DMACH0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_DMACH0_AW > ; impl < 'a , REG , const O : u8 > ISET_DMACH0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_dmach0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DMACH0_AW :: ISET_DMACH0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_dmach0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DMACH0_AW :: ISET_DMACH0_SET) } } # [doc = "DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_DMACH1_AW { # [doc = "0: NO_EFFECT"]
ISET_DMACH1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_DMACH1_SET = 1 , } impl From < ISET_DMACH1_AW > for bool { # [inline (always)]
fn from (variant : ISET_DMACH1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_DMACH1` writer - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type ISET_DMACH1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_DMACH1_AW > ; impl < 'a , REG , const O : u8 > ISET_DMACH1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_dmach1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DMACH1_AW :: ISET_DMACH1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_dmach1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DMACH1_AW :: ISET_DMACH1_SET) } } # [doc = "DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_DMACH2_AW { # [doc = "0: NO_EFFECT"]
ISET_DMACH2_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_DMACH2_SET = 1 , } impl From < ISET_DMACH2_AW > for bool { # [inline (always)]
fn from (variant : ISET_DMACH2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_DMACH2` writer - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type ISET_DMACH2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_DMACH2_AW > ; impl < 'a , REG , const O : u8 > ISET_DMACH2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_dmach2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DMACH2_AW :: ISET_DMACH2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_dmach2_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DMACH2_AW :: ISET_DMACH2_SET) } } # [doc = "Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_PREIRQCH0_AW { # [doc = "0: CLR"]
ISET_PREIRQCH0_CLR = 0 , # [doc = "1: SET"]
ISET_PREIRQCH0_SET = 1 , } impl From < ISET_PREIRQCH0_AW > for bool { # [inline (always)]
fn from (variant : ISET_PREIRQCH0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_PREIRQCH0` writer - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
pub type ISET_PREIRQCH0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_PREIRQCH0_AW > ; impl < 'a , REG , const O : u8 > ISET_PREIRQCH0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn iset_preirqch0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PREIRQCH0_AW :: ISET_PREIRQCH0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn iset_preirqch0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_PREIRQCH0_AW :: ISET_PREIRQCH0_SET) } } # [doc = "DMA address error, SRC address not reachable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_ADDRERR_AW { # [doc = "0: CLR"]
ISET_ADDRERR_CLR = 0 , # [doc = "1: SET"]
ISET_ADDRERR_SET = 1 , } impl From < ISET_ADDRERR_AW > for bool { # [inline (always)]
fn from (variant : ISET_ADDRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_ADDRERR` writer - DMA address error, SRC address not reachable."]
pub type ISET_ADDRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_ADDRERR_AW > ; impl < 'a , REG , const O : u8 > ISET_ADDRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn iset_addrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ADDRERR_AW :: ISET_ADDRERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn iset_addrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ADDRERR_AW :: ISET_ADDRERR_SET) } } # [doc = "DMA data error, SRC data might be corrupted (PAR or ECC error).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_DATAERR_AW { # [doc = "0: CLR"]
ISET_DATAERR_CLR = 0 , # [doc = "1: SET"]
ISET_DATAERR_SET = 1 , } impl From < ISET_DATAERR_AW > for bool { # [inline (always)]
fn from (variant : ISET_DATAERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_DATAERR` writer - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
pub type ISET_DATAERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_DATAERR_AW > ; impl < 'a , REG , const O : u8 > ISET_DATAERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn iset_dataerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DATAERR_AW :: ISET_DATAERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn iset_dataerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_DATAERR_AW :: ISET_DATAERR_SET) } } impl W { # [doc = "Bit 0 - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn iset_dmach0 (& mut self) -> ISET_DMACH0_W < ISET_SPEC , 0 > { ISET_DMACH0_W :: new (self) } # [doc = "Bit 1 - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn iset_dmach1 (& mut self) -> ISET_DMACH1_W < ISET_SPEC , 1 > { ISET_DMACH1_W :: new (self) } # [doc = "Bit 2 - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn iset_dmach2 (& mut self) -> ISET_DMACH2_W < ISET_SPEC , 2 > { ISET_DMACH2_W :: new (self) } # [doc = "Bit 16 - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
# [inline (always)]
# [must_use]
pub fn iset_preirqch0 (& mut self) -> ISET_PREIRQCH0_W < ISET_SPEC , 16 > { ISET_PREIRQCH0_W :: new (self) } # [doc = "Bit 24 - DMA address error, SRC address not reachable."]
# [inline (always)]
# [must_use]
pub fn iset_addrerr (& mut self) -> ISET_ADDRERR_W < ISET_SPEC , 24 > { ISET_ADDRERR_W :: new (self) } # [doc = "Bit 25 - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
# [inline (always)]
# [must_use]
pub fn iset_dataerr (& mut self) -> ISET_DATAERR_W < ISET_SPEC , 25 > { ISET_DATAERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_DMACH0_AW { # [doc = "0: NO_EFFECT"]
ICLR_DMACH0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_DMACH0_CLR = 1 , } impl From < ICLR_DMACH0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_DMACH0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_DMACH0` writer - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type ICLR_DMACH0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_DMACH0_AW > ; impl < 'a , REG , const O : u8 > ICLR_DMACH0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_dmach0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DMACH0_AW :: ICLR_DMACH0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_dmach0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DMACH0_AW :: ICLR_DMACH0_CLR) } } # [doc = "DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_DMACH1_AW { # [doc = "0: NO_EFFECT"]
ICLR_DMACH1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_DMACH1_CLR = 1 , } impl From < ICLR_DMACH1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_DMACH1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_DMACH1` writer - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type ICLR_DMACH1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_DMACH1_AW > ; impl < 'a , REG , const O : u8 > ICLR_DMACH1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_dmach1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DMACH1_AW :: ICLR_DMACH1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_dmach1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DMACH1_AW :: ICLR_DMACH1_CLR) } } # [doc = "DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_DMACH2_AW { # [doc = "0: NO_EFFECT"]
ICLR_DMACH2_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_DMACH2_CLR = 1 , } impl From < ICLR_DMACH2_AW > for bool { # [inline (always)]
fn from (variant : ICLR_DMACH2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_DMACH2` writer - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
pub type ICLR_DMACH2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_DMACH2_AW > ; impl < 'a , REG , const O : u8 > ICLR_DMACH2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_dmach2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DMACH2_AW :: ICLR_DMACH2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_dmach2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DMACH2_AW :: ICLR_DMACH2_CLR) } } # [doc = "Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_PREIRQCH0_AW { # [doc = "0: CLR"]
ICLR_PREIRQCH0_CLR = 0 , # [doc = "1: SET"]
ICLR_PREIRQCH0_SET = 1 , } impl From < ICLR_PREIRQCH0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_PREIRQCH0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_PREIRQCH0` writer - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
pub type ICLR_PREIRQCH0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_PREIRQCH0_AW > ; impl < 'a , REG , const O : u8 > ICLR_PREIRQCH0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn iclr_preirqch0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_PREIRQCH0_AW :: ICLR_PREIRQCH0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn iclr_preirqch0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_PREIRQCH0_AW :: ICLR_PREIRQCH0_SET) } } # [doc = "DMA address error, SRC address not reachable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_ADDRERR_AW { # [doc = "0: CLR"]
ICLR_ADDRERR_CLR = 0 , # [doc = "1: SET"]
ICLR_ADDRERR_SET = 1 , } impl From < ICLR_ADDRERR_AW > for bool { # [inline (always)]
fn from (variant : ICLR_ADDRERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_ADDRERR` writer - DMA address error, SRC address not reachable."]
pub type ICLR_ADDRERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_ADDRERR_AW > ; impl < 'a , REG , const O : u8 > ICLR_ADDRERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn iclr_addrerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ADDRERR_AW :: ICLR_ADDRERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn iclr_addrerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ADDRERR_AW :: ICLR_ADDRERR_SET) } } # [doc = "DMA data error, SRC data might be corrupted (PAR or ECC error).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_DATAERR_AW { # [doc = "0: CLR"]
ICLR_DATAERR_CLR = 0 , # [doc = "1: SET"]
ICLR_DATAERR_SET = 1 , } impl From < ICLR_DATAERR_AW > for bool { # [inline (always)]
fn from (variant : ICLR_DATAERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_DATAERR` writer - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
pub type ICLR_DATAERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_DATAERR_AW > ; impl < 'a , REG , const O : u8 > ICLR_DATAERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn iclr_dataerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DATAERR_AW :: ICLR_DATAERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn iclr_dataerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_DATAERR_AW :: ICLR_DATAERR_SET) } } impl W { # [doc = "Bit 0 - DMA Channel 0 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn iclr_dmach0 (& mut self) -> ICLR_DMACH0_W < ICLR_SPEC , 0 > { ICLR_DMACH0_W :: new (self) } # [doc = "Bit 1 - DMA Channel 1 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn iclr_dmach1 (& mut self) -> ICLR_DMACH1_W < ICLR_SPEC , 1 > { ICLR_DMACH1_W :: new (self) } # [doc = "Bit 2 - DMA Channel 2 interrupt signals that size counter reached zero (DMASZ=0)."]
# [inline (always)]
# [must_use]
pub fn iclr_dmach2 (& mut self) -> ICLR_DMACH2_W < ICLR_SPEC , 2 > { ICLR_DMACH2_W :: new (self) } # [doc = "Bit 16 - Pre-IRQ for Channel 0. Size counter reached Pre-IRQ threshold."]
# [inline (always)]
# [must_use]
pub fn iclr_preirqch0 (& mut self) -> ICLR_PREIRQCH0_W < ICLR_SPEC , 16 > { ICLR_PREIRQCH0_W :: new (self) } # [doc = "Bit 24 - DMA address error, SRC address not reachable."]
# [inline (always)]
# [must_use]
pub fn iclr_addrerr (& mut self) -> ICLR_ADDRERR_W < ICLR_SPEC , 24 > { ICLR_ADDRERR_W :: new (self) } # [doc = "Bit 25 - DMA data error, SRC data might be corrupted (PAR or ECC error)."]
# [inline (always)]
# [must_use]
pub fn iclr_dataerr (& mut self) -> ICLR_DATAERR_W < ICLR_SPEC , 25 > { ICLR_DATAERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to interrupt event INT_EVENT\\[0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to interrupt event INT_EVENT\\[0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to generic event INT_EVENT\\[1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to generic event INT_EVENT\\[1\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to interrupt event INT_EVENT\\[0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to generic event INT_EVENT\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the DMA: number of DMA channel minus one (e.g. 0-&amp;gt;1ch, 2-&amp;gt;3ch, 15-&amp;gt;16ch)."]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the DMA: number of DMA channel minus one (e.g. 0-&amp;gt;1ch, 2-&amp;gt;3ch, 15-&amp;gt;16ch)."]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DMAPRIO (rw) register accessor: DMA Channel Priority Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaprio::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaprio::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmaprio`]
module"]
pub type DMAPRIO = crate :: Reg < dmaprio :: DMAPRIO_SPEC > ; # [doc = "DMA Channel Priority Control"]
pub mod dmaprio { # [doc = "Register `DMAPRIO` reader"]
pub type R = crate :: R < DMAPRIO_SPEC > ; # [doc = "Register `DMAPRIO` writer"]
pub type W = crate :: W < DMAPRIO_SPEC > ; # [doc = "Field `DMAPRIO_ROUNDROBIN` reader - Round robin. This bit enables the round-robin DMA channel priorities."]
pub type DMAPRIO_ROUNDROBIN_R = crate :: BitReader < DMAPRIO_ROUNDROBIN_A > ; # [doc = "Round robin. This bit enables the round-robin DMA channel priorities.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMAPRIO_ROUNDROBIN_A { # [doc = "0: DISABLE"]
DMAPRIO_ROUNDROBIN_DISABLE = 0 , # [doc = "1: ENABLE"]
DMAPRIO_ROUNDROBIN_ENABLE = 1 , } impl From < DMAPRIO_ROUNDROBIN_A > for bool { # [inline (always)]
fn from (variant : DMAPRIO_ROUNDROBIN_A) -> Self { variant as u8 != 0 } } impl DMAPRIO_ROUNDROBIN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAPRIO_ROUNDROBIN_A { match self . bits { false => DMAPRIO_ROUNDROBIN_A :: DMAPRIO_ROUNDROBIN_DISABLE , true => DMAPRIO_ROUNDROBIN_A :: DMAPRIO_ROUNDROBIN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmaprio_roundrobin_disable (& self) -> bool { * self == DMAPRIO_ROUNDROBIN_A :: DMAPRIO_ROUNDROBIN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmaprio_roundrobin_enable (& self) -> bool { * self == DMAPRIO_ROUNDROBIN_A :: DMAPRIO_ROUNDROBIN_ENABLE } } # [doc = "Field `DMAPRIO_ROUNDROBIN` writer - Round robin. This bit enables the round-robin DMA channel priorities."]
pub type DMAPRIO_ROUNDROBIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMAPRIO_ROUNDROBIN_A > ; impl < 'a , REG , const O : u8 > DMAPRIO_ROUNDROBIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmaprio_roundrobin_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAPRIO_ROUNDROBIN_A :: DMAPRIO_ROUNDROBIN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmaprio_roundrobin_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMAPRIO_ROUNDROBIN_A :: DMAPRIO_ROUNDROBIN_ENABLE) } } # [doc = "Field `DMAPRIO_BURSTSZ` reader - Define the burst size of a block transfer, before the priority is re-evaluated"]
pub type DMAPRIO_BURSTSZ_R = crate :: FieldReader < DMAPRIO_BURSTSZ_A > ; # [doc = "Define the burst size of a block transfer, before the priority is re-evaluated\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMAPRIO_BURSTSZ_A { # [doc = "0: INFINITI"]
DMAPRIO_BURSTSZ_INFINITI = 0 , # [doc = "1: BURST_8"]
DMAPRIO_BURSTSZ_BURST_8 = 1 , # [doc = "2: BUSRT_16"]
DMAPRIO_BURSTSZ_BUSRT_16 = 2 , # [doc = "3: BURST_32"]
DMAPRIO_BURSTSZ_BURST_32 = 3 , } impl From < DMAPRIO_BURSTSZ_A > for u8 { # [inline (always)]
fn from (variant : DMAPRIO_BURSTSZ_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMAPRIO_BURSTSZ_A { type Ux = u8 ; } impl DMAPRIO_BURSTSZ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMAPRIO_BURSTSZ_A { match self . bits { 0 => DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_INFINITI , 1 => DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BURST_8 , 2 => DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BUSRT_16 , 3 => DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BURST_32 , _ => unreachable ! () , } } # [doc = "INFINITI"]
# [inline (always)]
pub fn is_dmaprio_burstsz_infiniti (& self) -> bool { * self == DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_INFINITI } # [doc = "BURST_8"]
# [inline (always)]
pub fn is_dmaprio_burstsz_burst_8 (& self) -> bool { * self == DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BURST_8 } # [doc = "BUSRT_16"]
# [inline (always)]
pub fn is_dmaprio_burstsz_busrt_16 (& self) -> bool { * self == DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BUSRT_16 } # [doc = "BURST_32"]
# [inline (always)]
pub fn is_dmaprio_burstsz_burst_32 (& self) -> bool { * self == DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BURST_32 } } # [doc = "Field `DMAPRIO_BURSTSZ` writer - Define the burst size of a block transfer, before the priority is re-evaluated"]
pub type DMAPRIO_BURSTSZ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , DMAPRIO_BURSTSZ_A > ; impl < 'a , REG , const O : u8 > DMAPRIO_BURSTSZ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "INFINITI"]
# [inline (always)]
pub fn dmaprio_burstsz_infiniti (self) -> & 'a mut crate :: W < REG > { self . variant (DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_INFINITI) } # [doc = "BURST_8"]
# [inline (always)]
pub fn dmaprio_burstsz_burst_8 (self) -> & 'a mut crate :: W < REG > { self . variant (DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BURST_8) } # [doc = "BUSRT_16"]
# [inline (always)]
pub fn dmaprio_burstsz_busrt_16 (self) -> & 'a mut crate :: W < REG > { self . variant (DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BUSRT_16) } # [doc = "BURST_32"]
# [inline (always)]
pub fn dmaprio_burstsz_burst_32 (self) -> & 'a mut crate :: W < REG > { self . variant (DMAPRIO_BURSTSZ_A :: DMAPRIO_BURSTSZ_BURST_32) } } impl R { # [doc = "Bit 0 - Round robin. This bit enables the round-robin DMA channel priorities."]
# [inline (always)]
pub fn dmaprio_roundrobin (& self) -> DMAPRIO_ROUNDROBIN_R { DMAPRIO_ROUNDROBIN_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 16:17 - Define the burst size of a block transfer, before the priority is re-evaluated"]
# [inline (always)]
pub fn dmaprio_burstsz (& self) -> DMAPRIO_BURSTSZ_R { DMAPRIO_BURSTSZ_R :: new (((self . bits >> 16) & 3) as u8) } } impl W { # [doc = "Bit 0 - Round robin. This bit enables the round-robin DMA channel priorities."]
# [inline (always)]
# [must_use]
pub fn dmaprio_roundrobin (& mut self) -> DMAPRIO_ROUNDROBIN_W < DMAPRIO_SPEC , 0 > { DMAPRIO_ROUNDROBIN_W :: new (self) } # [doc = "Bits 16:17 - Define the burst size of a block transfer, before the priority is re-evaluated"]
# [inline (always)]
# [must_use]
pub fn dmaprio_burstsz (& mut self) -> DMAPRIO_BURSTSZ_W < DMAPRIO_SPEC , 16 > { DMAPRIO_BURSTSZ_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA Channel Priority Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmaprio::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmaprio::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMAPRIO_SPEC ; impl crate :: RegisterSpec for DMAPRIO_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmaprio::R`](R) reader structure"]
impl crate :: Readable for DMAPRIO_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmaprio::W`](W) writer structure"]
impl crate :: Writable for DMAPRIO_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DMAPRIO to value 0"]
impl crate :: Resettable for DMAPRIO_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DMATCTL (rw) register accessor: DMA Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmatctl`]
module"]
pub type DMATCTL = crate :: Reg < dmatctl :: DMATCTL_SPEC > ; # [doc = "DMA Trigger Select"]
pub mod dmatctl { # [doc = "Register `DMATCTL` reader"]
pub type R = crate :: R < DMATCTL_SPEC > ; # [doc = "Register `DMATCTL` writer"]
pub type W = crate :: W < DMATCTL_SPEC > ; # [doc = "Field `DMATCTL_DMATSEL` reader - DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping."]
pub type DMATCTL_DMATSEL_R = crate :: FieldReader < DMATCTL_DMATSEL_A > ; # [doc = "DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMATCTL_DMATSEL_A { # [doc = "0: DMAREQ"]
DMATCTL_DMATSEL_DMAREQ = 0 , } impl From < DMATCTL_DMATSEL_A > for u8 { # [inline (always)]
fn from (variant : DMATCTL_DMATSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMATCTL_DMATSEL_A { type Ux = u8 ; } impl DMATCTL_DMATSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < DMATCTL_DMATSEL_A > { match self . bits { 0 => Some (DMATCTL_DMATSEL_A :: DMATCTL_DMATSEL_DMAREQ) , _ => None , } } # [doc = "DMAREQ"]
# [inline (always)]
pub fn is_dmatctl_dmatsel_dmareq (& self) -> bool { * self == DMATCTL_DMATSEL_A :: DMATCTL_DMATSEL_DMAREQ } } # [doc = "Field `DMATCTL_DMATSEL` writer - DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping."]
pub type DMATCTL_DMATSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O , DMATCTL_DMATSEL_A > ; impl < 'a , REG , const O : u8 > DMATCTL_DMATSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DMAREQ"]
# [inline (always)]
pub fn dmatctl_dmatsel_dmareq (self) -> & 'a mut crate :: W < REG > { self . variant (DMATCTL_DMATSEL_A :: DMATCTL_DMATSEL_DMAREQ) } } # [doc = "Field `DMATCTL_DMATINT` reader - DMA Trigger by Internal Channel"]
pub type DMATCTL_DMATINT_R = crate :: BitReader < DMATCTL_DMATINT_A > ; # [doc = "DMA Trigger by Internal Channel\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMATCTL_DMATINT_A { # [doc = "0: EXTERNAL"]
DMATCTL_DMATINT_EXTERNAL = 0 , # [doc = "1: INTERNAL"]
DMATCTL_DMATINT_INTERNAL = 1 , } impl From < DMATCTL_DMATINT_A > for bool { # [inline (always)]
fn from (variant : DMATCTL_DMATINT_A) -> Self { variant as u8 != 0 } } impl DMATCTL_DMATINT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMATCTL_DMATINT_A { match self . bits { false => DMATCTL_DMATINT_A :: DMATCTL_DMATINT_EXTERNAL , true => DMATCTL_DMATINT_A :: DMATCTL_DMATINT_INTERNAL , } } # [doc = "EXTERNAL"]
# [inline (always)]
pub fn is_dmatctl_dmatint_external (& self) -> bool { * self == DMATCTL_DMATINT_A :: DMATCTL_DMATINT_EXTERNAL } # [doc = "INTERNAL"]
# [inline (always)]
pub fn is_dmatctl_dmatint_internal (& self) -> bool { * self == DMATCTL_DMATINT_A :: DMATCTL_DMATINT_INTERNAL } } # [doc = "Field `DMATCTL_DMATINT` writer - DMA Trigger by Internal Channel"]
pub type DMATCTL_DMATINT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMATCTL_DMATINT_A > ; impl < 'a , REG , const O : u8 > DMATCTL_DMATINT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "EXTERNAL"]
# [inline (always)]
pub fn dmatctl_dmatint_external (self) -> & 'a mut crate :: W < REG > { self . variant (DMATCTL_DMATINT_A :: DMATCTL_DMATINT_EXTERNAL) } # [doc = "INTERNAL"]
# [inline (always)]
pub fn dmatctl_dmatint_internal (self) -> & 'a mut crate :: W < REG > { self . variant (DMATCTL_DMATINT_A :: DMATCTL_DMATINT_INTERNAL) } } impl R { # [doc = "Bits 0:5 - DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping."]
# [inline (always)]
pub fn dmatctl_dmatsel (& self) -> DMATCTL_DMATSEL_R { DMATCTL_DMATSEL_R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 7 - DMA Trigger by Internal Channel"]
# [inline (always)]
pub fn dmatctl_dmatint (& self) -> DMATCTL_DMATINT_R { DMATCTL_DMATINT_R :: new (((self . bits >> 7) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - DMA Trigger Select Note: Reference the datasheet of the device to see the specific trigger mapping."]
# [inline (always)]
# [must_use]
pub fn dmatctl_dmatsel (& mut self) -> DMATCTL_DMATSEL_W < DMATCTL_SPEC , 0 > { DMATCTL_DMATSEL_W :: new (self) } # [doc = "Bit 7 - DMA Trigger by Internal Channel"]
# [inline (always)]
# [must_use]
pub fn dmatctl_dmatint (& mut self) -> DMATCTL_DMATINT_W < DMATCTL_SPEC , 7 > { DMATCTL_DMATINT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmatctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmatctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMATCTL_SPEC ; impl crate :: RegisterSpec for DMATCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmatctl::R`](R) reader structure"]
impl crate :: Readable for DMATCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmatctl::W`](W) writer structure"]
impl crate :: Writable for DMATCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DMATCTL to value 0"]
impl crate :: Resettable for DMATCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DMACTL (rw) register accessor: DMA Channel Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmactl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmactl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmactl`]
module"]
pub type DMACTL = crate :: Reg < dmactl :: DMACTL_SPEC > ; # [doc = "DMA Channel Control"]
pub mod dmactl { # [doc = "Register `DMACTL` reader"]
pub type R = crate :: R < DMACTL_SPEC > ; # [doc = "Register `DMACTL` writer"]
pub type W = crate :: W < DMACTL_SPEC > ; # [doc = "Field `DMACTL_DMAREQ` reader - DMA request. Software-controlled DMA start. DMAREQ is reset automatically."]
pub type DMACTL_DMAREQ_R = crate :: BitReader < DMACTL_DMAREQ_A > ; # [doc = "DMA request. Software-controlled DMA start. DMAREQ is reset automatically.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMACTL_DMAREQ_A { # [doc = "0: IDLE"]
DMACTL_DMAREQ_IDLE = 0 , # [doc = "1: REQUEST"]
DMACTL_DMAREQ_REQUEST = 1 , } impl From < DMACTL_DMAREQ_A > for bool { # [inline (always)]
fn from (variant : DMACTL_DMAREQ_A) -> Self { variant as u8 != 0 } } impl DMACTL_DMAREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMACTL_DMAREQ_A { match self . bits { false => DMACTL_DMAREQ_A :: DMACTL_DMAREQ_IDLE , true => DMACTL_DMAREQ_A :: DMACTL_DMAREQ_REQUEST , } } # [doc = "IDLE"]
# [inline (always)]
pub fn is_dmactl_dmareq_idle (& self) -> bool { * self == DMACTL_DMAREQ_A :: DMACTL_DMAREQ_IDLE } # [doc = "REQUEST"]
# [inline (always)]
pub fn is_dmactl_dmareq_request (& self) -> bool { * self == DMACTL_DMAREQ_A :: DMACTL_DMAREQ_REQUEST } } # [doc = "Field `DMACTL_DMAREQ` writer - DMA request. Software-controlled DMA start. DMAREQ is reset automatically."]
pub type DMACTL_DMAREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMACTL_DMAREQ_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMAREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IDLE"]
# [inline (always)]
pub fn dmactl_dmareq_idle (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAREQ_A :: DMACTL_DMAREQ_IDLE) } # [doc = "REQUEST"]
# [inline (always)]
pub fn dmactl_dmareq_request (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAREQ_A :: DMACTL_DMAREQ_REQUEST) } } # [doc = "Field `DMACTL_DMAEN` reader - DMA enable"]
pub type DMACTL_DMAEN_R = crate :: BitReader < DMACTL_DMAEN_A > ; # [doc = "DMA enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum DMACTL_DMAEN_A { # [doc = "0: DISABLE"]
DMACTL_DMAEN_DISABLE = 0 , # [doc = "1: ENABLE"]
DMACTL_DMAEN_ENABLE = 1 , } impl From < DMACTL_DMAEN_A > for bool { # [inline (always)]
fn from (variant : DMACTL_DMAEN_A) -> Self { variant as u8 != 0 } } impl DMACTL_DMAEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMACTL_DMAEN_A { match self . bits { false => DMACTL_DMAEN_A :: DMACTL_DMAEN_DISABLE , true => DMACTL_DMAEN_A :: DMACTL_DMAEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_dmactl_dmaen_disable (& self) -> bool { * self == DMACTL_DMAEN_A :: DMACTL_DMAEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_dmactl_dmaen_enable (& self) -> bool { * self == DMACTL_DMAEN_A :: DMACTL_DMAEN_ENABLE } } # [doc = "Field `DMACTL_DMAEN` writer - DMA enable"]
pub type DMACTL_DMAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , DMACTL_DMAEN_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn dmactl_dmaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAEN_A :: DMACTL_DMAEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn dmactl_dmaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAEN_A :: DMACTL_DMAEN_ENABLE) } } # [doc = "Field `DMACTL_DMAPREIRQ` reader - Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0."]
pub type DMACTL_DMAPREIRQ_R = crate :: FieldReader < DMACTL_DMAPREIRQ_A > ; # [doc = "Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMACTL_DMAPREIRQ_A { # [doc = "0: PREIRQ_DISABLE"]
DMACTL_DMAPREIRQ_PREIRQ_DISABLE = 0 , # [doc = "1: PREIRQ_1"]
DMACTL_DMAPREIRQ_PREIRQ_1 = 1 , # [doc = "2: PREIRQ_2"]
DMACTL_DMAPREIRQ_PREIRQ_2 = 2 , # [doc = "3: PREIRQ_4"]
DMACTL_DMAPREIRQ_PREIRQ_4 = 3 , # [doc = "4: PREIRQ_8"]
DMACTL_DMAPREIRQ_PREIRQ_8 = 4 , # [doc = "5: PREIRQ_32"]
DMACTL_DMAPREIRQ_PREIRQ_32 = 5 , # [doc = "6: PREIRQ_64"]
DMACTL_DMAPREIRQ_PREIRQ_64 = 6 , # [doc = "7: PREIRQ_HALF"]
DMACTL_DMAPREIRQ_PREIRQ_HALF = 7 , } impl From < DMACTL_DMAPREIRQ_A > for u8 { # [inline (always)]
fn from (variant : DMACTL_DMAPREIRQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMACTL_DMAPREIRQ_A { type Ux = u8 ; } impl DMACTL_DMAPREIRQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMACTL_DMAPREIRQ_A { match self . bits { 0 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_DISABLE , 1 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_1 , 2 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_2 , 3 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_4 , 4 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_8 , 5 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_32 , 6 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_64 , 7 => DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_HALF , _ => unreachable ! () , } } # [doc = "PREIRQ_DISABLE"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_disable (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_DISABLE } # [doc = "PREIRQ_1"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_1 (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_1 } # [doc = "PREIRQ_2"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_2 (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_2 } # [doc = "PREIRQ_4"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_4 (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_4 } # [doc = "PREIRQ_8"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_8 (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_8 } # [doc = "PREIRQ_32"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_32 (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_32 } # [doc = "PREIRQ_64"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_64 (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_64 } # [doc = "PREIRQ_HALF"]
# [inline (always)]
pub fn is_dmactl_dmapreirq_preirq_half (& self) -> bool { * self == DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_HALF } } # [doc = "Field `DMACTL_DMAPREIRQ` writer - Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0."]
pub type DMACTL_DMAPREIRQ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , DMACTL_DMAPREIRQ_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMAPREIRQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "PREIRQ_DISABLE"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_DISABLE) } # [doc = "PREIRQ_1"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_1 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_1) } # [doc = "PREIRQ_2"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_2 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_2) } # [doc = "PREIRQ_4"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_4 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_4) } # [doc = "PREIRQ_8"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_8 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_8) } # [doc = "PREIRQ_32"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_32 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_32) } # [doc = "PREIRQ_64"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_64 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_64) } # [doc = "PREIRQ_HALF"]
# [inline (always)]
pub fn dmactl_dmapreirq_preirq_half (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAPREIRQ_A :: DMACTL_DMAPREIRQ_PREIRQ_HALF) } } # [doc = "Field `DMACTL_DMASRCWDTH` reader - DMA source width. This bit selects the source data width as a byte, half word, word or long word."]
pub type DMACTL_DMASRCWDTH_R = crate :: FieldReader < DMACTL_DMASRCWDTH_A > ; # [doc = "DMA source width. This bit selects the source data width as a byte, half word, word or long word.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMACTL_DMASRCWDTH_A { # [doc = "0: BYTE"]
DMACTL_DMASRCWDTH_BYTE = 0 , # [doc = "1: HALF"]
DMACTL_DMASRCWDTH_HALF = 1 , # [doc = "2: WORD"]
DMACTL_DMASRCWDTH_WORD = 2 , # [doc = "3: LONG"]
DMACTL_DMASRCWDTH_LONG = 3 , } impl From < DMACTL_DMASRCWDTH_A > for u8 { # [inline (always)]
fn from (variant : DMACTL_DMASRCWDTH_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMACTL_DMASRCWDTH_A { type Ux = u8 ; } impl DMACTL_DMASRCWDTH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMACTL_DMASRCWDTH_A { match self . bits { 0 => DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_BYTE , 1 => DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_HALF , 2 => DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_WORD , 3 => DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_LONG , _ => unreachable ! () , } } # [doc = "BYTE"]
# [inline (always)]
pub fn is_dmactl_dmasrcwdth_byte (& self) -> bool { * self == DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_BYTE } # [doc = "HALF"]
# [inline (always)]
pub fn is_dmactl_dmasrcwdth_half (& self) -> bool { * self == DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_HALF } # [doc = "WORD"]
# [inline (always)]
pub fn is_dmactl_dmasrcwdth_word (& self) -> bool { * self == DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_WORD } # [doc = "LONG"]
# [inline (always)]
pub fn is_dmactl_dmasrcwdth_long (& self) -> bool { * self == DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_LONG } } # [doc = "Field `DMACTL_DMASRCWDTH` writer - DMA source width. This bit selects the source data width as a byte, half word, word or long word."]
pub type DMACTL_DMASRCWDTH_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , DMACTL_DMASRCWDTH_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMASRCWDTH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "BYTE"]
# [inline (always)]
pub fn dmactl_dmasrcwdth_byte (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_BYTE) } # [doc = "HALF"]
# [inline (always)]
pub fn dmactl_dmasrcwdth_half (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_HALF) } # [doc = "WORD"]
# [inline (always)]
pub fn dmactl_dmasrcwdth_word (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_WORD) } # [doc = "LONG"]
# [inline (always)]
pub fn dmactl_dmasrcwdth_long (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCWDTH_A :: DMACTL_DMASRCWDTH_LONG) } } # [doc = "Field `DMACTL_DMADSTWDTH` reader - DMA destination width. This bit selects the destination as a byte, half word, word or long word."]
pub type DMACTL_DMADSTWDTH_R = crate :: FieldReader < DMACTL_DMADSTWDTH_A > ; # [doc = "DMA destination width. This bit selects the destination as a byte, half word, word or long word.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMACTL_DMADSTWDTH_A { # [doc = "0: BYTE"]
DMACTL_DMADSTWDTH_BYTE = 0 , # [doc = "1: HALF"]
DMACTL_DMADSTWDTH_HALF = 1 , # [doc = "2: WORD"]
DMACTL_DMADSTWDTH_WORD = 2 , # [doc = "3: LONG"]
DMACTL_DMADSTWDTH_LONG = 3 , } impl From < DMACTL_DMADSTWDTH_A > for u8 { # [inline (always)]
fn from (variant : DMACTL_DMADSTWDTH_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMACTL_DMADSTWDTH_A { type Ux = u8 ; } impl DMACTL_DMADSTWDTH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMACTL_DMADSTWDTH_A { match self . bits { 0 => DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_BYTE , 1 => DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_HALF , 2 => DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_WORD , 3 => DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_LONG , _ => unreachable ! () , } } # [doc = "BYTE"]
# [inline (always)]
pub fn is_dmactl_dmadstwdth_byte (& self) -> bool { * self == DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_BYTE } # [doc = "HALF"]
# [inline (always)]
pub fn is_dmactl_dmadstwdth_half (& self) -> bool { * self == DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_HALF } # [doc = "WORD"]
# [inline (always)]
pub fn is_dmactl_dmadstwdth_word (& self) -> bool { * self == DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_WORD } # [doc = "LONG"]
# [inline (always)]
pub fn is_dmactl_dmadstwdth_long (& self) -> bool { * self == DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_LONG } } # [doc = "Field `DMACTL_DMADSTWDTH` writer - DMA destination width. This bit selects the destination as a byte, half word, word or long word."]
pub type DMACTL_DMADSTWDTH_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , DMACTL_DMADSTWDTH_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMADSTWDTH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "BYTE"]
# [inline (always)]
pub fn dmactl_dmadstwdth_byte (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_BYTE) } # [doc = "HALF"]
# [inline (always)]
pub fn dmactl_dmadstwdth_half (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_HALF) } # [doc = "WORD"]
# [inline (always)]
pub fn dmactl_dmadstwdth_word (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_WORD) } # [doc = "LONG"]
# [inline (always)]
pub fn dmactl_dmadstwdth_long (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTWDTH_A :: DMACTL_DMADSTWDTH_LONG) } } # [doc = "Field `DMACTL_DMASRCINCR` reader - DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4."]
pub type DMACTL_DMASRCINCR_R = crate :: FieldReader < DMACTL_DMASRCINCR_A > ; # [doc = "DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMACTL_DMASRCINCR_A { # [doc = "0: UNCHANGED"]
DMACTL_DMASRCINCR_UNCHANGED = 0 , # [doc = "2: DECREMENT"]
DMACTL_DMASRCINCR_DECREMENT = 2 , # [doc = "3: INCREMENT"]
DMACTL_DMASRCINCR_INCREMENT = 3 , # [doc = "8: STRIDE_2"]
DMACTL_DMASRCINCR_STRIDE_2 = 8 , # [doc = "9: STRIDE_3"]
DMACTL_DMASRCINCR_STRIDE_3 = 9 , # [doc = "10: STRIDE_4"]
DMACTL_DMASRCINCR_STRIDE_4 = 10 , # [doc = "11: STRIDE_5"]
DMACTL_DMASRCINCR_STRIDE_5 = 11 , # [doc = "12: STRIDE_6"]
DMACTL_DMASRCINCR_STRIDE_6 = 12 , # [doc = "13: STRIDE_7"]
DMACTL_DMASRCINCR_STRIDE_7 = 13 , # [doc = "14: STRIDE_8"]
DMACTL_DMASRCINCR_STRIDE_8 = 14 , # [doc = "15: STRIDE_9"]
DMACTL_DMASRCINCR_STRIDE_9 = 15 , } impl From < DMACTL_DMASRCINCR_A > for u8 { # [inline (always)]
fn from (variant : DMACTL_DMASRCINCR_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMACTL_DMASRCINCR_A { type Ux = u8 ; } impl DMACTL_DMASRCINCR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < DMACTL_DMASRCINCR_A > { match self . bits { 0 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_UNCHANGED) , 2 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_DECREMENT) , 3 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_INCREMENT) , 8 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_2) , 9 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_3) , 10 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_4) , 11 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_5) , 12 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_6) , 13 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_7) , 14 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_8) , 15 => Some (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_9) , _ => None , } } # [doc = "UNCHANGED"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_unchanged (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_UNCHANGED } # [doc = "DECREMENT"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_decrement (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_DECREMENT } # [doc = "INCREMENT"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_increment (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_INCREMENT } # [doc = "STRIDE_2"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_2 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_2 } # [doc = "STRIDE_3"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_3 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_3 } # [doc = "STRIDE_4"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_4 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_4 } # [doc = "STRIDE_5"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_5 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_5 } # [doc = "STRIDE_6"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_6 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_6 } # [doc = "STRIDE_7"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_7 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_7 } # [doc = "STRIDE_8"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_8 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_8 } # [doc = "STRIDE_9"]
# [inline (always)]
pub fn is_dmactl_dmasrcincr_stride_9 (& self) -> bool { * self == DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_9 } } # [doc = "Field `DMACTL_DMASRCINCR` writer - DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4."]
pub type DMACTL_DMASRCINCR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , DMACTL_DMASRCINCR_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMASRCINCR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCHANGED"]
# [inline (always)]
pub fn dmactl_dmasrcincr_unchanged (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_UNCHANGED) } # [doc = "DECREMENT"]
# [inline (always)]
pub fn dmactl_dmasrcincr_decrement (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_DECREMENT) } # [doc = "INCREMENT"]
# [inline (always)]
pub fn dmactl_dmasrcincr_increment (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_INCREMENT) } # [doc = "STRIDE_2"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_2 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_2) } # [doc = "STRIDE_3"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_3 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_3) } # [doc = "STRIDE_4"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_4 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_4) } # [doc = "STRIDE_5"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_5 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_5) } # [doc = "STRIDE_6"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_6 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_6) } # [doc = "STRIDE_7"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_7 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_7) } # [doc = "STRIDE_8"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_8 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_8) } # [doc = "STRIDE_9"]
# [inline (always)]
pub fn dmactl_dmasrcincr_stride_9 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMASRCINCR_A :: DMACTL_DMASRCINCR_STRIDE_9) } } # [doc = "Field `DMACTL_DMADSTINCR` reader - DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4."]
pub type DMACTL_DMADSTINCR_R = crate :: FieldReader < DMACTL_DMADSTINCR_A > ; # [doc = "DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMACTL_DMADSTINCR_A { # [doc = "0: UNCHANGED"]
DMACTL_DMADSTINCR_UNCHANGED = 0 , # [doc = "2: DECREMENT"]
DMACTL_DMADSTINCR_DECREMENT = 2 , # [doc = "3: INCREMENT"]
DMACTL_DMADSTINCR_INCREMENT = 3 , # [doc = "8: STRIDE_2"]
DMACTL_DMADSTINCR_STRIDE_2 = 8 , # [doc = "9: STRIDE_3"]
DMACTL_DMADSTINCR_STRIDE_3 = 9 , # [doc = "10: STRIDE_4"]
DMACTL_DMADSTINCR_STRIDE_4 = 10 , # [doc = "11: STRIDE_5"]
DMACTL_DMADSTINCR_STRIDE_5 = 11 , # [doc = "12: STRIDE_6"]
DMACTL_DMADSTINCR_STRIDE_6 = 12 , # [doc = "13: STRIDE_7"]
DMACTL_DMADSTINCR_STRIDE_7 = 13 , # [doc = "14: STRIDE_8"]
DMACTL_DMADSTINCR_STRIDE_8 = 14 , # [doc = "15: STRIDE_9"]
DMACTL_DMADSTINCR_STRIDE_9 = 15 , } impl From < DMACTL_DMADSTINCR_A > for u8 { # [inline (always)]
fn from (variant : DMACTL_DMADSTINCR_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMACTL_DMADSTINCR_A { type Ux = u8 ; } impl DMACTL_DMADSTINCR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < DMACTL_DMADSTINCR_A > { match self . bits { 0 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_UNCHANGED) , 2 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_DECREMENT) , 3 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_INCREMENT) , 8 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_2) , 9 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_3) , 10 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_4) , 11 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_5) , 12 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_6) , 13 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_7) , 14 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_8) , 15 => Some (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_9) , _ => None , } } # [doc = "UNCHANGED"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_unchanged (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_UNCHANGED } # [doc = "DECREMENT"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_decrement (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_DECREMENT } # [doc = "INCREMENT"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_increment (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_INCREMENT } # [doc = "STRIDE_2"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_2 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_2 } # [doc = "STRIDE_3"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_3 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_3 } # [doc = "STRIDE_4"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_4 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_4 } # [doc = "STRIDE_5"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_5 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_5 } # [doc = "STRIDE_6"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_6 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_6 } # [doc = "STRIDE_7"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_7 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_7 } # [doc = "STRIDE_8"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_8 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_8 } # [doc = "STRIDE_9"]
# [inline (always)]
pub fn is_dmactl_dmadstincr_stride_9 (& self) -> bool { * self == DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_9 } } # [doc = "Field `DMACTL_DMADSTINCR` writer - DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4."]
pub type DMACTL_DMADSTINCR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , DMACTL_DMADSTINCR_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMADSTINCR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCHANGED"]
# [inline (always)]
pub fn dmactl_dmadstincr_unchanged (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_UNCHANGED) } # [doc = "DECREMENT"]
# [inline (always)]
pub fn dmactl_dmadstincr_decrement (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_DECREMENT) } # [doc = "INCREMENT"]
# [inline (always)]
pub fn dmactl_dmadstincr_increment (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_INCREMENT) } # [doc = "STRIDE_2"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_2 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_2) } # [doc = "STRIDE_3"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_3 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_3) } # [doc = "STRIDE_4"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_4 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_4) } # [doc = "STRIDE_5"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_5 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_5) } # [doc = "STRIDE_6"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_6 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_6) } # [doc = "STRIDE_7"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_7 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_7) } # [doc = "STRIDE_8"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_8 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_8) } # [doc = "STRIDE_9"]
# [inline (always)]
pub fn dmactl_dmadstincr_stride_9 (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMADSTINCR_A :: DMACTL_DMADSTINCR_STRIDE_9) } } # [doc = "Field `DMACTL_DMAEM` reader - DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0."]
pub type DMACTL_DMAEM_R = crate :: FieldReader < DMACTL_DMAEM_A > ; # [doc = "DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMACTL_DMAEM_A { # [doc = "0: NORMAL"]
DMACTL_DMAEM_NORMAL = 0 , # [doc = "2: FILLMODE"]
DMACTL_DMAEM_FILLMODE = 2 , # [doc = "3: TABLEMODE"]
DMACTL_DMAEM_TABLEMODE = 3 , } impl From < DMACTL_DMAEM_A > for u8 { # [inline (always)]
fn from (variant : DMACTL_DMAEM_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMACTL_DMAEM_A { type Ux = u8 ; } impl DMACTL_DMAEM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < DMACTL_DMAEM_A > { match self . bits { 0 => Some (DMACTL_DMAEM_A :: DMACTL_DMAEM_NORMAL) , 2 => Some (DMACTL_DMAEM_A :: DMACTL_DMAEM_FILLMODE) , 3 => Some (DMACTL_DMAEM_A :: DMACTL_DMAEM_TABLEMODE) , _ => None , } } # [doc = "NORMAL"]
# [inline (always)]
pub fn is_dmactl_dmaem_normal (& self) -> bool { * self == DMACTL_DMAEM_A :: DMACTL_DMAEM_NORMAL } # [doc = "FILLMODE"]
# [inline (always)]
pub fn is_dmactl_dmaem_fillmode (& self) -> bool { * self == DMACTL_DMAEM_A :: DMACTL_DMAEM_FILLMODE } # [doc = "TABLEMODE"]
# [inline (always)]
pub fn is_dmactl_dmaem_tablemode (& self) -> bool { * self == DMACTL_DMAEM_A :: DMACTL_DMAEM_TABLEMODE } } # [doc = "Field `DMACTL_DMAEM` writer - DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0."]
pub type DMACTL_DMAEM_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , DMACTL_DMAEM_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMAEM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NORMAL"]
# [inline (always)]
pub fn dmactl_dmaem_normal (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAEM_A :: DMACTL_DMAEM_NORMAL) } # [doc = "FILLMODE"]
# [inline (always)]
pub fn dmactl_dmaem_fillmode (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAEM_A :: DMACTL_DMAEM_FILLMODE) } # [doc = "TABLEMODE"]
# [inline (always)]
pub fn dmactl_dmaem_tablemode (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMAEM_A :: DMACTL_DMAEM_TABLEMODE) } } # [doc = "Field `DMACTL_DMATM` reader - DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set."]
pub type DMACTL_DMATM_R = crate :: FieldReader < DMACTL_DMATM_A > ; # [doc = "DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum DMACTL_DMATM_A { # [doc = "0: SINGLE"]
DMACTL_DMATM_SINGLE = 0 , # [doc = "1: BLOCK"]
DMACTL_DMATM_BLOCK = 1 , # [doc = "2: RPTSNGL"]
DMACTL_DMATM_RPTSNGL = 2 , # [doc = "3: RPTBLCK"]
DMACTL_DMATM_RPTBLCK = 3 , } impl From < DMACTL_DMATM_A > for u8 { # [inline (always)]
fn from (variant : DMACTL_DMATM_A) -> Self { variant as _ } } impl crate :: FieldSpec for DMACTL_DMATM_A { type Ux = u8 ; } impl DMACTL_DMATM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> DMACTL_DMATM_A { match self . bits { 0 => DMACTL_DMATM_A :: DMACTL_DMATM_SINGLE , 1 => DMACTL_DMATM_A :: DMACTL_DMATM_BLOCK , 2 => DMACTL_DMATM_A :: DMACTL_DMATM_RPTSNGL , 3 => DMACTL_DMATM_A :: DMACTL_DMATM_RPTBLCK , _ => unreachable ! () , } } # [doc = "SINGLE"]
# [inline (always)]
pub fn is_dmactl_dmatm_single (& self) -> bool { * self == DMACTL_DMATM_A :: DMACTL_DMATM_SINGLE } # [doc = "BLOCK"]
# [inline (always)]
pub fn is_dmactl_dmatm_block (& self) -> bool { * self == DMACTL_DMATM_A :: DMACTL_DMATM_BLOCK } # [doc = "RPTSNGL"]
# [inline (always)]
pub fn is_dmactl_dmatm_rptsngl (& self) -> bool { * self == DMACTL_DMATM_A :: DMACTL_DMATM_RPTSNGL } # [doc = "RPTBLCK"]
# [inline (always)]
pub fn is_dmactl_dmatm_rptblck (& self) -> bool { * self == DMACTL_DMATM_A :: DMACTL_DMATM_RPTBLCK } } # [doc = "Field `DMACTL_DMATM` writer - DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set."]
pub type DMACTL_DMATM_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , DMACTL_DMATM_A > ; impl < 'a , REG , const O : u8 > DMACTL_DMATM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SINGLE"]
# [inline (always)]
pub fn dmactl_dmatm_single (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMATM_A :: DMACTL_DMATM_SINGLE) } # [doc = "BLOCK"]
# [inline (always)]
pub fn dmactl_dmatm_block (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMATM_A :: DMACTL_DMATM_BLOCK) } # [doc = "RPTSNGL"]
# [inline (always)]
pub fn dmactl_dmatm_rptsngl (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMATM_A :: DMACTL_DMATM_RPTSNGL) } # [doc = "RPTBLCK"]
# [inline (always)]
pub fn dmactl_dmatm_rptblck (self) -> & 'a mut crate :: W < REG > { self . variant (DMACTL_DMATM_A :: DMACTL_DMATM_RPTBLCK) } } impl R { # [doc = "Bit 0 - DMA request. Software-controlled DMA start. DMAREQ is reset automatically."]
# [inline (always)]
pub fn dmactl_dmareq (& self) -> DMACTL_DMAREQ_R { DMACTL_DMAREQ_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - DMA enable"]
# [inline (always)]
pub fn dmactl_dmaen (& self) -> DMACTL_DMAEN_R { DMACTL_DMAEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 4:6 - Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0."]
# [inline (always)]
pub fn dmactl_dmapreirq (& self) -> DMACTL_DMAPREIRQ_R { DMACTL_DMAPREIRQ_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:9 - DMA source width. This bit selects the source data width as a byte, half word, word or long word."]
# [inline (always)]
pub fn dmactl_dmasrcwdth (& self) -> DMACTL_DMASRCWDTH_R { DMACTL_DMASRCWDTH_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 12:13 - DMA destination width. This bit selects the destination as a byte, half word, word or long word."]
# [inline (always)]
pub fn dmactl_dmadstwdth (& self) -> DMACTL_DMADSTWDTH_R { DMACTL_DMADSTWDTH_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 16:19 - DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4."]
# [inline (always)]
pub fn dmactl_dmasrcincr (& self) -> DMACTL_DMASRCINCR_R { DMACTL_DMASRCINCR_R :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:23 - DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4."]
# [inline (always)]
pub fn dmactl_dmadstincr (& self) -> DMACTL_DMADSTINCR_R { DMACTL_DMADSTINCR_R :: new (((self . bits >> 20) & 0x0f) as u8) } # [doc = "Bits 24:25 - DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0."]
# [inline (always)]
pub fn dmactl_dmaem (& self) -> DMACTL_DMAEM_R { DMACTL_DMAEM_R :: new (((self . bits >> 24) & 3) as u8) } # [doc = "Bits 28:29 - DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set."]
# [inline (always)]
pub fn dmactl_dmatm (& self) -> DMACTL_DMATM_R { DMACTL_DMATM_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - DMA request. Software-controlled DMA start. DMAREQ is reset automatically."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmareq (& mut self) -> DMACTL_DMAREQ_W < DMACTL_SPEC , 0 > { DMACTL_DMAREQ_W :: new (self) } # [doc = "Bit 1 - DMA enable"]
# [inline (always)]
# [must_use]
pub fn dmactl_dmaen (& mut self) -> DMACTL_DMAEN_W < DMACTL_SPEC , 1 > { DMACTL_DMAEN_W :: new (self) } # [doc = "Bits 4:6 - Enable an early IRQ event. This can help software to react quicker to and DMA done event or allows some additional configuration before the channel is complete. Note: This register is only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC configuration this register is a read only value and always reads as 0x0."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmapreirq (& mut self) -> DMACTL_DMAPREIRQ_W < DMACTL_SPEC , 4 > { DMACTL_DMAPREIRQ_W :: new (self) } # [doc = "Bits 8:9 - DMA source width. This bit selects the source data width as a byte, half word, word or long word."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmasrcwdth (& mut self) -> DMACTL_DMASRCWDTH_W < DMACTL_SPEC , 8 > { DMACTL_DMASRCWDTH_W :: new (self) } # [doc = "Bits 12:13 - DMA destination width. This bit selects the destination as a byte, half word, word or long word."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmadstwdth (& mut self) -> DMACTL_DMADSTWDTH_W < DMACTL_SPEC , 12 > { DMACTL_DMADSTWDTH_W :: new (self) } # [doc = "Bits 16:19 - DMA source increment. This bit selects automatic incrementing or decrementing of the source address DMASA for each transfer. The amount of change to the DMASA is based on the definitin in the DMASRCWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMASA by 4."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmasrcincr (& mut self) -> DMACTL_DMASRCINCR_W < DMACTL_SPEC , 16 > { DMACTL_DMASRCINCR_W :: new (self) } # [doc = "Bits 20:23 - DMA destination increment. This bit selects automatic incrementing or decrementing of the destination address DMADA for each transfer. The amount of change to the DMADA is based on the definitin in the DMADSTWDTH. For example an increment of 1 (+1) on a WORD transfer will increment the DMADA by 4."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmadstincr (& mut self) -> DMACTL_DMADSTINCR_W < DMACTL_SPEC , 20 > { DMACTL_DMADSTINCR_W :: new (self) } # [doc = "Bits 24:25 - DMA extended mode Note: The extended transfer modes are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration this register is a read-only register and reads 0x0."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmaem (& mut self) -> DMACTL_DMAEM_W < DMACTL_SPEC , 24 > { DMACTL_DMAEM_W :: new (self) } # [doc = "Bits 28:29 - DMA transfer mode register Note: The repeat-single (2h) and repeat-block (3h) transfer are only available in a FULL-channel configuration. Please consult the datasheet of the specific device to map which channel number has FULL or BASIC capability. In a BASIC channel configuration only the values for single (0h) and block (1h) transfer can be set."]
# [inline (always)]
# [must_use]
pub fn dmactl_dmatm (& mut self) -> DMACTL_DMATM_W < DMACTL_SPEC , 28 > { DMACTL_DMATM_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA Channel Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmactl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmactl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMACTL_SPEC ; impl crate :: RegisterSpec for DMACTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmactl::R`](R) reader structure"]
impl crate :: Readable for DMACTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmactl::W`](W) writer structure"]
impl crate :: Writable for DMACTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DMACTL to value 0"]
impl crate :: Resettable for DMACTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DMASA (rw) register accessor: DMA Channel Source Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasa`]
module"]
pub type DMASA = crate :: Reg < dmasa :: DMASA_SPEC > ; # [doc = "DMA Channel Source Address"]
pub mod dmasa { # [doc = "Register `DMASA` reader"]
pub type R = crate :: R < DMASA_SPEC > ; # [doc = "Register `DMASA` writer"]
pub type W = crate :: W < DMASA_SPEC > ; # [doc = "Field `DMASA_ADDR` reader - DMA Channel Source Address"]
pub type DMASA_ADDR_R = crate :: FieldReader < u32 > ; # [doc = "Field `DMASA_ADDR` writer - DMA Channel Source Address"]
pub type DMASA_ADDR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - DMA Channel Source Address"]
# [inline (always)]
pub fn dmasa_addr (& self) -> DMASA_ADDR_R { DMASA_ADDR_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - DMA Channel Source Address"]
# [inline (always)]
# [must_use]
pub fn dmasa_addr (& mut self) -> DMASA_ADDR_W < DMASA_SPEC , 0 > { DMASA_ADDR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA Channel Source Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasa::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMASA_SPEC ; impl crate :: RegisterSpec for DMASA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmasa::R`](R) reader structure"]
impl crate :: Readable for DMASA_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmasa::W`](W) writer structure"]
impl crate :: Writable for DMASA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DMASA to value 0"]
impl crate :: Resettable for DMASA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DMADA (rw) register accessor: DMA Channel Destination Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmada::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmada::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmada`]
module"]
pub type DMADA = crate :: Reg < dmada :: DMADA_SPEC > ; # [doc = "DMA Channel Destination Address"]
pub mod dmada { # [doc = "Register `DMADA` reader"]
pub type R = crate :: R < DMADA_SPEC > ; # [doc = "Register `DMADA` writer"]
pub type W = crate :: W < DMADA_SPEC > ; # [doc = "Field `DMADA_ADDR` reader - DMA Channel Destination Address"]
pub type DMADA_ADDR_R = crate :: FieldReader < u32 > ; # [doc = "Field `DMADA_ADDR` writer - DMA Channel Destination Address"]
pub type DMADA_ADDR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 32 , O , u32 > ; impl R { # [doc = "Bits 0:31 - DMA Channel Destination Address"]
# [inline (always)]
pub fn dmada_addr (& self) -> DMADA_ADDR_R { DMADA_ADDR_R :: new (self . bits) } } impl W { # [doc = "Bits 0:31 - DMA Channel Destination Address"]
# [inline (always)]
# [must_use]
pub fn dmada_addr (& mut self) -> DMADA_ADDR_W < DMADA_SPEC , 0 > { DMADA_ADDR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA Channel Destination Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmada::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmada::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMADA_SPEC ; impl crate :: RegisterSpec for DMADA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmada::R`](R) reader structure"]
impl crate :: Readable for DMADA_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmada::W`](W) writer structure"]
impl crate :: Writable for DMADA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DMADA to value 0"]
impl crate :: Resettable for DMADA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DMASZ (rw) register accessor: DMA Channel Size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasz::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dmasz`]
module"]
pub type DMASZ = crate :: Reg < dmasz :: DMASZ_SPEC > ; # [doc = "DMA Channel Size"]
pub mod dmasz { # [doc = "Register `DMASZ` reader"]
pub type R = crate :: R < DMASZ_SPEC > ; # [doc = "Register `DMASZ` writer"]
pub type W = crate :: W < DMASZ_SPEC > ; # [doc = "Field `DMASZ_SIZE` reader - DMA Channel Size in number of transfers"]
pub type DMASZ_SIZE_R = crate :: FieldReader < u16 > ; # [doc = "Field `DMASZ_SIZE` writer - DMA Channel Size in number of transfers"]
pub type DMASZ_SIZE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - DMA Channel Size in number of transfers"]
# [inline (always)]
pub fn dmasz_size (& self) -> DMASZ_SIZE_R { DMASZ_SIZE_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - DMA Channel Size in number of transfers"]
# [inline (always)]
# [must_use]
pub fn dmasz_size (& mut self) -> DMASZ_SIZE_W < DMASZ_SPEC , 0 > { DMASZ_SIZE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "DMA Channel Size\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dmasz::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dmasz::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DMASZ_SPEC ; impl crate :: RegisterSpec for DMASZ_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`dmasz::R`](R) reader structure"]
impl crate :: Readable for DMASZ_SPEC { } # [doc = "`write(|w| ..)` method takes [`dmasz::W`](W) writer structure"]
impl crate :: Writable for DMASZ_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets DMASZ to value 0"]
impl crate :: Resettable for DMASZ_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct COMP0 { _marker : PhantomData < * const () > } unsafe impl Send for COMP0 { } impl COMP0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const comp0 :: RegisterBlock = 0x4000_8000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const comp0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for COMP0 { type Target = comp0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for COMP0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("COMP0") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod comp0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subscriber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , _reserved2 : [u8 ; 0x3c]
, # [doc = "0x444 - Publisher port 1"]
pub fpub_1 : FPUB_1 , _reserved3 : [u8 ; 0x03b8]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , # [doc = "0x808 - Peripheral Clock Configuration Register"]
pub clkcfg : CLKCFG , _reserved6 : [u8 ; 0x08]
, # [doc = "0x814 - Status Register"]
pub gprcm_stat : GPRCM_STAT , _reserved7 : [u8 ; 0x0808]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved13 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved14 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - Control 0"]
pub ctl0 : CTL0 , # [doc = "0x1104 - Control 1"]
pub ctl1 : CTL1 , # [doc = "0x1108 - Control 2"]
pub ctl2 : CTL2 , # [doc = "0x110c - Control 3"]
pub ctl3 : CTL3 , _reserved19 : [u8 ; 0x10]
, # [doc = "0x1120 - Status"]
pub stat : STAT , } # [doc = "FSUB_0 (rw) register accessor: Subscriber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subscriber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher port 1"]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKCFG (rw) register accessor: Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkcfg`]
module"]
pub type CLKCFG = crate :: Reg < clkcfg :: CLKCFG_SPEC > ; # [doc = "Peripheral Clock Configuration Register"]
pub mod clkcfg { # [doc = "Register `CLKCFG` reader"]
pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"]
pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"]
CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"]
CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"]
pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"]
# [inline (always)]
pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
# [must_use]
pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"]
# [inline (always)]
# [must_use]
pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"]
impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"]
impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"]
impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GPRCM_STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gprcm_stat`]
module"]
pub type GPRCM_STAT = crate :: Reg < gprcm_stat :: GPRCM_STAT_SPEC > ; # [doc = "Status Register"]
pub mod gprcm_stat { # [doc = "Register `GPRCM_STAT` reader"]
pub type R = crate :: R < GPRCM_STAT_SPEC > ; # [doc = "Field `GPRCM_STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type GPRCM_STAT_RESETSTKY_R = crate :: BitReader < GPRCM_STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GPRCM_STAT_RESETSTKY_A { # [doc = "0: NORES"]
GPRCM_STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
GPRCM_STAT_RESETSTKY_RESET = 1 , } impl From < GPRCM_STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : GPRCM_STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl GPRCM_STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GPRCM_STAT_RESETSTKY_A { match self . bits { false => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES , true => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_nores (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_reset (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn gprcm_stat_resetstky (& self) -> GPRCM_STAT_RESETSTKY_R { GPRCM_STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GPRCM_STAT_SPEC ; impl crate :: RegisterSpec for GPRCM_STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gprcm_stat::R`](R) reader structure"]
impl crate :: Readable for GPRCM_STAT_SPEC { } # [doc = "`reset()` method sets GPRCM_STAT to value 0"]
impl crate :: Resettable for GPRCM_STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Interrupt index status"]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: OUTRDYIFG"]
IIDX_STAT_OUTRDYIFG = 1 , # [doc = "2: COMPIFG"]
IIDX_STAT_COMPIFG = 2 , # [doc = "3: COMPINVIFG"]
IIDX_STAT_COMPINVIFG = 3 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IIDX_STAT_A { match self . bits { 0 => IIDX_STAT_A :: IIDX_STAT_NO_INTR , 1 => IIDX_STAT_A :: IIDX_STAT_OUTRDYIFG , 2 => IIDX_STAT_A :: IIDX_STAT_COMPIFG , 3 => IIDX_STAT_A :: IIDX_STAT_COMPINVIFG , _ => unreachable ! () , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "OUTRDYIFG"]
# [inline (always)]
pub fn is_iidx_stat_outrdyifg (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_OUTRDYIFG } # [doc = "COMPIFG"]
# [inline (always)]
pub fn is_iidx_stat_compifg (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_COMPIFG } # [doc = "COMPINVIFG"]
# [inline (always)]
pub fn is_iidx_stat_compinvifg (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_COMPINVIFG } } impl R { # [doc = "Bits 0:1 - Interrupt index status"]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 3) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_COMPIFG` reader - Masks COMPIFG"]
pub type IMASK_COMPIFG_R = crate :: BitReader < IMASK_COMPIFG_A > ; # [doc = "Masks COMPIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_COMPIFG_A { # [doc = "0: CLR"]
IMASK_COMPIFG_CLR = 0 , # [doc = "1: SET"]
IMASK_COMPIFG_SET = 1 , } impl From < IMASK_COMPIFG_A > for bool { # [inline (always)]
fn from (variant : IMASK_COMPIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_COMPIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_COMPIFG_A { match self . bits { false => IMASK_COMPIFG_A :: IMASK_COMPIFG_CLR , true => IMASK_COMPIFG_A :: IMASK_COMPIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_compifg_clr (& self) -> bool { * self == IMASK_COMPIFG_A :: IMASK_COMPIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_compifg_set (& self) -> bool { * self == IMASK_COMPIFG_A :: IMASK_COMPIFG_SET } } # [doc = "Field `IMASK_COMPIFG` writer - Masks COMPIFG"]
pub type IMASK_COMPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_COMPIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_COMPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_compifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_COMPIFG_A :: IMASK_COMPIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_compifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_COMPIFG_A :: IMASK_COMPIFG_SET) } } # [doc = "Field `IMASK_COMPINVIFG` reader - Masks COMPINVIFG"]
pub type IMASK_COMPINVIFG_R = crate :: BitReader < IMASK_COMPINVIFG_A > ; # [doc = "Masks COMPINVIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_COMPINVIFG_A { # [doc = "0: CLR"]
IMASK_COMPINVIFG_CLR = 0 , # [doc = "1: SET"]
IMASK_COMPINVIFG_SET = 1 , } impl From < IMASK_COMPINVIFG_A > for bool { # [inline (always)]
fn from (variant : IMASK_COMPINVIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_COMPINVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_COMPINVIFG_A { match self . bits { false => IMASK_COMPINVIFG_A :: IMASK_COMPINVIFG_CLR , true => IMASK_COMPINVIFG_A :: IMASK_COMPINVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_compinvifg_clr (& self) -> bool { * self == IMASK_COMPINVIFG_A :: IMASK_COMPINVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_compinvifg_set (& self) -> bool { * self == IMASK_COMPINVIFG_A :: IMASK_COMPINVIFG_SET } } # [doc = "Field `IMASK_COMPINVIFG` writer - Masks COMPINVIFG"]
pub type IMASK_COMPINVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_COMPINVIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_COMPINVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_compinvifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_COMPINVIFG_A :: IMASK_COMPINVIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_compinvifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_COMPINVIFG_A :: IMASK_COMPINVIFG_SET) } } # [doc = "Field `IMASK_OUTRDYIFG` reader - Masks OUTRDYIFG"]
pub type IMASK_OUTRDYIFG_R = crate :: BitReader < IMASK_OUTRDYIFG_A > ; # [doc = "Masks OUTRDYIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_OUTRDYIFG_A { # [doc = "0: CLR"]
IMASK_OUTRDYIFG_CLR = 0 , # [doc = "1: SET"]
IMASK_OUTRDYIFG_SET = 1 , } impl From < IMASK_OUTRDYIFG_A > for bool { # [inline (always)]
fn from (variant : IMASK_OUTRDYIFG_A) -> Self { variant as u8 != 0 } } impl IMASK_OUTRDYIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_OUTRDYIFG_A { match self . bits { false => IMASK_OUTRDYIFG_A :: IMASK_OUTRDYIFG_CLR , true => IMASK_OUTRDYIFG_A :: IMASK_OUTRDYIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_outrdyifg_clr (& self) -> bool { * self == IMASK_OUTRDYIFG_A :: IMASK_OUTRDYIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_outrdyifg_set (& self) -> bool { * self == IMASK_OUTRDYIFG_A :: IMASK_OUTRDYIFG_SET } } # [doc = "Field `IMASK_OUTRDYIFG` writer - Masks OUTRDYIFG"]
pub type IMASK_OUTRDYIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_OUTRDYIFG_A > ; impl < 'a , REG , const O : u8 > IMASK_OUTRDYIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_outrdyifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_OUTRDYIFG_A :: IMASK_OUTRDYIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_outrdyifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_OUTRDYIFG_A :: IMASK_OUTRDYIFG_SET) } } impl R { # [doc = "Bit 1 - Masks COMPIFG"]
# [inline (always)]
pub fn imask_compifg (& self) -> IMASK_COMPIFG_R { IMASK_COMPIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masks COMPINVIFG"]
# [inline (always)]
pub fn imask_compinvifg (& self) -> IMASK_COMPINVIFG_R { IMASK_COMPINVIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masks OUTRDYIFG"]
# [inline (always)]
pub fn imask_outrdyifg (& self) -> IMASK_OUTRDYIFG_R { IMASK_OUTRDYIFG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Masks COMPIFG"]
# [inline (always)]
# [must_use]
pub fn imask_compifg (& mut self) -> IMASK_COMPIFG_W < IMASK_SPEC , 1 > { IMASK_COMPIFG_W :: new (self) } # [doc = "Bit 2 - Masks COMPINVIFG"]
# [inline (always)]
# [must_use]
pub fn imask_compinvifg (& mut self) -> IMASK_COMPINVIFG_W < IMASK_SPEC , 2 > { IMASK_COMPINVIFG_W :: new (self) } # [doc = "Bit 3 - Masks OUTRDYIFG"]
# [inline (always)]
# [must_use]
pub fn imask_outrdyifg (& mut self) -> IMASK_OUTRDYIFG_W < IMASK_SPEC , 3 > { IMASK_OUTRDYIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_COMPIFG` reader - Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit."]
pub type RIS_COMPIFG_R = crate :: BitReader < RIS_COMPIFG_A > ; # [doc = "Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_COMPIFG_A { # [doc = "0: CLR"]
RIS_COMPIFG_CLR = 0 , # [doc = "1: SET"]
RIS_COMPIFG_SET = 1 , } impl From < RIS_COMPIFG_A > for bool { # [inline (always)]
fn from (variant : RIS_COMPIFG_A) -> Self { variant as u8 != 0 } } impl RIS_COMPIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_COMPIFG_A { match self . bits { false => RIS_COMPIFG_A :: RIS_COMPIFG_CLR , true => RIS_COMPIFG_A :: RIS_COMPIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_compifg_clr (& self) -> bool { * self == RIS_COMPIFG_A :: RIS_COMPIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_compifg_set (& self) -> bool { * self == RIS_COMPIFG_A :: RIS_COMPIFG_SET } } # [doc = "Field `RIS_COMPINVIFG` reader - Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit."]
pub type RIS_COMPINVIFG_R = crate :: BitReader < RIS_COMPINVIFG_A > ; # [doc = "Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_COMPINVIFG_A { # [doc = "0: CLR"]
RIS_COMPINVIFG_CLR = 0 , # [doc = "1: SET"]
RIS_COMPINVIFG_SET = 1 , } impl From < RIS_COMPINVIFG_A > for bool { # [inline (always)]
fn from (variant : RIS_COMPINVIFG_A) -> Self { variant as u8 != 0 } } impl RIS_COMPINVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_COMPINVIFG_A { match self . bits { false => RIS_COMPINVIFG_A :: RIS_COMPINVIFG_CLR , true => RIS_COMPINVIFG_A :: RIS_COMPINVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_compinvifg_clr (& self) -> bool { * self == RIS_COMPINVIFG_A :: RIS_COMPINVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_compinvifg_set (& self) -> bool { * self == RIS_COMPINVIFG_A :: RIS_COMPINVIFG_SET } } # [doc = "Field `RIS_OUTRDYIFG` reader - Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid."]
pub type RIS_OUTRDYIFG_R = crate :: BitReader < RIS_OUTRDYIFG_A > ; # [doc = "Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_OUTRDYIFG_A { # [doc = "0: CLR"]
RIS_OUTRDYIFG_CLR = 0 , # [doc = "1: SET"]
RIS_OUTRDYIFG_SET = 1 , } impl From < RIS_OUTRDYIFG_A > for bool { # [inline (always)]
fn from (variant : RIS_OUTRDYIFG_A) -> Self { variant as u8 != 0 } } impl RIS_OUTRDYIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_OUTRDYIFG_A { match self . bits { false => RIS_OUTRDYIFG_A :: RIS_OUTRDYIFG_CLR , true => RIS_OUTRDYIFG_A :: RIS_OUTRDYIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_outrdyifg_clr (& self) -> bool { * self == RIS_OUTRDYIFG_A :: RIS_OUTRDYIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_outrdyifg_set (& self) -> bool { * self == RIS_OUTRDYIFG_A :: RIS_OUTRDYIFG_SET } } impl R { # [doc = "Bit 1 - Raw interrupt status for comparator output interrupt flag. The IES bit defines the transition of the comparator output setting this bit."]
# [inline (always)]
pub fn ris_compifg (& self) -> RIS_COMPIFG_R { RIS_COMPIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Raw interrupt status for comparator output inverted interrupt flag. The IES bit defines the transition of the comparator output setting this bit."]
# [inline (always)]
pub fn ris_compinvifg (& self) -> RIS_COMPINVIFG_R { RIS_COMPINVIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt status for comparator output ready interrupt flag. This bit is set when the comparator output is valid."]
# [inline (always)]
pub fn ris_outrdyifg (& self) -> RIS_OUTRDYIFG_R { RIS_OUTRDYIFG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_COMPIFG` reader - Masked interrupt status for COMPIFG"]
pub type MIS_COMPIFG_R = crate :: BitReader < MIS_COMPIFG_A > ; # [doc = "Masked interrupt status for COMPIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_COMPIFG_A { # [doc = "0: CLR"]
MIS_COMPIFG_CLR = 0 , # [doc = "1: SET"]
MIS_COMPIFG_SET = 1 , } impl From < MIS_COMPIFG_A > for bool { # [inline (always)]
fn from (variant : MIS_COMPIFG_A) -> Self { variant as u8 != 0 } } impl MIS_COMPIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_COMPIFG_A { match self . bits { false => MIS_COMPIFG_A :: MIS_COMPIFG_CLR , true => MIS_COMPIFG_A :: MIS_COMPIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_compifg_clr (& self) -> bool { * self == MIS_COMPIFG_A :: MIS_COMPIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_compifg_set (& self) -> bool { * self == MIS_COMPIFG_A :: MIS_COMPIFG_SET } } # [doc = "Field `MIS_COMPINVIFG` reader - Masked interrupt status for COMPINVIFG"]
pub type MIS_COMPINVIFG_R = crate :: BitReader < MIS_COMPINVIFG_A > ; # [doc = "Masked interrupt status for COMPINVIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_COMPINVIFG_A { # [doc = "0: CLR"]
MIS_COMPINVIFG_CLR = 0 , # [doc = "1: SET"]
MIS_COMPINVIFG_SET = 1 , } impl From < MIS_COMPINVIFG_A > for bool { # [inline (always)]
fn from (variant : MIS_COMPINVIFG_A) -> Self { variant as u8 != 0 } } impl MIS_COMPINVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_COMPINVIFG_A { match self . bits { false => MIS_COMPINVIFG_A :: MIS_COMPINVIFG_CLR , true => MIS_COMPINVIFG_A :: MIS_COMPINVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_compinvifg_clr (& self) -> bool { * self == MIS_COMPINVIFG_A :: MIS_COMPINVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_compinvifg_set (& self) -> bool { * self == MIS_COMPINVIFG_A :: MIS_COMPINVIFG_SET } } # [doc = "Field `MIS_OUTRDYIFG` reader - Masked interrupt status for OUTRDYIFG"]
pub type MIS_OUTRDYIFG_R = crate :: BitReader < MIS_OUTRDYIFG_A > ; # [doc = "Masked interrupt status for OUTRDYIFG\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_OUTRDYIFG_A { # [doc = "0: CLR"]
MIS_OUTRDYIFG_CLR = 0 , # [doc = "1: SET"]
MIS_OUTRDYIFG_SET = 1 , } impl From < MIS_OUTRDYIFG_A > for bool { # [inline (always)]
fn from (variant : MIS_OUTRDYIFG_A) -> Self { variant as u8 != 0 } } impl MIS_OUTRDYIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_OUTRDYIFG_A { match self . bits { false => MIS_OUTRDYIFG_A :: MIS_OUTRDYIFG_CLR , true => MIS_OUTRDYIFG_A :: MIS_OUTRDYIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_outrdyifg_clr (& self) -> bool { * self == MIS_OUTRDYIFG_A :: MIS_OUTRDYIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_outrdyifg_set (& self) -> bool { * self == MIS_OUTRDYIFG_A :: MIS_OUTRDYIFG_SET } } impl R { # [doc = "Bit 1 - Masked interrupt status for COMPIFG"]
# [inline (always)]
pub fn mis_compifg (& self) -> MIS_COMPIFG_R { MIS_COMPIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Masked interrupt status for COMPINVIFG"]
# [inline (always)]
pub fn mis_compinvifg (& self) -> MIS_COMPINVIFG_R { MIS_COMPINVIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Masked interrupt status for OUTRDYIFG"]
# [inline (always)]
pub fn mis_outrdyifg (& self) -> MIS_OUTRDYIFG_R { MIS_OUTRDYIFG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Sets COMPIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_COMPIFG_AW { # [doc = "0: NO_EFFECT"]
ISET_COMPIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_COMPIFG_SET = 1 , } impl From < ISET_COMPIFG_AW > for bool { # [inline (always)]
fn from (variant : ISET_COMPIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_COMPIFG` writer - Sets COMPIFG in RIS register"]
pub type ISET_COMPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_COMPIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_COMPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_compifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_COMPIFG_AW :: ISET_COMPIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_compifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_COMPIFG_AW :: ISET_COMPIFG_SET) } } # [doc = "Sets COMPINVIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_COMPINVIFG_AW { # [doc = "0: NO_EFFECT"]
ISET_COMPINVIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_COMPINVIFG_SET = 1 , } impl From < ISET_COMPINVIFG_AW > for bool { # [inline (always)]
fn from (variant : ISET_COMPINVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_COMPINVIFG` writer - Sets COMPINVIFG in RIS register"]
pub type ISET_COMPINVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_COMPINVIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_COMPINVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_compinvifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_COMPINVIFG_AW :: ISET_COMPINVIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_compinvifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_COMPINVIFG_AW :: ISET_COMPINVIFG_SET) } } # [doc = "Sets OUTRDYIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_OUTRDYIFG_AW { # [doc = "0: NO_EFFECT"]
ISET_OUTRDYIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_OUTRDYIFG_SET = 1 , } impl From < ISET_OUTRDYIFG_AW > for bool { # [inline (always)]
fn from (variant : ISET_OUTRDYIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_OUTRDYIFG` writer - Sets OUTRDYIFG in RIS register"]
pub type ISET_OUTRDYIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_OUTRDYIFG_AW > ; impl < 'a , REG , const O : u8 > ISET_OUTRDYIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_outrdyifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_OUTRDYIFG_AW :: ISET_OUTRDYIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_outrdyifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_OUTRDYIFG_AW :: ISET_OUTRDYIFG_SET) } } impl W { # [doc = "Bit 1 - Sets COMPIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_compifg (& mut self) -> ISET_COMPIFG_W < ISET_SPEC , 1 > { ISET_COMPIFG_W :: new (self) } # [doc = "Bit 2 - Sets COMPINVIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_compinvifg (& mut self) -> ISET_COMPINVIFG_W < ISET_SPEC , 2 > { ISET_COMPINVIFG_W :: new (self) } # [doc = "Bit 3 - Sets OUTRDYIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iset_outrdyifg (& mut self) -> ISET_OUTRDYIFG_W < ISET_SPEC , 3 > { ISET_OUTRDYIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Clears COMPIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_COMPIFG_AW { # [doc = "0: NO_EFFECT"]
ICLR_COMPIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_COMPIFG_CLR = 1 , } impl From < ICLR_COMPIFG_AW > for bool { # [inline (always)]
fn from (variant : ICLR_COMPIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_COMPIFG` writer - Clears COMPIFG in RIS register"]
pub type ICLR_COMPIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_COMPIFG_AW > ; impl < 'a , REG , const O : u8 > ICLR_COMPIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_compifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_COMPIFG_AW :: ICLR_COMPIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_compifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_COMPIFG_AW :: ICLR_COMPIFG_CLR) } } # [doc = "Clears COMPINVIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_COMPINVIFG_AW { # [doc = "0: NO_EFFECT"]
ICLR_COMPINVIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_COMPINVIFG_CLR = 1 , } impl From < ICLR_COMPINVIFG_AW > for bool { # [inline (always)]
fn from (variant : ICLR_COMPINVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_COMPINVIFG` writer - Clears COMPINVIFG in RIS register"]
pub type ICLR_COMPINVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_COMPINVIFG_AW > ; impl < 'a , REG , const O : u8 > ICLR_COMPINVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_compinvifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_COMPINVIFG_AW :: ICLR_COMPINVIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_compinvifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_COMPINVIFG_AW :: ICLR_COMPINVIFG_CLR) } } # [doc = "Clears OUTRDYIFG in RIS register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_OUTRDYIFG_AW { # [doc = "0: NO_EFFECT"]
ICLR_OUTRDYIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_OUTRDYIFG_CLR = 1 , } impl From < ICLR_OUTRDYIFG_AW > for bool { # [inline (always)]
fn from (variant : ICLR_OUTRDYIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_OUTRDYIFG` writer - Clears OUTRDYIFG in RIS register"]
pub type ICLR_OUTRDYIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_OUTRDYIFG_AW > ; impl < 'a , REG , const O : u8 > ICLR_OUTRDYIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_outrdyifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_OUTRDYIFG_AW :: ICLR_OUTRDYIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_outrdyifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_OUTRDYIFG_AW :: ICLR_OUTRDYIFG_CLR) } } impl W { # [doc = "Bit 1 - Clears COMPIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_compifg (& mut self) -> ICLR_COMPIFG_W < ICLR_SPEC , 1 > { ICLR_COMPIFG_W :: new (self) } # [doc = "Bit 2 - Clears COMPINVIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_compinvifg (& mut self) -> ICLR_COMPINVIFG_W < ICLR_SPEC , 2 > { ICLR_COMPINVIFG_W :: new (self) } # [doc = "Bit 3 - Clears OUTRDYIFG in RIS register"]
# [inline (always)]
# [must_use]
pub fn iclr_outrdyifg (& mut self) -> ICLR_OUTRDYIFG_W < ICLR_SPEC , 3 > { ICLR_OUTRDYIFG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0x09"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0x09 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL0 (rw) register accessor: Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl0`]
module"]
pub type CTL0 = crate :: Reg < ctl0 :: CTL0_SPEC > ; # [doc = "Control 0"]
pub mod ctl0 { # [doc = "Register `CTL0` reader"]
pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"]
pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_IPSEL` reader - Channel input selected for the positive terminal of the comparator if IPEN is set to 1."]
pub type CTL0_IPSEL_R = crate :: FieldReader < CTL0_IPSEL_A > ; # [doc = "Channel input selected for the positive terminal of the comparator if IPEN is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_IPSEL_A { # [doc = "0: CH_0"]
CTL0_IPSEL_CH_0 = 0 , # [doc = "1: CH_1"]
CTL0_IPSEL_CH_1 = 1 , # [doc = "2: CH_2"]
CTL0_IPSEL_CH_2 = 2 , # [doc = "3: CH_3"]
CTL0_IPSEL_CH_3 = 3 , # [doc = "4: CH_4"]
CTL0_IPSEL_CH_4 = 4 , # [doc = "5: CH_5"]
CTL0_IPSEL_CH_5 = 5 , # [doc = "6: CH_6"]
CTL0_IPSEL_CH_6 = 6 , # [doc = "7: CH_7"]
CTL0_IPSEL_CH_7 = 7 , } impl From < CTL0_IPSEL_A > for u8 { # [inline (always)]
fn from (variant : CTL0_IPSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_IPSEL_A { type Ux = u8 ; } impl CTL0_IPSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_IPSEL_A { match self . bits { 0 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_0 , 1 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_1 , 2 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_2 , 3 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_3 , 4 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_4 , 5 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_5 , 6 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_6 , 7 => CTL0_IPSEL_A :: CTL0_IPSEL_CH_7 , _ => unreachable ! () , } } # [doc = "CH_0"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_0 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_0 } # [doc = "CH_1"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_1 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_1 } # [doc = "CH_2"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_2 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_2 } # [doc = "CH_3"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_3 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_3 } # [doc = "CH_4"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_4 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_4 } # [doc = "CH_5"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_5 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_5 } # [doc = "CH_6"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_6 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_6 } # [doc = "CH_7"]
# [inline (always)]
pub fn is_ctl0_ipsel_ch_7 (& self) -> bool { * self == CTL0_IPSEL_A :: CTL0_IPSEL_CH_7 } } # [doc = "Field `CTL0_IPSEL` writer - Channel input selected for the positive terminal of the comparator if IPEN is set to 1."]
pub type CTL0_IPSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CTL0_IPSEL_A > ; impl < 'a , REG , const O : u8 > CTL0_IPSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CH_0"]
# [inline (always)]
pub fn ctl0_ipsel_ch_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_0) } # [doc = "CH_1"]
# [inline (always)]
pub fn ctl0_ipsel_ch_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_1) } # [doc = "CH_2"]
# [inline (always)]
pub fn ctl0_ipsel_ch_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_2) } # [doc = "CH_3"]
# [inline (always)]
pub fn ctl0_ipsel_ch_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_3) } # [doc = "CH_4"]
# [inline (always)]
pub fn ctl0_ipsel_ch_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_4) } # [doc = "CH_5"]
# [inline (always)]
pub fn ctl0_ipsel_ch_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_5) } # [doc = "CH_6"]
# [inline (always)]
pub fn ctl0_ipsel_ch_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_6) } # [doc = "CH_7"]
# [inline (always)]
pub fn ctl0_ipsel_ch_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPSEL_A :: CTL0_IPSEL_CH_7) } } # [doc = "Field `CTL0_IPEN` reader - Channel input enable for the positive terminal of the comparator."]
pub type CTL0_IPEN_R = crate :: BitReader < CTL0_IPEN_A > ; # [doc = "Channel input enable for the positive terminal of the comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_IPEN_A { # [doc = "0: DISABLE"]
CTL0_IPEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_IPEN_ENABLE = 1 , } impl From < CTL0_IPEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_IPEN_A) -> Self { variant as u8 != 0 } } impl CTL0_IPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_IPEN_A { match self . bits { false => CTL0_IPEN_A :: CTL0_IPEN_DISABLE , true => CTL0_IPEN_A :: CTL0_IPEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_ipen_disable (& self) -> bool { * self == CTL0_IPEN_A :: CTL0_IPEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_ipen_enable (& self) -> bool { * self == CTL0_IPEN_A :: CTL0_IPEN_ENABLE } } # [doc = "Field `CTL0_IPEN` writer - Channel input enable for the positive terminal of the comparator."]
pub type CTL0_IPEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_IPEN_A > ; impl < 'a , REG , const O : u8 > CTL0_IPEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_ipen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPEN_A :: CTL0_IPEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_ipen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IPEN_A :: CTL0_IPEN_ENABLE) } } # [doc = "Field `CTL0_IMSEL` reader - Channel input selected for the negative terminal of the comparator if IMEN is set to 1."]
pub type CTL0_IMSEL_R = crate :: FieldReader < CTL0_IMSEL_A > ; # [doc = "Channel input selected for the negative terminal of the comparator if IMEN is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_IMSEL_A { # [doc = "0: CH_0"]
CTL0_IMSEL_CH_0 = 0 , # [doc = "1: CH_1"]
CTL0_IMSEL_CH_1 = 1 , # [doc = "2: CH_2"]
CTL0_IMSEL_CH_2 = 2 , # [doc = "3: CH_3"]
CTL0_IMSEL_CH_3 = 3 , # [doc = "4: CH_4"]
CTL0_IMSEL_CH_4 = 4 , # [doc = "5: CH_5"]
CTL0_IMSEL_CH_5 = 5 , # [doc = "6: CH_6"]
CTL0_IMSEL_CH_6 = 6 , # [doc = "7: CH_7"]
CTL0_IMSEL_CH_7 = 7 , } impl From < CTL0_IMSEL_A > for u8 { # [inline (always)]
fn from (variant : CTL0_IMSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_IMSEL_A { type Ux = u8 ; } impl CTL0_IMSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_IMSEL_A { match self . bits { 0 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_0 , 1 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_1 , 2 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_2 , 3 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_3 , 4 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_4 , 5 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_5 , 6 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_6 , 7 => CTL0_IMSEL_A :: CTL0_IMSEL_CH_7 , _ => unreachable ! () , } } # [doc = "CH_0"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_0 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_0 } # [doc = "CH_1"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_1 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_1 } # [doc = "CH_2"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_2 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_2 } # [doc = "CH_3"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_3 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_3 } # [doc = "CH_4"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_4 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_4 } # [doc = "CH_5"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_5 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_5 } # [doc = "CH_6"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_6 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_6 } # [doc = "CH_7"]
# [inline (always)]
pub fn is_ctl0_imsel_ch_7 (& self) -> bool { * self == CTL0_IMSEL_A :: CTL0_IMSEL_CH_7 } } # [doc = "Field `CTL0_IMSEL` writer - Channel input selected for the negative terminal of the comparator if IMEN is set to 1."]
pub type CTL0_IMSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CTL0_IMSEL_A > ; impl < 'a , REG , const O : u8 > CTL0_IMSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CH_0"]
# [inline (always)]
pub fn ctl0_imsel_ch_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_0) } # [doc = "CH_1"]
# [inline (always)]
pub fn ctl0_imsel_ch_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_1) } # [doc = "CH_2"]
# [inline (always)]
pub fn ctl0_imsel_ch_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_2) } # [doc = "CH_3"]
# [inline (always)]
pub fn ctl0_imsel_ch_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_3) } # [doc = "CH_4"]
# [inline (always)]
pub fn ctl0_imsel_ch_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_4) } # [doc = "CH_5"]
# [inline (always)]
pub fn ctl0_imsel_ch_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_5) } # [doc = "CH_6"]
# [inline (always)]
pub fn ctl0_imsel_ch_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_6) } # [doc = "CH_7"]
# [inline (always)]
pub fn ctl0_imsel_ch_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMSEL_A :: CTL0_IMSEL_CH_7) } } # [doc = "Field `CTL0_IMEN` reader - Channel input enable for the negative terminal of the comparator."]
pub type CTL0_IMEN_R = crate :: BitReader < CTL0_IMEN_A > ; # [doc = "Channel input enable for the negative terminal of the comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_IMEN_A { # [doc = "0: DISABLE"]
CTL0_IMEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL0_IMEN_ENABLE = 1 , } impl From < CTL0_IMEN_A > for bool { # [inline (always)]
fn from (variant : CTL0_IMEN_A) -> Self { variant as u8 != 0 } } impl CTL0_IMEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_IMEN_A { match self . bits { false => CTL0_IMEN_A :: CTL0_IMEN_DISABLE , true => CTL0_IMEN_A :: CTL0_IMEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl0_imen_disable (& self) -> bool { * self == CTL0_IMEN_A :: CTL0_IMEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl0_imen_enable (& self) -> bool { * self == CTL0_IMEN_A :: CTL0_IMEN_ENABLE } } # [doc = "Field `CTL0_IMEN` writer - Channel input enable for the negative terminal of the comparator."]
pub type CTL0_IMEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_IMEN_A > ; impl < 'a , REG , const O : u8 > CTL0_IMEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl0_imen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMEN_A :: CTL0_IMEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl0_imen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_IMEN_A :: CTL0_IMEN_ENABLE) } } impl R { # [doc = "Bits 0:2 - Channel input selected for the positive terminal of the comparator if IPEN is set to 1."]
# [inline (always)]
pub fn ctl0_ipsel (& self) -> CTL0_IPSEL_R { CTL0_IPSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 15 - Channel input enable for the positive terminal of the comparator."]
# [inline (always)]
pub fn ctl0_ipen (& self) -> CTL0_IPEN_R { CTL0_IPEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:18 - Channel input selected for the negative terminal of the comparator if IMEN is set to 1."]
# [inline (always)]
pub fn ctl0_imsel (& self) -> CTL0_IMSEL_R { CTL0_IMSEL_R :: new (((self . bits >> 16) & 7) as u8) } # [doc = "Bit 31 - Channel input enable for the negative terminal of the comparator."]
# [inline (always)]
pub fn ctl0_imen (& self) -> CTL0_IMEN_R { CTL0_IMEN_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Channel input selected for the positive terminal of the comparator if IPEN is set to 1."]
# [inline (always)]
# [must_use]
pub fn ctl0_ipsel (& mut self) -> CTL0_IPSEL_W < CTL0_SPEC , 0 > { CTL0_IPSEL_W :: new (self) } # [doc = "Bit 15 - Channel input enable for the positive terminal of the comparator."]
# [inline (always)]
# [must_use]
pub fn ctl0_ipen (& mut self) -> CTL0_IPEN_W < CTL0_SPEC , 15 > { CTL0_IPEN_W :: new (self) } # [doc = "Bits 16:18 - Channel input selected for the negative terminal of the comparator if IMEN is set to 1."]
# [inline (always)]
# [must_use]
pub fn ctl0_imsel (& mut self) -> CTL0_IMSEL_W < CTL0_SPEC , 16 > { CTL0_IMSEL_W :: new (self) } # [doc = "Bit 31 - Channel input enable for the negative terminal of the comparator."]
# [inline (always)]
# [must_use]
pub fn ctl0_imen (& mut self) -> CTL0_IMEN_W < CTL0_SPEC , 31 > { CTL0_IMEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0"]
impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL1 (rw) register accessor: Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl1`]
module"]
pub type CTL1 = crate :: Reg < ctl1 :: CTL1_SPEC > ; # [doc = "Control 1"]
pub mod ctl1 { # [doc = "Register `CTL1` reader"]
pub type R = crate :: R < CTL1_SPEC > ; # [doc = "Register `CTL1` writer"]
pub type W = crate :: W < CTL1_SPEC > ; # [doc = "Field `CTL1_ENABLE` reader - This bit turns on the comparator. When the comparator is turned off it consumes no power."]
pub type CTL1_ENABLE_R = crate :: BitReader < CTL1_ENABLE_A > ; # [doc = "This bit turns on the comparator. When the comparator is turned off it consumes no power.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_ENABLE_A { # [doc = "0: OFF"]
CTL1_ENABLE_OFF = 0 , # [doc = "1: ON"]
CTL1_ENABLE_ON = 1 , } impl From < CTL1_ENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL1_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL1_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_ENABLE_A { match self . bits { false => CTL1_ENABLE_A :: CTL1_ENABLE_OFF , true => CTL1_ENABLE_A :: CTL1_ENABLE_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_ctl1_enable_off (& self) -> bool { * self == CTL1_ENABLE_A :: CTL1_ENABLE_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_ctl1_enable_on (& self) -> bool { * self == CTL1_ENABLE_A :: CTL1_ENABLE_ON } } # [doc = "Field `CTL1_ENABLE` writer - This bit turns on the comparator. When the comparator is turned off it consumes no power."]
pub type CTL1_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL1_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"]
# [inline (always)]
pub fn ctl1_enable_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_ENABLE_A :: CTL1_ENABLE_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn ctl1_enable_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_ENABLE_A :: CTL1_ENABLE_ON) } } # [doc = "Field `CTL1_MODE` reader - This bit selects the comparator operating mode."]
pub type CTL1_MODE_R = crate :: BitReader < CTL1_MODE_A > ; # [doc = "This bit selects the comparator operating mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_MODE_A { # [doc = "0: FAST"]
CTL1_MODE_FAST = 0 , # [doc = "1: ULP"]
CTL1_MODE_ULP = 1 , } impl From < CTL1_MODE_A > for bool { # [inline (always)]
fn from (variant : CTL1_MODE_A) -> Self { variant as u8 != 0 } } impl CTL1_MODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_MODE_A { match self . bits { false => CTL1_MODE_A :: CTL1_MODE_FAST , true => CTL1_MODE_A :: CTL1_MODE_ULP , } } # [doc = "FAST"]
# [inline (always)]
pub fn is_ctl1_mode_fast (& self) -> bool { * self == CTL1_MODE_A :: CTL1_MODE_FAST } # [doc = "ULP"]
# [inline (always)]
pub fn is_ctl1_mode_ulp (& self) -> bool { * self == CTL1_MODE_A :: CTL1_MODE_ULP } } # [doc = "Field `CTL1_MODE` writer - This bit selects the comparator operating mode."]
pub type CTL1_MODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_MODE_A > ; impl < 'a , REG , const O : u8 > CTL1_MODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FAST"]
# [inline (always)]
pub fn ctl1_mode_fast (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_MODE_A :: CTL1_MODE_FAST) } # [doc = "ULP"]
# [inline (always)]
pub fn ctl1_mode_ulp (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_MODE_A :: CTL1_MODE_ULP) } } # [doc = "Field `CTL1_EXCH` reader - This bit exchanges the comparator inputs and inverts the comparator output."]
pub type CTL1_EXCH_R = crate :: BitReader < CTL1_EXCH_A > ; # [doc = "This bit exchanges the comparator inputs and inverts the comparator output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_EXCH_A { # [doc = "0: NO_EXC"]
CTL1_EXCH_NO_EXC = 0 , # [doc = "1: EXC"]
CTL1_EXCH_EXC = 1 , } impl From < CTL1_EXCH_A > for bool { # [inline (always)]
fn from (variant : CTL1_EXCH_A) -> Self { variant as u8 != 0 } } impl CTL1_EXCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_EXCH_A { match self . bits { false => CTL1_EXCH_A :: CTL1_EXCH_NO_EXC , true => CTL1_EXCH_A :: CTL1_EXCH_EXC , } } # [doc = "NO_EXC"]
# [inline (always)]
pub fn is_ctl1_exch_no_exc (& self) -> bool { * self == CTL1_EXCH_A :: CTL1_EXCH_NO_EXC } # [doc = "EXC"]
# [inline (always)]
pub fn is_ctl1_exch_exc (& self) -> bool { * self == CTL1_EXCH_A :: CTL1_EXCH_EXC } } # [doc = "Field `CTL1_EXCH` writer - This bit exchanges the comparator inputs and inverts the comparator output."]
pub type CTL1_EXCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_EXCH_A > ; impl < 'a , REG , const O : u8 > CTL1_EXCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EXC"]
# [inline (always)]
pub fn ctl1_exch_no_exc (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_EXCH_A :: CTL1_EXCH_NO_EXC) } # [doc = "EXC"]
# [inline (always)]
pub fn ctl1_exch_exc (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_EXCH_A :: CTL1_EXCH_EXC) } } # [doc = "Field `CTL1_SHORT` reader - This bit shorts the positive and negative input terminals of the comparator."]
pub type CTL1_SHORT_R = crate :: BitReader < CTL1_SHORT_A > ; # [doc = "This bit shorts the positive and negative input terminals of the comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_SHORT_A { # [doc = "0: NO_SHT"]
CTL1_SHORT_NO_SHT = 0 , # [doc = "1: SHT"]
CTL1_SHORT_SHT = 1 , } impl From < CTL1_SHORT_A > for bool { # [inline (always)]
fn from (variant : CTL1_SHORT_A) -> Self { variant as u8 != 0 } } impl CTL1_SHORT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_SHORT_A { match self . bits { false => CTL1_SHORT_A :: CTL1_SHORT_NO_SHT , true => CTL1_SHORT_A :: CTL1_SHORT_SHT , } } # [doc = "NO_SHT"]
# [inline (always)]
pub fn is_ctl1_short_no_sht (& self) -> bool { * self == CTL1_SHORT_A :: CTL1_SHORT_NO_SHT } # [doc = "SHT"]
# [inline (always)]
pub fn is_ctl1_short_sht (& self) -> bool { * self == CTL1_SHORT_A :: CTL1_SHORT_SHT } } # [doc = "Field `CTL1_SHORT` writer - This bit shorts the positive and negative input terminals of the comparator."]
pub type CTL1_SHORT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_SHORT_A > ; impl < 'a , REG , const O : u8 > CTL1_SHORT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_SHT"]
# [inline (always)]
pub fn ctl1_short_no_sht (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SHORT_A :: CTL1_SHORT_NO_SHT) } # [doc = "SHT"]
# [inline (always)]
pub fn ctl1_short_sht (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SHORT_A :: CTL1_SHORT_SHT) } } # [doc = "Field `CTL1_IES` reader - This bit selected the interrupt edge for COMPIFG and COMPINVIFG."]
pub type CTL1_IES_R = crate :: BitReader < CTL1_IES_A > ; # [doc = "This bit selected the interrupt edge for COMPIFG and COMPINVIFG.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_IES_A { # [doc = "0: RISING"]
CTL1_IES_RISING = 0 , # [doc = "1: FALLING"]
CTL1_IES_FALLING = 1 , } impl From < CTL1_IES_A > for bool { # [inline (always)]
fn from (variant : CTL1_IES_A) -> Self { variant as u8 != 0 } } impl CTL1_IES_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_IES_A { match self . bits { false => CTL1_IES_A :: CTL1_IES_RISING , true => CTL1_IES_A :: CTL1_IES_FALLING , } } # [doc = "RISING"]
# [inline (always)]
pub fn is_ctl1_ies_rising (& self) -> bool { * self == CTL1_IES_A :: CTL1_IES_RISING } # [doc = "FALLING"]
# [inline (always)]
pub fn is_ctl1_ies_falling (& self) -> bool { * self == CTL1_IES_A :: CTL1_IES_FALLING } } # [doc = "Field `CTL1_IES` writer - This bit selected the interrupt edge for COMPIFG and COMPINVIFG."]
pub type CTL1_IES_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_IES_A > ; impl < 'a , REG , const O : u8 > CTL1_IES_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RISING"]
# [inline (always)]
pub fn ctl1_ies_rising (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_IES_A :: CTL1_IES_RISING) } # [doc = "FALLING"]
# [inline (always)]
pub fn ctl1_ies_falling (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_IES_A :: CTL1_IES_FALLING) } } # [doc = "Field `CTL1_HYST` reader - These bits select the hysteresis setting of the comparator."]
pub type CTL1_HYST_R = crate :: FieldReader < CTL1_HYST_A > ; # [doc = "These bits select the hysteresis setting of the comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL1_HYST_A { # [doc = "0: NO_HYS"]
CTL1_HYST_NO_HYS = 0 , # [doc = "1: LOW_HYS"]
CTL1_HYST_LOW_HYS = 1 , # [doc = "2: MED_HYS"]
CTL1_HYST_MED_HYS = 2 , # [doc = "3: HIGH_HYS"]
CTL1_HYST_HIGH_HYS = 3 , } impl From < CTL1_HYST_A > for u8 { # [inline (always)]
fn from (variant : CTL1_HYST_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL1_HYST_A { type Ux = u8 ; } impl CTL1_HYST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_HYST_A { match self . bits { 0 => CTL1_HYST_A :: CTL1_HYST_NO_HYS , 1 => CTL1_HYST_A :: CTL1_HYST_LOW_HYS , 2 => CTL1_HYST_A :: CTL1_HYST_MED_HYS , 3 => CTL1_HYST_A :: CTL1_HYST_HIGH_HYS , _ => unreachable ! () , } } # [doc = "NO_HYS"]
# [inline (always)]
pub fn is_ctl1_hyst_no_hys (& self) -> bool { * self == CTL1_HYST_A :: CTL1_HYST_NO_HYS } # [doc = "LOW_HYS"]
# [inline (always)]
pub fn is_ctl1_hyst_low_hys (& self) -> bool { * self == CTL1_HYST_A :: CTL1_HYST_LOW_HYS } # [doc = "MED_HYS"]
# [inline (always)]
pub fn is_ctl1_hyst_med_hys (& self) -> bool { * self == CTL1_HYST_A :: CTL1_HYST_MED_HYS } # [doc = "HIGH_HYS"]
# [inline (always)]
pub fn is_ctl1_hyst_high_hys (& self) -> bool { * self == CTL1_HYST_A :: CTL1_HYST_HIGH_HYS } } # [doc = "Field `CTL1_HYST` writer - These bits select the hysteresis setting of the comparator."]
pub type CTL1_HYST_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL1_HYST_A > ; impl < 'a , REG , const O : u8 > CTL1_HYST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NO_HYS"]
# [inline (always)]
pub fn ctl1_hyst_no_hys (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_HYST_A :: CTL1_HYST_NO_HYS) } # [doc = "LOW_HYS"]
# [inline (always)]
pub fn ctl1_hyst_low_hys (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_HYST_A :: CTL1_HYST_LOW_HYS) } # [doc = "MED_HYS"]
# [inline (always)]
pub fn ctl1_hyst_med_hys (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_HYST_A :: CTL1_HYST_MED_HYS) } # [doc = "HIGH_HYS"]
# [inline (always)]
pub fn ctl1_hyst_high_hys (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_HYST_A :: CTL1_HYST_HIGH_HYS) } } # [doc = "Field `CTL1_OUTPOL` reader - This bit selects the comparator output polarity."]
pub type CTL1_OUTPOL_R = crate :: BitReader < CTL1_OUTPOL_A > ; # [doc = "This bit selects the comparator output polarity.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_OUTPOL_A { # [doc = "0: NON_INV"]
CTL1_OUTPOL_NON_INV = 0 , # [doc = "1: INV"]
CTL1_OUTPOL_INV = 1 , } impl From < CTL1_OUTPOL_A > for bool { # [inline (always)]
fn from (variant : CTL1_OUTPOL_A) -> Self { variant as u8 != 0 } } impl CTL1_OUTPOL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_OUTPOL_A { match self . bits { false => CTL1_OUTPOL_A :: CTL1_OUTPOL_NON_INV , true => CTL1_OUTPOL_A :: CTL1_OUTPOL_INV , } } # [doc = "NON_INV"]
# [inline (always)]
pub fn is_ctl1_outpol_non_inv (& self) -> bool { * self == CTL1_OUTPOL_A :: CTL1_OUTPOL_NON_INV } # [doc = "INV"]
# [inline (always)]
pub fn is_ctl1_outpol_inv (& self) -> bool { * self == CTL1_OUTPOL_A :: CTL1_OUTPOL_INV } } # [doc = "Field `CTL1_OUTPOL` writer - This bit selects the comparator output polarity."]
pub type CTL1_OUTPOL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_OUTPOL_A > ; impl < 'a , REG , const O : u8 > CTL1_OUTPOL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NON_INV"]
# [inline (always)]
pub fn ctl1_outpol_non_inv (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_OUTPOL_A :: CTL1_OUTPOL_NON_INV) } # [doc = "INV"]
# [inline (always)]
pub fn ctl1_outpol_inv (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_OUTPOL_A :: CTL1_OUTPOL_INV) } } # [doc = "Field `CTL1_FLTEN` reader - This bit enables the analog filter at comparator output."]
pub type CTL1_FLTEN_R = crate :: BitReader < CTL1_FLTEN_A > ; # [doc = "This bit enables the analog filter at comparator output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_FLTEN_A { # [doc = "0: DISABLE"]
CTL1_FLTEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL1_FLTEN_ENABLE = 1 , } impl From < CTL1_FLTEN_A > for bool { # [inline (always)]
fn from (variant : CTL1_FLTEN_A) -> Self { variant as u8 != 0 } } impl CTL1_FLTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_FLTEN_A { match self . bits { false => CTL1_FLTEN_A :: CTL1_FLTEN_DISABLE , true => CTL1_FLTEN_A :: CTL1_FLTEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_flten_disable (& self) -> bool { * self == CTL1_FLTEN_A :: CTL1_FLTEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl1_flten_enable (& self) -> bool { * self == CTL1_FLTEN_A :: CTL1_FLTEN_ENABLE } } # [doc = "Field `CTL1_FLTEN` writer - This bit enables the analog filter at comparator output."]
pub type CTL1_FLTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_FLTEN_A > ; impl < 'a , REG , const O : u8 > CTL1_FLTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_flten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_FLTEN_A :: CTL1_FLTEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl1_flten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_FLTEN_A :: CTL1_FLTEN_ENABLE) } } # [doc = "Field `CTL1_FLTDLY` reader - These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings."]
pub type CTL1_FLTDLY_R = crate :: FieldReader < CTL1_FLTDLY_A > ; # [doc = "These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL1_FLTDLY_A { # [doc = "0: DLY_0"]
CTL1_FLTDLY_DLY_0 = 0 , # [doc = "1: DLY_1"]
CTL1_FLTDLY_DLY_1 = 1 , # [doc = "2: DLY_2"]
CTL1_FLTDLY_DLY_2 = 2 , # [doc = "3: DLY_3"]
CTL1_FLTDLY_DLY_3 = 3 , } impl From < CTL1_FLTDLY_A > for u8 { # [inline (always)]
fn from (variant : CTL1_FLTDLY_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL1_FLTDLY_A { type Ux = u8 ; } impl CTL1_FLTDLY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_FLTDLY_A { match self . bits { 0 => CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_0 , 1 => CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_1 , 2 => CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_2 , 3 => CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_3 , _ => unreachable ! () , } } # [doc = "DLY_0"]
# [inline (always)]
pub fn is_ctl1_fltdly_dly_0 (& self) -> bool { * self == CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_0 } # [doc = "DLY_1"]
# [inline (always)]
pub fn is_ctl1_fltdly_dly_1 (& self) -> bool { * self == CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_1 } # [doc = "DLY_2"]
# [inline (always)]
pub fn is_ctl1_fltdly_dly_2 (& self) -> bool { * self == CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_2 } # [doc = "DLY_3"]
# [inline (always)]
pub fn is_ctl1_fltdly_dly_3 (& self) -> bool { * self == CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_3 } } # [doc = "Field `CTL1_FLTDLY` writer - These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings."]
pub type CTL1_FLTDLY_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL1_FLTDLY_A > ; impl < 'a , REG , const O : u8 > CTL1_FLTDLY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DLY_0"]
# [inline (always)]
pub fn ctl1_fltdly_dly_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_0) } # [doc = "DLY_1"]
# [inline (always)]
pub fn ctl1_fltdly_dly_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_1) } # [doc = "DLY_2"]
# [inline (always)]
pub fn ctl1_fltdly_dly_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_2) } # [doc = "DLY_3"]
# [inline (always)]
pub fn ctl1_fltdly_dly_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_FLTDLY_A :: CTL1_FLTDLY_DLY_3) } } # [doc = "Field `CTL1_WINCOMPEN` reader - This bit enables window comparator operation of comparator."]
pub type CTL1_WINCOMPEN_R = crate :: BitReader < CTL1_WINCOMPEN_A > ; # [doc = "This bit enables window comparator operation of comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_WINCOMPEN_A { # [doc = "0: OFF"]
CTL1_WINCOMPEN_OFF = 0 , # [doc = "1: ON"]
CTL1_WINCOMPEN_ON = 1 , } impl From < CTL1_WINCOMPEN_A > for bool { # [inline (always)]
fn from (variant : CTL1_WINCOMPEN_A) -> Self { variant as u8 != 0 } } impl CTL1_WINCOMPEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_WINCOMPEN_A { match self . bits { false => CTL1_WINCOMPEN_A :: CTL1_WINCOMPEN_OFF , true => CTL1_WINCOMPEN_A :: CTL1_WINCOMPEN_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_ctl1_wincompen_off (& self) -> bool { * self == CTL1_WINCOMPEN_A :: CTL1_WINCOMPEN_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_ctl1_wincompen_on (& self) -> bool { * self == CTL1_WINCOMPEN_A :: CTL1_WINCOMPEN_ON } } # [doc = "Field `CTL1_WINCOMPEN` writer - This bit enables window comparator operation of comparator."]
pub type CTL1_WINCOMPEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_WINCOMPEN_A > ; impl < 'a , REG , const O : u8 > CTL1_WINCOMPEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"]
# [inline (always)]
pub fn ctl1_wincompen_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_WINCOMPEN_A :: CTL1_WINCOMPEN_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn ctl1_wincompen_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_WINCOMPEN_A :: CTL1_WINCOMPEN_ON) } } impl R { # [doc = "Bit 0 - This bit turns on the comparator. When the comparator is turned off it consumes no power."]
# [inline (always)]
pub fn ctl1_enable (& self) -> CTL1_ENABLE_R { CTL1_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - This bit selects the comparator operating mode."]
# [inline (always)]
pub fn ctl1_mode (& self) -> CTL1_MODE_R { CTL1_MODE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - This bit exchanges the comparator inputs and inverts the comparator output."]
# [inline (always)]
pub fn ctl1_exch (& self) -> CTL1_EXCH_R { CTL1_EXCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - This bit shorts the positive and negative input terminals of the comparator."]
# [inline (always)]
pub fn ctl1_short (& self) -> CTL1_SHORT_R { CTL1_SHORT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - This bit selected the interrupt edge for COMPIFG and COMPINVIFG."]
# [inline (always)]
pub fn ctl1_ies (& self) -> CTL1_IES_R { CTL1_IES_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bits 5:6 - These bits select the hysteresis setting of the comparator."]
# [inline (always)]
pub fn ctl1_hyst (& self) -> CTL1_HYST_R { CTL1_HYST_R :: new (((self . bits >> 5) & 3) as u8) } # [doc = "Bit 7 - This bit selects the comparator output polarity."]
# [inline (always)]
pub fn ctl1_outpol (& self) -> CTL1_OUTPOL_R { CTL1_OUTPOL_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - This bit enables the analog filter at comparator output."]
# [inline (always)]
pub fn ctl1_flten (& self) -> CTL1_FLTEN_R { CTL1_FLTEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings."]
# [inline (always)]
pub fn ctl1_fltdly (& self) -> CTL1_FLTDLY_R { CTL1_FLTDLY_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 12 - This bit enables window comparator operation of comparator."]
# [inline (always)]
pub fn ctl1_wincompen (& self) -> CTL1_WINCOMPEN_R { CTL1_WINCOMPEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bit 0 - This bit turns on the comparator. When the comparator is turned off it consumes no power."]
# [inline (always)]
# [must_use]
pub fn ctl1_enable (& mut self) -> CTL1_ENABLE_W < CTL1_SPEC , 0 > { CTL1_ENABLE_W :: new (self) } # [doc = "Bit 1 - This bit selects the comparator operating mode."]
# [inline (always)]
# [must_use]
pub fn ctl1_mode (& mut self) -> CTL1_MODE_W < CTL1_SPEC , 1 > { CTL1_MODE_W :: new (self) } # [doc = "Bit 2 - This bit exchanges the comparator inputs and inverts the comparator output."]
# [inline (always)]
# [must_use]
pub fn ctl1_exch (& mut self) -> CTL1_EXCH_W < CTL1_SPEC , 2 > { CTL1_EXCH_W :: new (self) } # [doc = "Bit 3 - This bit shorts the positive and negative input terminals of the comparator."]
# [inline (always)]
# [must_use]
pub fn ctl1_short (& mut self) -> CTL1_SHORT_W < CTL1_SPEC , 3 > { CTL1_SHORT_W :: new (self) } # [doc = "Bit 4 - This bit selected the interrupt edge for COMPIFG and COMPINVIFG."]
# [inline (always)]
# [must_use]
pub fn ctl1_ies (& mut self) -> CTL1_IES_W < CTL1_SPEC , 4 > { CTL1_IES_W :: new (self) } # [doc = "Bits 5:6 - These bits select the hysteresis setting of the comparator."]
# [inline (always)]
# [must_use]
pub fn ctl1_hyst (& mut self) -> CTL1_HYST_W < CTL1_SPEC , 5 > { CTL1_HYST_W :: new (self) } # [doc = "Bit 7 - This bit selects the comparator output polarity."]
# [inline (always)]
# [must_use]
pub fn ctl1_outpol (& mut self) -> CTL1_OUTPOL_W < CTL1_SPEC , 7 > { CTL1_OUTPOL_W :: new (self) } # [doc = "Bit 8 - This bit enables the analog filter at comparator output."]
# [inline (always)]
# [must_use]
pub fn ctl1_flten (& mut self) -> CTL1_FLTEN_W < CTL1_SPEC , 8 > { CTL1_FLTEN_W :: new (self) } # [doc = "Bits 9:10 - These bits select the comparator output filter delay. See the device-specific data sheet for specific values on comparator propagation delay for different filter delay settings."]
# [inline (always)]
# [must_use]
pub fn ctl1_fltdly (& mut self) -> CTL1_FLTDLY_W < CTL1_SPEC , 9 > { CTL1_FLTDLY_W :: new (self) } # [doc = "Bit 12 - This bit enables window comparator operation of comparator."]
# [inline (always)]
# [must_use]
pub fn ctl1_wincompen (& mut self) -> CTL1_WINCOMPEN_W < CTL1_SPEC , 12 > { CTL1_WINCOMPEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL1_SPEC ; impl crate :: RegisterSpec for CTL1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl1::R`](R) reader structure"]
impl crate :: Readable for CTL1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl1::W`](W) writer structure"]
impl crate :: Writable for CTL1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL1 to value 0"]
impl crate :: Resettable for CTL1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL2 (rw) register accessor: Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl2`]
module"]
pub type CTL2 = crate :: Reg < ctl2 :: CTL2_SPEC > ; # [doc = "Control 2"]
pub mod ctl2 { # [doc = "Register `CTL2` reader"]
pub type R = crate :: R < CTL2_SPEC > ; # [doc = "Register `CTL2` writer"]
pub type W = crate :: W < CTL2_SPEC > ; # [doc = "Field `CTL2_REFMODE` reader - This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL &amp;gt; 0."]
pub type CTL2_REFMODE_R = crate :: BitReader < CTL2_REFMODE_A > ; # [doc = "This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL &amp;gt; 0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_REFMODE_A { # [doc = "0: STATIC"]
CTL2_REFMODE_STATIC = 0 , # [doc = "1: SAMPLED"]
CTL2_REFMODE_SAMPLED = 1 , } impl From < CTL2_REFMODE_A > for bool { # [inline (always)]
fn from (variant : CTL2_REFMODE_A) -> Self { variant as u8 != 0 } } impl CTL2_REFMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_REFMODE_A { match self . bits { false => CTL2_REFMODE_A :: CTL2_REFMODE_STATIC , true => CTL2_REFMODE_A :: CTL2_REFMODE_SAMPLED , } } # [doc = "STATIC"]
# [inline (always)]
pub fn is_ctl2_refmode_static (& self) -> bool { * self == CTL2_REFMODE_A :: CTL2_REFMODE_STATIC } # [doc = "SAMPLED"]
# [inline (always)]
pub fn is_ctl2_refmode_sampled (& self) -> bool { * self == CTL2_REFMODE_A :: CTL2_REFMODE_SAMPLED } } # [doc = "Field `CTL2_REFMODE` writer - This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL &amp;gt; 0."]
pub type CTL2_REFMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_REFMODE_A > ; impl < 'a , REG , const O : u8 > CTL2_REFMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STATIC"]
# [inline (always)]
pub fn ctl2_refmode_static (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFMODE_A :: CTL2_REFMODE_STATIC) } # [doc = "SAMPLED"]
# [inline (always)]
pub fn ctl2_refmode_sampled (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFMODE_A :: CTL2_REFMODE_SAMPLED) } } # [doc = "Field `CTL2_REFSRC` reader - These bits select the reference source for the comparator."]
pub type CTL2_REFSRC_R = crate :: FieldReader < CTL2_REFSRC_A > ; # [doc = "These bits select the reference source for the comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL2_REFSRC_A { # [doc = "0: OFF"]
CTL2_REFSRC_OFF = 0 , # [doc = "1: VDDA_DAC"]
CTL2_REFSRC_VDDA_DAC = 1 , # [doc = "2: VREF_DAC"]
CTL2_REFSRC_VREF_DAC = 2 , # [doc = "3: VREF"]
CTL2_REFSRC_VREF = 3 , } impl From < CTL2_REFSRC_A > for u8 { # [inline (always)]
fn from (variant : CTL2_REFSRC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL2_REFSRC_A { type Ux = u8 ; } impl CTL2_REFSRC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_REFSRC_A { match self . bits { 0 => CTL2_REFSRC_A :: CTL2_REFSRC_OFF , 1 => CTL2_REFSRC_A :: CTL2_REFSRC_VDDA_DAC , 2 => CTL2_REFSRC_A :: CTL2_REFSRC_VREF_DAC , 3 => CTL2_REFSRC_A :: CTL2_REFSRC_VREF , _ => unreachable ! () , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_ctl2_refsrc_off (& self) -> bool { * self == CTL2_REFSRC_A :: CTL2_REFSRC_OFF } # [doc = "VDDA_DAC"]
# [inline (always)]
pub fn is_ctl2_refsrc_vdda_dac (& self) -> bool { * self == CTL2_REFSRC_A :: CTL2_REFSRC_VDDA_DAC } # [doc = "VREF_DAC"]
# [inline (always)]
pub fn is_ctl2_refsrc_vref_dac (& self) -> bool { * self == CTL2_REFSRC_A :: CTL2_REFSRC_VREF_DAC } # [doc = "VREF"]
# [inline (always)]
pub fn is_ctl2_refsrc_vref (& self) -> bool { * self == CTL2_REFSRC_A :: CTL2_REFSRC_VREF } } # [doc = "Field `CTL2_REFSRC` writer - These bits select the reference source for the comparator."]
pub type CTL2_REFSRC_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL2_REFSRC_A > ; impl < 'a , REG , const O : u8 > CTL2_REFSRC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"]
# [inline (always)]
pub fn ctl2_refsrc_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFSRC_A :: CTL2_REFSRC_OFF) } # [doc = "VDDA_DAC"]
# [inline (always)]
pub fn ctl2_refsrc_vdda_dac (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFSRC_A :: CTL2_REFSRC_VDDA_DAC) } # [doc = "VREF_DAC"]
# [inline (always)]
pub fn ctl2_refsrc_vref_dac (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFSRC_A :: CTL2_REFSRC_VREF_DAC) } # [doc = "VREF"]
# [inline (always)]
pub fn ctl2_refsrc_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFSRC_A :: CTL2_REFSRC_VREF) } } # [doc = "Field `CTL2_REFSEL` reader - This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator."]
pub type CTL2_REFSEL_R = crate :: BitReader < CTL2_REFSEL_A > ; # [doc = "This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_REFSEL_A { # [doc = "0: POSITIVE"]
CTL2_REFSEL_POSITIVE = 0 , # [doc = "1: NEGATIVE"]
CTL2_REFSEL_NEGATIVE = 1 , } impl From < CTL2_REFSEL_A > for bool { # [inline (always)]
fn from (variant : CTL2_REFSEL_A) -> Self { variant as u8 != 0 } } impl CTL2_REFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_REFSEL_A { match self . bits { false => CTL2_REFSEL_A :: CTL2_REFSEL_POSITIVE , true => CTL2_REFSEL_A :: CTL2_REFSEL_NEGATIVE , } } # [doc = "POSITIVE"]
# [inline (always)]
pub fn is_ctl2_refsel_positive (& self) -> bool { * self == CTL2_REFSEL_A :: CTL2_REFSEL_POSITIVE } # [doc = "NEGATIVE"]
# [inline (always)]
pub fn is_ctl2_refsel_negative (& self) -> bool { * self == CTL2_REFSEL_A :: CTL2_REFSEL_NEGATIVE } } # [doc = "Field `CTL2_REFSEL` writer - This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator."]
pub type CTL2_REFSEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_REFSEL_A > ; impl < 'a , REG , const O : u8 > CTL2_REFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "POSITIVE"]
# [inline (always)]
pub fn ctl2_refsel_positive (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFSEL_A :: CTL2_REFSEL_POSITIVE) } # [doc = "NEGATIVE"]
# [inline (always)]
pub fn ctl2_refsel_negative (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_REFSEL_A :: CTL2_REFSEL_NEGATIVE) } } # [doc = "Field `CTL2_BLANKSRC` reader - These bits select the blanking source for the comparator."]
pub type CTL2_BLANKSRC_R = crate :: FieldReader < CTL2_BLANKSRC_A > ; # [doc = "These bits select the blanking source for the comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL2_BLANKSRC_A { # [doc = "0: DISABLE"]
CTL2_BLANKSRC_DISABLE = 0 , # [doc = "1: BLANKSRC1"]
CTL2_BLANKSRC_BLANKSRC1 = 1 , # [doc = "2: BLANKSRC2"]
CTL2_BLANKSRC_BLANKSRC2 = 2 , # [doc = "3: BLANKSRC3"]
CTL2_BLANKSRC_BLANKSRC3 = 3 , # [doc = "4: BLANKSRC4"]
CTL2_BLANKSRC_BLANKSRC4 = 4 , # [doc = "5: BLANKSRC5"]
CTL2_BLANKSRC_BLANKSRC5 = 5 , # [doc = "6: BLANKSRC6"]
CTL2_BLANKSRC_BLANKSRC6 = 6 , } impl From < CTL2_BLANKSRC_A > for u8 { # [inline (always)]
fn from (variant : CTL2_BLANKSRC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL2_BLANKSRC_A { type Ux = u8 ; } impl CTL2_BLANKSRC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL2_BLANKSRC_A > { match self . bits { 0 => Some (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_DISABLE) , 1 => Some (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC1) , 2 => Some (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC2) , 3 => Some (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC3) , 4 => Some (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC4) , 5 => Some (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC5) , 6 => Some (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC6) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl2_blanksrc_disable (& self) -> bool { * self == CTL2_BLANKSRC_A :: CTL2_BLANKSRC_DISABLE } # [doc = "BLANKSRC1"]
# [inline (always)]
pub fn is_ctl2_blanksrc_blanksrc1 (& self) -> bool { * self == CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC1 } # [doc = "BLANKSRC2"]
# [inline (always)]
pub fn is_ctl2_blanksrc_blanksrc2 (& self) -> bool { * self == CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC2 } # [doc = "BLANKSRC3"]
# [inline (always)]
pub fn is_ctl2_blanksrc_blanksrc3 (& self) -> bool { * self == CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC3 } # [doc = "BLANKSRC4"]
# [inline (always)]
pub fn is_ctl2_blanksrc_blanksrc4 (& self) -> bool { * self == CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC4 } # [doc = "BLANKSRC5"]
# [inline (always)]
pub fn is_ctl2_blanksrc_blanksrc5 (& self) -> bool { * self == CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC5 } # [doc = "BLANKSRC6"]
# [inline (always)]
pub fn is_ctl2_blanksrc_blanksrc6 (& self) -> bool { * self == CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC6 } } # [doc = "Field `CTL2_BLANKSRC` writer - These bits select the blanking source for the comparator."]
pub type CTL2_BLANKSRC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTL2_BLANKSRC_A > ; impl < 'a , REG , const O : u8 > CTL2_BLANKSRC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl2_blanksrc_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_DISABLE) } # [doc = "BLANKSRC1"]
# [inline (always)]
pub fn ctl2_blanksrc_blanksrc1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC1) } # [doc = "BLANKSRC2"]
# [inline (always)]
pub fn ctl2_blanksrc_blanksrc2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC2) } # [doc = "BLANKSRC3"]
# [inline (always)]
pub fn ctl2_blanksrc_blanksrc3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC3) } # [doc = "BLANKSRC4"]
# [inline (always)]
pub fn ctl2_blanksrc_blanksrc4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC4) } # [doc = "BLANKSRC5"]
# [inline (always)]
pub fn ctl2_blanksrc_blanksrc5 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC5) } # [doc = "BLANKSRC6"]
# [inline (always)]
pub fn ctl2_blanksrc_blanksrc6 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_BLANKSRC_A :: CTL2_BLANKSRC_BLANKSRC6) } } # [doc = "Field `CTL2_DACCTL` reader - This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1."]
pub type CTL2_DACCTL_R = crate :: BitReader < CTL2_DACCTL_A > ; # [doc = "This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_DACCTL_A { # [doc = "0: COMPOUT_SEL"]
CTL2_DACCTL_COMPOUT_SEL = 0 , # [doc = "1: DACSW_SEL"]
CTL2_DACCTL_DACSW_SEL = 1 , } impl From < CTL2_DACCTL_A > for bool { # [inline (always)]
fn from (variant : CTL2_DACCTL_A) -> Self { variant as u8 != 0 } } impl CTL2_DACCTL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_DACCTL_A { match self . bits { false => CTL2_DACCTL_A :: CTL2_DACCTL_COMPOUT_SEL , true => CTL2_DACCTL_A :: CTL2_DACCTL_DACSW_SEL , } } # [doc = "COMPOUT_SEL"]
# [inline (always)]
pub fn is_ctl2_dacctl_compout_sel (& self) -> bool { * self == CTL2_DACCTL_A :: CTL2_DACCTL_COMPOUT_SEL } # [doc = "DACSW_SEL"]
# [inline (always)]
pub fn is_ctl2_dacctl_dacsw_sel (& self) -> bool { * self == CTL2_DACCTL_A :: CTL2_DACCTL_DACSW_SEL } } # [doc = "Field `CTL2_DACCTL` writer - This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1."]
pub type CTL2_DACCTL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_DACCTL_A > ; impl < 'a , REG , const O : u8 > CTL2_DACCTL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPOUT_SEL"]
# [inline (always)]
pub fn ctl2_dacctl_compout_sel (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DACCTL_A :: CTL2_DACCTL_COMPOUT_SEL) } # [doc = "DACSW_SEL"]
# [inline (always)]
pub fn ctl2_dacctl_dacsw_sel (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DACCTL_A :: CTL2_DACCTL_DACSW_SEL) } } # [doc = "Field `CTL2_DACSW` reader - This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1."]
pub type CTL2_DACSW_R = crate :: BitReader < CTL2_DACSW_A > ; # [doc = "This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_DACSW_A { # [doc = "0: DACCODE0_SEL"]
CTL2_DACSW_DACCODE0_SEL = 0 , # [doc = "1: DACCODE1_SEL"]
CTL2_DACSW_DACCODE1_SEL = 1 , } impl From < CTL2_DACSW_A > for bool { # [inline (always)]
fn from (variant : CTL2_DACSW_A) -> Self { variant as u8 != 0 } } impl CTL2_DACSW_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_DACSW_A { match self . bits { false => CTL2_DACSW_A :: CTL2_DACSW_DACCODE0_SEL , true => CTL2_DACSW_A :: CTL2_DACSW_DACCODE1_SEL , } } # [doc = "DACCODE0_SEL"]
# [inline (always)]
pub fn is_ctl2_dacsw_daccode0_sel (& self) -> bool { * self == CTL2_DACSW_A :: CTL2_DACSW_DACCODE0_SEL } # [doc = "DACCODE1_SEL"]
# [inline (always)]
pub fn is_ctl2_dacsw_daccode1_sel (& self) -> bool { * self == CTL2_DACSW_A :: CTL2_DACSW_DACCODE1_SEL } } # [doc = "Field `CTL2_DACSW` writer - This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1."]
pub type CTL2_DACSW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_DACSW_A > ; impl < 'a , REG , const O : u8 > CTL2_DACSW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DACCODE0_SEL"]
# [inline (always)]
pub fn ctl2_dacsw_daccode0_sel (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DACSW_A :: CTL2_DACSW_DACCODE0_SEL) } # [doc = "DACCODE1_SEL"]
# [inline (always)]
pub fn ctl2_dacsw_daccode1_sel (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DACSW_A :: CTL2_DACSW_DACCODE1_SEL) } } # [doc = "Field `CTL2_SAMPMODE` reader - Enable sampled mode of comparator."]
pub type CTL2_SAMPMODE_R = crate :: BitReader < CTL2_SAMPMODE_A > ; # [doc = "Enable sampled mode of comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_SAMPMODE_A { # [doc = "0: DISABLE"]
CTL2_SAMPMODE_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL2_SAMPMODE_ENABLE = 1 , } impl From < CTL2_SAMPMODE_A > for bool { # [inline (always)]
fn from (variant : CTL2_SAMPMODE_A) -> Self { variant as u8 != 0 } } impl CTL2_SAMPMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_SAMPMODE_A { match self . bits { false => CTL2_SAMPMODE_A :: CTL2_SAMPMODE_DISABLE , true => CTL2_SAMPMODE_A :: CTL2_SAMPMODE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl2_sampmode_disable (& self) -> bool { * self == CTL2_SAMPMODE_A :: CTL2_SAMPMODE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl2_sampmode_enable (& self) -> bool { * self == CTL2_SAMPMODE_A :: CTL2_SAMPMODE_ENABLE } } # [doc = "Field `CTL2_SAMPMODE` writer - Enable sampled mode of comparator."]
pub type CTL2_SAMPMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_SAMPMODE_A > ; impl < 'a , REG , const O : u8 > CTL2_SAMPMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl2_sampmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_SAMPMODE_A :: CTL2_SAMPMODE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl2_sampmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_SAMPMODE_A :: CTL2_SAMPMODE_ENABLE) } } impl R { # [doc = "Bit 0 - This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL &amp;gt; 0."]
# [inline (always)]
pub fn ctl2_refmode (& self) -> CTL2_REFMODE_R { CTL2_REFMODE_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 3:4 - These bits select the reference source for the comparator."]
# [inline (always)]
pub fn ctl2_refsrc (& self) -> CTL2_REFSRC_R { CTL2_REFSRC_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bit 7 - This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator."]
# [inline (always)]
pub fn ctl2_refsel (& self) -> CTL2_REFSEL_R { CTL2_REFSEL_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - These bits select the blanking source for the comparator."]
# [inline (always)]
pub fn ctl2_blanksrc (& self) -> CTL2_BLANKSRC_R { CTL2_BLANKSRC_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 16 - This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1."]
# [inline (always)]
pub fn ctl2_dacctl (& self) -> CTL2_DACCTL_R { CTL2_DACCTL_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1."]
# [inline (always)]
pub fn ctl2_dacsw (& self) -> CTL2_DACSW_R { CTL2_DACSW_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 24 - Enable sampled mode of comparator."]
# [inline (always)]
pub fn ctl2_sampmode (& self) -> CTL2_SAMPMODE_R { CTL2_SAMPMODE_R :: new (((self . bits >> 24) & 1) != 0) } } impl W { # [doc = "Bit 0 - This bit requests ULP_REF bandgap operation in static mode or sampled mode. The local reference buffer and 8-bit DAC inside comparator module are also configured accordingly. Static mode operation offers higher accuracy but consumes higher current. Sampled mode operation consumes lower current but with relaxed reference voltage accuracy. Comparator requests for reference voltage from ULP_REF only when REFLVL &amp;gt; 0."]
# [inline (always)]
# [must_use]
pub fn ctl2_refmode (& mut self) -> CTL2_REFMODE_W < CTL2_SPEC , 0 > { CTL2_REFMODE_W :: new (self) } # [doc = "Bits 3:4 - These bits select the reference source for the comparator."]
# [inline (always)]
# [must_use]
pub fn ctl2_refsrc (& mut self) -> CTL2_REFSRC_W < CTL2_SPEC , 3 > { CTL2_REFSRC_W :: new (self) } # [doc = "Bit 7 - This bit selects if the selected reference voltage is applied to positive or negative terminal of the comparator."]
# [inline (always)]
# [must_use]
pub fn ctl2_refsel (& mut self) -> CTL2_REFSEL_W < CTL2_SPEC , 7 > { CTL2_REFSEL_W :: new (self) } # [doc = "Bits 8:10 - These bits select the blanking source for the comparator."]
# [inline (always)]
# [must_use]
pub fn ctl2_blanksrc (& mut self) -> CTL2_BLANKSRC_W < CTL2_SPEC , 8 > { CTL2_BLANKSRC_W :: new (self) } # [doc = "Bit 16 - This bit determines if the comparator output or DACSW bit controls the selection between DACCODE0 and DACCODE1."]
# [inline (always)]
# [must_use]
pub fn ctl2_dacctl (& mut self) -> CTL2_DACCTL_W < CTL2_SPEC , 16 > { CTL2_DACCTL_W :: new (self) } # [doc = "Bit 17 - This bit selects between DACCODE0 and DACCODE1 to 8-bit DAC when DACCTL bit is 1."]
# [inline (always)]
# [must_use]
pub fn ctl2_dacsw (& mut self) -> CTL2_DACSW_W < CTL2_SPEC , 17 > { CTL2_DACSW_W :: new (self) } # [doc = "Bit 24 - Enable sampled mode of comparator."]
# [inline (always)]
# [must_use]
pub fn ctl2_sampmode (& mut self) -> CTL2_SAMPMODE_W < CTL2_SPEC , 24 > { CTL2_SAMPMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL2_SPEC ; impl crate :: RegisterSpec for CTL2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl2::R`](R) reader structure"]
impl crate :: Readable for CTL2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl2::W`](W) writer structure"]
impl crate :: Writable for CTL2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL2 to value 0"]
impl crate :: Resettable for CTL2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL3 (rw) register accessor: Control 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl3`]
module"]
pub type CTL3 = crate :: Reg < ctl3 :: CTL3_SPEC > ; # [doc = "Control 3"]
pub mod ctl3 { # [doc = "Register `CTL3` reader"]
pub type R = crate :: R < CTL3_SPEC > ; # [doc = "Register `CTL3` writer"]
pub type W = crate :: W < CTL3_SPEC > ; # [doc = "Field `CTL3_DACCODE0` reader - This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
pub type CTL3_DACCODE0_R = crate :: FieldReader ; # [doc = "Field `CTL3_DACCODE0` writer - This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
pub type CTL3_DACCODE0_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `CTL3_DACCODE1` reader - This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
pub type CTL3_DACCODE1_R = crate :: FieldReader ; # [doc = "Field `CTL3_DACCODE1` writer - This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
pub type CTL3_DACCODE1_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
# [inline (always)]
pub fn ctl3_daccode0 (& self) -> CTL3_DACCODE0_R { CTL3_DACCODE0_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 16:23 - This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
# [inline (always)]
pub fn ctl3_daccode1 (& self) -> CTL3_DACCODE1_R { CTL3_DACCODE1_R :: new (((self . bits >> 16) & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - This is the first 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
# [inline (always)]
# [must_use]
pub fn ctl3_daccode0 (& mut self) -> CTL3_DACCODE0_W < CTL3_SPEC , 0 > { CTL3_DACCODE0_W :: new (self) } # [doc = "Bits 16:23 - This is the second 8-bit DAC code. When the DAC code is 0x0 the DAC output will be 0 V. When the DAC code is 0xFF the DAC output will be selected reference voltage x 255/256."]
# [inline (always)]
# [must_use]
pub fn ctl3_daccode1 (& mut self) -> CTL3_DACCODE1_W < CTL3_SPEC , 16 > { CTL3_DACCODE1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL3_SPEC ; impl crate :: RegisterSpec for CTL3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl3::R`](R) reader structure"]
impl crate :: Readable for CTL3_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl3::W`](W) writer structure"]
impl crate :: Writable for CTL3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL3 to value 0"]
impl crate :: Resettable for CTL3_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_OUT` reader - This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output."]
pub type STAT_OUT_R = crate :: BitReader < STAT_OUT_A > ; # [doc = "This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_OUT_A { # [doc = "0: LOW"]
STAT_OUT_LOW = 0 , # [doc = "1: HIGH"]
STAT_OUT_HIGH = 1 , } impl From < STAT_OUT_A > for bool { # [inline (always)]
fn from (variant : STAT_OUT_A) -> Self { variant as u8 != 0 } } impl STAT_OUT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_OUT_A { match self . bits { false => STAT_OUT_A :: STAT_OUT_LOW , true => STAT_OUT_A :: STAT_OUT_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_stat_out_low (& self) -> bool { * self == STAT_OUT_A :: STAT_OUT_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_stat_out_high (& self) -> bool { * self == STAT_OUT_A :: STAT_OUT_HIGH } } impl R { # [doc = "Bit 0 - This bit reflects the value of the comparator output. Writing to this bit has no effect on the comparator output."]
# [inline (always)]
pub fn stat_out (& self) -> STAT_OUT_R { STAT_OUT_R :: new ((self . bits & 1) != 0) } } # [doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "mem_map"]
pub struct SYSCTL { _marker : PhantomData < * const () > } unsafe impl Send for SYSCTL { } impl SYSCTL { # [doc = r"Pointer to the register block"]
pub const PTR : * const sysctl :: RegisterBlock = 0x400a_f000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const sysctl :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for SYSCTL { type Target = sysctl :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for SYSCTL { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("SYSCTL") . finish () } } # [doc = "mem_map"]
pub mod sysctl { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x1020]
, # [doc = "0x1020 - SYSCTL interrupt index"]
pub iidx : IIDX , _reserved1 : [u8 ; 0x04]
, # [doc = "0x1028 - SYSCTL interrupt mask"]
pub imask : IMASK , _reserved2 : [u8 ; 0x04]
, # [doc = "0x1030 - SYSCTL raw interrupt status"]
pub ris : RIS , _reserved3 : [u8 ; 0x04]
, # [doc = "0x1038 - SYSCTL masked interrupt status"]
pub mis : MIS , _reserved4 : [u8 ; 0x04]
, # [doc = "0x1040 - SYSCTL interrupt set"]
pub iset : ISET , _reserved5 : [u8 ; 0x04]
, # [doc = "0x1048 - SYSCTL interrupt clear"]
pub iclr : ICLR , _reserved6 : [u8 ; 0x04]
, # [doc = "0x1050 - NMI interrupt index"]
pub nmiiidx : NMIIIDX , _reserved7 : [u8 ; 0x0c]
, # [doc = "0x1060 - NMI raw interrupt status"]
pub nmiris : NMIRIS , _reserved8 : [u8 ; 0x0c]
, # [doc = "0x1070 - NMI interrupt set"]
pub nmiiset : NMIISET , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1078 - NMI interrupt clear"]
pub nmiiclr : NMIICLR , _reserved10 : [u8 ; 0x84]
, # [doc = "0x1100 - SYSOSC configuration"]
pub sysosccfg : SYSOSCCFG , # [doc = "0x1104 - Main clock (MCLK) configuration"]
pub mclkcfg : MCLKCFG , _reserved12 : [u8 ; 0x30]
, # [doc = "0x1138 - General clock configuration"]
pub genclkcfg : GENCLKCFG , # [doc = "0x113c - General clock enable control"]
pub genclken : GENCLKEN , # [doc = "0x1140 - Power mode configuration"]
pub pmodecfg : PMODECFG , _reserved15 : [u8 ; 0x0c]
, # [doc = "0x1150 - Frequency clock counter (FCC) count"]
pub fcc : FCC , _reserved16 : [u8 ; 0x1c]
, # [doc = "0x1170 - SYSOSC user-specified trim"]
pub sysosctrimuser : SYSOSCTRIMUSER , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1178 - SRAM Write Boundary"]
pub sramboundary : SRAMBOUNDARY , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1180 - System configuration"]
pub systemcfg : SYSTEMCFG , _reserved19 : [u8 ; 0x7c]
, # [doc = "0x1200 - SYSCTL register write lockout"]
pub writelock : WRITELOCK , _reserved20 : [u8 ; 0x1c]
, # [doc = "0x1220 - Reset cause"]
pub rstcause : RSTCAUSE , _reserved21 : [u8 ; 0xdc]
, # [doc = "0x1300 - Reset level for application-triggered reset command"]
pub resetlevel : RESETLEVEL , # [doc = "0x1304 - Execute an application-triggered reset command"]
pub resetcmd : RESETCMD , # [doc = "0x1308 - BOR threshold selection"]
pub borthreshold : BORTHRESHOLD , # [doc = "0x130c - Set the BOR threshold"]
pub borclrcmd : BORCLRCMD , # [doc = "0x1310 - SYSOSC frequency correction loop (FCL) ROSC enable"]
pub sysoscfclctl : SYSOSCFCLCTL , _reserved26 : [u8 ; 0x08]
, # [doc = "0x131c - SHUTDOWN IO release control"]
pub shdniorel : SHDNIOREL , # [doc = "0x1320 - Disable the reset function of the NRST pin"]
pub exrstpin : EXRSTPIN , _reserved28 : [u8 ; 0x04]
, # [doc = "0x1328 - Disable the SWD function on the SWD pins"]
pub swdcfg : SWDCFG , # [doc = "0x132c - Frequency clock counter start capture"]
pub fcccmd : FCCCMD , _reserved30 : [u8 ; 0x50]
, # [doc = "0x1380 - GPAMP control"]
pub pmuopamp : PMUOPAMP , _reserved31 : [u8 ; 0x7c]
, # [doc = "0x1400 - Shutdown storage memory (byte 0)"]
pub shutdnstore0 : SHUTDNSTORE0 , # [doc = "0x1404 - Shutdown storage memory (byte 1)"]
pub shutdnstore1 : SHUTDNSTORE1 , # [doc = "0x1408 - Shutdown storage memory (byte 2)"]
pub shutdnstore2 : SHUTDNSTORE2 , # [doc = "0x140c - Shutdown storage memory (byte 3)"]
pub shutdnstore3 : SHUTDNSTORE3 , } # [doc = "IIDX (r) register accessor: SYSCTL interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "SYSCTL interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers."]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: LFOSCGOOD"]
IIDX_STAT_LFOSCGOOD = 1 , # [doc = "2: ANACLKERR"]
IIDX_STAT_ANACLKERR = 2 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_LFOSCGOOD) , 2 => Some (IIDX_STAT_A :: IIDX_STAT_ANACLKERR) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "LFOSCGOOD"]
# [inline (always)]
pub fn is_iidx_stat_lfoscgood (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_LFOSCGOOD } # [doc = "ANACLKERR"]
# [inline (always)]
pub fn is_iidx_stat_anaclkerr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_ANACLKERR } } impl R { # [doc = "Bits 0:1 - The SYSCTL interrupt index (IIDX) register generates a value corresponding to the highest priority pending interrupt source. This value may be used as an address offset for fast, deterministic handling in the interrupt service routine. A read of the IIDX register will clear the corresponding interrupt status in the RIS and MIS registers."]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 3) as u8) } } # [doc = "SYSCTL interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: SYSCTL interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "SYSCTL interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_LFOSCGOOD` reader - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."]
pub type IMASK_LFOSCGOOD_R = crate :: BitReader < IMASK_LFOSCGOOD_A > ; # [doc = "Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_LFOSCGOOD_A { # [doc = "0: DISABLE"]
IMASK_LFOSCGOOD_DISABLE = 0 , # [doc = "1: ENABLE"]
IMASK_LFOSCGOOD_ENABLE = 1 , } impl From < IMASK_LFOSCGOOD_A > for bool { # [inline (always)]
fn from (variant : IMASK_LFOSCGOOD_A) -> Self { variant as u8 != 0 } } impl IMASK_LFOSCGOOD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_LFOSCGOOD_A { match self . bits { false => IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE , true => IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_imask_lfoscgood_disable (& self) -> bool { * self == IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_imask_lfoscgood_enable (& self) -> bool { * self == IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE } } # [doc = "Field `IMASK_LFOSCGOOD` writer - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."]
pub type IMASK_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_LFOSCGOOD_A > ; impl < 'a , REG , const O : u8 > IMASK_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn imask_lfoscgood_disable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn imask_lfoscgood_enable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_LFOSCGOOD_A :: IMASK_LFOSCGOOD_ENABLE) } } # [doc = "Field `IMASK_ANACLKERR` reader - Analog Clocking Consistency Error"]
pub type IMASK_ANACLKERR_R = crate :: BitReader < IMASK_ANACLKERR_A > ; # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_ANACLKERR_A { # [doc = "0: DISABLE"]
IMASK_ANACLKERR_DISABLE = 0 , # [doc = "1: ENABLE"]
IMASK_ANACLKERR_ENABLE = 1 , } impl From < IMASK_ANACLKERR_A > for bool { # [inline (always)]
fn from (variant : IMASK_ANACLKERR_A) -> Self { variant as u8 != 0 } } impl IMASK_ANACLKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_ANACLKERR_A { match self . bits { false => IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE , true => IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_imask_anaclkerr_disable (& self) -> bool { * self == IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_imask_anaclkerr_enable (& self) -> bool { * self == IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE } } # [doc = "Field `IMASK_ANACLKERR` writer - Analog Clocking Consistency Error"]
pub type IMASK_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_ANACLKERR_A > ; impl < 'a , REG , const O : u8 > IMASK_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn imask_anaclkerr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ANACLKERR_A :: IMASK_ANACLKERR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn imask_anaclkerr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_ANACLKERR_A :: IMASK_ANACLKERR_ENABLE) } } impl R { # [doc = "Bit 0 - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."]
# [inline (always)]
pub fn imask_lfoscgood (& self) -> IMASK_LFOSCGOOD_R { IMASK_LFOSCGOOD_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Analog Clocking Consistency Error"]
# [inline (always)]
pub fn imask_anaclkerr (& self) -> IMASK_ANACLKERR_R { IMASK_ANACLKERR_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable or disable the LFOSCGOOD interrupt. LFOSCGOOD indicates that the LFOSC has started successfully."]
# [inline (always)]
# [must_use]
pub fn imask_lfoscgood (& mut self) -> IMASK_LFOSCGOOD_W < IMASK_SPEC , 0 > { IMASK_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"]
# [inline (always)]
# [must_use]
pub fn imask_anaclkerr (& mut self) -> IMASK_ANACLKERR_W < IMASK_SPEC , 1 > { IMASK_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: SYSCTL raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "SYSCTL raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_LFOSCGOOD` reader - Raw status of the LFOSCGOOD interrupt."]
pub type RIS_LFOSCGOOD_R = crate :: BitReader < RIS_LFOSCGOOD_A > ; # [doc = "Raw status of the LFOSCGOOD interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_LFOSCGOOD_A { # [doc = "0: FALSE"]
RIS_LFOSCGOOD_FALSE = 0 , # [doc = "1: TRUE"]
RIS_LFOSCGOOD_TRUE = 1 , } impl From < RIS_LFOSCGOOD_A > for bool { # [inline (always)]
fn from (variant : RIS_LFOSCGOOD_A) -> Self { variant as u8 != 0 } } impl RIS_LFOSCGOOD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_LFOSCGOOD_A { match self . bits { false => RIS_LFOSCGOOD_A :: RIS_LFOSCGOOD_FALSE , true => RIS_LFOSCGOOD_A :: RIS_LFOSCGOOD_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_ris_lfoscgood_false (& self) -> bool { * self == RIS_LFOSCGOOD_A :: RIS_LFOSCGOOD_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_ris_lfoscgood_true (& self) -> bool { * self == RIS_LFOSCGOOD_A :: RIS_LFOSCGOOD_TRUE } } # [doc = "Field `RIS_ANACLKERR` reader - Analog Clocking Consistency Error"]
pub type RIS_ANACLKERR_R = crate :: BitReader < RIS_ANACLKERR_A > ; # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_ANACLKERR_A { # [doc = "0: FALSE"]
RIS_ANACLKERR_FALSE = 0 , # [doc = "1: TRUE"]
RIS_ANACLKERR_TRUE = 1 , } impl From < RIS_ANACLKERR_A > for bool { # [inline (always)]
fn from (variant : RIS_ANACLKERR_A) -> Self { variant as u8 != 0 } } impl RIS_ANACLKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_ANACLKERR_A { match self . bits { false => RIS_ANACLKERR_A :: RIS_ANACLKERR_FALSE , true => RIS_ANACLKERR_A :: RIS_ANACLKERR_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_ris_anaclkerr_false (& self) -> bool { * self == RIS_ANACLKERR_A :: RIS_ANACLKERR_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_ris_anaclkerr_true (& self) -> bool { * self == RIS_ANACLKERR_A :: RIS_ANACLKERR_TRUE } } impl R { # [doc = "Bit 0 - Raw status of the LFOSCGOOD interrupt."]
# [inline (always)]
pub fn ris_lfoscgood (& self) -> RIS_LFOSCGOOD_R { RIS_LFOSCGOOD_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Analog Clocking Consistency Error"]
# [inline (always)]
pub fn ris_anaclkerr (& self) -> RIS_ANACLKERR_R { RIS_ANACLKERR_R :: new (((self . bits >> 1) & 1) != 0) } } # [doc = "SYSCTL raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: SYSCTL masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "SYSCTL masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_LFOSCGOOD` reader - Masked status of the LFOSCGOOD interrupt."]
pub type MIS_LFOSCGOOD_R = crate :: BitReader < MIS_LFOSCGOOD_A > ; # [doc = "Masked status of the LFOSCGOOD interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_LFOSCGOOD_A { # [doc = "0: FALSE"]
MIS_LFOSCGOOD_FALSE = 0 , # [doc = "1: TRUE"]
MIS_LFOSCGOOD_TRUE = 1 , } impl From < MIS_LFOSCGOOD_A > for bool { # [inline (always)]
fn from (variant : MIS_LFOSCGOOD_A) -> Self { variant as u8 != 0 } } impl MIS_LFOSCGOOD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_LFOSCGOOD_A { match self . bits { false => MIS_LFOSCGOOD_A :: MIS_LFOSCGOOD_FALSE , true => MIS_LFOSCGOOD_A :: MIS_LFOSCGOOD_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_mis_lfoscgood_false (& self) -> bool { * self == MIS_LFOSCGOOD_A :: MIS_LFOSCGOOD_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_mis_lfoscgood_true (& self) -> bool { * self == MIS_LFOSCGOOD_A :: MIS_LFOSCGOOD_TRUE } } # [doc = "Field `MIS_ANACLKERR` reader - Analog Clocking Consistency Error"]
pub type MIS_ANACLKERR_R = crate :: BitReader < MIS_ANACLKERR_A > ; # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_ANACLKERR_A { # [doc = "0: FALSE"]
MIS_ANACLKERR_FALSE = 0 , # [doc = "1: TRUE"]
MIS_ANACLKERR_TRUE = 1 , } impl From < MIS_ANACLKERR_A > for bool { # [inline (always)]
fn from (variant : MIS_ANACLKERR_A) -> Self { variant as u8 != 0 } } impl MIS_ANACLKERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_ANACLKERR_A { match self . bits { false => MIS_ANACLKERR_A :: MIS_ANACLKERR_FALSE , true => MIS_ANACLKERR_A :: MIS_ANACLKERR_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_mis_anaclkerr_false (& self) -> bool { * self == MIS_ANACLKERR_A :: MIS_ANACLKERR_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_mis_anaclkerr_true (& self) -> bool { * self == MIS_ANACLKERR_A :: MIS_ANACLKERR_TRUE } } impl R { # [doc = "Bit 0 - Masked status of the LFOSCGOOD interrupt."]
# [inline (always)]
pub fn mis_lfoscgood (& self) -> MIS_LFOSCGOOD_R { MIS_LFOSCGOOD_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Analog Clocking Consistency Error"]
# [inline (always)]
pub fn mis_anaclkerr (& self) -> MIS_ANACLKERR_R { MIS_ANACLKERR_R :: new (((self . bits >> 1) & 1) != 0) } } # [doc = "SYSCTL masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: SYSCTL interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "SYSCTL interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Set the LFOSCGOOD interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_LFOSCGOOD_AW { # [doc = "0: NO_EFFECT"]
ISET_LFOSCGOOD_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_LFOSCGOOD_SET = 1 , } impl From < ISET_LFOSCGOOD_AW > for bool { # [inline (always)]
fn from (variant : ISET_LFOSCGOOD_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_LFOSCGOOD` writer - Set the LFOSCGOOD interrupt."]
pub type ISET_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_LFOSCGOOD_AW > ; impl < 'a , REG , const O : u8 > ISET_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_lfoscgood_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_LFOSCGOOD_AW :: ISET_LFOSCGOOD_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_lfoscgood_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_LFOSCGOOD_AW :: ISET_LFOSCGOOD_SET) } } # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_ANACLKERR_AW { # [doc = "0: NO_EFFECT"]
ISET_ANACLKERR_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_ANACLKERR_SET = 1 , } impl From < ISET_ANACLKERR_AW > for bool { # [inline (always)]
fn from (variant : ISET_ANACLKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_ANACLKERR` writer - Analog Clocking Consistency Error"]
pub type ISET_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_ANACLKERR_AW > ; impl < 'a , REG , const O : u8 > ISET_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_anaclkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ANACLKERR_AW :: ISET_ANACLKERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_anaclkerr_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_ANACLKERR_AW :: ISET_ANACLKERR_SET) } } impl W { # [doc = "Bit 0 - Set the LFOSCGOOD interrupt."]
# [inline (always)]
# [must_use]
pub fn iset_lfoscgood (& mut self) -> ISET_LFOSCGOOD_W < ISET_SPEC , 0 > { ISET_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"]
# [inline (always)]
# [must_use]
pub fn iset_anaclkerr (& mut self) -> ISET_ANACLKERR_W < ISET_SPEC , 1 > { ISET_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: SYSCTL interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "SYSCTL interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Clear the LFOSCGOOD interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_LFOSCGOOD_AW { # [doc = "0: NO_EFFECT"]
ICLR_LFOSCGOOD_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_LFOSCGOOD_CLR = 1 , } impl From < ICLR_LFOSCGOOD_AW > for bool { # [inline (always)]
fn from (variant : ICLR_LFOSCGOOD_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_LFOSCGOOD` writer - Clear the LFOSCGOOD interrupt."]
pub type ICLR_LFOSCGOOD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_LFOSCGOOD_AW > ; impl < 'a , REG , const O : u8 > ICLR_LFOSCGOOD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_lfoscgood_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_LFOSCGOOD_AW :: ICLR_LFOSCGOOD_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_lfoscgood_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_LFOSCGOOD_AW :: ICLR_LFOSCGOOD_CLR) } } # [doc = "Analog Clocking Consistency Error\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_ANACLKERR_AW { # [doc = "0: NO_EFFECT"]
ICLR_ANACLKERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_ANACLKERR_CLR = 1 , } impl From < ICLR_ANACLKERR_AW > for bool { # [inline (always)]
fn from (variant : ICLR_ANACLKERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_ANACLKERR` writer - Analog Clocking Consistency Error"]
pub type ICLR_ANACLKERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_ANACLKERR_AW > ; impl < 'a , REG , const O : u8 > ICLR_ANACLKERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_anaclkerr_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ANACLKERR_AW :: ICLR_ANACLKERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_anaclkerr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_ANACLKERR_AW :: ICLR_ANACLKERR_CLR) } } impl W { # [doc = "Bit 0 - Clear the LFOSCGOOD interrupt."]
# [inline (always)]
# [must_use]
pub fn iclr_lfoscgood (& mut self) -> ICLR_LFOSCGOOD_W < ICLR_SPEC , 0 > { ICLR_LFOSCGOOD_W :: new (self) } # [doc = "Bit 1 - Analog Clocking Consistency Error"]
# [inline (always)]
# [must_use]
pub fn iclr_anaclkerr (& mut self) -> ICLR_ANACLKERR_W < ICLR_SPEC , 1 > { ICLR_ANACLKERR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "NMIIIDX (r) register accessor: NMI interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmiiidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmiiidx`]
module"]
pub type NMIIIDX = crate :: Reg < nmiiidx :: NMIIIDX_SPEC > ; # [doc = "NMI interrupt index"]
pub mod nmiiidx { # [doc = "Register `NMIIIDX` reader"]
pub type R = crate :: R < NMIIIDX_SPEC > ; # [doc = "Field `NMIIIDX_STAT` reader - The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register."]
pub type NMIIIDX_STAT_R = crate :: FieldReader < NMIIIDX_STAT_A > ; # [doc = "The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum NMIIIDX_STAT_A { # [doc = "0: NO_INTR"]
NMIIIDX_STAT_NO_INTR = 0 , # [doc = "1: BORLVL"]
NMIIIDX_STAT_BORLVL = 1 , # [doc = "2: WWDT0"]
NMIIIDX_STAT_WWDT0 = 2 , } impl From < NMIIIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : NMIIIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for NMIIIDX_STAT_A { type Ux = u8 ; } impl NMIIIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < NMIIIDX_STAT_A > { match self . bits { 0 => Some (NMIIIDX_STAT_A :: NMIIIDX_STAT_NO_INTR) , 1 => Some (NMIIIDX_STAT_A :: NMIIIDX_STAT_BORLVL) , 2 => Some (NMIIIDX_STAT_A :: NMIIIDX_STAT_WWDT0) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_nmiiidx_stat_no_intr (& self) -> bool { * self == NMIIIDX_STAT_A :: NMIIIDX_STAT_NO_INTR } # [doc = "BORLVL"]
# [inline (always)]
pub fn is_nmiiidx_stat_borlvl (& self) -> bool { * self == NMIIIDX_STAT_A :: NMIIIDX_STAT_BORLVL } # [doc = "WWDT0"]
# [inline (always)]
pub fn is_nmiiidx_stat_wwdt0 (& self) -> bool { * self == NMIIIDX_STAT_A :: NMIIIDX_STAT_WWDT0 } } impl R { # [doc = "Bits 0:1 - The NMI interrupt index (NMIIIDX) register generates a value corresponding to the highest priority pending NMI source. This value may be used as an address offset for fast, deterministic handling in the NMI service routine. A read of the NMIIIDX register will clear the corresponding interrupt status in the NMIRIS register."]
# [inline (always)]
pub fn nmiiidx_stat (& self) -> NMIIIDX_STAT_R { NMIIIDX_STAT_R :: new ((self . bits & 3) as u8) } } # [doc = "NMI interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmiiidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NMIIIDX_SPEC ; impl crate :: RegisterSpec for NMIIIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`nmiiidx::R`](R) reader structure"]
impl crate :: Readable for NMIIIDX_SPEC { } # [doc = "`reset()` method sets NMIIIDX to value 0"]
impl crate :: Resettable for NMIIIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "NMIRIS (r) register accessor: NMI raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmiris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmiris`]
module"]
pub type NMIRIS = crate :: Reg < nmiris :: NMIRIS_SPEC > ; # [doc = "NMI raw interrupt status"]
pub mod nmiris { # [doc = "Register `NMIRIS` reader"]
pub type R = crate :: R < NMIRIS_SPEC > ; # [doc = "Field `NMIRIS_BORLVL` reader - Raw status of the BORLVL NMI"]
pub type NMIRIS_BORLVL_R = crate :: BitReader < NMIRIS_BORLVL_A > ; # [doc = "Raw status of the BORLVL NMI\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum NMIRIS_BORLVL_A { # [doc = "0: FALSE"]
NMIRIS_BORLVL_FALSE = 0 , # [doc = "1: TRUE"]
NMIRIS_BORLVL_TRUE = 1 , } impl From < NMIRIS_BORLVL_A > for bool { # [inline (always)]
fn from (variant : NMIRIS_BORLVL_A) -> Self { variant as u8 != 0 } } impl NMIRIS_BORLVL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> NMIRIS_BORLVL_A { match self . bits { false => NMIRIS_BORLVL_A :: NMIRIS_BORLVL_FALSE , true => NMIRIS_BORLVL_A :: NMIRIS_BORLVL_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_nmiris_borlvl_false (& self) -> bool { * self == NMIRIS_BORLVL_A :: NMIRIS_BORLVL_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_nmiris_borlvl_true (& self) -> bool { * self == NMIRIS_BORLVL_A :: NMIRIS_BORLVL_TRUE } } # [doc = "Field `NMIRIS_WWDT0` reader - Watch Dog 0 Fault"]
pub type NMIRIS_WWDT0_R = crate :: BitReader < NMIRIS_WWDT0_A > ; # [doc = "Watch Dog 0 Fault\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum NMIRIS_WWDT0_A { # [doc = "0: FALSE"]
NMIRIS_WWDT0_FALSE = 0 , # [doc = "1: TRUE"]
NMIRIS_WWDT0_TRUE = 1 , } impl From < NMIRIS_WWDT0_A > for bool { # [inline (always)]
fn from (variant : NMIRIS_WWDT0_A) -> Self { variant as u8 != 0 } } impl NMIRIS_WWDT0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> NMIRIS_WWDT0_A { match self . bits { false => NMIRIS_WWDT0_A :: NMIRIS_WWDT0_FALSE , true => NMIRIS_WWDT0_A :: NMIRIS_WWDT0_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_nmiris_wwdt0_false (& self) -> bool { * self == NMIRIS_WWDT0_A :: NMIRIS_WWDT0_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_nmiris_wwdt0_true (& self) -> bool { * self == NMIRIS_WWDT0_A :: NMIRIS_WWDT0_TRUE } } impl R { # [doc = "Bit 0 - Raw status of the BORLVL NMI"]
# [inline (always)]
pub fn nmiris_borlvl (& self) -> NMIRIS_BORLVL_R { NMIRIS_BORLVL_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Watch Dog 0 Fault"]
# [inline (always)]
pub fn nmiris_wwdt0 (& self) -> NMIRIS_WWDT0_R { NMIRIS_WWDT0_R :: new (((self . bits >> 1) & 1) != 0) } } # [doc = "NMI raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`nmiris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NMIRIS_SPEC ; impl crate :: RegisterSpec for NMIRIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`nmiris::R`](R) reader structure"]
impl crate :: Readable for NMIRIS_SPEC { } # [doc = "`reset()` method sets NMIRIS to value 0"]
impl crate :: Resettable for NMIRIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "NMIISET (w) register accessor: NMI interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmiiset`]
module"]
pub type NMIISET = crate :: Reg < nmiiset :: NMIISET_SPEC > ; # [doc = "NMI interrupt set"]
pub mod nmiiset { # [doc = "Register `NMIISET` writer"]
pub type W = crate :: W < NMIISET_SPEC > ; # [doc = "Set the BORLVL NMI\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum NMIISET_BORLVL_AW { # [doc = "0: NO_EFFECT"]
NMIISET_BORLVL_NO_EFFECT = 0 , # [doc = "1: SET"]
NMIISET_BORLVL_SET = 1 , } impl From < NMIISET_BORLVL_AW > for bool { # [inline (always)]
fn from (variant : NMIISET_BORLVL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIISET_BORLVL` writer - Set the BORLVL NMI"]
pub type NMIISET_BORLVL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIISET_BORLVL_AW > ; impl < 'a , REG , const O : u8 > NMIISET_BORLVL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn nmiiset_borlvl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_BORLVL_AW :: NMIISET_BORLVL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn nmiiset_borlvl_set (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_BORLVL_AW :: NMIISET_BORLVL_SET) } } # [doc = "Watch Dog 0 Fault\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum NMIISET_WWDT0_AW { # [doc = "0: NO_EFFECT"]
NMIISET_WWDT0_NO_EFFECT = 0 , # [doc = "1: SET"]
NMIISET_WWDT0_SET = 1 , } impl From < NMIISET_WWDT0_AW > for bool { # [inline (always)]
fn from (variant : NMIISET_WWDT0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIISET_WWDT0` writer - Watch Dog 0 Fault"]
pub type NMIISET_WWDT0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIISET_WWDT0_AW > ; impl < 'a , REG , const O : u8 > NMIISET_WWDT0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn nmiiset_wwdt0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_WWDT0_AW :: NMIISET_WWDT0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn nmiiset_wwdt0_set (self) -> & 'a mut crate :: W < REG > { self . variant (NMIISET_WWDT0_AW :: NMIISET_WWDT0_SET) } } impl W { # [doc = "Bit 0 - Set the BORLVL NMI"]
# [inline (always)]
# [must_use]
pub fn nmiiset_borlvl (& mut self) -> NMIISET_BORLVL_W < NMIISET_SPEC , 0 > { NMIISET_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watch Dog 0 Fault"]
# [inline (always)]
# [must_use]
pub fn nmiiset_wwdt0 (& mut self) -> NMIISET_WWDT0_W < NMIISET_SPEC , 1 > { NMIISET_WWDT0_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "NMI interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NMIISET_SPEC ; impl crate :: RegisterSpec for NMIISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`nmiiset::W`](W) writer structure"]
impl crate :: Writable for NMIISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets NMIISET to value 0"]
impl crate :: Resettable for NMIISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "NMIICLR (w) register accessor: NMI interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmiiclr`]
module"]
pub type NMIICLR = crate :: Reg < nmiiclr :: NMIICLR_SPEC > ; # [doc = "NMI interrupt clear"]
pub mod nmiiclr { # [doc = "Register `NMIICLR` writer"]
pub type W = crate :: W < NMIICLR_SPEC > ; # [doc = "Clr the BORLVL NMI\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum NMIICLR_BORLVL_AW { # [doc = "0: NO_EFFECT"]
NMIICLR_BORLVL_NO_EFFECT = 0 , # [doc = "1: CLR"]
NMIICLR_BORLVL_CLR = 1 , } impl From < NMIICLR_BORLVL_AW > for bool { # [inline (always)]
fn from (variant : NMIICLR_BORLVL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIICLR_BORLVL` writer - Clr the BORLVL NMI"]
pub type NMIICLR_BORLVL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIICLR_BORLVL_AW > ; impl < 'a , REG , const O : u8 > NMIICLR_BORLVL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn nmiiclr_borlvl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_BORLVL_AW :: NMIICLR_BORLVL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn nmiiclr_borlvl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_BORLVL_AW :: NMIICLR_BORLVL_CLR) } } # [doc = "Watch Dog 0 Fault\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum NMIICLR_WWDT0_AW { # [doc = "0: NO_EFFECT"]
NMIICLR_WWDT0_NO_EFFECT = 0 , # [doc = "1: CLR"]
NMIICLR_WWDT0_CLR = 1 , } impl From < NMIICLR_WWDT0_AW > for bool { # [inline (always)]
fn from (variant : NMIICLR_WWDT0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `NMIICLR_WWDT0` writer - Watch Dog 0 Fault"]
pub type NMIICLR_WWDT0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , NMIICLR_WWDT0_AW > ; impl < 'a , REG , const O : u8 > NMIICLR_WWDT0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn nmiiclr_wwdt0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_WWDT0_AW :: NMIICLR_WWDT0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn nmiiclr_wwdt0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (NMIICLR_WWDT0_AW :: NMIICLR_WWDT0_CLR) } } impl W { # [doc = "Bit 0 - Clr the BORLVL NMI"]
# [inline (always)]
# [must_use]
pub fn nmiiclr_borlvl (& mut self) -> NMIICLR_BORLVL_W < NMIICLR_SPEC , 0 > { NMIICLR_BORLVL_W :: new (self) } # [doc = "Bit 1 - Watch Dog 0 Fault"]
# [inline (always)]
# [must_use]
pub fn nmiiclr_wwdt0 (& mut self) -> NMIICLR_WWDT0_W < NMIICLR_SPEC , 1 > { NMIICLR_WWDT0_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "NMI interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`nmiiclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct NMIICLR_SPEC ; impl crate :: RegisterSpec for NMIICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`nmiiclr::W`](W) writer structure"]
impl crate :: Writable for NMIICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets NMIICLR to value 0"]
impl crate :: Resettable for NMIICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SYSOSCCFG (rw) register accessor: SYSOSC configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysosccfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysosccfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysosccfg`]
module"]
pub type SYSOSCCFG = crate :: Reg < sysosccfg :: SYSOSCCFG_SPEC > ; # [doc = "SYSOSC configuration"]
pub mod sysosccfg { # [doc = "Register `SYSOSCCFG` reader"]
pub type R = crate :: R < SYSOSCCFG_SPEC > ; # [doc = "Register `SYSOSCCFG` writer"]
pub type W = crate :: W < SYSOSCCFG_SPEC > ; # [doc = "Field `SYSOSCCFG_FREQ` reader - Target operating frequency for the system oscillator (SYSOSC)"]
pub type SYSOSCCFG_FREQ_R = crate :: FieldReader < SYSOSCCFG_FREQ_A > ; # [doc = "Target operating frequency for the system oscillator (SYSOSC)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SYSOSCCFG_FREQ_A { # [doc = "0: SYSOSCBASE"]
SYSOSCCFG_FREQ_SYSOSCBASE = 0 , # [doc = "1: SYSOSC4M"]
SYSOSCCFG_FREQ_SYSOSC4M = 1 , # [doc = "2: SYSOSCUSER"]
SYSOSCCFG_FREQ_SYSOSCUSER = 2 , # [doc = "3: SYSOSCTURBO"]
SYSOSCCFG_FREQ_SYSOSCTURBO = 3 , } impl From < SYSOSCCFG_FREQ_A > for u8 { # [inline (always)]
fn from (variant : SYSOSCCFG_FREQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for SYSOSCCFG_FREQ_A { type Ux = u8 ; } impl SYSOSCCFG_FREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SYSOSCCFG_FREQ_A { match self . bits { 0 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE , 1 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M , 2 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER , 3 => SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO , _ => unreachable ! () , } } # [doc = "SYSOSCBASE"]
# [inline (always)]
pub fn is_sysosccfg_freq_sysoscbase (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE } # [doc = "SYSOSC4M"]
# [inline (always)]
pub fn is_sysosccfg_freq_sysosc4m (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M } # [doc = "SYSOSCUSER"]
# [inline (always)]
pub fn is_sysosccfg_freq_sysoscuser (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER } # [doc = "SYSOSCTURBO"]
# [inline (always)]
pub fn is_sysosccfg_freq_sysoscturbo (& self) -> bool { * self == SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO } } # [doc = "Field `SYSOSCCFG_FREQ` writer - Target operating frequency for the system oscillator (SYSOSC)"]
pub type SYSOSCCFG_FREQ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , SYSOSCCFG_FREQ_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSOSCBASE"]
# [inline (always)]
pub fn sysosccfg_freq_sysoscbase (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCBASE) } # [doc = "SYSOSC4M"]
# [inline (always)]
pub fn sysosccfg_freq_sysosc4m (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSC4M) } # [doc = "SYSOSCUSER"]
# [inline (always)]
pub fn sysosccfg_freq_sysoscuser (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCUSER) } # [doc = "SYSOSCTURBO"]
# [inline (always)]
pub fn sysosccfg_freq_sysoscturbo (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FREQ_A :: SYSOSCCFG_FREQ_SYSOSCTURBO) } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` reader - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."]
pub type SYSOSCCFG_USE4MHZSTOP_R = crate :: BitReader < SYSOSCCFG_USE4MHZSTOP_A > ; # [doc = "USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SYSOSCCFG_USE4MHZSTOP_A { # [doc = "0: DISABLE"]
SYSOSCCFG_USE4MHZSTOP_DISABLE = 0 , # [doc = "1: ENABLE"]
SYSOSCCFG_USE4MHZSTOP_ENABLE = 1 , } impl From < SYSOSCCFG_USE4MHZSTOP_A > for bool { # [inline (always)]
fn from (variant : SYSOSCCFG_USE4MHZSTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_USE4MHZSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SYSOSCCFG_USE4MHZSTOP_A { match self . bits { false => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE , true => SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sysosccfg_use4mhzstop_disable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sysosccfg_use4mhzstop_enable (& self) -> bool { * self == SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_USE4MHZSTOP` writer - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."]
pub type SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_USE4MHZSTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_USE4MHZSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sysosccfg_use4mhzstop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sysosccfg_use4mhzstop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_USE4MHZSTOP_A :: SYSOSCCFG_USE4MHZSTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` reader - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."]
pub type SYSOSCCFG_DISABLESTOP_R = crate :: BitReader < SYSOSCCFG_DISABLESTOP_A > ; # [doc = "DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SYSOSCCFG_DISABLESTOP_A { # [doc = "0: DISABLE"]
SYSOSCCFG_DISABLESTOP_DISABLE = 0 , # [doc = "1: ENABLE"]
SYSOSCCFG_DISABLESTOP_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLESTOP_A > for bool { # [inline (always)]
fn from (variant : SYSOSCCFG_DISABLESTOP_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLESTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SYSOSCCFG_DISABLESTOP_A { match self . bits { false => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE , true => SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sysosccfg_disablestop_disable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sysosccfg_disablestop_enable (& self) -> bool { * self == SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLESTOP` writer - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."]
pub type SYSOSCCFG_DISABLESTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLESTOP_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLESTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sysosccfg_disablestop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sysosccfg_disablestop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLESTOP_A :: SYSOSCCFG_DISABLESTOP_ENABLE) } } # [doc = "Field `SYSOSCCFG_DISABLE` reader - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."]
pub type SYSOSCCFG_DISABLE_R = crate :: BitReader < SYSOSCCFG_DISABLE_A > ; # [doc = "DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SYSOSCCFG_DISABLE_A { # [doc = "0: DISABLE"]
SYSOSCCFG_DISABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
SYSOSCCFG_DISABLE_ENABLE = 1 , } impl From < SYSOSCCFG_DISABLE_A > for bool { # [inline (always)]
fn from (variant : SYSOSCCFG_DISABLE_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_DISABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SYSOSCCFG_DISABLE_A { match self . bits { false => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE , true => SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sysosccfg_disable_disable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sysosccfg_disable_enable (& self) -> bool { * self == SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE } } # [doc = "Field `SYSOSCCFG_DISABLE` writer - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."]
pub type SYSOSCCFG_DISABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_DISABLE_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_DISABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sysosccfg_disable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sysosccfg_disable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_DISABLE_A :: SYSOSCCFG_DISABLE_ENABLE) } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` reader - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."]
pub type SYSOSCCFG_BLOCKASYNCALL_R = crate :: BitReader < SYSOSCCFG_BLOCKASYNCALL_A > ; # [doc = "BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SYSOSCCFG_BLOCKASYNCALL_A { # [doc = "0: DISABLE"]
SYSOSCCFG_BLOCKASYNCALL_DISABLE = 0 , # [doc = "1: ENABLE"]
SYSOSCCFG_BLOCKASYNCALL_ENABLE = 1 , } impl From < SYSOSCCFG_BLOCKASYNCALL_A > for bool { # [inline (always)]
fn from (variant : SYSOSCCFG_BLOCKASYNCALL_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_BLOCKASYNCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SYSOSCCFG_BLOCKASYNCALL_A { match self . bits { false => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE , true => SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sysosccfg_blockasyncall_disable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sysosccfg_blockasyncall_enable (& self) -> bool { * self == SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE } } # [doc = "Field `SYSOSCCFG_BLOCKASYNCALL` writer - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."]
pub type SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_BLOCKASYNCALL_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_BLOCKASYNCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sysosccfg_blockasyncall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sysosccfg_blockasyncall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_BLOCKASYNCALL_A :: SYSOSCCFG_BLOCKASYNCALL_ENABLE) } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` reader - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."]
pub type SYSOSCCFG_FASTCPUEVENT_R = crate :: BitReader < SYSOSCCFG_FASTCPUEVENT_A > ; # [doc = "FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency.\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SYSOSCCFG_FASTCPUEVENT_A { # [doc = "0: DISABLE"]
SYSOSCCFG_FASTCPUEVENT_DISABLE = 0 , # [doc = "1: ENABLE"]
SYSOSCCFG_FASTCPUEVENT_ENABLE = 1 , } impl From < SYSOSCCFG_FASTCPUEVENT_A > for bool { # [inline (always)]
fn from (variant : SYSOSCCFG_FASTCPUEVENT_A) -> Self { variant as u8 != 0 } } impl SYSOSCCFG_FASTCPUEVENT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SYSOSCCFG_FASTCPUEVENT_A { match self . bits { false => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE , true => SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sysosccfg_fastcpuevent_disable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sysosccfg_fastcpuevent_enable (& self) -> bool { * self == SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE } } # [doc = "Field `SYSOSCCFG_FASTCPUEVENT` writer - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."]
pub type SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCCFG_FASTCPUEVENT_A > ; impl < 'a , REG , const O : u8 > SYSOSCCFG_FASTCPUEVENT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sysosccfg_fastcpuevent_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sysosccfg_fastcpuevent_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCCFG_FASTCPUEVENT_A :: SYSOSCCFG_FASTCPUEVENT_ENABLE) } } impl R { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"]
# [inline (always)]
pub fn sysosccfg_freq (& self) -> SYSOSCCFG_FREQ_R { SYSOSCCFG_FREQ_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."]
# [inline (always)]
pub fn sysosccfg_use4mhzstop (& self) -> SYSOSCCFG_USE4MHZSTOP_R { SYSOSCCFG_USE4MHZSTOP_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."]
# [inline (always)]
pub fn sysosccfg_disablestop (& self) -> SYSOSCCFG_DISABLESTOP_R { SYSOSCCFG_DISABLESTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."]
# [inline (always)]
pub fn sysosccfg_disable (& self) -> SYSOSCCFG_DISABLE_R { SYSOSCCFG_DISABLE_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."]
# [inline (always)]
pub fn sysosccfg_blockasyncall (& self) -> SYSOSCCFG_BLOCKASYNCALL_R { SYSOSCCFG_BLOCKASYNCALL_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."]
# [inline (always)]
pub fn sysosccfg_fastcpuevent (& self) -> SYSOSCCFG_FASTCPUEVENT_R { SYSOSCCFG_FASTCPUEVENT_R :: new (((self . bits >> 17) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - Target operating frequency for the system oscillator (SYSOSC)"]
# [inline (always)]
# [must_use]
pub fn sysosccfg_freq (& mut self) -> SYSOSCCFG_FREQ_W < SYSOSCCFG_SPEC , 0 > { SYSOSCCFG_FREQ_W :: new (self) } # [doc = "Bit 8 - USE4MHZSTOP sets the SYSOSC stop mode frequency policy. When entering STOP mode, the SYSOSC frequency may be automatically switched to 4MHz to reduce SYSOSC power consumption."]
# [inline (always)]
# [must_use]
pub fn sysosccfg_use4mhzstop (& mut self) -> SYSOSCCFG_USE4MHZSTOP_W < SYSOSCCFG_SPEC , 8 > { SYSOSCCFG_USE4MHZSTOP_W :: new (self) } # [doc = "Bit 9 - DISABLESTOP sets the SYSOSC stop mode enable/disable policy. When operating in STOP mode, the SYSOSC may be automatically disabled. When set, ULPCLK will run from LFCLK in STOP mode and SYSOSC will be disabled to reduce power consumption."]
# [inline (always)]
# [must_use]
pub fn sysosccfg_disablestop (& mut self) -> SYSOSCCFG_DISABLESTOP_W < SYSOSCCFG_SPEC , 9 > { SYSOSCCFG_DISABLESTOP_W :: new (self) } # [doc = "Bit 10 - DISABLE sets the SYSOSC enable/disable policy. SYSOSC may be powered off in RUN, SLEEP, and STOP modes to reduce power consumption. When SYSOSC is disabled, MCLK and ULPCLK are sourced from LFCLK."]
# [inline (always)]
# [must_use]
pub fn sysosccfg_disable (& mut self) -> SYSOSCCFG_DISABLE_W < SYSOSCCFG_SPEC , 10 > { SYSOSCCFG_DISABLE_W :: new (self) } # [doc = "Bit 16 - BLOCKASYNCALL may be used to mask block all asynchronous fast clock requests, preventing hardware from dynamically changing the active clock configuration when operating in a given mode."]
# [inline (always)]
# [must_use]
pub fn sysosccfg_blockasyncall (& mut self) -> SYSOSCCFG_BLOCKASYNCALL_W < SYSOSCCFG_SPEC , 16 > { SYSOSCCFG_BLOCKASYNCALL_W :: new (self) } # [doc = "Bit 17 - FASTCPUEVENT may be used to assert a fast clock request when an interrupt is asserted to the CPU, reducing interrupt latency."]
# [inline (always)]
# [must_use]
pub fn sysosccfg_fastcpuevent (& mut self) -> SYSOSCCFG_FASTCPUEVENT_W < SYSOSCCFG_SPEC , 17 > { SYSOSCCFG_FASTCPUEVENT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSOSC configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysosccfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysosccfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SYSOSCCFG_SPEC ; impl crate :: RegisterSpec for SYSOSCCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sysosccfg::R`](R) reader structure"]
impl crate :: Readable for SYSOSCCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`sysosccfg::W`](W) writer structure"]
impl crate :: Writable for SYSOSCCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SYSOSCCFG to value 0x0002_0000"]
impl crate :: Resettable for SYSOSCCFG_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0000 ; } } # [doc = "MCLKCFG (rw) register accessor: Main clock (MCLK) configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mclkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mclkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mclkcfg`]
module"]
pub type MCLKCFG = crate :: Reg < mclkcfg :: MCLKCFG_SPEC > ; # [doc = "Main clock (MCLK) configuration"]
pub mod mclkcfg { # [doc = "Register `MCLKCFG` reader"]
pub type R = crate :: R < MCLKCFG_SPEC > ; # [doc = "Register `MCLKCFG` writer"]
pub type W = crate :: W < MCLKCFG_SPEC > ; # [doc = "Field `MCLKCFG_MDIV` reader - MDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC"]
pub type MCLKCFG_MDIV_R = crate :: FieldReader ; # [doc = "Field `MCLKCFG_MDIV` writer - MDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC"]
pub type MCLKCFG_MDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; # [doc = "Field `MCLKCFG_FLASHWAIT` reader - FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK"]
pub type MCLKCFG_FLASHWAIT_R = crate :: FieldReader ; # [doc = "Field `MCLKCFG_FLASHWAIT` writer - FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK"]
pub type MCLKCFG_FLASHWAIT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; # [doc = "Field `MCLKCFG_USEMFTICK` reader - USEMFTICK specifies whether the 4MHz constant-rate cloc20(MFCLK) to peripherals is enabled or disabled."]
pub type MCLKCFG_USEMFTICK_R = crate :: BitReader ; # [doc = "Field `MCLKCFG_USEMFTICK` writer - USEMFTICK specifies whether the 4MHz constant-rate cloc20(MFCLK) to peripherals is enabled or disabled."]
pub type MCLKCFG_USEMFTICK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `MCLKCFG_USELFCLK` reader - USELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source"]
pub type MCLKCFG_USELFCLK_R = crate :: BitReader ; # [doc = "Field `MCLKCFG_USELFCLK` writer - USELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source"]
pub type MCLKCFG_USELFCLK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `MCLKCFG_STOPCLKSTBY` reader - STOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1)."]
pub type MCLKCFG_STOPCLKSTBY_R = crate :: BitReader ; # [doc = "Field `MCLKCFG_STOPCLKSTBY` writer - STOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1)."]
pub type MCLKCFG_STOPCLKSTBY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `MCLKCFG_MCLKDEADCHK` reader - MCLKDEADCHK enables or disables the continuous MCLK dead check monitor"]
pub type MCLKCFG_MCLKDEADCHK_R = crate :: BitReader ; # [doc = "Field `MCLKCFG_MCLKDEADCHK` writer - MCLKDEADCHK enables or disables the continuous MCLK dead check monitor"]
pub type MCLKCFG_MCLKDEADCHK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; impl R { # [doc = "Bits 0:3 - MDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC"]
# [inline (always)]
pub fn mclkcfg_mdiv (& self) -> MCLKCFG_MDIV_R { MCLKCFG_MDIV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 8:11 - FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK"]
# [inline (always)]
pub fn mclkcfg_flashwait (& self) -> MCLKCFG_FLASHWAIT_R { MCLKCFG_FLASHWAIT_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 12 - USEMFTICK specifies whether the 4MHz constant-rate cloc20(MFCLK) to peripherals is enabled or disabled."]
# [inline (always)]
pub fn mclkcfg_usemftick (& self) -> MCLKCFG_USEMFTICK_R { MCLKCFG_USEMFTICK_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 20 - USELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source"]
# [inline (always)]
pub fn mclkcfg_uselfclk (& self) -> MCLKCFG_USELFCLK_R { MCLKCFG_USELFCLK_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - STOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1)."]
# [inline (always)]
pub fn mclkcfg_stopclkstby (& self) -> MCLKCFG_STOPCLKSTBY_R { MCLKCFG_STOPCLKSTBY_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - MCLKDEADCHK enables or disables the continuous MCLK dead check monitor"]
# [inline (always)]
pub fn mclkcfg_mclkdeadchk (& self) -> MCLKCFG_MCLKDEADCHK_R { MCLKCFG_MCLKDEADCHK_R :: new (((self . bits >> 22) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - MDIV may be used to divide the MCLK frequency when MCLK is sourced from SYSOSC"]
# [inline (always)]
# [must_use]
pub fn mclkcfg_mdiv (& mut self) -> MCLKCFG_MDIV_W < MCLKCFG_SPEC , 0 > { MCLKCFG_MDIV_W :: new (self) } # [doc = "Bits 8:11 - FLASHWAIT specifies the number of flash wait states when MCLK is sourced from HSCLK"]
# [inline (always)]
# [must_use]
pub fn mclkcfg_flashwait (& mut self) -> MCLKCFG_FLASHWAIT_W < MCLKCFG_SPEC , 8 > { MCLKCFG_FLASHWAIT_W :: new (self) } # [doc = "Bit 12 - USEMFTICK specifies whether the 4MHz constant-rate cloc20(MFCLK) to peripherals is enabled or disabled."]
# [inline (always)]
# [must_use]
pub fn mclkcfg_usemftick (& mut self) -> MCLKCFG_USEMFTICK_W < MCLKCFG_SPEC , 12 > { MCLKCFG_USEMFTICK_W :: new (self) } # [doc = "Bit 20 - USELFCLK sets the MCLK source policy. Set USELFCLK to use LFCLK as the MCLK source"]
# [inline (always)]
# [must_use]
pub fn mclkcfg_uselfclk (& mut self) -> MCLKCFG_USELFCLK_W < MCLKCFG_SPEC , 20 > { MCLKCFG_USELFCLK_W :: new (self) } # [doc = "Bit 21 - STOPCLKSTBY sets the STANDBY mode policy (STANDBY0 or STANDBY1)."]
# [inline (always)]
# [must_use]
pub fn mclkcfg_stopclkstby (& mut self) -> MCLKCFG_STOPCLKSTBY_W < MCLKCFG_SPEC , 21 > { MCLKCFG_STOPCLKSTBY_W :: new (self) } # [doc = "Bit 22 - MCLKDEADCHK enables or disables the continuous MCLK dead check monitor"]
# [inline (always)]
# [must_use]
pub fn mclkcfg_mclkdeadchk (& mut self) -> MCLKCFG_MCLKDEADCHK_W < MCLKCFG_SPEC , 22 > { MCLKCFG_MCLKDEADCHK_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Main clock (MCLK) configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mclkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mclkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MCLKCFG_SPEC ; impl crate :: RegisterSpec for MCLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mclkcfg::R`](R) reader structure"]
impl crate :: Readable for MCLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`mclkcfg::W`](W) writer structure"]
impl crate :: Writable for MCLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCLKCFG to value 0"]
impl crate :: Resettable for MCLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GENCLKCFG (rw) register accessor: General clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`genclkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`genclkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@genclkcfg`]
module"]
pub type GENCLKCFG = crate :: Reg < genclkcfg :: GENCLKCFG_SPEC > ; # [doc = "General clock configuration"]
pub mod genclkcfg { # [doc = "Register `GENCLKCFG` reader"]
pub type R = crate :: R < GENCLKCFG_SPEC > ; # [doc = "Register `GENCLKCFG` writer"]
pub type W = crate :: W < GENCLKCFG_SPEC > ; # [doc = "Field `GENCLKCFG_EXCLKSRC` reader - EXCLKSRC selects the source for the CLK_OUT external clockoutput block. ULPCLK and MFPCLK require the CLK_OUT divider(EXCLKDIVEN) to be enabled"]
pub type GENCLKCFG_EXCLKSRC_R = crate :: FieldReader ; # [doc = "Field `GENCLKCFG_EXCLKSRC` writer - EXCLKSRC selects the source for the CLK_OUT external clockoutput block. ULPCLK and MFPCLK require the CLK_OUT divider(EXCLKDIVEN) to be enabled"]
pub type GENCLKCFG_EXCLKSRC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `GENCLKCFG_EXCLKDIVVAL` reader - EXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block."]
pub type GENCLKCFG_EXCLKDIVVAL_R = crate :: FieldReader ; # [doc = "Field `GENCLKCFG_EXCLKDIVVAL` writer - EXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block."]
pub type GENCLKCFG_EXCLKDIVVAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `GENCLKCFG_EXCLKDIVEN` reader - EXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block."]
pub type GENCLKCFG_EXCLKDIVEN_R = crate :: BitReader ; # [doc = "Field `GENCLKCFG_EXCLKDIVEN` writer - EXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block."]
pub type GENCLKCFG_EXCLKDIVEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `GENCLKCFG_FCCSELCLK` reader - FCCSELCLK selectes the frequency clock counter (FCC) clock source"]
pub type GENCLKCFG_FCCSELCLK_R = crate :: FieldReader ; # [doc = "Field `GENCLKCFG_FCCSELCLK` writer - FCCSELCLK selectes the frequency clock counter (FCC) clock source"]
pub type GENCLKCFG_FCCSELCLK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; # [doc = "Field `GENCLKCFG_FCCTRIGSRC` reader - FCCTRIGSRC selects the frequency clock counter (FCC) trigger source"]
pub type GENCLKCFG_FCCTRIGSRC_R = crate :: BitReader ; # [doc = "Field `GENCLKCFG_FCCTRIGSRC` writer - FCCTRIGSRC selects the frequency clock counter (FCC) trigger source"]
pub type GENCLKCFG_FCCTRIGSRC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `GENCLKCFG_FCCLVLTRIG` reader - FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode"]
pub type GENCLKCFG_FCCLVLTRIG_R = crate :: BitReader ; # [doc = "Field `GENCLKCFG_FCCLVLTRIG` writer - FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode"]
pub type GENCLKCFG_FCCLVLTRIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `GENCLKCFG_ANACPUMPCFG` reader - ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method."]
pub type GENCLKCFG_ANACPUMPCFG_R = crate :: FieldReader ; # [doc = "Field `GENCLKCFG_ANACPUMPCFG` writer - ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method."]
pub type GENCLKCFG_ANACPUMPCFG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O > ; # [doc = "Field `GENCLKCFG_FCCTRIGCNT` reader - FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified."]
pub type GENCLKCFG_FCCTRIGCNT_R = crate :: FieldReader ; # [doc = "Field `GENCLKCFG_FCCTRIGCNT` writer - FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified."]
pub type GENCLKCFG_FCCTRIGCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O > ; impl R { # [doc = "Bits 0:2 - EXCLKSRC selects the source for the CLK_OUT external clockoutput block. ULPCLK and MFPCLK require the CLK_OUT divider(EXCLKDIVEN) to be enabled"]
# [inline (always)]
pub fn genclkcfg_exclksrc (& self) -> GENCLKCFG_EXCLKSRC_R { GENCLKCFG_EXCLKSRC_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - EXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block."]
# [inline (always)]
pub fn genclkcfg_exclkdivval (& self) -> GENCLKCFG_EXCLKDIVVAL_R { GENCLKCFG_EXCLKDIVVAL_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bit 7 - EXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block."]
# [inline (always)]
pub fn genclkcfg_exclkdiven (& self) -> GENCLKCFG_EXCLKDIVEN_R { GENCLKCFG_EXCLKDIVEN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:19 - FCCSELCLK selectes the frequency clock counter (FCC) clock source"]
# [inline (always)]
pub fn genclkcfg_fccselclk (& self) -> GENCLKCFG_FCCSELCLK_R { GENCLKCFG_FCCSELCLK_R :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bit 20 - FCCTRIGSRC selects the frequency clock counter (FCC) trigger source"]
# [inline (always)]
pub fn genclkcfg_fcctrigsrc (& self) -> GENCLKCFG_FCCTRIGSRC_R { GENCLKCFG_FCCTRIGSRC_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode"]
# [inline (always)]
pub fn genclkcfg_fcclvltrig (& self) -> GENCLKCFG_FCCLVLTRIG_R { GENCLKCFG_FCCLVLTRIG_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bits 22:23 - ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method."]
# [inline (always)]
pub fn genclkcfg_anacpumpcfg (& self) -> GENCLKCFG_ANACPUMPCFG_R { GENCLKCFG_ANACPUMPCFG_R :: new (((self . bits >> 22) & 3) as u8) } # [doc = "Bits 24:28 - FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified."]
# [inline (always)]
pub fn genclkcfg_fcctrigcnt (& self) -> GENCLKCFG_FCCTRIGCNT_R { GENCLKCFG_FCCTRIGCNT_R :: new (((self . bits >> 24) & 0x1f) as u8) } } impl W { # [doc = "Bits 0:2 - EXCLKSRC selects the source for the CLK_OUT external clockoutput block. ULPCLK and MFPCLK require the CLK_OUT divider(EXCLKDIVEN) to be enabled"]
# [inline (always)]
# [must_use]
pub fn genclkcfg_exclksrc (& mut self) -> GENCLKCFG_EXCLKSRC_W < GENCLKCFG_SPEC , 0 > { GENCLKCFG_EXCLKSRC_W :: new (self) } # [doc = "Bits 4:6 - EXCLKDIVVAL selects the divider value for the divider in the CLK_OUT external clock output block."]
# [inline (always)]
# [must_use]
pub fn genclkcfg_exclkdivval (& mut self) -> GENCLKCFG_EXCLKDIVVAL_W < GENCLKCFG_SPEC , 4 > { GENCLKCFG_EXCLKDIVVAL_W :: new (self) } # [doc = "Bit 7 - EXCLKDIVEN enables or disables the divider function of the CLK_OUT external clock output block."]
# [inline (always)]
# [must_use]
pub fn genclkcfg_exclkdiven (& mut self) -> GENCLKCFG_EXCLKDIVEN_W < GENCLKCFG_SPEC , 7 > { GENCLKCFG_EXCLKDIVEN_W :: new (self) } # [doc = "Bits 16:19 - FCCSELCLK selectes the frequency clock counter (FCC) clock source"]
# [inline (always)]
# [must_use]
pub fn genclkcfg_fccselclk (& mut self) -> GENCLKCFG_FCCSELCLK_W < GENCLKCFG_SPEC , 16 > { GENCLKCFG_FCCSELCLK_W :: new (self) } # [doc = "Bit 20 - FCCTRIGSRC selects the frequency clock counter (FCC) trigger source"]
# [inline (always)]
# [must_use]
pub fn genclkcfg_fcctrigsrc (& mut self) -> GENCLKCFG_FCCTRIGSRC_W < GENCLKCFG_SPEC , 20 > { GENCLKCFG_FCCTRIGSRC_W :: new (self) } # [doc = "Bit 21 - FCCLVLTRIG selects the frequency clock counter (FCC) trigger mode"]
# [inline (always)]
# [must_use]
pub fn genclkcfg_fcclvltrig (& mut self) -> GENCLKCFG_FCCLVLTRIG_W < GENCLKCFG_SPEC , 21 > { GENCLKCFG_FCCLVLTRIG_W :: new (self) } # [doc = "Bits 22:23 - ANACPUMPCFG selects the analog mux charge pump (VBOOST) enable method."]
# [inline (always)]
# [must_use]
pub fn genclkcfg_anacpumpcfg (& mut self) -> GENCLKCFG_ANACPUMPCFG_W < GENCLKCFG_SPEC , 22 > { GENCLKCFG_ANACPUMPCFG_W :: new (self) } # [doc = "Bits 24:28 - FCCTRIGCNT specifies the number of trigger clock periods in the trigger window. FCCTRIGCNT=0h (one trigger clock period) up to 1Fh (32 trigger clock periods) may be specified."]
# [inline (always)]
# [must_use]
pub fn genclkcfg_fcctrigcnt (& mut self) -> GENCLKCFG_FCCTRIGCNT_W < GENCLKCFG_SPEC , 24 > { GENCLKCFG_FCCTRIGCNT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "General clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`genclkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`genclkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GENCLKCFG_SPEC ; impl crate :: RegisterSpec for GENCLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`genclkcfg::R`](R) reader structure"]
impl crate :: Readable for GENCLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`genclkcfg::W`](W) writer structure"]
impl crate :: Writable for GENCLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GENCLKCFG to value 0"]
impl crate :: Resettable for GENCLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GENCLKEN (rw) register accessor: General clock enable control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`genclken::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`genclken::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@genclken`]
module"]
pub type GENCLKEN = crate :: Reg < genclken :: GENCLKEN_SPEC > ; # [doc = "General clock enable control"]
pub mod genclken { # [doc = "Register `GENCLKEN` reader"]
pub type R = crate :: R < GENCLKEN_SPEC > ; # [doc = "Register `GENCLKEN` writer"]
pub type W = crate :: W < GENCLKEN_SPEC > ; # [doc = "Field `GENCLKEN_EXCLKEN` reader - EXCLKEN enables the CLK_OUT external clock output block."]
pub type GENCLKEN_EXCLKEN_R = crate :: BitReader < GENCLKEN_EXCLKEN_A > ; # [doc = "EXCLKEN enables the CLK_OUT external clock output block.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GENCLKEN_EXCLKEN_A { # [doc = "0: DISABLE"]
GENCLKEN_EXCLKEN_DISABLE = 0 , # [doc = "1: ENABLE"]
GENCLKEN_EXCLKEN_ENABLE = 1 , } impl From < GENCLKEN_EXCLKEN_A > for bool { # [inline (always)]
fn from (variant : GENCLKEN_EXCLKEN_A) -> Self { variant as u8 != 0 } } impl GENCLKEN_EXCLKEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GENCLKEN_EXCLKEN_A { match self . bits { false => GENCLKEN_EXCLKEN_A :: GENCLKEN_EXCLKEN_DISABLE , true => GENCLKEN_EXCLKEN_A :: GENCLKEN_EXCLKEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_genclken_exclken_disable (& self) -> bool { * self == GENCLKEN_EXCLKEN_A :: GENCLKEN_EXCLKEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_genclken_exclken_enable (& self) -> bool { * self == GENCLKEN_EXCLKEN_A :: GENCLKEN_EXCLKEN_ENABLE } } # [doc = "Field `GENCLKEN_EXCLKEN` writer - EXCLKEN enables the CLK_OUT external clock output block."]
pub type GENCLKEN_EXCLKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GENCLKEN_EXCLKEN_A > ; impl < 'a , REG , const O : u8 > GENCLKEN_EXCLKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn genclken_exclken_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GENCLKEN_EXCLKEN_A :: GENCLKEN_EXCLKEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn genclken_exclken_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GENCLKEN_EXCLKEN_A :: GENCLKEN_EXCLKEN_ENABLE) } } # [doc = "Field `GENCLKEN_MFPCLKEN` reader - MFPCLKEN enables the middle frequency precision clock (MFPCLK)."]
pub type GENCLKEN_MFPCLKEN_R = crate :: BitReader < GENCLKEN_MFPCLKEN_A > ; # [doc = "MFPCLKEN enables the middle frequency precision clock (MFPCLK).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GENCLKEN_MFPCLKEN_A { # [doc = "0: DISABLE"]
GENCLKEN_MFPCLKEN_DISABLE = 0 , # [doc = "1: ENABLE"]
GENCLKEN_MFPCLKEN_ENABLE = 1 , } impl From < GENCLKEN_MFPCLKEN_A > for bool { # [inline (always)]
fn from (variant : GENCLKEN_MFPCLKEN_A) -> Self { variant as u8 != 0 } } impl GENCLKEN_MFPCLKEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GENCLKEN_MFPCLKEN_A { match self . bits { false => GENCLKEN_MFPCLKEN_A :: GENCLKEN_MFPCLKEN_DISABLE , true => GENCLKEN_MFPCLKEN_A :: GENCLKEN_MFPCLKEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_genclken_mfpclken_disable (& self) -> bool { * self == GENCLKEN_MFPCLKEN_A :: GENCLKEN_MFPCLKEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_genclken_mfpclken_enable (& self) -> bool { * self == GENCLKEN_MFPCLKEN_A :: GENCLKEN_MFPCLKEN_ENABLE } } # [doc = "Field `GENCLKEN_MFPCLKEN` writer - MFPCLKEN enables the middle frequency precision clock (MFPCLK)."]
pub type GENCLKEN_MFPCLKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GENCLKEN_MFPCLKEN_A > ; impl < 'a , REG , const O : u8 > GENCLKEN_MFPCLKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn genclken_mfpclken_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GENCLKEN_MFPCLKEN_A :: GENCLKEN_MFPCLKEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn genclken_mfpclken_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GENCLKEN_MFPCLKEN_A :: GENCLKEN_MFPCLKEN_ENABLE) } } impl R { # [doc = "Bit 0 - EXCLKEN enables the CLK_OUT external clock output block."]
# [inline (always)]
pub fn genclken_exclken (& self) -> GENCLKEN_EXCLKEN_R { GENCLKEN_EXCLKEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 4 - MFPCLKEN enables the middle frequency precision clock (MFPCLK)."]
# [inline (always)]
pub fn genclken_mfpclken (& self) -> GENCLKEN_MFPCLKEN_R { GENCLKEN_MFPCLKEN_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - EXCLKEN enables the CLK_OUT external clock output block."]
# [inline (always)]
# [must_use]
pub fn genclken_exclken (& mut self) -> GENCLKEN_EXCLKEN_W < GENCLKEN_SPEC , 0 > { GENCLKEN_EXCLKEN_W :: new (self) } # [doc = "Bit 4 - MFPCLKEN enables the middle frequency precision clock (MFPCLK)."]
# [inline (always)]
# [must_use]
pub fn genclken_mfpclken (& mut self) -> GENCLKEN_MFPCLKEN_W < GENCLKEN_SPEC , 4 > { GENCLKEN_MFPCLKEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "General clock enable control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`genclken::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`genclken::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GENCLKEN_SPEC ; impl crate :: RegisterSpec for GENCLKEN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`genclken::R`](R) reader structure"]
impl crate :: Readable for GENCLKEN_SPEC { } # [doc = "`write(|w| ..)` method takes [`genclken::W`](W) writer structure"]
impl crate :: Writable for GENCLKEN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GENCLKEN to value 0"]
impl crate :: Resettable for GENCLKEN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PMODECFG (rw) register accessor: Power mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmodecfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmodecfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmodecfg`]
module"]
pub type PMODECFG = crate :: Reg < pmodecfg :: PMODECFG_SPEC > ; # [doc = "Power mode configuration"]
pub mod pmodecfg { # [doc = "Register `PMODECFG` reader"]
pub type R = crate :: R < PMODECFG_SPEC > ; # [doc = "Register `PMODECFG` writer"]
pub type W = crate :: W < PMODECFG_SPEC > ; # [doc = "Field `PMODECFG_DSLEEP` reader - DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU."]
pub type PMODECFG_DSLEEP_R = crate :: FieldReader < PMODECFG_DSLEEP_A > ; # [doc = "DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PMODECFG_DSLEEP_A { # [doc = "0: STOP"]
PMODECFG_DSLEEP_STOP = 0 , # [doc = "1: STANDBY"]
PMODECFG_DSLEEP_STANDBY = 1 , # [doc = "2: SHUTDOWN"]
PMODECFG_DSLEEP_SHUTDOWN = 2 , } impl From < PMODECFG_DSLEEP_A > for u8 { # [inline (always)]
fn from (variant : PMODECFG_DSLEEP_A) -> Self { variant as _ } } impl crate :: FieldSpec for PMODECFG_DSLEEP_A { type Ux = u8 ; } impl PMODECFG_DSLEEP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < PMODECFG_DSLEEP_A > { match self . bits { 0 => Some (PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_STOP) , 1 => Some (PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_STANDBY) , 2 => Some (PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_SHUTDOWN) , _ => None , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pmodecfg_dsleep_stop (& self) -> bool { * self == PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_STOP } # [doc = "STANDBY"]
# [inline (always)]
pub fn is_pmodecfg_dsleep_standby (& self) -> bool { * self == PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_STANDBY } # [doc = "SHUTDOWN"]
# [inline (always)]
pub fn is_pmodecfg_dsleep_shutdown (& self) -> bool { * self == PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_SHUTDOWN } } # [doc = "Field `PMODECFG_DSLEEP` writer - DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU."]
pub type PMODECFG_DSLEEP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , PMODECFG_DSLEEP_A > ; impl < 'a , REG , const O : u8 > PMODECFG_DSLEEP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "STOP"]
# [inline (always)]
pub fn pmodecfg_dsleep_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_STOP) } # [doc = "STANDBY"]
# [inline (always)]
pub fn pmodecfg_dsleep_standby (self) -> & 'a mut crate :: W < REG > { self . variant (PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_STANDBY) } # [doc = "SHUTDOWN"]
# [inline (always)]
pub fn pmodecfg_dsleep_shutdown (self) -> & 'a mut crate :: W < REG > { self . variant (PMODECFG_DSLEEP_A :: PMODECFG_DSLEEP_SHUTDOWN) } } # [doc = "Field `PMODECFG_SYSSRAMONSTOP` reader - SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode."]
pub type PMODECFG_SYSSRAMONSTOP_R = crate :: BitReader < PMODECFG_SYSSRAMONSTOP_A > ; # [doc = "SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PMODECFG_SYSSRAMONSTOP_A { # [doc = "0: DISABLE"]
PMODECFG_SYSSRAMONSTOP_DISABLE = 0 , # [doc = "1: ENABLE"]
PMODECFG_SYSSRAMONSTOP_ENABLE = 1 , } impl From < PMODECFG_SYSSRAMONSTOP_A > for bool { # [inline (always)]
fn from (variant : PMODECFG_SYSSRAMONSTOP_A) -> Self { variant as u8 != 0 } } impl PMODECFG_SYSSRAMONSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PMODECFG_SYSSRAMONSTOP_A { match self . bits { false => PMODECFG_SYSSRAMONSTOP_A :: PMODECFG_SYSSRAMONSTOP_DISABLE , true => PMODECFG_SYSSRAMONSTOP_A :: PMODECFG_SYSSRAMONSTOP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pmodecfg_syssramonstop_disable (& self) -> bool { * self == PMODECFG_SYSSRAMONSTOP_A :: PMODECFG_SYSSRAMONSTOP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pmodecfg_syssramonstop_enable (& self) -> bool { * self == PMODECFG_SYSSRAMONSTOP_A :: PMODECFG_SYSSRAMONSTOP_ENABLE } } # [doc = "Field `PMODECFG_SYSSRAMONSTOP` writer - SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode."]
pub type PMODECFG_SYSSRAMONSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PMODECFG_SYSSRAMONSTOP_A > ; impl < 'a , REG , const O : u8 > PMODECFG_SYSSRAMONSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pmodecfg_syssramonstop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PMODECFG_SYSSRAMONSTOP_A :: PMODECFG_SYSSRAMONSTOP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pmodecfg_syssramonstop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PMODECFG_SYSSRAMONSTOP_A :: PMODECFG_SYSSRAMONSTOP_ENABLE) } } impl R { # [doc = "Bits 0:1 - DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU."]
# [inline (always)]
pub fn pmodecfg_dsleep (& self) -> PMODECFG_DSLEEP_R { PMODECFG_DSLEEP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 5 - SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode."]
# [inline (always)]
pub fn pmodecfg_syssramonstop (& self) -> PMODECFG_SYSSRAMONSTOP_R { PMODECFG_SYSSRAMONSTOP_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - DSLEEP selects the operating mode to enter upon a DEEPSLEEP request from the CPU."]
# [inline (always)]
# [must_use]
pub fn pmodecfg_dsleep (& mut self) -> PMODECFG_DSLEEP_W < PMODECFG_SPEC , 0 > { PMODECFG_DSLEEP_W :: new (self) } # [doc = "Bit 5 - SYSSRAMONSTOP selects whether the SRAM controller is enabled or disabled in STOP mode."]
# [inline (always)]
# [must_use]
pub fn pmodecfg_syssramonstop (& mut self) -> PMODECFG_SYSSRAMONSTOP_W < PMODECFG_SPEC , 5 > { PMODECFG_SYSSRAMONSTOP_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power mode configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmodecfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmodecfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PMODECFG_SPEC ; impl crate :: RegisterSpec for PMODECFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pmodecfg::R`](R) reader structure"]
impl crate :: Readable for PMODECFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`pmodecfg::W`](W) writer structure"]
impl crate :: Writable for PMODECFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PMODECFG to value 0"]
impl crate :: Resettable for PMODECFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FCC (r) register accessor: Frequency clock counter (FCC) count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcc`]
module"]
pub type FCC = crate :: Reg < fcc :: FCC_SPEC > ; # [doc = "Frequency clock counter (FCC) count"]
pub mod fcc { # [doc = "Register `FCC` reader"]
pub type R = crate :: R < FCC_SPEC > ; # [doc = "Field `FCC_DATA` reader - Frequency clock counter (FCC) count value."]
pub type FCC_DATA_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 0:21 - Frequency clock counter (FCC) count value."]
# [inline (always)]
pub fn fcc_data (& self) -> FCC_DATA_R { FCC_DATA_R :: new (self . bits & 0x003f_ffff) } } # [doc = "Frequency clock counter (FCC) count\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fcc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FCC_SPEC ; impl crate :: RegisterSpec for FCC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fcc::R`](R) reader structure"]
impl crate :: Readable for FCC_SPEC { } # [doc = "`reset()` method sets FCC to value 0"]
impl crate :: Resettable for FCC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SYSOSCTRIMUSER (rw) register accessor: SYSOSC user-specified trim\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysosctrimuser::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysosctrimuser::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysosctrimuser`]
module"]
pub type SYSOSCTRIMUSER = crate :: Reg < sysosctrimuser :: SYSOSCTRIMUSER_SPEC > ; # [doc = "SYSOSC user-specified trim"]
pub mod sysosctrimuser { # [doc = "Register `SYSOSCTRIMUSER` reader"]
pub type R = crate :: R < SYSOSCTRIMUSER_SPEC > ; # [doc = "Register `SYSOSCTRIMUSER` writer"]
pub type W = crate :: W < SYSOSCTRIMUSER_SPEC > ; # [doc = "Field `SYSOSCTRIMUSER_FREQ` reader - FREQ specifies the target user-trimmed frequency for SYSOSC."]
pub type SYSOSCTRIMUSER_FREQ_R = crate :: FieldReader < SYSOSCTRIMUSER_FREQ_A > ; # [doc = "FREQ specifies the target user-trimmed frequency for SYSOSC.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SYSOSCTRIMUSER_FREQ_A { # [doc = "1: SYSOSC16M"]
SYSOSCTRIMUSER_FREQ_SYSOSC16M = 1 , # [doc = "2: SYSOSC24M"]
SYSOSCTRIMUSER_FREQ_SYSOSC24M = 2 , } impl From < SYSOSCTRIMUSER_FREQ_A > for u8 { # [inline (always)]
fn from (variant : SYSOSCTRIMUSER_FREQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for SYSOSCTRIMUSER_FREQ_A { type Ux = u8 ; } impl SYSOSCTRIMUSER_FREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SYSOSCTRIMUSER_FREQ_A > { match self . bits { 1 => Some (SYSOSCTRIMUSER_FREQ_A :: SYSOSCTRIMUSER_FREQ_SYSOSC16M) , 2 => Some (SYSOSCTRIMUSER_FREQ_A :: SYSOSCTRIMUSER_FREQ_SYSOSC24M) , _ => None , } } # [doc = "SYSOSC16M"]
# [inline (always)]
pub fn is_sysosctrimuser_freq_sysosc16m (& self) -> bool { * self == SYSOSCTRIMUSER_FREQ_A :: SYSOSCTRIMUSER_FREQ_SYSOSC16M } # [doc = "SYSOSC24M"]
# [inline (always)]
pub fn is_sysosctrimuser_freq_sysosc24m (& self) -> bool { * self == SYSOSCTRIMUSER_FREQ_A :: SYSOSCTRIMUSER_FREQ_SYSOSC24M } } # [doc = "Field `SYSOSCTRIMUSER_FREQ` writer - FREQ specifies the target user-trimmed frequency for SYSOSC."]
pub type SYSOSCTRIMUSER_FREQ_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , SYSOSCTRIMUSER_FREQ_A > ; impl < 'a , REG , const O : u8 > SYSOSCTRIMUSER_FREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSOSC16M"]
# [inline (always)]
pub fn sysosctrimuser_freq_sysosc16m (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCTRIMUSER_FREQ_A :: SYSOSCTRIMUSER_FREQ_SYSOSC16M) } # [doc = "SYSOSC24M"]
# [inline (always)]
pub fn sysosctrimuser_freq_sysosc24m (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCTRIMUSER_FREQ_A :: SYSOSCTRIMUSER_FREQ_SYSOSC24M) } } # [doc = "Field `SYSOSCTRIMUSER_CAP` reader - CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_CAP_R = crate :: FieldReader ; # [doc = "Field `SYSOSCTRIMUSER_CAP` writer - CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_CAP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; # [doc = "Field `SYSOSCTRIMUSER_RESCOARSE` reader - RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_RESCOARSE_R = crate :: FieldReader ; # [doc = "Field `SYSOSCTRIMUSER_RESCOARSE` writer - RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_RESCOARSE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O > ; # [doc = "Field `SYSOSCTRIMUSER_RESFINE` reader - RESFINE specifies the resister fine trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_RESFINE_R = crate :: FieldReader ; # [doc = "Field `SYSOSCTRIMUSER_RESFINE` writer - RESFINE specifies the resister fine trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_RESFINE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O > ; # [doc = "Field `SYSOSCTRIMUSER_RDIV` reader - RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_RDIV_R = crate :: FieldReader < u16 > ; # [doc = "Field `SYSOSCTRIMUSER_RDIV` writer - RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."]
pub type SYSOSCTRIMUSER_RDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; impl R { # [doc = "Bits 0:1 - FREQ specifies the target user-trimmed frequency for SYSOSC."]
# [inline (always)]
pub fn sysosctrimuser_freq (& self) -> SYSOSCTRIMUSER_FREQ_R { SYSOSCTRIMUSER_FREQ_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 4:6 - CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency."]
# [inline (always)]
pub fn sysosctrimuser_cap (& self) -> SYSOSCTRIMUSER_CAP_R { SYSOSCTRIMUSER_CAP_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:13 - RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."]
# [inline (always)]
pub fn sysosctrimuser_rescoarse (& self) -> SYSOSCTRIMUSER_RESCOARSE_R { SYSOSCTRIMUSER_RESCOARSE_R :: new (((self . bits >> 8) & 0x3f) as u8) } # [doc = "Bits 16:19 - RESFINE specifies the resister fine trim. This value changes with the target frequency."]
# [inline (always)]
pub fn sysosctrimuser_resfine (& self) -> SYSOSCTRIMUSER_RESFINE_R { SYSOSCTRIMUSER_RESFINE_R :: new (((self . bits >> 16) & 0x0f) as u8) } # [doc = "Bits 20:28 - RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."]
# [inline (always)]
pub fn sysosctrimuser_rdiv (& self) -> SYSOSCTRIMUSER_RDIV_R { SYSOSCTRIMUSER_RDIV_R :: new (((self . bits >> 20) & 0x01ff) as u16) } } impl W { # [doc = "Bits 0:1 - FREQ specifies the target user-trimmed frequency for SYSOSC."]
# [inline (always)]
# [must_use]
pub fn sysosctrimuser_freq (& mut self) -> SYSOSCTRIMUSER_FREQ_W < SYSOSCTRIMUSER_SPEC , 0 > { SYSOSCTRIMUSER_FREQ_W :: new (self) } # [doc = "Bits 4:6 - CAP specifies the SYSOSC capacitor trim. This value changes with the target frequency."]
# [inline (always)]
# [must_use]
pub fn sysosctrimuser_cap (& mut self) -> SYSOSCTRIMUSER_CAP_W < SYSOSCTRIMUSER_SPEC , 4 > { SYSOSCTRIMUSER_CAP_W :: new (self) } # [doc = "Bits 8:13 - RESCOARSE specifies the resister coarse trim. This value changes with the target frequency."]
# [inline (always)]
# [must_use]
pub fn sysosctrimuser_rescoarse (& mut self) -> SYSOSCTRIMUSER_RESCOARSE_W < SYSOSCTRIMUSER_SPEC , 8 > { SYSOSCTRIMUSER_RESCOARSE_W :: new (self) } # [doc = "Bits 16:19 - RESFINE specifies the resister fine trim. This value changes with the target frequency."]
# [inline (always)]
# [must_use]
pub fn sysosctrimuser_resfine (& mut self) -> SYSOSCTRIMUSER_RESFINE_W < SYSOSCTRIMUSER_SPEC , 16 > { SYSOSCTRIMUSER_RESFINE_W :: new (self) } # [doc = "Bits 20:28 - RDIV specifies the frequency correction loop (FCL) resistor trim. This value changes with the target frequency."]
# [inline (always)]
# [must_use]
pub fn sysosctrimuser_rdiv (& mut self) -> SYSOSCTRIMUSER_RDIV_W < SYSOSCTRIMUSER_SPEC , 20 > { SYSOSCTRIMUSER_RDIV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSOSC user-specified trim\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sysosctrimuser::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysosctrimuser::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SYSOSCTRIMUSER_SPEC ; impl crate :: RegisterSpec for SYSOSCTRIMUSER_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sysosctrimuser::R`](R) reader structure"]
impl crate :: Readable for SYSOSCTRIMUSER_SPEC { } # [doc = "`write(|w| ..)` method takes [`sysosctrimuser::W`](W) writer structure"]
impl crate :: Writable for SYSOSCTRIMUSER_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SYSOSCTRIMUSER to value 0"]
impl crate :: Resettable for SYSOSCTRIMUSER_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SRAMBOUNDARY (rw) register accessor: SRAM Write Boundary\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sramboundary::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sramboundary::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sramboundary`]
module"]
pub type SRAMBOUNDARY = crate :: Reg < sramboundary :: SRAMBOUNDARY_SPEC > ; # [doc = "SRAM Write Boundary"]
pub mod sramboundary { # [doc = "Register `SRAMBOUNDARY` reader"]
pub type R = crate :: R < SRAMBOUNDARY_SPEC > ; # [doc = "Register `SRAMBOUNDARY` writer"]
pub type W = crate :: W < SRAMBOUNDARY_SPEC > ; # [doc = "Field `SRAMBOUNDARY_ADDR` reader - SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size."]
pub type SRAMBOUNDARY_ADDR_R = crate :: FieldReader < u16 > ; # [doc = "Field `SRAMBOUNDARY_ADDR` writer - SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size."]
pub type SRAMBOUNDARY_ADDR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 15 , O , u16 > ; impl R { # [doc = "Bits 5:19 - SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size."]
# [inline (always)]
pub fn sramboundary_addr (& self) -> SRAMBOUNDARY_ADDR_R { SRAMBOUNDARY_ADDR_R :: new (((self . bits >> 5) & 0x7fff) as u16) } } impl W { # [doc = "Bits 5:19 - SRAM boundary configuration. The value configured into this acts such that: SRAM accesses to addresses less than or equal value will be RW only. SRAM accesses to addresses greater than value will be RX only. Value of 0 is not valid (system will have no stack). If set to 0, the system acts as if the entire SRAM is RWX. Any non-zero value can be configured, including a value = SRAM size."]
# [inline (always)]
# [must_use]
pub fn sramboundary_addr (& mut self) -> SRAMBOUNDARY_ADDR_W < SRAMBOUNDARY_SPEC , 5 > { SRAMBOUNDARY_ADDR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SRAM Write Boundary\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sramboundary::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sramboundary::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRAMBOUNDARY_SPEC ; impl crate :: RegisterSpec for SRAMBOUNDARY_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sramboundary::R`](R) reader structure"]
impl crate :: Readable for SRAMBOUNDARY_SPEC { } # [doc = "`write(|w| ..)` method takes [`sramboundary::W`](W) writer structure"]
impl crate :: Writable for SRAMBOUNDARY_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SRAMBOUNDARY to value 0"]
impl crate :: Resettable for SRAMBOUNDARY_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SYSTEMCFG (rw) register accessor: System configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systemcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systemcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@systemcfg`]
module"]
pub type SYSTEMCFG = crate :: Reg < systemcfg :: SYSTEMCFG_SPEC > ; # [doc = "System configuration"]
pub mod systemcfg { # [doc = "Register `SYSTEMCFG` reader"]
pub type R = crate :: R < SYSTEMCFG_SPEC > ; # [doc = "Register `SYSTEMCFG` writer"]
pub type W = crate :: W < SYSTEMCFG_SPEC > ; # [doc = "Field `SYSTEMCFG_WWDTLP0RSTDIS` reader - WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI."]
pub type SYSTEMCFG_WWDTLP0RSTDIS_R = crate :: BitReader < SYSTEMCFG_WWDTLP0RSTDIS_A > ; # [doc = "WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SYSTEMCFG_WWDTLP0RSTDIS_A { # [doc = "0: FALSE"]
SYSTEMCFG_WWDTLP0RSTDIS_FALSE = 0 , # [doc = "1: TRUE"]
SYSTEMCFG_WWDTLP0RSTDIS_TRUE = 1 , } impl From < SYSTEMCFG_WWDTLP0RSTDIS_A > for bool { # [inline (always)]
fn from (variant : SYSTEMCFG_WWDTLP0RSTDIS_A) -> Self { variant as u8 != 0 } } impl SYSTEMCFG_WWDTLP0RSTDIS_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SYSTEMCFG_WWDTLP0RSTDIS_A { match self . bits { false => SYSTEMCFG_WWDTLP0RSTDIS_A :: SYSTEMCFG_WWDTLP0RSTDIS_FALSE , true => SYSTEMCFG_WWDTLP0RSTDIS_A :: SYSTEMCFG_WWDTLP0RSTDIS_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_systemcfg_wwdtlp0rstdis_false (& self) -> bool { * self == SYSTEMCFG_WWDTLP0RSTDIS_A :: SYSTEMCFG_WWDTLP0RSTDIS_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_systemcfg_wwdtlp0rstdis_true (& self) -> bool { * self == SYSTEMCFG_WWDTLP0RSTDIS_A :: SYSTEMCFG_WWDTLP0RSTDIS_TRUE } } # [doc = "Field `SYSTEMCFG_WWDTLP0RSTDIS` writer - WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI."]
pub type SYSTEMCFG_WWDTLP0RSTDIS_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSTEMCFG_WWDTLP0RSTDIS_A > ; impl < 'a , REG , const O : u8 > SYSTEMCFG_WWDTLP0RSTDIS_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FALSE"]
# [inline (always)]
pub fn systemcfg_wwdtlp0rstdis_false (self) -> & 'a mut crate :: W < REG > { self . variant (SYSTEMCFG_WWDTLP0RSTDIS_A :: SYSTEMCFG_WWDTLP0RSTDIS_FALSE) } # [doc = "TRUE"]
# [inline (always)]
pub fn systemcfg_wwdtlp0rstdis_true (self) -> & 'a mut crate :: W < REG > { self . variant (SYSTEMCFG_WWDTLP0RSTDIS_A :: SYSTEMCFG_WWDTLP0RSTDIS_TRUE) } } # [doc = "The key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SYSTEMCFG_KEY_AW { # [doc = "27: VALUE"]
SYSTEMCFG_KEY_VALUE = 27 , } impl From < SYSTEMCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : SYSTEMCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for SYSTEMCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `SYSTEMCFG_KEY` writer - The key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0"]
pub type SYSTEMCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , SYSTEMCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > SYSTEMCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn systemcfg_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (SYSTEMCFG_KEY_AW :: SYSTEMCFG_KEY_VALUE) } } impl R { # [doc = "Bit 0 - WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI."]
# [inline (always)]
pub fn systemcfg_wwdtlp0rstdis (& self) -> SYSTEMCFG_WWDTLP0RSTDIS_R { SYSTEMCFG_WWDTLP0RSTDIS_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - WWDTLP0RSTDIS specifies whether a WWDT Error Event will trigger a BOOTRST or an NMI."]
# [inline (always)]
# [must_use]
pub fn systemcfg_wwdtlp0rstdis (& mut self) -> SYSTEMCFG_WWDTLP0RSTDIS_W < SYSTEMCFG_SPEC , 0 > { SYSTEMCFG_WWDTLP0RSTDIS_W :: new (self) } # [doc = "Bits 24:31 - The key value of 1Bh (27) must be written to KEY together with contents to be updated. Reads as 0"]
# [inline (always)]
# [must_use]
pub fn systemcfg_key (& mut self) -> SYSTEMCFG_KEY_W < SYSTEMCFG_SPEC , 24 > { SYSTEMCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "System configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`systemcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`systemcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SYSTEMCFG_SPEC ; impl crate :: RegisterSpec for SYSTEMCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`systemcfg::R`](R) reader structure"]
impl crate :: Readable for SYSTEMCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`systemcfg::W`](W) writer structure"]
impl crate :: Writable for SYSTEMCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SYSTEMCFG to value 0"]
impl crate :: Resettable for SYSTEMCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "WRITELOCK (rw) register accessor: SYSCTL register write lockout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`writelock::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`writelock::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@writelock`]
module"]
pub type WRITELOCK = crate :: Reg < writelock :: WRITELOCK_SPEC > ; # [doc = "SYSCTL register write lockout"]
pub mod writelock { # [doc = "Register `WRITELOCK` reader"]
pub type R = crate :: R < WRITELOCK_SPEC > ; # [doc = "Register `WRITELOCK` writer"]
pub type W = crate :: W < WRITELOCK_SPEC > ; # [doc = "Field `WRITELOCK_ACTIVE` reader - ACTIVE controls whether critical SYSCTL registers are write protected or not."]
pub type WRITELOCK_ACTIVE_R = crate :: BitReader < WRITELOCK_ACTIVE_A > ; # [doc = "ACTIVE controls whether critical SYSCTL registers are write protected or not.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum WRITELOCK_ACTIVE_A { # [doc = "0: DISABLE"]
WRITELOCK_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"]
WRITELOCK_ACTIVE_ENABLE = 1 , } impl From < WRITELOCK_ACTIVE_A > for bool { # [inline (always)]
fn from (variant : WRITELOCK_ACTIVE_A) -> Self { variant as u8 != 0 } } impl WRITELOCK_ACTIVE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> WRITELOCK_ACTIVE_A { match self . bits { false => WRITELOCK_ACTIVE_A :: WRITELOCK_ACTIVE_DISABLE , true => WRITELOCK_ACTIVE_A :: WRITELOCK_ACTIVE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_writelock_active_disable (& self) -> bool { * self == WRITELOCK_ACTIVE_A :: WRITELOCK_ACTIVE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_writelock_active_enable (& self) -> bool { * self == WRITELOCK_ACTIVE_A :: WRITELOCK_ACTIVE_ENABLE } } # [doc = "Field `WRITELOCK_ACTIVE` writer - ACTIVE controls whether critical SYSCTL registers are write protected or not."]
pub type WRITELOCK_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , WRITELOCK_ACTIVE_A > ; impl < 'a , REG , const O : u8 > WRITELOCK_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn writelock_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (WRITELOCK_ACTIVE_A :: WRITELOCK_ACTIVE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn writelock_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (WRITELOCK_ACTIVE_A :: WRITELOCK_ACTIVE_ENABLE) } } impl R { # [doc = "Bit 0 - ACTIVE controls whether critical SYSCTL registers are write protected or not."]
# [inline (always)]
pub fn writelock_active (& self) -> WRITELOCK_ACTIVE_R { WRITELOCK_ACTIVE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - ACTIVE controls whether critical SYSCTL registers are write protected or not."]
# [inline (always)]
# [must_use]
pub fn writelock_active (& mut self) -> WRITELOCK_ACTIVE_W < WRITELOCK_SPEC , 0 > { WRITELOCK_ACTIVE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSCTL register write lockout\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`writelock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`writelock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WRITELOCK_SPEC ; impl crate :: RegisterSpec for WRITELOCK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`writelock::R`](R) reader structure"]
impl crate :: Readable for WRITELOCK_SPEC { } # [doc = "`write(|w| ..)` method takes [`writelock::W`](W) writer structure"]
impl crate :: Writable for WRITELOCK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WRITELOCK to value 0"]
impl crate :: Resettable for WRITELOCK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCAUSE (r) register accessor: Reset cause\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstcause::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstcause`]
module"]
pub type RSTCAUSE = crate :: Reg < rstcause :: RSTCAUSE_SPEC > ; # [doc = "Reset cause"]
pub mod rstcause { # [doc = "Register `RSTCAUSE` reader"]
pub type R = crate :: R < RSTCAUSE_SPEC > ; # [doc = "Field `RSTCAUSE_ID` reader - ID is a read-to-clear field which indicates the lowest level reset cause since the last read."]
pub type RSTCAUSE_ID_R = crate :: FieldReader < RSTCAUSE_ID_A > ; # [doc = "ID is a read-to-clear field which indicates the lowest level reset cause since the last read.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCAUSE_ID_A { # [doc = "0: NORST"]
RSTCAUSE_ID_NORST = 0 , # [doc = "1: PORHWFAIL"]
RSTCAUSE_ID_PORHWFAIL = 1 , # [doc = "2: POREXNRST"]
RSTCAUSE_ID_POREXNRST = 2 , # [doc = "3: PORSW"]
RSTCAUSE_ID_PORSW = 3 , # [doc = "4: BORSUPPLY"]
RSTCAUSE_ID_BORSUPPLY = 4 , # [doc = "5: BORWAKESHUTDN"]
RSTCAUSE_ID_BORWAKESHUTDN = 5 , # [doc = "8: BOOTNONPMUPARITY"]
RSTCAUSE_ID_BOOTNONPMUPARITY = 8 , # [doc = "9: BOOTCLKFAIL"]
RSTCAUSE_ID_BOOTCLKFAIL = 9 , # [doc = "12: BOOTEXNRST"]
RSTCAUSE_ID_BOOTEXNRST = 12 , # [doc = "13: BOOTSW"]
RSTCAUSE_ID_BOOTSW = 13 , # [doc = "14: SYSWWDT0"]
RSTCAUSE_ID_SYSWWDT0 = 14 , # [doc = "16: SYSBSLEXIT"]
RSTCAUSE_ID_SYSBSLEXIT = 16 , # [doc = "17: SYSBSLENTRY"]
RSTCAUSE_ID_SYSBSLENTRY = 17 , # [doc = "19: SYSWWDT1"]
RSTCAUSE_ID_SYSWWDT1 = 19 , # [doc = "20: SYSFLASHECC"]
RSTCAUSE_ID_SYSFLASHECC = 20 , # [doc = "21: SYSCPULOCK"]
RSTCAUSE_ID_SYSCPULOCK = 21 , # [doc = "26: SYSDBG"]
RSTCAUSE_ID_SYSDBG = 26 , # [doc = "27: SYSSW"]
RSTCAUSE_ID_SYSSW = 27 , # [doc = "28: CPUDBG"]
RSTCAUSE_ID_CPUDBG = 28 , # [doc = "29: CPUSW"]
RSTCAUSE_ID_CPUSW = 29 , } impl From < RSTCAUSE_ID_A > for u8 { # [inline (always)]
fn from (variant : RSTCAUSE_ID_A) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCAUSE_ID_A { type Ux = u8 ; } impl RSTCAUSE_ID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < RSTCAUSE_ID_A > { match self . bits { 0 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_NORST) , 1 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_PORHWFAIL) , 2 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_POREXNRST) , 3 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_PORSW) , 4 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_BORSUPPLY) , 5 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_BORWAKESHUTDN) , 8 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTNONPMUPARITY) , 9 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTCLKFAIL) , 12 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTEXNRST) , 13 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTSW) , 14 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSWWDT0) , 16 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSBSLEXIT) , 17 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSBSLENTRY) , 19 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSWWDT1) , 20 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSFLASHECC) , 21 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSCPULOCK) , 26 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSDBG) , 27 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSSW) , 28 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_CPUDBG) , 29 => Some (RSTCAUSE_ID_A :: RSTCAUSE_ID_CPUSW) , _ => None , } } # [doc = "NORST"]
# [inline (always)]
pub fn is_rstcause_id_norst (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_NORST } # [doc = "PORHWFAIL"]
# [inline (always)]
pub fn is_rstcause_id_porhwfail (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_PORHWFAIL } # [doc = "POREXNRST"]
# [inline (always)]
pub fn is_rstcause_id_porexnrst (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_POREXNRST } # [doc = "PORSW"]
# [inline (always)]
pub fn is_rstcause_id_porsw (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_PORSW } # [doc = "BORSUPPLY"]
# [inline (always)]
pub fn is_rstcause_id_borsupply (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_BORSUPPLY } # [doc = "BORWAKESHUTDN"]
# [inline (always)]
pub fn is_rstcause_id_borwakeshutdn (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_BORWAKESHUTDN } # [doc = "BOOTNONPMUPARITY"]
# [inline (always)]
pub fn is_rstcause_id_bootnonpmuparity (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTNONPMUPARITY } # [doc = "BOOTCLKFAIL"]
# [inline (always)]
pub fn is_rstcause_id_bootclkfail (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTCLKFAIL } # [doc = "BOOTEXNRST"]
# [inline (always)]
pub fn is_rstcause_id_bootexnrst (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTEXNRST } # [doc = "BOOTSW"]
# [inline (always)]
pub fn is_rstcause_id_bootsw (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_BOOTSW } # [doc = "SYSWWDT0"]
# [inline (always)]
pub fn is_rstcause_id_syswwdt0 (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSWWDT0 } # [doc = "SYSBSLEXIT"]
# [inline (always)]
pub fn is_rstcause_id_sysbslexit (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSBSLEXIT } # [doc = "SYSBSLENTRY"]
# [inline (always)]
pub fn is_rstcause_id_sysbslentry (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSBSLENTRY } # [doc = "SYSWWDT1"]
# [inline (always)]
pub fn is_rstcause_id_syswwdt1 (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSWWDT1 } # [doc = "SYSFLASHECC"]
# [inline (always)]
pub fn is_rstcause_id_sysflashecc (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSFLASHECC } # [doc = "SYSCPULOCK"]
# [inline (always)]
pub fn is_rstcause_id_syscpulock (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSCPULOCK } # [doc = "SYSDBG"]
# [inline (always)]
pub fn is_rstcause_id_sysdbg (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSDBG } # [doc = "SYSSW"]
# [inline (always)]
pub fn is_rstcause_id_syssw (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_SYSSW } # [doc = "CPUDBG"]
# [inline (always)]
pub fn is_rstcause_id_cpudbg (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_CPUDBG } # [doc = "CPUSW"]
# [inline (always)]
pub fn is_rstcause_id_cpusw (& self) -> bool { * self == RSTCAUSE_ID_A :: RSTCAUSE_ID_CPUSW } } impl R { # [doc = "Bits 0:4 - ID is a read-to-clear field which indicates the lowest level reset cause since the last read."]
# [inline (always)]
pub fn rstcause_id (& self) -> RSTCAUSE_ID_R { RSTCAUSE_ID_R :: new ((self . bits & 0x1f) as u8) } } # [doc = "Reset cause\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rstcause::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCAUSE_SPEC ; impl crate :: RegisterSpec for RSTCAUSE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`rstcause::R`](R) reader structure"]
impl crate :: Readable for RSTCAUSE_SPEC { } # [doc = "`reset()` method sets RSTCAUSE to value 0"]
impl crate :: Resettable for RSTCAUSE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RESETLEVEL (rw) register accessor: Reset level for application-triggered reset command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resetlevel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resetlevel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resetlevel`]
module"]
pub type RESETLEVEL = crate :: Reg < resetlevel :: RESETLEVEL_SPEC > ; # [doc = "Reset level for application-triggered reset command"]
pub mod resetlevel { # [doc = "Register `RESETLEVEL` reader"]
pub type R = crate :: R < RESETLEVEL_SPEC > ; # [doc = "Register `RESETLEVEL` writer"]
pub type W = crate :: W < RESETLEVEL_SPEC > ; # [doc = "Field `RESETLEVEL_LEVEL` reader - LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset."]
pub type RESETLEVEL_LEVEL_R = crate :: FieldReader < RESETLEVEL_LEVEL_A > ; # [doc = "LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RESETLEVEL_LEVEL_A { # [doc = "0: CPU"]
RESETLEVEL_LEVEL_CPU = 0 , # [doc = "1: BOOT"]
RESETLEVEL_LEVEL_BOOT = 1 , # [doc = "2: BOOTLOADERENTRY"]
RESETLEVEL_LEVEL_BOOTLOADERENTRY = 2 , # [doc = "3: POR"]
RESETLEVEL_LEVEL_POR = 3 , # [doc = "4: BOOTLOADEREXIT"]
RESETLEVEL_LEVEL_BOOTLOADEREXIT = 4 , } impl From < RESETLEVEL_LEVEL_A > for u8 { # [inline (always)]
fn from (variant : RESETLEVEL_LEVEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for RESETLEVEL_LEVEL_A { type Ux = u8 ; } impl RESETLEVEL_LEVEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < RESETLEVEL_LEVEL_A > { match self . bits { 0 => Some (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_CPU) , 1 => Some (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOT) , 2 => Some (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOTLOADERENTRY) , 3 => Some (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_POR) , 4 => Some (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOTLOADEREXIT) , _ => None , } } # [doc = "CPU"]
# [inline (always)]
pub fn is_resetlevel_level_cpu (& self) -> bool { * self == RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_CPU } # [doc = "BOOT"]
# [inline (always)]
pub fn is_resetlevel_level_boot (& self) -> bool { * self == RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOT } # [doc = "BOOTLOADERENTRY"]
# [inline (always)]
pub fn is_resetlevel_level_bootloaderentry (& self) -> bool { * self == RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOTLOADERENTRY } # [doc = "POR"]
# [inline (always)]
pub fn is_resetlevel_level_por (& self) -> bool { * self == RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_POR } # [doc = "BOOTLOADEREXIT"]
# [inline (always)]
pub fn is_resetlevel_level_bootloaderexit (& self) -> bool { * self == RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOTLOADEREXIT } } # [doc = "Field `RESETLEVEL_LEVEL` writer - LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset."]
pub type RESETLEVEL_LEVEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , RESETLEVEL_LEVEL_A > ; impl < 'a , REG , const O : u8 > RESETLEVEL_LEVEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CPU"]
# [inline (always)]
pub fn resetlevel_level_cpu (self) -> & 'a mut crate :: W < REG > { self . variant (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_CPU) } # [doc = "BOOT"]
# [inline (always)]
pub fn resetlevel_level_boot (self) -> & 'a mut crate :: W < REG > { self . variant (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOT) } # [doc = "BOOTLOADERENTRY"]
# [inline (always)]
pub fn resetlevel_level_bootloaderentry (self) -> & 'a mut crate :: W < REG > { self . variant (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOTLOADERENTRY) } # [doc = "POR"]
# [inline (always)]
pub fn resetlevel_level_por (self) -> & 'a mut crate :: W < REG > { self . variant (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_POR) } # [doc = "BOOTLOADEREXIT"]
# [inline (always)]
pub fn resetlevel_level_bootloaderexit (self) -> & 'a mut crate :: W < REG > { self . variant (RESETLEVEL_LEVEL_A :: RESETLEVEL_LEVEL_BOOTLOADEREXIT) } } impl R { # [doc = "Bits 0:2 - LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset."]
# [inline (always)]
pub fn resetlevel_level (& self) -> RESETLEVEL_LEVEL_R { RESETLEVEL_LEVEL_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - LEVEL is used to specify the type of reset to be issued when RESETCMD is set to generate a software triggered reset."]
# [inline (always)]
# [must_use]
pub fn resetlevel_level (& mut self) -> RESETLEVEL_LEVEL_W < RESETLEVEL_SPEC , 0 > { RESETLEVEL_LEVEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset level for application-triggered reset command\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`resetlevel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resetlevel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RESETLEVEL_SPEC ; impl crate :: RegisterSpec for RESETLEVEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`resetlevel::R`](R) reader structure"]
impl crate :: Readable for RESETLEVEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`resetlevel::W`](W) writer structure"]
impl crate :: Writable for RESETLEVEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RESETLEVEL to value 0"]
impl crate :: Resettable for RESETLEVEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RESETCMD (w) register accessor: Execute an application-triggered reset command\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resetcmd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@resetcmd`]
module"]
pub type RESETCMD = crate :: Reg < resetcmd :: RESETCMD_SPEC > ; # [doc = "Execute an application-triggered reset command"]
pub mod resetcmd { # [doc = "Register `RESETCMD` writer"]
pub type W = crate :: W < RESETCMD_SPEC > ; # [doc = "Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RESETCMD_GO_AW { # [doc = "1: TRUE"]
RESETCMD_GO_TRUE = 1 , } impl From < RESETCMD_GO_AW > for bool { # [inline (always)]
fn from (variant : RESETCMD_GO_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RESETCMD_GO` writer - Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY."]
pub type RESETCMD_GO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RESETCMD_GO_AW > ; impl < 'a , REG , const O : u8 > RESETCMD_GO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRUE"]
# [inline (always)]
pub fn resetcmd_go_true (self) -> & 'a mut crate :: W < REG > { self . variant (RESETCMD_GO_AW :: RESETCMD_GO_TRUE) } } # [doc = "The key value of E4h (228) must be written to KEY together with GO to trigger the reset.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RESETCMD_KEY_AW { # [doc = "228: VALUE"]
RESETCMD_KEY_VALUE = 228 , } impl From < RESETCMD_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RESETCMD_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RESETCMD_KEY_AW { type Ux = u8 ; } # [doc = "Field `RESETCMD_KEY` writer - The key value of E4h (228) must be written to KEY together with GO to trigger the reset."]
pub type RESETCMD_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RESETCMD_KEY_AW > ; impl < 'a , REG , const O : u8 > RESETCMD_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn resetcmd_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (RESETCMD_KEY_AW :: RESETCMD_KEY_VALUE) } } impl W { # [doc = "Bit 0 - Execute the reset specified in RESETLEVEL.LEVEL. Must be written together with the KEY."]
# [inline (always)]
# [must_use]
pub fn resetcmd_go (& mut self) -> RESETCMD_GO_W < RESETCMD_SPEC , 0 > { RESETCMD_GO_W :: new (self) } # [doc = "Bits 24:31 - The key value of E4h (228) must be written to KEY together with GO to trigger the reset."]
# [inline (always)]
# [must_use]
pub fn resetcmd_key (& mut self) -> RESETCMD_KEY_W < RESETCMD_SPEC , 24 > { RESETCMD_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Execute an application-triggered reset command\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`resetcmd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RESETCMD_SPEC ; impl crate :: RegisterSpec for RESETCMD_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`resetcmd::W`](W) writer structure"]
impl crate :: Writable for RESETCMD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RESETCMD to value 0"]
impl crate :: Resettable for RESETCMD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "BORTHRESHOLD (rw) register accessor: BOR threshold selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`borthreshold::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`borthreshold::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@borthreshold`]
module"]
pub type BORTHRESHOLD = crate :: Reg < borthreshold :: BORTHRESHOLD_SPEC > ; # [doc = "BOR threshold selection"]
pub mod borthreshold { # [doc = "Register `BORTHRESHOLD` reader"]
pub type R = crate :: R < BORTHRESHOLD_SPEC > ; # [doc = "Register `BORTHRESHOLD` writer"]
pub type W = crate :: W < BORTHRESHOLD_SPEC > ; # [doc = "Field `BORTHRESHOLD_LEVEL` reader - LEVEL specifies the desired BOR threshold and BOR mode."]
pub type BORTHRESHOLD_LEVEL_R = crate :: FieldReader < BORTHRESHOLD_LEVEL_A > ; # [doc = "LEVEL specifies the desired BOR threshold and BOR mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum BORTHRESHOLD_LEVEL_A { # [doc = "0: BORMIN"]
BORTHRESHOLD_LEVEL_BORMIN = 0 , # [doc = "1: BORLEVEL1"]
BORTHRESHOLD_LEVEL_BORLEVEL1 = 1 , # [doc = "2: BORLEVEL2"]
BORTHRESHOLD_LEVEL_BORLEVEL2 = 2 , # [doc = "3: BORLEVEL3"]
BORTHRESHOLD_LEVEL_BORLEVEL3 = 3 , } impl From < BORTHRESHOLD_LEVEL_A > for u8 { # [inline (always)]
fn from (variant : BORTHRESHOLD_LEVEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for BORTHRESHOLD_LEVEL_A { type Ux = u8 ; } impl BORTHRESHOLD_LEVEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> BORTHRESHOLD_LEVEL_A { match self . bits { 0 => BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORMIN , 1 => BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL1 , 2 => BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL2 , 3 => BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL3 , _ => unreachable ! () , } } # [doc = "BORMIN"]
# [inline (always)]
pub fn is_borthreshold_level_bormin (& self) -> bool { * self == BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORMIN } # [doc = "BORLEVEL1"]
# [inline (always)]
pub fn is_borthreshold_level_borlevel1 (& self) -> bool { * self == BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL1 } # [doc = "BORLEVEL2"]
# [inline (always)]
pub fn is_borthreshold_level_borlevel2 (& self) -> bool { * self == BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL2 } # [doc = "BORLEVEL3"]
# [inline (always)]
pub fn is_borthreshold_level_borlevel3 (& self) -> bool { * self == BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL3 } } # [doc = "Field `BORTHRESHOLD_LEVEL` writer - LEVEL specifies the desired BOR threshold and BOR mode."]
pub type BORTHRESHOLD_LEVEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , BORTHRESHOLD_LEVEL_A > ; impl < 'a , REG , const O : u8 > BORTHRESHOLD_LEVEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "BORMIN"]
# [inline (always)]
pub fn borthreshold_level_bormin (self) -> & 'a mut crate :: W < REG > { self . variant (BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORMIN) } # [doc = "BORLEVEL1"]
# [inline (always)]
pub fn borthreshold_level_borlevel1 (self) -> & 'a mut crate :: W < REG > { self . variant (BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL1) } # [doc = "BORLEVEL2"]
# [inline (always)]
pub fn borthreshold_level_borlevel2 (self) -> & 'a mut crate :: W < REG > { self . variant (BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL2) } # [doc = "BORLEVEL3"]
# [inline (always)]
pub fn borthreshold_level_borlevel3 (self) -> & 'a mut crate :: W < REG > { self . variant (BORTHRESHOLD_LEVEL_A :: BORTHRESHOLD_LEVEL_BORLEVEL3) } } impl R { # [doc = "Bits 0:1 - LEVEL specifies the desired BOR threshold and BOR mode."]
# [inline (always)]
pub fn borthreshold_level (& self) -> BORTHRESHOLD_LEVEL_R { BORTHRESHOLD_LEVEL_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - LEVEL specifies the desired BOR threshold and BOR mode."]
# [inline (always)]
# [must_use]
pub fn borthreshold_level (& mut self) -> BORTHRESHOLD_LEVEL_W < BORTHRESHOLD_SPEC , 0 > { BORTHRESHOLD_LEVEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "BOR threshold selection\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`borthreshold::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`borthreshold::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BORTHRESHOLD_SPEC ; impl crate :: RegisterSpec for BORTHRESHOLD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`borthreshold::R`](R) reader structure"]
impl crate :: Readable for BORTHRESHOLD_SPEC { } # [doc = "`write(|w| ..)` method takes [`borthreshold::W`](W) writer structure"]
impl crate :: Writable for BORTHRESHOLD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets BORTHRESHOLD to value 0"]
impl crate :: Resettable for BORTHRESHOLD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "BORCLRCMD (w) register accessor: Set the BOR threshold\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`borclrcmd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@borclrcmd`]
module"]
pub type BORCLRCMD = crate :: Reg < borclrcmd :: BORCLRCMD_SPEC > ; # [doc = "Set the BOR threshold"]
pub mod borclrcmd { # [doc = "Register `BORCLRCMD` writer"]
pub type W = crate :: W < BORCLRCMD_SPEC > ; # [doc = "GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum BORCLRCMD_GO_AW { # [doc = "1: TRUE"]
BORCLRCMD_GO_TRUE = 1 , } impl From < BORCLRCMD_GO_AW > for bool { # [inline (always)]
fn from (variant : BORCLRCMD_GO_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `BORCLRCMD_GO` writer - GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register."]
pub type BORCLRCMD_GO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , BORCLRCMD_GO_AW > ; impl < 'a , REG , const O : u8 > BORCLRCMD_GO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRUE"]
# [inline (always)]
pub fn borclrcmd_go_true (self) -> & 'a mut crate :: W < REG > { self . variant (BORCLRCMD_GO_AW :: BORCLRCMD_GO_TRUE) } } # [doc = "The key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum BORCLRCMD_KEY_AW { # [doc = "199: VALUE"]
BORCLRCMD_KEY_VALUE = 199 , } impl From < BORCLRCMD_KEY_AW > for u8 { # [inline (always)]
fn from (variant : BORCLRCMD_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for BORCLRCMD_KEY_AW { type Ux = u8 ; } # [doc = "Field `BORCLRCMD_KEY` writer - The key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change."]
pub type BORCLRCMD_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , BORCLRCMD_KEY_AW > ; impl < 'a , REG , const O : u8 > BORCLRCMD_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn borclrcmd_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (BORCLRCMD_KEY_AW :: BORCLRCMD_KEY_VALUE) } } impl W { # [doc = "Bit 0 - GO clears any prior BOR violation status indications and attempts to change the active BOR mode to that specified in the LEVEL field of the BORTHRESHOLD register."]
# [inline (always)]
# [must_use]
pub fn borclrcmd_go (& mut self) -> BORCLRCMD_GO_W < BORCLRCMD_SPEC , 0 > { BORCLRCMD_GO_W :: new (self) } # [doc = "Bits 24:31 - The key value of C7h (199) must be written to KEY together with GO to trigger the clear and BOR threshold change."]
# [inline (always)]
# [must_use]
pub fn borclrcmd_key (& mut self) -> BORCLRCMD_KEY_W < BORCLRCMD_SPEC , 24 > { BORCLRCMD_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Set the BOR threshold\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`borclrcmd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct BORCLRCMD_SPEC ; impl crate :: RegisterSpec for BORCLRCMD_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`borclrcmd::W`](W) writer structure"]
impl crate :: Writable for BORCLRCMD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets BORCLRCMD to value 0"]
impl crate :: Resettable for BORCLRCMD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SYSOSCFCLCTL (w) register accessor: SYSOSC frequency correction loop (FCL) ROSC enable\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysoscfclctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sysoscfclctl`]
module"]
pub type SYSOSCFCLCTL = crate :: Reg < sysoscfclctl :: SYSOSCFCLCTL_SPEC > ; # [doc = "SYSOSC frequency correction loop (FCL) ROSC enable"]
pub mod sysoscfclctl { # [doc = "Register `SYSOSCFCLCTL` writer"]
pub type W = crate :: W < SYSOSCFCLCTL_SPEC > ; # [doc = "Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SYSOSCFCLCTL_SETUSEFCL_AW { # [doc = "1: TRUE"]
SYSOSCFCLCTL_SETUSEFCL_TRUE = 1 , } impl From < SYSOSCFCLCTL_SETUSEFCL_AW > for bool { # [inline (always)]
fn from (variant : SYSOSCFCLCTL_SETUSEFCL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `SYSOSCFCLCTL_SETUSEFCL` writer - Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST."]
pub type SYSOSCFCLCTL_SETUSEFCL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SYSOSCFCLCTL_SETUSEFCL_AW > ; impl < 'a , REG , const O : u8 > SYSOSCFCLCTL_SETUSEFCL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRUE"]
# [inline (always)]
pub fn sysoscfclctl_setusefcl_true (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCFCLCTL_SETUSEFCL_AW :: SYSOSCFCLCTL_SETUSEFCL_TRUE) } } # [doc = "The key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SYSOSCFCLCTL_KEY_AW { # [doc = "42: VALUE"]
SYSOSCFCLCTL_KEY_VALUE = 42 , } impl From < SYSOSCFCLCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : SYSOSCFCLCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for SYSOSCFCLCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `SYSOSCFCLCTL_KEY` writer - The key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL."]
pub type SYSOSCFCLCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , SYSOSCFCLCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > SYSOSCFCLCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn sysoscfclctl_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (SYSOSCFCLCTL_KEY_AW :: SYSOSCFCLCTL_KEY_VALUE) } } impl W { # [doc = "Bit 0 - Set SETUSEFCL to enable the frequency correction loop in SYSOSC. Once enabled, this state is locked until the next BOOTRST."]
# [inline (always)]
# [must_use]
pub fn sysoscfclctl_setusefcl (& mut self) -> SYSOSCFCLCTL_SETUSEFCL_W < SYSOSCFCLCTL_SPEC , 0 > { SYSOSCFCLCTL_SETUSEFCL_W :: new (self) } # [doc = "Bits 24:31 - The key value of 2Ah (42) must be written to KEY together with SETUSEFCL to enable the FCL."]
# [inline (always)]
# [must_use]
pub fn sysoscfclctl_key (& mut self) -> SYSOSCFCLCTL_KEY_W < SYSOSCFCLCTL_SPEC , 24 > { SYSOSCFCLCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SYSOSC frequency correction loop (FCL) ROSC enable\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sysoscfclctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SYSOSCFCLCTL_SPEC ; impl crate :: RegisterSpec for SYSOSCFCLCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`sysoscfclctl::W`](W) writer structure"]
impl crate :: Writable for SYSOSCFCLCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SYSOSCFCLCTL to value 0"]
impl crate :: Resettable for SYSOSCFCLCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SHDNIOREL (w) register accessor: SHUTDOWN IO release control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shdniorel::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shdniorel`]
module"]
pub type SHDNIOREL = crate :: Reg < shdniorel :: SHDNIOREL_SPEC > ; # [doc = "SHUTDOWN IO release control"]
pub mod shdniorel { # [doc = "Register `SHDNIOREL` writer"]
pub type W = crate :: W < SHDNIOREL_SPEC > ; # [doc = "Set RELEASE to release the IO after a SHUTDOWN mode exit.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SHDNIOREL_RELEASE_AW { # [doc = "1: TRUE"]
SHDNIOREL_RELEASE_TRUE = 1 , } impl From < SHDNIOREL_RELEASE_AW > for bool { # [inline (always)]
fn from (variant : SHDNIOREL_RELEASE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `SHDNIOREL_RELEASE` writer - Set RELEASE to release the IO after a SHUTDOWN mode exit."]
pub type SHDNIOREL_RELEASE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SHDNIOREL_RELEASE_AW > ; impl < 'a , REG , const O : u8 > SHDNIOREL_RELEASE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRUE"]
# [inline (always)]
pub fn shdniorel_release_true (self) -> & 'a mut crate :: W < REG > { self . variant (SHDNIOREL_RELEASE_AW :: SHDNIOREL_RELEASE_TRUE) } } # [doc = "The key value 91h must be written to KEY together with RELEASE to set RELEASE.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SHDNIOREL_KEY_AW { # [doc = "145: VALUE"]
SHDNIOREL_KEY_VALUE = 145 , } impl From < SHDNIOREL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : SHDNIOREL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for SHDNIOREL_KEY_AW { type Ux = u8 ; } # [doc = "Field `SHDNIOREL_KEY` writer - The key value 91h must be written to KEY together with RELEASE to set RELEASE."]
pub type SHDNIOREL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , SHDNIOREL_KEY_AW > ; impl < 'a , REG , const O : u8 > SHDNIOREL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn shdniorel_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (SHDNIOREL_KEY_AW :: SHDNIOREL_KEY_VALUE) } } impl W { # [doc = "Bit 0 - Set RELEASE to release the IO after a SHUTDOWN mode exit."]
# [inline (always)]
# [must_use]
pub fn shdniorel_release (& mut self) -> SHDNIOREL_RELEASE_W < SHDNIOREL_SPEC , 0 > { SHDNIOREL_RELEASE_W :: new (self) } # [doc = "Bits 24:31 - The key value 91h must be written to KEY together with RELEASE to set RELEASE."]
# [inline (always)]
# [must_use]
pub fn shdniorel_key (& mut self) -> SHDNIOREL_KEY_W < SHDNIOREL_SPEC , 24 > { SHDNIOREL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "SHUTDOWN IO release control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shdniorel::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SHDNIOREL_SPEC ; impl crate :: RegisterSpec for SHDNIOREL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`shdniorel::W`](W) writer structure"]
impl crate :: Writable for SHDNIOREL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SHDNIOREL to value 0"]
impl crate :: Resettable for SHDNIOREL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EXRSTPIN (w) register accessor: Disable the reset function of the NRST pin\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrstpin::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@exrstpin`]
module"]
pub type EXRSTPIN = crate :: Reg < exrstpin :: EXRSTPIN_SPEC > ; # [doc = "Disable the reset function of the NRST pin"]
pub mod exrstpin { # [doc = "Register `EXRSTPIN` writer"]
pub type W = crate :: W < EXRSTPIN_SPEC > ; # [doc = "Set DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum EXRSTPIN_DISABLE_AW { # [doc = "0: FALSE"]
EXRSTPIN_DISABLE_FALSE = 0 , # [doc = "1: TRUE"]
EXRSTPIN_DISABLE_TRUE = 1 , } impl From < EXRSTPIN_DISABLE_AW > for bool { # [inline (always)]
fn from (variant : EXRSTPIN_DISABLE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `EXRSTPIN_DISABLE` writer - Set DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR."]
pub type EXRSTPIN_DISABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , EXRSTPIN_DISABLE_AW > ; impl < 'a , REG , const O : u8 > EXRSTPIN_DISABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FALSE"]
# [inline (always)]
pub fn exrstpin_disable_false (self) -> & 'a mut crate :: W < REG > { self . variant (EXRSTPIN_DISABLE_AW :: EXRSTPIN_DISABLE_FALSE) } # [doc = "TRUE"]
# [inline (always)]
pub fn exrstpin_disable_true (self) -> & 'a mut crate :: W < REG > { self . variant (EXRSTPIN_DISABLE_AW :: EXRSTPIN_DISABLE_TRUE) } } # [doc = "The key value 1Eh must be written together with DISABLE to disable the reset function.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EXRSTPIN_KEY_AW { # [doc = "30: VALUE"]
EXRSTPIN_KEY_VALUE = 30 , } impl From < EXRSTPIN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : EXRSTPIN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for EXRSTPIN_KEY_AW { type Ux = u8 ; } # [doc = "Field `EXRSTPIN_KEY` writer - The key value 1Eh must be written together with DISABLE to disable the reset function."]
pub type EXRSTPIN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , EXRSTPIN_KEY_AW > ; impl < 'a , REG , const O : u8 > EXRSTPIN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn exrstpin_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (EXRSTPIN_KEY_AW :: EXRSTPIN_KEY_VALUE) } } impl W { # [doc = "Bit 0 - Set DISABLE to disable the reset function of the NRST pin. Once set, this configuration is locked until the next POR."]
# [inline (always)]
# [must_use]
pub fn exrstpin_disable (& mut self) -> EXRSTPIN_DISABLE_W < EXRSTPIN_SPEC , 0 > { EXRSTPIN_DISABLE_W :: new (self) } # [doc = "Bits 24:31 - The key value 1Eh must be written together with DISABLE to disable the reset function."]
# [inline (always)]
# [must_use]
pub fn exrstpin_key (& mut self) -> EXRSTPIN_KEY_W < EXRSTPIN_SPEC , 24 > { EXRSTPIN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Disable the reset function of the NRST pin\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`exrstpin::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EXRSTPIN_SPEC ; impl crate :: RegisterSpec for EXRSTPIN_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`exrstpin::W`](W) writer structure"]
impl crate :: Writable for EXRSTPIN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EXRSTPIN to value 0"]
impl crate :: Resettable for EXRSTPIN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SWDCFG (w) register accessor: Disable the SWD function on the SWD pins\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swdcfg::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swdcfg`]
module"]
pub type SWDCFG = crate :: Reg < swdcfg :: SWDCFG_SPEC > ; # [doc = "Disable the SWD function on the SWD pins"]
pub mod swdcfg { # [doc = "Register `SWDCFG` writer"]
pub type W = crate :: W < SWDCFG_SPEC > ; # [doc = "Set DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SWDCFG_DISABLE_AW { # [doc = "1: TRUE"]
SWDCFG_DISABLE_TRUE = 1 , } impl From < SWDCFG_DISABLE_AW > for bool { # [inline (always)]
fn from (variant : SWDCFG_DISABLE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `SWDCFG_DISABLE` writer - Set DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO."]
pub type SWDCFG_DISABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SWDCFG_DISABLE_AW > ; impl < 'a , REG , const O : u8 > SWDCFG_DISABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRUE"]
# [inline (always)]
pub fn swdcfg_disable_true (self) -> & 'a mut crate :: W < REG > { self . variant (SWDCFG_DISABLE_AW :: SWDCFG_DISABLE_TRUE) } } # [doc = "The key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SWDCFG_KEY_AW { # [doc = "98: VALUE"]
SWDCFG_KEY_VALUE = 98 , } impl From < SWDCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : SWDCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for SWDCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `SWDCFG_KEY` writer - The key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions."]
pub type SWDCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , SWDCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > SWDCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn swdcfg_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (SWDCFG_KEY_AW :: SWDCFG_KEY_VALUE) } } impl W { # [doc = "Bit 0 - Set DISABLE to disable the SWD function on SWD pins, allowing the SWD pins to be used as GPIO."]
# [inline (always)]
# [must_use]
pub fn swdcfg_disable (& mut self) -> SWDCFG_DISABLE_W < SWDCFG_SPEC , 0 > { SWDCFG_DISABLE_W :: new (self) } # [doc = "Bits 24:31 - The key value 62h (98) must be written to KEY together with DISBALE to disable the SWD functions."]
# [inline (always)]
# [must_use]
pub fn swdcfg_key (& mut self) -> SWDCFG_KEY_W < SWDCFG_SPEC , 24 > { SWDCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Disable the SWD function on the SWD pins\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`swdcfg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SWDCFG_SPEC ; impl crate :: RegisterSpec for SWDCFG_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`swdcfg::W`](W) writer structure"]
impl crate :: Writable for SWDCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SWDCFG to value 0"]
impl crate :: Resettable for SWDCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FCCCMD (w) register accessor: Frequency clock counter start capture\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcccmd::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fcccmd`]
module"]
pub type FCCCMD = crate :: Reg < fcccmd :: FCCCMD_SPEC > ; # [doc = "Frequency clock counter start capture"]
pub mod fcccmd { # [doc = "Register `FCCCMD` writer"]
pub type W = crate :: W < FCCCMD_SPEC > ; # [doc = "Set GO to start a capture with the frequency clock counter (FCC).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum FCCCMD_GO_AW { # [doc = "1: TRUE"]
FCCCMD_GO_TRUE = 1 , } impl From < FCCCMD_GO_AW > for bool { # [inline (always)]
fn from (variant : FCCCMD_GO_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `FCCCMD_GO` writer - Set GO to start a capture with the frequency clock counter (FCC)."]
pub type FCCCMD_GO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , FCCCMD_GO_AW > ; impl < 'a , REG , const O : u8 > FCCCMD_GO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRUE"]
# [inline (always)]
pub fn fcccmd_go_true (self) -> & 'a mut crate :: W < REG > { self . variant (FCCCMD_GO_AW :: FCCCMD_GO_TRUE) } } # [doc = "The key value 0Eh (14) must be written with GO to start a capture.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FCCCMD_KEY_AW { # [doc = "14: VALUE"]
FCCCMD_KEY_VALUE = 14 , } impl From < FCCCMD_KEY_AW > for u8 { # [inline (always)]
fn from (variant : FCCCMD_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for FCCCMD_KEY_AW { type Ux = u8 ; } # [doc = "Field `FCCCMD_KEY` writer - The key value 0Eh (14) must be written with GO to start a capture."]
pub type FCCCMD_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , FCCCMD_KEY_AW > ; impl < 'a , REG , const O : u8 > FCCCMD_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VALUE"]
# [inline (always)]
pub fn fcccmd_key_value (self) -> & 'a mut crate :: W < REG > { self . variant (FCCCMD_KEY_AW :: FCCCMD_KEY_VALUE) } } impl W { # [doc = "Bit 0 - Set GO to start a capture with the frequency clock counter (FCC)."]
# [inline (always)]
# [must_use]
pub fn fcccmd_go (& mut self) -> FCCCMD_GO_W < FCCCMD_SPEC , 0 > { FCCCMD_GO_W :: new (self) } # [doc = "Bits 24:31 - The key value 0Eh (14) must be written with GO to start a capture."]
# [inline (always)]
# [must_use]
pub fn fcccmd_key (& mut self) -> FCCCMD_KEY_W < FCCCMD_SPEC , 24 > { FCCCMD_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Frequency clock counter start capture\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcccmd::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FCCCMD_SPEC ; impl crate :: RegisterSpec for FCCCMD_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`fcccmd::W`](W) writer structure"]
impl crate :: Writable for FCCCMD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FCCCMD to value 0"]
impl crate :: Resettable for FCCCMD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PMUOPAMP (rw) register accessor: GPAMP control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmuopamp::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmuopamp::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pmuopamp`]
module"]
pub type PMUOPAMP = crate :: Reg < pmuopamp :: PMUOPAMP_SPEC > ; # [doc = "GPAMP control"]
pub mod pmuopamp { # [doc = "Register `PMUOPAMP` reader"]
pub type R = crate :: R < PMUOPAMP_SPEC > ; # [doc = "Register `PMUOPAMP` writer"]
pub type W = crate :: W < PMUOPAMP_SPEC > ; # [doc = "Field `PMUOPAMP_ENABLE` reader - Set ENABLE to turn on the GPAMP."]
pub type PMUOPAMP_ENABLE_R = crate :: BitReader < PMUOPAMP_ENABLE_A > ; # [doc = "Set ENABLE to turn on the GPAMP.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PMUOPAMP_ENABLE_A { # [doc = "0: FALSE"]
PMUOPAMP_ENABLE_FALSE = 0 , # [doc = "1: TRUE"]
PMUOPAMP_ENABLE_TRUE = 1 , } impl From < PMUOPAMP_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PMUOPAMP_ENABLE_A) -> Self { variant as u8 != 0 } } impl PMUOPAMP_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PMUOPAMP_ENABLE_A { match self . bits { false => PMUOPAMP_ENABLE_A :: PMUOPAMP_ENABLE_FALSE , true => PMUOPAMP_ENABLE_A :: PMUOPAMP_ENABLE_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_pmuopamp_enable_false (& self) -> bool { * self == PMUOPAMP_ENABLE_A :: PMUOPAMP_ENABLE_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_pmuopamp_enable_true (& self) -> bool { * self == PMUOPAMP_ENABLE_A :: PMUOPAMP_ENABLE_TRUE } } # [doc = "Field `PMUOPAMP_ENABLE` writer - Set ENABLE to turn on the GPAMP."]
pub type PMUOPAMP_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PMUOPAMP_ENABLE_A > ; impl < 'a , REG , const O : u8 > PMUOPAMP_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FALSE"]
# [inline (always)]
pub fn pmuopamp_enable_false (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_ENABLE_A :: PMUOPAMP_ENABLE_FALSE) } # [doc = "TRUE"]
# [inline (always)]
pub fn pmuopamp_enable_true (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_ENABLE_A :: PMUOPAMP_ENABLE_TRUE) } } # [doc = "Field `PMUOPAMP_PCHENABLE` reader - Set PCHENABLE to enable the positive channel input."]
pub type PMUOPAMP_PCHENABLE_R = crate :: BitReader < PMUOPAMP_PCHENABLE_A > ; # [doc = "Set PCHENABLE to enable the positive channel input.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PMUOPAMP_PCHENABLE_A { # [doc = "0: FALSE"]
PMUOPAMP_PCHENABLE_FALSE = 0 , # [doc = "1: TRUE"]
PMUOPAMP_PCHENABLE_TRUE = 1 , } impl From < PMUOPAMP_PCHENABLE_A > for bool { # [inline (always)]
fn from (variant : PMUOPAMP_PCHENABLE_A) -> Self { variant as u8 != 0 } } impl PMUOPAMP_PCHENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PMUOPAMP_PCHENABLE_A { match self . bits { false => PMUOPAMP_PCHENABLE_A :: PMUOPAMP_PCHENABLE_FALSE , true => PMUOPAMP_PCHENABLE_A :: PMUOPAMP_PCHENABLE_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_pmuopamp_pchenable_false (& self) -> bool { * self == PMUOPAMP_PCHENABLE_A :: PMUOPAMP_PCHENABLE_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_pmuopamp_pchenable_true (& self) -> bool { * self == PMUOPAMP_PCHENABLE_A :: PMUOPAMP_PCHENABLE_TRUE } } # [doc = "Field `PMUOPAMP_PCHENABLE` writer - Set PCHENABLE to enable the positive channel input."]
pub type PMUOPAMP_PCHENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PMUOPAMP_PCHENABLE_A > ; impl < 'a , REG , const O : u8 > PMUOPAMP_PCHENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FALSE"]
# [inline (always)]
pub fn pmuopamp_pchenable_false (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_PCHENABLE_A :: PMUOPAMP_PCHENABLE_FALSE) } # [doc = "TRUE"]
# [inline (always)]
pub fn pmuopamp_pchenable_true (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_PCHENABLE_A :: PMUOPAMP_PCHENABLE_TRUE) } } # [doc = "Field `PMUOPAMP_NSEL` reader - NSEL selects the GPAMP negative channel input."]
pub type PMUOPAMP_NSEL_R = crate :: FieldReader < PMUOPAMP_NSEL_A > ; # [doc = "NSEL selects the GPAMP negative channel input.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PMUOPAMP_NSEL_A { # [doc = "0: SEL0"]
PMUOPAMP_NSEL_SEL0 = 0 , # [doc = "1: SEL1"]
PMUOPAMP_NSEL_SEL1 = 1 , # [doc = "2: SEL2"]
PMUOPAMP_NSEL_SEL2 = 2 , # [doc = "3: SEL3"]
PMUOPAMP_NSEL_SEL3 = 3 , } impl From < PMUOPAMP_NSEL_A > for u8 { # [inline (always)]
fn from (variant : PMUOPAMP_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for PMUOPAMP_NSEL_A { type Ux = u8 ; } impl PMUOPAMP_NSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PMUOPAMP_NSEL_A { match self . bits { 0 => PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL0 , 1 => PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL1 , 2 => PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL2 , 3 => PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL3 , _ => unreachable ! () , } } # [doc = "SEL0"]
# [inline (always)]
pub fn is_pmuopamp_nsel_sel0 (& self) -> bool { * self == PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL0 } # [doc = "SEL1"]
# [inline (always)]
pub fn is_pmuopamp_nsel_sel1 (& self) -> bool { * self == PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL1 } # [doc = "SEL2"]
# [inline (always)]
pub fn is_pmuopamp_nsel_sel2 (& self) -> bool { * self == PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL2 } # [doc = "SEL3"]
# [inline (always)]
pub fn is_pmuopamp_nsel_sel3 (& self) -> bool { * self == PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL3 } } # [doc = "Field `PMUOPAMP_NSEL` writer - NSEL selects the GPAMP negative channel input."]
pub type PMUOPAMP_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , PMUOPAMP_NSEL_A > ; impl < 'a , REG , const O : u8 > PMUOPAMP_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL0"]
# [inline (always)]
pub fn pmuopamp_nsel_sel0 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL0) } # [doc = "SEL1"]
# [inline (always)]
pub fn pmuopamp_nsel_sel1 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL1) } # [doc = "SEL2"]
# [inline (always)]
pub fn pmuopamp_nsel_sel2 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL2) } # [doc = "SEL3"]
# [inline (always)]
pub fn pmuopamp_nsel_sel3 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_NSEL_A :: PMUOPAMP_NSEL_SEL3) } } # [doc = "Field `PMUOPAMP_RRI` reader - RRI selects the rail-to-rail input mode."]
pub type PMUOPAMP_RRI_R = crate :: FieldReader < PMUOPAMP_RRI_A > ; # [doc = "RRI selects the rail-to-rail input mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PMUOPAMP_RRI_A { # [doc = "0: MODE0"]
PMUOPAMP_RRI_MODE0 = 0 , # [doc = "1: MODE1"]
PMUOPAMP_RRI_MODE1 = 1 , # [doc = "2: MODE2"]
PMUOPAMP_RRI_MODE2 = 2 , # [doc = "3: MODE3"]
PMUOPAMP_RRI_MODE3 = 3 , } impl From < PMUOPAMP_RRI_A > for u8 { # [inline (always)]
fn from (variant : PMUOPAMP_RRI_A) -> Self { variant as _ } } impl crate :: FieldSpec for PMUOPAMP_RRI_A { type Ux = u8 ; } impl PMUOPAMP_RRI_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PMUOPAMP_RRI_A { match self . bits { 0 => PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE0 , 1 => PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE1 , 2 => PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE2 , 3 => PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE3 , _ => unreachable ! () , } } # [doc = "MODE0"]
# [inline (always)]
pub fn is_pmuopamp_rri_mode0 (& self) -> bool { * self == PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE0 } # [doc = "MODE1"]
# [inline (always)]
pub fn is_pmuopamp_rri_mode1 (& self) -> bool { * self == PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE1 } # [doc = "MODE2"]
# [inline (always)]
pub fn is_pmuopamp_rri_mode2 (& self) -> bool { * self == PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE2 } # [doc = "MODE3"]
# [inline (always)]
pub fn is_pmuopamp_rri_mode3 (& self) -> bool { * self == PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE3 } } # [doc = "Field `PMUOPAMP_RRI` writer - RRI selects the rail-to-rail input mode."]
pub type PMUOPAMP_RRI_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , PMUOPAMP_RRI_A > ; impl < 'a , REG , const O : u8 > PMUOPAMP_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "MODE0"]
# [inline (always)]
pub fn pmuopamp_rri_mode0 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE0) } # [doc = "MODE1"]
# [inline (always)]
pub fn pmuopamp_rri_mode1 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE1) } # [doc = "MODE2"]
# [inline (always)]
pub fn pmuopamp_rri_mode2 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE2) } # [doc = "MODE3"]
# [inline (always)]
pub fn pmuopamp_rri_mode3 (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_RRI_A :: PMUOPAMP_RRI_MODE3) } } # [doc = "Field `PMUOPAMP_OUTENABLE` reader - Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin"]
pub type PMUOPAMP_OUTENABLE_R = crate :: BitReader < PMUOPAMP_OUTENABLE_A > ; # [doc = "Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PMUOPAMP_OUTENABLE_A { # [doc = "0: FALSE"]
PMUOPAMP_OUTENABLE_FALSE = 0 , # [doc = "1: TRUE"]
PMUOPAMP_OUTENABLE_TRUE = 1 , } impl From < PMUOPAMP_OUTENABLE_A > for bool { # [inline (always)]
fn from (variant : PMUOPAMP_OUTENABLE_A) -> Self { variant as u8 != 0 } } impl PMUOPAMP_OUTENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PMUOPAMP_OUTENABLE_A { match self . bits { false => PMUOPAMP_OUTENABLE_A :: PMUOPAMP_OUTENABLE_FALSE , true => PMUOPAMP_OUTENABLE_A :: PMUOPAMP_OUTENABLE_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_pmuopamp_outenable_false (& self) -> bool { * self == PMUOPAMP_OUTENABLE_A :: PMUOPAMP_OUTENABLE_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_pmuopamp_outenable_true (& self) -> bool { * self == PMUOPAMP_OUTENABLE_A :: PMUOPAMP_OUTENABLE_TRUE } } # [doc = "Field `PMUOPAMP_OUTENABLE` writer - Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin"]
pub type PMUOPAMP_OUTENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PMUOPAMP_OUTENABLE_A > ; impl < 'a , REG , const O : u8 > PMUOPAMP_OUTENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "FALSE"]
# [inline (always)]
pub fn pmuopamp_outenable_false (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_OUTENABLE_A :: PMUOPAMP_OUTENABLE_FALSE) } # [doc = "TRUE"]
# [inline (always)]
pub fn pmuopamp_outenable_true (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_OUTENABLE_A :: PMUOPAMP_OUTENABLE_TRUE) } } # [doc = "Field `PMUOPAMP_CHOPCLKFREQ` reader - CHOPCLKFREQ selects the GPAMP chopping clock frequency"]
pub type PMUOPAMP_CHOPCLKFREQ_R = crate :: FieldReader < PMUOPAMP_CHOPCLKFREQ_A > ; # [doc = "CHOPCLKFREQ selects the GPAMP chopping clock frequency\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PMUOPAMP_CHOPCLKFREQ_A { # [doc = "0: CLK16KHZ"]
PMUOPAMP_CHOPCLKFREQ_CLK16KHZ = 0 , # [doc = "1: CLK8KHZ"]
PMUOPAMP_CHOPCLKFREQ_CLK8KHZ = 1 , # [doc = "2: CLK4KHZ"]
PMUOPAMP_CHOPCLKFREQ_CLK4KHZ = 2 , # [doc = "3: CLK2KHZ"]
PMUOPAMP_CHOPCLKFREQ_CLK2KHZ = 3 , } impl From < PMUOPAMP_CHOPCLKFREQ_A > for u8 { # [inline (always)]
fn from (variant : PMUOPAMP_CHOPCLKFREQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for PMUOPAMP_CHOPCLKFREQ_A { type Ux = u8 ; } impl PMUOPAMP_CHOPCLKFREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PMUOPAMP_CHOPCLKFREQ_A { match self . bits { 0 => PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK16KHZ , 1 => PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK8KHZ , 2 => PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK4KHZ , 3 => PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK2KHZ , _ => unreachable ! () , } } # [doc = "CLK16KHZ"]
# [inline (always)]
pub fn is_pmuopamp_chopclkfreq_clk16khz (& self) -> bool { * self == PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK16KHZ } # [doc = "CLK8KHZ"]
# [inline (always)]
pub fn is_pmuopamp_chopclkfreq_clk8khz (& self) -> bool { * self == PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK8KHZ } # [doc = "CLK4KHZ"]
# [inline (always)]
pub fn is_pmuopamp_chopclkfreq_clk4khz (& self) -> bool { * self == PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK4KHZ } # [doc = "CLK2KHZ"]
# [inline (always)]
pub fn is_pmuopamp_chopclkfreq_clk2khz (& self) -> bool { * self == PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK2KHZ } } # [doc = "Field `PMUOPAMP_CHOPCLKFREQ` writer - CHOPCLKFREQ selects the GPAMP chopping clock frequency"]
pub type PMUOPAMP_CHOPCLKFREQ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , PMUOPAMP_CHOPCLKFREQ_A > ; impl < 'a , REG , const O : u8 > PMUOPAMP_CHOPCLKFREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CLK16KHZ"]
# [inline (always)]
pub fn pmuopamp_chopclkfreq_clk16khz (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK16KHZ) } # [doc = "CLK8KHZ"]
# [inline (always)]
pub fn pmuopamp_chopclkfreq_clk8khz (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK8KHZ) } # [doc = "CLK4KHZ"]
# [inline (always)]
pub fn pmuopamp_chopclkfreq_clk4khz (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK4KHZ) } # [doc = "CLK2KHZ"]
# [inline (always)]
pub fn pmuopamp_chopclkfreq_clk2khz (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_CHOPCLKFREQ_A :: PMUOPAMP_CHOPCLKFREQ_CLK2KHZ) } } # [doc = "Field `PMUOPAMP_CHOPCLKMODE` reader - CHOPCLKMODE selects the GPAMP chopping mode."]
pub type PMUOPAMP_CHOPCLKMODE_R = crate :: FieldReader < PMUOPAMP_CHOPCLKMODE_A > ; # [doc = "CHOPCLKMODE selects the GPAMP chopping mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PMUOPAMP_CHOPCLKMODE_A { # [doc = "0: CHOPDISABLED"]
PMUOPAMP_CHOPCLKMODE_CHOPDISABLED = 0 , # [doc = "1: REGCHOP"]
PMUOPAMP_CHOPCLKMODE_REGCHOP = 1 , # [doc = "2: ADCASSIST"]
PMUOPAMP_CHOPCLKMODE_ADCASSIST = 2 , } impl From < PMUOPAMP_CHOPCLKMODE_A > for u8 { # [inline (always)]
fn from (variant : PMUOPAMP_CHOPCLKMODE_A) -> Self { variant as _ } } impl crate :: FieldSpec for PMUOPAMP_CHOPCLKMODE_A { type Ux = u8 ; } impl PMUOPAMP_CHOPCLKMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < PMUOPAMP_CHOPCLKMODE_A > { match self . bits { 0 => Some (PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_CHOPDISABLED) , 1 => Some (PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_REGCHOP) , 2 => Some (PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_ADCASSIST) , _ => None , } } # [doc = "CHOPDISABLED"]
# [inline (always)]
pub fn is_pmuopamp_chopclkmode_chopdisabled (& self) -> bool { * self == PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_CHOPDISABLED } # [doc = "REGCHOP"]
# [inline (always)]
pub fn is_pmuopamp_chopclkmode_regchop (& self) -> bool { * self == PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_REGCHOP } # [doc = "ADCASSIST"]
# [inline (always)]
pub fn is_pmuopamp_chopclkmode_adcassist (& self) -> bool { * self == PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_ADCASSIST } } # [doc = "Field `PMUOPAMP_CHOPCLKMODE` writer - CHOPCLKMODE selects the GPAMP chopping mode."]
pub type PMUOPAMP_CHOPCLKMODE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , PMUOPAMP_CHOPCLKMODE_A > ; impl < 'a , REG , const O : u8 > PMUOPAMP_CHOPCLKMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CHOPDISABLED"]
# [inline (always)]
pub fn pmuopamp_chopclkmode_chopdisabled (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_CHOPDISABLED) } # [doc = "REGCHOP"]
# [inline (always)]
pub fn pmuopamp_chopclkmode_regchop (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_REGCHOP) } # [doc = "ADCASSIST"]
# [inline (always)]
pub fn pmuopamp_chopclkmode_adcassist (self) -> & 'a mut crate :: W < REG > { self . variant (PMUOPAMP_CHOPCLKMODE_A :: PMUOPAMP_CHOPCLKMODE_ADCASSIST) } } impl R { # [doc = "Bit 0 - Set ENABLE to turn on the GPAMP."]
# [inline (always)]
pub fn pmuopamp_enable (& self) -> PMUOPAMP_ENABLE_R { PMUOPAMP_ENABLE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Set PCHENABLE to enable the positive channel input."]
# [inline (always)]
pub fn pmuopamp_pchenable (& self) -> PMUOPAMP_PCHENABLE_R { PMUOPAMP_PCHENABLE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 2:3 - NSEL selects the GPAMP negative channel input."]
# [inline (always)]
pub fn pmuopamp_nsel (& self) -> PMUOPAMP_NSEL_R { PMUOPAMP_NSEL_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - RRI selects the rail-to-rail input mode."]
# [inline (always)]
pub fn pmuopamp_rri (& self) -> PMUOPAMP_RRI_R { PMUOPAMP_RRI_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bit 6 - Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin"]
# [inline (always)]
pub fn pmuopamp_outenable (& self) -> PMUOPAMP_OUTENABLE_R { PMUOPAMP_OUTENABLE_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 8:9 - CHOPCLKFREQ selects the GPAMP chopping clock frequency"]
# [inline (always)]
pub fn pmuopamp_chopclkfreq (& self) -> PMUOPAMP_CHOPCLKFREQ_R { PMUOPAMP_CHOPCLKFREQ_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bits 10:11 - CHOPCLKMODE selects the GPAMP chopping mode."]
# [inline (always)]
pub fn pmuopamp_chopclkmode (& self) -> PMUOPAMP_CHOPCLKMODE_R { PMUOPAMP_CHOPCLKMODE_R :: new (((self . bits >> 10) & 3) as u8) } } impl W { # [doc = "Bit 0 - Set ENABLE to turn on the GPAMP."]
# [inline (always)]
# [must_use]
pub fn pmuopamp_enable (& mut self) -> PMUOPAMP_ENABLE_W < PMUOPAMP_SPEC , 0 > { PMUOPAMP_ENABLE_W :: new (self) } # [doc = "Bit 1 - Set PCHENABLE to enable the positive channel input."]
# [inline (always)]
# [must_use]
pub fn pmuopamp_pchenable (& mut self) -> PMUOPAMP_PCHENABLE_W < PMUOPAMP_SPEC , 1 > { PMUOPAMP_PCHENABLE_W :: new (self) } # [doc = "Bits 2:3 - NSEL selects the GPAMP negative channel input."]
# [inline (always)]
# [must_use]
pub fn pmuopamp_nsel (& mut self) -> PMUOPAMP_NSEL_W < PMUOPAMP_SPEC , 2 > { PMUOPAMP_NSEL_W :: new (self) } # [doc = "Bits 4:5 - RRI selects the rail-to-rail input mode."]
# [inline (always)]
# [must_use]
pub fn pmuopamp_rri (& mut self) -> PMUOPAMP_RRI_W < PMUOPAMP_SPEC , 4 > { PMUOPAMP_RRI_W :: new (self) } # [doc = "Bit 6 - Set OUTENABLE to connect the GPAMP output signal to the GPAMP_OUT pin"]
# [inline (always)]
# [must_use]
pub fn pmuopamp_outenable (& mut self) -> PMUOPAMP_OUTENABLE_W < PMUOPAMP_SPEC , 6 > { PMUOPAMP_OUTENABLE_W :: new (self) } # [doc = "Bits 8:9 - CHOPCLKFREQ selects the GPAMP chopping clock frequency"]
# [inline (always)]
# [must_use]
pub fn pmuopamp_chopclkfreq (& mut self) -> PMUOPAMP_CHOPCLKFREQ_W < PMUOPAMP_SPEC , 8 > { PMUOPAMP_CHOPCLKFREQ_W :: new (self) } # [doc = "Bits 10:11 - CHOPCLKMODE selects the GPAMP chopping mode."]
# [inline (always)]
# [must_use]
pub fn pmuopamp_chopclkmode (& mut self) -> PMUOPAMP_CHOPCLKMODE_W < PMUOPAMP_SPEC , 10 > { PMUOPAMP_CHOPCLKMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "GPAMP control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pmuopamp::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pmuopamp::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PMUOPAMP_SPEC ; impl crate :: RegisterSpec for PMUOPAMP_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pmuopamp::R`](R) reader structure"]
impl crate :: Readable for PMUOPAMP_SPEC { } # [doc = "`write(|w| ..)` method takes [`pmuopamp::W`](W) writer structure"]
impl crate :: Writable for PMUOPAMP_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PMUOPAMP to value 0"]
impl crate :: Resettable for PMUOPAMP_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SHUTDNSTORE0 (rw) register accessor: Shutdown storage memory (byte 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shutdnstore0`]
module"]
pub type SHUTDNSTORE0 = crate :: Reg < shutdnstore0 :: SHUTDNSTORE0_SPEC > ; # [doc = "Shutdown storage memory (byte 0)"]
pub mod shutdnstore0 { # [doc = "Register `SHUTDNSTORE0` reader"]
pub type R = crate :: R < SHUTDNSTORE0_SPEC > ; # [doc = "Register `SHUTDNSTORE0` writer"]
pub type W = crate :: W < SHUTDNSTORE0_SPEC > ; # [doc = "Field `SHUTDNSTORE0_DATA` reader - Shutdown storage byte 0"]
pub type SHUTDNSTORE0_DATA_R = crate :: FieldReader ; # [doc = "Field `SHUTDNSTORE0_DATA` writer - Shutdown storage byte 0"]
pub type SHUTDNSTORE0_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Shutdown storage byte 0"]
# [inline (always)]
pub fn shutdnstore0_data (& self) -> SHUTDNSTORE0_DATA_R { SHUTDNSTORE0_DATA_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Shutdown storage byte 0"]
# [inline (always)]
# [must_use]
pub fn shutdnstore0_data (& mut self) -> SHUTDNSTORE0_DATA_W < SHUTDNSTORE0_SPEC , 0 > { SHUTDNSTORE0_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Shutdown storage memory (byte 0)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SHUTDNSTORE0_SPEC ; impl crate :: RegisterSpec for SHUTDNSTORE0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`shutdnstore0::R`](R) reader structure"]
impl crate :: Readable for SHUTDNSTORE0_SPEC { } # [doc = "`write(|w| ..)` method takes [`shutdnstore0::W`](W) writer structure"]
impl crate :: Writable for SHUTDNSTORE0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SHUTDNSTORE0 to value 0"]
impl crate :: Resettable for SHUTDNSTORE0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SHUTDNSTORE1 (rw) register accessor: Shutdown storage memory (byte 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shutdnstore1`]
module"]
pub type SHUTDNSTORE1 = crate :: Reg < shutdnstore1 :: SHUTDNSTORE1_SPEC > ; # [doc = "Shutdown storage memory (byte 1)"]
pub mod shutdnstore1 { # [doc = "Register `SHUTDNSTORE1` reader"]
pub type R = crate :: R < SHUTDNSTORE1_SPEC > ; # [doc = "Register `SHUTDNSTORE1` writer"]
pub type W = crate :: W < SHUTDNSTORE1_SPEC > ; # [doc = "Field `SHUTDNSTORE1_DATA` reader - Shutdown storage byte 1"]
pub type SHUTDNSTORE1_DATA_R = crate :: FieldReader ; # [doc = "Field `SHUTDNSTORE1_DATA` writer - Shutdown storage byte 1"]
pub type SHUTDNSTORE1_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Shutdown storage byte 1"]
# [inline (always)]
pub fn shutdnstore1_data (& self) -> SHUTDNSTORE1_DATA_R { SHUTDNSTORE1_DATA_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Shutdown storage byte 1"]
# [inline (always)]
# [must_use]
pub fn shutdnstore1_data (& mut self) -> SHUTDNSTORE1_DATA_W < SHUTDNSTORE1_SPEC , 0 > { SHUTDNSTORE1_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Shutdown storage memory (byte 1)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SHUTDNSTORE1_SPEC ; impl crate :: RegisterSpec for SHUTDNSTORE1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`shutdnstore1::R`](R) reader structure"]
impl crate :: Readable for SHUTDNSTORE1_SPEC { } # [doc = "`write(|w| ..)` method takes [`shutdnstore1::W`](W) writer structure"]
impl crate :: Writable for SHUTDNSTORE1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SHUTDNSTORE1 to value 0"]
impl crate :: Resettable for SHUTDNSTORE1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SHUTDNSTORE2 (rw) register accessor: Shutdown storage memory (byte 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shutdnstore2`]
module"]
pub type SHUTDNSTORE2 = crate :: Reg < shutdnstore2 :: SHUTDNSTORE2_SPEC > ; # [doc = "Shutdown storage memory (byte 2)"]
pub mod shutdnstore2 { # [doc = "Register `SHUTDNSTORE2` reader"]
pub type R = crate :: R < SHUTDNSTORE2_SPEC > ; # [doc = "Register `SHUTDNSTORE2` writer"]
pub type W = crate :: W < SHUTDNSTORE2_SPEC > ; # [doc = "Field `SHUTDNSTORE2_DATA` reader - Shutdown storage byte 2"]
pub type SHUTDNSTORE2_DATA_R = crate :: FieldReader ; # [doc = "Field `SHUTDNSTORE2_DATA` writer - Shutdown storage byte 2"]
pub type SHUTDNSTORE2_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Shutdown storage byte 2"]
# [inline (always)]
pub fn shutdnstore2_data (& self) -> SHUTDNSTORE2_DATA_R { SHUTDNSTORE2_DATA_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Shutdown storage byte 2"]
# [inline (always)]
# [must_use]
pub fn shutdnstore2_data (& mut self) -> SHUTDNSTORE2_DATA_W < SHUTDNSTORE2_SPEC , 0 > { SHUTDNSTORE2_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Shutdown storage memory (byte 2)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SHUTDNSTORE2_SPEC ; impl crate :: RegisterSpec for SHUTDNSTORE2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`shutdnstore2::R`](R) reader structure"]
impl crate :: Readable for SHUTDNSTORE2_SPEC { } # [doc = "`write(|w| ..)` method takes [`shutdnstore2::W`](W) writer structure"]
impl crate :: Writable for SHUTDNSTORE2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SHUTDNSTORE2 to value 0"]
impl crate :: Resettable for SHUTDNSTORE2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SHUTDNSTORE3 (rw) register accessor: Shutdown storage memory (byte 3)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@shutdnstore3`]
module"]
pub type SHUTDNSTORE3 = crate :: Reg < shutdnstore3 :: SHUTDNSTORE3_SPEC > ; # [doc = "Shutdown storage memory (byte 3)"]
pub mod shutdnstore3 { # [doc = "Register `SHUTDNSTORE3` reader"]
pub type R = crate :: R < SHUTDNSTORE3_SPEC > ; # [doc = "Register `SHUTDNSTORE3` writer"]
pub type W = crate :: W < SHUTDNSTORE3_SPEC > ; # [doc = "Field `SHUTDNSTORE3_DATA` reader - Shutdown storage byte 3"]
pub type SHUTDNSTORE3_DATA_R = crate :: FieldReader ; # [doc = "Field `SHUTDNSTORE3_DATA` writer - Shutdown storage byte 3"]
pub type SHUTDNSTORE3_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Shutdown storage byte 3"]
# [inline (always)]
pub fn shutdnstore3_data (& self) -> SHUTDNSTORE3_DATA_R { SHUTDNSTORE3_DATA_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Shutdown storage byte 3"]
# [inline (always)]
# [must_use]
pub fn shutdnstore3_data (& mut self) -> SHUTDNSTORE3_DATA_W < SHUTDNSTORE3_SPEC , 0 > { SHUTDNSTORE3_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Shutdown storage memory (byte 3)\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`shutdnstore3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`shutdnstore3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SHUTDNSTORE3_SPEC ; impl crate :: RegisterSpec for SHUTDNSTORE3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`shutdnstore3::R`](R) reader structure"]
impl crate :: Readable for SHUTDNSTORE3_SPEC { } # [doc = "`write(|w| ..)` method takes [`shutdnstore3::W`](W) writer structure"]
impl crate :: Writable for SHUTDNSTORE3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SHUTDNSTORE3 to value 0"]
impl crate :: Resettable for SHUTDNSTORE3_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct OPA1 { _marker : PhantomData < * const () > } unsafe impl Send for OPA1 { } impl OPA1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const opa1 :: RegisterBlock = 0x4002_2000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const opa1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for OPA1 { type Target = opa1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for OPA1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("OPA1") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod opa1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved2 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub gprcm_stat : GPRCM_STAT , _reserved3 : [u8 ; 0x07f8]
, # [doc = "0x1010 - Clock Override"]
pub clkovr : CLKOVR , _reserved4 : [u8 ; 0x08]
, # [doc = "0x101c - Power Control"]
pub pwrctl : PWRCTL , _reserved5 : [u8 ; 0xe0]
, # [doc = "0x1100 - Control Register"]
pub ctl : CTL , # [doc = "0x1104 - Configuration Base Register"]
pub cfgbase : CFGBASE , # [doc = "0x1108 - Configuration Register"]
pub cfg : CFG , _reserved8 : [u8 ; 0x0c]
, # [doc = "0x1118 - Status Register"]
pub stat : STAT , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GPRCM_STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gprcm_stat`]
module"]
pub type GPRCM_STAT = crate :: Reg < gprcm_stat :: GPRCM_STAT_SPEC > ; # [doc = "Status Register"]
pub mod gprcm_stat { # [doc = "Register `GPRCM_STAT` reader"]
pub type R = crate :: R < GPRCM_STAT_SPEC > ; # [doc = "Field `GPRCM_STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type GPRCM_STAT_RESETSTKY_R = crate :: BitReader < GPRCM_STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GPRCM_STAT_RESETSTKY_A { # [doc = "0: NORES"]
GPRCM_STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
GPRCM_STAT_RESETSTKY_RESET = 1 , } impl From < GPRCM_STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : GPRCM_STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl GPRCM_STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GPRCM_STAT_RESETSTKY_A { match self . bits { false => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES , true => GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_nores (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_gprcm_stat_resetstky_reset (& self) -> bool { * self == GPRCM_STAT_RESETSTKY_A :: GPRCM_STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn gprcm_stat_resetstky (& self) -> GPRCM_STAT_RESETSTKY_R { GPRCM_STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gprcm_stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GPRCM_STAT_SPEC ; impl crate :: RegisterSpec for GPRCM_STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gprcm_stat::R`](R) reader structure"]
impl crate :: Readable for GPRCM_STAT_SPEC { } # [doc = "`reset()` method sets GPRCM_STAT to value 0"]
impl crate :: Resettable for GPRCM_STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKOVR (rw) register accessor: Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkovr`]
module"]
pub type CLKOVR = crate :: Reg < clkovr :: CLKOVR_SPEC > ; # [doc = "Clock Override"]
pub mod clkovr { # [doc = "Register `CLKOVR` reader"]
pub type R = crate :: R < CLKOVR_SPEC > ; # [doc = "Register `CLKOVR` writer"]
pub type W = crate :: W < CLKOVR_SPEC > ; # [doc = "Field `CLKOVR_OVERRIDE` reader - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
pub type CLKOVR_OVERRIDE_R = crate :: BitReader < CLKOVR_OVERRIDE_A > ; # [doc = "Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKOVR_OVERRIDE_A { # [doc = "0: DISABLED"]
CLKOVR_OVERRIDE_DISABLED = 0 , # [doc = "1: ENABLED"]
CLKOVR_OVERRIDE_ENABLED = 1 , } impl From < CLKOVR_OVERRIDE_A > for bool { # [inline (always)]
fn from (variant : CLKOVR_OVERRIDE_A) -> Self { variant as u8 != 0 } } impl CLKOVR_OVERRIDE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKOVR_OVERRIDE_A { match self . bits { false => CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED , true => CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_clkovr_override_disabled (& self) -> bool { * self == CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_clkovr_override_enabled (& self) -> bool { * self == CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED } } # [doc = "Field `CLKOVR_OVERRIDE` writer - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
pub type CLKOVR_OVERRIDE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKOVR_OVERRIDE_A > ; impl < 'a , REG , const O : u8 > CLKOVR_OVERRIDE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn clkovr_override_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn clkovr_override_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_OVERRIDE_A :: CLKOVR_OVERRIDE_ENABLED) } } # [doc = "Field `CLKOVR_RUN_STOP` reader - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
pub type CLKOVR_RUN_STOP_R = crate :: BitReader < CLKOVR_RUN_STOP_A > ; # [doc = "If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKOVR_RUN_STOP_A { # [doc = "0: RUN"]
CLKOVR_RUN_STOP_RUN = 0 , # [doc = "1: STOP"]
CLKOVR_RUN_STOP_STOP = 1 , } impl From < CLKOVR_RUN_STOP_A > for bool { # [inline (always)]
fn from (variant : CLKOVR_RUN_STOP_A) -> Self { variant as u8 != 0 } } impl CLKOVR_RUN_STOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKOVR_RUN_STOP_A { match self . bits { false => CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN , true => CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP , } } # [doc = "RUN"]
# [inline (always)]
pub fn is_clkovr_run_stop_run (& self) -> bool { * self == CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN } # [doc = "STOP"]
# [inline (always)]
pub fn is_clkovr_run_stop_stop (& self) -> bool { * self == CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP } } # [doc = "Field `CLKOVR_RUN_STOP` writer - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
pub type CLKOVR_RUN_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKOVR_RUN_STOP_A > ; impl < 'a , REG , const O : u8 > CLKOVR_RUN_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RUN"]
# [inline (always)]
pub fn clkovr_run_stop_run (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_RUN) } # [doc = "STOP"]
# [inline (always)]
pub fn clkovr_run_stop_stop (self) -> & 'a mut crate :: W < REG > { self . variant (CLKOVR_RUN_STOP_A :: CLKOVR_RUN_STOP_STOP) } } impl R { # [doc = "Bit 0 - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
# [inline (always)]
pub fn clkovr_override (& self) -> CLKOVR_OVERRIDE_R { CLKOVR_OVERRIDE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
# [inline (always)]
pub fn clkovr_run_stop (& self) -> CLKOVR_RUN_STOP_R { CLKOVR_RUN_STOP_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Unlocks the functionality of \\[RUN_STOP\\]
to override the automatic peripheral clock request"]
# [inline (always)]
# [must_use]
pub fn clkovr_override (& mut self) -> CLKOVR_OVERRIDE_W < CLKOVR_SPEC , 0 > { CLKOVR_OVERRIDE_W :: new (self) } # [doc = "Bit 1 - If \\[OVERRIDE\\]
is enabled, this register is used to manually control the peripheral's clock request to the system"]
# [inline (always)]
# [must_use]
pub fn clkovr_run_stop (& mut self) -> CLKOVR_RUN_STOP_W < CLKOVR_SPEC , 1 > { CLKOVR_RUN_STOP_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Override\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkovr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkovr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKOVR_SPEC ; impl crate :: RegisterSpec for CLKOVR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkovr::R`](R) reader structure"]
impl crate :: Readable for CLKOVR_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkovr::W`](W) writer structure"]
impl crate :: Writable for CLKOVR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKOVR to value 0"]
impl crate :: Resettable for CLKOVR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWRCTL (rw) register accessor: Power Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwrctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwrctl`]
module"]
pub type PWRCTL = crate :: Reg < pwrctl :: PWRCTL_SPEC > ; # [doc = "Power Control"]
pub mod pwrctl { # [doc = "Register `PWRCTL` reader"]
pub type R = crate :: R < PWRCTL_SPEC > ; # [doc = "Register `PWRCTL` writer"]
pub type W = crate :: W < PWRCTL_SPEC > ; # [doc = "Field `PWRCTL_AUTO_OFF` reader - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
pub type PWRCTL_AUTO_OFF_R = crate :: BitReader < PWRCTL_AUTO_OFF_A > ; # [doc = "When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWRCTL_AUTO_OFF_A { # [doc = "0: DISABLE"]
PWRCTL_AUTO_OFF_DISABLE = 0 , # [doc = "1: ENABLE"]
PWRCTL_AUTO_OFF_ENABLE = 1 , } impl From < PWRCTL_AUTO_OFF_A > for bool { # [inline (always)]
fn from (variant : PWRCTL_AUTO_OFF_A) -> Self { variant as u8 != 0 } } impl PWRCTL_AUTO_OFF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWRCTL_AUTO_OFF_A { match self . bits { false => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE , true => PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwrctl_auto_off_disable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwrctl_auto_off_enable (& self) -> bool { * self == PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE } } # [doc = "Field `PWRCTL_AUTO_OFF` writer - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
pub type PWRCTL_AUTO_OFF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWRCTL_AUTO_OFF_A > ; impl < 'a , REG , const O : u8 > PWRCTL_AUTO_OFF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwrctl_auto_off_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwrctl_auto_off_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWRCTL_AUTO_OFF_A :: PWRCTL_AUTO_OFF_ENABLE) } } impl R { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
# [inline (always)]
pub fn pwrctl_auto_off (& self) -> PWRCTL_AUTO_OFF_R { PWRCTL_AUTO_OFF_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - When set the peripheral will remove its local IP request for enable so that it can be disabled if no other entities in the system are requesting it to be enabled."]
# [inline (always)]
# [must_use]
pub fn pwrctl_auto_off (& mut self) -> PWRCTL_AUTO_OFF_W < PWRCTL_SPEC , 0 > { PWRCTL_AUTO_OFF_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwrctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWRCTL_SPEC ; impl crate :: RegisterSpec for PWRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwrctl::R`](R) reader structure"]
impl crate :: Readable for PWRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwrctl::W`](W) writer structure"]
impl crate :: Writable for PWRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWRCTL to value 0"]
impl crate :: Resettable for PWRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl`]
module"]
pub type CTL = crate :: Reg < ctl :: CTL_SPEC > ; # [doc = "Control Register"]
pub mod ctl { # [doc = "Register `CTL` reader"]
pub type R = crate :: R < CTL_SPEC > ; # [doc = "Register `CTL` writer"]
pub type W = crate :: W < CTL_SPEC > ; # [doc = "Field `CTL_ENABLE` reader - OAxn Enable."]
pub type CTL_ENABLE_R = crate :: BitReader < CTL_ENABLE_A > ; # [doc = "OAxn Enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL_ENABLE_A { # [doc = "0: OFF"]
CTL_ENABLE_OFF = 0 , # [doc = "1: ON"]
CTL_ENABLE_ON = 1 , } impl From < CTL_ENABLE_A > for bool { # [inline (always)]
fn from (variant : CTL_ENABLE_A) -> Self { variant as u8 != 0 } } impl CTL_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL_ENABLE_A { match self . bits { false => CTL_ENABLE_A :: CTL_ENABLE_OFF , true => CTL_ENABLE_A :: CTL_ENABLE_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_ctl_enable_off (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_ctl_enable_on (& self) -> bool { * self == CTL_ENABLE_A :: CTL_ENABLE_ON } } # [doc = "Field `CTL_ENABLE` writer - OAxn Enable."]
pub type CTL_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL_ENABLE_A > ; impl < 'a , REG , const O : u8 > CTL_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"]
# [inline (always)]
pub fn ctl_enable_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn ctl_enable_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL_ENABLE_A :: CTL_ENABLE_ON) } } impl R { # [doc = "Bit 0 - OAxn Enable."]
# [inline (always)]
pub fn ctl_enable (& self) -> CTL_ENABLE_R { CTL_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - OAxn Enable."]
# [inline (always)]
# [must_use]
pub fn ctl_enable (& mut self) -> CTL_ENABLE_W < CTL_SPEC , 0 > { CTL_ENABLE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL_SPEC ; impl crate :: RegisterSpec for CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl::R`](R) reader structure"]
impl crate :: Readable for CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl::W`](W) writer structure"]
impl crate :: Writable for CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL to value 0"]
impl crate :: Resettable for CTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CFGBASE (rw) register accessor: Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfgbase`]
module"]
pub type CFGBASE = crate :: Reg < cfgbase :: CFGBASE_SPEC > ; # [doc = "Configuration Base Register"]
pub mod cfgbase { # [doc = "Register `CFGBASE` reader"]
pub type R = crate :: R < CFGBASE_SPEC > ; # [doc = "Register `CFGBASE` writer"]
pub type W = crate :: W < CFGBASE_SPEC > ; # [doc = "Field `CFGBASE_GBW` reader - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
pub type CFGBASE_GBW_R = crate :: BitReader < CFGBASE_GBW_A > ; # [doc = "Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CFGBASE_GBW_A { # [doc = "0: LOWGAIN"]
CFGBASE_GBW_LOWGAIN = 0 , # [doc = "1: HIGHGAIN"]
CFGBASE_GBW_HIGHGAIN = 1 , } impl From < CFGBASE_GBW_A > for bool { # [inline (always)]
fn from (variant : CFGBASE_GBW_A) -> Self { variant as u8 != 0 } } impl CFGBASE_GBW_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CFGBASE_GBW_A { match self . bits { false => CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN , true => CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN , } } # [doc = "LOWGAIN"]
# [inline (always)]
pub fn is_cfgbase_gbw_lowgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN } # [doc = "HIGHGAIN"]
# [inline (always)]
pub fn is_cfgbase_gbw_highgain (& self) -> bool { * self == CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN } } # [doc = "Field `CFGBASE_GBW` writer - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
pub type CFGBASE_GBW_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_GBW_A > ; impl < 'a , REG , const O : u8 > CFGBASE_GBW_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOWGAIN"]
# [inline (always)]
pub fn cfgbase_gbw_lowgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_LOWGAIN) } # [doc = "HIGHGAIN"]
# [inline (always)]
pub fn cfgbase_gbw_highgain (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_GBW_A :: CFGBASE_GBW_HIGHGAIN) } } # [doc = "Field `CFGBASE_RRI` reader - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
pub type CFGBASE_RRI_R = crate :: BitReader < CFGBASE_RRI_A > ; # [doc = "Rail-to-rail input enable. Can only be modified when STAT.BUSY=0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CFGBASE_RRI_A { # [doc = "0: OFF"]
CFGBASE_RRI_OFF = 0 , # [doc = "1: ON"]
CFGBASE_RRI_ON = 1 , } impl From < CFGBASE_RRI_A > for bool { # [inline (always)]
fn from (variant : CFGBASE_RRI_A) -> Self { variant as u8 != 0 } } impl CFGBASE_RRI_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CFGBASE_RRI_A { match self . bits { false => CFGBASE_RRI_A :: CFGBASE_RRI_OFF , true => CFGBASE_RRI_A :: CFGBASE_RRI_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_cfgbase_rri_off (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_cfgbase_rri_on (& self) -> bool { * self == CFGBASE_RRI_A :: CFGBASE_RRI_ON } } # [doc = "Field `CFGBASE_RRI` writer - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
pub type CFGBASE_RRI_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFGBASE_RRI_A > ; impl < 'a , REG , const O : u8 > CFGBASE_RRI_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"]
# [inline (always)]
pub fn cfgbase_rri_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn cfgbase_rri_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFGBASE_RRI_A :: CFGBASE_RRI_ON) } } impl R { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
# [inline (always)]
pub fn cfgbase_gbw (& self) -> CFGBASE_GBW_R { CFGBASE_GBW_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
# [inline (always)]
pub fn cfgbase_rri (& self) -> CFGBASE_RRI_R { CFGBASE_RRI_R :: new (((self . bits >> 2) & 1) != 0) } } impl W { # [doc = "Bit 0 - Select gain bandwidth which affects current as well the gain bandwidth. The lower gain bandwidth has lower current. See device specific datasheet for values. Can only be modified when STAT.BUSY=0."]
# [inline (always)]
# [must_use]
pub fn cfgbase_gbw (& mut self) -> CFGBASE_GBW_W < CFGBASE_SPEC , 0 > { CFGBASE_GBW_W :: new (self) } # [doc = "Bit 2 - Rail-to-rail input enable. Can only be modified when STAT.BUSY=0"]
# [inline (always)]
# [must_use]
pub fn cfgbase_rri (& mut self) -> CFGBASE_RRI_W < CFGBASE_SPEC , 2 > { CFGBASE_RRI_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Base Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfgbase::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfgbase::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFGBASE_SPEC ; impl crate :: RegisterSpec for CFGBASE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfgbase::R`](R) reader structure"]
impl crate :: Readable for CFGBASE_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfgbase::W`](W) writer structure"]
impl crate :: Writable for CFGBASE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFGBASE to value 0"]
impl crate :: Resettable for CFGBASE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CFG (rw) register accessor: Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub type CFG = crate :: Reg < cfg :: CFG_SPEC > ; # [doc = "Configuration Register"]
pub mod cfg { # [doc = "Register `CFG` reader"]
pub type R = crate :: R < CFG_SPEC > ; # [doc = "Register `CFG` writer"]
pub type W = crate :: W < CFG_SPEC > ; # [doc = "Field `CFG_CHOP` reader - Chopping enable."]
pub type CFG_CHOP_R = crate :: FieldReader < CFG_CHOP_A > ; # [doc = "Chopping enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_CHOP_A { # [doc = "0: OFF"]
CFG_CHOP_OFF = 0 , # [doc = "1: ON"]
CFG_CHOP_ON = 1 , # [doc = "2: AVGON"]
CFG_CHOP_AVGON = 2 , } impl From < CFG_CHOP_A > for u8 { # [inline (always)]
fn from (variant : CFG_CHOP_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_CHOP_A { type Ux = u8 ; } impl CFG_CHOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_CHOP_A > { match self . bits { 0 => Some (CFG_CHOP_A :: CFG_CHOP_OFF) , 1 => Some (CFG_CHOP_A :: CFG_CHOP_ON) , 2 => Some (CFG_CHOP_A :: CFG_CHOP_AVGON) , _ => None , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_cfg_chop_off (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_cfg_chop_on (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_ON } # [doc = "AVGON"]
# [inline (always)]
pub fn is_cfg_chop_avgon (& self) -> bool { * self == CFG_CHOP_A :: CFG_CHOP_AVGON } } # [doc = "Field `CFG_CHOP` writer - Chopping enable."]
pub type CFG_CHOP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CFG_CHOP_A > ; impl < 'a , REG , const O : u8 > CFG_CHOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "OFF"]
# [inline (always)]
pub fn cfg_chop_off (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn cfg_chop_on (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_ON) } # [doc = "AVGON"]
# [inline (always)]
pub fn cfg_chop_avgon (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_CHOP_A :: CFG_CHOP_AVGON) } } # [doc = "Field `CFG_OUTPIN` reader - Enable output pin"]
pub type CFG_OUTPIN_R = crate :: BitReader < CFG_OUTPIN_A > ; # [doc = "Enable output pin\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CFG_OUTPIN_A { # [doc = "0: DISABLED"]
CFG_OUTPIN_DISABLED = 0 , # [doc = "1: ENABLED"]
CFG_OUTPIN_ENABLED = 1 , } impl From < CFG_OUTPIN_A > for bool { # [inline (always)]
fn from (variant : CFG_OUTPIN_A) -> Self { variant as u8 != 0 } } impl CFG_OUTPIN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CFG_OUTPIN_A { match self . bits { false => CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED , true => CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cfg_outpin_disabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_cfg_outpin_enabled (& self) -> bool { * self == CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED } } # [doc = "Field `CFG_OUTPIN` writer - Enable output pin"]
pub type CFG_OUTPIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CFG_OUTPIN_A > ; impl < 'a , REG , const O : u8 > CFG_OUTPIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cfg_outpin_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn cfg_outpin_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_OUTPIN_A :: CFG_OUTPIN_ENABLED) } } # [doc = "Field `CFG_PSEL` reader - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_PSEL_R = crate :: FieldReader < CFG_PSEL_A > ; # [doc = "Positive OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_PSEL_A { # [doc = "0: NC"]
CFG_PSEL_NC = 0 , # [doc = "1: EXTPIN0"]
CFG_PSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"]
CFG_PSEL_EXTPIN1 = 2 , # [doc = "3: DAC12OUT"]
CFG_PSEL_DAC12OUT = 3 , # [doc = "4: DAC8OUT"]
CFG_PSEL_DAC8OUT = 4 , # [doc = "5: VREF"]
CFG_PSEL_VREF = 5 , # [doc = "6: OANM1RTOP"]
CFG_PSEL_OANM1RTOP = 6 , # [doc = "7: GPAMP_OUT_INT"]
CFG_PSEL_GPAMP_OUT_INT = 7 , # [doc = "8: VSS"]
CFG_PSEL_VSS = 8 , } impl From < CFG_PSEL_A > for u8 { # [inline (always)]
fn from (variant : CFG_PSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_PSEL_A { type Ux = u8 ; } impl CFG_PSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_PSEL_A > { match self . bits { 0 => Some (CFG_PSEL_A :: CFG_PSEL_NC) , 1 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) , 2 => Some (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) , 3 => Some (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) , 4 => Some (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) , 5 => Some (CFG_PSEL_A :: CFG_PSEL_VREF) , 6 => Some (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) , 7 => Some (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) , 8 => Some (CFG_PSEL_A :: CFG_PSEL_VSS) , _ => None , } } # [doc = "NC"]
# [inline (always)]
pub fn is_cfg_psel_nc (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_NC } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn is_cfg_psel_extpin0 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN0 } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn is_cfg_psel_extpin1 (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_EXTPIN1 } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn is_cfg_psel_dac12out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC12OUT } # [doc = "DAC8OUT"]
# [inline (always)]
pub fn is_cfg_psel_dac8out (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_DAC8OUT } # [doc = "VREF"]
# [inline (always)]
pub fn is_cfg_psel_vref (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VREF } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn is_cfg_psel_oanm1rtop (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_OANM1RTOP } # [doc = "GPAMP_OUT_INT"]
# [inline (always)]
pub fn is_cfg_psel_gpamp_out_int (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT } # [doc = "VSS"]
# [inline (always)]
pub fn is_cfg_psel_vss (& self) -> bool { * self == CFG_PSEL_A :: CFG_PSEL_VSS } } # [doc = "Field `CFG_PSEL` writer - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_PSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CFG_PSEL_A > ; impl < 'a , REG , const O : u8 > CFG_PSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"]
# [inline (always)]
pub fn cfg_psel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_NC) } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn cfg_psel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN0) } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn cfg_psel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_EXTPIN1) } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn cfg_psel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC12OUT) } # [doc = "DAC8OUT"]
# [inline (always)]
pub fn cfg_psel_dac8out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_DAC8OUT) } # [doc = "VREF"]
# [inline (always)]
pub fn cfg_psel_vref (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VREF) } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn cfg_psel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_OANM1RTOP) } # [doc = "GPAMP_OUT_INT"]
# [inline (always)]
pub fn cfg_psel_gpamp_out_int (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_GPAMP_OUT_INT) } # [doc = "VSS"]
# [inline (always)]
pub fn cfg_psel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_PSEL_A :: CFG_PSEL_VSS) } } # [doc = "Field `CFG_NSEL` reader - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_NSEL_R = crate :: FieldReader < CFG_NSEL_A > ; # [doc = "Negative OA input selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_NSEL_A { # [doc = "0: NC"]
CFG_NSEL_NC = 0 , # [doc = "1: EXTPIN0"]
CFG_NSEL_EXTPIN0 = 1 , # [doc = "2: EXTPIN1"]
CFG_NSEL_EXTPIN1 = 2 , # [doc = "3: OANP1RBOT"]
CFG_NSEL_OANP1RBOT = 3 , # [doc = "4: OANRTAP"]
CFG_NSEL_OANRTAP = 4 , # [doc = "5: OANRTOP"]
CFG_NSEL_OANRTOP = 5 , # [doc = "6: SPARE"]
CFG_NSEL_SPARE = 6 , } impl From < CFG_NSEL_A > for u8 { # [inline (always)]
fn from (variant : CFG_NSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_NSEL_A { type Ux = u8 ; } impl CFG_NSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_NSEL_A > { match self . bits { 0 => Some (CFG_NSEL_A :: CFG_NSEL_NC) , 1 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) , 2 => Some (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) , 3 => Some (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) , 4 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTAP) , 5 => Some (CFG_NSEL_A :: CFG_NSEL_OANRTOP) , 6 => Some (CFG_NSEL_A :: CFG_NSEL_SPARE) , _ => None , } } # [doc = "NC"]
# [inline (always)]
pub fn is_cfg_nsel_nc (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_NC } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn is_cfg_nsel_extpin0 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN0 } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn is_cfg_nsel_extpin1 (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_EXTPIN1 } # [doc = "OANP1RBOT"]
# [inline (always)]
pub fn is_cfg_nsel_oanp1rbot (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANP1RBOT } # [doc = "OANRTAP"]
# [inline (always)]
pub fn is_cfg_nsel_oanrtap (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTAP } # [doc = "OANRTOP"]
# [inline (always)]
pub fn is_cfg_nsel_oanrtop (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_OANRTOP } # [doc = "SPARE"]
# [inline (always)]
pub fn is_cfg_nsel_spare (& self) -> bool { * self == CFG_NSEL_A :: CFG_NSEL_SPARE } } # [doc = "Field `CFG_NSEL` writer - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_NSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_NSEL_A > ; impl < 'a , REG , const O : u8 > CFG_NSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"]
# [inline (always)]
pub fn cfg_nsel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_NC) } # [doc = "EXTPIN0"]
# [inline (always)]
pub fn cfg_nsel_extpin0 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN0) } # [doc = "EXTPIN1"]
# [inline (always)]
pub fn cfg_nsel_extpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_EXTPIN1) } # [doc = "OANP1RBOT"]
# [inline (always)]
pub fn cfg_nsel_oanp1rbot (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANP1RBOT) } # [doc = "OANRTAP"]
# [inline (always)]
pub fn cfg_nsel_oanrtap (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTAP) } # [doc = "OANRTOP"]
# [inline (always)]
pub fn cfg_nsel_oanrtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_OANRTOP) } # [doc = "SPARE"]
# [inline (always)]
pub fn cfg_nsel_spare (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_NSEL_A :: CFG_NSEL_SPARE) } } # [doc = "Field `CFG_MSEL` reader - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_MSEL_R = crate :: FieldReader < CFG_MSEL_A > ; # [doc = "MSEL Mux selection. Please refer to the device specific datasheet for exact channels available.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CFG_MSEL_A { # [doc = "0: NC"]
CFG_MSEL_NC = 0 , # [doc = "1: EXTNPIN1"]
CFG_MSEL_EXTNPIN1 = 1 , # [doc = "2: VSS"]
CFG_MSEL_VSS = 2 , # [doc = "3: DAC12OUT"]
CFG_MSEL_DAC12OUT = 3 , # [doc = "4: OANM1RTOP"]
CFG_MSEL_OANM1RTOP = 4 , } impl From < CFG_MSEL_A > for u8 { # [inline (always)]
fn from (variant : CFG_MSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CFG_MSEL_A { type Ux = u8 ; } impl CFG_MSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CFG_MSEL_A > { match self . bits { 0 => Some (CFG_MSEL_A :: CFG_MSEL_NC) , 1 => Some (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) , 2 => Some (CFG_MSEL_A :: CFG_MSEL_VSS) , 3 => Some (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) , 4 => Some (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) , _ => None , } } # [doc = "NC"]
# [inline (always)]
pub fn is_cfg_msel_nc (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_NC } # [doc = "EXTNPIN1"]
# [inline (always)]
pub fn is_cfg_msel_extnpin1 (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_EXTNPIN1 } # [doc = "VSS"]
# [inline (always)]
pub fn is_cfg_msel_vss (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_VSS } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn is_cfg_msel_dac12out (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_DAC12OUT } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn is_cfg_msel_oanm1rtop (& self) -> bool { * self == CFG_MSEL_A :: CFG_MSEL_OANM1RTOP } } # [doc = "Field `CFG_MSEL` writer - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
pub type CFG_MSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CFG_MSEL_A > ; impl < 'a , REG , const O : u8 > CFG_MSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NC"]
# [inline (always)]
pub fn cfg_msel_nc (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_NC) } # [doc = "EXTNPIN1"]
# [inline (always)]
pub fn cfg_msel_extnpin1 (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_EXTNPIN1) } # [doc = "VSS"]
# [inline (always)]
pub fn cfg_msel_vss (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_VSS) } # [doc = "DAC12OUT"]
# [inline (always)]
pub fn cfg_msel_dac12out (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_DAC12OUT) } # [doc = "OANM1RTOP"]
# [inline (always)]
pub fn cfg_msel_oanm1rtop (self) -> & 'a mut crate :: W < REG > { self . variant (CFG_MSEL_A :: CFG_MSEL_OANM1RTOP) } } # [doc = "Field `CFG_GAIN` reader - Gain setting. Refer to TRM for enumeration information."]
pub type CFG_GAIN_R = crate :: FieldReader ; # [doc = "Field `CFG_GAIN` writer - Gain setting. Refer to TRM for enumeration information."]
pub type CFG_GAIN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O > ; impl R { # [doc = "Bits 0:1 - Chopping enable."]
# [inline (always)]
pub fn cfg_chop (& self) -> CFG_CHOP_R { CFG_CHOP_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 2 - Enable output pin"]
# [inline (always)]
pub fn cfg_outpin (& self) -> CFG_OUTPIN_R { CFG_OUTPIN_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
pub fn cfg_psel (& self) -> CFG_PSEL_R { CFG_PSEL_R :: new (((self . bits >> 3) & 0x0f) as u8) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
pub fn cfg_nsel (& self) -> CFG_NSEL_R { CFG_NSEL_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
pub fn cfg_msel (& self) -> CFG_MSEL_R { CFG_MSEL_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."]
# [inline (always)]
pub fn cfg_gain (& self) -> CFG_GAIN_R { CFG_GAIN_R :: new (((self . bits >> 13) & 7) as u8) } } impl W { # [doc = "Bits 0:1 - Chopping enable."]
# [inline (always)]
# [must_use]
pub fn cfg_chop (& mut self) -> CFG_CHOP_W < CFG_SPEC , 0 > { CFG_CHOP_W :: new (self) } # [doc = "Bit 2 - Enable output pin"]
# [inline (always)]
# [must_use]
pub fn cfg_outpin (& mut self) -> CFG_OUTPIN_W < CFG_SPEC , 2 > { CFG_OUTPIN_W :: new (self) } # [doc = "Bits 3:6 - Positive OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
# [must_use]
pub fn cfg_psel (& mut self) -> CFG_PSEL_W < CFG_SPEC , 3 > { CFG_PSEL_W :: new (self) } # [doc = "Bits 7:9 - Negative OA input selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
# [must_use]
pub fn cfg_nsel (& mut self) -> CFG_NSEL_W < CFG_SPEC , 7 > { CFG_NSEL_W :: new (self) } # [doc = "Bits 10:12 - MSEL Mux selection. Please refer to the device specific datasheet for exact channels available."]
# [inline (always)]
# [must_use]
pub fn cfg_msel (& mut self) -> CFG_MSEL_W < CFG_SPEC , 10 > { CFG_MSEL_W :: new (self) } # [doc = "Bits 13:15 - Gain setting. Refer to TRM for enumeration information."]
# [inline (always)]
# [must_use]
pub fn cfg_gain (& mut self) -> CFG_GAIN_W < CFG_SPEC , 13 > { CFG_GAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CFG_SPEC ; impl crate :: RegisterSpec for CFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cfg::R`](R) reader structure"]
impl crate :: Readable for CFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
impl crate :: Writable for CFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CFG to value 0"]
impl crate :: Resettable for CFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RDY` reader - OA ready status."]
pub type STAT_RDY_R = crate :: BitReader < STAT_RDY_A > ; # [doc = "OA ready status.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RDY_A { # [doc = "0: FALSE"]
STAT_RDY_FALSE = 0 , # [doc = "1: TRUE"]
STAT_RDY_TRUE = 1 , } impl From < STAT_RDY_A > for bool { # [inline (always)]
fn from (variant : STAT_RDY_A) -> Self { variant as u8 != 0 } } impl STAT_RDY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RDY_A { match self . bits { false => STAT_RDY_A :: STAT_RDY_FALSE , true => STAT_RDY_A :: STAT_RDY_TRUE , } } # [doc = "FALSE"]
# [inline (always)]
pub fn is_stat_rdy_false (& self) -> bool { * self == STAT_RDY_A :: STAT_RDY_FALSE } # [doc = "TRUE"]
# [inline (always)]
pub fn is_stat_rdy_true (& self) -> bool { * self == STAT_RDY_A :: STAT_RDY_TRUE } } impl R { # [doc = "Bit 0 - OA ready status."]
# [inline (always)]
pub fn stat_rdy (& self) -> STAT_RDY_R { STAT_RDY_R :: new ((self . bits & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct I2C1 { _marker : PhantomData < * const () > } unsafe impl Send for I2C1 { } impl I2C1 { # [doc = r"Pointer to the register block"]
pub const PTR : * const i2c1 :: RegisterBlock = 0x400f_2000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const i2c1 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for I2C1 { type Target = i2c1 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for I2C1 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("I2C1") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod i2c1 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0800]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , # [doc = "0x808 - Peripheral Clock Configuration Register"]
pub clkcfg : CLKCFG , _reserved3 : [u8 ; 0x08]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved4 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , # [doc = "0x1004 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved6 : [u8 ; 0x10]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub int_event0_iidx : INT_EVENT0_IIDX , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub int_event0_imask : INT_EVENT0_IMASK , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub int_event0_ris : INT_EVENT0_RIS , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub int_event0_mis : INT_EVENT0_MIS , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub int_event0_iset : INT_EVENT0_ISET , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub int_event0_iclr : INT_EVENT0_ICLR , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1050 - Interrupt index"]
pub int_event1_iidx : INT_EVENT1_IIDX , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1058 - Interrupt mask"]
pub int_event1_imask : INT_EVENT1_IMASK , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1060 - Raw interrupt status"]
pub int_event1_ris : INT_EVENT1_RIS , _reserved16 : [u8 ; 0x04]
, # [doc = "0x1068 - Masked interrupt status"]
pub int_event1_mis : INT_EVENT1_MIS , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1070 - Interrupt set"]
pub int_event1_iset : INT_EVENT1_ISET , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1078 - Interrupt clear"]
pub int_event1_iclr : INT_EVENT1_ICLR , _reserved19 : [u8 ; 0x04]
, # [doc = "0x1080 - Interrupt index"]
pub int_event2_iidx : INT_EVENT2_IIDX , _reserved20 : [u8 ; 0x04]
, # [doc = "0x1088 - Interrupt mask"]
pub int_event2_imask : INT_EVENT2_IMASK , _reserved21 : [u8 ; 0x04]
, # [doc = "0x1090 - Raw interrupt status"]
pub int_event2_ris : INT_EVENT2_RIS , _reserved22 : [u8 ; 0x04]
, # [doc = "0x1098 - Masked interrupt status"]
pub int_event2_mis : INT_EVENT2_MIS , _reserved23 : [u8 ; 0x04]
, # [doc = "0x10a0 - Interrupt set"]
pub int_event2_iset : INT_EVENT2_ISET , _reserved24 : [u8 ; 0x04]
, # [doc = "0x10a8 - Interrupt clear"]
pub int_event2_iclr : INT_EVENT2_ICLR , _reserved25 : [u8 ; 0x34]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved26 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , _reserved27 : [u8 ; 0x0100]
, # [doc = "0x1200 - I2C Glitch Filter Control"]
pub gfctl : GFCTL , # [doc = "0x1204 - I2C Timeout Count Control Register"]
pub timeout_ctl : TIMEOUT_CTL , # [doc = "0x1208 - I2C Timeout Count Register"]
pub timeout_cnt : TIMEOUT_CNT , _reserved30 : [u8 ; 0x04]
, # [doc = "0x1210 - I2C Master Slave Address Register"]
pub msa : MSA , # [doc = "0x1214 - I2C Master Control Register"]
pub mctr : MCTR , # [doc = "0x1218 - I2C Master Status Register"]
pub msr : MSR , # [doc = "0x121c - I2C Master RXData"]
pub mrxdata : MRXDATA , # [doc = "0x1220 - I2C Master TXData"]
pub mtxdata : MTXDATA , # [doc = "0x1224 - I2C Master Timer Period"]
pub mtpr : MTPR , # [doc = "0x1228 - I2C Master Configuration"]
pub mcr : MCR , _reserved37 : [u8 ; 0x08]
, # [doc = "0x1234 - I2C Master Bus Monitor"]
pub mbmon : MBMON , # [doc = "0x1238 - I2C Master FIFO Control"]
pub mfifoctl : MFIFOCTL , # [doc = "0x123c - I2C Master FIFO Status Register"]
pub mfifosr : MFIFOSR , # [doc = "0x1240 - I2C master PEC control register"]
pub master_i2cpecctl : MASTER_I2CPECCTL , # [doc = "0x1244 - I2C master PEC status register"]
pub master_pecsr : MASTER_PECSR , _reserved42 : [u8 ; 0x08]
, # [doc = "0x1250 - I2C Slave Own Address"]
pub soar : SOAR , # [doc = "0x1254 - I2C Slave Own Address 2"]
pub soar2 : SOAR2 , # [doc = "0x1258 - I2C Slave Control Register"]
pub sctr : SCTR , # [doc = "0x125c - I2C Slave Status Register"]
pub ssr : SSR , # [doc = "0x1260 - I2C Slave RXData"]
pub srxdata : SRXDATA , # [doc = "0x1264 - I2C Slave TXData"]
pub stxdata : STXDATA , # [doc = "0x1268 - I2C Slave ACK Control"]
pub sackctl : SACKCTL , # [doc = "0x126c - I2C Slave FIFO Control"]
pub sfifoctl : SFIFOCTL , # [doc = "0x1270 - I2C Slave FIFO Status Register"]
pub sfifosr : SFIFOSR , # [doc = "0x1274 - I2C Slave PEC control register"]
pub slave_pecctl : SLAVE_PECCTL , # [doc = "0x1278 - I2C slave PEC status register"]
pub slave_pecsr : SLAVE_PECSR , } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKCFG (rw) register accessor: Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkcfg`]
module"]
pub type CLKCFG = crate :: Reg < clkcfg :: CLKCFG_SPEC > ; # [doc = "Peripheral Clock Configuration Register"]
pub mod clkcfg { # [doc = "Register `CLKCFG` reader"]
pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"]
pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_BLOCKASYNC` reader - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_R = crate :: BitReader < CLKCFG_BLOCKASYNC_A > ; # [doc = "Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_BLOCKASYNC_A { # [doc = "0: DISABLE"]
CLKCFG_BLOCKASYNC_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_BLOCKASYNC_ENABLE = 1 , } impl From < CLKCFG_BLOCKASYNC_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_BLOCKASYNC_A) -> Self { variant as u8 != 0 } } impl CLKCFG_BLOCKASYNC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_BLOCKASYNC_A { match self . bits { false => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE , true => CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_disable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_blockasync_enable (& self) -> bool { * self == CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE } } # [doc = "Field `CLKCFG_BLOCKASYNC` writer - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
pub type CLKCFG_BLOCKASYNC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_BLOCKASYNC_A > ; impl < 'a , REG , const O : u8 > CLKCFG_BLOCKASYNC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_blockasync_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_BLOCKASYNC_A :: CLKCFG_BLOCKASYNC_ENABLE) } } # [doc = "KEY to Allow State Change -- 0xA9\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_KEY_AW { # [doc = "169: _UNLOCK_W_"]
CLKCFG_KEY_UNLOCK = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - KEY to Allow State Change -- 0xA9"]
pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_UNLOCK_W_"]
# [inline (always)]
pub fn clkcfg_key_unlock (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK) } } impl R { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
pub fn clkcfg_blockasync (& self) -> CLKCFG_BLOCKASYNC_R { CLKCFG_BLOCKASYNC_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 8 - Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz"]
# [inline (always)]
# [must_use]
pub fn clkcfg_blockasync (& mut self) -> CLKCFG_BLOCKASYNC_W < CLKCFG_SPEC , 8 > { CLKCFG_BLOCKASYNC_W :: new (self) } # [doc = "Bits 24:31 - KEY to Allow State Change -- 0xA9"]
# [inline (always)]
# [must_use]
pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"]
impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"]
impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"]
impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iidx`]
module"]
pub type INT_EVENT0_IIDX = crate :: Reg < int_event0_iidx :: INT_EVENT0_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event0_iidx { # [doc = "Register `INT_EVENT0_IIDX` reader"]
pub type R = crate :: R < INT_EVENT0_IIDX_SPEC > ; # [doc = "Field `INT_EVENT0_IIDX_STAT` reader - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
pub type INT_EVENT0_IIDX_STAT_R = crate :: FieldReader < INT_EVENT0_IIDX_STAT_A > ; # [doc = "I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: MRXDONEFG"]
INT_EVENT0_IIDX_STAT_MRXDONEFG = 1 , # [doc = "2: MTXDONEFG"]
INT_EVENT0_IIDX_STAT_MTXDONEFG = 2 , # [doc = "3: MRXFIFOTRG"]
INT_EVENT0_IIDX_STAT_MRXFIFOTRG = 3 , # [doc = "4: MTXFIFOTRG"]
INT_EVENT0_IIDX_STAT_MTXFIFOTRG = 4 , # [doc = "5: MRXFIFOFULL"]
INT_EVENT0_IIDX_STAT_MRXFIFOFULL = 5 , # [doc = "6: MTX_EMPTY"]
INT_EVENT0_IIDX_STAT_MTX_EMPTY = 6 , # [doc = "8: MNACKFG"]
INT_EVENT0_IIDX_STAT_MNACKFG = 8 , # [doc = "9: MSTARTFG"]
INT_EVENT0_IIDX_STAT_MSTARTFG = 9 , # [doc = "10: MSTOPFG"]
INT_EVENT0_IIDX_STAT_MSTOPFG = 10 , # [doc = "11: MARBLOSTFG"]
INT_EVENT0_IIDX_STAT_MARBLOSTFG = 11 , # [doc = "12: MDMA_DONE1_CH2"]
INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2 = 12 , # [doc = "13: MDMA_DONE1_CH3"]
INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3 = 13 , # [doc = "14: MPEC_RX_ERR"]
INT_EVENT0_IIDX_STAT_MPEC_RX_ERR = 14 , # [doc = "15: TIMEOUTA"]
INT_EVENT0_IIDX_STAT_TIMEOUTA = 15 , # [doc = "16: TIMEOUTB"]
INT_EVENT0_IIDX_STAT_TIMEOUTB = 16 , # [doc = "17: SRXDONEFG"]
INT_EVENT0_IIDX_STAT_SRXDONEFG = 17 , # [doc = "18: STXDONEFG"]
INT_EVENT0_IIDX_STAT_STXDONEFG = 18 , # [doc = "19: SRXFIFOTRG"]
INT_EVENT0_IIDX_STAT_SRXFIFOTRG = 19 , # [doc = "20: STXFIFOTRG"]
INT_EVENT0_IIDX_STAT_STXFIFOTRG = 20 , # [doc = "21: SRXFIFOFULL"]
INT_EVENT0_IIDX_STAT_SRXFIFOFULL = 21 , # [doc = "22: STXEMPTY"]
INT_EVENT0_IIDX_STAT_STXEMPTY = 22 , # [doc = "23: SSTARTFG"]
INT_EVENT0_IIDX_STAT_SSTARTFG = 23 , # [doc = "24: SSTOPFG"]
INT_EVENT0_IIDX_STAT_SSTOPFG = 24 , # [doc = "25: SGENCALL"]
INT_EVENT0_IIDX_STAT_SGENCALL = 25 , # [doc = "26: SDMA_DONE1_CH2"]
INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2 = 26 , # [doc = "27: SDMA_DONE1_CH3"]
INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3 = 27 , # [doc = "28: SPEC_RX_ERR"]
INT_EVENT0_IIDX_STAT_SPEC_RX_ERR = 28 , # [doc = "29: STX_UNFL"]
INT_EVENT0_IIDX_STAT_STX_UNFL = 29 , # [doc = "30: SRX_OVFL"]
INT_EVENT0_IIDX_STAT_SRX_OVFL = 30 , # [doc = "31: SARBLOST"]
INT_EVENT0_IIDX_STAT_SARBLOST = 31 , # [doc = "32: INTR_OVFL"]
INT_EVENT0_IIDX_STAT_INTR_OVFL = 32 , } impl From < INT_EVENT0_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT0_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXDONEFG) , 2 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXDONEFG) , 3 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOTRG) , 4 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXFIFOTRG) , 5 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOFULL) , 6 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTX_EMPTY) , 8 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MNACKFG) , 9 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTARTFG) , 10 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTOPFG) , 11 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MARBLOSTFG) , 12 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2) , 13 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3) , 14 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MPEC_RX_ERR) , 15 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTA) , 16 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTB) , 17 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXDONEFG) , 18 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXDONEFG) , 19 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOTRG) , 20 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXFIFOTRG) , 21 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOFULL) , 22 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXEMPTY) , 23 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTARTFG) , 24 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTOPFG) , 25 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SGENCALL) , 26 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2) , 27 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3) , 28 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SPEC_RX_ERR) , 29 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STX_UNFL) , 30 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRX_OVFL) , 31 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SARBLOST) , 32 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_INTR_OVFL) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR } # [doc = "MRXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mrxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXDONEFG } # [doc = "MTXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mtxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXDONEFG } # [doc = "MRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mrxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOTRG } # [doc = "MTXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mtxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTXFIFOTRG } # [doc = "MRXFIFOFULL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mrxfifofull (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MRXFIFOFULL } # [doc = "MTX_EMPTY"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mtx_empty (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MTX_EMPTY } # [doc = "MNACKFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mnackfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MNACKFG } # [doc = "MSTARTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mstartfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTARTFG } # [doc = "MSTOPFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mstopfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MSTOPFG } # [doc = "MARBLOSTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_marblostfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MARBLOSTFG } # [doc = "MDMA_DONE1_CH2"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mdma_done1_ch2 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH2 } # [doc = "MDMA_DONE1_CH3"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mdma_done1_ch3 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MDMA_DONE1_CH3 } # [doc = "MPEC_RX_ERR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_mpec_rx_err (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MPEC_RX_ERR } # [doc = "TIMEOUTA"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_timeouta (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTA } # [doc = "TIMEOUTB"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_timeoutb (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TIMEOUTB } # [doc = "SRXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXDONEFG } # [doc = "STXDONEFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stxdonefg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXDONEFG } # [doc = "SRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOTRG } # [doc = "STXFIFOTRG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stxfifotrg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXFIFOTRG } # [doc = "SRXFIFOFULL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srxfifofull (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRXFIFOFULL } # [doc = "STXEMPTY"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stxempty (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STXEMPTY } # [doc = "SSTARTFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sstartfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTARTFG } # [doc = "SSTOPFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sstopfg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SSTOPFG } # [doc = "SGENCALL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sgencall (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SGENCALL } # [doc = "SDMA_DONE1_CH2"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sdma_done1_ch2 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH2 } # [doc = "SDMA_DONE1_CH3"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sdma_done1_ch3 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SDMA_DONE1_CH3 } # [doc = "SPEC_RX_ERR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_spec_rx_err (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SPEC_RX_ERR } # [doc = "STX_UNFL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_stx_unfl (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_STX_UNFL } # [doc = "SRX_OVFL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_srx_ovfl (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SRX_OVFL } # [doc = "SARBLOST"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_sarblost (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_SARBLOST } # [doc = "INTR_OVFL"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_intr_ovfl (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_INTR_OVFL } } impl R { # [doc = "Bits 0:7 - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event0_iidx_stat (& self) -> INT_EVENT0_IIDX_STAT_R { INT_EVENT0_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_imask`]
module"]
pub type INT_EVENT0_IMASK = crate :: Reg < int_event0_imask :: INT_EVENT0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event0_imask { # [doc = "Register `INT_EVENT0_IMASK` reader"]
pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"]
pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_MRXDONE` reader - Master Receive Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MRXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_MRXDONE_A > ; # [doc = "Master Receive Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MRXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_MRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MRXDONE_A { match self . bits { false => INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_CLR , true => INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mrxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mrxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_MRXDONE` writer - Master Receive Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MRXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mrxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXDONE_A :: INT_EVENT0_IMASK_MRXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MTXDONE` reader - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MTXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_MTXDONE_A > ; # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MTXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MTXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MTXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_MTXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MTXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MTXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MTXDONE_A { match self . bits { false => INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_CLR , true => INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mtxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mtxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_MTXDONE` writer - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MTXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mtxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXDONE_A :: INT_EVENT0_IMASK_MTXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOTRG_A :: INT_EVENT0_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXFIFOTRG_A :: INT_EVENT0_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_IMASK_MRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_IMASK_MRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_MRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MRXFIFOFULL_A { match self . bits { false => INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_CLR , true => INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifofull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mrxfifofull_set (& self) -> bool { * self == INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_MRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_IMASK_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MRXFIFOFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mrxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MRXFIFOFULL_A :: INT_EVENT0_IMASK_MRXFIFOFULL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MTXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_MTXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_MTXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MTXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MTXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_MTXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MTXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MTXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MTXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_CLR , true => INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mtxempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mtxempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MTXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mtxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MTXEMPTY_A :: INT_EVENT0_IMASK_MTXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MNACK` reader - Address/Data NACK Interrupt"]
pub type INT_EVENT0_IMASK_MNACK_R = crate :: BitReader < INT_EVENT0_IMASK_MNACK_A > ; # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MNACK_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MNACK_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MNACK_SET = 1 , } impl From < INT_EVENT0_IMASK_MNACK_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MNACK_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MNACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MNACK_A { match self . bits { false => INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_CLR , true => INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mnack_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mnack_set (& self) -> bool { * self == INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_SET } } # [doc = "Field `INT_EVENT0_IMASK_MNACK` writer - Address/Data NACK Interrupt"]
pub type INT_EVENT0_IMASK_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MNACK_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mnack_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MNACK_A :: INT_EVENT0_IMASK_MNACK_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MSTART` reader - START Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTART_R = crate :: BitReader < INT_EVENT0_IMASK_MSTART_A > ; # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MSTART_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MSTART_SET = 1 , } impl From < INT_EVENT0_IMASK_MSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MSTART_A { match self . bits { false => INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_CLR , true => INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mstart_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mstart_set (& self) -> bool { * self == INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_SET } } # [doc = "Field `INT_EVENT0_IMASK_MSTART` writer - START Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MSTART_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTART_A :: INT_EVENT0_IMASK_MSTART_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MSTOP` reader - STOP Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTOP_R = crate :: BitReader < INT_EVENT0_IMASK_MSTOP_A > ; # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MSTOP_SET = 1 , } impl From < INT_EVENT0_IMASK_MSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MSTOP_A { match self . bits { false => INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_CLR , true => INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mstop_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mstop_set (& self) -> bool { * self == INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_SET } } # [doc = "Field `INT_EVENT0_IMASK_MSTOP` writer - STOP Detection Interrupt"]
pub type INT_EVENT0_IMASK_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MSTOP_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MSTOP_A :: INT_EVENT0_IMASK_MSTOP_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MARBLOST` reader - Arbitration Lost Interrupt"]
pub type INT_EVENT0_IMASK_MARBLOST_R = crate :: BitReader < INT_EVENT0_IMASK_MARBLOST_A > ; # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MARBLOST_SET = 1 , } impl From < INT_EVENT0_IMASK_MARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MARBLOST_A { match self . bits { false => INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_CLR , true => INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_marblost_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_marblost_set (& self) -> bool { * self == INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_SET } } # [doc = "Field `INT_EVENT0_IMASK_MARBLOST` writer - Arbitration Lost Interrupt"]
pub type INT_EVENT0_IMASK_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MARBLOST_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_marblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MARBLOST_A :: INT_EVENT0_IMASK_MARBLOST_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_IMASK_MDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_IMASK_MDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_CLR , true => INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MDMA_DONE1_2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_2_A :: INT_EVENT0_IMASK_MDMA_DONE1_2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_IMASK_MDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_IMASK_MDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_CLR , true => INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_IMASK_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MDMA_DONE1_3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MDMA_DONE1_3_A :: INT_EVENT0_IMASK_MDMA_DONE1_3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MPEC_RX_ERR` reader - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_MPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_IMASK_MPEC_RX_ERR_A > ; # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_IMASK_MPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_CLR , true => INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_mpec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_mpec_rx_err_set (& self) -> bool { * self == INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MPEC_RX_ERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_mpec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MPEC_RX_ERR_A :: INT_EVENT0_IMASK_MPEC_RX_ERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTA` reader - Timeout A Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTA_R = crate :: BitReader < INT_EVENT0_IMASK_TIMEOUTA_A > ; # [doc = "Timeout A Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TIMEOUTA_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TIMEOUTA_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_IMASK_TIMEOUTA_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TIMEOUTA_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TIMEOUTA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TIMEOUTA_A { match self . bits { false => INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_CLR , true => INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_timeouta_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_timeouta_set (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_SET } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTA` writer - Timeout A Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TIMEOUTA_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_timeouta_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTA_A :: INT_EVENT0_IMASK_TIMEOUTA_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTB` reader - Timeout B Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTB_R = crate :: BitReader < INT_EVENT0_IMASK_TIMEOUTB_A > ; # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TIMEOUTB_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TIMEOUTB_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_IMASK_TIMEOUTB_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TIMEOUTB_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TIMEOUTB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TIMEOUTB_A { match self . bits { false => INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_CLR , true => INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_timeoutb_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_timeoutb_set (& self) -> bool { * self == INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_SET } } # [doc = "Field `INT_EVENT0_IMASK_TIMEOUTB` writer - Timeout B Interrupt"]
pub type INT_EVENT0_IMASK_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TIMEOUTB_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_timeoutb_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TIMEOUTB_A :: INT_EVENT0_IMASK_TIMEOUTB_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRXDONE` reader - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_IMASK_SRXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_SRXDONE_A > ; # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_SRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRXDONE_A { match self . bits { false => INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_CLR , true => INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_IMASK_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXDONE_A :: INT_EVENT0_IMASK_SRXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STXDONE` reader - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_STXDONE_R = crate :: BitReader < INT_EVENT0_IMASK_STXDONE_A > ; # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STXDONE_SET = 1 , } impl From < INT_EVENT0_IMASK_STXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STXDONE_A { match self . bits { false => INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_CLR , true => INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stxdone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stxdone_set (& self) -> bool { * self == INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_STXDONE` writer - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_IMASK_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STXDONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXDONE_A :: INT_EVENT0_IMASK_STXDONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOTRG_A :: INT_EVENT0_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT0_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_IMASK_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_CLR , true => INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXFIFOTRG_A :: INT_EVENT0_IMASK_STXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
pub type INT_EVENT0_IMASK_SRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_IMASK_SRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an Slave RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_IMASK_SRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRXFIFOFULL_A { match self . bits { false => INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_CLR , true => INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifofull_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srxfifofull_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
pub type INT_EVENT0_IMASK_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRXFIFOFULL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRXFIFOFULL_A :: INT_EVENT0_IMASK_SRXFIFOFULL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STXEMPTY` reader - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_STXEMPTY_R = crate :: BitReader < INT_EVENT0_IMASK_STXEMPTY_A > ; # [doc = "Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_IMASK_STXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STXEMPTY_A { match self . bits { false => INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_CLR , true => INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stxempty_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stxempty_set (& self) -> bool { * self == INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_SET } } # [doc = "Field `INT_EVENT0_IMASK_STXEMPTY` writer - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_IMASK_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STXEMPTY_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STXEMPTY_A :: INT_EVENT0_IMASK_STXEMPTY_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SSTART` reader - Start Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTART_R = crate :: BitReader < INT_EVENT0_IMASK_SSTART_A > ; # [doc = "Start Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SSTART_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SSTART_SET = 1 , } impl From < INT_EVENT0_IMASK_SSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SSTART_A { match self . bits { false => INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_CLR , true => INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sstart_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sstart_set (& self) -> bool { * self == INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_SET } } # [doc = "Field `INT_EVENT0_IMASK_SSTART` writer - Start Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SSTART_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTART_A :: INT_EVENT0_IMASK_SSTART_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SSTOP` reader - Stop Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTOP_R = crate :: BitReader < INT_EVENT0_IMASK_SSTOP_A > ; # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SSTOP_SET = 1 , } impl From < INT_EVENT0_IMASK_SSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SSTOP_A { match self . bits { false => INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_CLR , true => INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sstop_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sstop_set (& self) -> bool { * self == INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_SET } } # [doc = "Field `INT_EVENT0_IMASK_SSTOP` writer - Stop Condition Interrupt"]
pub type INT_EVENT0_IMASK_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SSTOP_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SSTOP_A :: INT_EVENT0_IMASK_SSTOP_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SGENCALL` reader - General Call Interrupt"]
pub type INT_EVENT0_IMASK_SGENCALL_R = crate :: BitReader < INT_EVENT0_IMASK_SGENCALL_A > ; # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SGENCALL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SGENCALL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SGENCALL_SET = 1 , } impl From < INT_EVENT0_IMASK_SGENCALL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SGENCALL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SGENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SGENCALL_A { match self . bits { false => INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_CLR , true => INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sgencall_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sgencall_set (& self) -> bool { * self == INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_SET } } # [doc = "Field `INT_EVENT0_IMASK_SGENCALL` writer - General Call Interrupt"]
pub type INT_EVENT0_IMASK_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SGENCALL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sgencall_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SGENCALL_A :: INT_EVENT0_IMASK_SGENCALL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_2` reader - Slave DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_IMASK_SDMA_DONE1_2_A > ; # [doc = "Slave DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_IMASK_SDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_CLR , true => INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_2` writer - Slave DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SDMA_DONE1_2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_2_A :: INT_EVENT0_IMASK_SDMA_DONE1_2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_3` reader - Slave DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_IMASK_SDMA_DONE1_3_A > ; # [doc = "Slave DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_IMASK_SDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_CLR , true => INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_IMASK_SDMA_DONE1_3` writer - Slave DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_IMASK_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SDMA_DONE1_3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SDMA_DONE1_3_A :: INT_EVENT0_IMASK_SDMA_DONE1_3_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SPEC_RX_ERR` reader - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_SPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_IMASK_SPEC_RX_ERR_A > ; # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_IMASK_SPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_CLR , true => INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_spec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_spec_rx_err_set (& self) -> bool { * self == INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_IMASK_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_IMASK_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SPEC_RX_ERR_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_spec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SPEC_RX_ERR_A :: INT_EVENT0_IMASK_SPEC_RX_ERR_SET) } } # [doc = "Field `INT_EVENT0_IMASK_STX_UNFL` reader - Slave TX FIFO underflow"]
pub type INT_EVENT0_IMASK_STX_UNFL_R = crate :: BitReader < INT_EVENT0_IMASK_STX_UNFL_A > ; # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_STX_UNFL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_STX_UNFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_IMASK_STX_UNFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_STX_UNFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_STX_UNFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_STX_UNFL_A { match self . bits { false => INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_CLR , true => INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_stx_unfl_clr (& self) -> bool { * self == INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_stx_unfl_set (& self) -> bool { * self == INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_SET } } # [doc = "Field `INT_EVENT0_IMASK_STX_UNFL` writer - Slave TX FIFO underflow"]
pub type INT_EVENT0_IMASK_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_STX_UNFL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_stx_unfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_STX_UNFL_A :: INT_EVENT0_IMASK_STX_UNFL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SRX_OVFL` reader - Slave RX FIFO overflow"]
pub type INT_EVENT0_IMASK_SRX_OVFL_R = crate :: BitReader < INT_EVENT0_IMASK_SRX_OVFL_A > ; # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SRX_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SRX_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_IMASK_SRX_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SRX_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SRX_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SRX_OVFL_A { match self . bits { false => INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_CLR , true => INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_srx_ovfl_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_srx_ovfl_set (& self) -> bool { * self == INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_SET } } # [doc = "Field `INT_EVENT0_IMASK_SRX_OVFL` writer - Slave RX FIFO overflow"]
pub type INT_EVENT0_IMASK_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SRX_OVFL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_srx_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SRX_OVFL_A :: INT_EVENT0_IMASK_SRX_OVFL_SET) } } # [doc = "Field `INT_EVENT0_IMASK_SARBLOST` reader - Slave Arbitration Lost"]
pub type INT_EVENT0_IMASK_SARBLOST_R = crate :: BitReader < INT_EVENT0_IMASK_SARBLOST_A > ; # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_SARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_SARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_SARBLOST_SET = 1 , } impl From < INT_EVENT0_IMASK_SARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_SARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_SARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_SARBLOST_A { match self . bits { false => INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_CLR , true => INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_sarblost_clr (& self) -> bool { * self == INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_sarblost_set (& self) -> bool { * self == INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_SET } } # [doc = "Field `INT_EVENT0_IMASK_SARBLOST` writer - Slave Arbitration Lost"]
pub type INT_EVENT0_IMASK_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_SARBLOST_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_sarblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_SARBLOST_A :: INT_EVENT0_IMASK_SARBLOST_SET) } } # [doc = "Field `INT_EVENT0_IMASK_INTR_OVFL` reader - Interrupt Overflow Interrupt Mask"]
pub type INT_EVENT0_IMASK_INTR_OVFL_R = crate :: BitReader < INT_EVENT0_IMASK_INTR_OVFL_A > ; # [doc = "Interrupt Overflow Interrupt Mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_INTR_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_INTR_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_IMASK_INTR_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_INTR_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_INTR_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_INTR_OVFL_A { match self . bits { false => INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_CLR , true => INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_intr_ovfl_clr (& self) -> bool { * self == INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_intr_ovfl_set (& self) -> bool { * self == INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_SET } } # [doc = "Field `INT_EVENT0_IMASK_INTR_OVFL` writer - Interrupt Overflow Interrupt Mask"]
pub type INT_EVENT0_IMASK_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_INTR_OVFL_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_intr_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_INTR_OVFL_A :: INT_EVENT0_IMASK_INTR_OVFL_SET) } } impl R { # [doc = "Bit 0 - Master Receive Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mrxdone (& self) -> INT_EVENT0_IMASK_MRXDONE_R { INT_EVENT0_IMASK_MRXDONE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mtxdone (& self) -> INT_EVENT0_IMASK_MTXDONE_R { INT_EVENT0_IMASK_MTXDONE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event0_imask_mrxfifotrg (& self) -> INT_EVENT0_IMASK_MRXFIFOTRG_R { INT_EVENT0_IMASK_MRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event0_imask_mtxfifotrg (& self) -> INT_EVENT0_IMASK_MTXFIFOTRG_R { INT_EVENT0_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_imask_mrxfifofull (& self) -> INT_EVENT0_IMASK_MRXFIFOFULL_R { INT_EVENT0_IMASK_MRXFIFOFULL_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_imask_mtxempty (& self) -> INT_EVENT0_IMASK_MTXEMPTY_R { INT_EVENT0_IMASK_MTXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mnack (& self) -> INT_EVENT0_IMASK_MNACK_R { INT_EVENT0_IMASK_MNACK_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mstart (& self) -> INT_EVENT0_IMASK_MSTART_R { INT_EVENT0_IMASK_MSTART_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mstop (& self) -> INT_EVENT0_IMASK_MSTOP_R { INT_EVENT0_IMASK_MSTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
pub fn int_event0_imask_marblost (& self) -> INT_EVENT0_IMASK_MARBLOST_R { INT_EVENT0_IMASK_MARBLOST_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_2 (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_2_R { INT_EVENT0_IMASK_MDMA_DONE1_2_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_imask_mdma_done1_3 (& self) -> INT_EVENT0_IMASK_MDMA_DONE1_3_R { INT_EVENT0_IMASK_MDMA_DONE1_3_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_imask_mpec_rx_err (& self) -> INT_EVENT0_IMASK_MPEC_RX_ERR_R { INT_EVENT0_IMASK_MPEC_RX_ERR_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
pub fn int_event0_imask_timeouta (& self) -> INT_EVENT0_IMASK_TIMEOUTA_R { INT_EVENT0_IMASK_TIMEOUTA_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
pub fn int_event0_imask_timeoutb (& self) -> INT_EVENT0_IMASK_TIMEOUTB_R { INT_EVENT0_IMASK_TIMEOUTB_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
pub fn int_event0_imask_srxdone (& self) -> INT_EVENT0_IMASK_SRXDONE_R { INT_EVENT0_IMASK_SRXDONE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_imask_stxdone (& self) -> INT_EVENT0_IMASK_STXDONE_R { INT_EVENT0_IMASK_STXDONE_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event0_imask_srxfifotrg (& self) -> INT_EVENT0_IMASK_SRXFIFOTRG_R { INT_EVENT0_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event0_imask_stxfifotrg (& self) -> INT_EVENT0_IMASK_STXFIFOTRG_R { INT_EVENT0_IMASK_STXFIFOTRG_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
# [inline (always)]
pub fn int_event0_imask_srxfifofull (& self) -> INT_EVENT0_IMASK_SRXFIFOFULL_R { INT_EVENT0_IMASK_SRXFIFOFULL_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_imask_stxempty (& self) -> INT_EVENT0_IMASK_STXEMPTY_R { INT_EVENT0_IMASK_STXEMPTY_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
pub fn int_event0_imask_sstart (& self) -> INT_EVENT0_IMASK_SSTART_R { INT_EVENT0_IMASK_SSTART_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
pub fn int_event0_imask_sstop (& self) -> INT_EVENT0_IMASK_SSTOP_R { INT_EVENT0_IMASK_SSTOP_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
pub fn int_event0_imask_sgencall (& self) -> INT_EVENT0_IMASK_SGENCALL_R { INT_EVENT0_IMASK_SGENCALL_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - Slave DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_2 (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_2_R { INT_EVENT0_IMASK_SDMA_DONE1_2_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - Slave DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_imask_sdma_done1_3 (& self) -> INT_EVENT0_IMASK_SDMA_DONE1_3_R { INT_EVENT0_IMASK_SDMA_DONE1_3_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_imask_spec_rx_err (& self) -> INT_EVENT0_IMASK_SPEC_RX_ERR_R { INT_EVENT0_IMASK_SPEC_RX_ERR_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
pub fn int_event0_imask_stx_unfl (& self) -> INT_EVENT0_IMASK_STX_UNFL_R { INT_EVENT0_IMASK_STX_UNFL_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
pub fn int_event0_imask_srx_ovfl (& self) -> INT_EVENT0_IMASK_SRX_OVFL_R { INT_EVENT0_IMASK_SRX_OVFL_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
pub fn int_event0_imask_sarblost (& self) -> INT_EVENT0_IMASK_SARBLOST_R { INT_EVENT0_IMASK_SARBLOST_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Interrupt Overflow Interrupt Mask"]
# [inline (always)]
pub fn int_event0_imask_intr_ovfl (& self) -> INT_EVENT0_IMASK_INTR_OVFL_R { INT_EVENT0_IMASK_INTR_OVFL_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mrxdone (& mut self) -> INT_EVENT0_IMASK_MRXDONE_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mtxdone (& mut self) -> INT_EVENT0_IMASK_MTXDONE_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mrxfifotrg (& mut self) -> INT_EVENT0_IMASK_MRXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mtxfifotrg (& mut self) -> INT_EVENT0_IMASK_MTXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mrxfifofull (& mut self) -> INT_EVENT0_IMASK_MRXFIFOFULL_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mtxempty (& mut self) -> INT_EVENT0_IMASK_MTXEMPTY_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mnack (& mut self) -> INT_EVENT0_IMASK_MNACK_W < INT_EVENT0_IMASK_SPEC , 7 > { INT_EVENT0_IMASK_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mstart (& mut self) -> INT_EVENT0_IMASK_MSTART_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mstop (& mut self) -> INT_EVENT0_IMASK_MSTOP_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_marblost (& mut self) -> INT_EVENT0_IMASK_MARBLOST_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mdma_done1_2 (& mut self) -> INT_EVENT0_IMASK_MDMA_DONE1_2_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mdma_done1_3 (& mut self) -> INT_EVENT0_IMASK_MDMA_DONE1_3_W < INT_EVENT0_IMASK_SPEC , 12 > { INT_EVENT0_IMASK_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_mpec_rx_err (& mut self) -> INT_EVENT0_IMASK_MPEC_RX_ERR_W < INT_EVENT0_IMASK_SPEC , 13 > { INT_EVENT0_IMASK_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_timeouta (& mut self) -> INT_EVENT0_IMASK_TIMEOUTA_W < INT_EVENT0_IMASK_SPEC , 14 > { INT_EVENT0_IMASK_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_timeoutb (& mut self) -> INT_EVENT0_IMASK_TIMEOUTB_W < INT_EVENT0_IMASK_SPEC , 15 > { INT_EVENT0_IMASK_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srxdone (& mut self) -> INT_EVENT0_IMASK_SRXDONE_W < INT_EVENT0_IMASK_SPEC , 16 > { INT_EVENT0_IMASK_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stxdone (& mut self) -> INT_EVENT0_IMASK_STXDONE_W < INT_EVENT0_IMASK_SPEC , 17 > { INT_EVENT0_IMASK_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srxfifotrg (& mut self) -> INT_EVENT0_IMASK_SRXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 18 > { INT_EVENT0_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stxfifotrg (& mut self) -> INT_EVENT0_IMASK_STXFIFOTRG_W < INT_EVENT0_IMASK_SPEC , 19 > { INT_EVENT0_IMASK_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an Slave RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srxfifofull (& mut self) -> INT_EVENT0_IMASK_SRXFIFOFULL_W < INT_EVENT0_IMASK_SPEC , 20 > { INT_EVENT0_IMASK_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Slave Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stxempty (& mut self) -> INT_EVENT0_IMASK_STXEMPTY_W < INT_EVENT0_IMASK_SPEC , 21 > { INT_EVENT0_IMASK_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sstart (& mut self) -> INT_EVENT0_IMASK_SSTART_W < INT_EVENT0_IMASK_SPEC , 22 > { INT_EVENT0_IMASK_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sstop (& mut self) -> INT_EVENT0_IMASK_SSTOP_W < INT_EVENT0_IMASK_SPEC , 23 > { INT_EVENT0_IMASK_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sgencall (& mut self) -> INT_EVENT0_IMASK_SGENCALL_W < INT_EVENT0_IMASK_SPEC , 24 > { INT_EVENT0_IMASK_SGENCALL_W :: new (self) } # [doc = "Bit 25 - Slave DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sdma_done1_2 (& mut self) -> INT_EVENT0_IMASK_SDMA_DONE1_2_W < INT_EVENT0_IMASK_SPEC , 25 > { INT_EVENT0_IMASK_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - Slave DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sdma_done1_3 (& mut self) -> INT_EVENT0_IMASK_SDMA_DONE1_3_W < INT_EVENT0_IMASK_SPEC , 26 > { INT_EVENT0_IMASK_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_spec_rx_err (& mut self) -> INT_EVENT0_IMASK_SPEC_RX_ERR_W < INT_EVENT0_IMASK_SPEC , 27 > { INT_EVENT0_IMASK_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_stx_unfl (& mut self) -> INT_EVENT0_IMASK_STX_UNFL_W < INT_EVENT0_IMASK_SPEC , 28 > { INT_EVENT0_IMASK_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_srx_ovfl (& mut self) -> INT_EVENT0_IMASK_SRX_OVFL_W < INT_EVENT0_IMASK_SPEC , 29 > { INT_EVENT0_IMASK_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_sarblost (& mut self) -> INT_EVENT0_IMASK_SARBLOST_W < INT_EVENT0_IMASK_SPEC , 30 > { INT_EVENT0_IMASK_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt Overflow Interrupt Mask"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_intr_ovfl (& mut self) -> INT_EVENT0_IMASK_INTR_OVFL_W < INT_EVENT0_IMASK_SPEC , 31 > { INT_EVENT0_IMASK_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_ris`]
module"]
pub type INT_EVENT0_RIS = crate :: Reg < int_event0_ris :: INT_EVENT0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event0_ris { # [doc = "Register `INT_EVENT0_RIS` reader"]
pub type R = crate :: R < INT_EVENT0_RIS_SPEC > ; # [doc = "Field `INT_EVENT0_RIS_MRXDONE` reader - Master Receive Transaction completed Interrupt"]
pub type INT_EVENT0_RIS_MRXDONE_R = crate :: BitReader < INT_EVENT0_RIS_MRXDONE_A > ; # [doc = "Master Receive Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MRXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_MRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MRXDONE_A { match self . bits { false => INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_CLR , true => INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mrxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mrxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_MRXDONE_A :: INT_EVENT0_RIS_MRXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_MTXDONE` reader - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_RIS_MTXDONE_R = crate :: BitReader < INT_EVENT0_RIS_MTXDONE_A > ; # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MTXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MTXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MTXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_MTXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MTXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MTXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MTXDONE_A { match self . bits { false => INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_CLR , true => INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mtxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mtxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_MTXDONE_A :: INT_EVENT0_RIS_MTXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_RIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_CLR , true => INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOTRG_A :: INT_EVENT0_RIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_RIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_CLR , true => INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_MTXFIFOTRG_A :: INT_EVENT0_RIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_MRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_RIS_MRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_RIS_MRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_RIS_MRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MRXFIFOFULL_A { match self . bits { false => INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_CLR , true => INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifofull_clr (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mrxfifofull_set (& self) -> bool { * self == INT_EVENT0_RIS_MRXFIFOFULL_A :: INT_EVENT0_RIS_MRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_RIS_MTXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_RIS_MTXEMPTY_R = crate :: BitReader < INT_EVENT0_RIS_MTXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MTXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MTXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_RIS_MTXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MTXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MTXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MTXEMPTY_A { match self . bits { false => INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_CLR , true => INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mtxempty_clr (& self) -> bool { * self == INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mtxempty_set (& self) -> bool { * self == INT_EVENT0_RIS_MTXEMPTY_A :: INT_EVENT0_RIS_MTXEMPTY_SET } } # [doc = "Field `INT_EVENT0_RIS_MNACK` reader - Address/Data NACK Interrupt"]
pub type INT_EVENT0_RIS_MNACK_R = crate :: BitReader < INT_EVENT0_RIS_MNACK_A > ; # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MNACK_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MNACK_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MNACK_SET = 1 , } impl From < INT_EVENT0_RIS_MNACK_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MNACK_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MNACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MNACK_A { match self . bits { false => INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_CLR , true => INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mnack_clr (& self) -> bool { * self == INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mnack_set (& self) -> bool { * self == INT_EVENT0_RIS_MNACK_A :: INT_EVENT0_RIS_MNACK_SET } } # [doc = "Field `INT_EVENT0_RIS_MSTART` reader - START Detection Interrupt"]
pub type INT_EVENT0_RIS_MSTART_R = crate :: BitReader < INT_EVENT0_RIS_MSTART_A > ; # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MSTART_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MSTART_SET = 1 , } impl From < INT_EVENT0_RIS_MSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MSTART_A { match self . bits { false => INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_CLR , true => INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mstart_clr (& self) -> bool { * self == INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mstart_set (& self) -> bool { * self == INT_EVENT0_RIS_MSTART_A :: INT_EVENT0_RIS_MSTART_SET } } # [doc = "Field `INT_EVENT0_RIS_MSTOP` reader - STOP Detection Interrupt"]
pub type INT_EVENT0_RIS_MSTOP_R = crate :: BitReader < INT_EVENT0_RIS_MSTOP_A > ; # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MSTOP_SET = 1 , } impl From < INT_EVENT0_RIS_MSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MSTOP_A { match self . bits { false => INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_CLR , true => INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mstop_clr (& self) -> bool { * self == INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mstop_set (& self) -> bool { * self == INT_EVENT0_RIS_MSTOP_A :: INT_EVENT0_RIS_MSTOP_SET } } # [doc = "Field `INT_EVENT0_RIS_MARBLOST` reader - Arbitration Lost Interrupt"]
pub type INT_EVENT0_RIS_MARBLOST_R = crate :: BitReader < INT_EVENT0_RIS_MARBLOST_A > ; # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MARBLOST_SET = 1 , } impl From < INT_EVENT0_RIS_MARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MARBLOST_A { match self . bits { false => INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_CLR , true => INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_marblost_clr (& self) -> bool { * self == INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_marblost_set (& self) -> bool { * self == INT_EVENT0_RIS_MARBLOST_A :: INT_EVENT0_RIS_MARBLOST_SET } } # [doc = "Field `INT_EVENT0_RIS_MDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_RIS_MDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_RIS_MDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_RIS_MDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_CLR , true => INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_2_A :: INT_EVENT0_RIS_MDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_RIS_MDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_RIS_MDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_RIS_MDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_RIS_MDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_CLR , true => INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_RIS_MDMA_DONE1_3_A :: INT_EVENT0_RIS_MDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_RIS_MPEC_RX_ERR` reader - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_RIS_MPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_RIS_MPEC_RX_ERR_A > ; # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_RIS_MPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_CLR , true => INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_mpec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_mpec_rx_err_set (& self) -> bool { * self == INT_EVENT0_RIS_MPEC_RX_ERR_A :: INT_EVENT0_RIS_MPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_RIS_TIMEOUTA` reader - Timeout A Interrupt"]
pub type INT_EVENT0_RIS_TIMEOUTA_R = crate :: BitReader < INT_EVENT0_RIS_TIMEOUTA_A > ; # [doc = "Timeout A Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TIMEOUTA_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TIMEOUTA_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_RIS_TIMEOUTA_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TIMEOUTA_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TIMEOUTA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TIMEOUTA_A { match self . bits { false => INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_CLR , true => INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_timeouta_clr (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_timeouta_set (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTA_A :: INT_EVENT0_RIS_TIMEOUTA_SET } } # [doc = "Field `INT_EVENT0_RIS_TIMEOUTB` reader - Timeout B Interrupt"]
pub type INT_EVENT0_RIS_TIMEOUTB_R = crate :: BitReader < INT_EVENT0_RIS_TIMEOUTB_A > ; # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TIMEOUTB_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TIMEOUTB_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_RIS_TIMEOUTB_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TIMEOUTB_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TIMEOUTB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TIMEOUTB_A { match self . bits { false => INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_CLR , true => INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_timeoutb_clr (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_timeoutb_set (& self) -> bool { * self == INT_EVENT0_RIS_TIMEOUTB_A :: INT_EVENT0_RIS_TIMEOUTB_SET } } # [doc = "Field `INT_EVENT0_RIS_SRXDONE` reader - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_RIS_SRXDONE_R = crate :: BitReader < INT_EVENT0_RIS_SRXDONE_A > ; # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_SRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRXDONE_A { match self . bits { false => INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_CLR , true => INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_SRXDONE_A :: INT_EVENT0_RIS_SRXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_STXDONE` reader - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_RIS_STXDONE_R = crate :: BitReader < INT_EVENT0_RIS_STXDONE_A > ; # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STXDONE_SET = 1 , } impl From < INT_EVENT0_RIS_STXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STXDONE_A { match self . bits { false => INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_CLR , true => INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stxdone_clr (& self) -> bool { * self == INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stxdone_set (& self) -> bool { * self == INT_EVENT0_RIS_STXDONE_A :: INT_EVENT0_RIS_STXDONE_SET } } # [doc = "Field `INT_EVENT0_RIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_RIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_CLR , true => INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOTRG_A :: INT_EVENT0_RIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_RIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT0_RIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_RIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_CLR , true => INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stxfifotrg_set (& self) -> bool { * self == INT_EVENT0_RIS_STXFIFOTRG_A :: INT_EVENT0_RIS_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_RIS_SRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_RIS_SRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_RIS_SRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_RIS_SRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRXFIFOFULL_A { match self . bits { false => INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_CLR , true => INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifofull_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srxfifofull_set (& self) -> bool { * self == INT_EVENT0_RIS_SRXFIFOFULL_A :: INT_EVENT0_RIS_SRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_RIS_STXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_RIS_STXEMPTY_R = crate :: BitReader < INT_EVENT0_RIS_STXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_RIS_STXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STXEMPTY_A { match self . bits { false => INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_CLR , true => INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stxempty_clr (& self) -> bool { * self == INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stxempty_set (& self) -> bool { * self == INT_EVENT0_RIS_STXEMPTY_A :: INT_EVENT0_RIS_STXEMPTY_SET } } # [doc = "Field `INT_EVENT0_RIS_SSTART` reader - Start Condition Interrupt"]
pub type INT_EVENT0_RIS_SSTART_R = crate :: BitReader < INT_EVENT0_RIS_SSTART_A > ; # [doc = "Start Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SSTART_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SSTART_SET = 1 , } impl From < INT_EVENT0_RIS_SSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SSTART_A { match self . bits { false => INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_CLR , true => INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sstart_clr (& self) -> bool { * self == INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sstart_set (& self) -> bool { * self == INT_EVENT0_RIS_SSTART_A :: INT_EVENT0_RIS_SSTART_SET } } # [doc = "Field `INT_EVENT0_RIS_SSTOP` reader - Stop Condition Interrupt"]
pub type INT_EVENT0_RIS_SSTOP_R = crate :: BitReader < INT_EVENT0_RIS_SSTOP_A > ; # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SSTOP_SET = 1 , } impl From < INT_EVENT0_RIS_SSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SSTOP_A { match self . bits { false => INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_CLR , true => INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sstop_clr (& self) -> bool { * self == INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sstop_set (& self) -> bool { * self == INT_EVENT0_RIS_SSTOP_A :: INT_EVENT0_RIS_SSTOP_SET } } # [doc = "Field `INT_EVENT0_RIS_SGENCALL` reader - General Call Interrupt"]
pub type INT_EVENT0_RIS_SGENCALL_R = crate :: BitReader < INT_EVENT0_RIS_SGENCALL_A > ; # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SGENCALL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SGENCALL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SGENCALL_SET = 1 , } impl From < INT_EVENT0_RIS_SGENCALL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SGENCALL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SGENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SGENCALL_A { match self . bits { false => INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_CLR , true => INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sgencall_clr (& self) -> bool { * self == INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sgencall_set (& self) -> bool { * self == INT_EVENT0_RIS_SGENCALL_A :: INT_EVENT0_RIS_SGENCALL_SET } } # [doc = "Field `INT_EVENT0_RIS_SDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_RIS_SDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_RIS_SDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_RIS_SDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_CLR , true => INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_2_A :: INT_EVENT0_RIS_SDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_RIS_SDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_RIS_SDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_RIS_SDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_RIS_SDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_CLR , true => INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_RIS_SDMA_DONE1_3_A :: INT_EVENT0_RIS_SDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_RIS_SPEC_RX_ERR` reader - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_RIS_SPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_RIS_SPEC_RX_ERR_A > ; # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_RIS_SPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_CLR , true => INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_spec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_spec_rx_err_set (& self) -> bool { * self == INT_EVENT0_RIS_SPEC_RX_ERR_A :: INT_EVENT0_RIS_SPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_RIS_STX_UNFL` reader - Slave TX FIFO underflow"]
pub type INT_EVENT0_RIS_STX_UNFL_R = crate :: BitReader < INT_EVENT0_RIS_STX_UNFL_A > ; # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_STX_UNFL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_STX_UNFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_RIS_STX_UNFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_STX_UNFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_STX_UNFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_STX_UNFL_A { match self . bits { false => INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_CLR , true => INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_stx_unfl_clr (& self) -> bool { * self == INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_stx_unfl_set (& self) -> bool { * self == INT_EVENT0_RIS_STX_UNFL_A :: INT_EVENT0_RIS_STX_UNFL_SET } } # [doc = "Field `INT_EVENT0_RIS_SRX_OVFL` reader - Slave RX FIFO overflow"]
pub type INT_EVENT0_RIS_SRX_OVFL_R = crate :: BitReader < INT_EVENT0_RIS_SRX_OVFL_A > ; # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SRX_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SRX_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_RIS_SRX_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SRX_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SRX_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SRX_OVFL_A { match self . bits { false => INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_CLR , true => INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_srx_ovfl_clr (& self) -> bool { * self == INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_srx_ovfl_set (& self) -> bool { * self == INT_EVENT0_RIS_SRX_OVFL_A :: INT_EVENT0_RIS_SRX_OVFL_SET } } # [doc = "Field `INT_EVENT0_RIS_SARBLOST` reader - Slave Arbitration Lost"]
pub type INT_EVENT0_RIS_SARBLOST_R = crate :: BitReader < INT_EVENT0_RIS_SARBLOST_A > ; # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_SARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_SARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_SARBLOST_SET = 1 , } impl From < INT_EVENT0_RIS_SARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_SARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_SARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_SARBLOST_A { match self . bits { false => INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_CLR , true => INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_sarblost_clr (& self) -> bool { * self == INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_sarblost_set (& self) -> bool { * self == INT_EVENT0_RIS_SARBLOST_A :: INT_EVENT0_RIS_SARBLOST_SET } } # [doc = "Field `INT_EVENT0_RIS_INTR_OVFL` reader - Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced"]
pub type INT_EVENT0_RIS_INTR_OVFL_R = crate :: BitReader < INT_EVENT0_RIS_INTR_OVFL_A > ; # [doc = "Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_INTR_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_INTR_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_RIS_INTR_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_INTR_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_INTR_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_INTR_OVFL_A { match self . bits { false => INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_CLR , true => INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_intr_ovfl_clr (& self) -> bool { * self == INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_intr_ovfl_set (& self) -> bool { * self == INT_EVENT0_RIS_INTR_OVFL_A :: INT_EVENT0_RIS_INTR_OVFL_SET } } impl R { # [doc = "Bit 0 - Master Receive Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mrxdone (& self) -> INT_EVENT0_RIS_MRXDONE_R { INT_EVENT0_RIS_MRXDONE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mtxdone (& self) -> INT_EVENT0_RIS_MTXDONE_R { INT_EVENT0_RIS_MTXDONE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event0_ris_mrxfifotrg (& self) -> INT_EVENT0_RIS_MRXFIFOTRG_R { INT_EVENT0_RIS_MRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event0_ris_mtxfifotrg (& self) -> INT_EVENT0_RIS_MTXFIFOTRG_R { INT_EVENT0_RIS_MTXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_ris_mrxfifofull (& self) -> INT_EVENT0_RIS_MRXFIFOFULL_R { INT_EVENT0_RIS_MRXFIFOFULL_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_ris_mtxempty (& self) -> INT_EVENT0_RIS_MTXEMPTY_R { INT_EVENT0_RIS_MTXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mnack (& self) -> INT_EVENT0_RIS_MNACK_R { INT_EVENT0_RIS_MNACK_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mstart (& self) -> INT_EVENT0_RIS_MSTART_R { INT_EVENT0_RIS_MSTART_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mstop (& self) -> INT_EVENT0_RIS_MSTOP_R { INT_EVENT0_RIS_MSTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
pub fn int_event0_ris_marblost (& self) -> INT_EVENT0_RIS_MARBLOST_R { INT_EVENT0_RIS_MARBLOST_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_ris_mdma_done1_2 (& self) -> INT_EVENT0_RIS_MDMA_DONE1_2_R { INT_EVENT0_RIS_MDMA_DONE1_2_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_ris_mdma_done1_3 (& self) -> INT_EVENT0_RIS_MDMA_DONE1_3_R { INT_EVENT0_RIS_MDMA_DONE1_3_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_ris_mpec_rx_err (& self) -> INT_EVENT0_RIS_MPEC_RX_ERR_R { INT_EVENT0_RIS_MPEC_RX_ERR_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
pub fn int_event0_ris_timeouta (& self) -> INT_EVENT0_RIS_TIMEOUTA_R { INT_EVENT0_RIS_TIMEOUTA_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
pub fn int_event0_ris_timeoutb (& self) -> INT_EVENT0_RIS_TIMEOUTB_R { INT_EVENT0_RIS_TIMEOUTB_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
pub fn int_event0_ris_srxdone (& self) -> INT_EVENT0_RIS_SRXDONE_R { INT_EVENT0_RIS_SRXDONE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_ris_stxdone (& self) -> INT_EVENT0_RIS_STXDONE_R { INT_EVENT0_RIS_STXDONE_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event0_ris_srxfifotrg (& self) -> INT_EVENT0_RIS_SRXFIFOTRG_R { INT_EVENT0_RIS_SRXFIFOTRG_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event0_ris_stxfifotrg (& self) -> INT_EVENT0_RIS_STXFIFOTRG_R { INT_EVENT0_RIS_STXFIFOTRG_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_ris_srxfifofull (& self) -> INT_EVENT0_RIS_SRXFIFOFULL_R { INT_EVENT0_RIS_SRXFIFOFULL_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_ris_stxempty (& self) -> INT_EVENT0_RIS_STXEMPTY_R { INT_EVENT0_RIS_STXEMPTY_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
pub fn int_event0_ris_sstart (& self) -> INT_EVENT0_RIS_SSTART_R { INT_EVENT0_RIS_SSTART_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
pub fn int_event0_ris_sstop (& self) -> INT_EVENT0_RIS_SSTOP_R { INT_EVENT0_RIS_SSTOP_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
pub fn int_event0_ris_sgencall (& self) -> INT_EVENT0_RIS_SGENCALL_R { INT_EVENT0_RIS_SGENCALL_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_ris_sdma_done1_2 (& self) -> INT_EVENT0_RIS_SDMA_DONE1_2_R { INT_EVENT0_RIS_SDMA_DONE1_2_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_ris_sdma_done1_3 (& self) -> INT_EVENT0_RIS_SDMA_DONE1_3_R { INT_EVENT0_RIS_SDMA_DONE1_3_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_ris_spec_rx_err (& self) -> INT_EVENT0_RIS_SPEC_RX_ERR_R { INT_EVENT0_RIS_SPEC_RX_ERR_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
pub fn int_event0_ris_stx_unfl (& self) -> INT_EVENT0_RIS_STX_UNFL_R { INT_EVENT0_RIS_STX_UNFL_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
pub fn int_event0_ris_srx_ovfl (& self) -> INT_EVENT0_RIS_SRX_OVFL_R { INT_EVENT0_RIS_SRX_OVFL_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
pub fn int_event0_ris_sarblost (& self) -> INT_EVENT0_RIS_SARBLOST_R { INT_EVENT0_RIS_SARBLOST_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Interrupt overflow interrupt It is set when SSTART or SSTOP interrupts overflow i.e. occur twice without being serviced"]
# [inline (always)]
pub fn int_event0_ris_intr_ovfl (& self) -> INT_EVENT0_RIS_INTR_OVFL_R { INT_EVENT0_RIS_INTR_OVFL_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_RIS to value 0"]
impl crate :: Resettable for INT_EVENT0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_mis`]
module"]
pub type INT_EVENT0_MIS = crate :: Reg < int_event0_mis :: INT_EVENT0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event0_mis { # [doc = "Register `INT_EVENT0_MIS` reader"]
pub type R = crate :: R < INT_EVENT0_MIS_SPEC > ; # [doc = "Field `INT_EVENT0_MIS_MRXDONE` reader - Master Receive Data Interrupt"]
pub type INT_EVENT0_MIS_MRXDONE_R = crate :: BitReader < INT_EVENT0_MIS_MRXDONE_A > ; # [doc = "Master Receive Data Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MRXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_MRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MRXDONE_A { match self . bits { false => INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_CLR , true => INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mrxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mrxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_MRXDONE_A :: INT_EVENT0_MIS_MRXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_MTXDONE` reader - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_MIS_MTXDONE_R = crate :: BitReader < INT_EVENT0_MIS_MTXDONE_A > ; # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MTXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MTXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MTXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_MTXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MTXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MTXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MTXDONE_A { match self . bits { false => INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_CLR , true => INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mtxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mtxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_MTXDONE_A :: INT_EVENT0_MIS_MTXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_MIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_CLR , true => INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOTRG_A :: INT_EVENT0_MIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_MIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_CLR , true => INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_MTXFIFOTRG_A :: INT_EVENT0_MIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_MRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if the RX FIFO is full."]
pub type INT_EVENT0_MIS_MRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_MIS_MRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if the RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_MIS_MRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MRXFIFOFULL_A { match self . bits { false => INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_CLR , true => INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifofull_clr (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mrxfifofull_set (& self) -> bool { * self == INT_EVENT0_MIS_MRXFIFOFULL_A :: INT_EVENT0_MIS_MRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_MIS_MTXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_MIS_MTXEMPTY_R = crate :: BitReader < INT_EVENT0_MIS_MTXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MTXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MTXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_MIS_MTXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MTXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MTXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MTXEMPTY_A { match self . bits { false => INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_CLR , true => INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mtxempty_clr (& self) -> bool { * self == INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mtxempty_set (& self) -> bool { * self == INT_EVENT0_MIS_MTXEMPTY_A :: INT_EVENT0_MIS_MTXEMPTY_SET } } # [doc = "Field `INT_EVENT0_MIS_MNACK` reader - Address/Data NACK Interrupt"]
pub type INT_EVENT0_MIS_MNACK_R = crate :: BitReader < INT_EVENT0_MIS_MNACK_A > ; # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MNACK_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MNACK_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MNACK_SET = 1 , } impl From < INT_EVENT0_MIS_MNACK_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MNACK_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MNACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MNACK_A { match self . bits { false => INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_CLR , true => INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mnack_clr (& self) -> bool { * self == INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mnack_set (& self) -> bool { * self == INT_EVENT0_MIS_MNACK_A :: INT_EVENT0_MIS_MNACK_SET } } # [doc = "Field `INT_EVENT0_MIS_MSTART` reader - START Detection Interrupt"]
pub type INT_EVENT0_MIS_MSTART_R = crate :: BitReader < INT_EVENT0_MIS_MSTART_A > ; # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MSTART_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MSTART_SET = 1 , } impl From < INT_EVENT0_MIS_MSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MSTART_A { match self . bits { false => INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_CLR , true => INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mstart_clr (& self) -> bool { * self == INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mstart_set (& self) -> bool { * self == INT_EVENT0_MIS_MSTART_A :: INT_EVENT0_MIS_MSTART_SET } } # [doc = "Field `INT_EVENT0_MIS_MSTOP` reader - STOP Detection Interrupt"]
pub type INT_EVENT0_MIS_MSTOP_R = crate :: BitReader < INT_EVENT0_MIS_MSTOP_A > ; # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MSTOP_SET = 1 , } impl From < INT_EVENT0_MIS_MSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MSTOP_A { match self . bits { false => INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_CLR , true => INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mstop_clr (& self) -> bool { * self == INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mstop_set (& self) -> bool { * self == INT_EVENT0_MIS_MSTOP_A :: INT_EVENT0_MIS_MSTOP_SET } } # [doc = "Field `INT_EVENT0_MIS_MARBLOST` reader - Arbitration Lost Interrupt"]
pub type INT_EVENT0_MIS_MARBLOST_R = crate :: BitReader < INT_EVENT0_MIS_MARBLOST_A > ; # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MARBLOST_SET = 1 , } impl From < INT_EVENT0_MIS_MARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MARBLOST_A { match self . bits { false => INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_CLR , true => INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_marblost_clr (& self) -> bool { * self == INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_marblost_set (& self) -> bool { * self == INT_EVENT0_MIS_MARBLOST_A :: INT_EVENT0_MIS_MARBLOST_SET } } # [doc = "Field `INT_EVENT0_MIS_MDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_MIS_MDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_MIS_MDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_MIS_MDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_CLR , true => INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_2_A :: INT_EVENT0_MIS_MDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_MIS_MDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_MIS_MDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_MIS_MDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_MIS_MDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_CLR , true => INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_MIS_MDMA_DONE1_3_A :: INT_EVENT0_MIS_MDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_MIS_MPEC_RX_ERR` reader - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_MIS_MPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_MIS_MPEC_RX_ERR_A > ; # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_MIS_MPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_CLR , true => INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_mpec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_mpec_rx_err_set (& self) -> bool { * self == INT_EVENT0_MIS_MPEC_RX_ERR_A :: INT_EVENT0_MIS_MPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_MIS_TIMEOUTA` reader - Timeout A Interrupt"]
pub type INT_EVENT0_MIS_TIMEOUTA_R = crate :: BitReader < INT_EVENT0_MIS_TIMEOUTA_A > ; # [doc = "Timeout A Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TIMEOUTA_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TIMEOUTA_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_MIS_TIMEOUTA_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TIMEOUTA_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TIMEOUTA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TIMEOUTA_A { match self . bits { false => INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_CLR , true => INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_timeouta_clr (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_timeouta_set (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTA_A :: INT_EVENT0_MIS_TIMEOUTA_SET } } # [doc = "Field `INT_EVENT0_MIS_TIMEOUTB` reader - Timeout B Interrupt"]
pub type INT_EVENT0_MIS_TIMEOUTB_R = crate :: BitReader < INT_EVENT0_MIS_TIMEOUTB_A > ; # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TIMEOUTB_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TIMEOUTB_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_MIS_TIMEOUTB_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TIMEOUTB_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TIMEOUTB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TIMEOUTB_A { match self . bits { false => INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_CLR , true => INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_timeoutb_clr (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_timeoutb_set (& self) -> bool { * self == INT_EVENT0_MIS_TIMEOUTB_A :: INT_EVENT0_MIS_TIMEOUTB_SET } } # [doc = "Field `INT_EVENT0_MIS_SRXDONE` reader - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_MIS_SRXDONE_R = crate :: BitReader < INT_EVENT0_MIS_SRXDONE_A > ; # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_SRXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRXDONE_A { match self . bits { false => INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_CLR , true => INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_SRXDONE_A :: INT_EVENT0_MIS_SRXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_STXDONE` reader - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_MIS_STXDONE_R = crate :: BitReader < INT_EVENT0_MIS_STXDONE_A > ; # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STXDONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STXDONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STXDONE_SET = 1 , } impl From < INT_EVENT0_MIS_STXDONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STXDONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STXDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STXDONE_A { match self . bits { false => INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_CLR , true => INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stxdone_clr (& self) -> bool { * self == INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stxdone_set (& self) -> bool { * self == INT_EVENT0_MIS_STXDONE_A :: INT_EVENT0_MIS_STXDONE_SET } } # [doc = "Field `INT_EVENT0_MIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_MIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_CLR , true => INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOTRG_A :: INT_EVENT0_MIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_MIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT0_MIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_MIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_CLR , true => INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stxfifotrg_set (& self) -> bool { * self == INT_EVENT0_MIS_STXFIFOTRG_A :: INT_EVENT0_MIS_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT0_MIS_SRXFIFOFULL` reader - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_MIS_SRXFIFOFULL_R = crate :: BitReader < INT_EVENT0_MIS_SRXFIFOFULL_A > ; # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRXFIFOFULL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRXFIFOFULL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_MIS_SRXFIFOFULL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRXFIFOFULL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRXFIFOFULL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRXFIFOFULL_A { match self . bits { false => INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_CLR , true => INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifofull_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srxfifofull_set (& self) -> bool { * self == INT_EVENT0_MIS_SRXFIFOFULL_A :: INT_EVENT0_MIS_SRXFIFOFULL_SET } } # [doc = "Field `INT_EVENT0_MIS_STXEMPTY` reader - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_MIS_STXEMPTY_R = crate :: BitReader < INT_EVENT0_MIS_STXEMPTY_A > ; # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STXEMPTY_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STXEMPTY_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_MIS_STXEMPTY_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STXEMPTY_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STXEMPTY_A { match self . bits { false => INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_CLR , true => INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stxempty_clr (& self) -> bool { * self == INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stxempty_set (& self) -> bool { * self == INT_EVENT0_MIS_STXEMPTY_A :: INT_EVENT0_MIS_STXEMPTY_SET } } # [doc = "Field `INT_EVENT0_MIS_SSTART` reader - Slave START Detection Interrupt"]
pub type INT_EVENT0_MIS_SSTART_R = crate :: BitReader < INT_EVENT0_MIS_SSTART_A > ; # [doc = "Slave START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SSTART_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SSTART_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SSTART_SET = 1 , } impl From < INT_EVENT0_MIS_SSTART_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SSTART_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SSTART_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SSTART_A { match self . bits { false => INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_CLR , true => INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sstart_clr (& self) -> bool { * self == INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sstart_set (& self) -> bool { * self == INT_EVENT0_MIS_SSTART_A :: INT_EVENT0_MIS_SSTART_SET } } # [doc = "Field `INT_EVENT0_MIS_SSTOP` reader - Slave STOP Detection Interrupt"]
pub type INT_EVENT0_MIS_SSTOP_R = crate :: BitReader < INT_EVENT0_MIS_SSTOP_A > ; # [doc = "Slave STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SSTOP_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SSTOP_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SSTOP_SET = 1 , } impl From < INT_EVENT0_MIS_SSTOP_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SSTOP_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SSTOP_A { match self . bits { false => INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_CLR , true => INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sstop_clr (& self) -> bool { * self == INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sstop_set (& self) -> bool { * self == INT_EVENT0_MIS_SSTOP_A :: INT_EVENT0_MIS_SSTOP_SET } } # [doc = "Field `INT_EVENT0_MIS_SGENCALL` reader - General Call Interrupt"]
pub type INT_EVENT0_MIS_SGENCALL_R = crate :: BitReader < INT_EVENT0_MIS_SGENCALL_A > ; # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SGENCALL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SGENCALL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SGENCALL_SET = 1 , } impl From < INT_EVENT0_MIS_SGENCALL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SGENCALL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SGENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SGENCALL_A { match self . bits { false => INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_CLR , true => INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sgencall_clr (& self) -> bool { * self == INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sgencall_set (& self) -> bool { * self == INT_EVENT0_MIS_SGENCALL_A :: INT_EVENT0_MIS_SGENCALL_SET } } # [doc = "Field `INT_EVENT0_MIS_SDMA_DONE1_2` reader - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_MIS_SDMA_DONE1_2_R = crate :: BitReader < INT_EVENT0_MIS_SDMA_DONE1_2_A > ; # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SDMA_DONE1_2_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SDMA_DONE1_2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_MIS_SDMA_DONE1_2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SDMA_DONE1_2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SDMA_DONE1_2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SDMA_DONE1_2_A { match self . bits { false => INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_CLR , true => INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_2_clr (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_2_set (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_2_A :: INT_EVENT0_MIS_SDMA_DONE1_2_SET } } # [doc = "Field `INT_EVENT0_MIS_SDMA_DONE1_3` reader - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_MIS_SDMA_DONE1_3_R = crate :: BitReader < INT_EVENT0_MIS_SDMA_DONE1_3_A > ; # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SDMA_DONE1_3_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SDMA_DONE1_3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_MIS_SDMA_DONE1_3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SDMA_DONE1_3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SDMA_DONE1_3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SDMA_DONE1_3_A { match self . bits { false => INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_CLR , true => INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_3_clr (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sdma_done1_3_set (& self) -> bool { * self == INT_EVENT0_MIS_SDMA_DONE1_3_A :: INT_EVENT0_MIS_SDMA_DONE1_3_SET } } # [doc = "Field `INT_EVENT0_MIS_SPEC_RX_ERR` reader - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_MIS_SPEC_RX_ERR_R = crate :: BitReader < INT_EVENT0_MIS_SPEC_RX_ERR_A > ; # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SPEC_RX_ERR_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SPEC_RX_ERR_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_MIS_SPEC_RX_ERR_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SPEC_RX_ERR_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SPEC_RX_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SPEC_RX_ERR_A { match self . bits { false => INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_CLR , true => INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_spec_rx_err_clr (& self) -> bool { * self == INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_spec_rx_err_set (& self) -> bool { * self == INT_EVENT0_MIS_SPEC_RX_ERR_A :: INT_EVENT0_MIS_SPEC_RX_ERR_SET } } # [doc = "Field `INT_EVENT0_MIS_STX_UNFL` reader - Slave TX FIFO underflow"]
pub type INT_EVENT0_MIS_STX_UNFL_R = crate :: BitReader < INT_EVENT0_MIS_STX_UNFL_A > ; # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_STX_UNFL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_STX_UNFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_MIS_STX_UNFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_STX_UNFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_STX_UNFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_STX_UNFL_A { match self . bits { false => INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_CLR , true => INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_stx_unfl_clr (& self) -> bool { * self == INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_stx_unfl_set (& self) -> bool { * self == INT_EVENT0_MIS_STX_UNFL_A :: INT_EVENT0_MIS_STX_UNFL_SET } } # [doc = "Field `INT_EVENT0_MIS_SRX_OVFL` reader - Slave RX FIFO overflow"]
pub type INT_EVENT0_MIS_SRX_OVFL_R = crate :: BitReader < INT_EVENT0_MIS_SRX_OVFL_A > ; # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SRX_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SRX_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_MIS_SRX_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SRX_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SRX_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SRX_OVFL_A { match self . bits { false => INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_CLR , true => INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_srx_ovfl_clr (& self) -> bool { * self == INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_srx_ovfl_set (& self) -> bool { * self == INT_EVENT0_MIS_SRX_OVFL_A :: INT_EVENT0_MIS_SRX_OVFL_SET } } # [doc = "Field `INT_EVENT0_MIS_SARBLOST` reader - Slave Arbitration Lost"]
pub type INT_EVENT0_MIS_SARBLOST_R = crate :: BitReader < INT_EVENT0_MIS_SARBLOST_A > ; # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_SARBLOST_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_SARBLOST_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_SARBLOST_SET = 1 , } impl From < INT_EVENT0_MIS_SARBLOST_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_SARBLOST_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_SARBLOST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_SARBLOST_A { match self . bits { false => INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_CLR , true => INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_sarblost_clr (& self) -> bool { * self == INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_sarblost_set (& self) -> bool { * self == INT_EVENT0_MIS_SARBLOST_A :: INT_EVENT0_MIS_SARBLOST_SET } } # [doc = "Field `INT_EVENT0_MIS_INTR_OVFL` reader - Interrupt overflow"]
pub type INT_EVENT0_MIS_INTR_OVFL_R = crate :: BitReader < INT_EVENT0_MIS_INTR_OVFL_A > ; # [doc = "Interrupt overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_INTR_OVFL_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_INTR_OVFL_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_MIS_INTR_OVFL_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_INTR_OVFL_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_INTR_OVFL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_INTR_OVFL_A { match self . bits { false => INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_CLR , true => INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_intr_ovfl_clr (& self) -> bool { * self == INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_intr_ovfl_set (& self) -> bool { * self == INT_EVENT0_MIS_INTR_OVFL_A :: INT_EVENT0_MIS_INTR_OVFL_SET } } impl R { # [doc = "Bit 0 - Master Receive Data Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mrxdone (& self) -> INT_EVENT0_MIS_MRXDONE_R { INT_EVENT0_MIS_MRXDONE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mtxdone (& self) -> INT_EVENT0_MIS_MTXDONE_R { INT_EVENT0_MIS_MTXDONE_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event0_mis_mrxfifotrg (& self) -> INT_EVENT0_MIS_MRXFIFOTRG_R { INT_EVENT0_MIS_MRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event0_mis_mtxfifotrg (& self) -> INT_EVENT0_MIS_MTXFIFOTRG_R { INT_EVENT0_MIS_MTXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - RXFIFO full event. This interrupt is set if the RX FIFO is full."]
# [inline (always)]
pub fn int_event0_mis_mrxfifofull (& self) -> INT_EVENT0_MIS_MRXFIFOFULL_R { INT_EVENT0_MIS_MRXFIFOFULL_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_mis_mtxempty (& self) -> INT_EVENT0_MIS_MTXEMPTY_R { INT_EVENT0_MIS_MTXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mnack (& self) -> INT_EVENT0_MIS_MNACK_R { INT_EVENT0_MIS_MNACK_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mstart (& self) -> INT_EVENT0_MIS_MSTART_R { INT_EVENT0_MIS_MSTART_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mstop (& self) -> INT_EVENT0_MIS_MSTOP_R { INT_EVENT0_MIS_MSTOP_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
pub fn int_event0_mis_marblost (& self) -> INT_EVENT0_MIS_MARBLOST_R { INT_EVENT0_MIS_MARBLOST_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_mis_mdma_done1_2 (& self) -> INT_EVENT0_MIS_MDMA_DONE1_2_R { INT_EVENT0_MIS_MDMA_DONE1_2_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_mis_mdma_done1_3 (& self) -> INT_EVENT0_MIS_MDMA_DONE1_3_R { INT_EVENT0_MIS_MDMA_DONE1_3_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_mis_mpec_rx_err (& self) -> INT_EVENT0_MIS_MPEC_RX_ERR_R { INT_EVENT0_MIS_MPEC_RX_ERR_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Timeout A Interrupt"]
# [inline (always)]
pub fn int_event0_mis_timeouta (& self) -> INT_EVENT0_MIS_TIMEOUTA_R { INT_EVENT0_MIS_TIMEOUTA_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
pub fn int_event0_mis_timeoutb (& self) -> INT_EVENT0_MIS_TIMEOUTB_R { INT_EVENT0_MIS_TIMEOUTB_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
pub fn int_event0_mis_srxdone (& self) -> INT_EVENT0_MIS_SRXDONE_R { INT_EVENT0_MIS_SRXDONE_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
pub fn int_event0_mis_stxdone (& self) -> INT_EVENT0_MIS_STXDONE_R { INT_EVENT0_MIS_STXDONE_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event0_mis_srxfifotrg (& self) -> INT_EVENT0_MIS_SRXFIFOTRG_R { INT_EVENT0_MIS_SRXFIFOTRG_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event0_mis_stxfifotrg (& self) -> INT_EVENT0_MIS_STXFIFOTRG_R { INT_EVENT0_MIS_STXFIFOTRG_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
pub fn int_event0_mis_srxfifofull (& self) -> INT_EVENT0_MIS_SRXFIFOFULL_R { INT_EVENT0_MIS_SRXFIFOFULL_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
pub fn int_event0_mis_stxempty (& self) -> INT_EVENT0_MIS_STXEMPTY_R { INT_EVENT0_MIS_STXEMPTY_R :: new (((self . bits >> 21) & 1) != 0) } # [doc = "Bit 22 - Slave START Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_sstart (& self) -> INT_EVENT0_MIS_SSTART_R { INT_EVENT0_MIS_SSTART_R :: new (((self . bits >> 22) & 1) != 0) } # [doc = "Bit 23 - Slave STOP Detection Interrupt"]
# [inline (always)]
pub fn int_event0_mis_sstop (& self) -> INT_EVENT0_MIS_SSTOP_R { INT_EVENT0_MIS_SSTOP_R :: new (((self . bits >> 23) & 1) != 0) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
pub fn int_event0_mis_sgencall (& self) -> INT_EVENT0_MIS_SGENCALL_R { INT_EVENT0_MIS_SGENCALL_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
pub fn int_event0_mis_sdma_done1_2 (& self) -> INT_EVENT0_MIS_SDMA_DONE1_2_R { INT_EVENT0_MIS_SDMA_DONE1_2_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
pub fn int_event0_mis_sdma_done1_3 (& self) -> INT_EVENT0_MIS_SDMA_DONE1_3_R { INT_EVENT0_MIS_SDMA_DONE1_3_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
pub fn int_event0_mis_spec_rx_err (& self) -> INT_EVENT0_MIS_SPEC_RX_ERR_R { INT_EVENT0_MIS_SPEC_RX_ERR_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
pub fn int_event0_mis_stx_unfl (& self) -> INT_EVENT0_MIS_STX_UNFL_R { INT_EVENT0_MIS_STX_UNFL_R :: new (((self . bits >> 28) & 1) != 0) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
pub fn int_event0_mis_srx_ovfl (& self) -> INT_EVENT0_MIS_SRX_OVFL_R { INT_EVENT0_MIS_SRX_OVFL_R :: new (((self . bits >> 29) & 1) != 0) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
pub fn int_event0_mis_sarblost (& self) -> INT_EVENT0_MIS_SARBLOST_R { INT_EVENT0_MIS_SARBLOST_R :: new (((self . bits >> 30) & 1) != 0) } # [doc = "Bit 31 - Interrupt overflow"]
# [inline (always)]
pub fn int_event0_mis_intr_ovfl (& self) -> INT_EVENT0_MIS_INTR_OVFL_R { INT_EVENT0_MIS_INTR_OVFL_R :: new (((self . bits >> 31) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_MIS to value 0"]
impl crate :: Resettable for INT_EVENT0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iset`]
module"]
pub type INT_EVENT0_ISET = crate :: Reg < int_event0_iset :: INT_EVENT0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event0_iset { # [doc = "Register `INT_EVENT0_ISET` writer"]
pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ISET_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mrxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXDONE_AW :: INT_EVENT0_ISET_MRXDONE_SET) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MTXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MTXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MTXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_MTXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXDONE` writer - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ISET_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mtxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXDONE_AW :: INT_EVENT0_ISET_MTXDONE_SET) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOTRG_AW :: INT_EVENT0_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXFIFOTRG_AW :: INT_EVENT0_ISET_MTXFIFOTRG_SET) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_MRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MRXFIFOFULL` writer - RXFIFO full event."]
pub type INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mrxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MRXFIFOFULL_AW :: INT_EVENT0_ISET_MRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MTXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_MTXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mtxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MTXEMPTY_AW :: INT_EVENT0_ISET_MTXEMPTY_SET) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MNACK_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MNACK_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MNACK_SET = 1 , } impl From < INT_EVENT0_ISET_MNACK_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MNACK` writer - Address/Data NACK Interrupt"]
pub type INT_EVENT0_ISET_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mnack_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MNACK_AW :: INT_EVENT0_ISET_MNACK_SET) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MSTART_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MSTART_SET = 1 , } impl From < INT_EVENT0_ISET_MSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTART` writer - START Detection Interrupt"]
pub type INT_EVENT0_ISET_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTART_AW :: INT_EVENT0_ISET_MSTART_SET) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MSTOP_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_MSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MSTOP` writer - STOP Detection Interrupt"]
pub type INT_EVENT0_ISET_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MSTOP_AW :: INT_EVENT0_ISET_MSTOP_SET) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_MARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MARBLOST` writer - Arbitration Lost Interrupt"]
pub type INT_EVENT0_ISET_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_marblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MARBLOST_AW :: INT_EVENT0_ISET_MARBLOST_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_2_AW :: INT_EVENT0_ISET_MDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_MDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MDMA_DONE1_3_AW :: INT_EVENT0_ISET_MDMA_DONE1_3_SET) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_MPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_mpec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MPEC_RX_ERR_AW :: INT_EVENT0_ISET_MPEC_RX_ERR_SET) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TIMEOUTA_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTA_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTA` writer - Timeout A interrupt"]
pub type INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_timeouta_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTA_AW :: INT_EVENT0_ISET_TIMEOUTA_SET) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TIMEOUTB_SET = 1 , } impl From < INT_EVENT0_ISET_TIMEOUTB_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TIMEOUTB` writer - Timeout B Interrupt"]
pub type INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_timeoutb_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TIMEOUTB_AW :: INT_EVENT0_ISET_TIMEOUTB_SET) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_SRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ISET_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXDONE_AW :: INT_EVENT0_ISET_SRXDONE_SET) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STXDONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STXDONE_SET = 1 , } impl From < INT_EVENT0_ISET_STXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXDONE` writer - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ISET_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stxdone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXDONE_AW :: INT_EVENT0_ISET_STXDONE_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOTRG_AW :: INT_EVENT0_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT0_ISET_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXFIFOTRG_AW :: INT_EVENT0_ISET_STXFIFOTRG_SET) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRXFIFOFULL_SET = 1 , } impl From < INT_EVENT0_ISET_SRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srxfifofull_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRXFIFOFULL_AW :: INT_EVENT0_ISET_SRXFIFOFULL_SET) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STXEMPTY_SET = 1 , } impl From < INT_EVENT0_ISET_STXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stxempty_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STXEMPTY_AW :: INT_EVENT0_ISET_STXEMPTY_SET) } } # [doc = "Start Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SSTART_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SSTART_SET = 1 , } impl From < INT_EVENT0_ISET_SSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTART` writer - Start Condition Interrupt"]
pub type INT_EVENT0_ISET_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sstart_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTART_AW :: INT_EVENT0_ISET_SSTART_SET) } } # [doc = "Stop Condition Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SSTOP_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SSTOP_SET = 1 , } impl From < INT_EVENT0_ISET_SSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SSTOP` writer - Stop Condition Interrupt"]
pub type INT_EVENT0_ISET_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sstop_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SSTOP_AW :: INT_EVENT0_ISET_SSTOP_SET) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SGENCALL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SGENCALL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SGENCALL_SET = 1 , } impl From < INT_EVENT0_ISET_SGENCALL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SGENCALL` writer - General Call Interrupt"]
pub type INT_EVENT0_ISET_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sgencall_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SGENCALL_AW :: INT_EVENT0_ISET_SGENCALL_SET) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SDMA_DONE1_2_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_2_AW :: INT_EVENT0_ISET_SDMA_DONE1_2_SET) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SDMA_DONE1_3_SET = 1 , } impl From < INT_EVENT0_ISET_SDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sdma_done1_3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SDMA_DONE1_3_AW :: INT_EVENT0_ISET_SDMA_DONE1_3_SET) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SPEC_RX_ERR_SET = 1 , } impl From < INT_EVENT0_ISET_SPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_spec_rx_err_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SPEC_RX_ERR_AW :: INT_EVENT0_ISET_SPEC_RX_ERR_SET) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_STX_UNFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_STX_UNFL_SET = 1 , } impl From < INT_EVENT0_ISET_STX_UNFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_STX_UNFL` writer - Slave TX FIFO underflow"]
pub type INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_stx_unfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_STX_UNFL_AW :: INT_EVENT0_ISET_STX_UNFL_SET) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SRX_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_SRX_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SRX_OVFL` writer - Slave RX FIFO overflow"]
pub type INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_srx_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SRX_OVFL_AW :: INT_EVENT0_ISET_SRX_OVFL_SET) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_SARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_SARBLOST_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_SARBLOST_SET = 1 , } impl From < INT_EVENT0_ISET_SARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_SARBLOST` writer - Slave Arbitration Lost"]
pub type INT_EVENT0_ISET_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_sarblost_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_SARBLOST_AW :: INT_EVENT0_ISET_SARBLOST_SET) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_INTR_OVFL_SET = 1 , } impl From < INT_EVENT0_ISET_INTR_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INTR_OVFL` writer - Interrupt overflow"]
pub type INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_intr_ovfl_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INTR_OVFL_AW :: INT_EVENT0_ISET_INTR_OVFL_SET) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mrxdone (& mut self) -> INT_EVENT0_ISET_MRXDONE_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mtxdone (& mut self) -> INT_EVENT0_ISET_MTXDONE_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mrxfifotrg (& mut self) -> INT_EVENT0_ISET_MRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mtxfifotrg (& mut self) -> INT_EVENT0_ISET_MTXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mrxfifofull (& mut self) -> INT_EVENT0_ISET_MRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mtxempty (& mut self) -> INT_EVENT0_ISET_MTXEMPTY_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mnack (& mut self) -> INT_EVENT0_ISET_MNACK_W < INT_EVENT0_ISET_SPEC , 7 > { INT_EVENT0_ISET_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mstart (& mut self) -> INT_EVENT0_ISET_MSTART_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mstop (& mut self) -> INT_EVENT0_ISET_MSTOP_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_marblost (& mut self) -> INT_EVENT0_ISET_MARBLOST_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mdma_done1_2 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mdma_done1_3 (& mut self) -> INT_EVENT0_ISET_MDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 12 > { INT_EVENT0_ISET_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_mpec_rx_err (& mut self) -> INT_EVENT0_ISET_MPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 13 > { INT_EVENT0_ISET_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_timeouta (& mut self) -> INT_EVENT0_ISET_TIMEOUTA_W < INT_EVENT0_ISET_SPEC , 14 > { INT_EVENT0_ISET_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_timeoutb (& mut self) -> INT_EVENT0_ISET_TIMEOUTB_W < INT_EVENT0_ISET_SPEC , 15 > { INT_EVENT0_ISET_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srxdone (& mut self) -> INT_EVENT0_ISET_SRXDONE_W < INT_EVENT0_ISET_SPEC , 16 > { INT_EVENT0_ISET_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stxdone (& mut self) -> INT_EVENT0_ISET_STXDONE_W < INT_EVENT0_ISET_SPEC , 17 > { INT_EVENT0_ISET_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srxfifotrg (& mut self) -> INT_EVENT0_ISET_SRXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 18 > { INT_EVENT0_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stxfifotrg (& mut self) -> INT_EVENT0_ISET_STXFIFOTRG_W < INT_EVENT0_ISET_SPEC , 19 > { INT_EVENT0_ISET_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srxfifofull (& mut self) -> INT_EVENT0_ISET_SRXFIFOFULL_W < INT_EVENT0_ISET_SPEC , 20 > { INT_EVENT0_ISET_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stxempty (& mut self) -> INT_EVENT0_ISET_STXEMPTY_W < INT_EVENT0_ISET_SPEC , 21 > { INT_EVENT0_ISET_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Start Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sstart (& mut self) -> INT_EVENT0_ISET_SSTART_W < INT_EVENT0_ISET_SPEC , 22 > { INT_EVENT0_ISET_SSTART_W :: new (self) } # [doc = "Bit 23 - Stop Condition Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sstop (& mut self) -> INT_EVENT0_ISET_SSTOP_W < INT_EVENT0_ISET_SPEC , 23 > { INT_EVENT0_ISET_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sgencall (& mut self) -> INT_EVENT0_ISET_SGENCALL_W < INT_EVENT0_ISET_SPEC , 24 > { INT_EVENT0_ISET_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sdma_done1_2 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_2_W < INT_EVENT0_ISET_SPEC , 25 > { INT_EVENT0_ISET_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sdma_done1_3 (& mut self) -> INT_EVENT0_ISET_SDMA_DONE1_3_W < INT_EVENT0_ISET_SPEC , 26 > { INT_EVENT0_ISET_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_spec_rx_err (& mut self) -> INT_EVENT0_ISET_SPEC_RX_ERR_W < INT_EVENT0_ISET_SPEC , 27 > { INT_EVENT0_ISET_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_stx_unfl (& mut self) -> INT_EVENT0_ISET_STX_UNFL_W < INT_EVENT0_ISET_SPEC , 28 > { INT_EVENT0_ISET_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_srx_ovfl (& mut self) -> INT_EVENT0_ISET_SRX_OVFL_W < INT_EVENT0_ISET_SPEC , 29 > { INT_EVENT0_ISET_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_sarblost (& mut self) -> INT_EVENT0_ISET_SARBLOST_W < INT_EVENT0_ISET_SPEC , 30 > { INT_EVENT0_ISET_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_intr_ovfl (& mut self) -> INT_EVENT0_ISET_INTR_OVFL_W < INT_EVENT0_ISET_SPEC , 31 > { INT_EVENT0_ISET_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"]
impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iclr`]
module"]
pub type INT_EVENT0_ICLR = crate :: Reg < int_event0_iclr :: INT_EVENT0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event0_iclr { # [doc = "Register `INT_EVENT0_ICLR` writer"]
pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Master Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MRXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MRXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_MRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MRXDONE` writer - Master Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ICLR_MRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mrxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXDONE_AW :: INT_EVENT0_ICLR_MRXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mrxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXDONE_AW :: INT_EVENT0_ICLR_MRXDONE_CLR) } } # [doc = "Master Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MTXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MTXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MTXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_MTXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MTXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MTXDONE` writer - Master Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ICLR_MTXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MTXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MTXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mtxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXDONE_AW :: INT_EVENT0_ICLR_MTXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mtxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXDONE_AW :: INT_EVENT0_ICLR_MTXDONE_CLR) } } # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT0_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOTRG_AW :: INT_EVENT0_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOTRG_AW :: INT_EVENT0_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT0_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXFIFOTRG_AW :: INT_EVENT0_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXFIFOTRG_AW :: INT_EVENT0_ICLR_MTXFIFOTRG_CLR) } } # [doc = "RXFIFO full event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MRXFIFOFULL_CLR = 1 , } impl From < INT_EVENT0_ICLR_MRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MRXFIFOFULL` writer - RXFIFO full event."]
pub type INT_EVENT0_ICLR_MRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOFULL_AW :: INT_EVENT0_ICLR_MRXFIFOFULL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mrxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MRXFIFOFULL_AW :: INT_EVENT0_ICLR_MRXFIFOFULL_CLR) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MTXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MTXEMPTY_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MTXEMPTY_CLR = 1 , } impl From < INT_EVENT0_ICLR_MTXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MTXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MTXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ICLR_MTXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MTXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MTXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mtxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXEMPTY_AW :: INT_EVENT0_ICLR_MTXEMPTY_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mtxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MTXEMPTY_AW :: INT_EVENT0_ICLR_MTXEMPTY_CLR) } } # [doc = "Address/Data NACK Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MNACK_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MNACK_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MNACK_CLR = 1 , } impl From < INT_EVENT0_ICLR_MNACK_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MNACK_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MNACK` writer - Address/Data NACK Interrupt"]
pub type INT_EVENT0_ICLR_MNACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MNACK_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MNACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mnack_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MNACK_AW :: INT_EVENT0_ICLR_MNACK_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mnack_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MNACK_AW :: INT_EVENT0_ICLR_MNACK_CLR) } } # [doc = "START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MSTART_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MSTART_CLR = 1 , } impl From < INT_EVENT0_ICLR_MSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MSTART` writer - START Detection Interrupt"]
pub type INT_EVENT0_ICLR_MSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTART_AW :: INT_EVENT0_ICLR_MSTART_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTART_AW :: INT_EVENT0_ICLR_MSTART_CLR) } } # [doc = "STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MSTOP_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MSTOP_CLR = 1 , } impl From < INT_EVENT0_ICLR_MSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MSTOP` writer - STOP Detection Interrupt"]
pub type INT_EVENT0_ICLR_MSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTOP_AW :: INT_EVENT0_ICLR_MSTOP_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MSTOP_AW :: INT_EVENT0_ICLR_MSTOP_CLR) } } # [doc = "Arbitration Lost Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MARBLOST_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MARBLOST_CLR = 1 , } impl From < INT_EVENT0_ICLR_MARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MARBLOST` writer - Arbitration Lost Interrupt"]
pub type INT_EVENT0_ICLR_MARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_marblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MARBLOST_AW :: INT_EVENT0_ICLR_MARBLOST_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_marblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MARBLOST_AW :: INT_EVENT0_ICLR_MARBLOST_CLR) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MDMA_DONE1_2_CLR = 1 , } impl From < INT_EVENT0_ICLR_MDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ICLR_MDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_2_AW :: INT_EVENT0_ICLR_MDMA_DONE1_2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_2_AW :: INT_EVENT0_ICLR_MDMA_DONE1_2_CLR) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MDMA_DONE1_3_CLR = 1 , } impl From < INT_EVENT0_ICLR_MDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ICLR_MDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_3_AW :: INT_EVENT0_ICLR_MDMA_DONE1_3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MDMA_DONE1_3_AW :: INT_EVENT0_ICLR_MDMA_DONE1_3_CLR) } } # [doc = "Master RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MPEC_RX_ERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_MPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MPEC_RX_ERR` writer - Master RX Pec Error Interrupt"]
pub type INT_EVENT0_ICLR_MPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_mpec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MPEC_RX_ERR_AW :: INT_EVENT0_ICLR_MPEC_RX_ERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_mpec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MPEC_RX_ERR_AW :: INT_EVENT0_ICLR_MPEC_RX_ERR_CLR) } } # [doc = "Timeout A interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TIMEOUTA_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TIMEOUTA_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TIMEOUTA_CLR = 1 , } impl From < INT_EVENT0_ICLR_TIMEOUTA_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TIMEOUTA_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TIMEOUTA` writer - Timeout A interrupt"]
pub type INT_EVENT0_ICLR_TIMEOUTA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TIMEOUTA_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TIMEOUTA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_timeouta_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTA_AW :: INT_EVENT0_ICLR_TIMEOUTA_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_timeouta_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTA_AW :: INT_EVENT0_ICLR_TIMEOUTA_CLR) } } # [doc = "Timeout B Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TIMEOUTB_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TIMEOUTB_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TIMEOUTB_CLR = 1 , } impl From < INT_EVENT0_ICLR_TIMEOUTB_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TIMEOUTB_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TIMEOUTB` writer - Timeout B Interrupt"]
pub type INT_EVENT0_ICLR_TIMEOUTB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TIMEOUTB_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TIMEOUTB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_timeoutb_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTB_AW :: INT_EVENT0_ICLR_TIMEOUTB_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_timeoutb_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TIMEOUTB_AW :: INT_EVENT0_ICLR_TIMEOUTB_CLR) } } # [doc = "Slave Receive Data Interrupt Signals that a byte has been received\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRXDONE` writer - Slave Receive Data Interrupt Signals that a byte has been received"]
pub type INT_EVENT0_ICLR_SRXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXDONE_AW :: INT_EVENT0_ICLR_SRXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXDONE_AW :: INT_EVENT0_ICLR_SRXDONE_CLR) } } # [doc = "Slave Transmit Transaction completed Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STXDONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STXDONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STXDONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_STXDONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STXDONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STXDONE` writer - Slave Transmit Transaction completed Interrupt"]
pub type INT_EVENT0_ICLR_STXDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STXDONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STXDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stxdone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXDONE_AW :: INT_EVENT0_ICLR_STXDONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stxdone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXDONE_AW :: INT_EVENT0_ICLR_STXDONE_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT0_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOTRG_AW :: INT_EVENT0_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOTRG_AW :: INT_EVENT0_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT0_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT0_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXFIFOTRG_AW :: INT_EVENT0_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXFIFOTRG_AW :: INT_EVENT0_ICLR_STXFIFOTRG_CLR) } } # [doc = "RXFIFO full event. This interrupt is set if an RX FIFO is full.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRXFIFOFULL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRXFIFOFULL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRXFIFOFULL_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRXFIFOFULL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRXFIFOFULL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRXFIFOFULL` writer - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
pub type INT_EVENT0_ICLR_SRXFIFOFULL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRXFIFOFULL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRXFIFOFULL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srxfifofull_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOFULL_AW :: INT_EVENT0_ICLR_SRXFIFOFULL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srxfifofull_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRXFIFOFULL_AW :: INT_EVENT0_ICLR_SRXFIFOFULL_CLR) } } # [doc = "Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STXEMPTY_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STXEMPTY_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STXEMPTY_CLR = 1 , } impl From < INT_EVENT0_ICLR_STXEMPTY_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STXEMPTY_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STXEMPTY` writer - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
pub type INT_EVENT0_ICLR_STXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STXEMPTY_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stxempty_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXEMPTY_AW :: INT_EVENT0_ICLR_STXEMPTY_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stxempty_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STXEMPTY_AW :: INT_EVENT0_ICLR_STXEMPTY_CLR) } } # [doc = "Slave START Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SSTART_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SSTART_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SSTART_CLR = 1 , } impl From < INT_EVENT0_ICLR_SSTART_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SSTART_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SSTART` writer - Slave START Detection Interrupt"]
pub type INT_EVENT0_ICLR_SSTART_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SSTART_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SSTART_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sstart_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTART_AW :: INT_EVENT0_ICLR_SSTART_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sstart_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTART_AW :: INT_EVENT0_ICLR_SSTART_CLR) } } # [doc = "Slave STOP Detection Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SSTOP_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SSTOP_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SSTOP_CLR = 1 , } impl From < INT_EVENT0_ICLR_SSTOP_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SSTOP_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SSTOP` writer - Slave STOP Detection Interrupt"]
pub type INT_EVENT0_ICLR_SSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SSTOP_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sstop_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTOP_AW :: INT_EVENT0_ICLR_SSTOP_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sstop_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SSTOP_AW :: INT_EVENT0_ICLR_SSTOP_CLR) } } # [doc = "General Call Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SGENCALL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SGENCALL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SGENCALL_CLR = 1 , } impl From < INT_EVENT0_ICLR_SGENCALL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SGENCALL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SGENCALL` writer - General Call Interrupt"]
pub type INT_EVENT0_ICLR_SGENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SGENCALL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SGENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sgencall_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SGENCALL_AW :: INT_EVENT0_ICLR_SGENCALL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sgencall_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SGENCALL_AW :: INT_EVENT0_ICLR_SGENCALL_CLR) } } # [doc = "DMA Done 1 on Event Channel 2\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SDMA_DONE1_2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SDMA_DONE1_2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SDMA_DONE1_2_CLR = 1 , } impl From < INT_EVENT0_ICLR_SDMA_DONE1_2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SDMA_DONE1_2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SDMA_DONE1_2` writer - DMA Done 1 on Event Channel 2"]
pub type INT_EVENT0_ICLR_SDMA_DONE1_2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SDMA_DONE1_2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SDMA_DONE1_2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_2_AW :: INT_EVENT0_ICLR_SDMA_DONE1_2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_2_AW :: INT_EVENT0_ICLR_SDMA_DONE1_2_CLR) } } # [doc = "DMA Done 1 on Event Channel 3\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SDMA_DONE1_3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SDMA_DONE1_3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SDMA_DONE1_3_CLR = 1 , } impl From < INT_EVENT0_ICLR_SDMA_DONE1_3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SDMA_DONE1_3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SDMA_DONE1_3` writer - DMA Done 1 on Event Channel 3"]
pub type INT_EVENT0_ICLR_SDMA_DONE1_3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SDMA_DONE1_3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SDMA_DONE1_3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_3_AW :: INT_EVENT0_ICLR_SDMA_DONE1_3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sdma_done1_3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SDMA_DONE1_3_AW :: INT_EVENT0_ICLR_SDMA_DONE1_3_CLR) } } # [doc = "Slave RX Pec Error Interrupt\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SPEC_RX_ERR_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SPEC_RX_ERR_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SPEC_RX_ERR_CLR = 1 , } impl From < INT_EVENT0_ICLR_SPEC_RX_ERR_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SPEC_RX_ERR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SPEC_RX_ERR` writer - Slave RX Pec Error Interrupt"]
pub type INT_EVENT0_ICLR_SPEC_RX_ERR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SPEC_RX_ERR_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SPEC_RX_ERR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_spec_rx_err_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SPEC_RX_ERR_AW :: INT_EVENT0_ICLR_SPEC_RX_ERR_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_spec_rx_err_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SPEC_RX_ERR_AW :: INT_EVENT0_ICLR_SPEC_RX_ERR_CLR) } } # [doc = "Slave TX FIFO underflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_STX_UNFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_STX_UNFL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_STX_UNFL_CLR = 1 , } impl From < INT_EVENT0_ICLR_STX_UNFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_STX_UNFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_STX_UNFL` writer - Slave TX FIFO underflow"]
pub type INT_EVENT0_ICLR_STX_UNFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_STX_UNFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_STX_UNFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_stx_unfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STX_UNFL_AW :: INT_EVENT0_ICLR_STX_UNFL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_stx_unfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_STX_UNFL_AW :: INT_EVENT0_ICLR_STX_UNFL_CLR) } } # [doc = "Slave RX FIFO overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SRX_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SRX_OVFL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SRX_OVFL_CLR = 1 , } impl From < INT_EVENT0_ICLR_SRX_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SRX_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SRX_OVFL` writer - Slave RX FIFO overflow"]
pub type INT_EVENT0_ICLR_SRX_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SRX_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SRX_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_srx_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRX_OVFL_AW :: INT_EVENT0_ICLR_SRX_OVFL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_srx_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SRX_OVFL_AW :: INT_EVENT0_ICLR_SRX_OVFL_CLR) } } # [doc = "Slave Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_SARBLOST_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_SARBLOST_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_SARBLOST_CLR = 1 , } impl From < INT_EVENT0_ICLR_SARBLOST_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_SARBLOST_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_SARBLOST` writer - Slave Arbitration Lost"]
pub type INT_EVENT0_ICLR_SARBLOST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_SARBLOST_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_SARBLOST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_sarblost_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SARBLOST_AW :: INT_EVENT0_ICLR_SARBLOST_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_sarblost_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_SARBLOST_AW :: INT_EVENT0_ICLR_SARBLOST_CLR) } } # [doc = "Interrupt overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_INTR_OVFL_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_INTR_OVFL_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_INTR_OVFL_CLR = 1 , } impl From < INT_EVENT0_ICLR_INTR_OVFL_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_INTR_OVFL_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_INTR_OVFL` writer - Interrupt overflow"]
pub type INT_EVENT0_ICLR_INTR_OVFL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_INTR_OVFL_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_INTR_OVFL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_intr_ovfl_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_INTR_OVFL_AW :: INT_EVENT0_ICLR_INTR_OVFL_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_intr_ovfl_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_INTR_OVFL_AW :: INT_EVENT0_ICLR_INTR_OVFL_CLR) } } impl W { # [doc = "Bit 0 - Master Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mrxdone (& mut self) -> INT_EVENT0_ICLR_MRXDONE_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_MRXDONE_W :: new (self) } # [doc = "Bit 1 - Master Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mtxdone (& mut self) -> INT_EVENT0_ICLR_MTXDONE_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_MTXDONE_W :: new (self) } # [doc = "Bit 2 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mrxfifotrg (& mut self) -> INT_EVENT0_ICLR_MRXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mtxfifotrg (& mut self) -> INT_EVENT0_ICLR_MTXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 4 - RXFIFO full event."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mrxfifofull (& mut self) -> INT_EVENT0_ICLR_MRXFIFOFULL_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_MRXFIFOFULL_W :: new (self) } # [doc = "Bit 5 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mtxempty (& mut self) -> INT_EVENT0_ICLR_MTXEMPTY_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_MTXEMPTY_W :: new (self) } # [doc = "Bit 7 - Address/Data NACK Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mnack (& mut self) -> INT_EVENT0_ICLR_MNACK_W < INT_EVENT0_ICLR_SPEC , 7 > { INT_EVENT0_ICLR_MNACK_W :: new (self) } # [doc = "Bit 8 - START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mstart (& mut self) -> INT_EVENT0_ICLR_MSTART_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_MSTART_W :: new (self) } # [doc = "Bit 9 - STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mstop (& mut self) -> INT_EVENT0_ICLR_MSTOP_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_MSTOP_W :: new (self) } # [doc = "Bit 10 - Arbitration Lost Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_marblost (& mut self) -> INT_EVENT0_ICLR_MARBLOST_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_MARBLOST_W :: new (self) } # [doc = "Bit 11 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mdma_done1_2 (& mut self) -> INT_EVENT0_ICLR_MDMA_DONE1_2_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_MDMA_DONE1_2_W :: new (self) } # [doc = "Bit 12 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mdma_done1_3 (& mut self) -> INT_EVENT0_ICLR_MDMA_DONE1_3_W < INT_EVENT0_ICLR_SPEC , 12 > { INT_EVENT0_ICLR_MDMA_DONE1_3_W :: new (self) } # [doc = "Bit 13 - Master RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_mpec_rx_err (& mut self) -> INT_EVENT0_ICLR_MPEC_RX_ERR_W < INT_EVENT0_ICLR_SPEC , 13 > { INT_EVENT0_ICLR_MPEC_RX_ERR_W :: new (self) } # [doc = "Bit 14 - Timeout A interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_timeouta (& mut self) -> INT_EVENT0_ICLR_TIMEOUTA_W < INT_EVENT0_ICLR_SPEC , 14 > { INT_EVENT0_ICLR_TIMEOUTA_W :: new (self) } # [doc = "Bit 15 - Timeout B Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_timeoutb (& mut self) -> INT_EVENT0_ICLR_TIMEOUTB_W < INT_EVENT0_ICLR_SPEC , 15 > { INT_EVENT0_ICLR_TIMEOUTB_W :: new (self) } # [doc = "Bit 16 - Slave Receive Data Interrupt Signals that a byte has been received"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srxdone (& mut self) -> INT_EVENT0_ICLR_SRXDONE_W < INT_EVENT0_ICLR_SPEC , 16 > { INT_EVENT0_ICLR_SRXDONE_W :: new (self) } # [doc = "Bit 17 - Slave Transmit Transaction completed Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stxdone (& mut self) -> INT_EVENT0_ICLR_STXDONE_W < INT_EVENT0_ICLR_SPEC , 17 > { INT_EVENT0_ICLR_STXDONE_W :: new (self) } # [doc = "Bit 18 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srxfifotrg (& mut self) -> INT_EVENT0_ICLR_SRXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 18 > { INT_EVENT0_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 19 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stxfifotrg (& mut self) -> INT_EVENT0_ICLR_STXFIFOTRG_W < INT_EVENT0_ICLR_SPEC , 19 > { INT_EVENT0_ICLR_STXFIFOTRG_W :: new (self) } # [doc = "Bit 20 - RXFIFO full event. This interrupt is set if an RX FIFO is full."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srxfifofull (& mut self) -> INT_EVENT0_ICLR_SRXFIFOFULL_W < INT_EVENT0_ICLR_SPEC , 20 > { INT_EVENT0_ICLR_SRXFIFOFULL_W :: new (self) } # [doc = "Bit 21 - Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been shifted out and the transmit goes into idle mode."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stxempty (& mut self) -> INT_EVENT0_ICLR_STXEMPTY_W < INT_EVENT0_ICLR_SPEC , 21 > { INT_EVENT0_ICLR_STXEMPTY_W :: new (self) } # [doc = "Bit 22 - Slave START Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sstart (& mut self) -> INT_EVENT0_ICLR_SSTART_W < INT_EVENT0_ICLR_SPEC , 22 > { INT_EVENT0_ICLR_SSTART_W :: new (self) } # [doc = "Bit 23 - Slave STOP Detection Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sstop (& mut self) -> INT_EVENT0_ICLR_SSTOP_W < INT_EVENT0_ICLR_SPEC , 23 > { INT_EVENT0_ICLR_SSTOP_W :: new (self) } # [doc = "Bit 24 - General Call Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sgencall (& mut self) -> INT_EVENT0_ICLR_SGENCALL_W < INT_EVENT0_ICLR_SPEC , 24 > { INT_EVENT0_ICLR_SGENCALL_W :: new (self) } # [doc = "Bit 25 - DMA Done 1 on Event Channel 2"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sdma_done1_2 (& mut self) -> INT_EVENT0_ICLR_SDMA_DONE1_2_W < INT_EVENT0_ICLR_SPEC , 25 > { INT_EVENT0_ICLR_SDMA_DONE1_2_W :: new (self) } # [doc = "Bit 26 - DMA Done 1 on Event Channel 3"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sdma_done1_3 (& mut self) -> INT_EVENT0_ICLR_SDMA_DONE1_3_W < INT_EVENT0_ICLR_SPEC , 26 > { INT_EVENT0_ICLR_SDMA_DONE1_3_W :: new (self) } # [doc = "Bit 27 - Slave RX Pec Error Interrupt"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_spec_rx_err (& mut self) -> INT_EVENT0_ICLR_SPEC_RX_ERR_W < INT_EVENT0_ICLR_SPEC , 27 > { INT_EVENT0_ICLR_SPEC_RX_ERR_W :: new (self) } # [doc = "Bit 28 - Slave TX FIFO underflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_stx_unfl (& mut self) -> INT_EVENT0_ICLR_STX_UNFL_W < INT_EVENT0_ICLR_SPEC , 28 > { INT_EVENT0_ICLR_STX_UNFL_W :: new (self) } # [doc = "Bit 29 - Slave RX FIFO overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_srx_ovfl (& mut self) -> INT_EVENT0_ICLR_SRX_OVFL_W < INT_EVENT0_ICLR_SPEC , 29 > { INT_EVENT0_ICLR_SRX_OVFL_W :: new (self) } # [doc = "Bit 30 - Slave Arbitration Lost"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_sarblost (& mut self) -> INT_EVENT0_ICLR_SARBLOST_W < INT_EVENT0_ICLR_SPEC , 30 > { INT_EVENT0_ICLR_SARBLOST_W :: new (self) } # [doc = "Bit 31 - Interrupt overflow"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_intr_ovfl (& mut self) -> INT_EVENT0_ICLR_INTR_OVFL_W < INT_EVENT0_ICLR_SPEC , 31 > { INT_EVENT0_ICLR_INTR_OVFL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iidx`]
module"]
pub type INT_EVENT1_IIDX = crate :: Reg < int_event1_iidx :: INT_EVENT1_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event1_iidx { # [doc = "Register `INT_EVENT1_IIDX` reader"]
pub type R = crate :: R < INT_EVENT1_IIDX_SPEC > ; # [doc = "Field `INT_EVENT1_IIDX_STAT` reader - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
pub type INT_EVENT1_IIDX_STAT_R = crate :: FieldReader < INT_EVENT1_IIDX_STAT_A > ; # [doc = "I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT1_IIDX_STAT_NO_INTR = 0 , # [doc = "1: MRXFIFOTRG"]
INT_EVENT1_IIDX_STAT_MRXFIFOTRG = 1 , # [doc = "2: MTXFIFOTRG"]
INT_EVENT1_IIDX_STAT_MTXFIFOTRG = 2 , # [doc = "3: SRXFIFOTRG"]
INT_EVENT1_IIDX_STAT_SRXFIFOTRG = 3 , # [doc = "4: STXFIFOTRG"]
INT_EVENT1_IIDX_STAT_STXFIFOTRG = 4 , } impl From < INT_EVENT1_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT1_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MRXFIFOTRG) , 2 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MTXFIFOTRG) , 3 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_SRXFIFOTRG) , 4 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_STXFIFOTRG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR } # [doc = "MRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_mrxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MRXFIFOTRG } # [doc = "MTXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_mtxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MTXFIFOTRG } # [doc = "SRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_srxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_SRXFIFOTRG } # [doc = "STXFIFOTRG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_stxfifotrg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_STXFIFOTRG } } impl R { # [doc = "Bits 0:7 - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event1_iidx_stat (& self) -> INT_EVENT1_IIDX_STAT_R { INT_EVENT1_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_imask`]
module"]
pub type INT_EVENT1_IMASK = crate :: Reg < int_event1_imask :: INT_EVENT1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event1_imask { # [doc = "Register `INT_EVENT1_IMASK` reader"]
pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"]
pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MRXFIFOTRG_A :: INT_EVENT1_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MTXFIFOTRG_A :: INT_EVENT1_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_SRXFIFOTRG_A :: INT_EVENT1_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT1_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_IMASK_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_CLR , true => INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_STXFIFOTRG_A :: INT_EVENT1_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event1_imask_mrxfifotrg (& self) -> INT_EVENT1_IMASK_MRXFIFOTRG_R { INT_EVENT1_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event1_imask_mtxfifotrg (& self) -> INT_EVENT1_IMASK_MTXFIFOTRG_R { INT_EVENT1_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event1_imask_srxfifotrg (& self) -> INT_EVENT1_IMASK_SRXFIFOTRG_R { INT_EVENT1_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event1_imask_stxfifotrg (& self) -> INT_EVENT1_IMASK_STXFIFOTRG_R { INT_EVENT1_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_mrxfifotrg (& mut self) -> INT_EVENT1_IMASK_MRXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 0 > { INT_EVENT1_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_mtxfifotrg (& mut self) -> INT_EVENT1_IMASK_MTXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 1 > { INT_EVENT1_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_srxfifotrg (& mut self) -> INT_EVENT1_IMASK_SRXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 2 > { INT_EVENT1_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_stxfifotrg (& mut self) -> INT_EVENT1_IMASK_STXFIFOTRG_W < INT_EVENT1_IMASK_SPEC , 3 > { INT_EVENT1_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_ris`]
module"]
pub type INT_EVENT1_RIS = crate :: Reg < int_event1_ris :: INT_EVENT1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event1_ris { # [doc = "Register `INT_EVENT1_RIS` reader"]
pub type R = crate :: R < INT_EVENT1_RIS_SPEC > ; # [doc = "Field `INT_EVENT1_RIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_RIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_CLR , true => INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_MRXFIFOTRG_A :: INT_EVENT1_RIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_RIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_RIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_CLR , true => INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_MTXFIFOTRG_A :: INT_EVENT1_RIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_RIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_RIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_CLR , true => INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_srxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_SRXFIFOTRG_A :: INT_EVENT1_RIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_RIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_RIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT1_RIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_RIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_CLR , true => INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_stxfifotrg_set (& self) -> bool { * self == INT_EVENT1_RIS_STXFIFOTRG_A :: INT_EVENT1_RIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event1_ris_mrxfifotrg (& self) -> INT_EVENT1_RIS_MRXFIFOTRG_R { INT_EVENT1_RIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event1_ris_mtxfifotrg (& self) -> INT_EVENT1_RIS_MTXFIFOTRG_R { INT_EVENT1_RIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event1_ris_srxfifotrg (& self) -> INT_EVENT1_RIS_SRXFIFOTRG_R { INT_EVENT1_RIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event1_ris_stxfifotrg (& self) -> INT_EVENT1_RIS_STXFIFOTRG_R { INT_EVENT1_RIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_RIS to value 0"]
impl crate :: Resettable for INT_EVENT1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_mis`]
module"]
pub type INT_EVENT1_MIS = crate :: Reg < int_event1_mis :: INT_EVENT1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event1_mis { # [doc = "Register `INT_EVENT1_MIS` reader"]
pub type R = crate :: R < INT_EVENT1_MIS_SPEC > ; # [doc = "Field `INT_EVENT1_MIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_MIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_CLR , true => INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_MRXFIFOTRG_A :: INT_EVENT1_MIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_MIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_MIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_CLR , true => INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_MTXFIFOTRG_A :: INT_EVENT1_MIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_MIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_MIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_CLR , true => INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_srxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_SRXFIFOTRG_A :: INT_EVENT1_MIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT1_MIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_MIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT1_MIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_MIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_CLR , true => INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_stxfifotrg_set (& self) -> bool { * self == INT_EVENT1_MIS_STXFIFOTRG_A :: INT_EVENT1_MIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event1_mis_mrxfifotrg (& self) -> INT_EVENT1_MIS_MRXFIFOTRG_R { INT_EVENT1_MIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event1_mis_mtxfifotrg (& self) -> INT_EVENT1_MIS_MTXFIFOTRG_R { INT_EVENT1_MIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event1_mis_srxfifotrg (& self) -> INT_EVENT1_MIS_SRXFIFOTRG_R { INT_EVENT1_MIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event1_mis_stxfifotrg (& self) -> INT_EVENT1_MIS_STXFIFOTRG_R { INT_EVENT1_MIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_MIS to value 0"]
impl crate :: Resettable for INT_EVENT1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iset`]
module"]
pub type INT_EVENT1_ISET = crate :: Reg < int_event1_iset :: INT_EVENT1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event1_iset { # [doc = "Register `INT_EVENT1_ISET` writer"]
pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MRXFIFOTRG_AW :: INT_EVENT1_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MTXFIFOTRG_AW :: INT_EVENT1_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_SRXFIFOTRG_AW :: INT_EVENT1_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT1_ISET_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_STXFIFOTRG_AW :: INT_EVENT1_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_mrxfifotrg (& mut self) -> INT_EVENT1_ISET_MRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 0 > { INT_EVENT1_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_mtxfifotrg (& mut self) -> INT_EVENT1_ISET_MTXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 1 > { INT_EVENT1_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_srxfifotrg (& mut self) -> INT_EVENT1_ISET_SRXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_stxfifotrg (& mut self) -> INT_EVENT1_ISET_STXFIFOTRG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"]
impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iclr`]
module"]
pub type INT_EVENT1_ICLR = crate :: Reg < int_event1_iclr :: INT_EVENT1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event1_iclr { # [doc = "Register `INT_EVENT1_ICLR` writer"]
pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MRXFIFOTRG_AW :: INT_EVENT1_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MTXFIFOTRG_AW :: INT_EVENT1_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_SRXFIFOTRG_AW :: INT_EVENT1_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT1_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_STXFIFOTRG_AW :: INT_EVENT1_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_mrxfifotrg (& mut self) -> INT_EVENT1_ICLR_MRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 0 > { INT_EVENT1_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_mtxfifotrg (& mut self) -> INT_EVENT1_ICLR_MTXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 1 > { INT_EVENT1_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_srxfifotrg (& mut self) -> INT_EVENT1_ICLR_SRXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_stxfifotrg (& mut self) -> INT_EVENT1_ICLR_STXFIFOTRG_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iidx`]
module"]
pub type INT_EVENT2_IIDX = crate :: Reg < int_event2_iidx :: INT_EVENT2_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event2_iidx { # [doc = "Register `INT_EVENT2_IIDX` reader"]
pub type R = crate :: R < INT_EVENT2_IIDX_SPEC > ; # [doc = "Field `INT_EVENT2_IIDX_STAT` reader - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
pub type INT_EVENT2_IIDX_STAT_R = crate :: FieldReader < INT_EVENT2_IIDX_STAT_A > ; # [doc = "I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum INT_EVENT2_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT2_IIDX_STAT_NO_INTR = 0 , # [doc = "1: MRXFIFOTRG"]
INT_EVENT2_IIDX_STAT_MRXFIFOTRG = 1 , # [doc = "2: MTXFIFOTRG"]
INT_EVENT2_IIDX_STAT_MTXFIFOTRG = 2 , # [doc = "3: SRXFIFOTRG"]
INT_EVENT2_IIDX_STAT_SRXFIFOTRG = 3 , # [doc = "4: STXFIFOTRG"]
INT_EVENT2_IIDX_STAT_STXFIFOTRG = 4 , } impl From < INT_EVENT2_IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : INT_EVENT2_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT2_IIDX_STAT_A { type Ux = u8 ; } impl INT_EVENT2_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT2_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MRXFIFOTRG) , 2 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MTXFIFOTRG) , 3 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_SRXFIFOTRG) , 4 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_STXFIFOTRG) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR } # [doc = "MRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_mrxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MRXFIFOTRG } # [doc = "MTXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_mtxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MTXFIFOTRG } # [doc = "SRXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_srxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_SRXFIFOTRG } # [doc = "STXFIFOTRG"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_stxfifotrg (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_STXFIFOTRG } } impl R { # [doc = "Bits 0:7 - I2C Module Interrupt Vector Value. This register provides the highes priority interrupt index. A read clears the corresponding interrupt flag in RIS and MISC. 15h-1Fh = Reserved"]
# [inline (always)]
pub fn int_event2_iidx_stat (& self) -> INT_EVENT2_IIDX_STAT_R { INT_EVENT2_IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT2_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_imask`]
module"]
pub type INT_EVENT2_IMASK = crate :: Reg < int_event2_imask :: INT_EVENT2_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event2_imask { # [doc = "Register `INT_EVENT2_IMASK` reader"]
pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"]
pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_IMASK_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MRXFIFOTRG_A :: INT_EVENT2_IMASK_MRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_IMASK_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR , true => INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MTXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MTXFIFOTRG_A :: INT_EVENT2_IMASK_MTXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_IMASK_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR , true => INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_SRXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_SRXFIFOTRG_A :: INT_EVENT2_IMASK_SRXFIFOTRG_SET) } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_IMASK_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_IMASK_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_IMASK_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR , true => INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_IMASK_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_STXFIFOTRG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_STXFIFOTRG_A :: INT_EVENT2_IMASK_STXFIFOTRG_SET) } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event2_imask_mrxfifotrg (& self) -> INT_EVENT2_IMASK_MRXFIFOTRG_R { INT_EVENT2_IMASK_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event2_imask_mtxfifotrg (& self) -> INT_EVENT2_IMASK_MTXFIFOTRG_R { INT_EVENT2_IMASK_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event2_imask_srxfifotrg (& self) -> INT_EVENT2_IMASK_SRXFIFOTRG_R { INT_EVENT2_IMASK_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event2_imask_stxfifotrg (& self) -> INT_EVENT2_IMASK_STXFIFOTRG_R { INT_EVENT2_IMASK_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_mrxfifotrg (& mut self) -> INT_EVENT2_IMASK_MRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 0 > { INT_EVENT2_IMASK_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_mtxfifotrg (& mut self) -> INT_EVENT2_IMASK_MTXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 1 > { INT_EVENT2_IMASK_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_srxfifotrg (& mut self) -> INT_EVENT2_IMASK_SRXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 2 > { INT_EVENT2_IMASK_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_stxfifotrg (& mut self) -> INT_EVENT2_IMASK_STXFIFOTRG_W < INT_EVENT2_IMASK_SPEC , 3 > { INT_EVENT2_IMASK_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_ris`]
module"]
pub type INT_EVENT2_RIS = crate :: Reg < int_event2_ris :: INT_EVENT2_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event2_ris { # [doc = "Register `INT_EVENT2_RIS` reader"]
pub type R = crate :: R < INT_EVENT2_RIS_SPEC > ; # [doc = "Field `INT_EVENT2_RIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_RIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_CLR , true => INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_MRXFIFOTRG_A :: INT_EVENT2_RIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_RIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_RIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_CLR , true => INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_MTXFIFOTRG_A :: INT_EVENT2_RIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_RIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_RIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_CLR , true => INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_SRXFIFOTRG_A :: INT_EVENT2_RIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_RIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_RIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_RIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_RIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_CLR , true => INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_RIS_STXFIFOTRG_A :: INT_EVENT2_RIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event2_ris_mrxfifotrg (& self) -> INT_EVENT2_RIS_MRXFIFOTRG_R { INT_EVENT2_RIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event2_ris_mtxfifotrg (& self) -> INT_EVENT2_RIS_MTXFIFOTRG_R { INT_EVENT2_RIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event2_ris_srxfifotrg (& self) -> INT_EVENT2_RIS_SRXFIFOTRG_R { INT_EVENT2_RIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event2_ris_stxfifotrg (& self) -> INT_EVENT2_RIS_STXFIFOTRG_R { INT_EVENT2_RIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_RIS to value 0"]
impl crate :: Resettable for INT_EVENT2_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_mis`]
module"]
pub type INT_EVENT2_MIS = crate :: Reg < int_event2_mis :: INT_EVENT2_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event2_mis { # [doc = "Register `INT_EVENT2_MIS` reader"]
pub type R = crate :: R < INT_EVENT2_MIS_SPEC > ; # [doc = "Field `INT_EVENT2_MIS_MRXFIFOTRG` reader - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_MIS_MRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_MRXFIFOTRG_A > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_MRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MRXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_CLR , true => INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_mrxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_mrxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_MRXFIFOTRG_A :: INT_EVENT2_MIS_MRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_MIS_MTXFIFOTRG` reader - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_MIS_MTXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_MTXFIFOTRG_A > ; # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MTXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MTXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_MTXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MTXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MTXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MTXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_CLR , true => INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_mtxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_mtxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_MTXFIFOTRG_A :: INT_EVENT2_MIS_MTXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_MIS_SRXFIFOTRG` reader - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_MIS_SRXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_SRXFIFOTRG_A > ; # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_SRXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_SRXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_SRXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_SRXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_SRXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_SRXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_CLR , true => INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_srxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_srxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_SRXFIFOTRG_A :: INT_EVENT2_MIS_SRXFIFOTRG_SET } } # [doc = "Field `INT_EVENT2_MIS_STXFIFOTRG` reader - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_MIS_STXFIFOTRG_R = crate :: BitReader < INT_EVENT2_MIS_STXFIFOTRG_A > ; # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_STXFIFOTRG_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_STXFIFOTRG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_MIS_STXFIFOTRG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_STXFIFOTRG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_STXFIFOTRG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_STXFIFOTRG_A { match self . bits { false => INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_CLR , true => INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_stxfifotrg_clr (& self) -> bool { * self == INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_stxfifotrg_set (& self) -> bool { * self == INT_EVENT2_MIS_STXFIFOTRG_A :: INT_EVENT2_MIS_STXFIFOTRG_SET } } impl R { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
pub fn int_event2_mis_mrxfifotrg (& self) -> INT_EVENT2_MIS_MRXFIFOTRG_R { INT_EVENT2_MIS_MRXFIFOTRG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
pub fn int_event2_mis_mtxfifotrg (& self) -> INT_EVENT2_MIS_MTXFIFOTRG_R { INT_EVENT2_MIS_MTXFIFOTRG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
pub fn int_event2_mis_srxfifotrg (& self) -> INT_EVENT2_MIS_SRXFIFOTRG_R { INT_EVENT2_MIS_SRXFIFOTRG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
pub fn int_event2_mis_stxfifotrg (& self) -> INT_EVENT2_MIS_STXFIFOTRG_R { INT_EVENT2_MIS_STXFIFOTRG_R :: new (((self . bits >> 3) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_MIS to value 0"]
impl crate :: Resettable for INT_EVENT2_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iset`]
module"]
pub type INT_EVENT2_ISET = crate :: Reg < int_event2_iset :: INT_EVENT2_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event2_iset { # [doc = "Register `INT_EVENT2_ISET` writer"]
pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_mrxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MRXFIFOTRG_AW :: INT_EVENT2_ISET_MRXFIFOTRG_SET) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MTXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_mtxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MTXFIFOTRG_AW :: INT_EVENT2_ISET_MTXFIFOTRG_SET) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_SRXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_srxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_SRXFIFOTRG_AW :: INT_EVENT2_ISET_SRXFIFOTRG_SET) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_STXFIFOTRG_SET = 1 , } impl From < INT_EVENT2_ISET_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_stxfifotrg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_STXFIFOTRG_AW :: INT_EVENT2_ISET_STXFIFOTRG_SET) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_mrxfifotrg (& mut self) -> INT_EVENT2_ISET_MRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 0 > { INT_EVENT2_ISET_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_mtxfifotrg (& mut self) -> INT_EVENT2_ISET_MTXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 1 > { INT_EVENT2_ISET_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_srxfifotrg (& mut self) -> INT_EVENT2_ISET_SRXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 2 > { INT_EVENT2_ISET_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_stxfifotrg (& mut self) -> INT_EVENT2_ISET_STXFIFOTRG_W < INT_EVENT2_ISET_SPEC , 3 > { INT_EVENT2_ISET_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"]
impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iclr`]
module"]
pub type INT_EVENT2_ICLR = crate :: Reg < int_event2_iclr :: INT_EVENT2_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event2_iclr { # [doc = "Register `INT_EVENT2_ICLR` writer"]
pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_MRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MRXFIFOTRG` writer - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
pub type INT_EVENT2_ICLR_MRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_mrxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MRXFIFOTRG_AW :: INT_EVENT2_ICLR_MRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_mrxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MRXFIFOTRG_AW :: INT_EVENT2_ICLR_MRXFIFOTRG_CLR) } } # [doc = "Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MTXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MTXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MTXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_MTXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MTXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MTXFIFOTRG` writer - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
pub type INT_EVENT2_ICLR_MTXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MTXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MTXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_mtxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MTXFIFOTRG_AW :: INT_EVENT2_ICLR_MTXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_mtxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MTXFIFOTRG_AW :: INT_EVENT2_ICLR_MTXFIFOTRG_CLR) } } # [doc = "Slave Receive FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_SRXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_SRXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_SRXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_SRXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_SRXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_SRXFIFOTRG` writer - Slave Receive FIFO Trigger"]
pub type INT_EVENT2_ICLR_SRXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_SRXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_SRXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_srxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_SRXFIFOTRG_AW :: INT_EVENT2_ICLR_SRXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_srxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_SRXFIFOTRG_AW :: INT_EVENT2_ICLR_SRXFIFOTRG_CLR) } } # [doc = "Slave Transmit FIFO Trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_STXFIFOTRG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_STXFIFOTRG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_STXFIFOTRG_CLR = 1 , } impl From < INT_EVENT2_ICLR_STXFIFOTRG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_STXFIFOTRG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_STXFIFOTRG` writer - Slave Transmit FIFO Trigger"]
pub type INT_EVENT2_ICLR_STXFIFOTRG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_STXFIFOTRG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_STXFIFOTRG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_stxfifotrg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_STXFIFOTRG_AW :: INT_EVENT2_ICLR_STXFIFOTRG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_stxfifotrg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_STXFIFOTRG_AW :: INT_EVENT2_ICLR_STXFIFOTRG_CLR) } } impl W { # [doc = "Bit 0 - Master Receive FIFO Trigger Trigger when RX FIFO contains &amp;gt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_mrxfifotrg (& mut self) -> INT_EVENT2_ICLR_MRXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 0 > { INT_EVENT2_ICLR_MRXFIFOTRG_W :: new (self) } # [doc = "Bit 1 - Master Transmit FIFO Trigger Trigger when Transmit FIFO contains &amp;lt;= defined bytes"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_mtxfifotrg (& mut self) -> INT_EVENT2_ICLR_MTXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 1 > { INT_EVENT2_ICLR_MTXFIFOTRG_W :: new (self) } # [doc = "Bit 2 - Slave Receive FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_srxfifotrg (& mut self) -> INT_EVENT2_ICLR_SRXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 2 > { INT_EVENT2_ICLR_SRXFIFOTRG_W :: new (self) } # [doc = "Bit 3 - Slave Transmit FIFO Trigger"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_stxfifotrg (& mut self) -> INT_EVENT2_ICLR_STXFIFOTRG_W < INT_EVENT2_ICLR_SPEC , 3 > { INT_EVENT2_ICLR_STXFIFOTRG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_INT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
pub type EVT_MODE_INT1_CFG_R = crate :: FieldReader < EVT_MODE_INT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_DISABLE) , 1 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_disable (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_software (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int1_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT1_CFG_A :: EVT_MODE_INT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT0\\]"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT1\\]"]
# [inline (always)]
pub fn evt_mode_int1_cfg (& self) -> EVT_MODE_INT1_CFG_R { EVT_MODE_INT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT2\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GFCTL (rw) register accessor: I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gfctl`]
module"]
pub type GFCTL = crate :: Reg < gfctl :: GFCTL_SPEC > ; # [doc = "I2C Glitch Filter Control"]
pub mod gfctl { # [doc = "Register `GFCTL` reader"]
pub type R = crate :: R < GFCTL_SPEC > ; # [doc = "Register `GFCTL` writer"]
pub type W = crate :: W < GFCTL_SPEC > ; # [doc = "Field `GFCTL_DGFSEL` reader - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
pub type GFCTL_DGFSEL_R = crate :: FieldReader < GFCTL_DGFSEL_A > ; # [doc = "Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GFCTL_DGFSEL_A { # [doc = "0: DISABLED"]
GFCTL_DGFSEL_DISABLED = 0 , # [doc = "1: CLK_1"]
GFCTL_DGFSEL_CLK_1 = 1 , # [doc = "2: CLK_2"]
GFCTL_DGFSEL_CLK_2 = 2 , # [doc = "3: CLK_3"]
GFCTL_DGFSEL_CLK_3 = 3 , # [doc = "4: CLK_4"]
GFCTL_DGFSEL_CLK_4 = 4 , # [doc = "5: CLK_8"]
GFCTL_DGFSEL_CLK_8 = 5 , # [doc = "6: CLK_16"]
GFCTL_DGFSEL_CLK_16 = 6 , # [doc = "7: CLK_31"]
GFCTL_DGFSEL_CLK_31 = 7 , } impl From < GFCTL_DGFSEL_A > for u8 { # [inline (always)]
fn from (variant : GFCTL_DGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_DGFSEL_A { type Ux = u8 ; } impl GFCTL_DGFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_DGFSEL_A { match self . bits { 0 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED , 1 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 , 2 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 , 3 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 , 4 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 , 5 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 , 6 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 , 7 => GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_gfctl_dgfsel_disabled (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED } # [doc = "CLK_1"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_1 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1 } # [doc = "CLK_2"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_2 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2 } # [doc = "CLK_3"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_3 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3 } # [doc = "CLK_4"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_4 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4 } # [doc = "CLK_8"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_8 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8 } # [doc = "CLK_16"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_16 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16 } # [doc = "CLK_31"]
# [inline (always)]
pub fn is_gfctl_dgfsel_clk_31 (& self) -> bool { * self == GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31 } } # [doc = "Field `GFCTL_DGFSEL` writer - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
pub type GFCTL_DGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , GFCTL_DGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_DGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn gfctl_dgfsel_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_DISABLED) } # [doc = "CLK_1"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_1 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_1) } # [doc = "CLK_2"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_2 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_2) } # [doc = "CLK_3"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_3 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_3) } # [doc = "CLK_4"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_4 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_4) } # [doc = "CLK_8"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_8 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_8) } # [doc = "CLK_16"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_16 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_16) } # [doc = "CLK_31"]
# [inline (always)]
pub fn gfctl_dgfsel_clk_31 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_DGFSEL_A :: GFCTL_DGFSEL_CLK_31) } } # [doc = "Field `GFCTL_AGFEN` reader - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_R = crate :: BitReader < GFCTL_AGFEN_A > ; # [doc = "Analog Glitch Suppression Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GFCTL_AGFEN_A { # [doc = "0: DISABLE"]
GFCTL_AGFEN_DISABLE = 0 , # [doc = "1: ENABLE"]
GFCTL_AGFEN_ENABLE = 1 , } impl From < GFCTL_AGFEN_A > for bool { # [inline (always)]
fn from (variant : GFCTL_AGFEN_A) -> Self { variant as u8 != 0 } } impl GFCTL_AGFEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFEN_A { match self . bits { false => GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE , true => GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_disable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_gfctl_agfen_enable (& self) -> bool { * self == GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE } } # [doc = "Field `GFCTL_AGFEN` writer - Analog Glitch Suppression Enable"]
pub type GFCTL_AGFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_AGFEN_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn gfctl_agfen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn gfctl_agfen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFEN_A :: GFCTL_AGFEN_ENABLE) } } # [doc = "Field `GFCTL_AGFSEL` reader - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
pub type GFCTL_AGFSEL_R = crate :: FieldReader < GFCTL_AGFSEL_A > ; # [doc = "Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum GFCTL_AGFSEL_A { # [doc = "0: AGLIT_5"]
GFCTL_AGFSEL_AGLIT_5 = 0 , # [doc = "1: AGLIT_10"]
GFCTL_AGFSEL_AGLIT_10 = 1 , # [doc = "2: AGLIT_25"]
GFCTL_AGFSEL_AGLIT_25 = 2 , # [doc = "3: AGLIT_50"]
GFCTL_AGFSEL_AGLIT_50 = 3 , } impl From < GFCTL_AGFSEL_A > for u8 { # [inline (always)]
fn from (variant : GFCTL_AGFSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for GFCTL_AGFSEL_A { type Ux = u8 ; } impl GFCTL_AGFSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_AGFSEL_A { match self . bits { 0 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 , 1 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 , 2 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 , 3 => GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 , _ => unreachable ! () , } } # [doc = "AGLIT_5"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_5 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5 } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_10 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10 } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_25 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25 } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn is_gfctl_agfsel_aglit_50 (& self) -> bool { * self == GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50 } } # [doc = "Field `GFCTL_AGFSEL` writer - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
pub type GFCTL_AGFSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , GFCTL_AGFSEL_A > ; impl < 'a , REG , const O : u8 > GFCTL_AGFSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "AGLIT_5"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_5 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_5) } # [doc = "AGLIT_10"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_10) } # [doc = "AGLIT_25"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_25 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_25) } # [doc = "AGLIT_50"]
# [inline (always)]
pub fn gfctl_agfsel_aglit_50 (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_AGFSEL_A :: GFCTL_AGFSEL_AGLIT_50) } } # [doc = "Field `GFCTL_CHAIN` reader - Analog and digital noise filters chaining enable."]
pub type GFCTL_CHAIN_R = crate :: BitReader < GFCTL_CHAIN_A > ; # [doc = "Analog and digital noise filters chaining enable.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GFCTL_CHAIN_A { # [doc = "0: DISABLE"]
GFCTL_CHAIN_DISABLE = 0 , # [doc = "1: ENABLE"]
GFCTL_CHAIN_ENABLE = 1 , } impl From < GFCTL_CHAIN_A > for bool { # [inline (always)]
fn from (variant : GFCTL_CHAIN_A) -> Self { variant as u8 != 0 } } impl GFCTL_CHAIN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GFCTL_CHAIN_A { match self . bits { false => GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE , true => GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_gfctl_chain_disable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_gfctl_chain_enable (& self) -> bool { * self == GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE } } # [doc = "Field `GFCTL_CHAIN` writer - Analog and digital noise filters chaining enable."]
pub type GFCTL_CHAIN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GFCTL_CHAIN_A > ; impl < 'a , REG , const O : u8 > GFCTL_CHAIN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn gfctl_chain_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn gfctl_chain_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GFCTL_CHAIN_A :: GFCTL_CHAIN_ENABLE) } } impl R { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
# [inline (always)]
pub fn gfctl_dgfsel (& self) -> GFCTL_DGFSEL_R { GFCTL_DGFSEL_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
pub fn gfctl_agfen (& self) -> GFCTL_AGFEN_R { GFCTL_AGFEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
# [inline (always)]
pub fn gfctl_agfsel (& self) -> GFCTL_AGFSEL_R { GFCTL_AGFSEL_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."]
# [inline (always)]
pub fn gfctl_chain (& self) -> GFCTL_CHAIN_R { GFCTL_CHAIN_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - Glitch Suppression Pulse Width This field controls the pulse width select for glitch suppression on the SCL and SDA lines. The following values are the glitch suppression values in terms of functional clocks. (Core Domain only)"]
# [inline (always)]
# [must_use]
pub fn gfctl_dgfsel (& mut self) -> GFCTL_DGFSEL_W < GFCTL_SPEC , 0 > { GFCTL_DGFSEL_W :: new (self) } # [doc = "Bit 8 - Analog Glitch Suppression Enable"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfen (& mut self) -> GFCTL_AGFEN_W < GFCTL_SPEC , 8 > { GFCTL_AGFEN_W :: new (self) } # [doc = "Bits 9:10 - Analog Glitch Suppression Pulse Width This field controls the pulse width select for the analog glitch suppression on SCL and SDA lines. See device datasheet for exact values. (ULP I2C only)"]
# [inline (always)]
# [must_use]
pub fn gfctl_agfsel (& mut self) -> GFCTL_AGFSEL_W < GFCTL_SPEC , 9 > { GFCTL_AGFSEL_W :: new (self) } # [doc = "Bit 11 - Analog and digital noise filters chaining enable."]
# [inline (always)]
# [must_use]
pub fn gfctl_chain (& mut self) -> GFCTL_CHAIN_W < GFCTL_SPEC , 11 > { GFCTL_CHAIN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Glitch Filter Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gfctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gfctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GFCTL_SPEC ; impl crate :: RegisterSpec for GFCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gfctl::R`](R) reader structure"]
impl crate :: Readable for GFCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gfctl::W`](W) writer structure"]
impl crate :: Writable for GFCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GFCTL to value 0"]
impl crate :: Resettable for GFCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TIMEOUT_CTL (rw) register accessor: I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeout_ctl`]
module"]
pub type TIMEOUT_CTL = crate :: Reg < timeout_ctl :: TIMEOUT_CTL_SPEC > ; # [doc = "I2C Timeout Count Control Register"]
pub mod timeout_ctl { # [doc = "Register `TIMEOUT_CTL` reader"]
pub type R = crate :: R < TIMEOUT_CTL_SPEC > ; # [doc = "Register `TIMEOUT_CTL` writer"]
pub type W = crate :: W < TIMEOUT_CTL_SPEC > ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` reader - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
pub type TIMEOUT_CTL_TCNTLA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLA` writer - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
pub type TIMEOUT_CTL_TCNTLA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTAEN` reader - Timeout Counter A Enable"]
pub type TIMEOUT_CTL_TCNTAEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTAEN_A > ; # [doc = "Timeout Counter A Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TIMEOUT_CTL_TCNTAEN_A { # [doc = "0: DISABLE"]
TIMEOUT_CTL_TCNTAEN_DISABLE = 0 , # [doc = "1: ENABLE"]
TIMEOUT_CTL_TCNTAEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTAEN_A > for bool { # [inline (always)]
fn from (variant : TIMEOUT_CTL_TCNTAEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTAEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TIMEOUT_CTL_TCNTAEN_A { match self . bits { false => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE , true => TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntaen_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntaen_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTAEN` writer - Timeout Counter A Enable"]
pub type TIMEOUT_CTL_TCNTAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTAEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTAEN_A :: TIMEOUT_CTL_TCNTAEN_ENABLE) } } # [doc = "Field `TIMEOUT_CTL_TCNTLB` reader - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
pub type TIMEOUT_CTL_TCNTLB_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CTL_TCNTLB` writer - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
pub type TIMEOUT_CTL_TCNTLB_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; # [doc = "Field `TIMEOUT_CTL_TCNTBEN` reader - Timeout Counter B Enable"]
pub type TIMEOUT_CTL_TCNTBEN_R = crate :: BitReader < TIMEOUT_CTL_TCNTBEN_A > ; # [doc = "Timeout Counter B Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TIMEOUT_CTL_TCNTBEN_A { # [doc = "0: DISABLE"]
TIMEOUT_CTL_TCNTBEN_DISABLE = 0 , # [doc = "1: ENABLE"]
TIMEOUT_CTL_TCNTBEN_ENABLE = 1 , } impl From < TIMEOUT_CTL_TCNTBEN_A > for bool { # [inline (always)]
fn from (variant : TIMEOUT_CTL_TCNTBEN_A) -> Self { variant as u8 != 0 } } impl TIMEOUT_CTL_TCNTBEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TIMEOUT_CTL_TCNTBEN_A { match self . bits { false => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE , true => TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntben_disable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_timeout_ctl_tcntben_enable (& self) -> bool { * self == TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE } } # [doc = "Field `TIMEOUT_CTL_TCNTBEN` writer - Timeout Counter B Enable"]
pub type TIMEOUT_CTL_TCNTBEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TIMEOUT_CTL_TCNTBEN_A > ; impl < 'a , REG , const O : u8 > TIMEOUT_CTL_TCNTBEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntben_disable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn timeout_ctl_tcntben_enable (self) -> & 'a mut crate :: W < REG > { self . variant (TIMEOUT_CTL_TCNTBEN_A :: TIMEOUT_CTL_TCNTBEN_ENABLE) } } impl R { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
# [inline (always)]
pub fn timeout_ctl_tcntla (& self) -> TIMEOUT_CTL_TCNTLA_R { TIMEOUT_CTL_TCNTLA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bit 15 - Timeout Counter A Enable"]
# [inline (always)]
pub fn timeout_ctl_tcntaen (& self) -> TIMEOUT_CTL_TCNTAEN_R { TIMEOUT_CTL_TCNTAEN_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
# [inline (always)]
pub fn timeout_ctl_tcntlb (& self) -> TIMEOUT_CTL_TCNTLB_R { TIMEOUT_CTL_TCNTLB_R :: new (((self . bits >> 16) & 0xff) as u8) } # [doc = "Bit 31 - Timeout Counter B Enable"]
# [inline (always)]
pub fn timeout_ctl_tcntben (& self) -> TIMEOUT_CTL_TCNTBEN_R { TIMEOUT_CTL_TCNTBEN_R :: new (((self . bits >> 31) & 1) != 0) } } impl W { # [doc = "Bits 0:7 - Timeout counter A load value Counter A is used for SCL low detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout A count. NOTE: The value of CNTLA must be greater than 1h. Each count is equal to 520 times the timeout period of functional clock. For example, with 8MHz functional clock and a 100KHz operating I2C clock, one timeout period will be equal to (1 / 8MHz) * 520 or 65 us."]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntla (& mut self) -> TIMEOUT_CTL_TCNTLA_W < TIMEOUT_CTL_SPEC , 0 > { TIMEOUT_CTL_TCNTLA_W :: new (self) } # [doc = "Bit 15 - Timeout Counter A Enable"]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntaen (& mut self) -> TIMEOUT_CTL_TCNTAEN_W < TIMEOUT_CTL_SPEC , 15 > { TIMEOUT_CTL_TCNTAEN_W :: new (self) } # [doc = "Bits 16:23 - Timeout Count B Load: Counter B is used for SCL High Detection. This field contains the upper 8 bits of a 12-bit pre-load value for the Timeout B count. NOTE: The value of CNTLB must be greater than 1h. Each count is equal to 1* clock period. For example, with 10MHz functional clock one timeout period will be equal to1*100ns."]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntlb (& mut self) -> TIMEOUT_CTL_TCNTLB_W < TIMEOUT_CTL_SPEC , 16 > { TIMEOUT_CTL_TCNTLB_W :: new (self) } # [doc = "Bit 31 - Timeout Counter B Enable"]
# [inline (always)]
# [must_use]
pub fn timeout_ctl_tcntben (& mut self) -> TIMEOUT_CTL_TCNTBEN_W < TIMEOUT_CTL_SPEC , 31 > { TIMEOUT_CTL_TCNTBEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Timeout Count Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`timeout_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TIMEOUT_CTL_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_ctl::R`](R) reader structure"]
impl crate :: Readable for TIMEOUT_CTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`timeout_ctl::W`](W) writer structure"]
impl crate :: Writable for TIMEOUT_CTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TIMEOUT_CTL to value 0x0002_0002"]
impl crate :: Resettable for TIMEOUT_CTL_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } } # [doc = "TIMEOUT_CNT (r) register accessor: I2C Timeout Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_cnt::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timeout_cnt`]
module"]
pub type TIMEOUT_CNT = crate :: Reg < timeout_cnt :: TIMEOUT_CNT_SPEC > ; # [doc = "I2C Timeout Count Register"]
pub mod timeout_cnt { # [doc = "Register `TIMEOUT_CNT` reader"]
pub type R = crate :: R < TIMEOUT_CNT_SPEC > ; # [doc = "Field `TIMEOUT_CNT_TCNTA` reader - Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"]
pub type TIMEOUT_CNT_TCNTA_R = crate :: FieldReader ; # [doc = "Field `TIMEOUT_CNT_TCNTB` reader - Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"]
pub type TIMEOUT_CNT_TCNTB_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Timeout Count A Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter A"]
# [inline (always)]
pub fn timeout_cnt_tcnta (& self) -> TIMEOUT_CNT_TCNTA_R { TIMEOUT_CNT_TCNTA_R :: new ((self . bits & 0xff) as u8) } # [doc = "Bits 16:23 - Timeout Count B Current Count: This field contains the upper 8 bits of a 12-bit current counter for timeout counter B"]
# [inline (always)]
pub fn timeout_cnt_tcntb (& self) -> TIMEOUT_CNT_TCNTB_R { TIMEOUT_CNT_TCNTB_R :: new (((self . bits >> 16) & 0xff) as u8) } } # [doc = "I2C Timeout Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`timeout_cnt::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TIMEOUT_CNT_SPEC ; impl crate :: RegisterSpec for TIMEOUT_CNT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`timeout_cnt::R`](R) reader structure"]
impl crate :: Readable for TIMEOUT_CNT_SPEC { } # [doc = "`reset()` method sets TIMEOUT_CNT to value 0x0002_0002"]
impl crate :: Resettable for TIMEOUT_CNT_SPEC { const RESET_VALUE : Self :: Ux = 0x0002_0002 ; } } # [doc = "MSA (rw) register accessor: I2C Master Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msa::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msa::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msa`]
module"]
pub type MSA = crate :: Reg < msa :: MSA_SPEC > ; # [doc = "I2C Master Slave Address Register"]
pub mod msa { # [doc = "Register `MSA` reader"]
pub type R = crate :: R < MSA_SPEC > ; # [doc = "Register `MSA` writer"]
pub type W = crate :: W < MSA_SPEC > ; # [doc = "Field `MSA_DIR` reader - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
pub type MSA_DIR_R = crate :: BitReader < MSA_DIR_A > ; # [doc = "Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSA_DIR_A { # [doc = "0: TRANSMIT"]
MSA_DIR_TRANSMIT = 0 , # [doc = "1: RECEIVE"]
MSA_DIR_RECEIVE = 1 , } impl From < MSA_DIR_A > for bool { # [inline (always)]
fn from (variant : MSA_DIR_A) -> Self { variant as u8 != 0 } } impl MSA_DIR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSA_DIR_A { match self . bits { false => MSA_DIR_A :: MSA_DIR_TRANSMIT , true => MSA_DIR_A :: MSA_DIR_RECEIVE , } } # [doc = "TRANSMIT"]
# [inline (always)]
pub fn is_msa_dir_transmit (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_TRANSMIT } # [doc = "RECEIVE"]
# [inline (always)]
pub fn is_msa_dir_receive (& self) -> bool { * self == MSA_DIR_A :: MSA_DIR_RECEIVE } } # [doc = "Field `MSA_DIR` writer - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
pub type MSA_DIR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_DIR_A > ; impl < 'a , REG , const O : u8 > MSA_DIR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "TRANSMIT"]
# [inline (always)]
pub fn msa_dir_transmit (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_TRANSMIT) } # [doc = "RECEIVE"]
# [inline (always)]
pub fn msa_dir_receive (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_DIR_A :: MSA_DIR_RECEIVE) } } # [doc = "Field `MSA_SADDR` reader - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
pub type MSA_SADDR_R = crate :: FieldReader < u16 > ; # [doc = "Field `MSA_SADDR` writer - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
pub type MSA_SADDR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `MSA_MMODE` reader - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type MSA_MMODE_R = crate :: BitReader < MSA_MMODE_A > ; # [doc = "This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSA_MMODE_A { # [doc = "0: MODE7"]
MSA_MMODE_MODE7 = 0 , # [doc = "1: MODE10"]
MSA_MMODE_MODE10 = 1 , } impl From < MSA_MMODE_A > for bool { # [inline (always)]
fn from (variant : MSA_MMODE_A) -> Self { variant as u8 != 0 } } impl MSA_MMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSA_MMODE_A { match self . bits { false => MSA_MMODE_A :: MSA_MMODE_MODE7 , true => MSA_MMODE_A :: MSA_MMODE_MODE10 , } } # [doc = "MODE7"]
# [inline (always)]
pub fn is_msa_mmode_mode7 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE7 } # [doc = "MODE10"]
# [inline (always)]
pub fn is_msa_mmode_mode10 (& self) -> bool { * self == MSA_MMODE_A :: MSA_MMODE_MODE10 } } # [doc = "Field `MSA_MMODE` writer - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type MSA_MMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MSA_MMODE_A > ; impl < 'a , REG , const O : u8 > MSA_MMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"]
# [inline (always)]
pub fn msa_mmode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE7) } # [doc = "MODE10"]
# [inline (always)]
pub fn msa_mmode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (MSA_MMODE_A :: MSA_MMODE_MODE10) } } impl R { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
# [inline (always)]
pub fn msa_dir (& self) -> MSA_DIR_R { MSA_DIR_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
pub fn msa_saddr (& self) -> MSA_SADDR_R { MSA_SADDR_R :: new (((self . bits >> 1) & 0x03ff) as u16) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
pub fn msa_mmode (& self) -> MSA_MMODE_R { MSA_MMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bit 0 - Receive/Send The DIR bit specifies if the next master operation is a Receive (High) or Transmit (Low). 0h = Transmit 1h = Receive"]
# [inline (always)]
# [must_use]
pub fn msa_dir (& mut self) -> MSA_DIR_W < MSA_SPEC , 0 > { MSA_DIR_W :: new (self) } # [doc = "Bits 1:10 - I2C Slave Address This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by MSA.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
# [must_use]
pub fn msa_saddr (& mut self) -> MSA_SADDR_W < MSA_SPEC , 1 > { MSA_SADDR_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in master mode When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
# [must_use]
pub fn msa_mmode (& mut self) -> MSA_MMODE_W < MSA_SPEC , 15 > { MSA_MMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Slave Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msa::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`msa::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MSA_SPEC ; impl crate :: RegisterSpec for MSA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`msa::R`](R) reader structure"]
impl crate :: Readable for MSA_SPEC { } # [doc = "`write(|w| ..)` method takes [`msa::W`](W) writer structure"]
impl crate :: Writable for MSA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MSA to value 0"]
impl crate :: Resettable for MSA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MCTR (rw) register accessor: I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mctr`]
module"]
pub type MCTR = crate :: Reg < mctr :: MCTR_SPEC > ; # [doc = "I2C Master Control Register"]
pub mod mctr { # [doc = "Register `MCTR` reader"]
pub type R = crate :: R < MCTR_SPEC > ; # [doc = "Register `MCTR` writer"]
pub type W = crate :: W < MCTR_SPEC > ; # [doc = "Field `MCTR_BURSTRUN` reader - I2C Master Enable and start transaction"]
pub type MCTR_BURSTRUN_R = crate :: BitReader < MCTR_BURSTRUN_A > ; # [doc = "I2C Master Enable and start transaction\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_BURSTRUN_A { # [doc = "0: DISABLE"]
MCTR_BURSTRUN_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_BURSTRUN_ENABLE = 1 , } impl From < MCTR_BURSTRUN_A > for bool { # [inline (always)]
fn from (variant : MCTR_BURSTRUN_A) -> Self { variant as u8 != 0 } } impl MCTR_BURSTRUN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_BURSTRUN_A { match self . bits { false => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE , true => MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_burstrun_disable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_burstrun_enable (& self) -> bool { * self == MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE } } # [doc = "Field `MCTR_BURSTRUN` writer - I2C Master Enable and start transaction"]
pub type MCTR_BURSTRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_BURSTRUN_A > ; impl < 'a , REG , const O : u8 > MCTR_BURSTRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_burstrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_burstrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_BURSTRUN_A :: MCTR_BURSTRUN_ENABLE) } } # [doc = "Field `MCTR_START` reader - Generate START"]
pub type MCTR_START_R = crate :: BitReader < MCTR_START_A > ; # [doc = "Generate START\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_START_A { # [doc = "0: DISABLE"]
MCTR_START_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_START_ENABLE = 1 , } impl From < MCTR_START_A > for bool { # [inline (always)]
fn from (variant : MCTR_START_A) -> Self { variant as u8 != 0 } } impl MCTR_START_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_START_A { match self . bits { false => MCTR_START_A :: MCTR_START_DISABLE , true => MCTR_START_A :: MCTR_START_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_start_disable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_start_enable (& self) -> bool { * self == MCTR_START_A :: MCTR_START_ENABLE } } # [doc = "Field `MCTR_START` writer - Generate START"]
pub type MCTR_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_START_A > ; impl < 'a , REG , const O : u8 > MCTR_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_START_A :: MCTR_START_ENABLE) } } # [doc = "Field `MCTR_STOP` reader - Generate STOP"]
pub type MCTR_STOP_R = crate :: BitReader < MCTR_STOP_A > ; # [doc = "Generate STOP\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_STOP_A { # [doc = "0: DISABLE"]
MCTR_STOP_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_STOP_ENABLE = 1 , } impl From < MCTR_STOP_A > for bool { # [inline (always)]
fn from (variant : MCTR_STOP_A) -> Self { variant as u8 != 0 } } impl MCTR_STOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_STOP_A { match self . bits { false => MCTR_STOP_A :: MCTR_STOP_DISABLE , true => MCTR_STOP_A :: MCTR_STOP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_stop_disable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_stop_enable (& self) -> bool { * self == MCTR_STOP_A :: MCTR_STOP_ENABLE } } # [doc = "Field `MCTR_STOP` writer - Generate STOP"]
pub type MCTR_STOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_STOP_A > ; impl < 'a , REG , const O : u8 > MCTR_STOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_stop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_stop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_STOP_A :: MCTR_STOP_ENABLE) } } # [doc = "Field `MCTR_ACK` reader - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
pub type MCTR_ACK_R = crate :: BitReader < MCTR_ACK_A > ; # [doc = "Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_ACK_A { # [doc = "0: DISABLE"]
MCTR_ACK_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_ACK_ENABLE = 1 , } impl From < MCTR_ACK_A > for bool { # [inline (always)]
fn from (variant : MCTR_ACK_A) -> Self { variant as u8 != 0 } } impl MCTR_ACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_ACK_A { match self . bits { false => MCTR_ACK_A :: MCTR_ACK_DISABLE , true => MCTR_ACK_A :: MCTR_ACK_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_ack_disable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_ack_enable (& self) -> bool { * self == MCTR_ACK_A :: MCTR_ACK_ENABLE } } # [doc = "Field `MCTR_ACK` writer - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
pub type MCTR_ACK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_ACK_A > ; impl < 'a , REG , const O : u8 > MCTR_ACK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_ack_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_ack_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_ACK_A :: MCTR_ACK_ENABLE) } } # [doc = "Field `MCTR_MACKOEN` reader - Master ACK overrride Enable"]
pub type MCTR_MACKOEN_R = crate :: BitReader < MCTR_MACKOEN_A > ; # [doc = "Master ACK overrride Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_MACKOEN_A { # [doc = "0: DISABLE"]
MCTR_MACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_MACKOEN_ENABLE = 1 , } impl From < MCTR_MACKOEN_A > for bool { # [inline (always)]
fn from (variant : MCTR_MACKOEN_A) -> Self { variant as u8 != 0 } } impl MCTR_MACKOEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_MACKOEN_A { match self . bits { false => MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE , true => MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_mackoen_disable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_mackoen_enable (& self) -> bool { * self == MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE } } # [doc = "Field `MCTR_MACKOEN` writer - Master ACK overrride Enable"]
pub type MCTR_MACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_MACKOEN_A > ; impl < 'a , REG , const O : u8 > MCTR_MACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_mackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_mackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_MACKOEN_A :: MCTR_MACKOEN_ENABLE) } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` reader - Read on TX Empty"]
pub type MCTR_RD_ON_TXEMPTY_R = crate :: BitReader < MCTR_RD_ON_TXEMPTY_A > ; # [doc = "Read on TX Empty\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCTR_RD_ON_TXEMPTY_A { # [doc = "0: DISABLE"]
MCTR_RD_ON_TXEMPTY_DISABLE = 0 , # [doc = "1: ENABLE"]
MCTR_RD_ON_TXEMPTY_ENABLE = 1 , } impl From < MCTR_RD_ON_TXEMPTY_A > for bool { # [inline (always)]
fn from (variant : MCTR_RD_ON_TXEMPTY_A) -> Self { variant as u8 != 0 } } impl MCTR_RD_ON_TXEMPTY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCTR_RD_ON_TXEMPTY_A { match self . bits { false => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE , true => MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mctr_rd_on_txempty_disable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mctr_rd_on_txempty_enable (& self) -> bool { * self == MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE } } # [doc = "Field `MCTR_RD_ON_TXEMPTY` writer - Read on TX Empty"]
pub type MCTR_RD_ON_TXEMPTY_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCTR_RD_ON_TXEMPTY_A > ; impl < 'a , REG , const O : u8 > MCTR_RD_ON_TXEMPTY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mctr_rd_on_txempty_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mctr_rd_on_txempty_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCTR_RD_ON_TXEMPTY_A :: MCTR_RD_ON_TXEMPTY_ENABLE) } } # [doc = "Field `MCTR_MBLEN` reader - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
pub type MCTR_MBLEN_R = crate :: FieldReader < u16 > ; # [doc = "Field `MCTR_MBLEN` writer - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
pub type MCTR_MBLEN_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 12 , O , u16 > ; impl R { # [doc = "Bit 0 - I2C Master Enable and start transaction"]
# [inline (always)]
pub fn mctr_burstrun (& self) -> MCTR_BURSTRUN_R { MCTR_BURSTRUN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Generate START"]
# [inline (always)]
pub fn mctr_start (& self) -> MCTR_START_R { MCTR_START_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Generate STOP"]
# [inline (always)]
pub fn mctr_stop (& self) -> MCTR_STOP_R { MCTR_STOP_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
# [inline (always)]
pub fn mctr_ack (& self) -> MCTR_ACK_R { MCTR_ACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Master ACK overrride Enable"]
# [inline (always)]
pub fn mctr_mackoen (& self) -> MCTR_MACKOEN_R { MCTR_MACKOEN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Read on TX Empty"]
# [inline (always)]
pub fn mctr_rd_on_txempty (& self) -> MCTR_RD_ON_TXEMPTY_R { MCTR_RD_ON_TXEMPTY_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
# [inline (always)]
pub fn mctr_mblen (& self) -> MCTR_MBLEN_R { MCTR_MBLEN_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } impl W { # [doc = "Bit 0 - I2C Master Enable and start transaction"]
# [inline (always)]
# [must_use]
pub fn mctr_burstrun (& mut self) -> MCTR_BURSTRUN_W < MCTR_SPEC , 0 > { MCTR_BURSTRUN_W :: new (self) } # [doc = "Bit 1 - Generate START"]
# [inline (always)]
# [must_use]
pub fn mctr_start (& mut self) -> MCTR_START_W < MCTR_SPEC , 1 > { MCTR_START_W :: new (self) } # [doc = "Bit 2 - Generate STOP"]
# [inline (always)]
# [must_use]
pub fn mctr_stop (& mut self) -> MCTR_STOP_W < MCTR_SPEC , 2 > { MCTR_STOP_W :: new (self) } # [doc = "Bit 3 - Data Acknowledge Enable. Software needs to configure this bit to send the ACK or NACK. See field decoding in Table: MCTR Field decoding."]
# [inline (always)]
# [must_use]
pub fn mctr_ack (& mut self) -> MCTR_ACK_W < MCTR_SPEC , 3 > { MCTR_ACK_W :: new (self) } # [doc = "Bit 4 - Master ACK overrride Enable"]
# [inline (always)]
# [must_use]
pub fn mctr_mackoen (& mut self) -> MCTR_MACKOEN_W < MCTR_SPEC , 4 > { MCTR_MACKOEN_W :: new (self) } # [doc = "Bit 5 - Read on TX Empty"]
# [inline (always)]
# [must_use]
pub fn mctr_rd_on_txempty (& mut self) -> MCTR_RD_ON_TXEMPTY_W < MCTR_SPEC , 5 > { MCTR_RD_ON_TXEMPTY_W :: new (self) } # [doc = "Bits 16:27 - I2C transaction length This field contains the programmed length of bytes of the Transaction."]
# [inline (always)]
# [must_use]
pub fn mctr_mblen (& mut self) -> MCTR_MBLEN_W < MCTR_SPEC , 16 > { MCTR_MBLEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MCTR_SPEC ; impl crate :: RegisterSpec for MCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mctr::R`](R) reader structure"]
impl crate :: Readable for MCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mctr::W`](W) writer structure"]
impl crate :: Writable for MCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCTR to value 0"]
impl crate :: Resettable for MCTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MSR (r) register accessor: I2C Master Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`]
module"]
pub type MSR = crate :: Reg < msr :: MSR_SPEC > ; # [doc = "I2C Master Status Register"]
pub mod msr { # [doc = "Register `MSR` reader"]
pub type R = crate :: R < MSR_SPEC > ; # [doc = "Field `MSR_BUSY` reader - I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction."]
pub type MSR_BUSY_R = crate :: BitReader < MSR_BUSY_A > ; # [doc = "I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_BUSY_A { # [doc = "0: CLEARED"]
MSR_BUSY_CLEARED = 0 , # [doc = "1: SET"]
MSR_BUSY_SET = 1 , } impl From < MSR_BUSY_A > for bool { # [inline (always)]
fn from (variant : MSR_BUSY_A) -> Self { variant as u8 != 0 } } impl MSR_BUSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_BUSY_A { match self . bits { false => MSR_BUSY_A :: MSR_BUSY_CLEARED , true => MSR_BUSY_A :: MSR_BUSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_busy_cleared (& self) -> bool { * self == MSR_BUSY_A :: MSR_BUSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_busy_set (& self) -> bool { * self == MSR_BUSY_A :: MSR_BUSY_SET } } # [doc = "Field `MSR_ERR` reader - Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged."]
pub type MSR_ERR_R = crate :: BitReader < MSR_ERR_A > ; # [doc = "Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_ERR_A { # [doc = "0: CLEARED"]
MSR_ERR_CLEARED = 0 , # [doc = "1: SET"]
MSR_ERR_SET = 1 , } impl From < MSR_ERR_A > for bool { # [inline (always)]
fn from (variant : MSR_ERR_A) -> Self { variant as u8 != 0 } } impl MSR_ERR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_ERR_A { match self . bits { false => MSR_ERR_A :: MSR_ERR_CLEARED , true => MSR_ERR_A :: MSR_ERR_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_err_cleared (& self) -> bool { * self == MSR_ERR_A :: MSR_ERR_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_err_set (& self) -> bool { * self == MSR_ERR_A :: MSR_ERR_SET } } # [doc = "Field `MSR_ADRACK` reader - Acknowledge Address"]
pub type MSR_ADRACK_R = crate :: BitReader < MSR_ADRACK_A > ; # [doc = "Acknowledge Address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_ADRACK_A { # [doc = "0: CLEARED"]
MSR_ADRACK_CLEARED = 0 , # [doc = "1: SET"]
MSR_ADRACK_SET = 1 , } impl From < MSR_ADRACK_A > for bool { # [inline (always)]
fn from (variant : MSR_ADRACK_A) -> Self { variant as u8 != 0 } } impl MSR_ADRACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_ADRACK_A { match self . bits { false => MSR_ADRACK_A :: MSR_ADRACK_CLEARED , true => MSR_ADRACK_A :: MSR_ADRACK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_adrack_cleared (& self) -> bool { * self == MSR_ADRACK_A :: MSR_ADRACK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_adrack_set (& self) -> bool { * self == MSR_ADRACK_A :: MSR_ADRACK_SET } } # [doc = "Field `MSR_DATACK` reader - Acknowledge Data"]
pub type MSR_DATACK_R = crate :: BitReader < MSR_DATACK_A > ; # [doc = "Acknowledge Data\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_DATACK_A { # [doc = "0: CLEARED"]
MSR_DATACK_CLEARED = 0 , # [doc = "1: SET"]
MSR_DATACK_SET = 1 , } impl From < MSR_DATACK_A > for bool { # [inline (always)]
fn from (variant : MSR_DATACK_A) -> Self { variant as u8 != 0 } } impl MSR_DATACK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_DATACK_A { match self . bits { false => MSR_DATACK_A :: MSR_DATACK_CLEARED , true => MSR_DATACK_A :: MSR_DATACK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_datack_cleared (& self) -> bool { * self == MSR_DATACK_A :: MSR_DATACK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_datack_set (& self) -> bool { * self == MSR_DATACK_A :: MSR_DATACK_SET } } # [doc = "Field `MSR_ARBLST` reader - Arbitration Lost"]
pub type MSR_ARBLST_R = crate :: BitReader < MSR_ARBLST_A > ; # [doc = "Arbitration Lost\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_ARBLST_A { # [doc = "0: CLEARED"]
MSR_ARBLST_CLEARED = 0 , # [doc = "1: SET"]
MSR_ARBLST_SET = 1 , } impl From < MSR_ARBLST_A > for bool { # [inline (always)]
fn from (variant : MSR_ARBLST_A) -> Self { variant as u8 != 0 } } impl MSR_ARBLST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_ARBLST_A { match self . bits { false => MSR_ARBLST_A :: MSR_ARBLST_CLEARED , true => MSR_ARBLST_A :: MSR_ARBLST_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_arblst_cleared (& self) -> bool { * self == MSR_ARBLST_A :: MSR_ARBLST_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_arblst_set (& self) -> bool { * self == MSR_ARBLST_A :: MSR_ARBLST_SET } } # [doc = "Field `MSR_IDLE` reader - I2C Idle"]
pub type MSR_IDLE_R = crate :: BitReader < MSR_IDLE_A > ; # [doc = "I2C Idle\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_IDLE_A { # [doc = "0: CLEARED"]
MSR_IDLE_CLEARED = 0 , # [doc = "1: SET"]
MSR_IDLE_SET = 1 , } impl From < MSR_IDLE_A > for bool { # [inline (always)]
fn from (variant : MSR_IDLE_A) -> Self { variant as u8 != 0 } } impl MSR_IDLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_IDLE_A { match self . bits { false => MSR_IDLE_A :: MSR_IDLE_CLEARED , true => MSR_IDLE_A :: MSR_IDLE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_idle_cleared (& self) -> bool { * self == MSR_IDLE_A :: MSR_IDLE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_idle_set (& self) -> bool { * self == MSR_IDLE_A :: MSR_IDLE_SET } } # [doc = "Field `MSR_BUSBSY` reader - I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY."]
pub type MSR_BUSBSY_R = crate :: BitReader < MSR_BUSBSY_A > ; # [doc = "I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MSR_BUSBSY_A { # [doc = "0: CLEARED"]
MSR_BUSBSY_CLEARED = 0 , # [doc = "1: SET"]
MSR_BUSBSY_SET = 1 , } impl From < MSR_BUSBSY_A > for bool { # [inline (always)]
fn from (variant : MSR_BUSBSY_A) -> Self { variant as u8 != 0 } } impl MSR_BUSBSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MSR_BUSBSY_A { match self . bits { false => MSR_BUSBSY_A :: MSR_BUSBSY_CLEARED , true => MSR_BUSBSY_A :: MSR_BUSBSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_msr_busbsy_cleared (& self) -> bool { * self == MSR_BUSBSY_A :: MSR_BUSBSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_msr_busbsy_set (& self) -> bool { * self == MSR_BUSBSY_A :: MSR_BUSBSY_SET } } # [doc = "Field `MSR_MBCNT` reader - I2C Master Transaction Count This field contains the current count-down value of the transaction."]
pub type MSR_MBCNT_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bit 0 - I2C Master FSM Busy The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in MBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction."]
# [inline (always)]
pub fn msr_busy (& self) -> MSR_BUSY_R { MSR_BUSY_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Error The error can be from the slave address not being acknowledged or the transmit data not being acknowledged."]
# [inline (always)]
pub fn msr_err (& self) -> MSR_ERR_R { MSR_ERR_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Acknowledge Address"]
# [inline (always)]
pub fn msr_adrack (& self) -> MSR_ADRACK_R { MSR_ADRACK_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Acknowledge Data"]
# [inline (always)]
pub fn msr_datack (& self) -> MSR_DATACK_R { MSR_DATACK_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Arbitration Lost"]
# [inline (always)]
pub fn msr_arblst (& self) -> MSR_ARBLST_R { MSR_ARBLST_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - I2C Idle"]
# [inline (always)]
pub fn msr_idle (& self) -> MSR_IDLE_R { MSR_IDLE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - I2C Bus is Busy Master State Machine will wait until this bit is cleared before starting a transaction. When first enabling the Master in multi master environments, FW should wait for one I2C clock period after setting ACTIVE high before writing to the MTCR register to start the transaction so that if SCL goes low it will trigger the BUSBSY."]
# [inline (always)]
pub fn msr_busbsy (& self) -> MSR_BUSBSY_R { MSR_BUSBSY_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bits 16:27 - I2C Master Transaction Count This field contains the current count-down value of the transaction."]
# [inline (always)]
pub fn msr_mbcnt (& self) -> MSR_MBCNT_R { MSR_MBCNT_R :: new (((self . bits >> 16) & 0x0fff) as u16) } } # [doc = "I2C Master Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`msr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MSR_SPEC ; impl crate :: RegisterSpec for MSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`msr::R`](R) reader structure"]
impl crate :: Readable for MSR_SPEC { } # [doc = "`reset()` method sets MSR to value 0"]
impl crate :: Resettable for MSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MRXDATA (r) register accessor: I2C Master RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mrxdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mrxdata`]
module"]
pub type MRXDATA = crate :: Reg < mrxdata :: MRXDATA_SPEC > ; # [doc = "I2C Master RXData"]
pub mod mrxdata { # [doc = "Register `MRXDATA` reader"]
pub type R = crate :: R < MRXDATA_SPEC > ; # [doc = "Field `MRXDATA_VALUE` reader - Received Data. This field contains the last received data."]
pub type MRXDATA_VALUE_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Received Data. This field contains the last received data."]
# [inline (always)]
pub fn mrxdata_value (& self) -> MRXDATA_VALUE_R { MRXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } # [doc = "I2C Master RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mrxdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MRXDATA_SPEC ; impl crate :: RegisterSpec for MRXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mrxdata::R`](R) reader structure"]
impl crate :: Readable for MRXDATA_SPEC { } # [doc = "`reset()` method sets MRXDATA to value 0"]
impl crate :: Resettable for MRXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MTXDATA (rw) register accessor: I2C Master TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtxdata::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtxdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtxdata`]
module"]
pub type MTXDATA = crate :: Reg < mtxdata :: MTXDATA_SPEC > ; # [doc = "I2C Master TXData"]
pub mod mtxdata { # [doc = "Register `MTXDATA` reader"]
pub type R = crate :: R < MTXDATA_SPEC > ; # [doc = "Register `MTXDATA` writer"]
pub type W = crate :: W < MTXDATA_SPEC > ; # [doc = "Field `MTXDATA_VALUE` reader - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type MTXDATA_VALUE_R = crate :: FieldReader ; # [doc = "Field `MTXDATA_VALUE` writer - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type MTXDATA_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
pub fn mtxdata_value (& self) -> MTXDATA_VALUE_R { MTXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
# [must_use]
pub fn mtxdata_value (& mut self) -> MTXDATA_VALUE_W < MTXDATA_SPEC , 0 > { MTXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtxdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtxdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MTXDATA_SPEC ; impl crate :: RegisterSpec for MTXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mtxdata::R`](R) reader structure"]
impl crate :: Readable for MTXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`mtxdata::W`](W) writer structure"]
impl crate :: Writable for MTXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MTXDATA to value 0"]
impl crate :: Resettable for MTXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MTPR (rw) register accessor: I2C Master Timer Period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtpr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtpr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mtpr`]
module"]
pub type MTPR = crate :: Reg < mtpr :: MTPR_SPEC > ; # [doc = "I2C Master Timer Period"]
pub mod mtpr { # [doc = "Register `MTPR` reader"]
pub type R = crate :: R < MTPR_SPEC > ; # [doc = "Register `MTPR` writer"]
pub type W = crate :: W < MTPR_SPEC > ; # [doc = "Field `MTPR_TPR` reader - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
pub type MTPR_TPR_R = crate :: FieldReader ; # [doc = "Field `MTPR_TPR` writer - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
pub type MTPR_TPR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
# [inline (always)]
pub fn mtpr_tpr (& self) -> MTPR_TPR_R { MTPR_TPR_R :: new ((self . bits & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - Timer Period This field is used in the equation to configure SCL_PERIOD : SCL_PERIOD = (1 + TPR ) * (SCL_LP + SCL_HP ) * INT_CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 127). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). CLK_PRD is the functional clock period in ns."]
# [inline (always)]
# [must_use]
pub fn mtpr_tpr (& mut self) -> MTPR_TPR_W < MTPR_SPEC , 0 > { MTPR_TPR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Timer Period\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mtpr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mtpr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MTPR_SPEC ; impl crate :: RegisterSpec for MTPR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mtpr::R`](R) reader structure"]
impl crate :: Readable for MTPR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mtpr::W`](W) writer structure"]
impl crate :: Writable for MTPR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MTPR to value 0x01"]
impl crate :: Resettable for MTPR_SPEC { const RESET_VALUE : Self :: Ux = 0x01 ; } } # [doc = "MCR (rw) register accessor: I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
module"]
pub type MCR = crate :: Reg < mcr :: MCR_SPEC > ; # [doc = "I2C Master Configuration"]
pub mod mcr { # [doc = "Register `MCR` reader"]
pub type R = crate :: R < MCR_SPEC > ; # [doc = "Register `MCR` writer"]
pub type W = crate :: W < MCR_SPEC > ; # [doc = "Field `MCR_ACTIVE` reader - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
pub type MCR_ACTIVE_R = crate :: BitReader < MCR_ACTIVE_A > ; # [doc = "Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_ACTIVE_A { # [doc = "0: DISABLE"]
MCR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_ACTIVE_ENABLE = 1 , } impl From < MCR_ACTIVE_A > for bool { # [inline (always)]
fn from (variant : MCR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl MCR_ACTIVE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_ACTIVE_A { match self . bits { false => MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE , true => MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_active_disable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_active_enable (& self) -> bool { * self == MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE } } # [doc = "Field `MCR_ACTIVE` writer - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
pub type MCR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > MCR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_ACTIVE_A :: MCR_ACTIVE_ENABLE) } } # [doc = "Field `MCR_MMST` reader - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
pub type MCR_MMST_R = crate :: BitReader < MCR_MMST_A > ; # [doc = "Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_MMST_A { # [doc = "0: DISABLE"]
MCR_MMST_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_MMST_ENABLE = 1 , } impl From < MCR_MMST_A > for bool { # [inline (always)]
fn from (variant : MCR_MMST_A) -> Self { variant as u8 != 0 } } impl MCR_MMST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_MMST_A { match self . bits { false => MCR_MMST_A :: MCR_MMST_DISABLE , true => MCR_MMST_A :: MCR_MMST_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_mmst_disable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_mmst_enable (& self) -> bool { * self == MCR_MMST_A :: MCR_MMST_ENABLE } } # [doc = "Field `MCR_MMST` writer - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
pub type MCR_MMST_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_MMST_A > ; impl < 'a , REG , const O : u8 > MCR_MMST_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_mmst_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_mmst_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_MMST_A :: MCR_MMST_ENABLE) } } # [doc = "Field `MCR_CLKSTRETCH` reader - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
pub type MCR_CLKSTRETCH_R = crate :: BitReader < MCR_CLKSTRETCH_A > ; # [doc = "Clock Stretching. This bit controls the support for clock stretching of the I2C bus.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_CLKSTRETCH_A { # [doc = "0: DISABLE"]
MCR_CLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_CLKSTRETCH_ENABLE = 1 , } impl From < MCR_CLKSTRETCH_A > for bool { # [inline (always)]
fn from (variant : MCR_CLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl MCR_CLKSTRETCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_CLKSTRETCH_A { match self . bits { false => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE , true => MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_clkstretch_disable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_clkstretch_enable (& self) -> bool { * self == MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE } } # [doc = "Field `MCR_CLKSTRETCH` writer - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
pub type MCR_CLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_CLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > MCR_CLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_clkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_clkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_CLKSTRETCH_A :: MCR_CLKSTRETCH_ENABLE) } } # [doc = "Field `MCR_LPBK` reader - I2C Loopback"]
pub type MCR_LPBK_R = crate :: BitReader < MCR_LPBK_A > ; # [doc = "I2C Loopback\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MCR_LPBK_A { # [doc = "0: DISABLE"]
MCR_LPBK_DISABLE = 0 , # [doc = "1: ENABLE"]
MCR_LPBK_ENABLE = 1 , } impl From < MCR_LPBK_A > for bool { # [inline (always)]
fn from (variant : MCR_LPBK_A) -> Self { variant as u8 != 0 } } impl MCR_LPBK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MCR_LPBK_A { match self . bits { false => MCR_LPBK_A :: MCR_LPBK_DISABLE , true => MCR_LPBK_A :: MCR_LPBK_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_mcr_lpbk_disable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_mcr_lpbk_enable (& self) -> bool { * self == MCR_LPBK_A :: MCR_LPBK_ENABLE } } # [doc = "Field `MCR_LPBK` writer - I2C Loopback"]
pub type MCR_LPBK_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MCR_LPBK_A > ; impl < 'a , REG , const O : u8 > MCR_LPBK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn mcr_lpbk_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn mcr_lpbk_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MCR_LPBK_A :: MCR_LPBK_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
# [inline (always)]
pub fn mcr_active (& self) -> MCR_ACTIVE_R { MCR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
# [inline (always)]
pub fn mcr_mmst (& self) -> MCR_MMST_R { MCR_MMST_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
# [inline (always)]
pub fn mcr_clkstretch (& self) -> MCR_CLKSTRETCH_R { MCR_CLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 8 - I2C Loopback"]
# [inline (always)]
pub fn mcr_lpbk (& self) -> MCR_LPBK_R { MCR_LPBK_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active After this bit has been set, it should not be set again unless it has been cleared by writing a 0 or by a reset, otherwise transfer failures may occur."]
# [inline (always)]
# [must_use]
pub fn mcr_active (& mut self) -> MCR_ACTIVE_W < MCR_SPEC , 0 > { MCR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - Multimaster mode. In Multimaster mode the SCL high time counts once the SCL line has been detected high. If this is not enabled the high time counts as soon as the SCL line has been set high by the I2C controller."]
# [inline (always)]
# [must_use]
pub fn mcr_mmst (& mut self) -> MCR_MMST_W < MCR_SPEC , 1 > { MCR_MMST_W :: new (self) } # [doc = "Bit 2 - Clock Stretching. This bit controls the support for clock stretching of the I2C bus."]
# [inline (always)]
# [must_use]
pub fn mcr_clkstretch (& mut self) -> MCR_CLKSTRETCH_W < MCR_SPEC , 2 > { MCR_CLKSTRETCH_W :: new (self) } # [doc = "Bit 8 - I2C Loopback"]
# [inline (always)]
# [must_use]
pub fn mcr_lpbk (& mut self) -> MCR_LPBK_W < MCR_SPEC , 8 > { MCR_LPBK_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mcr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mcr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MCR_SPEC ; impl crate :: RegisterSpec for MCR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mcr::R`](R) reader structure"]
impl crate :: Readable for MCR_SPEC { } # [doc = "`write(|w| ..)` method takes [`mcr::W`](W) writer structure"]
impl crate :: Writable for MCR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MCR to value 0"]
impl crate :: Resettable for MCR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MBMON (r) register accessor: I2C Master Bus Monitor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mbmon::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mbmon`]
module"]
pub type MBMON = crate :: Reg < mbmon :: MBMON_SPEC > ; # [doc = "I2C Master Bus Monitor"]
pub mod mbmon { # [doc = "Register `MBMON` reader"]
pub type R = crate :: R < MBMON_SPEC > ; # [doc = "Field `MBMON_SCL` reader - I2C SCL Status"]
pub type MBMON_SCL_R = crate :: BitReader < MBMON_SCL_A > ; # [doc = "I2C SCL Status\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MBMON_SCL_A { # [doc = "0: CLEARED"]
MBMON_SCL_CLEARED = 0 , # [doc = "1: SET"]
MBMON_SCL_SET = 1 , } impl From < MBMON_SCL_A > for bool { # [inline (always)]
fn from (variant : MBMON_SCL_A) -> Self { variant as u8 != 0 } } impl MBMON_SCL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MBMON_SCL_A { match self . bits { false => MBMON_SCL_A :: MBMON_SCL_CLEARED , true => MBMON_SCL_A :: MBMON_SCL_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_mbmon_scl_cleared (& self) -> bool { * self == MBMON_SCL_A :: MBMON_SCL_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_mbmon_scl_set (& self) -> bool { * self == MBMON_SCL_A :: MBMON_SCL_SET } } # [doc = "Field `MBMON_SDA` reader - I2C SDA Status"]
pub type MBMON_SDA_R = crate :: BitReader < MBMON_SDA_A > ; # [doc = "I2C SDA Status\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MBMON_SDA_A { # [doc = "0: CLEARED"]
MBMON_SDA_CLEARED = 0 , # [doc = "1: SET"]
MBMON_SDA_SET = 1 , } impl From < MBMON_SDA_A > for bool { # [inline (always)]
fn from (variant : MBMON_SDA_A) -> Self { variant as u8 != 0 } } impl MBMON_SDA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MBMON_SDA_A { match self . bits { false => MBMON_SDA_A :: MBMON_SDA_CLEARED , true => MBMON_SDA_A :: MBMON_SDA_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_mbmon_sda_cleared (& self) -> bool { * self == MBMON_SDA_A :: MBMON_SDA_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_mbmon_sda_set (& self) -> bool { * self == MBMON_SDA_A :: MBMON_SDA_SET } } impl R { # [doc = "Bit 0 - I2C SCL Status"]
# [inline (always)]
pub fn mbmon_scl (& self) -> MBMON_SCL_R { MBMON_SCL_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C SDA Status"]
# [inline (always)]
pub fn mbmon_sda (& self) -> MBMON_SDA_R { MBMON_SDA_R :: new (((self . bits >> 1) & 1) != 0) } } # [doc = "I2C Master Bus Monitor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mbmon::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MBMON_SPEC ; impl crate :: RegisterSpec for MBMON_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mbmon::R`](R) reader structure"]
impl crate :: Readable for MBMON_SPEC { } # [doc = "`reset()` method sets MBMON to value 0x03"]
impl crate :: Resettable for MBMON_SPEC { const RESET_VALUE : Self :: Ux = 0x03 ; } } # [doc = "MFIFOCTL (rw) register accessor: I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfifoctl`]
module"]
pub type MFIFOCTL = crate :: Reg < mfifoctl :: MFIFOCTL_SPEC > ; # [doc = "I2C Master FIFO Control"]
pub mod mfifoctl { # [doc = "Register `MFIFOCTL` reader"]
pub type R = crate :: R < MFIFOCTL_SPEC > ; # [doc = "Register `MFIFOCTL` writer"]
pub type W = crate :: W < MFIFOCTL_SPEC > ; # [doc = "Field `MFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type MFIFOCTL_TXTRIG_R = crate :: FieldReader < MFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum MFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"]
MFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"]
MFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"]
MFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"]
MFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < MFIFOCTL_TXTRIG_A > for u8 { # [inline (always)]
fn from (variant : MFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < MFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_4 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_5 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_6 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_mfifoctl_txtrig_level_7 (& self) -> bool { * self == MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `MFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type MFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn mfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXTRIG_A :: MFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `MFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type MFIFOCTL_TXFLUSH_R = crate :: BitReader < MFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"]
MFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
MFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOCTL_TXFLUSH_A { match self . bits { false => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH , true => MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_mfifoctl_txflush_noflush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_mfifoctl_txflush_flush (& self) -> bool { * self == MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type MFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn mfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn mfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_TXFLUSH_A :: MFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `MFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type MFIFOCTL_RXTRIG_R = crate :: FieldReader < MFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum MFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"]
MFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"]
MFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"]
MFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"]
MFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < MFIFOCTL_RXTRIG_A > for u8 { # [inline (always)]
fn from (variant : MFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for MFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl MFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < MFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_5 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_6 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_7 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn is_mfifoctl_rxtrig_level_8 (& self) -> bool { * self == MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `MFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type MFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , MFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn mfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXTRIG_A :: MFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `MFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type MFIFOCTL_RXFLUSH_R = crate :: BitReader < MFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"]
MFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
MFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < MFIFOCTL_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOCTL_RXFLUSH_A { match self . bits { false => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH , true => MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_mfifoctl_rxflush_noflush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_mfifoctl_rxflush_flush (& self) -> bool { * self == MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `MFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type MFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > MFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn mfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn mfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (MFIFOCTL_RXFLUSH_A :: MFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
pub fn mfifoctl_txtrig (& self) -> MFIFOCTL_TXTRIG_R { MFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
pub fn mfifoctl_txflush (& self) -> MFIFOCTL_TXFLUSH_R { MFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
pub fn mfifoctl_rxtrig (& self) -> MFIFOCTL_RXTRIG_R { MFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
pub fn mfifoctl_rxflush (& self) -> MFIFOCTL_RXFLUSH_R { MFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_txtrig (& mut self) -> MFIFOCTL_TXTRIG_W < MFIFOCTL_SPEC , 0 > { MFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_txflush (& mut self) -> MFIFOCTL_TXFLUSH_W < MFIFOCTL_SPEC , 7 > { MFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_rxtrig (& mut self) -> MFIFOCTL_RXTRIG_W < MFIFOCTL_SPEC , 8 > { MFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn mfifoctl_rxflush (& mut self) -> MFIFOCTL_RXFLUSH_W < MFIFOCTL_SPEC , 15 > { MFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Master FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifoctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MFIFOCTL_SPEC ; impl crate :: RegisterSpec for MFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifoctl::R`](R) reader structure"]
impl crate :: Readable for MFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`mfifoctl::W`](W) writer structure"]
impl crate :: Writable for MFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MFIFOCTL to value 0"]
impl crate :: Resettable for MFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MFIFOSR (r) register accessor: I2C Master FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifosr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mfifosr`]
module"]
pub type MFIFOSR = crate :: Reg < mfifosr :: MFIFOSR_SPEC > ; # [doc = "I2C Master FIFO Status Register"]
pub mod mfifosr { # [doc = "Register `MFIFOSR` reader"]
pub type R = crate :: R < MFIFOSR_SPEC > ; # [doc = "Field `MFIFOSR_RXFIFOCNT` reader - Number of Bytes which could be read from the RX FIFO"]
pub type MFIFOSR_RXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `MFIFOSR_RXFLUSH` reader - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
pub type MFIFOSR_RXFLUSH_R = crate :: BitReader < MFIFOSR_RXFLUSH_A > ; # [doc = "RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOSR_RXFLUSH_A { # [doc = "0: INACTIVE"]
MFIFOSR_RXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
MFIFOSR_RXFLUSH_ACTIVE = 1 , } impl From < MFIFOSR_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOSR_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOSR_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOSR_RXFLUSH_A { match self . bits { false => MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_INACTIVE , true => MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_mfifosr_rxflush_inactive (& self) -> bool { * self == MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_mfifosr_rxflush_active (& self) -> bool { * self == MFIFOSR_RXFLUSH_A :: MFIFOSR_RXFLUSH_ACTIVE } } # [doc = "Field `MFIFOSR_TXFIFOCNT` reader - Number of Bytes which could be put into the TX FIFO"]
pub type MFIFOSR_TXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `MFIFOSR_TXFLUSH` reader - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
pub type MFIFOSR_TXFLUSH_R = crate :: BitReader < MFIFOSR_TXFLUSH_A > ; # [doc = "TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MFIFOSR_TXFLUSH_A { # [doc = "0: INACTIVE"]
MFIFOSR_TXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
MFIFOSR_TXFLUSH_ACTIVE = 1 , } impl From < MFIFOSR_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : MFIFOSR_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl MFIFOSR_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MFIFOSR_TXFLUSH_A { match self . bits { false => MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_INACTIVE , true => MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_mfifosr_txflush_inactive (& self) -> bool { * self == MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_mfifosr_txflush_active (& self) -> bool { * self == MFIFOSR_TXFLUSH_A :: MFIFOSR_TXFLUSH_ACTIVE } } impl R { # [doc = "Bits 0:3 - Number of Bytes which could be read from the RX FIFO"]
# [inline (always)]
pub fn mfifosr_rxfifocnt (& self) -> MFIFOSR_RXFIFOCNT_R { MFIFOSR_RXFIFOCNT_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn mfifosr_rxflush (& self) -> MFIFOSR_RXFLUSH_R { MFIFOSR_RXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:11 - Number of Bytes which could be put into the TX FIFO"]
# [inline (always)]
pub fn mfifosr_txfifocnt (& self) -> MFIFOSR_TXFIFOCNT_R { MFIFOSR_TXFIFOCNT_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 15 - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn mfifosr_txflush (& self) -> MFIFOSR_TXFLUSH_R { MFIFOSR_TXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "I2C Master FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mfifosr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MFIFOSR_SPEC ; impl crate :: RegisterSpec for MFIFOSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mfifosr::R`](R) reader structure"]
impl crate :: Readable for MFIFOSR_SPEC { } # [doc = "`reset()` method sets MFIFOSR to value 0x0800"]
impl crate :: Resettable for MFIFOSR_SPEC { const RESET_VALUE : Self :: Ux = 0x0800 ; } } # [doc = "MASTER_I2CPECCTL (rw) register accessor: I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@master_i2cpecctl`]
module"]
pub type MASTER_I2CPECCTL = crate :: Reg < master_i2cpecctl :: MASTER_I2CPECCTL_SPEC > ; # [doc = "I2C master PEC control register"]
pub mod master_i2cpecctl { # [doc = "Register `MASTER_I2CPECCTL` reader"]
pub type R = crate :: R < MASTER_I2CPECCTL_SPEC > ; # [doc = "Register `MASTER_I2CPECCTL` writer"]
pub type W = crate :: W < MASTER_I2CPECCTL_SPEC > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` reader - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
pub type MASTER_I2CPECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECCNT` writer - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
pub type MASTER_I2CPECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `MASTER_I2CPECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type MASTER_I2CPECCTL_PECEN_R = crate :: BitReader < MASTER_I2CPECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MASTER_I2CPECCTL_PECEN_A { # [doc = "0: DISABLE"]
MASTER_I2CPECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"]
MASTER_I2CPECCTL_PECEN_ENABLE = 1 , } impl From < MASTER_I2CPECCTL_PECEN_A > for bool { # [inline (always)]
fn from (variant : MASTER_I2CPECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl MASTER_I2CPECCTL_PECEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MASTER_I2CPECCTL_PECEN_A { match self . bits { false => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE , true => MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_master_i2cpecctl_pecen_disable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_master_i2cpecctl_pecen_enable (& self) -> bool { * self == MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE } } # [doc = "Field `MASTER_I2CPECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type MASTER_I2CPECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MASTER_I2CPECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > MASTER_I2CPECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn master_i2cpecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn master_i2cpecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MASTER_I2CPECCTL_PECEN_A :: MASTER_I2CPECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
# [inline (always)]
pub fn master_i2cpecctl_peccnt (& self) -> MASTER_I2CPECCTL_PECCNT_R { MASTER_I2CPECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
pub fn master_i2cpecctl_pecen (& self) -> MASTER_I2CPECCTL_PECEN_R { MASTER_I2CPECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - PEC Count When this field is non zero, the number of I2C bytes are counted (Note that although the PEC is calculated on the I2C address it is not counted at a byte). When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Master use case, FW would set PECEN=1 and PECCNT=SMB packet length (Not including Slave Address byte, but including the PEC byte). FW would then configure DMA to allow the packet to complete unassisted and write MCTR to initiate the transaction. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction. Note that any write to the MASTER_I2CPECCTL Register will clear the current PEC Byte Count in the Master State Machine."]
# [inline (always)]
# [must_use]
pub fn master_i2cpecctl_peccnt (& mut self) -> MASTER_I2CPECCTL_PECCNT_W < MASTER_I2CPECCTL_SPEC , 0 > { MASTER_I2CPECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
# [must_use]
pub fn master_i2cpecctl_pecen (& mut self) -> MASTER_I2CPECCTL_PECEN_W < MASTER_I2CPECCTL_SPEC , 12 > { MASTER_I2CPECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C master PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_i2cpecctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`master_i2cpecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MASTER_I2CPECCTL_SPEC ; impl crate :: RegisterSpec for MASTER_I2CPECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_i2cpecctl::R`](R) reader structure"]
impl crate :: Readable for MASTER_I2CPECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`master_i2cpecctl::W`](W) writer structure"]
impl crate :: Writable for MASTER_I2CPECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MASTER_I2CPECCTL to value 0"]
impl crate :: Resettable for MASTER_I2CPECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MASTER_PECSR (r) register accessor: I2C master PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_pecsr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@master_pecsr`]
module"]
pub type MASTER_PECSR = crate :: Reg < master_pecsr :: MASTER_PECSR_SPEC > ; # [doc = "I2C master PEC status register"]
pub mod master_pecsr { # [doc = "Register `MASTER_PECSR` reader"]
pub type R = crate :: R < MASTER_PECSR_SPEC > ; # [doc = "Field `MASTER_PECSR_PECBYTECNT` reader - PEC Byte Count This is the current PEC Byte Count of the Master State Machine."]
pub type MASTER_PECSR_PECBYTECNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `MASTER_PECSR_PECSTS_CHECK` reader - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
pub type MASTER_PECSR_PECSTS_CHECK_R = crate :: BitReader < MASTER_PECSR_PECSTS_CHECK_A > ; # [doc = "This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MASTER_PECSR_PECSTS_CHECK_A { # [doc = "0: CLEARED"]
MASTER_PECSR_PECSTS_CHECK_CLEARED = 0 , # [doc = "1: SET"]
MASTER_PECSR_PECSTS_CHECK_SET = 1 , } impl From < MASTER_PECSR_PECSTS_CHECK_A > for bool { # [inline (always)]
fn from (variant : MASTER_PECSR_PECSTS_CHECK_A) -> Self { variant as u8 != 0 } } impl MASTER_PECSR_PECSTS_CHECK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MASTER_PECSR_PECSTS_CHECK_A { match self . bits { false => MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_CLEARED , true => MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_check_cleared (& self) -> bool { * self == MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_check_set (& self) -> bool { * self == MASTER_PECSR_PECSTS_CHECK_A :: MASTER_PECSR_PECSTS_CHECK_SET } } # [doc = "Field `MASTER_PECSR_PECSTS_ERROR` reader - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
pub type MASTER_PECSR_PECSTS_ERROR_R = crate :: BitReader < MASTER_PECSR_PECSTS_ERROR_A > ; # [doc = "This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MASTER_PECSR_PECSTS_ERROR_A { # [doc = "0: CLEARED"]
MASTER_PECSR_PECSTS_ERROR_CLEARED = 0 , # [doc = "1: SET"]
MASTER_PECSR_PECSTS_ERROR_SET = 1 , } impl From < MASTER_PECSR_PECSTS_ERROR_A > for bool { # [inline (always)]
fn from (variant : MASTER_PECSR_PECSTS_ERROR_A) -> Self { variant as u8 != 0 } } impl MASTER_PECSR_PECSTS_ERROR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MASTER_PECSR_PECSTS_ERROR_A { match self . bits { false => MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_CLEARED , true => MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_error_cleared (& self) -> bool { * self == MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_master_pecsr_pecsts_error_set (& self) -> bool { * self == MASTER_PECSR_PECSTS_ERROR_A :: MASTER_PECSR_PECSTS_ERROR_SET } } impl R { # [doc = "Bits 0:8 - PEC Byte Count This is the current PEC Byte Count of the Master State Machine."]
# [inline (always)]
pub fn master_pecsr_pecbytecnt (& self) -> MASTER_PECSR_PECBYTECNT_R { MASTER_PECSR_PECBYTECNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 16 - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn master_pecsr_pecsts_check (& self) -> MASTER_PECSR_PECSTS_CHECK_R { MASTER_PECSR_PECSTS_CHECK_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn master_pecsr_pecsts_error (& self) -> MASTER_PECSR_PECSTS_ERROR_R { MASTER_PECSR_PECSTS_ERROR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "I2C master PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`master_pecsr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MASTER_PECSR_SPEC ; impl crate :: RegisterSpec for MASTER_PECSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`master_pecsr::R`](R) reader structure"]
impl crate :: Readable for MASTER_PECSR_SPEC { } # [doc = "`reset()` method sets MASTER_PECSR to value 0"]
impl crate :: Resettable for MASTER_PECSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SOAR (rw) register accessor: I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soar`]
module"]
pub type SOAR = crate :: Reg < soar :: SOAR_SPEC > ; # [doc = "I2C Slave Own Address"]
pub mod soar { # [doc = "Register `SOAR` reader"]
pub type R = crate :: R < SOAR_SPEC > ; # [doc = "Register `SOAR` writer"]
pub type W = crate :: W < SOAR_SPEC > ; # [doc = "Field `SOAR_OAR` reader - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
pub type SOAR_OAR_R = crate :: FieldReader < u16 > ; # [doc = "Field `SOAR_OAR` writer - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
pub type SOAR_OAR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; # [doc = "Field `SOAR_OAREN` reader - I2C Slave Own Address Enable"]
pub type SOAR_OAREN_R = crate :: BitReader < SOAR_OAREN_A > ; # [doc = "I2C Slave Own Address Enable\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SOAR_OAREN_A { # [doc = "0: DISABLE"]
SOAR_OAREN_DISABLE = 0 , # [doc = "1: ENABLE"]
SOAR_OAREN_ENABLE = 1 , } impl From < SOAR_OAREN_A > for bool { # [inline (always)]
fn from (variant : SOAR_OAREN_A) -> Self { variant as u8 != 0 } } impl SOAR_OAREN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SOAR_OAREN_A { match self . bits { false => SOAR_OAREN_A :: SOAR_OAREN_DISABLE , true => SOAR_OAREN_A :: SOAR_OAREN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_soar_oaren_disable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_soar_oaren_enable (& self) -> bool { * self == SOAR_OAREN_A :: SOAR_OAREN_ENABLE } } # [doc = "Field `SOAR_OAREN` writer - I2C Slave Own Address Enable"]
pub type SOAR_OAREN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_OAREN_A > ; impl < 'a , REG , const O : u8 > SOAR_OAREN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn soar_oaren_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn soar_oaren_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_OAREN_A :: SOAR_OAREN_ENABLE) } } # [doc = "Field `SOAR_SMODE` reader - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type SOAR_SMODE_R = crate :: BitReader < SOAR_SMODE_A > ; # [doc = "This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SOAR_SMODE_A { # [doc = "0: MODE7"]
SOAR_SMODE_MODE7 = 0 , # [doc = "1: MODE10"]
SOAR_SMODE_MODE10 = 1 , } impl From < SOAR_SMODE_A > for bool { # [inline (always)]
fn from (variant : SOAR_SMODE_A) -> Self { variant as u8 != 0 } } impl SOAR_SMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SOAR_SMODE_A { match self . bits { false => SOAR_SMODE_A :: SOAR_SMODE_MODE7 , true => SOAR_SMODE_A :: SOAR_SMODE_MODE10 , } } # [doc = "MODE7"]
# [inline (always)]
pub fn is_soar_smode_mode7 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE7 } # [doc = "MODE10"]
# [inline (always)]
pub fn is_soar_smode_mode10 (& self) -> bool { * self == SOAR_SMODE_A :: SOAR_SMODE_MODE10 } } # [doc = "Field `SOAR_SMODE` writer - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
pub type SOAR_SMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR_SMODE_A > ; impl < 'a , REG , const O : u8 > SOAR_SMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MODE7"]
# [inline (always)]
pub fn soar_smode_mode7 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE7) } # [doc = "MODE10"]
# [inline (always)]
pub fn soar_smode_mode10 (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR_SMODE_A :: SOAR_SMODE_MODE10) } } impl R { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
pub fn soar_oar (& self) -> SOAR_OAR_R { SOAR_OAR_R :: new ((self . bits & 0x03ff) as u16) } # [doc = "Bit 14 - I2C Slave Own Address Enable"]
# [inline (always)]
pub fn soar_oaren (& self) -> SOAR_OAREN_R { SOAR_OAREN_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
pub fn soar_smode (& self) -> SOAR_SMODE_R { SOAR_SMODE_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:9 - I2C Slave Own Address: This field specifies bits A9 through A0 of the slave address. In 7-bit addressing mode as selected by I2CSOAR.MODE bit, the top 3 bits are don't care"]
# [inline (always)]
# [must_use]
pub fn soar_oar (& mut self) -> SOAR_OAR_W < SOAR_SPEC , 0 > { SOAR_OAR_W :: new (self) } # [doc = "Bit 14 - I2C Slave Own Address Enable"]
# [inline (always)]
# [must_use]
pub fn soar_oaren (& mut self) -> SOAR_OAREN_W < SOAR_SPEC , 14 > { SOAR_OAREN_W :: new (self) } # [doc = "Bit 15 - This bit selects the adressing mode to be used in slave mode. When 0, 7-bit addressing is used. When 1, 10-bit addressing is used."]
# [inline (always)]
# [must_use]
pub fn soar_smode (& mut self) -> SOAR_SMODE_W < SOAR_SPEC , 15 > { SOAR_SMODE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOAR_SPEC ; impl crate :: RegisterSpec for SOAR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar::R`](R) reader structure"]
impl crate :: Readable for SOAR_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar::W`](W) writer structure"]
impl crate :: Writable for SOAR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR to value 0x4000"]
impl crate :: Resettable for SOAR_SPEC { const RESET_VALUE : Self :: Ux = 0x4000 ; } } # [doc = "SOAR2 (rw) register accessor: I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@soar2`]
module"]
pub type SOAR2 = crate :: Reg < soar2 :: SOAR2_SPEC > ; # [doc = "I2C Slave Own Address 2"]
pub mod soar2 { # [doc = "Register `SOAR2` reader"]
pub type R = crate :: R < SOAR2_SPEC > ; # [doc = "Register `SOAR2` writer"]
pub type W = crate :: W < SOAR2_SPEC > ; # [doc = "Field `SOAR2_OAR2` reader - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
pub type SOAR2_OAR2_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2` writer - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
pub type SOAR2_OAR2_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; # [doc = "Field `SOAR2_OAR2EN` reader - I2C Slave Own Address 2 Enable"]
pub type SOAR2_OAR2EN_R = crate :: BitReader < SOAR2_OAR2EN_A > ; # [doc = "I2C Slave Own Address 2 Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SOAR2_OAR2EN_A { # [doc = "0: DISABLE"]
SOAR2_OAR2EN_DISABLE = 0 , # [doc = "1: ENABLE"]
SOAR2_OAR2EN_ENABLE = 1 , } impl From < SOAR2_OAR2EN_A > for bool { # [inline (always)]
fn from (variant : SOAR2_OAR2EN_A) -> Self { variant as u8 != 0 } } impl SOAR2_OAR2EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SOAR2_OAR2EN_A { match self . bits { false => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE , true => SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_soar2_oar2en_disable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_soar2_oar2en_enable (& self) -> bool { * self == SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE } } # [doc = "Field `SOAR2_OAR2EN` writer - I2C Slave Own Address 2 Enable"]
pub type SOAR2_OAR2EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SOAR2_OAR2EN_A > ; impl < 'a , REG , const O : u8 > SOAR2_OAR2EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn soar2_oar2en_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn soar2_oar2en_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SOAR2_OAR2EN_A :: SOAR2_OAR2EN_ENABLE) } } # [doc = "Field `SOAR2_OAR2_MASK` reader - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
pub type SOAR2_OAR2_MASK_R = crate :: FieldReader ; # [doc = "Field `SOAR2_OAR2_MASK` writer - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
pub type SOAR2_OAR2_MASK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 7 , O > ; impl R { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
# [inline (always)]
pub fn soar2_oar2 (& self) -> SOAR2_OAR2_R { SOAR2_OAR2_R :: new ((self . bits & 0x7f) as u8) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"]
# [inline (always)]
pub fn soar2_oar2en (& self) -> SOAR2_OAR2EN_R { SOAR2_OAR2EN_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
# [inline (always)]
pub fn soar2_oar2_mask (& self) -> SOAR2_OAR2_MASK_R { SOAR2_OAR2_MASK_R :: new (((self . bits >> 16) & 0x7f) as u8) } } impl W { # [doc = "Bits 0:6 - I2C Slave Own Address 2 This field specifies the alternate OAR2 address."]
# [inline (always)]
# [must_use]
pub fn soar2_oar2 (& mut self) -> SOAR2_OAR2_W < SOAR2_SPEC , 0 > { SOAR2_OAR2_W :: new (self) } # [doc = "Bit 7 - I2C Slave Own Address 2 Enable"]
# [inline (always)]
# [must_use]
pub fn soar2_oar2en (& mut self) -> SOAR2_OAR2EN_W < SOAR2_SPEC , 7 > { SOAR2_OAR2EN_W :: new (self) } # [doc = "Bits 16:22 - I2C Slave Own Address 2 Mask: This field specifies bits A6 through A0 of the slave address. The bits with value 1 in SOAR2.OAR2_MASK field will make the corresponding incoming address bits to match by default regardless of the value inside SOAR2.OAR2 i.e. corresponding SOAR2.OAR2 bit is a dont care."]
# [inline (always)]
# [must_use]
pub fn soar2_oar2_mask (& mut self) -> SOAR2_OAR2_MASK_W < SOAR2_SPEC , 16 > { SOAR2_OAR2_MASK_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Own Address 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`soar2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`soar2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SOAR2_SPEC ; impl crate :: RegisterSpec for SOAR2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`soar2::R`](R) reader structure"]
impl crate :: Readable for SOAR2_SPEC { } # [doc = "`write(|w| ..)` method takes [`soar2::W`](W) writer structure"]
impl crate :: Writable for SOAR2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SOAR2 to value 0"]
impl crate :: Resettable for SOAR2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SCTR (rw) register accessor: I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sctr`]
module"]
pub type SCTR = crate :: Reg < sctr :: SCTR_SPEC > ; # [doc = "I2C Slave Control Register"]
pub mod sctr { # [doc = "Register `SCTR` reader"]
pub type R = crate :: R < SCTR_SPEC > ; # [doc = "Register `SCTR` writer"]
pub type W = crate :: W < SCTR_SPEC > ; # [doc = "Field `SCTR_ACTIVE` reader - Device Active. Setting this bit enables the slave functionality."]
pub type SCTR_ACTIVE_R = crate :: BitReader < SCTR_ACTIVE_A > ; # [doc = "Device Active. Setting this bit enables the slave functionality.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_ACTIVE_A { # [doc = "0: DISABLE"]
SCTR_ACTIVE_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_ACTIVE_ENABLE = 1 , } impl From < SCTR_ACTIVE_A > for bool { # [inline (always)]
fn from (variant : SCTR_ACTIVE_A) -> Self { variant as u8 != 0 } } impl SCTR_ACTIVE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_ACTIVE_A { match self . bits { false => SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE , true => SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_active_disable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_active_enable (& self) -> bool { * self == SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE } } # [doc = "Field `SCTR_ACTIVE` writer - Device Active. Setting this bit enables the slave functionality."]
pub type SCTR_ACTIVE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_ACTIVE_A > ; impl < 'a , REG , const O : u8 > SCTR_ACTIVE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_active_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_active_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_ACTIVE_A :: SCTR_ACTIVE_ENABLE) } } # [doc = "Field `SCTR_GENCALL` reader - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
pub type SCTR_GENCALL_R = crate :: BitReader < SCTR_GENCALL_A > ; # [doc = "General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_GENCALL_A { # [doc = "0: DISABLE"]
SCTR_GENCALL_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_GENCALL_ENABLE = 1 , } impl From < SCTR_GENCALL_A > for bool { # [inline (always)]
fn from (variant : SCTR_GENCALL_A) -> Self { variant as u8 != 0 } } impl SCTR_GENCALL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_GENCALL_A { match self . bits { false => SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE , true => SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_gencall_disable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_gencall_enable (& self) -> bool { * self == SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE } } # [doc = "Field `SCTR_GENCALL` writer - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
pub type SCTR_GENCALL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_GENCALL_A > ; impl < 'a , REG , const O : u8 > SCTR_GENCALL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_gencall_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_gencall_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_GENCALL_A :: SCTR_GENCALL_ENABLE) } } # [doc = "Field `SCTR_SCLKSTRETCH` reader - Slave Clock Stretch Enable"]
pub type SCTR_SCLKSTRETCH_R = crate :: BitReader < SCTR_SCLKSTRETCH_A > ; # [doc = "Slave Clock Stretch Enable\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_SCLKSTRETCH_A { # [doc = "0: DISABLE"]
SCTR_SCLKSTRETCH_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_SCLKSTRETCH_ENABLE = 1 , } impl From < SCTR_SCLKSTRETCH_A > for bool { # [inline (always)]
fn from (variant : SCTR_SCLKSTRETCH_A) -> Self { variant as u8 != 0 } } impl SCTR_SCLKSTRETCH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_SCLKSTRETCH_A { match self . bits { false => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE , true => SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_sclkstretch_disable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_sclkstretch_enable (& self) -> bool { * self == SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE } } # [doc = "Field `SCTR_SCLKSTRETCH` writer - Slave Clock Stretch Enable"]
pub type SCTR_SCLKSTRETCH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SCLKSTRETCH_A > ; impl < 'a , REG , const O : u8 > SCTR_SCLKSTRETCH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_sclkstretch_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_sclkstretch_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SCLKSTRETCH_A :: SCTR_SCLKSTRETCH_ENABLE) } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` reader - Tx Empty Interrupt on TREQ"]
pub type SCTR_TXEMPTY_ON_TREQ_R = crate :: BitReader < SCTR_TXEMPTY_ON_TREQ_A > ; # [doc = "Tx Empty Interrupt on TREQ\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_TXEMPTY_ON_TREQ_A { # [doc = "0: DISABLE"]
SCTR_TXEMPTY_ON_TREQ_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_TXEMPTY_ON_TREQ_ENABLE = 1 , } impl From < SCTR_TXEMPTY_ON_TREQ_A > for bool { # [inline (always)]
fn from (variant : SCTR_TXEMPTY_ON_TREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_TXEMPTY_ON_TREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_TXEMPTY_ON_TREQ_A { match self . bits { false => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE , true => SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_txempty_on_treq_disable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_txempty_on_treq_enable (& self) -> bool { * self == SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE } } # [doc = "Field `SCTR_TXEMPTY_ON_TREQ` writer - Tx Empty Interrupt on TREQ"]
pub type SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXEMPTY_ON_TREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_TXEMPTY_ON_TREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_txempty_on_treq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_txempty_on_treq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXEMPTY_ON_TREQ_A :: SCTR_TXEMPTY_ON_TREQ_ENABLE) } } # [doc = "Field `SCTR_TXTRIG_TXMODE` reader - Tx Trigger when slave FSM is in Tx Mode"]
pub type SCTR_TXTRIG_TXMODE_R = crate :: BitReader < SCTR_TXTRIG_TXMODE_A > ; # [doc = "Tx Trigger when slave FSM is in Tx Mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_TXTRIG_TXMODE_A { # [doc = "0: DISABLE"]
SCTR_TXTRIG_TXMODE_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_TXTRIG_TXMODE_ENABLE = 1 , } impl From < SCTR_TXTRIG_TXMODE_A > for bool { # [inline (always)]
fn from (variant : SCTR_TXTRIG_TXMODE_A) -> Self { variant as u8 != 0 } } impl SCTR_TXTRIG_TXMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_TXTRIG_TXMODE_A { match self . bits { false => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE , true => SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_txtrig_txmode_disable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_txtrig_txmode_enable (& self) -> bool { * self == SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE } } # [doc = "Field `SCTR_TXTRIG_TXMODE` writer - Tx Trigger when slave FSM is in Tx Mode"]
pub type SCTR_TXTRIG_TXMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXTRIG_TXMODE_A > ; impl < 'a , REG , const O : u8 > SCTR_TXTRIG_TXMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_txtrig_txmode_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_txtrig_txmode_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXTRIG_TXMODE_A :: SCTR_TXTRIG_TXMODE_ENABLE) } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` reader - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
pub type SCTR_TXWAIT_STALE_TXFIFO_R = crate :: BitReader < SCTR_TXWAIT_STALE_TXFIFO_A > ; # [doc = "Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_TXWAIT_STALE_TXFIFO_A { # [doc = "0: DISABLE"]
SCTR_TXWAIT_STALE_TXFIFO_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_TXWAIT_STALE_TXFIFO_ENABLE = 1 , } impl From < SCTR_TXWAIT_STALE_TXFIFO_A > for bool { # [inline (always)]
fn from (variant : SCTR_TXWAIT_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SCTR_TXWAIT_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_TXWAIT_STALE_TXFIFO_A { match self . bits { false => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE , true => SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_txwait_stale_txfifo_disable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_txwait_stale_txfifo_enable (& self) -> bool { * self == SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE } } # [doc = "Field `SCTR_TXWAIT_STALE_TXFIFO` writer - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
pub type SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_TXWAIT_STALE_TXFIFO_A > ; impl < 'a , REG , const O : u8 > SCTR_TXWAIT_STALE_TXFIFO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_txwait_stale_txfifo_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_txwait_stale_txfifo_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_TXWAIT_STALE_TXFIFO_A :: SCTR_TXWAIT_STALE_TXFIFO_ENABLE) } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` reader - Rx full interrupt generated on RREQ condition as indicated in SSR"]
pub type SCTR_RXFULL_ON_RREQ_R = crate :: BitReader < SCTR_RXFULL_ON_RREQ_A > ; # [doc = "Rx full interrupt generated on RREQ condition as indicated in SSR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_RXFULL_ON_RREQ_A { # [doc = "0: DISABLE"]
SCTR_RXFULL_ON_RREQ_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_RXFULL_ON_RREQ_ENABLE = 1 , } impl From < SCTR_RXFULL_ON_RREQ_A > for bool { # [inline (always)]
fn from (variant : SCTR_RXFULL_ON_RREQ_A) -> Self { variant as u8 != 0 } } impl SCTR_RXFULL_ON_RREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_RXFULL_ON_RREQ_A { match self . bits { false => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE , true => SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_rxfull_on_rreq_disable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_rxfull_on_rreq_enable (& self) -> bool { * self == SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE } } # [doc = "Field `SCTR_RXFULL_ON_RREQ` writer - Rx full interrupt generated on RREQ condition as indicated in SSR"]
pub type SCTR_RXFULL_ON_RREQ_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_RXFULL_ON_RREQ_A > ; impl < 'a , REG , const O : u8 > SCTR_RXFULL_ON_RREQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_rxfull_on_rreq_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_rxfull_on_rreq_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_RXFULL_ON_RREQ_A :: SCTR_RXFULL_ON_RREQ_ENABLE) } } # [doc = "Field `SCTR_EN_DEFHOSTADR` reader - Enable Default Host Address"]
pub type SCTR_EN_DEFHOSTADR_R = crate :: BitReader < SCTR_EN_DEFHOSTADR_A > ; # [doc = "Enable Default Host Address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_EN_DEFHOSTADR_A { # [doc = "0: DISABLE"]
SCTR_EN_DEFHOSTADR_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_EN_DEFHOSTADR_ENABLE = 1 , } impl From < SCTR_EN_DEFHOSTADR_A > for bool { # [inline (always)]
fn from (variant : SCTR_EN_DEFHOSTADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFHOSTADR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_EN_DEFHOSTADR_A { match self . bits { false => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE , true => SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_en_defhostadr_disable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_en_defhostadr_enable (& self) -> bool { * self == SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFHOSTADR` writer - Enable Default Host Address"]
pub type SCTR_EN_DEFHOSTADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFHOSTADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFHOSTADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_en_defhostadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_en_defhostadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFHOSTADR_A :: SCTR_EN_DEFHOSTADR_ENABLE) } } # [doc = "Field `SCTR_EN_ALRESPADR` reader - Enable Alert Response Address"]
pub type SCTR_EN_ALRESPADR_R = crate :: BitReader < SCTR_EN_ALRESPADR_A > ; # [doc = "Enable Alert Response Address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_EN_ALRESPADR_A { # [doc = "0: DISABLE"]
SCTR_EN_ALRESPADR_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_EN_ALRESPADR_ENABLE = 1 , } impl From < SCTR_EN_ALRESPADR_A > for bool { # [inline (always)]
fn from (variant : SCTR_EN_ALRESPADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_ALRESPADR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_EN_ALRESPADR_A { match self . bits { false => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE , true => SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_en_alrespadr_disable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_en_alrespadr_enable (& self) -> bool { * self == SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE } } # [doc = "Field `SCTR_EN_ALRESPADR` writer - Enable Alert Response Address"]
pub type SCTR_EN_ALRESPADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_ALRESPADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_ALRESPADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_en_alrespadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_en_alrespadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_ALRESPADR_A :: SCTR_EN_ALRESPADR_ENABLE) } } # [doc = "Field `SCTR_EN_DEFDEVADR` reader - Enable Deault device address"]
pub type SCTR_EN_DEFDEVADR_R = crate :: BitReader < SCTR_EN_DEFDEVADR_A > ; # [doc = "Enable Deault device address\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_EN_DEFDEVADR_A { # [doc = "0: DISABLE"]
SCTR_EN_DEFDEVADR_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_EN_DEFDEVADR_ENABLE = 1 , } impl From < SCTR_EN_DEFDEVADR_A > for bool { # [inline (always)]
fn from (variant : SCTR_EN_DEFDEVADR_A) -> Self { variant as u8 != 0 } } impl SCTR_EN_DEFDEVADR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_EN_DEFDEVADR_A { match self . bits { false => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE , true => SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_en_defdevadr_disable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_en_defdevadr_enable (& self) -> bool { * self == SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE } } # [doc = "Field `SCTR_EN_DEFDEVADR` writer - Enable Deault device address"]
pub type SCTR_EN_DEFDEVADR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_EN_DEFDEVADR_A > ; impl < 'a , REG , const O : u8 > SCTR_EN_DEFDEVADR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_en_defdevadr_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_en_defdevadr_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_EN_DEFDEVADR_A :: SCTR_EN_DEFDEVADR_ENABLE) } } # [doc = "Field `SCTR_SWUEN` reader - Slave Wakeup Enable"]
pub type SCTR_SWUEN_R = crate :: BitReader < SCTR_SWUEN_A > ; # [doc = "Slave Wakeup Enable\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SCTR_SWUEN_A { # [doc = "0: DISABLE"]
SCTR_SWUEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SCTR_SWUEN_ENABLE = 1 , } impl From < SCTR_SWUEN_A > for bool { # [inline (always)]
fn from (variant : SCTR_SWUEN_A) -> Self { variant as u8 != 0 } } impl SCTR_SWUEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SCTR_SWUEN_A { match self . bits { false => SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE , true => SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sctr_swuen_disable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sctr_swuen_enable (& self) -> bool { * self == SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE } } # [doc = "Field `SCTR_SWUEN` writer - Slave Wakeup Enable"]
pub type SCTR_SWUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SCTR_SWUEN_A > ; impl < 'a , REG , const O : u8 > SCTR_SWUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sctr_swuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sctr_swuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SCTR_SWUEN_A :: SCTR_SWUEN_ENABLE) } } impl R { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."]
# [inline (always)]
pub fn sctr_active (& self) -> SCTR_ACTIVE_R { SCTR_ACTIVE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
# [inline (always)]
pub fn sctr_gencall (& self) -> SCTR_GENCALL_R { SCTR_GENCALL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave Clock Stretch Enable"]
# [inline (always)]
pub fn sctr_sclkstretch (& self) -> SCTR_SCLKSTRETCH_R { SCTR_SCLKSTRETCH_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"]
# [inline (always)]
pub fn sctr_txempty_on_treq (& self) -> SCTR_TXEMPTY_ON_TREQ_R { SCTR_TXEMPTY_ON_TREQ_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"]
# [inline (always)]
pub fn sctr_txtrig_txmode (& self) -> SCTR_TXTRIG_TXMODE_R { SCTR_TXTRIG_TXMODE_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
# [inline (always)]
pub fn sctr_txwait_stale_txfifo (& self) -> SCTR_TXWAIT_STALE_TXFIFO_R { SCTR_TXWAIT_STALE_TXFIFO_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"]
# [inline (always)]
pub fn sctr_rxfull_on_rreq (& self) -> SCTR_RXFULL_ON_RREQ_R { SCTR_RXFULL_ON_RREQ_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Enable Default Host Address"]
# [inline (always)]
pub fn sctr_en_defhostadr (& self) -> SCTR_EN_DEFHOSTADR_R { SCTR_EN_DEFHOSTADR_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Enable Alert Response Address"]
# [inline (always)]
pub fn sctr_en_alrespadr (& self) -> SCTR_EN_ALRESPADR_R { SCTR_EN_ALRESPADR_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Enable Deault device address"]
# [inline (always)]
pub fn sctr_en_defdevadr (& self) -> SCTR_EN_DEFDEVADR_R { SCTR_EN_DEFDEVADR_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Slave Wakeup Enable"]
# [inline (always)]
pub fn sctr_swuen (& self) -> SCTR_SWUEN_R { SCTR_SWUEN_R :: new (((self . bits >> 10) & 1) != 0) } } impl W { # [doc = "Bit 0 - Device Active. Setting this bit enables the slave functionality."]
# [inline (always)]
# [must_use]
pub fn sctr_active (& mut self) -> SCTR_ACTIVE_W < SCTR_SPEC , 0 > { SCTR_ACTIVE_W :: new (self) } # [doc = "Bit 1 - General call response enable. This bit is only available in UCBxI2COA0. Modify only when UCSWRST = 1. 0b = Do not respond to a general call 1b = Respond to a general call"]
# [inline (always)]
# [must_use]
pub fn sctr_gencall (& mut self) -> SCTR_GENCALL_W < SCTR_SPEC , 1 > { SCTR_GENCALL_W :: new (self) } # [doc = "Bit 2 - Slave Clock Stretch Enable"]
# [inline (always)]
# [must_use]
pub fn sctr_sclkstretch (& mut self) -> SCTR_SCLKSTRETCH_W < SCTR_SPEC , 2 > { SCTR_SCLKSTRETCH_W :: new (self) } # [doc = "Bit 3 - Tx Empty Interrupt on TREQ"]
# [inline (always)]
# [must_use]
pub fn sctr_txempty_on_treq (& mut self) -> SCTR_TXEMPTY_ON_TREQ_W < SCTR_SPEC , 3 > { SCTR_TXEMPTY_ON_TREQ_W :: new (self) } # [doc = "Bit 4 - Tx Trigger when slave FSM is in Tx Mode"]
# [inline (always)]
# [must_use]
pub fn sctr_txtrig_txmode (& mut self) -> SCTR_TXTRIG_TXMODE_W < SCTR_SPEC , 4 > { SCTR_TXTRIG_TXMODE_W :: new (self) } # [doc = "Bit 5 - Tx transfer waits when stale data in Tx FIFO. This prevents stale bytes left in the TX FIFO from automatically being sent on the next I2C packet. Note: this should be used with TXEMPTY_ON_TREQ set to prevent the Slave State Machine from waiting for TX FIFO data without an interrupt notification when the FIFO data is stale."]
# [inline (always)]
# [must_use]
pub fn sctr_txwait_stale_txfifo (& mut self) -> SCTR_TXWAIT_STALE_TXFIFO_W < SCTR_SPEC , 5 > { SCTR_TXWAIT_STALE_TXFIFO_W :: new (self) } # [doc = "Bit 6 - Rx full interrupt generated on RREQ condition as indicated in SSR"]
# [inline (always)]
# [must_use]
pub fn sctr_rxfull_on_rreq (& mut self) -> SCTR_RXFULL_ON_RREQ_W < SCTR_SPEC , 6 > { SCTR_RXFULL_ON_RREQ_W :: new (self) } # [doc = "Bit 7 - Enable Default Host Address"]
# [inline (always)]
# [must_use]
pub fn sctr_en_defhostadr (& mut self) -> SCTR_EN_DEFHOSTADR_W < SCTR_SPEC , 7 > { SCTR_EN_DEFHOSTADR_W :: new (self) } # [doc = "Bit 8 - Enable Alert Response Address"]
# [inline (always)]
# [must_use]
pub fn sctr_en_alrespadr (& mut self) -> SCTR_EN_ALRESPADR_W < SCTR_SPEC , 8 > { SCTR_EN_ALRESPADR_W :: new (self) } # [doc = "Bit 9 - Enable Deault device address"]
# [inline (always)]
# [must_use]
pub fn sctr_en_defdevadr (& mut self) -> SCTR_EN_DEFDEVADR_W < SCTR_SPEC , 9 > { SCTR_EN_DEFDEVADR_W :: new (self) } # [doc = "Bit 10 - Slave Wakeup Enable"]
# [inline (always)]
# [must_use]
pub fn sctr_swuen (& mut self) -> SCTR_SWUEN_W < SCTR_SPEC , 10 > { SCTR_SWUEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SCTR_SPEC ; impl crate :: RegisterSpec for SCTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sctr::R`](R) reader structure"]
impl crate :: Readable for SCTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`sctr::W`](W) writer structure"]
impl crate :: Writable for SCTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCTR to value 0x0404"]
impl crate :: Resettable for SCTR_SPEC { const RESET_VALUE : Self :: Ux = 0x0404 ; } } # [doc = "SSR (r) register accessor: I2C Slave Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ssr`]
module"]
pub type SSR = crate :: Reg < ssr :: SSR_SPEC > ; # [doc = "I2C Slave Status Register"]
pub mod ssr { # [doc = "Register `SSR` reader"]
pub type R = crate :: R < SSR_SPEC > ; # [doc = "Field `SSR_RREQ` reader - Receive Request"]
pub type SSR_RREQ_R = crate :: BitReader < SSR_RREQ_A > ; # [doc = "Receive Request\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_RREQ_A { # [doc = "0: CLEARED"]
SSR_RREQ_CLEARED = 0 , # [doc = "1: SET"]
SSR_RREQ_SET = 1 , } impl From < SSR_RREQ_A > for bool { # [inline (always)]
fn from (variant : SSR_RREQ_A) -> Self { variant as u8 != 0 } } impl SSR_RREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_RREQ_A { match self . bits { false => SSR_RREQ_A :: SSR_RREQ_CLEARED , true => SSR_RREQ_A :: SSR_RREQ_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_rreq_cleared (& self) -> bool { * self == SSR_RREQ_A :: SSR_RREQ_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_rreq_set (& self) -> bool { * self == SSR_RREQ_A :: SSR_RREQ_SET } } # [doc = "Field `SSR_TREQ` reader - Transmit Request"]
pub type SSR_TREQ_R = crate :: BitReader < SSR_TREQ_A > ; # [doc = "Transmit Request\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_TREQ_A { # [doc = "0: CLEARED"]
SSR_TREQ_CLEARED = 0 , # [doc = "1: SET"]
SSR_TREQ_SET = 1 , } impl From < SSR_TREQ_A > for bool { # [inline (always)]
fn from (variant : SSR_TREQ_A) -> Self { variant as u8 != 0 } } impl SSR_TREQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_TREQ_A { match self . bits { false => SSR_TREQ_A :: SSR_TREQ_CLEARED , true => SSR_TREQ_A :: SSR_TREQ_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_treq_cleared (& self) -> bool { * self == SSR_TREQ_A :: SSR_TREQ_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_treq_set (& self) -> bool { * self == SSR_TREQ_A :: SSR_TREQ_SET } } # [doc = "Field `SSR_RXMODE` reader - Slave FSM is in Rx MODE"]
pub type SSR_RXMODE_R = crate :: BitReader < SSR_RXMODE_A > ; # [doc = "Slave FSM is in Rx MODE\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_RXMODE_A { # [doc = "0: CLEARED"]
SSR_RXMODE_CLEARED = 0 , # [doc = "1: SET"]
SSR_RXMODE_SET = 1 , } impl From < SSR_RXMODE_A > for bool { # [inline (always)]
fn from (variant : SSR_RXMODE_A) -> Self { variant as u8 != 0 } } impl SSR_RXMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_RXMODE_A { match self . bits { false => SSR_RXMODE_A :: SSR_RXMODE_CLEARED , true => SSR_RXMODE_A :: SSR_RXMODE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_rxmode_cleared (& self) -> bool { * self == SSR_RXMODE_A :: SSR_RXMODE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_rxmode_set (& self) -> bool { * self == SSR_RXMODE_A :: SSR_RXMODE_SET } } # [doc = "Field `SSR_OAR2SEL` reader - OAR2 Address Matched This bit gets reevaluated after every address comparison."]
pub type SSR_OAR2SEL_R = crate :: BitReader < SSR_OAR2SEL_A > ; # [doc = "OAR2 Address Matched This bit gets reevaluated after every address comparison.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_OAR2SEL_A { # [doc = "0: CLEARED"]
SSR_OAR2SEL_CLEARED = 0 , # [doc = "1: SET"]
SSR_OAR2SEL_SET = 1 , } impl From < SSR_OAR2SEL_A > for bool { # [inline (always)]
fn from (variant : SSR_OAR2SEL_A) -> Self { variant as u8 != 0 } } impl SSR_OAR2SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_OAR2SEL_A { match self . bits { false => SSR_OAR2SEL_A :: SSR_OAR2SEL_CLEARED , true => SSR_OAR2SEL_A :: SSR_OAR2SEL_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_oar2sel_cleared (& self) -> bool { * self == SSR_OAR2SEL_A :: SSR_OAR2SEL_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_oar2sel_set (& self) -> bool { * self == SSR_OAR2SEL_A :: SSR_OAR2SEL_SET } } # [doc = "Field `SSR_QCMDST` reader - Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction"]
pub type SSR_QCMDST_R = crate :: BitReader < SSR_QCMDST_A > ; # [doc = "Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_QCMDST_A { # [doc = "0: CLEARED"]
SSR_QCMDST_CLEARED = 0 , # [doc = "1: SET"]
SSR_QCMDST_SET = 1 , } impl From < SSR_QCMDST_A > for bool { # [inline (always)]
fn from (variant : SSR_QCMDST_A) -> Self { variant as u8 != 0 } } impl SSR_QCMDST_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_QCMDST_A { match self . bits { false => SSR_QCMDST_A :: SSR_QCMDST_CLEARED , true => SSR_QCMDST_A :: SSR_QCMDST_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_qcmdst_cleared (& self) -> bool { * self == SSR_QCMDST_A :: SSR_QCMDST_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_qcmdst_set (& self) -> bool { * self == SSR_QCMDST_A :: SSR_QCMDST_SET } } # [doc = "Field `SSR_QCMDRW` reader - Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read"]
pub type SSR_QCMDRW_R = crate :: BitReader < SSR_QCMDRW_A > ; # [doc = "Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_QCMDRW_A { # [doc = "0: CLEARED"]
SSR_QCMDRW_CLEARED = 0 , # [doc = "1: SET"]
SSR_QCMDRW_SET = 1 , } impl From < SSR_QCMDRW_A > for bool { # [inline (always)]
fn from (variant : SSR_QCMDRW_A) -> Self { variant as u8 != 0 } } impl SSR_QCMDRW_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_QCMDRW_A { match self . bits { false => SSR_QCMDRW_A :: SSR_QCMDRW_CLEARED , true => SSR_QCMDRW_A :: SSR_QCMDRW_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_qcmdrw_cleared (& self) -> bool { * self == SSR_QCMDRW_A :: SSR_QCMDRW_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_qcmdrw_set (& self) -> bool { * self == SSR_QCMDRW_A :: SSR_QCMDRW_SET } } # [doc = "Field `SSR_BUSBSY` reader - I2C bus is busy"]
pub type SSR_BUSBSY_R = crate :: BitReader < SSR_BUSBSY_A > ; # [doc = "I2C bus is busy\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_BUSBSY_A { # [doc = "0: CLEARED"]
SSR_BUSBSY_CLEARED = 0 , # [doc = "1: SET"]
SSR_BUSBSY_SET = 1 , } impl From < SSR_BUSBSY_A > for bool { # [inline (always)]
fn from (variant : SSR_BUSBSY_A) -> Self { variant as u8 != 0 } } impl SSR_BUSBSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_BUSBSY_A { match self . bits { false => SSR_BUSBSY_A :: SSR_BUSBSY_CLEARED , true => SSR_BUSBSY_A :: SSR_BUSBSY_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_busbsy_cleared (& self) -> bool { * self == SSR_BUSBSY_A :: SSR_BUSBSY_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_busbsy_set (& self) -> bool { * self == SSR_BUSBSY_A :: SSR_BUSBSY_SET } } # [doc = "Field `SSR_TXMODE` reader - Slave FSM is in TX MODE"]
pub type SSR_TXMODE_R = crate :: BitReader < SSR_TXMODE_A > ; # [doc = "Slave FSM is in TX MODE\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_TXMODE_A { # [doc = "0: CLEARED"]
SSR_TXMODE_CLEARED = 0 , # [doc = "1: SET"]
SSR_TXMODE_SET = 1 , } impl From < SSR_TXMODE_A > for bool { # [inline (always)]
fn from (variant : SSR_TXMODE_A) -> Self { variant as u8 != 0 } } impl SSR_TXMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_TXMODE_A { match self . bits { false => SSR_TXMODE_A :: SSR_TXMODE_CLEARED , true => SSR_TXMODE_A :: SSR_TXMODE_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_txmode_cleared (& self) -> bool { * self == SSR_TXMODE_A :: SSR_TXMODE_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_txmode_set (& self) -> bool { * self == SSR_TXMODE_A :: SSR_TXMODE_SET } } # [doc = "Field `SSR_STALE_TXFIFO` reader - Stale Tx FIFO"]
pub type SSR_STALE_TXFIFO_R = crate :: BitReader < SSR_STALE_TXFIFO_A > ; # [doc = "Stale Tx FIFO\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SSR_STALE_TXFIFO_A { # [doc = "0: CLEARED"]
SSR_STALE_TXFIFO_CLEARED = 0 , # [doc = "1: SET"]
SSR_STALE_TXFIFO_SET = 1 , } impl From < SSR_STALE_TXFIFO_A > for bool { # [inline (always)]
fn from (variant : SSR_STALE_TXFIFO_A) -> Self { variant as u8 != 0 } } impl SSR_STALE_TXFIFO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SSR_STALE_TXFIFO_A { match self . bits { false => SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_CLEARED , true => SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_ssr_stale_txfifo_cleared (& self) -> bool { * self == SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_ssr_stale_txfifo_set (& self) -> bool { * self == SSR_STALE_TXFIFO_A :: SSR_STALE_TXFIFO_SET } } # [doc = "Field `SSR_ADDRMATCH` reader - Indicates the address for which slave address match happened"]
pub type SSR_ADDRMATCH_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bit 0 - Receive Request"]
# [inline (always)]
pub fn ssr_rreq (& self) -> SSR_RREQ_R { SSR_RREQ_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Transmit Request"]
# [inline (always)]
pub fn ssr_treq (& self) -> SSR_TREQ_R { SSR_TREQ_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Slave FSM is in Rx MODE"]
# [inline (always)]
pub fn ssr_rxmode (& self) -> SSR_RXMODE_R { SSR_RXMODE_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - OAR2 Address Matched This bit gets reevaluated after every address comparison."]
# [inline (always)]
pub fn ssr_oar2sel (& self) -> SSR_OAR2SEL_R { SSR_OAR2SEL_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Quick Command Status Value Description: 0: The last transaction was a normal transaction or a transaction has not occurred. 1: The last transaction was a Quick Command transaction"]
# [inline (always)]
pub fn ssr_qcmdst (& self) -> SSR_QCMDST_R { SSR_QCMDST_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Quick Command Read / Write This bit only has meaning when the QCMDST bit is set. Value Description: 0: Quick command was a write 1: Quick command was a read"]
# [inline (always)]
pub fn ssr_qcmdrw (& self) -> SSR_QCMDRW_R { SSR_QCMDRW_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - I2C bus is busy"]
# [inline (always)]
pub fn ssr_busbsy (& self) -> SSR_BUSBSY_R { SSR_BUSBSY_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 7 - Slave FSM is in TX MODE"]
# [inline (always)]
pub fn ssr_txmode (& self) -> SSR_TXMODE_R { SSR_TXMODE_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 8 - Stale Tx FIFO"]
# [inline (always)]
pub fn ssr_stale_txfifo (& self) -> SSR_STALE_TXFIFO_R { SSR_STALE_TXFIFO_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 9:18 - Indicates the address for which slave address match happened"]
# [inline (always)]
pub fn ssr_addrmatch (& self) -> SSR_ADDRMATCH_R { SSR_ADDRMATCH_R :: new (((self . bits >> 9) & 0x03ff) as u16) } } # [doc = "I2C Slave Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ssr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SSR_SPEC ; impl crate :: RegisterSpec for SSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ssr::R`](R) reader structure"]
impl crate :: Readable for SSR_SPEC { } # [doc = "`reset()` method sets SSR to value 0"]
impl crate :: Resettable for SSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SRXDATA (r) register accessor: I2C Slave RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srxdata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@srxdata`]
module"]
pub type SRXDATA = crate :: Reg < srxdata :: SRXDATA_SPEC > ; # [doc = "I2C Slave RXData"]
pub mod srxdata { # [doc = "Register `SRXDATA` reader"]
pub type R = crate :: R < SRXDATA_SPEC > ; # [doc = "Field `SRXDATA_VALUE` reader - Received Data. This field contains the last received data."]
pub type SRXDATA_VALUE_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Received Data. This field contains the last received data."]
# [inline (always)]
pub fn srxdata_value (& self) -> SRXDATA_VALUE_R { SRXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } # [doc = "I2C Slave RXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`srxdata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SRXDATA_SPEC ; impl crate :: RegisterSpec for SRXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`srxdata::R`](R) reader structure"]
impl crate :: Readable for SRXDATA_SPEC { } # [doc = "`reset()` method sets SRXDATA to value 0"]
impl crate :: Resettable for SRXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STXDATA (rw) register accessor: I2C Slave TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stxdata::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stxdata::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stxdata`]
module"]
pub type STXDATA = crate :: Reg < stxdata :: STXDATA_SPEC > ; # [doc = "I2C Slave TXData"]
pub mod stxdata { # [doc = "Register `STXDATA` reader"]
pub type R = crate :: R < STXDATA_SPEC > ; # [doc = "Register `STXDATA` writer"]
pub type W = crate :: W < STXDATA_SPEC > ; # [doc = "Field `STXDATA_VALUE` reader - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type STXDATA_VALUE_R = crate :: FieldReader ; # [doc = "Field `STXDATA_VALUE` writer - Transmit Data This byte contains the data to be transferred during the next transaction."]
pub type STXDATA_VALUE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
pub fn stxdata_value (& self) -> STXDATA_VALUE_R { STXDATA_VALUE_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Transmit Data This byte contains the data to be transferred during the next transaction."]
# [inline (always)]
# [must_use]
pub fn stxdata_value (& mut self) -> STXDATA_VALUE_W < STXDATA_SPEC , 0 > { STXDATA_VALUE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave TXData\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stxdata::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stxdata::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STXDATA_SPEC ; impl crate :: RegisterSpec for STXDATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stxdata::R`](R) reader structure"]
impl crate :: Readable for STXDATA_SPEC { } # [doc = "`write(|w| ..)` method takes [`stxdata::W`](W) writer structure"]
impl crate :: Writable for STXDATA_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets STXDATA to value 0"]
impl crate :: Resettable for STXDATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SACKCTL (rw) register accessor: I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sackctl`]
module"]
pub type SACKCTL = crate :: Reg < sackctl :: SACKCTL_SPEC > ; # [doc = "I2C Slave ACK Control"]
pub mod sackctl { # [doc = "Register `SACKCTL` reader"]
pub type R = crate :: R < SACKCTL_SPEC > ; # [doc = "Register `SACKCTL` writer"]
pub type W = crate :: W < SACKCTL_SPEC > ; # [doc = "Field `SACKCTL_ACKOEN` reader - I2C Slave ACK Override Enable"]
pub type SACKCTL_ACKOEN_R = crate :: BitReader < SACKCTL_ACKOEN_A > ; # [doc = "I2C Slave ACK Override Enable\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_A { match self . bits { false => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE , true => SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_disable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_enable (& self) -> bool { * self == SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN` writer - I2C Slave ACK Override Enable"]
pub type SACKCTL_ACKOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_A :: SACKCTL_ACKOEN_ENABLE) } } # [doc = "Field `SACKCTL_ACKOVAL` reader - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
pub type SACKCTL_ACKOVAL_R = crate :: BitReader < SACKCTL_ACKOVAL_A > ; # [doc = "I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOVAL_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOVAL_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOVAL_ENABLE = 1 , } impl From < SACKCTL_ACKOVAL_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOVAL_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOVAL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOVAL_A { match self . bits { false => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE , true => SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoval_disable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoval_enable (& self) -> bool { * self == SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE } } # [doc = "Field `SACKCTL_ACKOVAL` writer - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
pub type SACKCTL_ACKOVAL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOVAL_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOVAL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoval_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoval_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOVAL_A :: SACKCTL_ACKOVAL_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` reader - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
pub type SACKCTL_ACKOEN_ON_START_R = crate :: BitReader < SACKCTL_ACKOEN_ON_START_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_ON_START_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_ON_START_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ON_START_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_START_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_ON_START_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_START_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_START_A { match self . bits { false => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE , true => SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_start_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_start_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_START` writer - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
pub type SACKCTL_ACKOEN_ON_START_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_START_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_START_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_start_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_start_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_START_A :: SACKCTL_ACKOEN_ON_START_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
pub type SACKCTL_ACKOEN_ON_PECNEXT_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECNEXT_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_ON_PECNEXT_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_ON_PECNEXT_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ON_PECNEXT_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECNEXT_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_ON_PECNEXT_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECNEXT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE , true => SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecnext_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecnext_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECNEXT` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
pub type SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECNEXT_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECNEXT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecnext_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecnext_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECNEXT_A :: SACKCTL_ACKOEN_ON_PECNEXT_ENABLE) } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` reader - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
pub type SACKCTL_ACKOEN_ON_PECDONE_R = crate :: BitReader < SACKCTL_ACKOEN_ON_PECDONE_A > ; # [doc = "When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SACKCTL_ACKOEN_ON_PECDONE_A { # [doc = "0: DISABLE"]
SACKCTL_ACKOEN_ON_PECDONE_DISABLE = 0 , # [doc = "1: ENABLE"]
SACKCTL_ACKOEN_ON_PECDONE_ENABLE = 1 , } impl From < SACKCTL_ACKOEN_ON_PECDONE_A > for bool { # [inline (always)]
fn from (variant : SACKCTL_ACKOEN_ON_PECDONE_A) -> Self { variant as u8 != 0 } } impl SACKCTL_ACKOEN_ON_PECDONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SACKCTL_ACKOEN_ON_PECDONE_A { match self . bits { false => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE , true => SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecdone_disable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_sackctl_ackoen_on_pecdone_enable (& self) -> bool { * self == SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE } } # [doc = "Field `SACKCTL_ACKOEN_ON_PECDONE` writer - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
pub type SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SACKCTL_ACKOEN_ON_PECDONE_A > ; impl < 'a , REG , const O : u8 > SACKCTL_ACKOEN_ON_PECDONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecdone_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn sackctl_ackoen_on_pecdone_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SACKCTL_ACKOEN_ON_PECDONE_A :: SACKCTL_ACKOEN_ON_PECDONE_ENABLE) } } impl R { # [doc = "Bit 0 - I2C Slave ACK Override Enable"]
# [inline (always)]
pub fn sackctl_ackoen (& self) -> SACKCTL_ACKOEN_R { SACKCTL_ACKOEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
# [inline (always)]
pub fn sackctl_ackoval (& self) -> SACKCTL_ACKOVAL_R { SACKCTL_ACKOVAL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
# [inline (always)]
pub fn sackctl_ackoen_on_start (& self) -> SACKCTL_ACKOEN_ON_START_R { SACKCTL_ACKOEN_ON_START_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
# [inline (always)]
pub fn sackctl_ackoen_on_pecnext (& self) -> SACKCTL_ACKOEN_ON_PECNEXT_R { SACKCTL_ACKOEN_ON_PECNEXT_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
# [inline (always)]
pub fn sackctl_ackoen_on_pecdone (& self) -> SACKCTL_ACKOEN_ON_PECDONE_R { SACKCTL_ACKOEN_ON_PECDONE_R :: new (((self . bits >> 4) & 1) != 0) } } impl W { # [doc = "Bit 0 - I2C Slave ACK Override Enable"]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen (& mut self) -> SACKCTL_ACKOEN_W < SACKCTL_SPEC , 0 > { SACKCTL_ACKOEN_W :: new (self) } # [doc = "Bit 1 - I2C Slave ACK Override Value Note: for General Call this bit will be ignored if set to NACK and slave continues to receive data."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoval (& mut self) -> SACKCTL_ACKOVAL_W < SACKCTL_SPEC , 1 > { SACKCTL_ACKOVAL_W :: new (self) } # [doc = "Bit 2 - When set this bit will automatically turn on the Slave ACKOEN field following a Start Condition."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen_on_start (& mut self) -> SACKCTL_ACKOEN_ON_START_W < SACKCTL_SPEC , 2 > { SACKCTL_ACKOEN_ON_START_W :: new (self) } # [doc = "Bit 3 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the byte received just prior to the PEC byte. Note that when ACKOEN is set the PEC byte will not automatically be ACKed/NACKed by the State Machine and FW must perform this function by writing SLAVE_SACKCTL."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen_on_pecnext (& mut self) -> SACKCTL_ACKOEN_ON_PECNEXT_W < SACKCTL_SPEC , 3 > { SACKCTL_ACKOEN_ON_PECNEXT_W :: new (self) } # [doc = "Bit 4 - When set this bit will automatically turn on the Slave ACKOEN field following the ACK/NACK of the received PEC byte."]
# [inline (always)]
# [must_use]
pub fn sackctl_ackoen_on_pecdone (& mut self) -> SACKCTL_ACKOEN_ON_PECDONE_W < SACKCTL_SPEC , 4 > { SACKCTL_ACKOEN_ON_PECDONE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave ACK Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sackctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sackctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SACKCTL_SPEC ; impl crate :: RegisterSpec for SACKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sackctl::R`](R) reader structure"]
impl crate :: Readable for SACKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sackctl::W`](W) writer structure"]
impl crate :: Writable for SACKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SACKCTL to value 0"]
impl crate :: Resettable for SACKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SFIFOCTL (rw) register accessor: I2C Slave FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifoctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfifoctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfifoctl`]
module"]
pub type SFIFOCTL = crate :: Reg < sfifoctl :: SFIFOCTL_SPEC > ; # [doc = "I2C Slave FIFO Control"]
pub mod sfifoctl { # [doc = "Register `SFIFOCTL` reader"]
pub type R = crate :: R < SFIFOCTL_SPEC > ; # [doc = "Register `SFIFOCTL` writer"]
pub type W = crate :: W < SFIFOCTL_SPEC > ; # [doc = "Field `SFIFOCTL_TXTRIG` reader - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type SFIFOCTL_TXTRIG_R = crate :: FieldReader < SFIFOCTL_TXTRIG_A > ; # [doc = "TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SFIFOCTL_TXTRIG_A { # [doc = "4: LEVEL_4"]
SFIFOCTL_TXTRIG_LEVEL_4 = 4 , # [doc = "5: LEVEL_5"]
SFIFOCTL_TXTRIG_LEVEL_5 = 5 , # [doc = "6: LEVEL_6"]
SFIFOCTL_TXTRIG_LEVEL_6 = 6 , # [doc = "7: LEVEL_7"]
SFIFOCTL_TXTRIG_LEVEL_7 = 7 , } impl From < SFIFOCTL_TXTRIG_A > for u8 { # [inline (always)]
fn from (variant : SFIFOCTL_TXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for SFIFOCTL_TXTRIG_A { type Ux = u8 ; } impl SFIFOCTL_TXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SFIFOCTL_TXTRIG_A > { match self . bits { 4 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4) , 5 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5) , 6 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6) , 7 => Some (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7) , _ => None , } } # [doc = "LEVEL_4"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_4 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4 } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_5 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_6 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_sfifoctl_txtrig_level_7 (& self) -> bool { * self == SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7 } } # [doc = "Field `SFIFOCTL_TXTRIG` writer - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
pub type SFIFOCTL_TXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , SFIFOCTL_TXTRIG_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_TXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_4"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_4 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_4) } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn sfifoctl_txtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXTRIG_A :: SFIFOCTL_TXTRIG_LEVEL_7) } } # [doc = "Field `SFIFOCTL_TXFLUSH` reader - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type SFIFOCTL_TXFLUSH_R = crate :: BitReader < SFIFOCTL_TXFLUSH_A > ; # [doc = "TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOCTL_TXFLUSH_A { # [doc = "0: NOFLUSH"]
SFIFOCTL_TXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
SFIFOCTL_TXFLUSH_FLUSH = 1 , } impl From < SFIFOCTL_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOCTL_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOCTL_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOCTL_TXFLUSH_A { match self . bits { false => SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH , true => SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_sfifoctl_txflush_noflush (& self) -> bool { * self == SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_sfifoctl_txflush_flush (& self) -> bool { * self == SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH } } # [doc = "Field `SFIFOCTL_TXFLUSH` writer - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
pub type SFIFOCTL_TXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SFIFOCTL_TXFLUSH_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_TXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn sfifoctl_txflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn sfifoctl_txflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_TXFLUSH_A :: SFIFOCTL_TXFLUSH_FLUSH) } } # [doc = "Field `SFIFOCTL_RXTRIG` reader - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type SFIFOCTL_RXTRIG_R = crate :: FieldReader < SFIFOCTL_RXTRIG_A > ; # [doc = "RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum SFIFOCTL_RXTRIG_A { # [doc = "4: LEVEL_5"]
SFIFOCTL_RXTRIG_LEVEL_5 = 4 , # [doc = "5: LEVEL_6"]
SFIFOCTL_RXTRIG_LEVEL_6 = 5 , # [doc = "6: LEVEL_7"]
SFIFOCTL_RXTRIG_LEVEL_7 = 6 , # [doc = "7: LEVEL_8"]
SFIFOCTL_RXTRIG_LEVEL_8 = 7 , } impl From < SFIFOCTL_RXTRIG_A > for u8 { # [inline (always)]
fn from (variant : SFIFOCTL_RXTRIG_A) -> Self { variant as _ } } impl crate :: FieldSpec for SFIFOCTL_RXTRIG_A { type Ux = u8 ; } impl SFIFOCTL_RXTRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < SFIFOCTL_RXTRIG_A > { match self . bits { 4 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5) , 5 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6) , 6 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7) , 7 => Some (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8) , _ => None , } } # [doc = "LEVEL_5"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_5 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5 } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_6 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6 } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_7 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7 } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn is_sfifoctl_rxtrig_level_8 (& self) -> bool { * self == SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8 } } # [doc = "Field `SFIFOCTL_RXTRIG` writer - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
pub type SFIFOCTL_RXTRIG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , SFIFOCTL_RXTRIG_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_RXTRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LEVEL_5"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_5 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_5) } # [doc = "LEVEL_6"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_6 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_6) } # [doc = "LEVEL_7"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_7 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_7) } # [doc = "LEVEL_8"]
# [inline (always)]
pub fn sfifoctl_rxtrig_level_8 (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXTRIG_A :: SFIFOCTL_RXTRIG_LEVEL_8) } } # [doc = "Field `SFIFOCTL_RXFLUSH` reader - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type SFIFOCTL_RXFLUSH_R = crate :: BitReader < SFIFOCTL_RXFLUSH_A > ; # [doc = "RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOCTL_RXFLUSH_A { # [doc = "0: NOFLUSH"]
SFIFOCTL_RXFLUSH_NOFLUSH = 0 , # [doc = "1: FLUSH"]
SFIFOCTL_RXFLUSH_FLUSH = 1 , } impl From < SFIFOCTL_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOCTL_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOCTL_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOCTL_RXFLUSH_A { match self . bits { false => SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH , true => SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH , } } # [doc = "NOFLUSH"]
# [inline (always)]
pub fn is_sfifoctl_rxflush_noflush (& self) -> bool { * self == SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH } # [doc = "FLUSH"]
# [inline (always)]
pub fn is_sfifoctl_rxflush_flush (& self) -> bool { * self == SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH } } # [doc = "Field `SFIFOCTL_RXFLUSH` writer - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
pub type SFIFOCTL_RXFLUSH_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SFIFOCTL_RXFLUSH_A > ; impl < 'a , REG , const O : u8 > SFIFOCTL_RXFLUSH_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOFLUSH"]
# [inline (always)]
pub fn sfifoctl_rxflush_noflush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_NOFLUSH) } # [doc = "FLUSH"]
# [inline (always)]
pub fn sfifoctl_rxflush_flush (self) -> & 'a mut crate :: W < REG > { self . variant (SFIFOCTL_RXFLUSH_A :: SFIFOCTL_RXFLUSH_FLUSH) } } impl R { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
pub fn sfifoctl_txtrig (& self) -> SFIFOCTL_TXTRIG_R { SFIFOCTL_TXTRIG_R :: new ((self . bits & 7) as u8) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
pub fn sfifoctl_txflush (& self) -> SFIFOCTL_TXFLUSH_R { SFIFOCTL_TXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
pub fn sfifoctl_rxtrig (& self) -> SFIFOCTL_RXTRIG_R { SFIFOCTL_RXTRIG_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
pub fn sfifoctl_rxflush (& self) -> SFIFOCTL_RXFLUSH_R { SFIFOCTL_RXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } impl W { # [doc = "Bits 0:2 - TX FIFO Trigger Indicates at what fill level in the TX FIFO a trigger will be generated."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_txtrig (& mut self) -> SFIFOCTL_TXTRIG_W < SFIFOCTL_SPEC , 0 > { SFIFOCTL_TXTRIG_W :: new (self) } # [doc = "Bit 7 - TX FIFO Flush Setting this bit will Flush the TX FIFO. Before reseting this bit to stop Flush the TXFIFOCNT should be checked to be 8 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_txflush (& mut self) -> SFIFOCTL_TXFLUSH_W < SFIFOCTL_SPEC , 7 > { SFIFOCTL_TXFLUSH_W :: new (self) } # [doc = "Bits 8:10 - RX FIFO Trigger Indicates at what fill level in the RX FIFO a trigger will be generated. Note: Programming RXTRIG to 0x0 has no effect since no data is present to transfer out of RX FIFO."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_rxtrig (& mut self) -> SFIFOCTL_RXTRIG_W < SFIFOCTL_SPEC , 8 > { SFIFOCTL_RXTRIG_W :: new (self) } # [doc = "Bit 15 - RX FIFO Flush Setting this bit will Flush the RX FIFO. Before reseting this bit to stop Flush the RXFIFOCNT should be checked to be 0 and indicating that the Flush has completed."]
# [inline (always)]
# [must_use]
pub fn sfifoctl_rxflush (& mut self) -> SFIFOCTL_RXFLUSH_W < SFIFOCTL_SPEC , 15 > { SFIFOCTL_RXFLUSH_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave FIFO Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifoctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`sfifoctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SFIFOCTL_SPEC ; impl crate :: RegisterSpec for SFIFOCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sfifoctl::R`](R) reader structure"]
impl crate :: Readable for SFIFOCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`sfifoctl::W`](W) writer structure"]
impl crate :: Writable for SFIFOCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SFIFOCTL to value 0"]
impl crate :: Resettable for SFIFOCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SFIFOSR (r) register accessor: I2C Slave FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifosr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sfifosr`]
module"]
pub type SFIFOSR = crate :: Reg < sfifosr :: SFIFOSR_SPEC > ; # [doc = "I2C Slave FIFO Status Register"]
pub mod sfifosr { # [doc = "Register `SFIFOSR` reader"]
pub type R = crate :: R < SFIFOSR_SPEC > ; # [doc = "Field `SFIFOSR_RXFIFOCNT` reader - Number of Bytes which could be read from the RX FIFO"]
pub type SFIFOSR_RXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `SFIFOSR_RXFLUSH` reader - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
pub type SFIFOSR_RXFLUSH_R = crate :: BitReader < SFIFOSR_RXFLUSH_A > ; # [doc = "RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOSR_RXFLUSH_A { # [doc = "0: INACTIVE"]
SFIFOSR_RXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
SFIFOSR_RXFLUSH_ACTIVE = 1 , } impl From < SFIFOSR_RXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOSR_RXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOSR_RXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOSR_RXFLUSH_A { match self . bits { false => SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_INACTIVE , true => SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_sfifosr_rxflush_inactive (& self) -> bool { * self == SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_sfifosr_rxflush_active (& self) -> bool { * self == SFIFOSR_RXFLUSH_A :: SFIFOSR_RXFLUSH_ACTIVE } } # [doc = "Field `SFIFOSR_TXFIFOCNT` reader - Number of Bytes which could be put into the TX FIFO"]
pub type SFIFOSR_TXFIFOCNT_R = crate :: FieldReader ; # [doc = "Field `SFIFOSR_TXFLUSH` reader - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
pub type SFIFOSR_TXFLUSH_R = crate :: BitReader < SFIFOSR_TXFLUSH_A > ; # [doc = "TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SFIFOSR_TXFLUSH_A { # [doc = "0: INACTIVE"]
SFIFOSR_TXFLUSH_INACTIVE = 0 , # [doc = "1: ACTIVE"]
SFIFOSR_TXFLUSH_ACTIVE = 1 , } impl From < SFIFOSR_TXFLUSH_A > for bool { # [inline (always)]
fn from (variant : SFIFOSR_TXFLUSH_A) -> Self { variant as u8 != 0 } } impl SFIFOSR_TXFLUSH_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SFIFOSR_TXFLUSH_A { match self . bits { false => SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_INACTIVE , true => SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_ACTIVE , } } # [doc = "INACTIVE"]
# [inline (always)]
pub fn is_sfifosr_txflush_inactive (& self) -> bool { * self == SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_INACTIVE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_sfifosr_txflush_active (& self) -> bool { * self == SFIFOSR_TXFLUSH_A :: SFIFOSR_TXFLUSH_ACTIVE } } impl R { # [doc = "Bits 0:3 - Number of Bytes which could be read from the RX FIFO"]
# [inline (always)]
pub fn sfifosr_rxfifocnt (& self) -> SFIFOSR_RXFIFOCNT_R { SFIFOSR_RXFIFOCNT_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - RX FIFO Flush When this bit is set a Flush operation for the RX FIFO is active. Clear the RXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn sfifosr_rxflush (& self) -> SFIFOSR_RXFLUSH_R { SFIFOSR_RXFLUSH_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:11 - Number of Bytes which could be put into the TX FIFO"]
# [inline (always)]
pub fn sfifosr_txfifocnt (& self) -> SFIFOSR_TXFIFOCNT_R { SFIFOSR_TXFIFOCNT_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bit 15 - TX FIFO Flush When this bit is set a Flush operation for the TX FIFO is active. Clear the TXFLUSH bit in the control register to stop."]
# [inline (always)]
pub fn sfifosr_txflush (& self) -> SFIFOSR_TXFLUSH_R { SFIFOSR_TXFLUSH_R :: new (((self . bits >> 15) & 1) != 0) } } # [doc = "I2C Slave FIFO Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`sfifosr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SFIFOSR_SPEC ; impl crate :: RegisterSpec for SFIFOSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`sfifosr::R`](R) reader structure"]
impl crate :: Readable for SFIFOSR_SPEC { } # [doc = "`reset()` method sets SFIFOSR to value 0x0800"]
impl crate :: Resettable for SFIFOSR_SPEC { const RESET_VALUE : Self :: Ux = 0x0800 ; } } # [doc = "SLAVE_PECCTL (rw) register accessor: I2C Slave PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave_pecctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slave_pecctl`]
module"]
pub type SLAVE_PECCTL = crate :: Reg < slave_pecctl :: SLAVE_PECCTL_SPEC > ; # [doc = "I2C Slave PEC control register"]
pub mod slave_pecctl { # [doc = "Register `SLAVE_PECCTL` reader"]
pub type R = crate :: R < SLAVE_PECCTL_SPEC > ; # [doc = "Register `SLAVE_PECCTL` writer"]
pub type W = crate :: W < SLAVE_PECCTL_SPEC > ; # [doc = "Field `SLAVE_PECCTL_PECCNT` reader - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
pub type SLAVE_PECCTL_PECCNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `SLAVE_PECCTL_PECCNT` writer - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
pub type SLAVE_PECCTL_PECCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 9 , O , u16 > ; # [doc = "Field `SLAVE_PECCTL_PECEN` reader - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type SLAVE_PECCTL_PECEN_R = crate :: BitReader < SLAVE_PECCTL_PECEN_A > ; # [doc = "PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SLAVE_PECCTL_PECEN_A { # [doc = "0: DISABLE"]
SLAVE_PECCTL_PECEN_DISABLE = 0 , # [doc = "1: ENABLE"]
SLAVE_PECCTL_PECEN_ENABLE = 1 , } impl From < SLAVE_PECCTL_PECEN_A > for bool { # [inline (always)]
fn from (variant : SLAVE_PECCTL_PECEN_A) -> Self { variant as u8 != 0 } } impl SLAVE_PECCTL_PECEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SLAVE_PECCTL_PECEN_A { match self . bits { false => SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_DISABLE , true => SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_slave_pecctl_pecen_disable (& self) -> bool { * self == SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_slave_pecctl_pecen_enable (& self) -> bool { * self == SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_ENABLE } } # [doc = "Field `SLAVE_PECCTL_PECEN` writer - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
pub type SLAVE_PECCTL_PECEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , SLAVE_PECCTL_PECEN_A > ; impl < 'a , REG , const O : u8 > SLAVE_PECCTL_PECEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn slave_pecctl_pecen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn slave_pecctl_pecen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (SLAVE_PECCTL_PECEN_A :: SLAVE_PECCTL_PECEN_ENABLE) } } impl R { # [doc = "Bits 0:8 - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
# [inline (always)]
pub fn slave_pecctl_peccnt (& self) -> SLAVE_PECCTL_PECCNT_R { SLAVE_PECCTL_PECCNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
pub fn slave_pecctl_pecen (& self) -> SLAVE_PECCTL_PECEN_R { SLAVE_PECCTL_PECEN_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:8 - When this field is non zero, the number of I2C data bytes are counted. When the byte count = PECCNT and the state machine is transmitting, the contents of the LSFR is loaded into the shift register instead of the byte received from the Tx FIFO. When the state machine is receiving, after the last bit of this byte is received the LSFR is checked and if it is non-zero, a PEC RX Error interrupt is generated. The I2C packet must be padded to include the PEC byte for both transmit and receive. In transmit mode the FIFO must be loaded with a dummy PEC byte. In receive mode the PEC byte will be passed to the Rx FIFO. In the normal Slave use case, FW would set PECEN=1 and PECCNT=0 and use the ACKOEN until the remaining SMB packet length is known. FW would then set the PECCNT to the remaining packet length (Including PEC bye). FW would then configure DMA to allow the packet to complete unassisted and exit NoAck mode. Note that when the byte count = PEC CNT, the byte count is reset to 0 and multiple PEC calculation can automatically occur within a single I2C transaction"]
# [inline (always)]
# [must_use]
pub fn slave_pecctl_peccnt (& mut self) -> SLAVE_PECCTL_PECCNT_W < SLAVE_PECCTL_SPEC , 0 > { SLAVE_PECCTL_PECCNT_W :: new (self) } # [doc = "Bit 12 - PEC Enable This bit enables the SMB Packet Error Checking (PEC). When enabled the PEC is calculated on all bits accept the Start, Stop, Ack and Nack. The PEC LSFR and the Byte Counter is set to 0 when the State Machine is in the IDLE state, which occur following a Stop or when a timeout occurs. The Counter is also set to 0 after the PEC byte is sent or received. Note that the NACK is automatically send following a PEC byte that results in a PEC error. The PEC Polynomial is x^8 + x^2 + x^1 + 1."]
# [inline (always)]
# [must_use]
pub fn slave_pecctl_pecen (& mut self) -> SLAVE_PECCTL_PECEN_W < SLAVE_PECCTL_SPEC , 12 > { SLAVE_PECCTL_PECEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "I2C Slave PEC control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave_pecctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SLAVE_PECCTL_SPEC ; impl crate :: RegisterSpec for SLAVE_PECCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`slave_pecctl::R`](R) reader structure"]
impl crate :: Readable for SLAVE_PECCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`slave_pecctl::W`](W) writer structure"]
impl crate :: Writable for SLAVE_PECCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SLAVE_PECCTL to value 0"]
impl crate :: Resettable for SLAVE_PECCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SLAVE_PECSR (r) register accessor: I2C slave PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecsr::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slave_pecsr`]
module"]
pub type SLAVE_PECSR = crate :: Reg < slave_pecsr :: SLAVE_PECSR_SPEC > ; # [doc = "I2C slave PEC status register"]
pub mod slave_pecsr { # [doc = "Register `SLAVE_PECSR` reader"]
pub type R = crate :: R < SLAVE_PECSR_SPEC > ; # [doc = "Field `SLAVE_PECSR_PECBYTECNT` reader - This is the current PEC Byte Count of the Slave State Machine."]
pub type SLAVE_PECSR_PECBYTECNT_R = crate :: FieldReader < u16 > ; # [doc = "Field `SLAVE_PECSR_PECSTS_CHECK` reader - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
pub type SLAVE_PECSR_PECSTS_CHECK_R = crate :: BitReader < SLAVE_PECSR_PECSTS_CHECK_A > ; # [doc = "This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SLAVE_PECSR_PECSTS_CHECK_A { # [doc = "0: CLEARED"]
SLAVE_PECSR_PECSTS_CHECK_CLEARED = 0 , # [doc = "1: SET"]
SLAVE_PECSR_PECSTS_CHECK_SET = 1 , } impl From < SLAVE_PECSR_PECSTS_CHECK_A > for bool { # [inline (always)]
fn from (variant : SLAVE_PECSR_PECSTS_CHECK_A) -> Self { variant as u8 != 0 } } impl SLAVE_PECSR_PECSTS_CHECK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SLAVE_PECSR_PECSTS_CHECK_A { match self . bits { false => SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_CLEARED , true => SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_check_cleared (& self) -> bool { * self == SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_check_set (& self) -> bool { * self == SLAVE_PECSR_PECSTS_CHECK_A :: SLAVE_PECSR_PECSTS_CHECK_SET } } # [doc = "Field `SLAVE_PECSR_PECSTS_ERROR` reader - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
pub type SLAVE_PECSR_PECSTS_ERROR_R = crate :: BitReader < SLAVE_PECSR_PECSTS_ERROR_A > ; # [doc = "This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum SLAVE_PECSR_PECSTS_ERROR_A { # [doc = "0: CLEARED"]
SLAVE_PECSR_PECSTS_ERROR_CLEARED = 0 , # [doc = "1: SET"]
SLAVE_PECSR_PECSTS_ERROR_SET = 1 , } impl From < SLAVE_PECSR_PECSTS_ERROR_A > for bool { # [inline (always)]
fn from (variant : SLAVE_PECSR_PECSTS_ERROR_A) -> Self { variant as u8 != 0 } } impl SLAVE_PECSR_PECSTS_ERROR_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> SLAVE_PECSR_PECSTS_ERROR_A { match self . bits { false => SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_CLEARED , true => SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_SET , } } # [doc = "CLEARED"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_error_cleared (& self) -> bool { * self == SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_CLEARED } # [doc = "SET"]
# [inline (always)]
pub fn is_slave_pecsr_pecsts_error_set (& self) -> bool { * self == SLAVE_PECSR_PECSTS_ERROR_A :: SLAVE_PECSR_PECSTS_ERROR_SET } } impl R { # [doc = "Bits 0:8 - This is the current PEC Byte Count of the Slave State Machine."]
# [inline (always)]
pub fn slave_pecsr_pecbytecnt (& self) -> SLAVE_PECSR_PECBYTECNT_R { SLAVE_PECSR_PECBYTECNT_R :: new ((self . bits & 0x01ff) as u16) } # [doc = "Bit 16 - This status bit indicates if the PEC was checked in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn slave_pecsr_pecsts_check (& self) -> SLAVE_PECSR_PECSTS_CHECK_R { SLAVE_PECSR_PECSTS_CHECK_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - This status bit indicates if a PEC check error occurred in the transaction that occurred before the last Stop. Latched on Stop."]
# [inline (always)]
pub fn slave_pecsr_pecsts_error (& self) -> SLAVE_PECSR_PECSTS_ERROR_R { SLAVE_PECSR_PECSTS_ERROR_R :: new (((self . bits >> 17) & 1) != 0) } } # [doc = "I2C slave PEC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave_pecsr::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SLAVE_PECSR_SPEC ; impl crate :: RegisterSpec for SLAVE_PECSR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`slave_pecsr::R`](R) reader structure"]
impl crate :: Readable for SLAVE_PECSR_SPEC { } # [doc = "`reset()` method sets SLAVE_PECSR to value 0"]
impl crate :: Resettable for SLAVE_PECSR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct IOMUX { _marker : PhantomData < * const () > } unsafe impl Send for IOMUX { } impl IOMUX { # [doc = r"Pointer to the register block"]
pub const PTR : * const iomux :: RegisterBlock = 0x4042_8000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const iomux :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for IOMUX { type Target = iomux :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for IOMUX { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("IOMUX") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod iomux { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x04]
, # [doc = "0x04..0xf8 - Pin Control Management Register in SECCFG region"]
pub pincm : [PINCM ; 61]
, } # [doc = "PINCM (rw) register accessor: Pin Control Management Register in SECCFG region\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pincm::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pincm::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pincm`]
module"]
pub type PINCM = crate :: Reg < pincm :: PINCM_SPEC > ; # [doc = "Pin Control Management Register in SECCFG region"]
pub mod pincm { # [doc = "Register `PINCM[%s]` reader"]
pub type R = crate :: R < PINCM_SPEC > ; # [doc = "Register `PINCM[%s]` writer"]
pub type W = crate :: W < PINCM_SPEC > ; # [doc = "Field `PINCM_PF` reader - P channel Function selection bits"]
pub type PINCM_PF_R = crate :: FieldReader ; # [doc = "Field `PINCM_PF` writer - P channel Function selection bits"]
pub type PINCM_PF_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 6 , O > ; # [doc = "Field `PINCM_PC` reader - Peripheral is Connected"]
pub type PINCM_PC_R = crate :: BitReader < PINCM_PC_A > ; # [doc = "Peripheral is Connected\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_PC_A { # [doc = "0: UNCONNECTED"]
PINCM_PC_UNCONNECTED = 0 , # [doc = "1: CONNECTED"]
PINCM_PC_CONNECTED = 1 , } impl From < PINCM_PC_A > for bool { # [inline (always)]
fn from (variant : PINCM_PC_A) -> Self { variant as u8 != 0 } } impl PINCM_PC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_PC_A { match self . bits { false => PINCM_PC_A :: PINCM_PC_UNCONNECTED , true => PINCM_PC_A :: PINCM_PC_CONNECTED , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_pincm_pc_unconnected (& self) -> bool { * self == PINCM_PC_A :: PINCM_PC_UNCONNECTED } # [doc = "CONNECTED"]
# [inline (always)]
pub fn is_pincm_pc_connected (& self) -> bool { * self == PINCM_PC_A :: PINCM_PC_CONNECTED } } # [doc = "Field `PINCM_PC` writer - Peripheral is Connected"]
pub type PINCM_PC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_PC_A > ; impl < 'a , REG , const O : u8 > PINCM_PC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn pincm_pc_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_PC_A :: PINCM_PC_UNCONNECTED) } # [doc = "CONNECTED"]
# [inline (always)]
pub fn pincm_pc_connected (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_PC_A :: PINCM_PC_CONNECTED) } } # [doc = "Field `PINCM_WAKESTAT` reader - This has the IOPAD WAKEUP signal as status bit."]
pub type PINCM_WAKESTAT_R = crate :: BitReader < PINCM_WAKESTAT_A > ; # [doc = "This has the IOPAD WAKEUP signal as status bit.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_WAKESTAT_A { # [doc = "0: DISABLE"]
PINCM_WAKESTAT_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_WAKESTAT_ENABLE = 1 , } impl From < PINCM_WAKESTAT_A > for bool { # [inline (always)]
fn from (variant : PINCM_WAKESTAT_A) -> Self { variant as u8 != 0 } } impl PINCM_WAKESTAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_WAKESTAT_A { match self . bits { false => PINCM_WAKESTAT_A :: PINCM_WAKESTAT_DISABLE , true => PINCM_WAKESTAT_A :: PINCM_WAKESTAT_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_wakestat_disable (& self) -> bool { * self == PINCM_WAKESTAT_A :: PINCM_WAKESTAT_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_wakestat_enable (& self) -> bool { * self == PINCM_WAKESTAT_A :: PINCM_WAKESTAT_ENABLE } } # [doc = "Field `PINCM_PIPD` reader - Pull Down control selection"]
pub type PINCM_PIPD_R = crate :: BitReader < PINCM_PIPD_A > ; # [doc = "Pull Down control selection\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_PIPD_A { # [doc = "0: DISABLE"]
PINCM_PIPD_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_PIPD_ENABLE = 1 , } impl From < PINCM_PIPD_A > for bool { # [inline (always)]
fn from (variant : PINCM_PIPD_A) -> Self { variant as u8 != 0 } } impl PINCM_PIPD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_PIPD_A { match self . bits { false => PINCM_PIPD_A :: PINCM_PIPD_DISABLE , true => PINCM_PIPD_A :: PINCM_PIPD_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_pipd_disable (& self) -> bool { * self == PINCM_PIPD_A :: PINCM_PIPD_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_pipd_enable (& self) -> bool { * self == PINCM_PIPD_A :: PINCM_PIPD_ENABLE } } # [doc = "Field `PINCM_PIPD` writer - Pull Down control selection"]
pub type PINCM_PIPD_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_PIPD_A > ; impl < 'a , REG , const O : u8 > PINCM_PIPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pincm_pipd_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_PIPD_A :: PINCM_PIPD_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pincm_pipd_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_PIPD_A :: PINCM_PIPD_ENABLE) } } # [doc = "Field `PINCM_PIPU` reader - Pull Up control selection"]
pub type PINCM_PIPU_R = crate :: BitReader < PINCM_PIPU_A > ; # [doc = "Pull Up control selection\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_PIPU_A { # [doc = "0: DISABLE"]
PINCM_PIPU_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_PIPU_ENABLE = 1 , } impl From < PINCM_PIPU_A > for bool { # [inline (always)]
fn from (variant : PINCM_PIPU_A) -> Self { variant as u8 != 0 } } impl PINCM_PIPU_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_PIPU_A { match self . bits { false => PINCM_PIPU_A :: PINCM_PIPU_DISABLE , true => PINCM_PIPU_A :: PINCM_PIPU_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_pipu_disable (& self) -> bool { * self == PINCM_PIPU_A :: PINCM_PIPU_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_pipu_enable (& self) -> bool { * self == PINCM_PIPU_A :: PINCM_PIPU_ENABLE } } # [doc = "Field `PINCM_PIPU` writer - Pull Up control selection"]
pub type PINCM_PIPU_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_PIPU_A > ; impl < 'a , REG , const O : u8 > PINCM_PIPU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pincm_pipu_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_PIPU_A :: PINCM_PIPU_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pincm_pipu_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_PIPU_A :: PINCM_PIPU_ENABLE) } } # [doc = "Field `PINCM_INENA` reader - Input Enable Control Selection"]
pub type PINCM_INENA_R = crate :: BitReader < PINCM_INENA_A > ; # [doc = "Input Enable Control Selection\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_INENA_A { # [doc = "0: DISABLE"]
PINCM_INENA_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_INENA_ENABLE = 1 , } impl From < PINCM_INENA_A > for bool { # [inline (always)]
fn from (variant : PINCM_INENA_A) -> Self { variant as u8 != 0 } } impl PINCM_INENA_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_INENA_A { match self . bits { false => PINCM_INENA_A :: PINCM_INENA_DISABLE , true => PINCM_INENA_A :: PINCM_INENA_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_inena_disable (& self) -> bool { * self == PINCM_INENA_A :: PINCM_INENA_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_inena_enable (& self) -> bool { * self == PINCM_INENA_A :: PINCM_INENA_ENABLE } } # [doc = "Field `PINCM_INENA` writer - Input Enable Control Selection"]
pub type PINCM_INENA_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_INENA_A > ; impl < 'a , REG , const O : u8 > PINCM_INENA_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pincm_inena_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_INENA_A :: PINCM_INENA_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pincm_inena_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_INENA_A :: PINCM_INENA_ENABLE) } } # [doc = "Field `PINCM_HYSTEN` reader - Hystersis Enable Control Selection"]
pub type PINCM_HYSTEN_R = crate :: BitReader < PINCM_HYSTEN_A > ; # [doc = "Hystersis Enable Control Selection\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_HYSTEN_A { # [doc = "0: DISABLE"]
PINCM_HYSTEN_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_HYSTEN_ENABLE = 1 , } impl From < PINCM_HYSTEN_A > for bool { # [inline (always)]
fn from (variant : PINCM_HYSTEN_A) -> Self { variant as u8 != 0 } } impl PINCM_HYSTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_HYSTEN_A { match self . bits { false => PINCM_HYSTEN_A :: PINCM_HYSTEN_DISABLE , true => PINCM_HYSTEN_A :: PINCM_HYSTEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_hysten_disable (& self) -> bool { * self == PINCM_HYSTEN_A :: PINCM_HYSTEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_hysten_enable (& self) -> bool { * self == PINCM_HYSTEN_A :: PINCM_HYSTEN_ENABLE } } # [doc = "Field `PINCM_HYSTEN` writer - Hystersis Enable Control Selection"]
pub type PINCM_HYSTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_HYSTEN_A > ; impl < 'a , REG , const O : u8 > PINCM_HYSTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pincm_hysten_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_HYSTEN_A :: PINCM_HYSTEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pincm_hysten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_HYSTEN_A :: PINCM_HYSTEN_ENABLE) } } # [doc = "Field `PINCM_DRV` reader - Drive strength control selection, for HS IOCELL only"]
pub type PINCM_DRV_R = crate :: BitReader < PINCM_DRV_A > ; # [doc = "Drive strength control selection, for HS IOCELL only\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_DRV_A { # [doc = "0: DRVVAL0"]
PINCM_DRV_DRVVAL0 = 0 , # [doc = "1: DRVVAL1"]
PINCM_DRV_DRVVAL1 = 1 , } impl From < PINCM_DRV_A > for bool { # [inline (always)]
fn from (variant : PINCM_DRV_A) -> Self { variant as u8 != 0 } } impl PINCM_DRV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_DRV_A { match self . bits { false => PINCM_DRV_A :: PINCM_DRV_DRVVAL0 , true => PINCM_DRV_A :: PINCM_DRV_DRVVAL1 , } } # [doc = "DRVVAL0"]
# [inline (always)]
pub fn is_pincm_drv_drvval0 (& self) -> bool { * self == PINCM_DRV_A :: PINCM_DRV_DRVVAL0 } # [doc = "DRVVAL1"]
# [inline (always)]
pub fn is_pincm_drv_drvval1 (& self) -> bool { * self == PINCM_DRV_A :: PINCM_DRV_DRVVAL1 } } # [doc = "Field `PINCM_DRV` writer - Drive strength control selection, for HS IOCELL only"]
pub type PINCM_DRV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_DRV_A > ; impl < 'a , REG , const O : u8 > PINCM_DRV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DRVVAL0"]
# [inline (always)]
pub fn pincm_drv_drvval0 (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_DRV_A :: PINCM_DRV_DRVVAL0) } # [doc = "DRVVAL1"]
# [inline (always)]
pub fn pincm_drv_drvval1 (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_DRV_A :: PINCM_DRV_DRVVAL1) } } # [doc = "Field `PINCM_HIZ1` reader - High output value will tri-state the output when this bit is enabled"]
pub type PINCM_HIZ1_R = crate :: BitReader < PINCM_HIZ1_A > ; # [doc = "High output value will tri-state the output when this bit is enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_HIZ1_A { # [doc = "0: DISABLE"]
PINCM_HIZ1_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_HIZ1_ENABLE = 1 , } impl From < PINCM_HIZ1_A > for bool { # [inline (always)]
fn from (variant : PINCM_HIZ1_A) -> Self { variant as u8 != 0 } } impl PINCM_HIZ1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_HIZ1_A { match self . bits { false => PINCM_HIZ1_A :: PINCM_HIZ1_DISABLE , true => PINCM_HIZ1_A :: PINCM_HIZ1_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_hiz1_disable (& self) -> bool { * self == PINCM_HIZ1_A :: PINCM_HIZ1_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_hiz1_enable (& self) -> bool { * self == PINCM_HIZ1_A :: PINCM_HIZ1_ENABLE } } # [doc = "Field `PINCM_HIZ1` writer - High output value will tri-state the output when this bit is enabled"]
pub type PINCM_HIZ1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_HIZ1_A > ; impl < 'a , REG , const O : u8 > PINCM_HIZ1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pincm_hiz1_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_HIZ1_A :: PINCM_HIZ1_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pincm_hiz1_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_HIZ1_A :: PINCM_HIZ1_ENABLE) } } # [doc = "Field `PINCM_INV` reader - Data inversion selection"]
pub type PINCM_INV_R = crate :: BitReader < PINCM_INV_A > ; # [doc = "Data inversion selection\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_INV_A { # [doc = "0: DISABLE"]
PINCM_INV_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_INV_ENABLE = 1 , } impl From < PINCM_INV_A > for bool { # [inline (always)]
fn from (variant : PINCM_INV_A) -> Self { variant as u8 != 0 } } impl PINCM_INV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_INV_A { match self . bits { false => PINCM_INV_A :: PINCM_INV_DISABLE , true => PINCM_INV_A :: PINCM_INV_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_inv_disable (& self) -> bool { * self == PINCM_INV_A :: PINCM_INV_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_inv_enable (& self) -> bool { * self == PINCM_INV_A :: PINCM_INV_ENABLE } } # [doc = "Field `PINCM_INV` writer - Data inversion selection"]
pub type PINCM_INV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_INV_A > ; impl < 'a , REG , const O : u8 > PINCM_INV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pincm_inv_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_INV_A :: PINCM_INV_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pincm_inv_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_INV_A :: PINCM_INV_ENABLE) } } # [doc = "Field `PINCM_WUEN` reader - Wakeup Enable bit"]
pub type PINCM_WUEN_R = crate :: BitReader < PINCM_WUEN_A > ; # [doc = "Wakeup Enable bit\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_WUEN_A { # [doc = "0: DISABLE"]
PINCM_WUEN_DISABLE = 0 , # [doc = "1: ENABLE"]
PINCM_WUEN_ENABLE = 1 , } impl From < PINCM_WUEN_A > for bool { # [inline (always)]
fn from (variant : PINCM_WUEN_A) -> Self { variant as u8 != 0 } } impl PINCM_WUEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_WUEN_A { match self . bits { false => PINCM_WUEN_A :: PINCM_WUEN_DISABLE , true => PINCM_WUEN_A :: PINCM_WUEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pincm_wuen_disable (& self) -> bool { * self == PINCM_WUEN_A :: PINCM_WUEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pincm_wuen_enable (& self) -> bool { * self == PINCM_WUEN_A :: PINCM_WUEN_ENABLE } } # [doc = "Field `PINCM_WUEN` writer - Wakeup Enable bit"]
pub type PINCM_WUEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_WUEN_A > ; impl < 'a , REG , const O : u8 > PINCM_WUEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pincm_wuen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_WUEN_A :: PINCM_WUEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pincm_wuen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_WUEN_A :: PINCM_WUEN_ENABLE) } } # [doc = "Field `PINCM_WCOMP` reader - Wakeup Compare Value bit"]
pub type PINCM_WCOMP_R = crate :: BitReader < PINCM_WCOMP_A > ; # [doc = "Wakeup Compare Value bit\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PINCM_WCOMP_A { # [doc = "0: MATCH0"]
PINCM_WCOMP_MATCH0 = 0 , # [doc = "1: MATCH1"]
PINCM_WCOMP_MATCH1 = 1 , } impl From < PINCM_WCOMP_A > for bool { # [inline (always)]
fn from (variant : PINCM_WCOMP_A) -> Self { variant as u8 != 0 } } impl PINCM_WCOMP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PINCM_WCOMP_A { match self . bits { false => PINCM_WCOMP_A :: PINCM_WCOMP_MATCH0 , true => PINCM_WCOMP_A :: PINCM_WCOMP_MATCH1 , } } # [doc = "MATCH0"]
# [inline (always)]
pub fn is_pincm_wcomp_match0 (& self) -> bool { * self == PINCM_WCOMP_A :: PINCM_WCOMP_MATCH0 } # [doc = "MATCH1"]
# [inline (always)]
pub fn is_pincm_wcomp_match1 (& self) -> bool { * self == PINCM_WCOMP_A :: PINCM_WCOMP_MATCH1 } } # [doc = "Field `PINCM_WCOMP` writer - Wakeup Compare Value bit"]
pub type PINCM_WCOMP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PINCM_WCOMP_A > ; impl < 'a , REG , const O : u8 > PINCM_WCOMP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "MATCH0"]
# [inline (always)]
pub fn pincm_wcomp_match0 (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_WCOMP_A :: PINCM_WCOMP_MATCH0) } # [doc = "MATCH1"]
# [inline (always)]
pub fn pincm_wcomp_match1 (self) -> & 'a mut crate :: W < REG > { self . variant (PINCM_WCOMP_A :: PINCM_WCOMP_MATCH1) } } impl R { # [doc = "Bits 0:5 - P channel Function selection bits"]
# [inline (always)]
pub fn pincm_pf (& self) -> PINCM_PF_R { PINCM_PF_R :: new ((self . bits & 0x3f) as u8) } # [doc = "Bit 7 - Peripheral is Connected"]
# [inline (always)]
pub fn pincm_pc (& self) -> PINCM_PC_R { PINCM_PC_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bit 13 - This has the IOPAD WAKEUP signal as status bit."]
# [inline (always)]
pub fn pincm_wakestat (& self) -> PINCM_WAKESTAT_R { PINCM_WAKESTAT_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 16 - Pull Down control selection"]
# [inline (always)]
pub fn pincm_pipd (& self) -> PINCM_PIPD_R { PINCM_PIPD_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 17 - Pull Up control selection"]
# [inline (always)]
pub fn pincm_pipu (& self) -> PINCM_PIPU_R { PINCM_PIPU_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bit 18 - Input Enable Control Selection"]
# [inline (always)]
pub fn pincm_inena (& self) -> PINCM_INENA_R { PINCM_INENA_R :: new (((self . bits >> 18) & 1) != 0) } # [doc = "Bit 19 - Hystersis Enable Control Selection"]
# [inline (always)]
pub fn pincm_hysten (& self) -> PINCM_HYSTEN_R { PINCM_HYSTEN_R :: new (((self . bits >> 19) & 1) != 0) } # [doc = "Bit 20 - Drive strength control selection, for HS IOCELL only"]
# [inline (always)]
pub fn pincm_drv (& self) -> PINCM_DRV_R { PINCM_DRV_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 25 - High output value will tri-state the output when this bit is enabled"]
# [inline (always)]
pub fn pincm_hiz1 (& self) -> PINCM_HIZ1_R { PINCM_HIZ1_R :: new (((self . bits >> 25) & 1) != 0) } # [doc = "Bit 26 - Data inversion selection"]
# [inline (always)]
pub fn pincm_inv (& self) -> PINCM_INV_R { PINCM_INV_R :: new (((self . bits >> 26) & 1) != 0) } # [doc = "Bit 27 - Wakeup Enable bit"]
# [inline (always)]
pub fn pincm_wuen (& self) -> PINCM_WUEN_R { PINCM_WUEN_R :: new (((self . bits >> 27) & 1) != 0) } # [doc = "Bit 28 - Wakeup Compare Value bit"]
# [inline (always)]
pub fn pincm_wcomp (& self) -> PINCM_WCOMP_R { PINCM_WCOMP_R :: new (((self . bits >> 28) & 1) != 0) } } impl W { # [doc = "Bits 0:5 - P channel Function selection bits"]
# [inline (always)]
# [must_use]
pub fn pincm_pf (& mut self) -> PINCM_PF_W < PINCM_SPEC , 0 > { PINCM_PF_W :: new (self) } # [doc = "Bit 7 - Peripheral is Connected"]
# [inline (always)]
# [must_use]
pub fn pincm_pc (& mut self) -> PINCM_PC_W < PINCM_SPEC , 7 > { PINCM_PC_W :: new (self) } # [doc = "Bit 16 - Pull Down control selection"]
# [inline (always)]
# [must_use]
pub fn pincm_pipd (& mut self) -> PINCM_PIPD_W < PINCM_SPEC , 16 > { PINCM_PIPD_W :: new (self) } # [doc = "Bit 17 - Pull Up control selection"]
# [inline (always)]
# [must_use]
pub fn pincm_pipu (& mut self) -> PINCM_PIPU_W < PINCM_SPEC , 17 > { PINCM_PIPU_W :: new (self) } # [doc = "Bit 18 - Input Enable Control Selection"]
# [inline (always)]
# [must_use]
pub fn pincm_inena (& mut self) -> PINCM_INENA_W < PINCM_SPEC , 18 > { PINCM_INENA_W :: new (self) } # [doc = "Bit 19 - Hystersis Enable Control Selection"]
# [inline (always)]
# [must_use]
pub fn pincm_hysten (& mut self) -> PINCM_HYSTEN_W < PINCM_SPEC , 19 > { PINCM_HYSTEN_W :: new (self) } # [doc = "Bit 20 - Drive strength control selection, for HS IOCELL only"]
# [inline (always)]
# [must_use]
pub fn pincm_drv (& mut self) -> PINCM_DRV_W < PINCM_SPEC , 20 > { PINCM_DRV_W :: new (self) } # [doc = "Bit 25 - High output value will tri-state the output when this bit is enabled"]
# [inline (always)]
# [must_use]
pub fn pincm_hiz1 (& mut self) -> PINCM_HIZ1_W < PINCM_SPEC , 25 > { PINCM_HIZ1_W :: new (self) } # [doc = "Bit 26 - Data inversion selection"]
# [inline (always)]
# [must_use]
pub fn pincm_inv (& mut self) -> PINCM_INV_W < PINCM_SPEC , 26 > { PINCM_INV_W :: new (self) } # [doc = "Bit 27 - Wakeup Enable bit"]
# [inline (always)]
# [must_use]
pub fn pincm_wuen (& mut self) -> PINCM_WUEN_W < PINCM_SPEC , 27 > { PINCM_WUEN_W :: new (self) } # [doc = "Bit 28 - Wakeup Compare Value bit"]
# [inline (always)]
# [must_use]
pub fn pincm_wcomp (& mut self) -> PINCM_WCOMP_W < PINCM_SPEC , 28 > { PINCM_WCOMP_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Pin Control Management Register in SECCFG region\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pincm::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pincm::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PINCM_SPEC ; impl crate :: RegisterSpec for PINCM_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pincm::R`](R) reader structure"]
impl crate :: Readable for PINCM_SPEC { } # [doc = "`write(|w| ..)` method takes [`pincm::W`](W) writer structure"]
impl crate :: Writable for PINCM_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PINCM[%s]
to value 0"]
impl crate :: Resettable for PINCM_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct TIMG2 { _marker : PhantomData < * const () > } unsafe impl Send for TIMG2 { } impl TIMG2 { # [doc = r"Pointer to the register block"]
pub const PTR : * const timg2 :: RegisterBlock = 0x4008_8000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const timg2 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIMG2 { type Target = timg2 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIMG2 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIMG2") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod timg2 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subsciber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , _reserved2 : [u8 ; 0x3c]
, # [doc = "0x444 - Publisher Port 0"]
pub fpub_0 : FPUB_0 , # [doc = "0x448 - Publisher Port 1"]
pub fpub_1 : FPUB_1 , _reserved4 : [u8 ; 0x03b4]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved6 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved7 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1008 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved9 : [u8 ; 0x0c]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved16 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved17 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - CCP Direction"]
pub ccpd : CCPD , # [doc = "0x1104 - Output Disable"]
pub odis : ODIS , # [doc = "0x1108 - Counter Clock Control Register"]
pub cclkctl : CCLKCTL , # [doc = "0x110c - Clock Prescale Register"]
pub cps : CPS , # [doc = "0x1110 - Clock prescale count status register"]
pub cpsv : CPSV , # [doc = "0x1114 - Timer Cross Trigger Control Register"]
pub cttrigctl : CTTRIGCTL , _reserved24 : [u8 ; 0x04]
, # [doc = "0x111c - Timer Cross Trigger Register"]
pub cttrig : CTTRIG , _reserved25 : [u8 ; 0x06e0]
, # [doc = "0x1800 - Counter Register"]
pub ctr : CTR , # [doc = "0x1804 - Counter Control Register"]
pub ctrctl : CTRCTL , # [doc = "0x1808 - Load Register"]
pub load : LOAD , _reserved28 : [u8 ; 0x04]
, # [doc = "0x1810..0x1818 - Capture or Compare Register 0 to Capture or Compare Register 1"]
pub cc_01 : [CC_01 ; 2]
, _reserved29 : [u8 ; 0x18]
, # [doc = "0x1830..0x1838 - Capture or Compare Control Registers"]
pub ccctl_01 : [CCCTL_01 ; 2]
, _reserved30 : [u8 ; 0x18]
, # [doc = "0x1850..0x1858 - CCP Output Control Registers"]
pub octl_01 : [OCTL_01 ; 2]
, _reserved31 : [u8 ; 0x18]
, # [doc = "0x1870..0x1878 - Capture or Compare Action Registers"]
pub ccact_01 : [CCACT_01 ; 2]
, _reserved32 : [u8 ; 0x08]
, # [doc = "0x1880..0x1888 - Input Filter Control Register"]
pub ifctl_01 : [IFCTL_01 ; 2]
, _reserved33 : [u8 ; 0x28]
, # [doc = "0x18b0 - Trigger Select"]
pub tsel : TSEL , } # [doc = "FSUB_0 (rw) register accessor: Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subsciber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_0 (rw) register accessor: Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_0`]
module"]
pub type FPUB_0 = crate :: Reg < fpub_0 :: FPUB_0_SPEC > ; # [doc = "Publisher Port 0"]
pub mod fpub_0 { # [doc = "Register `FPUB_0` reader"]
pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"]
pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"]
impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"]
impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"]
impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher Port 1"]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Interrupt index status"]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: Z"]
IIDX_STAT_Z = 1 , # [doc = "2: L"]
IIDX_STAT_L = 2 , # [doc = "5: CCD0"]
IIDX_STAT_CCD0 = 5 , # [doc = "6: CCD1"]
IIDX_STAT_CCD1 = 6 , # [doc = "7: CCD2"]
IIDX_STAT_CCD2 = 7 , # [doc = "8: CCD3"]
IIDX_STAT_CCD3 = 8 , # [doc = "9: CCU0"]
IIDX_STAT_CCU0 = 9 , # [doc = "10: CCU1"]
IIDX_STAT_CCU1 = 10 , # [doc = "11: CCU2"]
IIDX_STAT_CCU2 = 11 , # [doc = "12: CCU3"]
IIDX_STAT_CCU3 = 12 , # [doc = "13: CCD4"]
IIDX_STAT_CCD4 = 13 , # [doc = "14: CCD5"]
IIDX_STAT_CCD5 = 14 , # [doc = "15: CCU4"]
IIDX_STAT_CCU4 = 15 , # [doc = "16: CCU5"]
IIDX_STAT_CCU5 = 16 , # [doc = "25: F"]
IIDX_STAT_F = 25 , # [doc = "26: TOV"]
IIDX_STAT_TOV = 26 , # [doc = "27: REPC"]
IIDX_STAT_REPC = 27 , # [doc = "28: DC"]
IIDX_STAT_DC = 28 , # [doc = "29: QEIERR"]
IIDX_STAT_QEIERR = 29 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_Z) , 2 => Some (IIDX_STAT_A :: IIDX_STAT_L) , 5 => Some (IIDX_STAT_A :: IIDX_STAT_CCD0) , 6 => Some (IIDX_STAT_A :: IIDX_STAT_CCD1) , 7 => Some (IIDX_STAT_A :: IIDX_STAT_CCD2) , 8 => Some (IIDX_STAT_A :: IIDX_STAT_CCD3) , 9 => Some (IIDX_STAT_A :: IIDX_STAT_CCU0) , 10 => Some (IIDX_STAT_A :: IIDX_STAT_CCU1) , 11 => Some (IIDX_STAT_A :: IIDX_STAT_CCU2) , 12 => Some (IIDX_STAT_A :: IIDX_STAT_CCU3) , 13 => Some (IIDX_STAT_A :: IIDX_STAT_CCD4) , 14 => Some (IIDX_STAT_A :: IIDX_STAT_CCD5) , 15 => Some (IIDX_STAT_A :: IIDX_STAT_CCU4) , 16 => Some (IIDX_STAT_A :: IIDX_STAT_CCU5) , 25 => Some (IIDX_STAT_A :: IIDX_STAT_F) , 26 => Some (IIDX_STAT_A :: IIDX_STAT_TOV) , 27 => Some (IIDX_STAT_A :: IIDX_STAT_REPC) , 28 => Some (IIDX_STAT_A :: IIDX_STAT_DC) , 29 => Some (IIDX_STAT_A :: IIDX_STAT_QEIERR) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "Z"]
# [inline (always)]
pub fn is_iidx_stat_z (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_Z } # [doc = "L"]
# [inline (always)]
pub fn is_iidx_stat_l (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_iidx_stat_ccd0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_iidx_stat_ccd1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_iidx_stat_ccd2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_iidx_stat_ccd3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_iidx_stat_ccu0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_iidx_stat_ccu1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_iidx_stat_ccu2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_iidx_stat_ccu3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU3 } # [doc = "CCD4"]
# [inline (always)]
pub fn is_iidx_stat_ccd4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD4 } # [doc = "CCD5"]
# [inline (always)]
pub fn is_iidx_stat_ccd5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD5 } # [doc = "CCU4"]
# [inline (always)]
pub fn is_iidx_stat_ccu4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU4 } # [doc = "CCU5"]
# [inline (always)]
pub fn is_iidx_stat_ccu5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU5 } # [doc = "F"]
# [inline (always)]
pub fn is_iidx_stat_f (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_F } # [doc = "TOV"]
# [inline (always)]
pub fn is_iidx_stat_tov (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_TOV } # [doc = "REPC"]
# [inline (always)]
pub fn is_iidx_stat_repc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_REPC } # [doc = "DC"]
# [inline (always)]
pub fn is_iidx_stat_dc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DC } # [doc = "QEIERR"]
# [inline (always)]
pub fn is_iidx_stat_qeierr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_QEIERR } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_Z` reader - Zero Event mask"]
pub type IMASK_Z_R = crate :: BitReader < IMASK_Z_A > ; # [doc = "Zero Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_Z_A { # [doc = "0: CLR"]
IMASK_Z_CLR = 0 , # [doc = "1: SET"]
IMASK_Z_SET = 1 , } impl From < IMASK_Z_A > for bool { # [inline (always)]
fn from (variant : IMASK_Z_A) -> Self { variant as u8 != 0 } } impl IMASK_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_Z_A { match self . bits { false => IMASK_Z_A :: IMASK_Z_CLR , true => IMASK_Z_A :: IMASK_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_z_clr (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_z_set (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_SET } } # [doc = "Field `IMASK_Z` writer - Zero Event mask"]
pub type IMASK_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_Z_A > ; impl < 'a , REG , const O : u8 > IMASK_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_SET) } } # [doc = "Field `IMASK_L` reader - Load Event mask"]
pub type IMASK_L_R = crate :: BitReader < IMASK_L_A > ; # [doc = "Load Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_L_A { # [doc = "0: CLR"]
IMASK_L_CLR = 0 , # [doc = "1: SET"]
IMASK_L_SET = 1 , } impl From < IMASK_L_A > for bool { # [inline (always)]
fn from (variant : IMASK_L_A) -> Self { variant as u8 != 0 } } impl IMASK_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_L_A { match self . bits { false => IMASK_L_A :: IMASK_L_CLR , true => IMASK_L_A :: IMASK_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_l_clr (& self) -> bool { * self == IMASK_L_A :: IMASK_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_l_set (& self) -> bool { * self == IMASK_L_A :: IMASK_L_SET } } # [doc = "Field `IMASK_L` writer - Load Event mask"]
pub type IMASK_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_L_A > ; impl < 'a , REG , const O : u8 > IMASK_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_SET) } } # [doc = "Field `IMASK_CCD0` reader - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_R = crate :: BitReader < IMASK_CCD0_A > ; # [doc = "Capture or Compare DN event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD0_A { # [doc = "0: CLR"]
IMASK_CCD0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD0_SET = 1 , } impl From < IMASK_CCD0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD0_A { match self . bits { false => IMASK_CCD0_A :: IMASK_CCD0_CLR , true => IMASK_CCD0_A :: IMASK_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd0_clr (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd0_set (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_SET } } # [doc = "Field `IMASK_CCD0` writer - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_SET) } } # [doc = "Field `IMASK_CCD1` reader - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_R = crate :: BitReader < IMASK_CCD1_A > ; # [doc = "Capture or Compare DN event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD1_A { # [doc = "0: CLR"]
IMASK_CCD1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD1_SET = 1 , } impl From < IMASK_CCD1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD1_A { match self . bits { false => IMASK_CCD1_A :: IMASK_CCD1_CLR , true => IMASK_CCD1_A :: IMASK_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd1_clr (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd1_set (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_SET } } # [doc = "Field `IMASK_CCD1` writer - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_SET) } } # [doc = "Field `IMASK_CCU0` reader - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_R = crate :: BitReader < IMASK_CCU0_A > ; # [doc = "Capture or Compare UP event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU0_A { # [doc = "0: CLR"]
IMASK_CCU0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU0_SET = 1 , } impl From < IMASK_CCU0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU0_A { match self . bits { false => IMASK_CCU0_A :: IMASK_CCU0_CLR , true => IMASK_CCU0_A :: IMASK_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu0_clr (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu0_set (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_SET } } # [doc = "Field `IMASK_CCU0` writer - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_SET) } } # [doc = "Field `IMASK_CCU1` reader - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_R = crate :: BitReader < IMASK_CCU1_A > ; # [doc = "Capture or Compare UP event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU1_A { # [doc = "0: CLR"]
IMASK_CCU1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU1_SET = 1 , } impl From < IMASK_CCU1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU1_A { match self . bits { false => IMASK_CCU1_A :: IMASK_CCU1_CLR , true => IMASK_CCU1_A :: IMASK_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu1_clr (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu1_set (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_SET } } # [doc = "Field `IMASK_CCU1` writer - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_SET) } } # [doc = "Field `IMASK_TOV` reader - Trigger Overflow Event mask"]
pub type IMASK_TOV_R = crate :: BitReader < IMASK_TOV_A > ; # [doc = "Trigger Overflow Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_TOV_A { # [doc = "0: CLR"]
IMASK_TOV_CLR = 0 , # [doc = "1: SET"]
IMASK_TOV_SET = 1 , } impl From < IMASK_TOV_A > for bool { # [inline (always)]
fn from (variant : IMASK_TOV_A) -> Self { variant as u8 != 0 } } impl IMASK_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_TOV_A { match self . bits { false => IMASK_TOV_A :: IMASK_TOV_CLR , true => IMASK_TOV_A :: IMASK_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_tov_clr (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_tov_set (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_SET } } # [doc = "Field `IMASK_TOV` writer - Trigger Overflow Event mask"]
pub type IMASK_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TOV_A > ; impl < 'a , REG , const O : u8 > IMASK_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_SET) } } impl R { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
pub fn imask_z (& self) -> IMASK_Z_R { IMASK_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
pub fn imask_l (& self) -> IMASK_L_R { IMASK_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
pub fn imask_ccd0 (& self) -> IMASK_CCD0_R { IMASK_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
pub fn imask_ccd1 (& self) -> IMASK_CCD1_R { IMASK_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
pub fn imask_ccu0 (& self) -> IMASK_CCU0_R { IMASK_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
pub fn imask_ccu1 (& self) -> IMASK_CCU1_R { IMASK_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
pub fn imask_tov (& self) -> IMASK_TOV_R { IMASK_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_z (& mut self) -> IMASK_Z_W < IMASK_SPEC , 0 > { IMASK_Z_W :: new (self) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_l (& mut self) -> IMASK_L_W < IMASK_SPEC , 1 > { IMASK_L_W :: new (self) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccd0 (& mut self) -> IMASK_CCD0_W < IMASK_SPEC , 4 > { IMASK_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccd1 (& mut self) -> IMASK_CCD1_W < IMASK_SPEC , 5 > { IMASK_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccu0 (& mut self) -> IMASK_CCU0_W < IMASK_SPEC , 8 > { IMASK_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccu1 (& mut self) -> IMASK_CCU1_W < IMASK_SPEC , 9 > { IMASK_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_tov (& mut self) -> IMASK_TOV_W < IMASK_SPEC , 25 > { IMASK_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_Z` reader - Zero event generated an interrupt."]
pub type RIS_Z_R = crate :: BitReader < RIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_Z_A { # [doc = "0: CLR"]
RIS_Z_CLR = 0 , # [doc = "1: SET"]
RIS_Z_SET = 1 , } impl From < RIS_Z_A > for bool { # [inline (always)]
fn from (variant : RIS_Z_A) -> Self { variant as u8 != 0 } } impl RIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_Z_A { match self . bits { false => RIS_Z_A :: RIS_Z_CLR , true => RIS_Z_A :: RIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_z_clr (& self) -> bool { * self == RIS_Z_A :: RIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_z_set (& self) -> bool { * self == RIS_Z_A :: RIS_Z_SET } } # [doc = "Field `RIS_L` reader - Load event generated an interrupt."]
pub type RIS_L_R = crate :: BitReader < RIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_L_A { # [doc = "0: CLR"]
RIS_L_CLR = 0 , # [doc = "1: SET"]
RIS_L_SET = 1 , } impl From < RIS_L_A > for bool { # [inline (always)]
fn from (variant : RIS_L_A) -> Self { variant as u8 != 0 } } impl RIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_L_A { match self . bits { false => RIS_L_A :: RIS_L_CLR , true => RIS_L_A :: RIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_l_clr (& self) -> bool { * self == RIS_L_A :: RIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_l_set (& self) -> bool { * self == RIS_L_A :: RIS_L_SET } } # [doc = "Field `RIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type RIS_CCD0_R = crate :: BitReader < RIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD0_A { # [doc = "0: CLR"]
RIS_CCD0_CLR = 0 , # [doc = "1: SET"]
RIS_CCD0_SET = 1 , } impl From < RIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD0_A) -> Self { variant as u8 != 0 } } impl RIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD0_A { match self . bits { false => RIS_CCD0_A :: RIS_CCD0_CLR , true => RIS_CCD0_A :: RIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd0_clr (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd0_set (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_SET } } # [doc = "Field `RIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type RIS_CCD1_R = crate :: BitReader < RIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD1_A { # [doc = "0: CLR"]
RIS_CCD1_CLR = 0 , # [doc = "1: SET"]
RIS_CCD1_SET = 1 , } impl From < RIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD1_A) -> Self { variant as u8 != 0 } } impl RIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD1_A { match self . bits { false => RIS_CCD1_A :: RIS_CCD1_CLR , true => RIS_CCD1_A :: RIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd1_clr (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd1_set (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_SET } } # [doc = "Field `RIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type RIS_CCU0_R = crate :: BitReader < RIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU0_A { # [doc = "0: CLR"]
RIS_CCU0_CLR = 0 , # [doc = "1: SET"]
RIS_CCU0_SET = 1 , } impl From < RIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU0_A) -> Self { variant as u8 != 0 } } impl RIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU0_A { match self . bits { false => RIS_CCU0_A :: RIS_CCU0_CLR , true => RIS_CCU0_A :: RIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu0_clr (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu0_set (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_SET } } # [doc = "Field `RIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type RIS_CCU1_R = crate :: BitReader < RIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU1_A { # [doc = "0: CLR"]
RIS_CCU1_CLR = 0 , # [doc = "1: SET"]
RIS_CCU1_SET = 1 , } impl From < RIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU1_A) -> Self { variant as u8 != 0 } } impl RIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU1_A { match self . bits { false => RIS_CCU1_A :: RIS_CCU1_CLR , true => RIS_CCU1_A :: RIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu1_clr (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu1_set (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_SET } } # [doc = "Field `RIS_TOV` reader - Trigger overflow"]
pub type RIS_TOV_R = crate :: BitReader < RIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_TOV_A { # [doc = "0: CLR"]
RIS_TOV_CLR = 0 , # [doc = "1: SET"]
RIS_TOV_SET = 1 , } impl From < RIS_TOV_A > for bool { # [inline (always)]
fn from (variant : RIS_TOV_A) -> Self { variant as u8 != 0 } } impl RIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_TOV_A { match self . bits { false => RIS_TOV_A :: RIS_TOV_CLR , true => RIS_TOV_A :: RIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_tov_clr (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_tov_set (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn ris_z (& self) -> RIS_Z_R { RIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn ris_l (& self) -> RIS_L_R { RIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccd0 (& self) -> RIS_CCD0_R { RIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccd1 (& self) -> RIS_CCD1_R { RIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccu0 (& self) -> RIS_CCU0_R { RIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccu1 (& self) -> RIS_CCU1_R { RIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn ris_tov (& self) -> RIS_TOV_R { RIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_Z` reader - Zero event generated an interrupt."]
pub type MIS_Z_R = crate :: BitReader < MIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_Z_A { # [doc = "0: CLR"]
MIS_Z_CLR = 0 , # [doc = "1: SET"]
MIS_Z_SET = 1 , } impl From < MIS_Z_A > for bool { # [inline (always)]
fn from (variant : MIS_Z_A) -> Self { variant as u8 != 0 } } impl MIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_Z_A { match self . bits { false => MIS_Z_A :: MIS_Z_CLR , true => MIS_Z_A :: MIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_z_clr (& self) -> bool { * self == MIS_Z_A :: MIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_z_set (& self) -> bool { * self == MIS_Z_A :: MIS_Z_SET } } # [doc = "Field `MIS_L` reader - Load event generated an interrupt."]
pub type MIS_L_R = crate :: BitReader < MIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_L_A { # [doc = "0: CLR"]
MIS_L_CLR = 0 , # [doc = "1: SET"]
MIS_L_SET = 1 , } impl From < MIS_L_A > for bool { # [inline (always)]
fn from (variant : MIS_L_A) -> Self { variant as u8 != 0 } } impl MIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_L_A { match self . bits { false => MIS_L_A :: MIS_L_CLR , true => MIS_L_A :: MIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_l_clr (& self) -> bool { * self == MIS_L_A :: MIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_l_set (& self) -> bool { * self == MIS_L_A :: MIS_L_SET } } # [doc = "Field `MIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type MIS_CCD0_R = crate :: BitReader < MIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD0_A { # [doc = "0: CLR"]
MIS_CCD0_CLR = 0 , # [doc = "1: SET"]
MIS_CCD0_SET = 1 , } impl From < MIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD0_A) -> Self { variant as u8 != 0 } } impl MIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD0_A { match self . bits { false => MIS_CCD0_A :: MIS_CCD0_CLR , true => MIS_CCD0_A :: MIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd0_clr (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd0_set (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_SET } } # [doc = "Field `MIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type MIS_CCD1_R = crate :: BitReader < MIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD1_A { # [doc = "0: CLR"]
MIS_CCD1_CLR = 0 , # [doc = "1: SET"]
MIS_CCD1_SET = 1 , } impl From < MIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD1_A) -> Self { variant as u8 != 0 } } impl MIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD1_A { match self . bits { false => MIS_CCD1_A :: MIS_CCD1_CLR , true => MIS_CCD1_A :: MIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd1_clr (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd1_set (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_SET } } # [doc = "Field `MIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type MIS_CCU0_R = crate :: BitReader < MIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU0_A { # [doc = "0: CLR"]
MIS_CCU0_CLR = 0 , # [doc = "1: SET"]
MIS_CCU0_SET = 1 , } impl From < MIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU0_A) -> Self { variant as u8 != 0 } } impl MIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU0_A { match self . bits { false => MIS_CCU0_A :: MIS_CCU0_CLR , true => MIS_CCU0_A :: MIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu0_clr (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu0_set (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_SET } } # [doc = "Field `MIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type MIS_CCU1_R = crate :: BitReader < MIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU1_A { # [doc = "0: CLR"]
MIS_CCU1_CLR = 0 , # [doc = "1: SET"]
MIS_CCU1_SET = 1 , } impl From < MIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU1_A) -> Self { variant as u8 != 0 } } impl MIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU1_A { match self . bits { false => MIS_CCU1_A :: MIS_CCU1_CLR , true => MIS_CCU1_A :: MIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu1_clr (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu1_set (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_SET } } # [doc = "Field `MIS_TOV` reader - Trigger overflow"]
pub type MIS_TOV_R = crate :: BitReader < MIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_TOV_A { # [doc = "0: CLR"]
MIS_TOV_CLR = 0 , # [doc = "1: SET"]
MIS_TOV_SET = 1 , } impl From < MIS_TOV_A > for bool { # [inline (always)]
fn from (variant : MIS_TOV_A) -> Self { variant as u8 != 0 } } impl MIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_TOV_A { match self . bits { false => MIS_TOV_A :: MIS_TOV_CLR , true => MIS_TOV_A :: MIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_tov_clr (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_tov_set (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn mis_z (& self) -> MIS_Z_R { MIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn mis_l (& self) -> MIS_L_R { MIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccd0 (& self) -> MIS_CCD0_R { MIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccd1 (& self) -> MIS_CCD1_R { MIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccu0 (& self) -> MIS_CCU0_R { MIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccu1 (& self) -> MIS_CCU1_R { MIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn mis_tov (& self) -> MIS_TOV_R { MIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Zero event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_Z_AW { # [doc = "0: NO_EFFECT"]
ISET_Z_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_Z_SET = 1 , } impl From < ISET_Z_AW > for bool { # [inline (always)]
fn from (variant : ISET_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_Z` writer - Zero event SET"]
pub type ISET_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_Z_AW > ; impl < 'a , REG , const O : u8 > ISET_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_SET) } } # [doc = "Load event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_L_AW { # [doc = "0: NO_EFFECT"]
ISET_L_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_L_SET = 1 , } impl From < ISET_L_AW > for bool { # [inline (always)]
fn from (variant : ISET_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_L` writer - Load event SET"]
pub type ISET_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_L_AW > ; impl < 'a , REG , const O : u8 > ISET_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD0_SET = 1 , } impl From < ISET_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD0` writer - Capture or compare down event SET"]
pub type ISET_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD1_SET = 1 , } impl From < ISET_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD1` writer - Capture or compare down event SET"]
pub type ISET_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU0_SET = 1 , } impl From < ISET_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU0` writer - Capture or compare up event SET"]
pub type ISET_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU1_SET = 1 , } impl From < ISET_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU1` writer - Capture or compare up event SET"]
pub type ISET_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_SET) } } # [doc = "Trigger Overflow event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_TOV_AW { # [doc = "0: NO_EFFECT"]
ISET_TOV_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_TOV_SET = 1 , } impl From < ISET_TOV_AW > for bool { # [inline (always)]
fn from (variant : ISET_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_TOV` writer - Trigger Overflow event SET"]
pub type ISET_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_TOV_AW > ; impl < 'a , REG , const O : u8 > ISET_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_SET) } } impl W { # [doc = "Bit 0 - Zero event SET"]
# [inline (always)]
# [must_use]
pub fn iset_z (& mut self) -> ISET_Z_W < ISET_SPEC , 0 > { ISET_Z_W :: new (self) } # [doc = "Bit 1 - Load event SET"]
# [inline (always)]
# [must_use]
pub fn iset_l (& mut self) -> ISET_L_W < ISET_SPEC , 1 > { ISET_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd0 (& mut self) -> ISET_CCD0_W < ISET_SPEC , 4 > { ISET_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd1 (& mut self) -> ISET_CCD1_W < ISET_SPEC , 5 > { ISET_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu0 (& mut self) -> ISET_CCU0_W < ISET_SPEC , 8 > { ISET_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu1 (& mut self) -> ISET_CCU1_W < ISET_SPEC , 9 > { ISET_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event SET"]
# [inline (always)]
# [must_use]
pub fn iset_tov (& mut self) -> ISET_TOV_W < ISET_SPEC , 25 > { ISET_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Zero event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_Z_AW { # [doc = "0: NO_EFFECT"]
ICLR_Z_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_Z_CLR = 1 , } impl From < ICLR_Z_AW > for bool { # [inline (always)]
fn from (variant : ICLR_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_Z` writer - Zero event CLEAR"]
pub type ICLR_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_Z_AW > ; impl < 'a , REG , const O : u8 > ICLR_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_CLR) } } # [doc = "Load event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_L_AW { # [doc = "0: NO_EFFECT"]
ICLR_L_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_L_CLR = 1 , } impl From < ICLR_L_AW > for bool { # [inline (always)]
fn from (variant : ICLR_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_L` writer - Load event CLEAR"]
pub type ICLR_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_L_AW > ; impl < 'a , REG , const O : u8 > ICLR_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD0_CLR = 1 , } impl From < ICLR_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD0` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD1_CLR = 1 , } impl From < ICLR_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD1` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU0_CLR = 1 , } impl From < ICLR_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU0` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU1_CLR = 1 , } impl From < ICLR_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU1` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_CLR) } } # [doc = "Trigger Overflow event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_TOV_AW { # [doc = "0: NO_EFFECT"]
ICLR_TOV_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_TOV_CLR = 1 , } impl From < ICLR_TOV_AW > for bool { # [inline (always)]
fn from (variant : ICLR_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_TOV` writer - Trigger Overflow event CLEAR"]
pub type ICLR_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_TOV_AW > ; impl < 'a , REG , const O : u8 > ICLR_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_CLR) } } impl W { # [doc = "Bit 0 - Zero event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_z (& mut self) -> ICLR_Z_W < ICLR_SPEC , 0 > { ICLR_Z_W :: new (self) } # [doc = "Bit 1 - Load event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_l (& mut self) -> ICLR_L_W < ICLR_SPEC , 1 > { ICLR_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd0 (& mut self) -> ICLR_CCD0_W < ICLR_SPEC , 4 > { ICLR_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd1 (& mut self) -> ICLR_CCD1_W < ICLR_SPEC , 5 > { ICLR_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu0 (& mut self) -> ICLR_CCU0_W < ICLR_SPEC , 8 > { ICLR_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu1 (& mut self) -> ICLR_CCU1_W < ICLR_SPEC , 9 > { ICLR_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_tov (& mut self) -> ICLR_TOV_W < ICLR_SPEC , 25 > { ICLR_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_EVT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
pub type EVT_MODE_EVT0_CFG_R = crate :: FieldReader < EVT_MODE_EVT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_software (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
# [inline (always)]
pub fn evt_mode_evt0_cfg (& self) -> EVT_MODE_EVT0_CFG_R { EVT_MODE_EVT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0x29"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0x29 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCPD (rw) register accessor: CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccpd`]
module"]
pub type CCPD = crate :: Reg < ccpd :: CCPD_SPEC > ; # [doc = "CCP Direction"]
pub mod ccpd { # [doc = "Register `CCPD` reader"]
pub type R = crate :: R < CCPD_SPEC > ; # [doc = "Register `CCPD` writer"]
pub type W = crate :: W < CCPD_SPEC > ; # [doc = "Field `CCPD_C0CCP0` reader - Counter CCP0"]
pub type CCPD_C0CCP0_R = crate :: BitReader < CCPD_C0CCP0_A > ; # [doc = "Counter CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP0_A { # [doc = "0: INPUT"]
CCPD_C0CCP0_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP0_OUTPUT = 1 , } impl From < CCPD_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP0_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP0_A { match self . bits { false => CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT , true => CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_input (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_output (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT } } # [doc = "Field `CCPD_C0CCP0` writer - Counter CCP0"]
pub type CCPD_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP0_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT) } } # [doc = "Field `CCPD_C0CCP1` reader - Counter CCP1"]
pub type CCPD_C0CCP1_R = crate :: BitReader < CCPD_C0CCP1_A > ; # [doc = "Counter CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP1_A { # [doc = "0: INPUT"]
CCPD_C0CCP1_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP1_OUTPUT = 1 , } impl From < CCPD_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP1_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP1_A { match self . bits { false => CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT , true => CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_input (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_output (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT } } # [doc = "Field `CCPD_C0CCP1` writer - Counter CCP1"]
pub type CCPD_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP1_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT) } } impl R { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
pub fn ccpd_c0ccp0 (& self) -> CCPD_C0CCP0_R { CCPD_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
pub fn ccpd_c0ccp1 (& self) -> CCPD_C0CCP1_R { CCPD_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp0 (& mut self) -> CCPD_C0CCP0_W < CCPD_SPEC , 0 > { CCPD_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp1 (& mut self) -> CCPD_C0CCP1_W < CCPD_SPEC , 1 > { CCPD_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCPD_SPEC ; impl crate :: RegisterSpec for CCPD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccpd::R`](R) reader structure"]
impl crate :: Readable for CCPD_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccpd::W`](W) writer structure"]
impl crate :: Writable for CCPD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCPD to value 0"]
impl crate :: Resettable for CCPD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ODIS (rw) register accessor: Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@odis`]
module"]
pub type ODIS = crate :: Reg < odis :: ODIS_SPEC > ; # [doc = "Output Disable"]
pub mod odis { # [doc = "Register `ODIS` reader"]
pub type R = crate :: R < ODIS_SPEC > ; # [doc = "Register `ODIS` writer"]
pub type W = crate :: W < ODIS_SPEC > ; # [doc = "Field `ODIS_C0CCP0` reader - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_R = crate :: BitReader < ODIS_C0CCP0_A > ; # [doc = "Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP0_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP0_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP0_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP0_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP0_A { match self . bits { false => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL , true => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP0` writer - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP0_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW) } } # [doc = "Field `ODIS_C0CCP1` reader - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_R = crate :: BitReader < ODIS_C0CCP1_A > ; # [doc = "Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP1_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP1_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP1_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP1_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP1_A { match self . bits { false => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL , true => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP1` writer - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP1_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW) } } impl R { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp0 (& self) -> ODIS_C0CCP0_R { ODIS_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp1 (& self) -> ODIS_C0CCP1_R { ODIS_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp0 (& mut self) -> ODIS_C0CCP0_W < ODIS_SPEC , 0 > { ODIS_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp1 (& mut self) -> ODIS_C0CCP1_W < ODIS_SPEC , 1 > { ODIS_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ODIS_SPEC ; impl crate :: RegisterSpec for ODIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`odis::R`](R) reader structure"]
impl crate :: Readable for ODIS_SPEC { } # [doc = "`write(|w| ..)` method takes [`odis::W`](W) writer structure"]
impl crate :: Writable for ODIS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ODIS to value 0"]
impl crate :: Resettable for ODIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCLKCTL (rw) register accessor: Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cclkctl`]
module"]
pub type CCLKCTL = crate :: Reg < cclkctl :: CCLKCTL_SPEC > ; # [doc = "Counter Clock Control Register"]
pub mod cclkctl { # [doc = "Register `CCLKCTL` reader"]
pub type R = crate :: R < CCLKCTL_SPEC > ; # [doc = "Register `CCLKCTL` writer"]
pub type W = crate :: W < CCLKCTL_SPEC > ; # [doc = "Field `CCLKCTL_CLKEN` reader - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_R = crate :: BitReader < CCLKCTL_CLKEN_A > ; # [doc = "Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCLKCTL_CLKEN_A { # [doc = "0: DISABLED"]
CCLKCTL_CLKEN_DISABLED = 0 , # [doc = "1: ENABLED"]
CCLKCTL_CLKEN_ENABLED = 1 , } impl From < CCLKCTL_CLKEN_A > for bool { # [inline (always)]
fn from (variant : CCLKCTL_CLKEN_A) -> Self { variant as u8 != 0 } } impl CCLKCTL_CLKEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCLKCTL_CLKEN_A { match self . bits { false => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED , true => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_disabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_enabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED } } # [doc = "Field `CCLKCTL_CLKEN` writer - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCLKCTL_CLKEN_A > ; impl < 'a , REG , const O : u8 > CCLKCTL_CLKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cclkctl_clken_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn cclkctl_clken_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED) } } impl R { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
pub fn cclkctl_clken (& self) -> CCLKCTL_CLKEN_R { CCLKCTL_CLKEN_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
# [must_use]
pub fn cclkctl_clken (& mut self) -> CCLKCTL_CLKEN_W < CCLKCTL_SPEC , 0 > { CCLKCTL_CLKEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCLKCTL_SPEC ; impl crate :: RegisterSpec for CCLKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cclkctl::R`](R) reader structure"]
impl crate :: Readable for CCLKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cclkctl::W`](W) writer structure"]
impl crate :: Writable for CCLKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCLKCTL to value 0"]
impl crate :: Resettable for CCLKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPS (rw) register accessor: Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cps`]
module"]
pub type CPS = crate :: Reg < cps :: CPS_SPEC > ; # [doc = "Clock Prescale Register"]
pub mod cps { # [doc = "Register `CPS` reader"]
pub type R = crate :: R < CPS_SPEC > ; # [doc = "Register `CPS` writer"]
pub type W = crate :: W < CPS_SPEC > ; # [doc = "Field `CPS_PCNT` reader - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_R = crate :: FieldReader ; # [doc = "Field `CPS_PCNT` writer - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
pub fn cps_pcnt (& self) -> CPS_PCNT_R { CPS_PCNT_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
# [must_use]
pub fn cps_pcnt (& mut self) -> CPS_PCNT_W < CPS_SPEC , 0 > { CPS_PCNT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPS_SPEC ; impl crate :: RegisterSpec for CPS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cps::R`](R) reader structure"]
impl crate :: Readable for CPS_SPEC { } # [doc = "`write(|w| ..)` method takes [`cps::W`](W) writer structure"]
impl crate :: Writable for CPS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CPS to value 0"]
impl crate :: Resettable for CPS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPSV (r) register accessor: Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpsv`]
module"]
pub type CPSV = crate :: Reg < cpsv :: CPSV_SPEC > ; # [doc = "Clock prescale count status register"]
pub mod cpsv { # [doc = "Register `CPSV` reader"]
pub type R = crate :: R < CPSV_SPEC > ; # [doc = "Field `CPSV_CPSVAL` reader - Current Prescale Count Value"]
pub type CPSV_CPSVAL_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Current Prescale Count Value"]
# [inline (always)]
pub fn cpsv_cpsval (& self) -> CPSV_CPSVAL_R { CPSV_CPSVAL_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPSV_SPEC ; impl crate :: RegisterSpec for CPSV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cpsv::R`](R) reader structure"]
impl crate :: Readable for CPSV_SPEC { } # [doc = "`reset()` method sets CPSV to value 0"]
impl crate :: Resettable for CPSV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIGCTL (rw) register accessor: Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrigctl`]
module"]
pub type CTTRIGCTL = crate :: Reg < cttrigctl :: CTTRIGCTL_SPEC > ; # [doc = "Timer Cross Trigger Control Register"]
pub mod cttrigctl { # [doc = "Register `CTTRIGCTL` reader"]
pub type R = crate :: R < CTTRIGCTL_SPEC > ; # [doc = "Register `CTTRIGCTL` writer"]
pub type W = crate :: W < CTTRIGCTL_SPEC > ; # [doc = "Field `CTTRIGCTL_CTEN` reader - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_R = crate :: BitReader < CTTRIGCTL_CTEN_A > ; # [doc = "Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_CTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_CTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_CTEN_ENABLE = 1 , } impl From < CTTRIGCTL_CTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_CTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_CTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_CTEN_A { match self . bits { false => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED , true => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_cten_disabled (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_cten_enable (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_CTEN` writer - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_CTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_CTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_cten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_cten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTEN` reader - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_R = crate :: BitReader < CTTRIGCTL_EVTCTEN_A > ; # [doc = "Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_EVTCTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_EVTCTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_EVTCTEN_ENABLE = 1 , } impl From < CTTRIGCTL_EVTCTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_EVTCTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_EVTCTEN_A { match self . bits { false => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED , true => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_disabled (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_enable (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_EVTCTEN` writer - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_EVTCTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_evtcten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_evtcten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` reader - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_R = crate :: FieldReader < CTTRIGCTL_EVTCTTRIGSEL_A > ; # [doc = "Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTTRIGCTL_EVTCTTRIGSEL_A { # [doc = "0: FSUB0"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB0 = 0 , # [doc = "1: FSUB1"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB1 = 1 , # [doc = "2: Z"]
CTTRIGCTL_EVTCTTRIGSEL_Z = 2 , # [doc = "3: L"]
CTTRIGCTL_EVTCTTRIGSEL_L = 3 , # [doc = "4: CCD0"]
CTTRIGCTL_EVTCTTRIGSEL_CCD0 = 4 , # [doc = "5: CCD1"]
CTTRIGCTL_EVTCTTRIGSEL_CCD1 = 5 , # [doc = "6: CCD2"]
CTTRIGCTL_EVTCTTRIGSEL_CCD2 = 6 , # [doc = "7: CCD3"]
CTTRIGCTL_EVTCTTRIGSEL_CCD3 = 7 , # [doc = "8: CCU0"]
CTTRIGCTL_EVTCTTRIGSEL_CCU0 = 8 , # [doc = "9: CCU1"]
CTTRIGCTL_EVTCTTRIGSEL_CCU1 = 9 , # [doc = "10: CCU2"]
CTTRIGCTL_EVTCTTRIGSEL_CCU2 = 10 , # [doc = "11: CCU3"]
CTTRIGCTL_EVTCTTRIGSEL_CCU3 = 11 , } impl From < CTTRIGCTL_EVTCTTRIGSEL_A > for u8 { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTTRIGSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTTRIGCTL_EVTCTTRIGSEL_A { type Ux = u8 ; } impl CTTRIGCTL_EVTCTTRIGSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTTRIGCTL_EVTCTTRIGSEL_A > { match self . bits { 0 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) , 1 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) , 2 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) , 3 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) , 4 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) , 5 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) , 6 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) , 7 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) , 8 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) , 9 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) , 10 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) , 11 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) , _ => None , } } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1 } # [doc = "Z"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_z (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z } # [doc = "L"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_l (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3 } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` writer - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CTTRIGCTL_EVTCTTRIGSEL_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FSUB0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) } # [doc = "Z"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_z (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) } # [doc = "L"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_l (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) } # [doc = "CCD0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) } # [doc = "CCD1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) } # [doc = "CCD2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) } # [doc = "CCD3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) } # [doc = "CCU0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) } # [doc = "CCU1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) } # [doc = "CCU2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) } # [doc = "CCU3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) } } impl R { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
pub fn cttrigctl_cten (& self) -> CTTRIGCTL_CTEN_R { CTTRIGCTL_CTEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcten (& self) -> CTTRIGCTL_EVTCTEN_R { CTTRIGCTL_EVTCTEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel (& self) -> CTTRIGCTL_EVTCTTRIGSEL_R { CTTRIGCTL_EVTCTTRIGSEL_R :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
# [must_use]
pub fn cttrigctl_cten (& mut self) -> CTTRIGCTL_CTEN_W < CTTRIGCTL_SPEC , 0 > { CTTRIGCTL_CTEN_W :: new (self) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcten (& mut self) -> CTTRIGCTL_EVTCTEN_W < CTTRIGCTL_SPEC , 1 > { CTTRIGCTL_EVTCTEN_W :: new (self) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcttrigsel (& mut self) -> CTTRIGCTL_EVTCTTRIGSEL_W < CTTRIGCTL_SPEC , 16 > { CTTRIGCTL_EVTCTTRIGSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIGCTL_SPEC ; impl crate :: RegisterSpec for CTTRIGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cttrigctl::R`](R) reader structure"]
impl crate :: Readable for CTTRIGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cttrigctl::W`](W) writer structure"]
impl crate :: Writable for CTTRIGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIGCTL to value 0"]
impl crate :: Resettable for CTTRIGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIG (w) register accessor: Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrig`]
module"]
pub type CTTRIG = crate :: Reg < cttrig :: CTTRIG_SPEC > ; # [doc = "Timer Cross Trigger Register"]
pub mod cttrig { # [doc = "Register `CTTRIG` writer"]
pub type W = crate :: W < CTTRIG_SPEC > ; # [doc = "Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIG_TRIG_AW { # [doc = "0: DISABLED"]
CTTRIG_TRIG_DISABLED = 0 , # [doc = "1: GENERATE"]
CTTRIG_TRIG_GENERATE = 1 , } impl From < CTTRIG_TRIG_AW > for bool { # [inline (always)]
fn from (variant : CTTRIG_TRIG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `CTTRIG_TRIG` writer - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
pub type CTTRIG_TRIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIG_TRIG_AW > ; impl < 'a , REG , const O : u8 > CTTRIG_TRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrig_trig_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_DISABLED) } # [doc = "GENERATE"]
# [inline (always)]
pub fn cttrig_trig_generate (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_GENERATE) } } impl W { # [doc = "Bit 0 - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
# [inline (always)]
# [must_use]
pub fn cttrig_trig (& mut self) -> CTTRIG_TRIG_W < CTTRIG_SPEC , 0 > { CTTRIG_TRIG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIG_SPEC ; impl crate :: RegisterSpec for CTTRIG_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`cttrig::W`](W) writer structure"]
impl crate :: Writable for CTTRIG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIG to value 0"]
impl crate :: Resettable for CTTRIG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTR (rw) register accessor: Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`]
module"]
pub type CTR = crate :: Reg < ctr :: CTR_SPEC > ; # [doc = "Counter Register"]
pub mod ctr { # [doc = "Register `CTR` reader"]
pub type R = crate :: R < CTR_SPEC > ; # [doc = "Register `CTR` writer"]
pub type W = crate :: W < CTR_SPEC > ; # [doc = "Field `CTR_CCTR` reader - Current Counter value"]
pub type CTR_CCTR_R = crate :: FieldReader < u16 > ; # [doc = "Field `CTR_CCTR` writer - Current Counter value"]
pub type CTR_CCTR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
pub fn ctr_cctr (& self) -> CTR_CCTR_R { CTR_CCTR_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
# [must_use]
pub fn ctr_cctr (& mut self) -> CTR_CCTR_W < CTR_SPEC , 0 > { CTR_CCTR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTR_SPEC ; impl crate :: RegisterSpec for CTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctr::R`](R) reader structure"]
impl crate :: Readable for CTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
impl crate :: Writable for CTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTR to value 0"]
impl crate :: Resettable for CTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTRCTL (rw) register accessor: Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrctl`]
module"]
pub type CTRCTL = crate :: Reg < ctrctl :: CTRCTL_SPEC > ; # [doc = "Counter Control Register"]
pub mod ctrctl { # [doc = "Register `CTRCTL` reader"]
pub type R = crate :: R < CTRCTL_SPEC > ; # [doc = "Register `CTRCTL` writer"]
pub type W = crate :: W < CTRCTL_SPEC > ; # [doc = "Field `CTRCTL_EN` reader - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_R = crate :: BitReader < CTRCTL_EN_A > ; # [doc = "Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_EN_A { # [doc = "0: DISABLED"]
CTRCTL_EN_DISABLED = 0 , # [doc = "1: ENABLED"]
CTRCTL_EN_ENABLED = 1 , } impl From < CTRCTL_EN_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_EN_A) -> Self { variant as u8 != 0 } } impl CTRCTL_EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_EN_A { match self . bits { false => CTRCTL_EN_A :: CTRCTL_EN_DISABLED , true => CTRCTL_EN_A :: CTRCTL_EN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ctrctl_en_disabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ctrctl_en_enabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_ENABLED } } # [doc = "Field `CTRCTL_EN` writer - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_EN_A > ; impl < 'a , REG , const O : u8 > CTRCTL_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ctrctl_en_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ctrctl_en_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_ENABLED) } } # [doc = "Field `CTRCTL_REPEAT` reader - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_R = crate :: FieldReader < CTRCTL_REPEAT_A > ; # [doc = "Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_REPEAT_A { # [doc = "0: REPEAT_0"]
CTRCTL_REPEAT_REPEAT_0 = 0 , # [doc = "1: REPEAT_1"]
CTRCTL_REPEAT_REPEAT_1 = 1 , # [doc = "2: REPEAT_2"]
CTRCTL_REPEAT_REPEAT_2 = 2 , # [doc = "3: REPEAT_3"]
CTRCTL_REPEAT_REPEAT_3 = 3 , # [doc = "4: REPEAT_4"]
CTRCTL_REPEAT_REPEAT_4 = 4 , } impl From < CTRCTL_REPEAT_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_REPEAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_REPEAT_A { type Ux = u8 ; } impl CTRCTL_REPEAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_REPEAT_A > { match self . bits { 0 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) , 1 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) , 2 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) , 3 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) , 4 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) , _ => None , } } # [doc = "REPEAT_0"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_0 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0 } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_1 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1 } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_2 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2 } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_3 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3 } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_4 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4 } } # [doc = "Field `CTRCTL_REPEAT` writer - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_REPEAT_A > ; impl < 'a , REG , const O : u8 > CTRCTL_REPEAT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "REPEAT_0"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) } } # [doc = "Field `CTRCTL_CM` reader - Count Mode"]
pub type CTRCTL_CM_R = crate :: FieldReader < CTRCTL_CM_A > ; # [doc = "Count Mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CM_A { # [doc = "0: DOWN"]
CTRCTL_CM_DOWN = 0 , # [doc = "1: UP_DOWN"]
CTRCTL_CM_UP_DOWN = 1 , # [doc = "2: UP"]
CTRCTL_CM_UP = 2 , } impl From < CTRCTL_CM_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CM_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CM_A { type Ux = u8 ; } impl CTRCTL_CM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CM_A > { match self . bits { 0 => Some (CTRCTL_CM_A :: CTRCTL_CM_DOWN) , 1 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) , 2 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP) , _ => None , } } # [doc = "DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_DOWN } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_up_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN } # [doc = "UP"]
# [inline (always)]
pub fn is_ctrctl_cm_up (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP } } # [doc = "Field `CTRCTL_CM` writer - Count Mode"]
pub type CTRCTL_CM_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CM_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DOWN"]
# [inline (always)]
pub fn ctrctl_cm_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_DOWN) } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn ctrctl_cm_up_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) } # [doc = "UP"]
# [inline (always)]
pub fn ctrctl_cm_up (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP) } } # [doc = "Field `CTRCTL_CLC` reader - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_R = crate :: FieldReader < CTRCTL_CLC_A > ; # [doc = "Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CLC_A { # [doc = "0: CCCTL0_LCOND"]
CTRCTL_CLC_CCCTL0_LCOND = 0 , # [doc = "1: CCCTL1_LCOND"]
CTRCTL_CLC_CCCTL1_LCOND = 1 , # [doc = "2: CCCTL2_LCOND"]
CTRCTL_CLC_CCCTL2_LCOND = 2 , # [doc = "3: CCCTL3_LCOND"]
CTRCTL_CLC_CCCTL3_LCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CLC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CLC_QEI_3INP = 5 , } impl From < CTRCTL_CLC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CLC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CLC_A { type Ux = u8 ; } impl CTRCTL_CLC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CLC_A > { match self . bits { 0 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) , 1 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) , 2 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) , 3 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) , 4 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) , 5 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl0_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl1_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl2_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl3_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_2inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_3inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP } } # [doc = "Field `CTRCTL_CLC` writer - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CLC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CLC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl0_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl1_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl2_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl3_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) } } # [doc = "Field `CTRCTL_CAC` reader - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_R = crate :: FieldReader < CTRCTL_CAC_A > ; # [doc = "Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CAC_A { # [doc = "0: CCCTL0_ACOND"]
CTRCTL_CAC_CCCTL0_ACOND = 0 , # [doc = "1: CCCTL1_ACOND"]
CTRCTL_CAC_CCCTL1_ACOND = 1 , # [doc = "2: CCCTL2_ACOND"]
CTRCTL_CAC_CCCTL2_ACOND = 2 , # [doc = "3: CCCTL3_ACOND"]
CTRCTL_CAC_CCCTL3_ACOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CAC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CAC_QEI_3INP = 5 , } impl From < CTRCTL_CAC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CAC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CAC_A { type Ux = u8 ; } impl CTRCTL_CAC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CAC_A > { match self . bits { 0 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) , 1 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) , 2 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) , 3 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) , 4 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) , 5 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl0_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl1_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl2_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl3_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_2inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_3inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP } } # [doc = "Field `CTRCTL_CAC` writer - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CAC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CAC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl0_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl1_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl2_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl3_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) } } # [doc = "Field `CTRCTL_CZC` reader - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_R = crate :: FieldReader < CTRCTL_CZC_A > ; # [doc = "Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CZC_A { # [doc = "0: CCCTL0_ZCOND"]
CTRCTL_CZC_CCCTL0_ZCOND = 0 , # [doc = "1: CCCTL1_ZCOND"]
CTRCTL_CZC_CCCTL1_ZCOND = 1 , # [doc = "2: CCCTL2_ZCOND"]
CTRCTL_CZC_CCCTL2_ZCOND = 2 , # [doc = "3: CCCTL3_ZCOND"]
CTRCTL_CZC_CCCTL3_ZCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CZC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CZC_QEI_3INP = 5 , } impl From < CTRCTL_CZC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CZC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CZC_A { type Ux = u8 ; } impl CTRCTL_CZC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CZC_A > { match self . bits { 0 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) , 1 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) , 2 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) , 3 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) , 4 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) , 5 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl0_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl1_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl2_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl3_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_2inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_3inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP } } # [doc = "Field `CTRCTL_CZC` writer - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CZC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CZC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl0_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl1_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl2_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl3_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) } } # [doc = "Field `CTRCTL_DRB` reader - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_R = crate :: BitReader < CTRCTL_DRB_A > ; # [doc = "Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_DRB_A { # [doc = "0: RESUME"]
CTRCTL_DRB_RESUME = 0 , # [doc = "1: CVAE_ACTION"]
CTRCTL_DRB_CVAE_ACTION = 1 , } impl From < CTRCTL_DRB_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_DRB_A) -> Self { variant as u8 != 0 } } impl CTRCTL_DRB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_DRB_A { match self . bits { false => CTRCTL_DRB_A :: CTRCTL_DRB_RESUME , true => CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION , } } # [doc = "RESUME"]
# [inline (always)]
pub fn is_ctrctl_drb_resume (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_RESUME } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn is_ctrctl_drb_cvae_action (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION } } # [doc = "Field `CTRCTL_DRB` writer - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_DRB_A > ; impl < 'a , REG , const O : u8 > CTRCTL_DRB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RESUME"]
# [inline (always)]
pub fn ctrctl_drb_resume (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_RESUME) } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn ctrctl_drb_cvae_action (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION) } } # [doc = "Field `CTRCTL_CVAE` reader - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_R = crate :: FieldReader < CTRCTL_CVAE_A > ; # [doc = "Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CVAE_A { # [doc = "0: LDVAL"]
CTRCTL_CVAE_LDVAL = 0 , # [doc = "1: NOCHANGE"]
CTRCTL_CVAE_NOCHANGE = 1 , # [doc = "2: ZEROVAL"]
CTRCTL_CVAE_ZEROVAL = 2 , } impl From < CTRCTL_CVAE_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CVAE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CVAE_A { type Ux = u8 ; } impl CTRCTL_CVAE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CVAE_A > { match self . bits { 0 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) , 1 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) , 2 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) , _ => None , } } # [doc = "LDVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_ldval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn is_ctrctl_cvae_nochange (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_zeroval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL } } # [doc = "Field `CTRCTL_CVAE` writer - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CVAE_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CVAE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LDVAL"]
# [inline (always)]
pub fn ctrctl_cvae_ldval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn ctrctl_cvae_nochange (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn ctrctl_cvae_zeroval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) } } impl R { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
pub fn ctrctl_en (& self) -> CTRCTL_EN_R { CTRCTL_EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
pub fn ctrctl_repeat (& self) -> CTRCTL_REPEAT_R { CTRCTL_REPEAT_R :: new (((self . bits >> 1) & 7) as u8) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
pub fn ctrctl_cm (& self) -> CTRCTL_CM_R { CTRCTL_CM_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_clc (& self) -> CTRCTL_CLC_R { CTRCTL_CLC_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_cac (& self) -> CTRCTL_CAC_R { CTRCTL_CAC_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_czc (& self) -> CTRCTL_CZC_R { CTRCTL_CZC_R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
pub fn ctrctl_drb (& self) -> CTRCTL_DRB_R { CTRCTL_DRB_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
pub fn ctrctl_cvae (& self) -> CTRCTL_CVAE_R { CTRCTL_CVAE_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
# [must_use]
pub fn ctrctl_en (& mut self) -> CTRCTL_EN_W < CTRCTL_SPEC , 0 > { CTRCTL_EN_W :: new (self) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
# [must_use]
pub fn ctrctl_repeat (& mut self) -> CTRCTL_REPEAT_W < CTRCTL_SPEC , 1 > { CTRCTL_REPEAT_W :: new (self) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
# [must_use]
pub fn ctrctl_cm (& mut self) -> CTRCTL_CM_W < CTRCTL_SPEC , 4 > { CTRCTL_CM_W :: new (self) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_clc (& mut self) -> CTRCTL_CLC_W < CTRCTL_SPEC , 7 > { CTRCTL_CLC_W :: new (self) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cac (& mut self) -> CTRCTL_CAC_W < CTRCTL_SPEC , 10 > { CTRCTL_CAC_W :: new (self) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_czc (& mut self) -> CTRCTL_CZC_W < CTRCTL_SPEC , 13 > { CTRCTL_CZC_W :: new (self) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
# [must_use]
pub fn ctrctl_drb (& mut self) -> CTRCTL_DRB_W < CTRCTL_SPEC , 17 > { CTRCTL_DRB_W :: new (self) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cvae (& mut self) -> CTRCTL_CVAE_W < CTRCTL_SPEC , 28 > { CTRCTL_CVAE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRCTL_SPEC ; impl crate :: RegisterSpec for CTRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctrctl::R`](R) reader structure"]
impl crate :: Readable for CTRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctrctl::W`](W) writer structure"]
impl crate :: Writable for CTRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTRCTL to value 0xff80"]
impl crate :: Resettable for CTRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0xff80 ; } } # [doc = "LOAD (rw) register accessor: Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load`]
module"]
pub type LOAD = crate :: Reg < load :: LOAD_SPEC > ; # [doc = "Load Register"]
pub mod load { # [doc = "Register `LOAD` reader"]
pub type R = crate :: R < LOAD_SPEC > ; # [doc = "Register `LOAD` writer"]
pub type W = crate :: W < LOAD_SPEC > ; # [doc = "Field `LOAD_LD` reader - Load Value"]
pub type LOAD_LD_R = crate :: FieldReader < u16 > ; # [doc = "Field `LOAD_LD` writer - Load Value"]
pub type LOAD_LD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
pub fn load_ld (& self) -> LOAD_LD_R { LOAD_LD_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
# [must_use]
pub fn load_ld (& mut self) -> LOAD_LD_W < LOAD_SPEC , 0 > { LOAD_LD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LOAD_SPEC ; impl crate :: RegisterSpec for LOAD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`load::R`](R) reader structure"]
impl crate :: Readable for LOAD_SPEC { } # [doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"]
impl crate :: Writable for LOAD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LOAD to value 0"]
impl crate :: Resettable for LOAD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CC_01 (rw) register accessor: Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cc_01`]
module"]
pub type CC_01 = crate :: Reg < cc_01 :: CC_01_SPEC > ; # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1"]
pub mod cc_01 { # [doc = "Register `CC_01[%s]` reader"]
pub type R = crate :: R < CC_01_SPEC > ; # [doc = "Register `CC_01[%s]` writer"]
pub type W = crate :: W < CC_01_SPEC > ; # [doc = "Field `CC_01_CCVAL` reader - Capture or compare value"]
pub type CC_01_CCVAL_R = crate :: FieldReader < u16 > ; # [doc = "Field `CC_01_CCVAL` writer - Capture or compare value"]
pub type CC_01_CCVAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
pub fn cc_01_ccval (& self) -> CC_01_CCVAL_R { CC_01_CCVAL_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
# [must_use]
pub fn cc_01_ccval (& mut self) -> CC_01_CCVAL_W < CC_01_SPEC , 0 > { CC_01_CCVAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CC_01_SPEC ; impl crate :: RegisterSpec for CC_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cc_01::R`](R) reader structure"]
impl crate :: Readable for CC_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`cc_01::W`](W) writer structure"]
impl crate :: Writable for CC_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CC_01[%s]
to value 0"]
impl crate :: Resettable for CC_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCCTL_01 (rw) register accessor: Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccctl_01`]
module"]
pub type CCCTL_01 = crate :: Reg < ccctl_01 :: CCCTL_01_SPEC > ; # [doc = "Capture or Compare Control Registers"]
pub mod ccctl_01 { # [doc = "Register `CCCTL_01[%s]` reader"]
pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"]
pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"]
CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"]
CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"]
CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"]
# [inline (always)]
pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"]
# [inline (always)]
pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"]
CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"]
CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)]
fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"]
# [inline (always)]
pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"]
# [inline (always)]
pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"]
# [inline (always)]
pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"]
CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"]
CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"]
CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"]
CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"]
CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"]
CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"]
CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"]
CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"]
CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"]
CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"]
CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"]
# [inline (always)]
pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"]
CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"]
CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"]
CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"]
CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"]
CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"]
CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"]
impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"]
impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s]
to value 0"]
impl crate :: Resettable for CCCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "OCTL_01 (rw) register accessor: CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@octl_01`]
module"]
pub type OCTL_01 = crate :: Reg < octl_01 :: OCTL_01_SPEC > ; # [doc = "CCP Output Control Registers"]
pub mod octl_01 { # [doc = "Register `OCTL_01[%s]` reader"]
pub type R = crate :: R < OCTL_01_SPEC > ; # [doc = "Register `OCTL_01[%s]` writer"]
pub type W = crate :: W < OCTL_01_SPEC > ; # [doc = "Field `OCTL_01_CCPO` reader - CCP Output Source"]
pub type OCTL_01_CCPO_R = crate :: FieldReader < OCTL_01_CCPO_A > ; # [doc = "CCP Output Source\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum OCTL_01_CCPO_A { # [doc = "0: FUNCVAL"]
OCTL_01_CCPO_FUNCVAL = 0 , # [doc = "1: LOAD"]
OCTL_01_CCPO_LOAD = 1 , # [doc = "2: CMPVAL"]
OCTL_01_CCPO_CMPVAL = 2 , # [doc = "4: ZERO"]
OCTL_01_CCPO_ZERO = 4 , # [doc = "5: CAPCOND"]
OCTL_01_CCPO_CAPCOND = 5 , # [doc = "6: FAULTCOND"]
OCTL_01_CCPO_FAULTCOND = 6 , # [doc = "8: CC0_MIRROR_ALL"]
OCTL_01_CCPO_CC0_MIRROR_ALL = 8 , # [doc = "9: CC1_MIRROR_ALL"]
OCTL_01_CCPO_CC1_MIRROR_ALL = 9 , # [doc = "12: DEADBAND"]
OCTL_01_CCPO_DEADBAND = 12 , # [doc = "13: CNTDIR"]
OCTL_01_CCPO_CNTDIR = 13 , } impl From < OCTL_01_CCPO_A > for u8 { # [inline (always)]
fn from (variant : OCTL_01_CCPO_A) -> Self { variant as _ } } impl crate :: FieldSpec for OCTL_01_CCPO_A { type Ux = u8 ; } impl OCTL_01_CCPO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < OCTL_01_CCPO_A > { match self . bits { 0 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) , 1 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) , 2 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) , 4 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) , 5 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) , 6 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) , 8 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) , 9 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) , 12 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) , 13 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) , _ => None , } } # [doc = "FUNCVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_funcval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL } # [doc = "LOAD"]
# [inline (always)]
pub fn is_octl_01_ccpo_load (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD } # [doc = "CMPVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cmpval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL } # [doc = "ZERO"]
# [inline (always)]
pub fn is_octl_01_ccpo_zero (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO } # [doc = "CAPCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_capcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_faultcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc0_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc1_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL } # [doc = "DEADBAND"]
# [inline (always)]
pub fn is_octl_01_ccpo_deadband (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND } # [doc = "CNTDIR"]
# [inline (always)]
pub fn is_octl_01_ccpo_cntdir (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR } } # [doc = "Field `OCTL_01_CCPO` writer - CCP Output Source"]
pub type OCTL_01_CCPO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , OCTL_01_CCPO_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FUNCVAL"]
# [inline (always)]
pub fn octl_01_ccpo_funcval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) } # [doc = "LOAD"]
# [inline (always)]
pub fn octl_01_ccpo_load (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) } # [doc = "CMPVAL"]
# [inline (always)]
pub fn octl_01_ccpo_cmpval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) } # [doc = "ZERO"]
# [inline (always)]
pub fn octl_01_ccpo_zero (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) } # [doc = "CAPCOND"]
# [inline (always)]
pub fn octl_01_ccpo_capcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn octl_01_ccpo_faultcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc0_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc1_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) } # [doc = "DEADBAND"]
# [inline (always)]
pub fn octl_01_ccpo_deadband (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) } # [doc = "CNTDIR"]
# [inline (always)]
pub fn octl_01_ccpo_cntdir (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) } } # [doc = "Field `OCTL_01_CCPOINV` reader - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_R = crate :: BitReader < OCTL_01_CCPOINV_A > ; # [doc = "CCP Output Invert The output as selected by CCPO is conditionally inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPOINV_A { # [doc = "0: NOINV"]
OCTL_01_CCPOINV_NOINV = 0 , # [doc = "1: INV"]
OCTL_01_CCPOINV_INV = 1 , } impl From < OCTL_01_CCPOINV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPOINV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPOINV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPOINV_A { match self . bits { false => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV , true => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV , } } # [doc = "NOINV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_noinv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV } # [doc = "INV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_inv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV } } # [doc = "Field `OCTL_01_CCPOINV` writer - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPOINV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPOINV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINV"]
# [inline (always)]
pub fn octl_01_ccpoinv_noinv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV) } # [doc = "INV"]
# [inline (always)]
pub fn octl_01_ccpoinv_inv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV) } } # [doc = "Field `OCTL_01_CCPIV` reader - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_R = crate :: BitReader < OCTL_01_CCPIV_A > ; # [doc = "CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPIV_A { # [doc = "0: LOW"]
OCTL_01_CCPIV_LOW = 0 , # [doc = "1: HIGH"]
OCTL_01_CCPIV_HIGH = 1 , } impl From < OCTL_01_CCPIV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPIV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPIV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPIV_A { match self . bits { false => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW , true => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_octl_01_ccpiv_low (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_octl_01_ccpiv_high (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH } } # [doc = "Field `OCTL_01_CCPIV` writer - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPIV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"]
# [inline (always)]
pub fn octl_01_ccpiv_low (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW) } # [doc = "HIGH"]
# [inline (always)]
pub fn octl_01_ccpiv_high (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH) } } impl R { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
pub fn octl_01_ccpo (& self) -> OCTL_01_CCPO_R { OCTL_01_CCPO_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
pub fn octl_01_ccpoinv (& self) -> OCTL_01_CCPOINV_R { OCTL_01_CCPOINV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
pub fn octl_01_ccpiv (& self) -> OCTL_01_CCPIV_R { OCTL_01_CCPIV_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W < OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W < OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W < OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OCTL_01_SPEC ; impl crate :: RegisterSpec for OCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octl_01::R`](R) reader structure"]
impl crate :: Readable for OCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`octl_01::W`](W) writer structure"]
impl crate :: Writable for OCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets OCTL_01[%s]
to value 0"]
impl crate :: Resettable for OCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCACT_01 (rw) register accessor: Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccact_01`]
module"]
pub type CCACT_01 = crate :: Reg < ccact_01 :: CCACT_01_SPEC > ; # [doc = "Capture or Compare Action Registers"]
pub mod ccact_01 { # [doc = "Register `CCACT_01[%s]` reader"]
pub type R = crate :: R < CCACT_01_SPEC > ; # [doc = "Register `CCACT_01[%s]` writer"]
pub type W = crate :: W < CCACT_01_SPEC > ; # [doc = "Field `CCACT_01_ZACT` reader - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_R = crate :: FieldReader < CCACT_01_ZACT_A > ; # [doc = "CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_ZACT_A { # [doc = "0: DISABLED"]
CCACT_01_ZACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_ZACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_ZACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_ZACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_ZACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_ZACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_ZACT_A { type Ux = u8 ; } impl CCACT_01_ZACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_ZACT_A { match self . bits { 0 => CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED , 1 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH , 2 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW , 3 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_zact_disabled (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_high (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_low (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_toggle (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_ZACT` writer - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_ZACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_ZACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_zact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_zact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_zact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_zact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_LACT` reader - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_R = crate :: FieldReader < CCACT_01_LACT_A > ; # [doc = "CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_LACT_A { # [doc = "0: DISABLED"]
CCACT_01_LACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_LACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_LACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_LACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_LACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_LACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_LACT_A { type Ux = u8 ; } impl CCACT_01_LACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_LACT_A { match self . bits { 0 => CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED , 1 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH , 2 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW , 3 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_lact_disabled (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_high (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_low (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_toggle (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_LACT` writer - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_LACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_LACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_lact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_lact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_lact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_lact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CDACT` reader - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_R = crate :: FieldReader < CCACT_01_CDACT_A > ; # [doc = "CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CDACT_A { # [doc = "0: DISABLED"]
CCACT_01_CDACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CDACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CDACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CDACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CDACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CDACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CDACT_A { type Ux = u8 ; } impl CCACT_01_CDACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CDACT_A { match self . bits { 0 => CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED , 1 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH , 2 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW , 3 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cdact_disabled (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_high (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_low (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_toggle (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CDACT` writer - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CDACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CDACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cdact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CUACT` reader - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_R = crate :: FieldReader < CCACT_01_CUACT_A > ; # [doc = "CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CUACT_A { # [doc = "0: DISABLED"]
CCACT_01_CUACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CUACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CUACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CUACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CUACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CUACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CUACT_A { type Ux = u8 ; } impl CCACT_01_CUACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CUACT_A { match self . bits { 0 => CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED , 1 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH , 2 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW , 3 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cuact_disabled (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_high (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_low (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_toggle (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CUACT` writer - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CUACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CUACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cuact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2DACT` reader - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_R = crate :: FieldReader < CCACT_01_CC2DACT_A > ; # [doc = "CCP Output Action on CC2D event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2DACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2DACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2DACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2DACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2DACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2DACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2DACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2DACT_A { type Ux = u8 ; } impl CCACT_01_CC2DACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2DACT_A { match self . bits { 0 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED , 1 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH , 2 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW , 3 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_disabled (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_high (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_low (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2DACT` writer - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2DACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2DACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2dact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2UACT` reader - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_R = crate :: FieldReader < CCACT_01_CC2UACT_A > ; # [doc = "CCP Output Action on CC2U event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2UACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2UACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2UACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2UACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2UACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2UACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2UACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2UACT_A { type Ux = u8 ; } impl CCACT_01_CC2UACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2UACT_A { match self . bits { 0 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED , 1 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH , 2 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW , 3 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_disabled (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_high (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_low (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2UACT` writer - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2UACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2UACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2uact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_SWFRCACT` reader - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_R = crate :: FieldReader < CCACT_01_SWFRCACT_A > ; # [doc = "CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_SWFRCACT_A { # [doc = "0: DISABLED"]
CCACT_01_SWFRCACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_SWFRCACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_SWFRCACT_CCP_LOW = 2 , } impl From < CCACT_01_SWFRCACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_SWFRCACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_SWFRCACT_A { type Ux = u8 ; } impl CCACT_01_SWFRCACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCACT_01_SWFRCACT_A > { match self . bits { 0 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) , 1 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) , 2 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) , _ => None , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_disabled (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_high (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_low (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW } } # [doc = "Field `CCACT_01_SWFRCACT` writer - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CCACT_01_SWFRCACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_SWFRCACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_swfrcact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) } } impl R { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
pub fn ccact_01_zact (& self) -> CCACT_01_ZACT_R { CCACT_01_ZACT_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
pub fn ccact_01_lact (& self) -> CCACT_01_LACT_R { CCACT_01_LACT_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
pub fn ccact_01_cdact (& self) -> CCACT_01_CDACT_R { CCACT_01_CDACT_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
pub fn ccact_01_cuact (& self) -> CCACT_01_CUACT_R { CCACT_01_CUACT_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
pub fn ccact_01_cc2dact (& self) -> CCACT_01_CC2DACT_R { CCACT_01_CC2DACT_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
pub fn ccact_01_cc2uact (& self) -> CCACT_01_CC2UACT_R { CCACT_01_CC2UACT_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
pub fn ccact_01_swfrcact (& self) -> CCACT_01_SWFRCACT_R { CCACT_01_SWFRCACT_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W < CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W < CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W < CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cuact (& mut self) -> CCACT_01_CUACT_W < CCACT_01_SPEC , 9 > { CCACT_01_CUACT_W :: new (self) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2dact (& mut self) -> CCACT_01_CC2DACT_W < CCACT_01_SPEC , 12 > { CCACT_01_CC2DACT_W :: new (self) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2uact (& mut self) -> CCACT_01_CC2UACT_W < CCACT_01_SPEC , 15 > { CCACT_01_CC2UACT_W :: new (self) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
# [must_use]
pub fn ccact_01_swfrcact (& mut self) -> CCACT_01_SWFRCACT_W < CCACT_01_SPEC , 28 > { CCACT_01_SWFRCACT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCACT_01_SPEC ; impl crate :: RegisterSpec for CCACT_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccact_01::R`](R) reader structure"]
impl crate :: Readable for CCACT_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccact_01::W`](W) writer structure"]
impl crate :: Writable for CCACT_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCACT_01[%s]
to value 0"]
impl crate :: Resettable for CCACT_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IFCTL_01 (rw) register accessor: Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifctl_01`]
module"]
pub type IFCTL_01 = crate :: Reg < ifctl_01 :: IFCTL_01_SPEC > ; # [doc = "Input Filter Control Register"]
pub mod ifctl_01 { # [doc = "Register `IFCTL_01[%s]` reader"]
pub type R = crate :: R < IFCTL_01_SPEC > ; # [doc = "Register `IFCTL_01[%s]` writer"]
pub type W = crate :: W < IFCTL_01_SPEC > ; # [doc = "Field `IFCTL_01_ISEL` reader - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_R = crate :: FieldReader < IFCTL_01_ISEL_A > ; # [doc = "Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_ISEL_A { # [doc = "0: CCPX_INPUT"]
IFCTL_01_ISEL_CCPX_INPUT = 0 , # [doc = "1: CCPX_INPUT_PAIR"]
IFCTL_01_ISEL_CCPX_INPUT_PAIR = 1 , # [doc = "2: CCP0_INPUT"]
IFCTL_01_ISEL_CCP0_INPUT = 2 , # [doc = "3: TRIG_INPUT"]
IFCTL_01_ISEL_TRIG_INPUT = 3 , # [doc = "4: CCP_XOR"]
IFCTL_01_ISEL_CCP_XOR = 4 , # [doc = "5: FSUB0"]
IFCTL_01_ISEL_FSUB0 = 5 , # [doc = "6: FSUB1"]
IFCTL_01_ISEL_FSUB1 = 6 , # [doc = "7: COMP0"]
IFCTL_01_ISEL_COMP0 = 7 , # [doc = "8: COMP1"]
IFCTL_01_ISEL_COMP1 = 8 , # [doc = "9: COMP2"]
IFCTL_01_ISEL_COMP2 = 9 , } impl From < IFCTL_01_ISEL_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_ISEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_ISEL_A { type Ux = u8 ; } impl IFCTL_01_ISEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_ISEL_A > { match self . bits { 0 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) , 1 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) , 2 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) , 3 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) , 4 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) , 5 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) , 6 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) , 7 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) , 8 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) , 9 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) , _ => None , } } # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input_pair (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp0_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_trig_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp_xor (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1 } # [doc = "COMP0"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0 } # [doc = "COMP1"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1 } # [doc = "COMP2"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp2 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2 } } # [doc = "Field `IFCTL_01_ISEL` writer - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , IFCTL_01_ISEL_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_ISEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input_pair (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_trig_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn ifctl_01_isel_ccp_xor (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) } # [doc = "FSUB0"]
# [inline (always)]
pub fn ifctl_01_isel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn ifctl_01_isel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) } # [doc = "COMP0"]
# [inline (always)]
pub fn ifctl_01_isel_comp0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) } # [doc = "COMP1"]
# [inline (always)]
pub fn ifctl_01_isel_comp1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) } # [doc = "COMP2"]
# [inline (always)]
pub fn ifctl_01_isel_comp2 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) } } # [doc = "Field `IFCTL_01_INV` reader - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_R = crate :: BitReader < IFCTL_01_INV_A > ; # [doc = "Input Inversion This bit controls whether the selected input is inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_INV_A { # [doc = "0: NOINVERT"]
IFCTL_01_INV_NOINVERT = 0 , # [doc = "1: INVERT"]
IFCTL_01_INV_INVERT = 1 , } impl From < IFCTL_01_INV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_INV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_INV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_INV_A { match self . bits { false => IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT , true => IFCTL_01_INV_A :: IFCTL_01_INV_INVERT , } } # [doc = "NOINVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_noinvert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT } # [doc = "INVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_invert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_INVERT } } # [doc = "Field `IFCTL_01_INV` writer - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_INV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_INV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINVERT"]
# [inline (always)]
pub fn ifctl_01_inv_noinvert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT) } # [doc = "INVERT"]
# [inline (always)]
pub fn ifctl_01_inv_invert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_INVERT) } } # [doc = "Field `IFCTL_01_FP` reader - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_R = crate :: FieldReader < IFCTL_01_FP_A > ; # [doc = "Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_FP_A { # [doc = "0: _3"]
IFCTL_01_FP__3 = 0 , # [doc = "1: _5"]
IFCTL_01_FP__5 = 1 , # [doc = "2: _8"]
IFCTL_01_FP__8 = 2 , } impl From < IFCTL_01_FP_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_FP_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_FP_A { type Ux = u8 ; } impl IFCTL_01_FP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_FP_A > { match self . bits { 0 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__3) , 1 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__5) , 2 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__8) , _ => None , } } # [doc = "_3"]
# [inline (always)]
pub fn is_ifctl_01_fp__3 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__3 } # [doc = "_5"]
# [inline (always)]
pub fn is_ifctl_01_fp__5 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__5 } # [doc = "_8"]
# [inline (always)]
pub fn is_ifctl_01_fp__8 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__8 } } # [doc = "Field `IFCTL_01_FP` writer - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , IFCTL_01_FP_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_3"]
# [inline (always)]
pub fn ifctl_01_fp__3 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__3) } # [doc = "_5"]
# [inline (always)]
pub fn ifctl_01_fp__5 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__5) } # [doc = "_8"]
# [inline (always)]
pub fn ifctl_01_fp__8 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__8) } } # [doc = "Field `IFCTL_01_CPV` reader - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_R = crate :: BitReader < IFCTL_01_CPV_A > ; # [doc = "Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_CPV_A { # [doc = "0: CONSECUTIVE"]
IFCTL_01_CPV_CONSECUTIVE = 0 , # [doc = "1: VOTING"]
IFCTL_01_CPV_VOTING = 1 , } impl From < IFCTL_01_CPV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_CPV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_CPV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_CPV_A { match self . bits { false => IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE , true => IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING , } } # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn is_ifctl_01_cpv_consecutive (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE } # [doc = "VOTING"]
# [inline (always)]
pub fn is_ifctl_01_cpv_voting (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING } } # [doc = "Field `IFCTL_01_CPV` writer - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_CPV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_CPV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn ifctl_01_cpv_consecutive (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE) } # [doc = "VOTING"]
# [inline (always)]
pub fn ifctl_01_cpv_voting (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING) } } # [doc = "Field `IFCTL_01_FE` reader - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_R = crate :: BitReader < IFCTL_01_FE_A > ; # [doc = "Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_FE_A { # [doc = "0: DISABLED"]
IFCTL_01_FE_DISABLED = 0 , # [doc = "1: ENABLED"]
IFCTL_01_FE_ENABLED = 1 , } impl From < IFCTL_01_FE_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_FE_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_FE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_FE_A { match self . bits { false => IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED , true => IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_disabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_enabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED } } # [doc = "Field `IFCTL_01_FE` writer - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_FE_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ifctl_01_fe_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ifctl_01_fe_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED) } } impl R { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
pub fn ifctl_01_isel (& self) -> IFCTL_01_ISEL_R { IFCTL_01_ISEL_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
pub fn ifctl_01_inv (& self) -> IFCTL_01_INV_R { IFCTL_01_INV_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
pub fn ifctl_01_fp (& self) -> IFCTL_01_FP_R { IFCTL_01_FP_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
pub fn ifctl_01_cpv (& self) -> IFCTL_01_CPV_R { IFCTL_01_CPV_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
pub fn ifctl_01_fe (& self) -> IFCTL_01_FE_R { IFCTL_01_FE_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
# [must_use]
pub fn ifctl_01_isel (& mut self) -> IFCTL_01_ISEL_W < IFCTL_01_SPEC , 0 > { IFCTL_01_ISEL_W :: new (self) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_inv (& mut self) -> IFCTL_01_INV_W < IFCTL_01_SPEC , 7 > { IFCTL_01_INV_W :: new (self) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fp (& mut self) -> IFCTL_01_FP_W < IFCTL_01_SPEC , 8 > { IFCTL_01_FP_W :: new (self) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_cpv (& mut self) -> IFCTL_01_CPV_W < IFCTL_01_SPEC , 11 > { IFCTL_01_CPV_W :: new (self) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fe (& mut self) -> IFCTL_01_FE_W < IFCTL_01_SPEC , 12 > { IFCTL_01_FE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IFCTL_01_SPEC ; impl crate :: RegisterSpec for IFCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifctl_01::R`](R) reader structure"]
impl crate :: Readable for IFCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifctl_01::W`](W) writer structure"]
impl crate :: Writable for IFCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFCTL_01[%s]
to value 0"]
impl crate :: Resettable for IFCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TSEL (rw) register accessor: Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsel`]
module"]
pub type TSEL = crate :: Reg < tsel :: TSEL_SPEC > ; # [doc = "Trigger Select"]
pub mod tsel { # [doc = "Register `TSEL` reader"]
pub type R = crate :: R < TSEL_SPEC > ; # [doc = "Register `TSEL` writer"]
pub type W = crate :: W < TSEL_SPEC > ; # [doc = "Field `TSEL_ETSEL` reader - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_R = crate :: FieldReader < TSEL_ETSEL_A > ; # [doc = "External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum TSEL_ETSEL_A { # [doc = "0: TRIG0"]
TSEL_ETSEL_TRIG0 = 0 , # [doc = "1: TRIG1"]
TSEL_ETSEL_TRIG1 = 1 , # [doc = "2: TRIG2"]
TSEL_ETSEL_TRIG2 = 2 , # [doc = "3: TRIG3"]
TSEL_ETSEL_TRIG3 = 3 , # [doc = "4: TRIG4"]
TSEL_ETSEL_TRIG4 = 4 , # [doc = "5: TRIG5"]
TSEL_ETSEL_TRIG5 = 5 , # [doc = "6: TRIG6"]
TSEL_ETSEL_TRIG6 = 6 , # [doc = "7: TRIG7"]
TSEL_ETSEL_TRIG7 = 7 , # [doc = "8: TRIG8"]
TSEL_ETSEL_TRIG8 = 8 , # [doc = "9: TRIG9"]
TSEL_ETSEL_TRIG9 = 9 , # [doc = "10: TRIG10"]
TSEL_ETSEL_TRIG10 = 10 , # [doc = "11: TRIG11"]
TSEL_ETSEL_TRIG11 = 11 , # [doc = "12: TRIG12"]
TSEL_ETSEL_TRIG12 = 12 , # [doc = "13: TRIG13"]
TSEL_ETSEL_TRIG13 = 13 , # [doc = "14: TRIG14"]
TSEL_ETSEL_TRIG14 = 14 , # [doc = "15: TRIG15"]
TSEL_ETSEL_TRIG15 = 15 , # [doc = "16: TRIG_SUB0"]
TSEL_ETSEL_TRIG_SUB0 = 16 , # [doc = "17: TRIG_SUB1"]
TSEL_ETSEL_TRIG_SUB1 = 17 , } impl From < TSEL_ETSEL_A > for u8 { # [inline (always)]
fn from (variant : TSEL_ETSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for TSEL_ETSEL_A { type Ux = u8 ; } impl TSEL_ETSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < TSEL_ETSEL_A > { match self . bits { 0 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) , 1 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) , 2 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) , 3 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) , 4 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) , 5 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) , 6 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) , 7 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) , 8 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) , 9 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) , 10 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) , 11 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) , 12 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) , 13 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) , 14 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) , 15 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) , 16 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) , 17 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) , _ => None , } } # [doc = "TRIG0"]
# [inline (always)]
pub fn is_tsel_etsel_trig0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0 } # [doc = "TRIG1"]
# [inline (always)]
pub fn is_tsel_etsel_trig1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1 } # [doc = "TRIG2"]
# [inline (always)]
pub fn is_tsel_etsel_trig2 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2 } # [doc = "TRIG3"]
# [inline (always)]
pub fn is_tsel_etsel_trig3 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3 } # [doc = "TRIG4"]
# [inline (always)]
pub fn is_tsel_etsel_trig4 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4 } # [doc = "TRIG5"]
# [inline (always)]
pub fn is_tsel_etsel_trig5 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5 } # [doc = "TRIG6"]
# [inline (always)]
pub fn is_tsel_etsel_trig6 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6 } # [doc = "TRIG7"]
# [inline (always)]
pub fn is_tsel_etsel_trig7 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7 } # [doc = "TRIG8"]
# [inline (always)]
pub fn is_tsel_etsel_trig8 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8 } # [doc = "TRIG9"]
# [inline (always)]
pub fn is_tsel_etsel_trig9 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9 } # [doc = "TRIG10"]
# [inline (always)]
pub fn is_tsel_etsel_trig10 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10 } # [doc = "TRIG11"]
# [inline (always)]
pub fn is_tsel_etsel_trig11 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11 } # [doc = "TRIG12"]
# [inline (always)]
pub fn is_tsel_etsel_trig12 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12 } # [doc = "TRIG13"]
# [inline (always)]
pub fn is_tsel_etsel_trig13 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13 } # [doc = "TRIG14"]
# [inline (always)]
pub fn is_tsel_etsel_trig14 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14 } # [doc = "TRIG15"]
# [inline (always)]
pub fn is_tsel_etsel_trig15 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15 } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0 } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1 } } # [doc = "Field `TSEL_ETSEL` writer - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , TSEL_ETSEL_A > ; impl < 'a , REG , const O : u8 > TSEL_ETSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TRIG0"]
# [inline (always)]
pub fn tsel_etsel_trig0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) } # [doc = "TRIG1"]
# [inline (always)]
pub fn tsel_etsel_trig1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) } # [doc = "TRIG2"]
# [inline (always)]
pub fn tsel_etsel_trig2 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) } # [doc = "TRIG3"]
# [inline (always)]
pub fn tsel_etsel_trig3 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) } # [doc = "TRIG4"]
# [inline (always)]
pub fn tsel_etsel_trig4 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) } # [doc = "TRIG5"]
# [inline (always)]
pub fn tsel_etsel_trig5 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) } # [doc = "TRIG6"]
# [inline (always)]
pub fn tsel_etsel_trig6 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) } # [doc = "TRIG7"]
# [inline (always)]
pub fn tsel_etsel_trig7 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) } # [doc = "TRIG8"]
# [inline (always)]
pub fn tsel_etsel_trig8 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) } # [doc = "TRIG9"]
# [inline (always)]
pub fn tsel_etsel_trig9 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) } # [doc = "TRIG10"]
# [inline (always)]
pub fn tsel_etsel_trig10 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) } # [doc = "TRIG11"]
# [inline (always)]
pub fn tsel_etsel_trig11 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) } # [doc = "TRIG12"]
# [inline (always)]
pub fn tsel_etsel_trig12 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) } # [doc = "TRIG13"]
# [inline (always)]
pub fn tsel_etsel_trig13 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) } # [doc = "TRIG14"]
# [inline (always)]
pub fn tsel_etsel_trig14 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) } # [doc = "TRIG15"]
# [inline (always)]
pub fn tsel_etsel_trig15 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn tsel_etsel_trig_sub0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn tsel_etsel_trig_sub1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) } } # [doc = "Field `TSEL_TE` reader - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_R = crate :: BitReader < TSEL_TE_A > ; # [doc = "Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TSEL_TE_A { # [doc = "0: DISABLED"]
TSEL_TE_DISABLED = 0 , # [doc = "1: ENABLED"]
TSEL_TE_ENABLED = 1 , } impl From < TSEL_TE_A > for bool { # [inline (always)]
fn from (variant : TSEL_TE_A) -> Self { variant as u8 != 0 } } impl TSEL_TE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TSEL_TE_A { match self . bits { false => TSEL_TE_A :: TSEL_TE_DISABLED , true => TSEL_TE_A :: TSEL_TE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_tsel_te_disabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_tsel_te_enabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_ENABLED } } # [doc = "Field `TSEL_TE` writer - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TSEL_TE_A > ; impl < 'a , REG , const O : u8 > TSEL_TE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn tsel_te_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn tsel_te_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_ENABLED) } } impl R { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
pub fn tsel_etsel (& self) -> TSEL_ETSEL_R { TSEL_ETSEL_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
pub fn tsel_te (& self) -> TSEL_TE_R { TSEL_TE_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
# [must_use]
pub fn tsel_etsel (& mut self) -> TSEL_ETSEL_W < TSEL_SPEC , 0 > { TSEL_ETSEL_W :: new (self) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
# [must_use]
pub fn tsel_te (& mut self) -> TSEL_TE_W < TSEL_SPEC , 9 > { TSEL_TE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TSEL_SPEC ; impl crate :: RegisterSpec for TSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`tsel::R`](R) reader structure"]
impl crate :: Readable for TSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`tsel::W`](W) writer structure"]
impl crate :: Writable for TSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TSEL to value 0"]
impl crate :: Resettable for TSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct TIMG4 { _marker : PhantomData < * const () > } unsafe impl Send for TIMG4 { } impl TIMG4 { # [doc = r"Pointer to the register block"]
pub const PTR : * const timg4 :: RegisterBlock = 0x4008_c000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const timg4 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIMG4 { type Target = timg4 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIMG4 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIMG4") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod timg4 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subsciber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , _reserved2 : [u8 ; 0x3c]
, # [doc = "0x444 - Publisher Port 0"]
pub fpub_0 : FPUB_0 , # [doc = "0x448 - Publisher Port 1"]
pub fpub_1 : FPUB_1 , _reserved4 : [u8 ; 0x03b4]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved6 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved7 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1008 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved9 : [u8 ; 0x0c]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved16 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved17 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - CCP Direction"]
pub ccpd : CCPD , # [doc = "0x1104 - Output Disable"]
pub odis : ODIS , # [doc = "0x1108 - Counter Clock Control Register"]
pub cclkctl : CCLKCTL , # [doc = "0x110c - Clock Prescale Register"]
pub cps : CPS , # [doc = "0x1110 - Clock prescale count status register"]
pub cpsv : CPSV , # [doc = "0x1114 - Timer Cross Trigger Control Register"]
pub cttrigctl : CTTRIGCTL , _reserved24 : [u8 ; 0x04]
, # [doc = "0x111c - Timer Cross Trigger Register"]
pub cttrig : CTTRIG , _reserved25 : [u8 ; 0x04]
, # [doc = "0x1124 - Shadow to active load mask"]
pub gctl : GCTL , _reserved26 : [u8 ; 0x06d8]
, # [doc = "0x1800 - Counter Register"]
pub ctr : CTR , # [doc = "0x1804 - Counter Control Register"]
pub ctrctl : CTRCTL , # [doc = "0x1808 - Load Register"]
pub load : LOAD , _reserved29 : [u8 ; 0x04]
, # [doc = "0x1810..0x1818 - Capture or Compare Register 0 to Capture or Compare Register 1"]
pub cc_01 : [CC_01 ; 2]
, _reserved30 : [u8 ; 0x18]
, # [doc = "0x1830..0x1838 - Capture or Compare Control Registers"]
pub ccctl_01 : [CCCTL_01 ; 2]
, _reserved31 : [u8 ; 0x18]
, # [doc = "0x1850..0x1858 - CCP Output Control Registers"]
pub octl_01 : [OCTL_01 ; 2]
, _reserved32 : [u8 ; 0x18]
, # [doc = "0x1870..0x1878 - Capture or Compare Action Registers"]
pub ccact_01 : [CCACT_01 ; 2]
, _reserved33 : [u8 ; 0x08]
, # [doc = "0x1880..0x1888 - Input Filter Control Register"]
pub ifctl_01 : [IFCTL_01 ; 2]
, _reserved34 : [u8 ; 0x28]
, # [doc = "0x18b0 - Trigger Select"]
pub tsel : TSEL , } # [doc = "FSUB_0 (rw) register accessor: Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subsciber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_0 (rw) register accessor: Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_0`]
module"]
pub type FPUB_0 = crate :: Reg < fpub_0 :: FPUB_0_SPEC > ; # [doc = "Publisher Port 0"]
pub mod fpub_0 { # [doc = "Register `FPUB_0` reader"]
pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"]
pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"]
impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"]
impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"]
impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher Port 1"]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Interrupt index status"]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: Z"]
IIDX_STAT_Z = 1 , # [doc = "2: L"]
IIDX_STAT_L = 2 , # [doc = "5: CCD0"]
IIDX_STAT_CCD0 = 5 , # [doc = "6: CCD1"]
IIDX_STAT_CCD1 = 6 , # [doc = "7: CCD2"]
IIDX_STAT_CCD2 = 7 , # [doc = "8: CCD3"]
IIDX_STAT_CCD3 = 8 , # [doc = "9: CCU0"]
IIDX_STAT_CCU0 = 9 , # [doc = "10: CCU1"]
IIDX_STAT_CCU1 = 10 , # [doc = "11: CCU2"]
IIDX_STAT_CCU2 = 11 , # [doc = "12: CCU3"]
IIDX_STAT_CCU3 = 12 , # [doc = "13: CCD4"]
IIDX_STAT_CCD4 = 13 , # [doc = "14: CCD5"]
IIDX_STAT_CCD5 = 14 , # [doc = "15: CCU4"]
IIDX_STAT_CCU4 = 15 , # [doc = "16: CCU5"]
IIDX_STAT_CCU5 = 16 , # [doc = "25: F"]
IIDX_STAT_F = 25 , # [doc = "26: TOV"]
IIDX_STAT_TOV = 26 , # [doc = "27: REPC"]
IIDX_STAT_REPC = 27 , # [doc = "28: DC"]
IIDX_STAT_DC = 28 , # [doc = "29: QEIERR"]
IIDX_STAT_QEIERR = 29 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_Z) , 2 => Some (IIDX_STAT_A :: IIDX_STAT_L) , 5 => Some (IIDX_STAT_A :: IIDX_STAT_CCD0) , 6 => Some (IIDX_STAT_A :: IIDX_STAT_CCD1) , 7 => Some (IIDX_STAT_A :: IIDX_STAT_CCD2) , 8 => Some (IIDX_STAT_A :: IIDX_STAT_CCD3) , 9 => Some (IIDX_STAT_A :: IIDX_STAT_CCU0) , 10 => Some (IIDX_STAT_A :: IIDX_STAT_CCU1) , 11 => Some (IIDX_STAT_A :: IIDX_STAT_CCU2) , 12 => Some (IIDX_STAT_A :: IIDX_STAT_CCU3) , 13 => Some (IIDX_STAT_A :: IIDX_STAT_CCD4) , 14 => Some (IIDX_STAT_A :: IIDX_STAT_CCD5) , 15 => Some (IIDX_STAT_A :: IIDX_STAT_CCU4) , 16 => Some (IIDX_STAT_A :: IIDX_STAT_CCU5) , 25 => Some (IIDX_STAT_A :: IIDX_STAT_F) , 26 => Some (IIDX_STAT_A :: IIDX_STAT_TOV) , 27 => Some (IIDX_STAT_A :: IIDX_STAT_REPC) , 28 => Some (IIDX_STAT_A :: IIDX_STAT_DC) , 29 => Some (IIDX_STAT_A :: IIDX_STAT_QEIERR) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "Z"]
# [inline (always)]
pub fn is_iidx_stat_z (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_Z } # [doc = "L"]
# [inline (always)]
pub fn is_iidx_stat_l (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_iidx_stat_ccd0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_iidx_stat_ccd1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_iidx_stat_ccd2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_iidx_stat_ccd3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_iidx_stat_ccu0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_iidx_stat_ccu1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_iidx_stat_ccu2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_iidx_stat_ccu3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU3 } # [doc = "CCD4"]
# [inline (always)]
pub fn is_iidx_stat_ccd4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD4 } # [doc = "CCD5"]
# [inline (always)]
pub fn is_iidx_stat_ccd5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD5 } # [doc = "CCU4"]
# [inline (always)]
pub fn is_iidx_stat_ccu4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU4 } # [doc = "CCU5"]
# [inline (always)]
pub fn is_iidx_stat_ccu5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU5 } # [doc = "F"]
# [inline (always)]
pub fn is_iidx_stat_f (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_F } # [doc = "TOV"]
# [inline (always)]
pub fn is_iidx_stat_tov (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_TOV } # [doc = "REPC"]
# [inline (always)]
pub fn is_iidx_stat_repc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_REPC } # [doc = "DC"]
# [inline (always)]
pub fn is_iidx_stat_dc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DC } # [doc = "QEIERR"]
# [inline (always)]
pub fn is_iidx_stat_qeierr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_QEIERR } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_Z` reader - Zero Event mask"]
pub type IMASK_Z_R = crate :: BitReader < IMASK_Z_A > ; # [doc = "Zero Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_Z_A { # [doc = "0: CLR"]
IMASK_Z_CLR = 0 , # [doc = "1: SET"]
IMASK_Z_SET = 1 , } impl From < IMASK_Z_A > for bool { # [inline (always)]
fn from (variant : IMASK_Z_A) -> Self { variant as u8 != 0 } } impl IMASK_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_Z_A { match self . bits { false => IMASK_Z_A :: IMASK_Z_CLR , true => IMASK_Z_A :: IMASK_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_z_clr (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_z_set (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_SET } } # [doc = "Field `IMASK_Z` writer - Zero Event mask"]
pub type IMASK_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_Z_A > ; impl < 'a , REG , const O : u8 > IMASK_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_SET) } } # [doc = "Field `IMASK_L` reader - Load Event mask"]
pub type IMASK_L_R = crate :: BitReader < IMASK_L_A > ; # [doc = "Load Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_L_A { # [doc = "0: CLR"]
IMASK_L_CLR = 0 , # [doc = "1: SET"]
IMASK_L_SET = 1 , } impl From < IMASK_L_A > for bool { # [inline (always)]
fn from (variant : IMASK_L_A) -> Self { variant as u8 != 0 } } impl IMASK_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_L_A { match self . bits { false => IMASK_L_A :: IMASK_L_CLR , true => IMASK_L_A :: IMASK_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_l_clr (& self) -> bool { * self == IMASK_L_A :: IMASK_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_l_set (& self) -> bool { * self == IMASK_L_A :: IMASK_L_SET } } # [doc = "Field `IMASK_L` writer - Load Event mask"]
pub type IMASK_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_L_A > ; impl < 'a , REG , const O : u8 > IMASK_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_SET) } } # [doc = "Field `IMASK_CCD0` reader - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_R = crate :: BitReader < IMASK_CCD0_A > ; # [doc = "Capture or Compare DN event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD0_A { # [doc = "0: CLR"]
IMASK_CCD0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD0_SET = 1 , } impl From < IMASK_CCD0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD0_A { match self . bits { false => IMASK_CCD0_A :: IMASK_CCD0_CLR , true => IMASK_CCD0_A :: IMASK_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd0_clr (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd0_set (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_SET } } # [doc = "Field `IMASK_CCD0` writer - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_SET) } } # [doc = "Field `IMASK_CCD1` reader - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_R = crate :: BitReader < IMASK_CCD1_A > ; # [doc = "Capture or Compare DN event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD1_A { # [doc = "0: CLR"]
IMASK_CCD1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD1_SET = 1 , } impl From < IMASK_CCD1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD1_A { match self . bits { false => IMASK_CCD1_A :: IMASK_CCD1_CLR , true => IMASK_CCD1_A :: IMASK_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd1_clr (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd1_set (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_SET } } # [doc = "Field `IMASK_CCD1` writer - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_SET) } } # [doc = "Field `IMASK_CCU0` reader - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_R = crate :: BitReader < IMASK_CCU0_A > ; # [doc = "Capture or Compare UP event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU0_A { # [doc = "0: CLR"]
IMASK_CCU0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU0_SET = 1 , } impl From < IMASK_CCU0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU0_A { match self . bits { false => IMASK_CCU0_A :: IMASK_CCU0_CLR , true => IMASK_CCU0_A :: IMASK_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu0_clr (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu0_set (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_SET } } # [doc = "Field `IMASK_CCU0` writer - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_SET) } } # [doc = "Field `IMASK_CCU1` reader - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_R = crate :: BitReader < IMASK_CCU1_A > ; # [doc = "Capture or Compare UP event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU1_A { # [doc = "0: CLR"]
IMASK_CCU1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU1_SET = 1 , } impl From < IMASK_CCU1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU1_A { match self . bits { false => IMASK_CCU1_A :: IMASK_CCU1_CLR , true => IMASK_CCU1_A :: IMASK_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu1_clr (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu1_set (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_SET } } # [doc = "Field `IMASK_CCU1` writer - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_SET) } } # [doc = "Field `IMASK_TOV` reader - Trigger Overflow Event mask"]
pub type IMASK_TOV_R = crate :: BitReader < IMASK_TOV_A > ; # [doc = "Trigger Overflow Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_TOV_A { # [doc = "0: CLR"]
IMASK_TOV_CLR = 0 , # [doc = "1: SET"]
IMASK_TOV_SET = 1 , } impl From < IMASK_TOV_A > for bool { # [inline (always)]
fn from (variant : IMASK_TOV_A) -> Self { variant as u8 != 0 } } impl IMASK_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_TOV_A { match self . bits { false => IMASK_TOV_A :: IMASK_TOV_CLR , true => IMASK_TOV_A :: IMASK_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_tov_clr (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_tov_set (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_SET } } # [doc = "Field `IMASK_TOV` writer - Trigger Overflow Event mask"]
pub type IMASK_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TOV_A > ; impl < 'a , REG , const O : u8 > IMASK_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_SET) } } impl R { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
pub fn imask_z (& self) -> IMASK_Z_R { IMASK_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
pub fn imask_l (& self) -> IMASK_L_R { IMASK_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
pub fn imask_ccd0 (& self) -> IMASK_CCD0_R { IMASK_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
pub fn imask_ccd1 (& self) -> IMASK_CCD1_R { IMASK_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
pub fn imask_ccu0 (& self) -> IMASK_CCU0_R { IMASK_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
pub fn imask_ccu1 (& self) -> IMASK_CCU1_R { IMASK_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
pub fn imask_tov (& self) -> IMASK_TOV_R { IMASK_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_z (& mut self) -> IMASK_Z_W < IMASK_SPEC , 0 > { IMASK_Z_W :: new (self) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_l (& mut self) -> IMASK_L_W < IMASK_SPEC , 1 > { IMASK_L_W :: new (self) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccd0 (& mut self) -> IMASK_CCD0_W < IMASK_SPEC , 4 > { IMASK_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccd1 (& mut self) -> IMASK_CCD1_W < IMASK_SPEC , 5 > { IMASK_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccu0 (& mut self) -> IMASK_CCU0_W < IMASK_SPEC , 8 > { IMASK_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccu1 (& mut self) -> IMASK_CCU1_W < IMASK_SPEC , 9 > { IMASK_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_tov (& mut self) -> IMASK_TOV_W < IMASK_SPEC , 25 > { IMASK_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_Z` reader - Zero event generated an interrupt."]
pub type RIS_Z_R = crate :: BitReader < RIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_Z_A { # [doc = "0: CLR"]
RIS_Z_CLR = 0 , # [doc = "1: SET"]
RIS_Z_SET = 1 , } impl From < RIS_Z_A > for bool { # [inline (always)]
fn from (variant : RIS_Z_A) -> Self { variant as u8 != 0 } } impl RIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_Z_A { match self . bits { false => RIS_Z_A :: RIS_Z_CLR , true => RIS_Z_A :: RIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_z_clr (& self) -> bool { * self == RIS_Z_A :: RIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_z_set (& self) -> bool { * self == RIS_Z_A :: RIS_Z_SET } } # [doc = "Field `RIS_L` reader - Load event generated an interrupt."]
pub type RIS_L_R = crate :: BitReader < RIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_L_A { # [doc = "0: CLR"]
RIS_L_CLR = 0 , # [doc = "1: SET"]
RIS_L_SET = 1 , } impl From < RIS_L_A > for bool { # [inline (always)]
fn from (variant : RIS_L_A) -> Self { variant as u8 != 0 } } impl RIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_L_A { match self . bits { false => RIS_L_A :: RIS_L_CLR , true => RIS_L_A :: RIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_l_clr (& self) -> bool { * self == RIS_L_A :: RIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_l_set (& self) -> bool { * self == RIS_L_A :: RIS_L_SET } } # [doc = "Field `RIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type RIS_CCD0_R = crate :: BitReader < RIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD0_A { # [doc = "0: CLR"]
RIS_CCD0_CLR = 0 , # [doc = "1: SET"]
RIS_CCD0_SET = 1 , } impl From < RIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD0_A) -> Self { variant as u8 != 0 } } impl RIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD0_A { match self . bits { false => RIS_CCD0_A :: RIS_CCD0_CLR , true => RIS_CCD0_A :: RIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd0_clr (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd0_set (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_SET } } # [doc = "Field `RIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type RIS_CCD1_R = crate :: BitReader < RIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD1_A { # [doc = "0: CLR"]
RIS_CCD1_CLR = 0 , # [doc = "1: SET"]
RIS_CCD1_SET = 1 , } impl From < RIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD1_A) -> Self { variant as u8 != 0 } } impl RIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD1_A { match self . bits { false => RIS_CCD1_A :: RIS_CCD1_CLR , true => RIS_CCD1_A :: RIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd1_clr (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd1_set (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_SET } } # [doc = "Field `RIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type RIS_CCU0_R = crate :: BitReader < RIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU0_A { # [doc = "0: CLR"]
RIS_CCU0_CLR = 0 , # [doc = "1: SET"]
RIS_CCU0_SET = 1 , } impl From < RIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU0_A) -> Self { variant as u8 != 0 } } impl RIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU0_A { match self . bits { false => RIS_CCU0_A :: RIS_CCU0_CLR , true => RIS_CCU0_A :: RIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu0_clr (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu0_set (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_SET } } # [doc = "Field `RIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type RIS_CCU1_R = crate :: BitReader < RIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU1_A { # [doc = "0: CLR"]
RIS_CCU1_CLR = 0 , # [doc = "1: SET"]
RIS_CCU1_SET = 1 , } impl From < RIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU1_A) -> Self { variant as u8 != 0 } } impl RIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU1_A { match self . bits { false => RIS_CCU1_A :: RIS_CCU1_CLR , true => RIS_CCU1_A :: RIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu1_clr (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu1_set (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_SET } } # [doc = "Field `RIS_TOV` reader - Trigger overflow"]
pub type RIS_TOV_R = crate :: BitReader < RIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_TOV_A { # [doc = "0: CLR"]
RIS_TOV_CLR = 0 , # [doc = "1: SET"]
RIS_TOV_SET = 1 , } impl From < RIS_TOV_A > for bool { # [inline (always)]
fn from (variant : RIS_TOV_A) -> Self { variant as u8 != 0 } } impl RIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_TOV_A { match self . bits { false => RIS_TOV_A :: RIS_TOV_CLR , true => RIS_TOV_A :: RIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_tov_clr (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_tov_set (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn ris_z (& self) -> RIS_Z_R { RIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn ris_l (& self) -> RIS_L_R { RIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccd0 (& self) -> RIS_CCD0_R { RIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccd1 (& self) -> RIS_CCD1_R { RIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccu0 (& self) -> RIS_CCU0_R { RIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccu1 (& self) -> RIS_CCU1_R { RIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn ris_tov (& self) -> RIS_TOV_R { RIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_Z` reader - Zero event generated an interrupt."]
pub type MIS_Z_R = crate :: BitReader < MIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_Z_A { # [doc = "0: CLR"]
MIS_Z_CLR = 0 , # [doc = "1: SET"]
MIS_Z_SET = 1 , } impl From < MIS_Z_A > for bool { # [inline (always)]
fn from (variant : MIS_Z_A) -> Self { variant as u8 != 0 } } impl MIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_Z_A { match self . bits { false => MIS_Z_A :: MIS_Z_CLR , true => MIS_Z_A :: MIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_z_clr (& self) -> bool { * self == MIS_Z_A :: MIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_z_set (& self) -> bool { * self == MIS_Z_A :: MIS_Z_SET } } # [doc = "Field `MIS_L` reader - Load event generated an interrupt."]
pub type MIS_L_R = crate :: BitReader < MIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_L_A { # [doc = "0: CLR"]
MIS_L_CLR = 0 , # [doc = "1: SET"]
MIS_L_SET = 1 , } impl From < MIS_L_A > for bool { # [inline (always)]
fn from (variant : MIS_L_A) -> Self { variant as u8 != 0 } } impl MIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_L_A { match self . bits { false => MIS_L_A :: MIS_L_CLR , true => MIS_L_A :: MIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_l_clr (& self) -> bool { * self == MIS_L_A :: MIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_l_set (& self) -> bool { * self == MIS_L_A :: MIS_L_SET } } # [doc = "Field `MIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type MIS_CCD0_R = crate :: BitReader < MIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD0_A { # [doc = "0: CLR"]
MIS_CCD0_CLR = 0 , # [doc = "1: SET"]
MIS_CCD0_SET = 1 , } impl From < MIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD0_A) -> Self { variant as u8 != 0 } } impl MIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD0_A { match self . bits { false => MIS_CCD0_A :: MIS_CCD0_CLR , true => MIS_CCD0_A :: MIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd0_clr (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd0_set (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_SET } } # [doc = "Field `MIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type MIS_CCD1_R = crate :: BitReader < MIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD1_A { # [doc = "0: CLR"]
MIS_CCD1_CLR = 0 , # [doc = "1: SET"]
MIS_CCD1_SET = 1 , } impl From < MIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD1_A) -> Self { variant as u8 != 0 } } impl MIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD1_A { match self . bits { false => MIS_CCD1_A :: MIS_CCD1_CLR , true => MIS_CCD1_A :: MIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd1_clr (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd1_set (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_SET } } # [doc = "Field `MIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type MIS_CCU0_R = crate :: BitReader < MIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU0_A { # [doc = "0: CLR"]
MIS_CCU0_CLR = 0 , # [doc = "1: SET"]
MIS_CCU0_SET = 1 , } impl From < MIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU0_A) -> Self { variant as u8 != 0 } } impl MIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU0_A { match self . bits { false => MIS_CCU0_A :: MIS_CCU0_CLR , true => MIS_CCU0_A :: MIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu0_clr (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu0_set (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_SET } } # [doc = "Field `MIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type MIS_CCU1_R = crate :: BitReader < MIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU1_A { # [doc = "0: CLR"]
MIS_CCU1_CLR = 0 , # [doc = "1: SET"]
MIS_CCU1_SET = 1 , } impl From < MIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU1_A) -> Self { variant as u8 != 0 } } impl MIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU1_A { match self . bits { false => MIS_CCU1_A :: MIS_CCU1_CLR , true => MIS_CCU1_A :: MIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu1_clr (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu1_set (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_SET } } # [doc = "Field `MIS_CCD4` reader - Compare down event generated an interrupt CCP4"]
pub type MIS_CCD4_R = crate :: BitReader < MIS_CCD4_A > ; # [doc = "Compare down event generated an interrupt CCP4\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD4_A { # [doc = "0: CLR"]
MIS_CCD4_CLR = 0 , # [doc = "1: SET"]
MIS_CCD4_SET = 1 , } impl From < MIS_CCD4_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD4_A) -> Self { variant as u8 != 0 } } impl MIS_CCD4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD4_A { match self . bits { false => MIS_CCD4_A :: MIS_CCD4_CLR , true => MIS_CCD4_A :: MIS_CCD4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd4_clr (& self) -> bool { * self == MIS_CCD4_A :: MIS_CCD4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd4_set (& self) -> bool { * self == MIS_CCD4_A :: MIS_CCD4_SET } } # [doc = "Field `MIS_CCD5` reader - Compare down event generated an interrupt CCP5"]
pub type MIS_CCD5_R = crate :: BitReader < MIS_CCD5_A > ; # [doc = "Compare down event generated an interrupt CCP5\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD5_A { # [doc = "0: CLR"]
MIS_CCD5_CLR = 0 , # [doc = "1: SET"]
MIS_CCD5_SET = 1 , } impl From < MIS_CCD5_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD5_A) -> Self { variant as u8 != 0 } } impl MIS_CCD5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD5_A { match self . bits { false => MIS_CCD5_A :: MIS_CCD5_CLR , true => MIS_CCD5_A :: MIS_CCD5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd5_clr (& self) -> bool { * self == MIS_CCD5_A :: MIS_CCD5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd5_set (& self) -> bool { * self == MIS_CCD5_A :: MIS_CCD5_SET } } # [doc = "Field `MIS_CCU4` reader - Compare up event generated an interrupt CCP4"]
pub type MIS_CCU4_R = crate :: BitReader < MIS_CCU4_A > ; # [doc = "Compare up event generated an interrupt CCP4\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU4_A { # [doc = "0: CLR"]
MIS_CCU4_CLR = 0 , # [doc = "1: SET"]
MIS_CCU4_SET = 1 , } impl From < MIS_CCU4_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU4_A) -> Self { variant as u8 != 0 } } impl MIS_CCU4_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU4_A { match self . bits { false => MIS_CCU4_A :: MIS_CCU4_CLR , true => MIS_CCU4_A :: MIS_CCU4_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu4_clr (& self) -> bool { * self == MIS_CCU4_A :: MIS_CCU4_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu4_set (& self) -> bool { * self == MIS_CCU4_A :: MIS_CCU4_SET } } # [doc = "Field `MIS_CCU5` reader - Compare up event generated an interrupt CCP5"]
pub type MIS_CCU5_R = crate :: BitReader < MIS_CCU5_A > ; # [doc = "Compare up event generated an interrupt CCP5\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU5_A { # [doc = "0: CLR"]
MIS_CCU5_CLR = 0 , # [doc = "1: SET"]
MIS_CCU5_SET = 1 , } impl From < MIS_CCU5_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU5_A) -> Self { variant as u8 != 0 } } impl MIS_CCU5_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU5_A { match self . bits { false => MIS_CCU5_A :: MIS_CCU5_CLR , true => MIS_CCU5_A :: MIS_CCU5_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu5_clr (& self) -> bool { * self == MIS_CCU5_A :: MIS_CCU5_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu5_set (& self) -> bool { * self == MIS_CCU5_A :: MIS_CCU5_SET } } # [doc = "Field `MIS_TOV` reader - Trigger overflow"]
pub type MIS_TOV_R = crate :: BitReader < MIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_TOV_A { # [doc = "0: CLR"]
MIS_TOV_CLR = 0 , # [doc = "1: SET"]
MIS_TOV_SET = 1 , } impl From < MIS_TOV_A > for bool { # [inline (always)]
fn from (variant : MIS_TOV_A) -> Self { variant as u8 != 0 } } impl MIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_TOV_A { match self . bits { false => MIS_TOV_A :: MIS_TOV_CLR , true => MIS_TOV_A :: MIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_tov_clr (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_tov_set (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn mis_z (& self) -> MIS_Z_R { MIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn mis_l (& self) -> MIS_L_R { MIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccd0 (& self) -> MIS_CCD0_R { MIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccd1 (& self) -> MIS_CCD1_R { MIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccu0 (& self) -> MIS_CCU0_R { MIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccu1 (& self) -> MIS_CCU1_R { MIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 12 - Compare down event generated an interrupt CCP4"]
# [inline (always)]
pub fn mis_ccd4 (& self) -> MIS_CCD4_R { MIS_CCD4_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 13 - Compare down event generated an interrupt CCP5"]
# [inline (always)]
pub fn mis_ccd5 (& self) -> MIS_CCD5_R { MIS_CCD5_R :: new (((self . bits >> 13) & 1) != 0) } # [doc = "Bit 14 - Compare up event generated an interrupt CCP4"]
# [inline (always)]
pub fn mis_ccu4 (& self) -> MIS_CCU4_R { MIS_CCU4_R :: new (((self . bits >> 14) & 1) != 0) } # [doc = "Bit 15 - Compare up event generated an interrupt CCP5"]
# [inline (always)]
pub fn mis_ccu5 (& self) -> MIS_CCU5_R { MIS_CCU5_R :: new (((self . bits >> 15) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn mis_tov (& self) -> MIS_TOV_R { MIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Zero event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_Z_AW { # [doc = "0: NO_EFFECT"]
ISET_Z_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_Z_SET = 1 , } impl From < ISET_Z_AW > for bool { # [inline (always)]
fn from (variant : ISET_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_Z` writer - Zero event SET"]
pub type ISET_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_Z_AW > ; impl < 'a , REG , const O : u8 > ISET_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_SET) } } # [doc = "Load event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_L_AW { # [doc = "0: NO_EFFECT"]
ISET_L_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_L_SET = 1 , } impl From < ISET_L_AW > for bool { # [inline (always)]
fn from (variant : ISET_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_L` writer - Load event SET"]
pub type ISET_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_L_AW > ; impl < 'a , REG , const O : u8 > ISET_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD0_SET = 1 , } impl From < ISET_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD0` writer - Capture or compare down event SET"]
pub type ISET_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD1_SET = 1 , } impl From < ISET_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD1` writer - Capture or compare down event SET"]
pub type ISET_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU0_SET = 1 , } impl From < ISET_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU0` writer - Capture or compare up event SET"]
pub type ISET_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU1_SET = 1 , } impl From < ISET_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU1` writer - Capture or compare up event SET"]
pub type ISET_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_SET) } } # [doc = "Trigger Overflow event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_TOV_AW { # [doc = "0: NO_EFFECT"]
ISET_TOV_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_TOV_SET = 1 , } impl From < ISET_TOV_AW > for bool { # [inline (always)]
fn from (variant : ISET_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_TOV` writer - Trigger Overflow event SET"]
pub type ISET_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_TOV_AW > ; impl < 'a , REG , const O : u8 > ISET_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_SET) } } impl W { # [doc = "Bit 0 - Zero event SET"]
# [inline (always)]
# [must_use]
pub fn iset_z (& mut self) -> ISET_Z_W < ISET_SPEC , 0 > { ISET_Z_W :: new (self) } # [doc = "Bit 1 - Load event SET"]
# [inline (always)]
# [must_use]
pub fn iset_l (& mut self) -> ISET_L_W < ISET_SPEC , 1 > { ISET_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd0 (& mut self) -> ISET_CCD0_W < ISET_SPEC , 4 > { ISET_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd1 (& mut self) -> ISET_CCD1_W < ISET_SPEC , 5 > { ISET_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu0 (& mut self) -> ISET_CCU0_W < ISET_SPEC , 8 > { ISET_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu1 (& mut self) -> ISET_CCU1_W < ISET_SPEC , 9 > { ISET_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event SET"]
# [inline (always)]
# [must_use]
pub fn iset_tov (& mut self) -> ISET_TOV_W < ISET_SPEC , 25 > { ISET_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Zero event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_Z_AW { # [doc = "0: NO_EFFECT"]
ICLR_Z_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_Z_CLR = 1 , } impl From < ICLR_Z_AW > for bool { # [inline (always)]
fn from (variant : ICLR_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_Z` writer - Zero event CLEAR"]
pub type ICLR_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_Z_AW > ; impl < 'a , REG , const O : u8 > ICLR_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_CLR) } } # [doc = "Load event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_L_AW { # [doc = "0: NO_EFFECT"]
ICLR_L_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_L_CLR = 1 , } impl From < ICLR_L_AW > for bool { # [inline (always)]
fn from (variant : ICLR_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_L` writer - Load event CLEAR"]
pub type ICLR_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_L_AW > ; impl < 'a , REG , const O : u8 > ICLR_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD0_CLR = 1 , } impl From < ICLR_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD0` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD1_CLR = 1 , } impl From < ICLR_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD1` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU0_CLR = 1 , } impl From < ICLR_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU0` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU1_CLR = 1 , } impl From < ICLR_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU1` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_CLR) } } # [doc = "Trigger Overflow event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_TOV_AW { # [doc = "0: NO_EFFECT"]
ICLR_TOV_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_TOV_CLR = 1 , } impl From < ICLR_TOV_AW > for bool { # [inline (always)]
fn from (variant : ICLR_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_TOV` writer - Trigger Overflow event CLEAR"]
pub type ICLR_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_TOV_AW > ; impl < 'a , REG , const O : u8 > ICLR_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_CLR) } } impl W { # [doc = "Bit 0 - Zero event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_z (& mut self) -> ICLR_Z_W < ICLR_SPEC , 0 > { ICLR_Z_W :: new (self) } # [doc = "Bit 1 - Load event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_l (& mut self) -> ICLR_L_W < ICLR_SPEC , 1 > { ICLR_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd0 (& mut self) -> ICLR_CCD0_W < ICLR_SPEC , 4 > { ICLR_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd1 (& mut self) -> ICLR_CCD1_W < ICLR_SPEC , 5 > { ICLR_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu0 (& mut self) -> ICLR_CCU0_W < ICLR_SPEC , 8 > { ICLR_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu1 (& mut self) -> ICLR_CCU1_W < ICLR_SPEC , 9 > { ICLR_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_tov (& mut self) -> ICLR_TOV_W < ICLR_SPEC , 25 > { ICLR_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_EVT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
pub type EVT_MODE_EVT0_CFG_R = crate :: FieldReader < EVT_MODE_EVT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_software (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
# [inline (always)]
pub fn evt_mode_evt0_cfg (& self) -> EVT_MODE_EVT0_CFG_R { EVT_MODE_EVT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0x29"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0x29 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCPD (rw) register accessor: CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccpd`]
module"]
pub type CCPD = crate :: Reg < ccpd :: CCPD_SPEC > ; # [doc = "CCP Direction"]
pub mod ccpd { # [doc = "Register `CCPD` reader"]
pub type R = crate :: R < CCPD_SPEC > ; # [doc = "Register `CCPD` writer"]
pub type W = crate :: W < CCPD_SPEC > ; # [doc = "Field `CCPD_C0CCP0` reader - Counter CCP0"]
pub type CCPD_C0CCP0_R = crate :: BitReader < CCPD_C0CCP0_A > ; # [doc = "Counter CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP0_A { # [doc = "0: INPUT"]
CCPD_C0CCP0_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP0_OUTPUT = 1 , } impl From < CCPD_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP0_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP0_A { match self . bits { false => CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT , true => CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_input (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_output (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT } } # [doc = "Field `CCPD_C0CCP0` writer - Counter CCP0"]
pub type CCPD_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP0_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT) } } # [doc = "Field `CCPD_C0CCP1` reader - Counter CCP1"]
pub type CCPD_C0CCP1_R = crate :: BitReader < CCPD_C0CCP1_A > ; # [doc = "Counter CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP1_A { # [doc = "0: INPUT"]
CCPD_C0CCP1_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP1_OUTPUT = 1 , } impl From < CCPD_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP1_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP1_A { match self . bits { false => CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT , true => CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_input (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_output (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT } } # [doc = "Field `CCPD_C0CCP1` writer - Counter CCP1"]
pub type CCPD_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP1_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT) } } impl R { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
pub fn ccpd_c0ccp0 (& self) -> CCPD_C0CCP0_R { CCPD_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
pub fn ccpd_c0ccp1 (& self) -> CCPD_C0CCP1_R { CCPD_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp0 (& mut self) -> CCPD_C0CCP0_W < CCPD_SPEC , 0 > { CCPD_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp1 (& mut self) -> CCPD_C0CCP1_W < CCPD_SPEC , 1 > { CCPD_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCPD_SPEC ; impl crate :: RegisterSpec for CCPD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccpd::R`](R) reader structure"]
impl crate :: Readable for CCPD_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccpd::W`](W) writer structure"]
impl crate :: Writable for CCPD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCPD to value 0"]
impl crate :: Resettable for CCPD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ODIS (rw) register accessor: Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@odis`]
module"]
pub type ODIS = crate :: Reg < odis :: ODIS_SPEC > ; # [doc = "Output Disable"]
pub mod odis { # [doc = "Register `ODIS` reader"]
pub type R = crate :: R < ODIS_SPEC > ; # [doc = "Register `ODIS` writer"]
pub type W = crate :: W < ODIS_SPEC > ; # [doc = "Field `ODIS_C0CCP0` reader - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_R = crate :: BitReader < ODIS_C0CCP0_A > ; # [doc = "Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP0_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP0_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP0_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP0_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP0_A { match self . bits { false => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL , true => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP0` writer - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP0_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW) } } # [doc = "Field `ODIS_C0CCP1` reader - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_R = crate :: BitReader < ODIS_C0CCP1_A > ; # [doc = "Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP1_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP1_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP1_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP1_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP1_A { match self . bits { false => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL , true => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP1` writer - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP1_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW) } } impl R { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp0 (& self) -> ODIS_C0CCP0_R { ODIS_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp1 (& self) -> ODIS_C0CCP1_R { ODIS_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp0 (& mut self) -> ODIS_C0CCP0_W < ODIS_SPEC , 0 > { ODIS_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp1 (& mut self) -> ODIS_C0CCP1_W < ODIS_SPEC , 1 > { ODIS_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ODIS_SPEC ; impl crate :: RegisterSpec for ODIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`odis::R`](R) reader structure"]
impl crate :: Readable for ODIS_SPEC { } # [doc = "`write(|w| ..)` method takes [`odis::W`](W) writer structure"]
impl crate :: Writable for ODIS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ODIS to value 0"]
impl crate :: Resettable for ODIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCLKCTL (rw) register accessor: Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cclkctl`]
module"]
pub type CCLKCTL = crate :: Reg < cclkctl :: CCLKCTL_SPEC > ; # [doc = "Counter Clock Control Register"]
pub mod cclkctl { # [doc = "Register `CCLKCTL` reader"]
pub type R = crate :: R < CCLKCTL_SPEC > ; # [doc = "Register `CCLKCTL` writer"]
pub type W = crate :: W < CCLKCTL_SPEC > ; # [doc = "Field `CCLKCTL_CLKEN` reader - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_R = crate :: BitReader < CCLKCTL_CLKEN_A > ; # [doc = "Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCLKCTL_CLKEN_A { # [doc = "0: DISABLED"]
CCLKCTL_CLKEN_DISABLED = 0 , # [doc = "1: ENABLED"]
CCLKCTL_CLKEN_ENABLED = 1 , } impl From < CCLKCTL_CLKEN_A > for bool { # [inline (always)]
fn from (variant : CCLKCTL_CLKEN_A) -> Self { variant as u8 != 0 } } impl CCLKCTL_CLKEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCLKCTL_CLKEN_A { match self . bits { false => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED , true => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_disabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_enabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED } } # [doc = "Field `CCLKCTL_CLKEN` writer - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCLKCTL_CLKEN_A > ; impl < 'a , REG , const O : u8 > CCLKCTL_CLKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cclkctl_clken_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn cclkctl_clken_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED) } } impl R { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
pub fn cclkctl_clken (& self) -> CCLKCTL_CLKEN_R { CCLKCTL_CLKEN_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
# [must_use]
pub fn cclkctl_clken (& mut self) -> CCLKCTL_CLKEN_W < CCLKCTL_SPEC , 0 > { CCLKCTL_CLKEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCLKCTL_SPEC ; impl crate :: RegisterSpec for CCLKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cclkctl::R`](R) reader structure"]
impl crate :: Readable for CCLKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cclkctl::W`](W) writer structure"]
impl crate :: Writable for CCLKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCLKCTL to value 0"]
impl crate :: Resettable for CCLKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPS (rw) register accessor: Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cps`]
module"]
pub type CPS = crate :: Reg < cps :: CPS_SPEC > ; # [doc = "Clock Prescale Register"]
pub mod cps { # [doc = "Register `CPS` reader"]
pub type R = crate :: R < CPS_SPEC > ; # [doc = "Register `CPS` writer"]
pub type W = crate :: W < CPS_SPEC > ; # [doc = "Field `CPS_PCNT` reader - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_R = crate :: FieldReader ; # [doc = "Field `CPS_PCNT` writer - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
pub fn cps_pcnt (& self) -> CPS_PCNT_R { CPS_PCNT_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
# [must_use]
pub fn cps_pcnt (& mut self) -> CPS_PCNT_W < CPS_SPEC , 0 > { CPS_PCNT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPS_SPEC ; impl crate :: RegisterSpec for CPS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cps::R`](R) reader structure"]
impl crate :: Readable for CPS_SPEC { } # [doc = "`write(|w| ..)` method takes [`cps::W`](W) writer structure"]
impl crate :: Writable for CPS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CPS to value 0"]
impl crate :: Resettable for CPS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPSV (r) register accessor: Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpsv`]
module"]
pub type CPSV = crate :: Reg < cpsv :: CPSV_SPEC > ; # [doc = "Clock prescale count status register"]
pub mod cpsv { # [doc = "Register `CPSV` reader"]
pub type R = crate :: R < CPSV_SPEC > ; # [doc = "Field `CPSV_CPSVAL` reader - Current Prescale Count Value"]
pub type CPSV_CPSVAL_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Current Prescale Count Value"]
# [inline (always)]
pub fn cpsv_cpsval (& self) -> CPSV_CPSVAL_R { CPSV_CPSVAL_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPSV_SPEC ; impl crate :: RegisterSpec for CPSV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cpsv::R`](R) reader structure"]
impl crate :: Readable for CPSV_SPEC { } # [doc = "`reset()` method sets CPSV to value 0"]
impl crate :: Resettable for CPSV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIGCTL (rw) register accessor: Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrigctl`]
module"]
pub type CTTRIGCTL = crate :: Reg < cttrigctl :: CTTRIGCTL_SPEC > ; # [doc = "Timer Cross Trigger Control Register"]
pub mod cttrigctl { # [doc = "Register `CTTRIGCTL` reader"]
pub type R = crate :: R < CTTRIGCTL_SPEC > ; # [doc = "Register `CTTRIGCTL` writer"]
pub type W = crate :: W < CTTRIGCTL_SPEC > ; # [doc = "Field `CTTRIGCTL_CTEN` reader - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_R = crate :: BitReader < CTTRIGCTL_CTEN_A > ; # [doc = "Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_CTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_CTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_CTEN_ENABLE = 1 , } impl From < CTTRIGCTL_CTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_CTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_CTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_CTEN_A { match self . bits { false => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED , true => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_cten_disabled (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_cten_enable (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_CTEN` writer - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_CTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_CTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_cten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_cten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTEN` reader - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_R = crate :: BitReader < CTTRIGCTL_EVTCTEN_A > ; # [doc = "Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_EVTCTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_EVTCTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_EVTCTEN_ENABLE = 1 , } impl From < CTTRIGCTL_EVTCTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_EVTCTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_EVTCTEN_A { match self . bits { false => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED , true => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_disabled (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_enable (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_EVTCTEN` writer - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_EVTCTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_evtcten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_evtcten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` reader - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_R = crate :: FieldReader < CTTRIGCTL_EVTCTTRIGSEL_A > ; # [doc = "Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTTRIGCTL_EVTCTTRIGSEL_A { # [doc = "0: FSUB0"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB0 = 0 , # [doc = "1: FSUB1"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB1 = 1 , # [doc = "2: Z"]
CTTRIGCTL_EVTCTTRIGSEL_Z = 2 , # [doc = "3: L"]
CTTRIGCTL_EVTCTTRIGSEL_L = 3 , # [doc = "4: CCD0"]
CTTRIGCTL_EVTCTTRIGSEL_CCD0 = 4 , # [doc = "5: CCD1"]
CTTRIGCTL_EVTCTTRIGSEL_CCD1 = 5 , # [doc = "6: CCD2"]
CTTRIGCTL_EVTCTTRIGSEL_CCD2 = 6 , # [doc = "7: CCD3"]
CTTRIGCTL_EVTCTTRIGSEL_CCD3 = 7 , # [doc = "8: CCU0"]
CTTRIGCTL_EVTCTTRIGSEL_CCU0 = 8 , # [doc = "9: CCU1"]
CTTRIGCTL_EVTCTTRIGSEL_CCU1 = 9 , # [doc = "10: CCU2"]
CTTRIGCTL_EVTCTTRIGSEL_CCU2 = 10 , # [doc = "11: CCU3"]
CTTRIGCTL_EVTCTTRIGSEL_CCU3 = 11 , } impl From < CTTRIGCTL_EVTCTTRIGSEL_A > for u8 { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTTRIGSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTTRIGCTL_EVTCTTRIGSEL_A { type Ux = u8 ; } impl CTTRIGCTL_EVTCTTRIGSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTTRIGCTL_EVTCTTRIGSEL_A > { match self . bits { 0 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) , 1 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) , 2 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) , 3 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) , 4 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) , 5 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) , 6 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) , 7 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) , 8 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) , 9 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) , 10 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) , 11 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) , _ => None , } } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1 } # [doc = "Z"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_z (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z } # [doc = "L"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_l (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3 } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` writer - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CTTRIGCTL_EVTCTTRIGSEL_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FSUB0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) } # [doc = "Z"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_z (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) } # [doc = "L"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_l (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) } # [doc = "CCD0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) } # [doc = "CCD1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) } # [doc = "CCD2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) } # [doc = "CCD3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) } # [doc = "CCU0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) } # [doc = "CCU1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) } # [doc = "CCU2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) } # [doc = "CCU3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) } } impl R { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
pub fn cttrigctl_cten (& self) -> CTTRIGCTL_CTEN_R { CTTRIGCTL_CTEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcten (& self) -> CTTRIGCTL_EVTCTEN_R { CTTRIGCTL_EVTCTEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel (& self) -> CTTRIGCTL_EVTCTTRIGSEL_R { CTTRIGCTL_EVTCTTRIGSEL_R :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
# [must_use]
pub fn cttrigctl_cten (& mut self) -> CTTRIGCTL_CTEN_W < CTTRIGCTL_SPEC , 0 > { CTTRIGCTL_CTEN_W :: new (self) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcten (& mut self) -> CTTRIGCTL_EVTCTEN_W < CTTRIGCTL_SPEC , 1 > { CTTRIGCTL_EVTCTEN_W :: new (self) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcttrigsel (& mut self) -> CTTRIGCTL_EVTCTTRIGSEL_W < CTTRIGCTL_SPEC , 16 > { CTTRIGCTL_EVTCTTRIGSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIGCTL_SPEC ; impl crate :: RegisterSpec for CTTRIGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cttrigctl::R`](R) reader structure"]
impl crate :: Readable for CTTRIGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cttrigctl::W`](W) writer structure"]
impl crate :: Writable for CTTRIGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIGCTL to value 0"]
impl crate :: Resettable for CTTRIGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIG (w) register accessor: Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrig`]
module"]
pub type CTTRIG = crate :: Reg < cttrig :: CTTRIG_SPEC > ; # [doc = "Timer Cross Trigger Register"]
pub mod cttrig { # [doc = "Register `CTTRIG` writer"]
pub type W = crate :: W < CTTRIG_SPEC > ; # [doc = "Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIG_TRIG_AW { # [doc = "0: DISABLED"]
CTTRIG_TRIG_DISABLED = 0 , # [doc = "1: GENERATE"]
CTTRIG_TRIG_GENERATE = 1 , } impl From < CTTRIG_TRIG_AW > for bool { # [inline (always)]
fn from (variant : CTTRIG_TRIG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `CTTRIG_TRIG` writer - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
pub type CTTRIG_TRIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIG_TRIG_AW > ; impl < 'a , REG , const O : u8 > CTTRIG_TRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrig_trig_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_DISABLED) } # [doc = "GENERATE"]
# [inline (always)]
pub fn cttrig_trig_generate (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_GENERATE) } } impl W { # [doc = "Bit 0 - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
# [inline (always)]
# [must_use]
pub fn cttrig_trig (& mut self) -> CTTRIG_TRIG_W < CTTRIG_SPEC , 0 > { CTTRIG_TRIG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIG_SPEC ; impl crate :: RegisterSpec for CTTRIG_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`cttrig::W`](W) writer structure"]
impl crate :: Writable for CTTRIG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIG to value 0"]
impl crate :: Resettable for CTTRIG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "GCTL (rw) register accessor: Shadow to active load mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@gctl`]
module"]
pub type GCTL = crate :: Reg < gctl :: GCTL_SPEC > ; # [doc = "Shadow to active load mask"]
pub mod gctl { # [doc = "Register `GCTL` reader"]
pub type R = crate :: R < GCTL_SPEC > ; # [doc = "Register `GCTL` writer"]
pub type W = crate :: W < GCTL_SPEC > ; # [doc = "Field `GCTL_SHDWLDEN` reader - Enables shadow to active load of bufferred registers and register fields."]
pub type GCTL_SHDWLDEN_R = crate :: BitReader < GCTL_SHDWLDEN_A > ; # [doc = "Enables shadow to active load of bufferred registers and register fields.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum GCTL_SHDWLDEN_A { # [doc = "0: DISABLE"]
GCTL_SHDWLDEN_DISABLE = 0 , # [doc = "1: ENABLE"]
GCTL_SHDWLDEN_ENABLE = 1 , } impl From < GCTL_SHDWLDEN_A > for bool { # [inline (always)]
fn from (variant : GCTL_SHDWLDEN_A) -> Self { variant as u8 != 0 } } impl GCTL_SHDWLDEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> GCTL_SHDWLDEN_A { match self . bits { false => GCTL_SHDWLDEN_A :: GCTL_SHDWLDEN_DISABLE , true => GCTL_SHDWLDEN_A :: GCTL_SHDWLDEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_gctl_shdwlden_disable (& self) -> bool { * self == GCTL_SHDWLDEN_A :: GCTL_SHDWLDEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_gctl_shdwlden_enable (& self) -> bool { * self == GCTL_SHDWLDEN_A :: GCTL_SHDWLDEN_ENABLE } } # [doc = "Field `GCTL_SHDWLDEN` writer - Enables shadow to active load of bufferred registers and register fields."]
pub type GCTL_SHDWLDEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , GCTL_SHDWLDEN_A > ; impl < 'a , REG , const O : u8 > GCTL_SHDWLDEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn gctl_shdwlden_disable (self) -> & 'a mut crate :: W < REG > { self . variant (GCTL_SHDWLDEN_A :: GCTL_SHDWLDEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn gctl_shdwlden_enable (self) -> & 'a mut crate :: W < REG > { self . variant (GCTL_SHDWLDEN_A :: GCTL_SHDWLDEN_ENABLE) } } impl R { # [doc = "Bit 0 - Enables shadow to active load of bufferred registers and register fields."]
# [inline (always)]
pub fn gctl_shdwlden (& self) -> GCTL_SHDWLDEN_R { GCTL_SHDWLDEN_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enables shadow to active load of bufferred registers and register fields."]
# [inline (always)]
# [must_use]
pub fn gctl_shdwlden (& mut self) -> GCTL_SHDWLDEN_W < GCTL_SPEC , 0 > { GCTL_SHDWLDEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Shadow to active load mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`gctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`gctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct GCTL_SPEC ; impl crate :: RegisterSpec for GCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`gctl::R`](R) reader structure"]
impl crate :: Readable for GCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`gctl::W`](W) writer structure"]
impl crate :: Writable for GCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets GCTL to value 0"]
impl crate :: Resettable for GCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTR (rw) register accessor: Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`]
module"]
pub type CTR = crate :: Reg < ctr :: CTR_SPEC > ; # [doc = "Counter Register"]
pub mod ctr { # [doc = "Register `CTR` reader"]
pub type R = crate :: R < CTR_SPEC > ; # [doc = "Register `CTR` writer"]
pub type W = crate :: W < CTR_SPEC > ; # [doc = "Field `CTR_CCTR` reader - Current Counter value"]
pub type CTR_CCTR_R = crate :: FieldReader < u16 > ; # [doc = "Field `CTR_CCTR` writer - Current Counter value"]
pub type CTR_CCTR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
pub fn ctr_cctr (& self) -> CTR_CCTR_R { CTR_CCTR_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
# [must_use]
pub fn ctr_cctr (& mut self) -> CTR_CCTR_W < CTR_SPEC , 0 > { CTR_CCTR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTR_SPEC ; impl crate :: RegisterSpec for CTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctr::R`](R) reader structure"]
impl crate :: Readable for CTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
impl crate :: Writable for CTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTR to value 0"]
impl crate :: Resettable for CTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTRCTL (rw) register accessor: Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrctl`]
module"]
pub type CTRCTL = crate :: Reg < ctrctl :: CTRCTL_SPEC > ; # [doc = "Counter Control Register"]
pub mod ctrctl { # [doc = "Register `CTRCTL` reader"]
pub type R = crate :: R < CTRCTL_SPEC > ; # [doc = "Register `CTRCTL` writer"]
pub type W = crate :: W < CTRCTL_SPEC > ; # [doc = "Field `CTRCTL_EN` reader - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_R = crate :: BitReader < CTRCTL_EN_A > ; # [doc = "Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_EN_A { # [doc = "0: DISABLED"]
CTRCTL_EN_DISABLED = 0 , # [doc = "1: ENABLED"]
CTRCTL_EN_ENABLED = 1 , } impl From < CTRCTL_EN_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_EN_A) -> Self { variant as u8 != 0 } } impl CTRCTL_EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_EN_A { match self . bits { false => CTRCTL_EN_A :: CTRCTL_EN_DISABLED , true => CTRCTL_EN_A :: CTRCTL_EN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ctrctl_en_disabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ctrctl_en_enabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_ENABLED } } # [doc = "Field `CTRCTL_EN` writer - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_EN_A > ; impl < 'a , REG , const O : u8 > CTRCTL_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ctrctl_en_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ctrctl_en_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_ENABLED) } } # [doc = "Field `CTRCTL_REPEAT` reader - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_R = crate :: FieldReader < CTRCTL_REPEAT_A > ; # [doc = "Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_REPEAT_A { # [doc = "0: REPEAT_0"]
CTRCTL_REPEAT_REPEAT_0 = 0 , # [doc = "1: REPEAT_1"]
CTRCTL_REPEAT_REPEAT_1 = 1 , # [doc = "2: REPEAT_2"]
CTRCTL_REPEAT_REPEAT_2 = 2 , # [doc = "3: REPEAT_3"]
CTRCTL_REPEAT_REPEAT_3 = 3 , # [doc = "4: REPEAT_4"]
CTRCTL_REPEAT_REPEAT_4 = 4 , } impl From < CTRCTL_REPEAT_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_REPEAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_REPEAT_A { type Ux = u8 ; } impl CTRCTL_REPEAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_REPEAT_A > { match self . bits { 0 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) , 1 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) , 2 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) , 3 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) , 4 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) , _ => None , } } # [doc = "REPEAT_0"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_0 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0 } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_1 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1 } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_2 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2 } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_3 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3 } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_4 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4 } } # [doc = "Field `CTRCTL_REPEAT` writer - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_REPEAT_A > ; impl < 'a , REG , const O : u8 > CTRCTL_REPEAT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "REPEAT_0"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) } } # [doc = "Field `CTRCTL_CM` reader - Count Mode"]
pub type CTRCTL_CM_R = crate :: FieldReader < CTRCTL_CM_A > ; # [doc = "Count Mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CM_A { # [doc = "0: DOWN"]
CTRCTL_CM_DOWN = 0 , # [doc = "1: UP_DOWN"]
CTRCTL_CM_UP_DOWN = 1 , # [doc = "2: UP"]
CTRCTL_CM_UP = 2 , } impl From < CTRCTL_CM_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CM_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CM_A { type Ux = u8 ; } impl CTRCTL_CM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CM_A > { match self . bits { 0 => Some (CTRCTL_CM_A :: CTRCTL_CM_DOWN) , 1 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) , 2 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP) , _ => None , } } # [doc = "DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_DOWN } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_up_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN } # [doc = "UP"]
# [inline (always)]
pub fn is_ctrctl_cm_up (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP } } # [doc = "Field `CTRCTL_CM` writer - Count Mode"]
pub type CTRCTL_CM_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CM_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DOWN"]
# [inline (always)]
pub fn ctrctl_cm_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_DOWN) } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn ctrctl_cm_up_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) } # [doc = "UP"]
# [inline (always)]
pub fn ctrctl_cm_up (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP) } } # [doc = "Field `CTRCTL_CLC` reader - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_R = crate :: FieldReader < CTRCTL_CLC_A > ; # [doc = "Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CLC_A { # [doc = "0: CCCTL0_LCOND"]
CTRCTL_CLC_CCCTL0_LCOND = 0 , # [doc = "1: CCCTL1_LCOND"]
CTRCTL_CLC_CCCTL1_LCOND = 1 , # [doc = "2: CCCTL2_LCOND"]
CTRCTL_CLC_CCCTL2_LCOND = 2 , # [doc = "3: CCCTL3_LCOND"]
CTRCTL_CLC_CCCTL3_LCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CLC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CLC_QEI_3INP = 5 , } impl From < CTRCTL_CLC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CLC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CLC_A { type Ux = u8 ; } impl CTRCTL_CLC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CLC_A > { match self . bits { 0 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) , 1 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) , 2 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) , 3 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) , 4 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) , 5 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl0_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl1_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl2_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl3_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_2inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_3inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP } } # [doc = "Field `CTRCTL_CLC` writer - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CLC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CLC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl0_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl1_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl2_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl3_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) } } # [doc = "Field `CTRCTL_CAC` reader - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_R = crate :: FieldReader < CTRCTL_CAC_A > ; # [doc = "Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CAC_A { # [doc = "0: CCCTL0_ACOND"]
CTRCTL_CAC_CCCTL0_ACOND = 0 , # [doc = "1: CCCTL1_ACOND"]
CTRCTL_CAC_CCCTL1_ACOND = 1 , # [doc = "2: CCCTL2_ACOND"]
CTRCTL_CAC_CCCTL2_ACOND = 2 , # [doc = "3: CCCTL3_ACOND"]
CTRCTL_CAC_CCCTL3_ACOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CAC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CAC_QEI_3INP = 5 , } impl From < CTRCTL_CAC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CAC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CAC_A { type Ux = u8 ; } impl CTRCTL_CAC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CAC_A > { match self . bits { 0 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) , 1 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) , 2 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) , 3 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) , 4 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) , 5 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl0_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl1_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl2_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl3_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_2inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_3inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP } } # [doc = "Field `CTRCTL_CAC` writer - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CAC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CAC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl0_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl1_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl2_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl3_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) } } # [doc = "Field `CTRCTL_CZC` reader - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_R = crate :: FieldReader < CTRCTL_CZC_A > ; # [doc = "Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CZC_A { # [doc = "0: CCCTL0_ZCOND"]
CTRCTL_CZC_CCCTL0_ZCOND = 0 , # [doc = "1: CCCTL1_ZCOND"]
CTRCTL_CZC_CCCTL1_ZCOND = 1 , # [doc = "2: CCCTL2_ZCOND"]
CTRCTL_CZC_CCCTL2_ZCOND = 2 , # [doc = "3: CCCTL3_ZCOND"]
CTRCTL_CZC_CCCTL3_ZCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CZC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CZC_QEI_3INP = 5 , } impl From < CTRCTL_CZC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CZC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CZC_A { type Ux = u8 ; } impl CTRCTL_CZC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CZC_A > { match self . bits { 0 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) , 1 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) , 2 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) , 3 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) , 4 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) , 5 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl0_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl1_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl2_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl3_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_2inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_3inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP } } # [doc = "Field `CTRCTL_CZC` writer - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CZC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CZC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl0_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl1_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl2_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl3_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) } } # [doc = "Field `CTRCTL_DRB` reader - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_R = crate :: BitReader < CTRCTL_DRB_A > ; # [doc = "Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_DRB_A { # [doc = "0: RESUME"]
CTRCTL_DRB_RESUME = 0 , # [doc = "1: CVAE_ACTION"]
CTRCTL_DRB_CVAE_ACTION = 1 , } impl From < CTRCTL_DRB_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_DRB_A) -> Self { variant as u8 != 0 } } impl CTRCTL_DRB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_DRB_A { match self . bits { false => CTRCTL_DRB_A :: CTRCTL_DRB_RESUME , true => CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION , } } # [doc = "RESUME"]
# [inline (always)]
pub fn is_ctrctl_drb_resume (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_RESUME } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn is_ctrctl_drb_cvae_action (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION } } # [doc = "Field `CTRCTL_DRB` writer - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_DRB_A > ; impl < 'a , REG , const O : u8 > CTRCTL_DRB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RESUME"]
# [inline (always)]
pub fn ctrctl_drb_resume (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_RESUME) } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn ctrctl_drb_cvae_action (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION) } } # [doc = "Field `CTRCTL_CVAE` reader - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_R = crate :: FieldReader < CTRCTL_CVAE_A > ; # [doc = "Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CVAE_A { # [doc = "0: LDVAL"]
CTRCTL_CVAE_LDVAL = 0 , # [doc = "1: NOCHANGE"]
CTRCTL_CVAE_NOCHANGE = 1 , # [doc = "2: ZEROVAL"]
CTRCTL_CVAE_ZEROVAL = 2 , } impl From < CTRCTL_CVAE_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CVAE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CVAE_A { type Ux = u8 ; } impl CTRCTL_CVAE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CVAE_A > { match self . bits { 0 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) , 1 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) , 2 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) , _ => None , } } # [doc = "LDVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_ldval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn is_ctrctl_cvae_nochange (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_zeroval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL } } # [doc = "Field `CTRCTL_CVAE` writer - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CVAE_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CVAE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LDVAL"]
# [inline (always)]
pub fn ctrctl_cvae_ldval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn ctrctl_cvae_nochange (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn ctrctl_cvae_zeroval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) } } impl R { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
pub fn ctrctl_en (& self) -> CTRCTL_EN_R { CTRCTL_EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
pub fn ctrctl_repeat (& self) -> CTRCTL_REPEAT_R { CTRCTL_REPEAT_R :: new (((self . bits >> 1) & 7) as u8) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
pub fn ctrctl_cm (& self) -> CTRCTL_CM_R { CTRCTL_CM_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_clc (& self) -> CTRCTL_CLC_R { CTRCTL_CLC_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_cac (& self) -> CTRCTL_CAC_R { CTRCTL_CAC_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_czc (& self) -> CTRCTL_CZC_R { CTRCTL_CZC_R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
pub fn ctrctl_drb (& self) -> CTRCTL_DRB_R { CTRCTL_DRB_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
pub fn ctrctl_cvae (& self) -> CTRCTL_CVAE_R { CTRCTL_CVAE_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
# [must_use]
pub fn ctrctl_en (& mut self) -> CTRCTL_EN_W < CTRCTL_SPEC , 0 > { CTRCTL_EN_W :: new (self) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
# [must_use]
pub fn ctrctl_repeat (& mut self) -> CTRCTL_REPEAT_W < CTRCTL_SPEC , 1 > { CTRCTL_REPEAT_W :: new (self) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
# [must_use]
pub fn ctrctl_cm (& mut self) -> CTRCTL_CM_W < CTRCTL_SPEC , 4 > { CTRCTL_CM_W :: new (self) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_clc (& mut self) -> CTRCTL_CLC_W < CTRCTL_SPEC , 7 > { CTRCTL_CLC_W :: new (self) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cac (& mut self) -> CTRCTL_CAC_W < CTRCTL_SPEC , 10 > { CTRCTL_CAC_W :: new (self) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_czc (& mut self) -> CTRCTL_CZC_W < CTRCTL_SPEC , 13 > { CTRCTL_CZC_W :: new (self) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
# [must_use]
pub fn ctrctl_drb (& mut self) -> CTRCTL_DRB_W < CTRCTL_SPEC , 17 > { CTRCTL_DRB_W :: new (self) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cvae (& mut self) -> CTRCTL_CVAE_W < CTRCTL_SPEC , 28 > { CTRCTL_CVAE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRCTL_SPEC ; impl crate :: RegisterSpec for CTRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctrctl::R`](R) reader structure"]
impl crate :: Readable for CTRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctrctl::W`](W) writer structure"]
impl crate :: Writable for CTRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTRCTL to value 0xff80"]
impl crate :: Resettable for CTRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0xff80 ; } } # [doc = "LOAD (rw) register accessor: Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load`]
module"]
pub type LOAD = crate :: Reg < load :: LOAD_SPEC > ; # [doc = "Load Register"]
pub mod load { # [doc = "Register `LOAD` reader"]
pub type R = crate :: R < LOAD_SPEC > ; # [doc = "Register `LOAD` writer"]
pub type W = crate :: W < LOAD_SPEC > ; # [doc = "Field `LOAD_LD` reader - Load Value"]
pub type LOAD_LD_R = crate :: FieldReader < u16 > ; # [doc = "Field `LOAD_LD` writer - Load Value"]
pub type LOAD_LD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
pub fn load_ld (& self) -> LOAD_LD_R { LOAD_LD_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
# [must_use]
pub fn load_ld (& mut self) -> LOAD_LD_W < LOAD_SPEC , 0 > { LOAD_LD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LOAD_SPEC ; impl crate :: RegisterSpec for LOAD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`load::R`](R) reader structure"]
impl crate :: Readable for LOAD_SPEC { } # [doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"]
impl crate :: Writable for LOAD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LOAD to value 0"]
impl crate :: Resettable for LOAD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CC_01 (rw) register accessor: Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cc_01`]
module"]
pub type CC_01 = crate :: Reg < cc_01 :: CC_01_SPEC > ; # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1"]
pub mod cc_01 { # [doc = "Register `CC_01[%s]` reader"]
pub type R = crate :: R < CC_01_SPEC > ; # [doc = "Register `CC_01[%s]` writer"]
pub type W = crate :: W < CC_01_SPEC > ; # [doc = "Field `CC_01_CCVAL` reader - Capture or compare value"]
pub type CC_01_CCVAL_R = crate :: FieldReader < u16 > ; # [doc = "Field `CC_01_CCVAL` writer - Capture or compare value"]
pub type CC_01_CCVAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
pub fn cc_01_ccval (& self) -> CC_01_CCVAL_R { CC_01_CCVAL_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
# [must_use]
pub fn cc_01_ccval (& mut self) -> CC_01_CCVAL_W < CC_01_SPEC , 0 > { CC_01_CCVAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CC_01_SPEC ; impl crate :: RegisterSpec for CC_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cc_01::R`](R) reader structure"]
impl crate :: Readable for CC_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`cc_01::W`](W) writer structure"]
impl crate :: Writable for CC_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CC_01[%s]
to value 0"]
impl crate :: Resettable for CC_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCCTL_01 (rw) register accessor: Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccctl_01`]
module"]
pub type CCCTL_01 = crate :: Reg < ccctl_01 :: CCCTL_01_SPEC > ; # [doc = "Capture or Compare Control Registers"]
pub mod ccctl_01 { # [doc = "Register `CCCTL_01[%s]` reader"]
pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"]
pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"]
CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"]
CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"]
CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"]
# [inline (always)]
pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"]
# [inline (always)]
pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"]
CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"]
CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)]
fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"]
# [inline (always)]
pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"]
# [inline (always)]
pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"]
# [inline (always)]
pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CCUPD` reader - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."]
pub type CCCTL_01_CCUPD_R = crate :: FieldReader < CCCTL_01_CCUPD_A > ; # [doc = "Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCUPD_A { # [doc = "0: IMMEDIATELY"]
CCCTL_01_CCUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"]
CCCTL_01_CCUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"]
CCCTL_01_CCUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"]
CCCTL_01_CCUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"]
CCCTL_01_CCUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"]
CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"]
CCCTL_01_CCUPD_TRIG = 6 , } impl From < CCCTL_01_CCUPD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCUPD_A { type Ux = u8 ; } impl CCCTL_01_CCUPD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn is_ccctl_01_ccupd_immediately (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"]
# [inline (always)]
pub fn is_ccctl_01_ccupd_trig (& self) -> bool { * self == CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG } } # [doc = "Field `CCCTL_01_CCUPD` writer - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."]
pub type CCCTL_01_CCUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn ccctl_01_ccupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn ccctl_01_ccupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn ccctl_01_ccupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn ccctl_01_ccupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"]
# [inline (always)]
pub fn ccctl_01_ccupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCUPD_A :: CCCTL_01_CCUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"]
CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"]
CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"]
CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"]
CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"]
CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"]
CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"]
CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"]
CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"]
CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"]
CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"]
CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"]
# [inline (always)]
pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"]
CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"]
CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"]
CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"]
CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"]
CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"]
CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."]
# [inline (always)]
pub fn ccctl_01_ccupd (& self) -> CCCTL_01_CCUPD_R { CCCTL_01_CCUPD_R :: new (((self . bits >> 18) & 7) as u8) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 18:20 - Capture and Compare Update Method This field controls how updates to the pipelined capture and compare register are performed (when operating in compare mode, COC=0)."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccupd (& mut self) -> CCCTL_01_CCUPD_W < CCCTL_01_SPEC , 18 > { CCCTL_01_CCUPD_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"]
impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"]
impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s]
to value 0"]
impl crate :: Resettable for CCCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "OCTL_01 (rw) register accessor: CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@octl_01`]
module"]
pub type OCTL_01 = crate :: Reg < octl_01 :: OCTL_01_SPEC > ; # [doc = "CCP Output Control Registers"]
pub mod octl_01 { # [doc = "Register `OCTL_01[%s]` reader"]
pub type R = crate :: R < OCTL_01_SPEC > ; # [doc = "Register `OCTL_01[%s]` writer"]
pub type W = crate :: W < OCTL_01_SPEC > ; # [doc = "Field `OCTL_01_CCPO` reader - CCP Output Source"]
pub type OCTL_01_CCPO_R = crate :: FieldReader < OCTL_01_CCPO_A > ; # [doc = "CCP Output Source\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum OCTL_01_CCPO_A { # [doc = "0: FUNCVAL"]
OCTL_01_CCPO_FUNCVAL = 0 , # [doc = "1: LOAD"]
OCTL_01_CCPO_LOAD = 1 , # [doc = "2: CMPVAL"]
OCTL_01_CCPO_CMPVAL = 2 , # [doc = "4: ZERO"]
OCTL_01_CCPO_ZERO = 4 , # [doc = "5: CAPCOND"]
OCTL_01_CCPO_CAPCOND = 5 , # [doc = "6: FAULTCOND"]
OCTL_01_CCPO_FAULTCOND = 6 , # [doc = "8: CC0_MIRROR_ALL"]
OCTL_01_CCPO_CC0_MIRROR_ALL = 8 , # [doc = "9: CC1_MIRROR_ALL"]
OCTL_01_CCPO_CC1_MIRROR_ALL = 9 , # [doc = "12: DEADBAND"]
OCTL_01_CCPO_DEADBAND = 12 , # [doc = "13: CNTDIR"]
OCTL_01_CCPO_CNTDIR = 13 , } impl From < OCTL_01_CCPO_A > for u8 { # [inline (always)]
fn from (variant : OCTL_01_CCPO_A) -> Self { variant as _ } } impl crate :: FieldSpec for OCTL_01_CCPO_A { type Ux = u8 ; } impl OCTL_01_CCPO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < OCTL_01_CCPO_A > { match self . bits { 0 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) , 1 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) , 2 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) , 4 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) , 5 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) , 6 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) , 8 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) , 9 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) , 12 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) , 13 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) , _ => None , } } # [doc = "FUNCVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_funcval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL } # [doc = "LOAD"]
# [inline (always)]
pub fn is_octl_01_ccpo_load (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD } # [doc = "CMPVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cmpval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL } # [doc = "ZERO"]
# [inline (always)]
pub fn is_octl_01_ccpo_zero (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO } # [doc = "CAPCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_capcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_faultcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc0_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc1_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL } # [doc = "DEADBAND"]
# [inline (always)]
pub fn is_octl_01_ccpo_deadband (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND } # [doc = "CNTDIR"]
# [inline (always)]
pub fn is_octl_01_ccpo_cntdir (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR } } # [doc = "Field `OCTL_01_CCPO` writer - CCP Output Source"]
pub type OCTL_01_CCPO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , OCTL_01_CCPO_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FUNCVAL"]
# [inline (always)]
pub fn octl_01_ccpo_funcval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) } # [doc = "LOAD"]
# [inline (always)]
pub fn octl_01_ccpo_load (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) } # [doc = "CMPVAL"]
# [inline (always)]
pub fn octl_01_ccpo_cmpval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) } # [doc = "ZERO"]
# [inline (always)]
pub fn octl_01_ccpo_zero (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) } # [doc = "CAPCOND"]
# [inline (always)]
pub fn octl_01_ccpo_capcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn octl_01_ccpo_faultcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc0_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc1_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) } # [doc = "DEADBAND"]
# [inline (always)]
pub fn octl_01_ccpo_deadband (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) } # [doc = "CNTDIR"]
# [inline (always)]
pub fn octl_01_ccpo_cntdir (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) } } # [doc = "Field `OCTL_01_CCPOINV` reader - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_R = crate :: BitReader < OCTL_01_CCPOINV_A > ; # [doc = "CCP Output Invert The output as selected by CCPO is conditionally inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPOINV_A { # [doc = "0: NOINV"]
OCTL_01_CCPOINV_NOINV = 0 , # [doc = "1: INV"]
OCTL_01_CCPOINV_INV = 1 , } impl From < OCTL_01_CCPOINV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPOINV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPOINV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPOINV_A { match self . bits { false => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV , true => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV , } } # [doc = "NOINV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_noinv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV } # [doc = "INV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_inv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV } } # [doc = "Field `OCTL_01_CCPOINV` writer - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPOINV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPOINV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINV"]
# [inline (always)]
pub fn octl_01_ccpoinv_noinv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV) } # [doc = "INV"]
# [inline (always)]
pub fn octl_01_ccpoinv_inv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV) } } # [doc = "Field `OCTL_01_CCPIV` reader - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_R = crate :: BitReader < OCTL_01_CCPIV_A > ; # [doc = "CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPIV_A { # [doc = "0: LOW"]
OCTL_01_CCPIV_LOW = 0 , # [doc = "1: HIGH"]
OCTL_01_CCPIV_HIGH = 1 , } impl From < OCTL_01_CCPIV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPIV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPIV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPIV_A { match self . bits { false => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW , true => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_octl_01_ccpiv_low (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_octl_01_ccpiv_high (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH } } # [doc = "Field `OCTL_01_CCPIV` writer - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPIV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"]
# [inline (always)]
pub fn octl_01_ccpiv_low (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW) } # [doc = "HIGH"]
# [inline (always)]
pub fn octl_01_ccpiv_high (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH) } } impl R { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
pub fn octl_01_ccpo (& self) -> OCTL_01_CCPO_R { OCTL_01_CCPO_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
pub fn octl_01_ccpoinv (& self) -> OCTL_01_CCPOINV_R { OCTL_01_CCPOINV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
pub fn octl_01_ccpiv (& self) -> OCTL_01_CCPIV_R { OCTL_01_CCPIV_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W < OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W < OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W < OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OCTL_01_SPEC ; impl crate :: RegisterSpec for OCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octl_01::R`](R) reader structure"]
impl crate :: Readable for OCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`octl_01::W`](W) writer structure"]
impl crate :: Writable for OCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets OCTL_01[%s]
to value 0"]
impl crate :: Resettable for OCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCACT_01 (rw) register accessor: Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccact_01`]
module"]
pub type CCACT_01 = crate :: Reg < ccact_01 :: CCACT_01_SPEC > ; # [doc = "Capture or Compare Action Registers"]
pub mod ccact_01 { # [doc = "Register `CCACT_01[%s]` reader"]
pub type R = crate :: R < CCACT_01_SPEC > ; # [doc = "Register `CCACT_01[%s]` writer"]
pub type W = crate :: W < CCACT_01_SPEC > ; # [doc = "Field `CCACT_01_ZACT` reader - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_R = crate :: FieldReader < CCACT_01_ZACT_A > ; # [doc = "CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_ZACT_A { # [doc = "0: DISABLED"]
CCACT_01_ZACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_ZACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_ZACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_ZACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_ZACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_ZACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_ZACT_A { type Ux = u8 ; } impl CCACT_01_ZACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_ZACT_A { match self . bits { 0 => CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED , 1 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH , 2 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW , 3 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_zact_disabled (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_high (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_low (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_toggle (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_ZACT` writer - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_ZACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_ZACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_zact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_zact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_zact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_zact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_LACT` reader - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_R = crate :: FieldReader < CCACT_01_LACT_A > ; # [doc = "CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_LACT_A { # [doc = "0: DISABLED"]
CCACT_01_LACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_LACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_LACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_LACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_LACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_LACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_LACT_A { type Ux = u8 ; } impl CCACT_01_LACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_LACT_A { match self . bits { 0 => CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED , 1 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH , 2 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW , 3 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_lact_disabled (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_high (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_low (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_toggle (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_LACT` writer - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_LACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_LACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_lact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_lact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_lact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_lact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CDACT` reader - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_R = crate :: FieldReader < CCACT_01_CDACT_A > ; # [doc = "CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CDACT_A { # [doc = "0: DISABLED"]
CCACT_01_CDACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CDACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CDACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CDACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CDACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CDACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CDACT_A { type Ux = u8 ; } impl CCACT_01_CDACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CDACT_A { match self . bits { 0 => CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED , 1 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH , 2 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW , 3 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cdact_disabled (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_high (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_low (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_toggle (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CDACT` writer - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CDACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CDACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cdact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CUACT` reader - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_R = crate :: FieldReader < CCACT_01_CUACT_A > ; # [doc = "CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CUACT_A { # [doc = "0: DISABLED"]
CCACT_01_CUACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CUACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CUACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CUACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CUACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CUACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CUACT_A { type Ux = u8 ; } impl CCACT_01_CUACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CUACT_A { match self . bits { 0 => CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED , 1 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH , 2 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW , 3 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cuact_disabled (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_high (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_low (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_toggle (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CUACT` writer - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CUACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CUACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cuact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2DACT` reader - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_R = crate :: FieldReader < CCACT_01_CC2DACT_A > ; # [doc = "CCP Output Action on CC2D event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2DACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2DACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2DACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2DACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2DACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2DACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2DACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2DACT_A { type Ux = u8 ; } impl CCACT_01_CC2DACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2DACT_A { match self . bits { 0 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED , 1 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH , 2 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW , 3 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_disabled (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_high (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_low (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2DACT` writer - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2DACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2DACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2dact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2UACT` reader - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_R = crate :: FieldReader < CCACT_01_CC2UACT_A > ; # [doc = "CCP Output Action on CC2U event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2UACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2UACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2UACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2UACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2UACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2UACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2UACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2UACT_A { type Ux = u8 ; } impl CCACT_01_CC2UACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2UACT_A { match self . bits { 0 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED , 1 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH , 2 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW , 3 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_disabled (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_high (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_low (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2UACT` writer - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2UACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2UACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2uact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_SWFRCACT` reader - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_R = crate :: FieldReader < CCACT_01_SWFRCACT_A > ; # [doc = "CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_SWFRCACT_A { # [doc = "0: DISABLED"]
CCACT_01_SWFRCACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_SWFRCACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_SWFRCACT_CCP_LOW = 2 , } impl From < CCACT_01_SWFRCACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_SWFRCACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_SWFRCACT_A { type Ux = u8 ; } impl CCACT_01_SWFRCACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCACT_01_SWFRCACT_A > { match self . bits { 0 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) , 1 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) , 2 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) , _ => None , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_disabled (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_high (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_low (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW } } # [doc = "Field `CCACT_01_SWFRCACT` writer - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CCACT_01_SWFRCACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_SWFRCACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_swfrcact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) } } impl R { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
pub fn ccact_01_zact (& self) -> CCACT_01_ZACT_R { CCACT_01_ZACT_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
pub fn ccact_01_lact (& self) -> CCACT_01_LACT_R { CCACT_01_LACT_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
pub fn ccact_01_cdact (& self) -> CCACT_01_CDACT_R { CCACT_01_CDACT_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
pub fn ccact_01_cuact (& self) -> CCACT_01_CUACT_R { CCACT_01_CUACT_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
pub fn ccact_01_cc2dact (& self) -> CCACT_01_CC2DACT_R { CCACT_01_CC2DACT_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
pub fn ccact_01_cc2uact (& self) -> CCACT_01_CC2UACT_R { CCACT_01_CC2UACT_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
pub fn ccact_01_swfrcact (& self) -> CCACT_01_SWFRCACT_R { CCACT_01_SWFRCACT_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W < CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W < CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W < CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cuact (& mut self) -> CCACT_01_CUACT_W < CCACT_01_SPEC , 9 > { CCACT_01_CUACT_W :: new (self) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2dact (& mut self) -> CCACT_01_CC2DACT_W < CCACT_01_SPEC , 12 > { CCACT_01_CC2DACT_W :: new (self) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2uact (& mut self) -> CCACT_01_CC2UACT_W < CCACT_01_SPEC , 15 > { CCACT_01_CC2UACT_W :: new (self) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
# [must_use]
pub fn ccact_01_swfrcact (& mut self) -> CCACT_01_SWFRCACT_W < CCACT_01_SPEC , 28 > { CCACT_01_SWFRCACT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCACT_01_SPEC ; impl crate :: RegisterSpec for CCACT_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccact_01::R`](R) reader structure"]
impl crate :: Readable for CCACT_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccact_01::W`](W) writer structure"]
impl crate :: Writable for CCACT_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCACT_01[%s]
to value 0"]
impl crate :: Resettable for CCACT_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IFCTL_01 (rw) register accessor: Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifctl_01`]
module"]
pub type IFCTL_01 = crate :: Reg < ifctl_01 :: IFCTL_01_SPEC > ; # [doc = "Input Filter Control Register"]
pub mod ifctl_01 { # [doc = "Register `IFCTL_01[%s]` reader"]
pub type R = crate :: R < IFCTL_01_SPEC > ; # [doc = "Register `IFCTL_01[%s]` writer"]
pub type W = crate :: W < IFCTL_01_SPEC > ; # [doc = "Field `IFCTL_01_ISEL` reader - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_R = crate :: FieldReader < IFCTL_01_ISEL_A > ; # [doc = "Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_ISEL_A { # [doc = "0: CCPX_INPUT"]
IFCTL_01_ISEL_CCPX_INPUT = 0 , # [doc = "1: CCPX_INPUT_PAIR"]
IFCTL_01_ISEL_CCPX_INPUT_PAIR = 1 , # [doc = "2: CCP0_INPUT"]
IFCTL_01_ISEL_CCP0_INPUT = 2 , # [doc = "3: TRIG_INPUT"]
IFCTL_01_ISEL_TRIG_INPUT = 3 , # [doc = "4: CCP_XOR"]
IFCTL_01_ISEL_CCP_XOR = 4 , # [doc = "5: FSUB0"]
IFCTL_01_ISEL_FSUB0 = 5 , # [doc = "6: FSUB1"]
IFCTL_01_ISEL_FSUB1 = 6 , # [doc = "7: COMP0"]
IFCTL_01_ISEL_COMP0 = 7 , # [doc = "8: COMP1"]
IFCTL_01_ISEL_COMP1 = 8 , # [doc = "9: COMP2"]
IFCTL_01_ISEL_COMP2 = 9 , } impl From < IFCTL_01_ISEL_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_ISEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_ISEL_A { type Ux = u8 ; } impl IFCTL_01_ISEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_ISEL_A > { match self . bits { 0 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) , 1 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) , 2 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) , 3 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) , 4 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) , 5 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) , 6 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) , 7 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) , 8 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) , 9 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) , _ => None , } } # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input_pair (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp0_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_trig_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp_xor (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1 } # [doc = "COMP0"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0 } # [doc = "COMP1"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1 } # [doc = "COMP2"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp2 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2 } } # [doc = "Field `IFCTL_01_ISEL` writer - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , IFCTL_01_ISEL_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_ISEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input_pair (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_trig_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn ifctl_01_isel_ccp_xor (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) } # [doc = "FSUB0"]
# [inline (always)]
pub fn ifctl_01_isel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn ifctl_01_isel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) } # [doc = "COMP0"]
# [inline (always)]
pub fn ifctl_01_isel_comp0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) } # [doc = "COMP1"]
# [inline (always)]
pub fn ifctl_01_isel_comp1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) } # [doc = "COMP2"]
# [inline (always)]
pub fn ifctl_01_isel_comp2 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) } } # [doc = "Field `IFCTL_01_INV` reader - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_R = crate :: BitReader < IFCTL_01_INV_A > ; # [doc = "Input Inversion This bit controls whether the selected input is inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_INV_A { # [doc = "0: NOINVERT"]
IFCTL_01_INV_NOINVERT = 0 , # [doc = "1: INVERT"]
IFCTL_01_INV_INVERT = 1 , } impl From < IFCTL_01_INV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_INV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_INV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_INV_A { match self . bits { false => IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT , true => IFCTL_01_INV_A :: IFCTL_01_INV_INVERT , } } # [doc = "NOINVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_noinvert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT } # [doc = "INVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_invert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_INVERT } } # [doc = "Field `IFCTL_01_INV` writer - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_INV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_INV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINVERT"]
# [inline (always)]
pub fn ifctl_01_inv_noinvert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT) } # [doc = "INVERT"]
# [inline (always)]
pub fn ifctl_01_inv_invert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_INVERT) } } # [doc = "Field `IFCTL_01_FP` reader - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_R = crate :: FieldReader < IFCTL_01_FP_A > ; # [doc = "Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_FP_A { # [doc = "0: _3"]
IFCTL_01_FP__3 = 0 , # [doc = "1: _5"]
IFCTL_01_FP__5 = 1 , # [doc = "2: _8"]
IFCTL_01_FP__8 = 2 , } impl From < IFCTL_01_FP_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_FP_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_FP_A { type Ux = u8 ; } impl IFCTL_01_FP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_FP_A > { match self . bits { 0 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__3) , 1 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__5) , 2 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__8) , _ => None , } } # [doc = "_3"]
# [inline (always)]
pub fn is_ifctl_01_fp__3 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__3 } # [doc = "_5"]
# [inline (always)]
pub fn is_ifctl_01_fp__5 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__5 } # [doc = "_8"]
# [inline (always)]
pub fn is_ifctl_01_fp__8 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__8 } } # [doc = "Field `IFCTL_01_FP` writer - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , IFCTL_01_FP_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_3"]
# [inline (always)]
pub fn ifctl_01_fp__3 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__3) } # [doc = "_5"]
# [inline (always)]
pub fn ifctl_01_fp__5 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__5) } # [doc = "_8"]
# [inline (always)]
pub fn ifctl_01_fp__8 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__8) } } # [doc = "Field `IFCTL_01_CPV` reader - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_R = crate :: BitReader < IFCTL_01_CPV_A > ; # [doc = "Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_CPV_A { # [doc = "0: CONSECUTIVE"]
IFCTL_01_CPV_CONSECUTIVE = 0 , # [doc = "1: VOTING"]
IFCTL_01_CPV_VOTING = 1 , } impl From < IFCTL_01_CPV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_CPV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_CPV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_CPV_A { match self . bits { false => IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE , true => IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING , } } # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn is_ifctl_01_cpv_consecutive (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE } # [doc = "VOTING"]
# [inline (always)]
pub fn is_ifctl_01_cpv_voting (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING } } # [doc = "Field `IFCTL_01_CPV` writer - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_CPV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_CPV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn ifctl_01_cpv_consecutive (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE) } # [doc = "VOTING"]
# [inline (always)]
pub fn ifctl_01_cpv_voting (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING) } } # [doc = "Field `IFCTL_01_FE` reader - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_R = crate :: BitReader < IFCTL_01_FE_A > ; # [doc = "Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_FE_A { # [doc = "0: DISABLED"]
IFCTL_01_FE_DISABLED = 0 , # [doc = "1: ENABLED"]
IFCTL_01_FE_ENABLED = 1 , } impl From < IFCTL_01_FE_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_FE_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_FE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_FE_A { match self . bits { false => IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED , true => IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_disabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_enabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED } } # [doc = "Field `IFCTL_01_FE` writer - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_FE_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ifctl_01_fe_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ifctl_01_fe_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED) } } impl R { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
pub fn ifctl_01_isel (& self) -> IFCTL_01_ISEL_R { IFCTL_01_ISEL_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
pub fn ifctl_01_inv (& self) -> IFCTL_01_INV_R { IFCTL_01_INV_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
pub fn ifctl_01_fp (& self) -> IFCTL_01_FP_R { IFCTL_01_FP_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
pub fn ifctl_01_cpv (& self) -> IFCTL_01_CPV_R { IFCTL_01_CPV_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
pub fn ifctl_01_fe (& self) -> IFCTL_01_FE_R { IFCTL_01_FE_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
# [must_use]
pub fn ifctl_01_isel (& mut self) -> IFCTL_01_ISEL_W < IFCTL_01_SPEC , 0 > { IFCTL_01_ISEL_W :: new (self) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_inv (& mut self) -> IFCTL_01_INV_W < IFCTL_01_SPEC , 7 > { IFCTL_01_INV_W :: new (self) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fp (& mut self) -> IFCTL_01_FP_W < IFCTL_01_SPEC , 8 > { IFCTL_01_FP_W :: new (self) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_cpv (& mut self) -> IFCTL_01_CPV_W < IFCTL_01_SPEC , 11 > { IFCTL_01_CPV_W :: new (self) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fe (& mut self) -> IFCTL_01_FE_W < IFCTL_01_SPEC , 12 > { IFCTL_01_FE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IFCTL_01_SPEC ; impl crate :: RegisterSpec for IFCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifctl_01::R`](R) reader structure"]
impl crate :: Readable for IFCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifctl_01::W`](W) writer structure"]
impl crate :: Writable for IFCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFCTL_01[%s]
to value 0"]
impl crate :: Resettable for IFCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TSEL (rw) register accessor: Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsel`]
module"]
pub type TSEL = crate :: Reg < tsel :: TSEL_SPEC > ; # [doc = "Trigger Select"]
pub mod tsel { # [doc = "Register `TSEL` reader"]
pub type R = crate :: R < TSEL_SPEC > ; # [doc = "Register `TSEL` writer"]
pub type W = crate :: W < TSEL_SPEC > ; # [doc = "Field `TSEL_ETSEL` reader - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_R = crate :: FieldReader < TSEL_ETSEL_A > ; # [doc = "External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum TSEL_ETSEL_A { # [doc = "0: TRIG0"]
TSEL_ETSEL_TRIG0 = 0 , # [doc = "1: TRIG1"]
TSEL_ETSEL_TRIG1 = 1 , # [doc = "2: TRIG2"]
TSEL_ETSEL_TRIG2 = 2 , # [doc = "3: TRIG3"]
TSEL_ETSEL_TRIG3 = 3 , # [doc = "4: TRIG4"]
TSEL_ETSEL_TRIG4 = 4 , # [doc = "5: TRIG5"]
TSEL_ETSEL_TRIG5 = 5 , # [doc = "6: TRIG6"]
TSEL_ETSEL_TRIG6 = 6 , # [doc = "7: TRIG7"]
TSEL_ETSEL_TRIG7 = 7 , # [doc = "8: TRIG8"]
TSEL_ETSEL_TRIG8 = 8 , # [doc = "9: TRIG9"]
TSEL_ETSEL_TRIG9 = 9 , # [doc = "10: TRIG10"]
TSEL_ETSEL_TRIG10 = 10 , # [doc = "11: TRIG11"]
TSEL_ETSEL_TRIG11 = 11 , # [doc = "12: TRIG12"]
TSEL_ETSEL_TRIG12 = 12 , # [doc = "13: TRIG13"]
TSEL_ETSEL_TRIG13 = 13 , # [doc = "14: TRIG14"]
TSEL_ETSEL_TRIG14 = 14 , # [doc = "15: TRIG15"]
TSEL_ETSEL_TRIG15 = 15 , # [doc = "16: TRIG_SUB0"]
TSEL_ETSEL_TRIG_SUB0 = 16 , # [doc = "17: TRIG_SUB1"]
TSEL_ETSEL_TRIG_SUB1 = 17 , } impl From < TSEL_ETSEL_A > for u8 { # [inline (always)]
fn from (variant : TSEL_ETSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for TSEL_ETSEL_A { type Ux = u8 ; } impl TSEL_ETSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < TSEL_ETSEL_A > { match self . bits { 0 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) , 1 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) , 2 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) , 3 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) , 4 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) , 5 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) , 6 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) , 7 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) , 8 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) , 9 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) , 10 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) , 11 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) , 12 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) , 13 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) , 14 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) , 15 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) , 16 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) , 17 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) , _ => None , } } # [doc = "TRIG0"]
# [inline (always)]
pub fn is_tsel_etsel_trig0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0 } # [doc = "TRIG1"]
# [inline (always)]
pub fn is_tsel_etsel_trig1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1 } # [doc = "TRIG2"]
# [inline (always)]
pub fn is_tsel_etsel_trig2 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2 } # [doc = "TRIG3"]
# [inline (always)]
pub fn is_tsel_etsel_trig3 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3 } # [doc = "TRIG4"]
# [inline (always)]
pub fn is_tsel_etsel_trig4 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4 } # [doc = "TRIG5"]
# [inline (always)]
pub fn is_tsel_etsel_trig5 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5 } # [doc = "TRIG6"]
# [inline (always)]
pub fn is_tsel_etsel_trig6 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6 } # [doc = "TRIG7"]
# [inline (always)]
pub fn is_tsel_etsel_trig7 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7 } # [doc = "TRIG8"]
# [inline (always)]
pub fn is_tsel_etsel_trig8 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8 } # [doc = "TRIG9"]
# [inline (always)]
pub fn is_tsel_etsel_trig9 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9 } # [doc = "TRIG10"]
# [inline (always)]
pub fn is_tsel_etsel_trig10 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10 } # [doc = "TRIG11"]
# [inline (always)]
pub fn is_tsel_etsel_trig11 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11 } # [doc = "TRIG12"]
# [inline (always)]
pub fn is_tsel_etsel_trig12 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12 } # [doc = "TRIG13"]
# [inline (always)]
pub fn is_tsel_etsel_trig13 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13 } # [doc = "TRIG14"]
# [inline (always)]
pub fn is_tsel_etsel_trig14 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14 } # [doc = "TRIG15"]
# [inline (always)]
pub fn is_tsel_etsel_trig15 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15 } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0 } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1 } } # [doc = "Field `TSEL_ETSEL` writer - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , TSEL_ETSEL_A > ; impl < 'a , REG , const O : u8 > TSEL_ETSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TRIG0"]
# [inline (always)]
pub fn tsel_etsel_trig0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) } # [doc = "TRIG1"]
# [inline (always)]
pub fn tsel_etsel_trig1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) } # [doc = "TRIG2"]
# [inline (always)]
pub fn tsel_etsel_trig2 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) } # [doc = "TRIG3"]
# [inline (always)]
pub fn tsel_etsel_trig3 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) } # [doc = "TRIG4"]
# [inline (always)]
pub fn tsel_etsel_trig4 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) } # [doc = "TRIG5"]
# [inline (always)]
pub fn tsel_etsel_trig5 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) } # [doc = "TRIG6"]
# [inline (always)]
pub fn tsel_etsel_trig6 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) } # [doc = "TRIG7"]
# [inline (always)]
pub fn tsel_etsel_trig7 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) } # [doc = "TRIG8"]
# [inline (always)]
pub fn tsel_etsel_trig8 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) } # [doc = "TRIG9"]
# [inline (always)]
pub fn tsel_etsel_trig9 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) } # [doc = "TRIG10"]
# [inline (always)]
pub fn tsel_etsel_trig10 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) } # [doc = "TRIG11"]
# [inline (always)]
pub fn tsel_etsel_trig11 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) } # [doc = "TRIG12"]
# [inline (always)]
pub fn tsel_etsel_trig12 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) } # [doc = "TRIG13"]
# [inline (always)]
pub fn tsel_etsel_trig13 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) } # [doc = "TRIG14"]
# [inline (always)]
pub fn tsel_etsel_trig14 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) } # [doc = "TRIG15"]
# [inline (always)]
pub fn tsel_etsel_trig15 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn tsel_etsel_trig_sub0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn tsel_etsel_trig_sub1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) } } # [doc = "Field `TSEL_TE` reader - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_R = crate :: BitReader < TSEL_TE_A > ; # [doc = "Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TSEL_TE_A { # [doc = "0: DISABLED"]
TSEL_TE_DISABLED = 0 , # [doc = "1: ENABLED"]
TSEL_TE_ENABLED = 1 , } impl From < TSEL_TE_A > for bool { # [inline (always)]
fn from (variant : TSEL_TE_A) -> Self { variant as u8 != 0 } } impl TSEL_TE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TSEL_TE_A { match self . bits { false => TSEL_TE_A :: TSEL_TE_DISABLED , true => TSEL_TE_A :: TSEL_TE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_tsel_te_disabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_tsel_te_enabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_ENABLED } } # [doc = "Field `TSEL_TE` writer - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TSEL_TE_A > ; impl < 'a , REG , const O : u8 > TSEL_TE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn tsel_te_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn tsel_te_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_ENABLED) } } impl R { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
pub fn tsel_etsel (& self) -> TSEL_ETSEL_R { TSEL_ETSEL_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
pub fn tsel_te (& self) -> TSEL_TE_R { TSEL_TE_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
# [must_use]
pub fn tsel_etsel (& mut self) -> TSEL_ETSEL_W < TSEL_SPEC , 0 > { TSEL_ETSEL_W :: new (self) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
# [must_use]
pub fn tsel_te (& mut self) -> TSEL_TE_W < TSEL_SPEC , 9 > { TSEL_TE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TSEL_SPEC ; impl crate :: RegisterSpec for TSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`tsel::R`](R) reader structure"]
impl crate :: Readable for TSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`tsel::W`](W) writer structure"]
impl crate :: Writable for TSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TSEL to value 0"]
impl crate :: Resettable for TSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct ADC0 { _marker : PhantomData < * const () > } unsafe impl Send for ADC0 { } impl ADC0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const adc0 :: RegisterBlock = 0x4000_4000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const adc0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for ADC0 { type Target = adc0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for ADC0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("ADC0") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod adc0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subscriber Configuration Register."]
pub fsub_0 : FSUB_0 , _reserved1 : [u8 ; 0x40]
, # [doc = "0x444 - Publisher Configuration Register."]
pub fpub_1 : FPUB_1 , _reserved2 : [u8 ; 0x03b8]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , # [doc = "0x808 - ADC clock configuration Register"]
pub clkcfg : CLKCFG , _reserved5 : [u8 ; 0x08]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved6 : [u8 ; 0x0808]
, # [doc = "0x1020 - Interrupt index"]
pub int_event0_iidx : INT_EVENT0_IIDX , _reserved7 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub int_event0_imask : INT_EVENT0_IMASK , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub int_event0_ris : INT_EVENT0_RIS , _reserved9 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub int_event0_mis : INT_EVENT0_MIS , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub int_event0_iset : INT_EVENT0_ISET , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub int_event0_iclr : INT_EVENT0_ICLR , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1050 - Interrupt index"]
pub int_event1_iidx : INT_EVENT1_IIDX , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1058 - Interrupt mask"]
pub int_event1_imask : INT_EVENT1_IMASK , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1060 - Raw interrupt status"]
pub int_event1_ris : INT_EVENT1_RIS , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1068 - Masked interrupt status"]
pub int_event1_mis : INT_EVENT1_MIS , _reserved16 : [u8 ; 0x04]
, # [doc = "0x1070 - Interrupt set"]
pub int_event1_iset : INT_EVENT1_ISET , _reserved17 : [u8 ; 0x04]
, # [doc = "0x1078 - Interrupt clear"]
pub int_event1_iclr : INT_EVENT1_ICLR , _reserved18 : [u8 ; 0x04]
, # [doc = "0x1080 - Interrupt index"]
pub int_event2_iidx : INT_EVENT2_IIDX , _reserved19 : [u8 ; 0x04]
, # [doc = "0x1088 - Interrupt mask extension"]
pub int_event2_imask : INT_EVENT2_IMASK , _reserved20 : [u8 ; 0x04]
, # [doc = "0x1090 - Raw interrupt status extension"]
pub int_event2_ris : INT_EVENT2_RIS , _reserved21 : [u8 ; 0x04]
, # [doc = "0x1098 - Masked interrupt status extension"]
pub int_event2_mis : INT_EVENT2_MIS , _reserved22 : [u8 ; 0x04]
, # [doc = "0x10a0 - Interrupt set extension"]
pub int_event2_iset : INT_EVENT2_ISET , _reserved23 : [u8 ; 0x04]
, # [doc = "0x10a8 - Interrupt clear extension"]
pub int_event2_iclr : INT_EVENT2_ICLR , _reserved24 : [u8 ; 0x34]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved25 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - Control Register 0"]
pub ctl0 : CTL0 , # [doc = "0x1104 - Control Register 1"]
pub ctl1 : CTL1 , # [doc = "0x1108 - Control Register 2"]
pub ctl2 : CTL2 , # [doc = "0x110c - Control Register 3"]
pub ctl3 : CTL3 , # [doc = "0x1110 - Sample Clock Frequency Range Register"]
pub clkfreq : CLKFREQ , # [doc = "0x1114 - Sample Time Compare 0 Register"]
pub scomp0 : SCOMP0 , # [doc = "0x1118 - Sample Time Compare 1 Register"]
pub scomp1 : SCOMP1 , # [doc = "0x111c - Reference Buffer Configuration Register"]
pub refcfg : REFCFG , _reserved34 : [u8 ; 0x28]
, # [doc = "0x1148 - Window Comparator Low Threshold Register"]
pub wclow : WCLOW , _reserved35 : [u8 ; 0x04]
, # [doc = "0x1150 - Window Comparator High Threshold Register"]
pub wchigh : WCHIGH , _reserved36 : [u8 ; 0x2c]
, # [doc = "0x1180..0x1190 - Conversion Memory Control Register"]
pub memctl : [MEMCTL ; 4]
, _reserved37 : [u8 ; 0x01b0]
, # [doc = "0x1340 - Status Register"]
pub status : STATUS , } # [doc = "FSUB_0 (rw) register accessor: Subscriber Configuration Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subscriber Configuration Register."]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Configuration Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher Configuration Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher Configuration Register."]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Configuration Register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKCFG (rw) register accessor: ADC clock configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkcfg`]
module"]
pub type CLKCFG = crate :: Reg < clkcfg :: CLKCFG_SPEC > ; # [doc = "ADC clock configuration Register"]
pub mod clkcfg { # [doc = "Register `CLKCFG` reader"]
pub type R = crate :: R < CLKCFG_SPEC > ; # [doc = "Register `CLKCFG` writer"]
pub type W = crate :: W < CLKCFG_SPEC > ; # [doc = "Field `CLKCFG_SAMPCLK` reader - ADC sample clock source selection."]
pub type CLKCFG_SAMPCLK_R = crate :: FieldReader < CLKCFG_SAMPCLK_A > ; # [doc = "ADC sample clock source selection.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_SAMPCLK_A { # [doc = "0: SYSOSC"]
CLKCFG_SAMPCLK_SYSOSC = 0 , # [doc = "1: ULPCLK"]
CLKCFG_SAMPCLK_ULPCLK = 1 , # [doc = "2: HFCLK"]
CLKCFG_SAMPCLK_HFCLK = 2 , } impl From < CLKCFG_SAMPCLK_A > for u8 { # [inline (always)]
fn from (variant : CLKCFG_SAMPCLK_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_SAMPCLK_A { type Ux = u8 ; } impl CLKCFG_SAMPCLK_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CLKCFG_SAMPCLK_A > { match self . bits { 0 => Some (CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_SYSOSC) , 1 => Some (CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_ULPCLK) , 2 => Some (CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_HFCLK) , _ => None , } } # [doc = "SYSOSC"]
# [inline (always)]
pub fn is_clkcfg_sampclk_sysosc (& self) -> bool { * self == CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_SYSOSC } # [doc = "ULPCLK"]
# [inline (always)]
pub fn is_clkcfg_sampclk_ulpclk (& self) -> bool { * self == CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_ULPCLK } # [doc = "HFCLK"]
# [inline (always)]
pub fn is_clkcfg_sampclk_hfclk (& self) -> bool { * self == CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_HFCLK } } # [doc = "Field `CLKCFG_SAMPCLK` writer - ADC sample clock source selection."]
pub type CLKCFG_SAMPCLK_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CLKCFG_SAMPCLK_A > ; impl < 'a , REG , const O : u8 > CLKCFG_SAMPCLK_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SYSOSC"]
# [inline (always)]
pub fn clkcfg_sampclk_sysosc (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_SYSOSC) } # [doc = "ULPCLK"]
# [inline (always)]
pub fn clkcfg_sampclk_ulpclk (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_ULPCLK) } # [doc = "HFCLK"]
# [inline (always)]
pub fn clkcfg_sampclk_hfclk (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_SAMPCLK_A :: CLKCFG_SAMPCLK_HFCLK) } } # [doc = "Field `CLKCFG_CCONRUN` reader - CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source."]
pub type CLKCFG_CCONRUN_R = crate :: BitReader < CLKCFG_CCONRUN_A > ; # [doc = "CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_CCONRUN_A { # [doc = "0: DISABLE"]
CLKCFG_CCONRUN_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_CCONRUN_ENABLE = 1 , } impl From < CLKCFG_CCONRUN_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_CCONRUN_A) -> Self { variant as u8 != 0 } } impl CLKCFG_CCONRUN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_CCONRUN_A { match self . bits { false => CLKCFG_CCONRUN_A :: CLKCFG_CCONRUN_DISABLE , true => CLKCFG_CCONRUN_A :: CLKCFG_CCONRUN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_cconrun_disable (& self) -> bool { * self == CLKCFG_CCONRUN_A :: CLKCFG_CCONRUN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_cconrun_enable (& self) -> bool { * self == CLKCFG_CCONRUN_A :: CLKCFG_CCONRUN_ENABLE } } # [doc = "Field `CLKCFG_CCONRUN` writer - CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source."]
pub type CLKCFG_CCONRUN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_CCONRUN_A > ; impl < 'a , REG , const O : u8 > CLKCFG_CCONRUN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_cconrun_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_CCONRUN_A :: CLKCFG_CCONRUN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_cconrun_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_CCONRUN_A :: CLKCFG_CCONRUN_ENABLE) } } # [doc = "Field `CLKCFG_CCONSTOP` reader - CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source."]
pub type CLKCFG_CCONSTOP_R = crate :: BitReader < CLKCFG_CCONSTOP_A > ; # [doc = "CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKCFG_CCONSTOP_A { # [doc = "0: DISABLE"]
CLKCFG_CCONSTOP_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKCFG_CCONSTOP_ENABLE = 1 , } impl From < CLKCFG_CCONSTOP_A > for bool { # [inline (always)]
fn from (variant : CLKCFG_CCONSTOP_A) -> Self { variant as u8 != 0 } } impl CLKCFG_CCONSTOP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKCFG_CCONSTOP_A { match self . bits { false => CLKCFG_CCONSTOP_A :: CLKCFG_CCONSTOP_DISABLE , true => CLKCFG_CCONSTOP_A :: CLKCFG_CCONSTOP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clkcfg_cconstop_disable (& self) -> bool { * self == CLKCFG_CCONSTOP_A :: CLKCFG_CCONSTOP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clkcfg_cconstop_enable (& self) -> bool { * self == CLKCFG_CCONSTOP_A :: CLKCFG_CCONSTOP_ENABLE } } # [doc = "Field `CLKCFG_CCONSTOP` writer - CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source."]
pub type CLKCFG_CCONSTOP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKCFG_CCONSTOP_A > ; impl < 'a , REG , const O : u8 > CLKCFG_CCONSTOP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clkcfg_cconstop_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_CCONSTOP_A :: CLKCFG_CCONSTOP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clkcfg_cconstop_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_CCONSTOP_A :: CLKCFG_CCONSTOP_ENABLE) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKCFG_KEY_AW { # [doc = "169: _TO_UNLOCK_W_"]
CLKCFG_KEY_UNLOCK_W = 169 , } impl From < CLKCFG_KEY_AW > for u8 { # [inline (always)]
fn from (variant : CLKCFG_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for CLKCFG_KEY_AW { type Ux = u8 ; } # [doc = "Field `CLKCFG_KEY` writer - Unlock key"]
pub type CLKCFG_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , CLKCFG_KEY_AW > ; impl < 'a , REG , const O : u8 > CLKCFG_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn clkcfg_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (CLKCFG_KEY_AW :: CLKCFG_KEY_UNLOCK_W) } } impl R { # [doc = "Bits 0:1 - ADC sample clock source selection."]
# [inline (always)]
pub fn clkcfg_sampclk (& self) -> CLKCFG_SAMPCLK_R { CLKCFG_SAMPCLK_R :: new ((self . bits & 3) as u8) } # [doc = "Bit 4 - CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source."]
# [inline (always)]
pub fn clkcfg_cconrun (& self) -> CLKCFG_CCONRUN_R { CLKCFG_CCONRUN_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source."]
# [inline (always)]
pub fn clkcfg_cconstop (& self) -> CLKCFG_CCONSTOP_R { CLKCFG_CCONSTOP_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:1 - ADC sample clock source selection."]
# [inline (always)]
# [must_use]
pub fn clkcfg_sampclk (& mut self) -> CLKCFG_SAMPCLK_W < CLKCFG_SPEC , 0 > { CLKCFG_SAMPCLK_W :: new (self) } # [doc = "Bit 4 - CCONRUN: Forces SYSOSC to run at base frequency when device is in RUN mode which can be used as ADC sample or conversion clock source."]
# [inline (always)]
# [must_use]
pub fn clkcfg_cconrun (& mut self) -> CLKCFG_CCONRUN_W < CLKCFG_SPEC , 4 > { CLKCFG_CCONRUN_W :: new (self) } # [doc = "Bit 5 - CCONSTOP: Forces SYSOSC to run at base frequency when device is in STOP mode which can be used as ADC sample or conversion clock source."]
# [inline (always)]
# [must_use]
pub fn clkcfg_cconstop (& mut self) -> CLKCFG_CCONSTOP_W < CLKCFG_SPEC , 5 > { CLKCFG_CCONSTOP_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn clkcfg_key (& mut self) -> CLKCFG_KEY_W < CLKCFG_SPEC , 24 > { CLKCFG_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "ADC clock configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKCFG_SPEC ; impl crate :: RegisterSpec for CLKCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkcfg::R`](R) reader structure"]
impl crate :: Readable for CLKCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkcfg::W`](W) writer structure"]
impl crate :: Writable for CLKCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKCFG to value 0"]
impl crate :: Resettable for CLKCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iidx`]
module"]
pub type INT_EVENT0_IIDX = crate :: Reg < int_event0_iidx :: INT_EVENT0_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event0_iidx { # [doc = "Register `INT_EVENT0_IIDX` reader"]
pub type R = crate :: R < INT_EVENT0_IIDX_SPEC > ; # [doc = "Field `INT_EVENT0_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT0_IIDX_STAT_R = crate :: FieldReader < INT_EVENT0_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u16)]
pub enum INT_EVENT0_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT0_IIDX_STAT_NO_INTR = 0 , # [doc = "1: OVIFG"]
INT_EVENT0_IIDX_STAT_OVIFG = 1 , # [doc = "2: TOVIFG"]
INT_EVENT0_IIDX_STAT_TOVIFG = 2 , # [doc = "3: HIGHIFG"]
INT_EVENT0_IIDX_STAT_HIGHIFG = 3 , # [doc = "4: LOWIFG"]
INT_EVENT0_IIDX_STAT_LOWIFG = 4 , # [doc = "5: INIFG"]
INT_EVENT0_IIDX_STAT_INIFG = 5 , # [doc = "6: DMADONE"]
INT_EVENT0_IIDX_STAT_DMADONE = 6 , # [doc = "7: UVIFG"]
INT_EVENT0_IIDX_STAT_UVIFG = 7 , # [doc = "9: MEMRESIFG0"]
INT_EVENT0_IIDX_STAT_MEMRESIFG0 = 9 , # [doc = "10: MEMRESIFG1"]
INT_EVENT0_IIDX_STAT_MEMRESIFG1 = 10 , # [doc = "11: MEMRESIFG2"]
INT_EVENT0_IIDX_STAT_MEMRESIFG2 = 11 , # [doc = "12: MEMRESIFG3"]
INT_EVENT0_IIDX_STAT_MEMRESIFG3 = 12 , # [doc = "13: MEMRESIFG4"]
INT_EVENT0_IIDX_STAT_MEMRESIFG4 = 13 , # [doc = "14: MEMRESIFG5"]
INT_EVENT0_IIDX_STAT_MEMRESIFG5 = 14 , # [doc = "15: MEMRESIFG6"]
INT_EVENT0_IIDX_STAT_MEMRESIFG6 = 15 , # [doc = "16: MEMRESIFG7"]
INT_EVENT0_IIDX_STAT_MEMRESIFG7 = 16 , # [doc = "17: MEMRESIFG8"]
INT_EVENT0_IIDX_STAT_MEMRESIFG8 = 17 , # [doc = "18: MEMRESIFG9"]
INT_EVENT0_IIDX_STAT_MEMRESIFG9 = 18 , # [doc = "19: MEMRESIFG10"]
INT_EVENT0_IIDX_STAT_MEMRESIFG10 = 19 , # [doc = "20: MEMRESIFG11"]
INT_EVENT0_IIDX_STAT_MEMRESIFG11 = 20 , # [doc = "21: MEMRESIFG12"]
INT_EVENT0_IIDX_STAT_MEMRESIFG12 = 21 , # [doc = "22: MEMRESIFG13"]
INT_EVENT0_IIDX_STAT_MEMRESIFG13 = 22 , # [doc = "23: MEMRESIFG14"]
INT_EVENT0_IIDX_STAT_MEMRESIFG14 = 23 , # [doc = "24: MEMRESIFG15"]
INT_EVENT0_IIDX_STAT_MEMRESIFG15 = 24 , # [doc = "25: MEMRESIFG16"]
INT_EVENT0_IIDX_STAT_MEMRESIFG16 = 25 , # [doc = "26: MEMRESIFG17"]
INT_EVENT0_IIDX_STAT_MEMRESIFG17 = 26 , # [doc = "27: MEMRESIFG18"]
INT_EVENT0_IIDX_STAT_MEMRESIFG18 = 27 , # [doc = "28: MEMRESIFG19"]
INT_EVENT0_IIDX_STAT_MEMRESIFG19 = 28 , # [doc = "29: MEMRESIFG20"]
INT_EVENT0_IIDX_STAT_MEMRESIFG20 = 29 , # [doc = "30: MEMRESIFG21"]
INT_EVENT0_IIDX_STAT_MEMRESIFG21 = 30 , # [doc = "31: MEMRESIFG22"]
INT_EVENT0_IIDX_STAT_MEMRESIFG22 = 31 , # [doc = "32: MEMRESIFG23"]
INT_EVENT0_IIDX_STAT_MEMRESIFG23 = 32 , } impl From < INT_EVENT0_IIDX_STAT_A > for u16 { # [inline (always)]
fn from (variant : INT_EVENT0_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT0_IIDX_STAT_A { type Ux = u16 ; } impl INT_EVENT0_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT0_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR) , 1 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_OVIFG) , 2 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TOVIFG) , 3 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_HIGHIFG) , 4 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LOWIFG) , 5 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_INIFG) , 6 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMADONE) , 7 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_UVIFG) , 9 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG0) , 10 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG1) , 11 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG2) , 12 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG3) , 13 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG4) , 14 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG5) , 15 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG6) , 16 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG7) , 17 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG8) , 18 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG9) , 19 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG10) , 20 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG11) , 21 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG12) , 22 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG13) , 23 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG14) , 24 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG15) , 25 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG16) , 26 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG17) , 27 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG18) , 28 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG19) , 29 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG20) , 30 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG21) , 31 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG22) , 32 => Some (INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG23) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_NO_INTR } # [doc = "OVIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_ovifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_OVIFG } # [doc = "TOVIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_tovifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_TOVIFG } # [doc = "HIGHIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_highifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_HIGHIFG } # [doc = "LOWIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_lowifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_LOWIFG } # [doc = "INIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_inifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_INIFG } # [doc = "DMADONE"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_dmadone (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_DMADONE } # [doc = "UVIFG"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_uvifg (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_UVIFG } # [doc = "MEMRESIFG0"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg0 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG0 } # [doc = "MEMRESIFG1"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg1 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG1 } # [doc = "MEMRESIFG2"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg2 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG2 } # [doc = "MEMRESIFG3"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg3 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG3 } # [doc = "MEMRESIFG4"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg4 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG4 } # [doc = "MEMRESIFG5"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg5 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG5 } # [doc = "MEMRESIFG6"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg6 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG6 } # [doc = "MEMRESIFG7"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg7 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG7 } # [doc = "MEMRESIFG8"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg8 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG8 } # [doc = "MEMRESIFG9"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg9 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG9 } # [doc = "MEMRESIFG10"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg10 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG10 } # [doc = "MEMRESIFG11"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg11 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG11 } # [doc = "MEMRESIFG12"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg12 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG12 } # [doc = "MEMRESIFG13"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg13 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG13 } # [doc = "MEMRESIFG14"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg14 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG14 } # [doc = "MEMRESIFG15"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg15 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG15 } # [doc = "MEMRESIFG16"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg16 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG16 } # [doc = "MEMRESIFG17"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg17 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG17 } # [doc = "MEMRESIFG18"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg18 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG18 } # [doc = "MEMRESIFG19"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg19 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG19 } # [doc = "MEMRESIFG20"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg20 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG20 } # [doc = "MEMRESIFG21"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg21 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG21 } # [doc = "MEMRESIFG22"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg22 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG22 } # [doc = "MEMRESIFG23"]
# [inline (always)]
pub fn is_int_event0_iidx_stat_memresifg23 (& self) -> bool { * self == INT_EVENT0_IIDX_STAT_A :: INT_EVENT0_IIDX_STAT_MEMRESIFG23 } } impl R { # [doc = "Bits 0:9 - Interrupt index status"]
# [inline (always)]
pub fn int_event0_iidx_stat (& self) -> INT_EVENT0_IIDX_STAT_R { INT_EVENT0_IIDX_STAT_R :: new ((self . bits & 0x03ff) as u16) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT0_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_imask`]
module"]
pub type INT_EVENT0_IMASK = crate :: Reg < int_event0_imask :: INT_EVENT0_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event0_imask { # [doc = "Register `INT_EVENT0_IMASK` reader"]
pub type R = crate :: R < INT_EVENT0_IMASK_SPEC > ; # [doc = "Register `INT_EVENT0_IMASK` writer"]
pub type W = crate :: W < INT_EVENT0_IMASK_SPEC > ; # [doc = "Field `INT_EVENT0_IMASK_OVIFG` reader - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_OVIFG_R = crate :: BitReader < INT_EVENT0_IMASK_OVIFG_A > ; # [doc = "Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_OVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_OVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_OVIFG_SET = 1 , } impl From < INT_EVENT0_IMASK_OVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_OVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_OVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_OVIFG_A { match self . bits { false => INT_EVENT0_IMASK_OVIFG_A :: INT_EVENT0_IMASK_OVIFG_CLR , true => INT_EVENT0_IMASK_OVIFG_A :: INT_EVENT0_IMASK_OVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_ovifg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_OVIFG_A :: INT_EVENT0_IMASK_OVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_ovifg_set (& self) -> bool { * self == INT_EVENT0_IMASK_OVIFG_A :: INT_EVENT0_IMASK_OVIFG_SET } } # [doc = "Field `INT_EVENT0_IMASK_OVIFG` writer - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_OVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_OVIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_OVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_ovifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVIFG_A :: INT_EVENT0_IMASK_OVIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_ovifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_OVIFG_A :: INT_EVENT0_IMASK_OVIFG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_TOVIFG` reader - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_TOVIFG_R = crate :: BitReader < INT_EVENT0_IMASK_TOVIFG_A > ; # [doc = "Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_TOVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_TOVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_TOVIFG_SET = 1 , } impl From < INT_EVENT0_IMASK_TOVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_TOVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_TOVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_TOVIFG_A { match self . bits { false => INT_EVENT0_IMASK_TOVIFG_A :: INT_EVENT0_IMASK_TOVIFG_CLR , true => INT_EVENT0_IMASK_TOVIFG_A :: INT_EVENT0_IMASK_TOVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_tovifg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_TOVIFG_A :: INT_EVENT0_IMASK_TOVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_tovifg_set (& self) -> bool { * self == INT_EVENT0_IMASK_TOVIFG_A :: INT_EVENT0_IMASK_TOVIFG_SET } } # [doc = "Field `INT_EVENT0_IMASK_TOVIFG` writer - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_TOVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_TOVIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_TOVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_tovifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TOVIFG_A :: INT_EVENT0_IMASK_TOVIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_tovifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_TOVIFG_A :: INT_EVENT0_IMASK_TOVIFG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_HIGHIFG` reader - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_HIGHIFG_R = crate :: BitReader < INT_EVENT0_IMASK_HIGHIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_HIGHIFG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_HIGHIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_HIGHIFG_SET = 1 , } impl From < INT_EVENT0_IMASK_HIGHIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_HIGHIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_HIGHIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_HIGHIFG_A { match self . bits { false => INT_EVENT0_IMASK_HIGHIFG_A :: INT_EVENT0_IMASK_HIGHIFG_CLR , true => INT_EVENT0_IMASK_HIGHIFG_A :: INT_EVENT0_IMASK_HIGHIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_highifg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_HIGHIFG_A :: INT_EVENT0_IMASK_HIGHIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_highifg_set (& self) -> bool { * self == INT_EVENT0_IMASK_HIGHIFG_A :: INT_EVENT0_IMASK_HIGHIFG_SET } } # [doc = "Field `INT_EVENT0_IMASK_HIGHIFG` writer - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_HIGHIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_HIGHIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_HIGHIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_highifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_HIGHIFG_A :: INT_EVENT0_IMASK_HIGHIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_highifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_HIGHIFG_A :: INT_EVENT0_IMASK_HIGHIFG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_LOWIFG` reader - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_LOWIFG_R = crate :: BitReader < INT_EVENT0_IMASK_LOWIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_LOWIFG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_LOWIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_LOWIFG_SET = 1 , } impl From < INT_EVENT0_IMASK_LOWIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_LOWIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_LOWIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_LOWIFG_A { match self . bits { false => INT_EVENT0_IMASK_LOWIFG_A :: INT_EVENT0_IMASK_LOWIFG_CLR , true => INT_EVENT0_IMASK_LOWIFG_A :: INT_EVENT0_IMASK_LOWIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_lowifg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_LOWIFG_A :: INT_EVENT0_IMASK_LOWIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_lowifg_set (& self) -> bool { * self == INT_EVENT0_IMASK_LOWIFG_A :: INT_EVENT0_IMASK_LOWIFG_SET } } # [doc = "Field `INT_EVENT0_IMASK_LOWIFG` writer - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_LOWIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_LOWIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_LOWIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_lowifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LOWIFG_A :: INT_EVENT0_IMASK_LOWIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_lowifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_LOWIFG_A :: INT_EVENT0_IMASK_LOWIFG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_INIFG` reader - Mask INIFG in MIS_EX register."]
pub type INT_EVENT0_IMASK_INIFG_R = crate :: BitReader < INT_EVENT0_IMASK_INIFG_A > ; # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_INIFG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_INIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_INIFG_SET = 1 , } impl From < INT_EVENT0_IMASK_INIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_INIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_INIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_INIFG_A { match self . bits { false => INT_EVENT0_IMASK_INIFG_A :: INT_EVENT0_IMASK_INIFG_CLR , true => INT_EVENT0_IMASK_INIFG_A :: INT_EVENT0_IMASK_INIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_inifg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_INIFG_A :: INT_EVENT0_IMASK_INIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_inifg_set (& self) -> bool { * self == INT_EVENT0_IMASK_INIFG_A :: INT_EVENT0_IMASK_INIFG_SET } } # [doc = "Field `INT_EVENT0_IMASK_INIFG` writer - Mask INIFG in MIS_EX register."]
pub type INT_EVENT0_IMASK_INIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_INIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_INIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_inifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_INIFG_A :: INT_EVENT0_IMASK_INIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_inifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_INIFG_A :: INT_EVENT0_IMASK_INIFG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_DMADONE` reader - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_DMADONE_R = crate :: BitReader < INT_EVENT0_IMASK_DMADONE_A > ; # [doc = "Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_DMADONE_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_DMADONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_DMADONE_SET = 1 , } impl From < INT_EVENT0_IMASK_DMADONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_DMADONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_DMADONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_DMADONE_A { match self . bits { false => INT_EVENT0_IMASK_DMADONE_A :: INT_EVENT0_IMASK_DMADONE_CLR , true => INT_EVENT0_IMASK_DMADONE_A :: INT_EVENT0_IMASK_DMADONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_dmadone_clr (& self) -> bool { * self == INT_EVENT0_IMASK_DMADONE_A :: INT_EVENT0_IMASK_DMADONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_dmadone_set (& self) -> bool { * self == INT_EVENT0_IMASK_DMADONE_A :: INT_EVENT0_IMASK_DMADONE_SET } } # [doc = "Field `INT_EVENT0_IMASK_DMADONE` writer - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_IMASK_DMADONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_DMADONE_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_DMADONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_dmadone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMADONE_A :: INT_EVENT0_IMASK_DMADONE_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_dmadone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_DMADONE_A :: INT_EVENT0_IMASK_DMADONE_SET) } } # [doc = "Field `INT_EVENT0_IMASK_UVIFG` reader - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
pub type INT_EVENT0_IMASK_UVIFG_R = crate :: BitReader < INT_EVENT0_IMASK_UVIFG_A > ; # [doc = "Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_UVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_UVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_UVIFG_SET = 1 , } impl From < INT_EVENT0_IMASK_UVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_UVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_UVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_UVIFG_A { match self . bits { false => INT_EVENT0_IMASK_UVIFG_A :: INT_EVENT0_IMASK_UVIFG_CLR , true => INT_EVENT0_IMASK_UVIFG_A :: INT_EVENT0_IMASK_UVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_uvifg_clr (& self) -> bool { * self == INT_EVENT0_IMASK_UVIFG_A :: INT_EVENT0_IMASK_UVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_uvifg_set (& self) -> bool { * self == INT_EVENT0_IMASK_UVIFG_A :: INT_EVENT0_IMASK_UVIFG_SET } } # [doc = "Field `INT_EVENT0_IMASK_UVIFG` writer - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
pub type INT_EVENT0_IMASK_UVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_UVIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_UVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_uvifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_UVIFG_A :: INT_EVENT0_IMASK_UVIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_uvifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_UVIFG_A :: INT_EVENT0_IMASK_UVIFG_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG0_R = crate :: BitReader < INT_EVENT0_IMASK_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT0_IMASK_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MEMRESIFG0_A { match self . bits { false => INT_EVENT0_IMASK_MEMRESIFG0_A :: INT_EVENT0_IMASK_MEMRESIFG0_CLR , true => INT_EVENT0_IMASK_MEMRESIFG0_A :: INT_EVENT0_IMASK_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg0_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG0_A :: INT_EVENT0_IMASK_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg0_set (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG0_A :: INT_EVENT0_IMASK_MEMRESIFG0_SET } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MEMRESIFG0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_memresifg0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG0_A :: INT_EVENT0_IMASK_MEMRESIFG0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_memresifg0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG0_A :: INT_EVENT0_IMASK_MEMRESIFG0_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG1` reader - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG1_R = crate :: BitReader < INT_EVENT0_IMASK_MEMRESIFG1_A > ; # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MEMRESIFG1_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MEMRESIFG1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT0_IMASK_MEMRESIFG1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MEMRESIFG1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MEMRESIFG1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MEMRESIFG1_A { match self . bits { false => INT_EVENT0_IMASK_MEMRESIFG1_A :: INT_EVENT0_IMASK_MEMRESIFG1_CLR , true => INT_EVENT0_IMASK_MEMRESIFG1_A :: INT_EVENT0_IMASK_MEMRESIFG1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg1_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG1_A :: INT_EVENT0_IMASK_MEMRESIFG1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg1_set (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG1_A :: INT_EVENT0_IMASK_MEMRESIFG1_SET } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG1` writer - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MEMRESIFG1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MEMRESIFG1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_memresifg1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG1_A :: INT_EVENT0_IMASK_MEMRESIFG1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_memresifg1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG1_A :: INT_EVENT0_IMASK_MEMRESIFG1_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG2` reader - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG2_R = crate :: BitReader < INT_EVENT0_IMASK_MEMRESIFG2_A > ; # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MEMRESIFG2_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MEMRESIFG2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT0_IMASK_MEMRESIFG2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MEMRESIFG2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MEMRESIFG2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MEMRESIFG2_A { match self . bits { false => INT_EVENT0_IMASK_MEMRESIFG2_A :: INT_EVENT0_IMASK_MEMRESIFG2_CLR , true => INT_EVENT0_IMASK_MEMRESIFG2_A :: INT_EVENT0_IMASK_MEMRESIFG2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg2_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG2_A :: INT_EVENT0_IMASK_MEMRESIFG2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg2_set (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG2_A :: INT_EVENT0_IMASK_MEMRESIFG2_SET } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG2` writer - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MEMRESIFG2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MEMRESIFG2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_memresifg2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG2_A :: INT_EVENT0_IMASK_MEMRESIFG2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_memresifg2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG2_A :: INT_EVENT0_IMASK_MEMRESIFG2_SET) } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG3` reader - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG3_R = crate :: BitReader < INT_EVENT0_IMASK_MEMRESIFG3_A > ; # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_IMASK_MEMRESIFG3_A { # [doc = "0: CLR"]
INT_EVENT0_IMASK_MEMRESIFG3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_IMASK_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT0_IMASK_MEMRESIFG3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_IMASK_MEMRESIFG3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_IMASK_MEMRESIFG3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_IMASK_MEMRESIFG3_A { match self . bits { false => INT_EVENT0_IMASK_MEMRESIFG3_A :: INT_EVENT0_IMASK_MEMRESIFG3_CLR , true => INT_EVENT0_IMASK_MEMRESIFG3_A :: INT_EVENT0_IMASK_MEMRESIFG3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg3_clr (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG3_A :: INT_EVENT0_IMASK_MEMRESIFG3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_imask_memresifg3_set (& self) -> bool { * self == INT_EVENT0_IMASK_MEMRESIFG3_A :: INT_EVENT0_IMASK_MEMRESIFG3_SET } } # [doc = "Field `INT_EVENT0_IMASK_MEMRESIFG3` writer - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_IMASK_MEMRESIFG3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_IMASK_MEMRESIFG3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT0_IMASK_MEMRESIFG3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_imask_memresifg3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG3_A :: INT_EVENT0_IMASK_MEMRESIFG3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_imask_memresifg3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_IMASK_MEMRESIFG3_A :: INT_EVENT0_IMASK_MEMRESIFG3_SET) } } impl R { # [doc = "Bit 0 - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_imask_ovifg (& self) -> INT_EVENT0_IMASK_OVIFG_R { INT_EVENT0_IMASK_OVIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_imask_tovifg (& self) -> INT_EVENT0_IMASK_TOVIFG_R { INT_EVENT0_IMASK_TOVIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_imask_highifg (& self) -> INT_EVENT0_IMASK_HIGHIFG_R { INT_EVENT0_IMASK_HIGHIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_imask_lowifg (& self) -> INT_EVENT0_IMASK_LOWIFG_R { INT_EVENT0_IMASK_LOWIFG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
pub fn int_event0_imask_inifg (& self) -> INT_EVENT0_IMASK_INIFG_R { INT_EVENT0_IMASK_INIFG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_imask_dmadone (& self) -> INT_EVENT0_IMASK_DMADONE_R { INT_EVENT0_IMASK_DMADONE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
# [inline (always)]
pub fn int_event0_imask_uvifg (& self) -> INT_EVENT0_IMASK_UVIFG_R { INT_EVENT0_IMASK_UVIFG_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_imask_memresifg0 (& self) -> INT_EVENT0_IMASK_MEMRESIFG0_R { INT_EVENT0_IMASK_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_imask_memresifg1 (& self) -> INT_EVENT0_IMASK_MEMRESIFG1_R { INT_EVENT0_IMASK_MEMRESIFG1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_imask_memresifg2 (& self) -> INT_EVENT0_IMASK_MEMRESIFG2_R { INT_EVENT0_IMASK_MEMRESIFG2_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_imask_memresifg3 (& self) -> INT_EVENT0_IMASK_MEMRESIFG3_R { INT_EVENT0_IMASK_MEMRESIFG3_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 0 - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_ovifg (& mut self) -> INT_EVENT0_IMASK_OVIFG_W < INT_EVENT0_IMASK_SPEC , 0 > { INT_EVENT0_IMASK_OVIFG_W :: new (self) } # [doc = "Bit 1 - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_tovifg (& mut self) -> INT_EVENT0_IMASK_TOVIFG_W < INT_EVENT0_IMASK_SPEC , 1 > { INT_EVENT0_IMASK_TOVIFG_W :: new (self) } # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_highifg (& mut self) -> INT_EVENT0_IMASK_HIGHIFG_W < INT_EVENT0_IMASK_SPEC , 2 > { INT_EVENT0_IMASK_HIGHIFG_W :: new (self) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_lowifg (& mut self) -> INT_EVENT0_IMASK_LOWIFG_W < INT_EVENT0_IMASK_SPEC , 3 > { INT_EVENT0_IMASK_LOWIFG_W :: new (self) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_inifg (& mut self) -> INT_EVENT0_IMASK_INIFG_W < INT_EVENT0_IMASK_SPEC , 4 > { INT_EVENT0_IMASK_INIFG_W :: new (self) } # [doc = "Bit 5 - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_dmadone (& mut self) -> INT_EVENT0_IMASK_DMADONE_W < INT_EVENT0_IMASK_SPEC , 5 > { INT_EVENT0_IMASK_DMADONE_W :: new (self) } # [doc = "Bit 6 - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_uvifg (& mut self) -> INT_EVENT0_IMASK_UVIFG_W < INT_EVENT0_IMASK_SPEC , 6 > { INT_EVENT0_IMASK_UVIFG_W :: new (self) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_memresifg0 (& mut self) -> INT_EVENT0_IMASK_MEMRESIFG0_W < INT_EVENT0_IMASK_SPEC , 8 > { INT_EVENT0_IMASK_MEMRESIFG0_W :: new (self) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_memresifg1 (& mut self) -> INT_EVENT0_IMASK_MEMRESIFG1_W < INT_EVENT0_IMASK_SPEC , 9 > { INT_EVENT0_IMASK_MEMRESIFG1_W :: new (self) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_memresifg2 (& mut self) -> INT_EVENT0_IMASK_MEMRESIFG2_W < INT_EVENT0_IMASK_SPEC , 10 > { INT_EVENT0_IMASK_MEMRESIFG2_W :: new (self) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_imask_memresifg3 (& mut self) -> INT_EVENT0_IMASK_MEMRESIFG3_W < INT_EVENT0_IMASK_SPEC , 11 > { INT_EVENT0_IMASK_MEMRESIFG3_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event0_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT0_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_ris`]
module"]
pub type INT_EVENT0_RIS = crate :: Reg < int_event0_ris :: INT_EVENT0_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event0_ris { # [doc = "Register `INT_EVENT0_RIS` reader"]
pub type R = crate :: R < INT_EVENT0_RIS_SPEC > ; # [doc = "Field `INT_EVENT0_RIS_OVIFG` reader - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_RIS_OVIFG_R = crate :: BitReader < INT_EVENT0_RIS_OVIFG_A > ; # [doc = "Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_OVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_OVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_OVIFG_SET = 1 , } impl From < INT_EVENT0_RIS_OVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_OVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_OVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_OVIFG_A { match self . bits { false => INT_EVENT0_RIS_OVIFG_A :: INT_EVENT0_RIS_OVIFG_CLR , true => INT_EVENT0_RIS_OVIFG_A :: INT_EVENT0_RIS_OVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_ovifg_clr (& self) -> bool { * self == INT_EVENT0_RIS_OVIFG_A :: INT_EVENT0_RIS_OVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_ovifg_set (& self) -> bool { * self == INT_EVENT0_RIS_OVIFG_A :: INT_EVENT0_RIS_OVIFG_SET } } # [doc = "Field `INT_EVENT0_RIS_TOVIFG` reader - Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_RIS_TOVIFG_R = crate :: BitReader < INT_EVENT0_RIS_TOVIFG_A > ; # [doc = "Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_TOVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_TOVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_TOVIFG_SET = 1 , } impl From < INT_EVENT0_RIS_TOVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_TOVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_TOVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_TOVIFG_A { match self . bits { false => INT_EVENT0_RIS_TOVIFG_A :: INT_EVENT0_RIS_TOVIFG_CLR , true => INT_EVENT0_RIS_TOVIFG_A :: INT_EVENT0_RIS_TOVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_tovifg_clr (& self) -> bool { * self == INT_EVENT0_RIS_TOVIFG_A :: INT_EVENT0_RIS_TOVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_tovifg_set (& self) -> bool { * self == INT_EVENT0_RIS_TOVIFG_A :: INT_EVENT0_RIS_TOVIFG_SET } } # [doc = "Field `INT_EVENT0_RIS_HIGHIFG` reader - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_RIS_HIGHIFG_R = crate :: BitReader < INT_EVENT0_RIS_HIGHIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_HIGHIFG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_HIGHIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_HIGHIFG_SET = 1 , } impl From < INT_EVENT0_RIS_HIGHIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_HIGHIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_HIGHIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_HIGHIFG_A { match self . bits { false => INT_EVENT0_RIS_HIGHIFG_A :: INT_EVENT0_RIS_HIGHIFG_CLR , true => INT_EVENT0_RIS_HIGHIFG_A :: INT_EVENT0_RIS_HIGHIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_highifg_clr (& self) -> bool { * self == INT_EVENT0_RIS_HIGHIFG_A :: INT_EVENT0_RIS_HIGHIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_highifg_set (& self) -> bool { * self == INT_EVENT0_RIS_HIGHIFG_A :: INT_EVENT0_RIS_HIGHIFG_SET } } # [doc = "Field `INT_EVENT0_RIS_LOWIFG` reader - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_RIS_LOWIFG_R = crate :: BitReader < INT_EVENT0_RIS_LOWIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_LOWIFG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_LOWIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_LOWIFG_SET = 1 , } impl From < INT_EVENT0_RIS_LOWIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_LOWIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_LOWIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_LOWIFG_A { match self . bits { false => INT_EVENT0_RIS_LOWIFG_A :: INT_EVENT0_RIS_LOWIFG_CLR , true => INT_EVENT0_RIS_LOWIFG_A :: INT_EVENT0_RIS_LOWIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_lowifg_clr (& self) -> bool { * self == INT_EVENT0_RIS_LOWIFG_A :: INT_EVENT0_RIS_LOWIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_lowifg_set (& self) -> bool { * self == INT_EVENT0_RIS_LOWIFG_A :: INT_EVENT0_RIS_LOWIFG_SET } } # [doc = "Field `INT_EVENT0_RIS_INIFG` reader - Mask INIFG in MIS_EX register."]
pub type INT_EVENT0_RIS_INIFG_R = crate :: BitReader < INT_EVENT0_RIS_INIFG_A > ; # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_INIFG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_INIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_INIFG_SET = 1 , } impl From < INT_EVENT0_RIS_INIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_INIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_INIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_INIFG_A { match self . bits { false => INT_EVENT0_RIS_INIFG_A :: INT_EVENT0_RIS_INIFG_CLR , true => INT_EVENT0_RIS_INIFG_A :: INT_EVENT0_RIS_INIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_inifg_clr (& self) -> bool { * self == INT_EVENT0_RIS_INIFG_A :: INT_EVENT0_RIS_INIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_inifg_set (& self) -> bool { * self == INT_EVENT0_RIS_INIFG_A :: INT_EVENT0_RIS_INIFG_SET } } # [doc = "Field `INT_EVENT0_RIS_DMADONE` reader - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_RIS_DMADONE_R = crate :: BitReader < INT_EVENT0_RIS_DMADONE_A > ; # [doc = "Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_DMADONE_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_DMADONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_DMADONE_SET = 1 , } impl From < INT_EVENT0_RIS_DMADONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_DMADONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_DMADONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_DMADONE_A { match self . bits { false => INT_EVENT0_RIS_DMADONE_A :: INT_EVENT0_RIS_DMADONE_CLR , true => INT_EVENT0_RIS_DMADONE_A :: INT_EVENT0_RIS_DMADONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_dmadone_clr (& self) -> bool { * self == INT_EVENT0_RIS_DMADONE_A :: INT_EVENT0_RIS_DMADONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_dmadone_set (& self) -> bool { * self == INT_EVENT0_RIS_DMADONE_A :: INT_EVENT0_RIS_DMADONE_SET } } # [doc = "Field `INT_EVENT0_RIS_UVIFG` reader - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
pub type INT_EVENT0_RIS_UVIFG_R = crate :: BitReader < INT_EVENT0_RIS_UVIFG_A > ; # [doc = "Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_UVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_UVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_UVIFG_SET = 1 , } impl From < INT_EVENT0_RIS_UVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_UVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_UVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_UVIFG_A { match self . bits { false => INT_EVENT0_RIS_UVIFG_A :: INT_EVENT0_RIS_UVIFG_CLR , true => INT_EVENT0_RIS_UVIFG_A :: INT_EVENT0_RIS_UVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_uvifg_clr (& self) -> bool { * self == INT_EVENT0_RIS_UVIFG_A :: INT_EVENT0_RIS_UVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_uvifg_set (& self) -> bool { * self == INT_EVENT0_RIS_UVIFG_A :: INT_EVENT0_RIS_UVIFG_SET } } # [doc = "Field `INT_EVENT0_RIS_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_RIS_MEMRESIFG0_R = crate :: BitReader < INT_EVENT0_RIS_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT0_RIS_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MEMRESIFG0_A { match self . bits { false => INT_EVENT0_RIS_MEMRESIFG0_A :: INT_EVENT0_RIS_MEMRESIFG0_CLR , true => INT_EVENT0_RIS_MEMRESIFG0_A :: INT_EVENT0_RIS_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg0_clr (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG0_A :: INT_EVENT0_RIS_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg0_set (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG0_A :: INT_EVENT0_RIS_MEMRESIFG0_SET } } # [doc = "Field `INT_EVENT0_RIS_MEMRESIFG1` reader - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_RIS_MEMRESIFG1_R = crate :: BitReader < INT_EVENT0_RIS_MEMRESIFG1_A > ; # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MEMRESIFG1_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MEMRESIFG1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT0_RIS_MEMRESIFG1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MEMRESIFG1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MEMRESIFG1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MEMRESIFG1_A { match self . bits { false => INT_EVENT0_RIS_MEMRESIFG1_A :: INT_EVENT0_RIS_MEMRESIFG1_CLR , true => INT_EVENT0_RIS_MEMRESIFG1_A :: INT_EVENT0_RIS_MEMRESIFG1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg1_clr (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG1_A :: INT_EVENT0_RIS_MEMRESIFG1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg1_set (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG1_A :: INT_EVENT0_RIS_MEMRESIFG1_SET } } # [doc = "Field `INT_EVENT0_RIS_MEMRESIFG2` reader - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_RIS_MEMRESIFG2_R = crate :: BitReader < INT_EVENT0_RIS_MEMRESIFG2_A > ; # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MEMRESIFG2_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MEMRESIFG2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT0_RIS_MEMRESIFG2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MEMRESIFG2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MEMRESIFG2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MEMRESIFG2_A { match self . bits { false => INT_EVENT0_RIS_MEMRESIFG2_A :: INT_EVENT0_RIS_MEMRESIFG2_CLR , true => INT_EVENT0_RIS_MEMRESIFG2_A :: INT_EVENT0_RIS_MEMRESIFG2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg2_clr (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG2_A :: INT_EVENT0_RIS_MEMRESIFG2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg2_set (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG2_A :: INT_EVENT0_RIS_MEMRESIFG2_SET } } # [doc = "Field `INT_EVENT0_RIS_MEMRESIFG3` reader - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_RIS_MEMRESIFG3_R = crate :: BitReader < INT_EVENT0_RIS_MEMRESIFG3_A > ; # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_RIS_MEMRESIFG3_A { # [doc = "0: CLR"]
INT_EVENT0_RIS_MEMRESIFG3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_RIS_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT0_RIS_MEMRESIFG3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_RIS_MEMRESIFG3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_RIS_MEMRESIFG3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_RIS_MEMRESIFG3_A { match self . bits { false => INT_EVENT0_RIS_MEMRESIFG3_A :: INT_EVENT0_RIS_MEMRESIFG3_CLR , true => INT_EVENT0_RIS_MEMRESIFG3_A :: INT_EVENT0_RIS_MEMRESIFG3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg3_clr (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG3_A :: INT_EVENT0_RIS_MEMRESIFG3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_ris_memresifg3_set (& self) -> bool { * self == INT_EVENT0_RIS_MEMRESIFG3_A :: INT_EVENT0_RIS_MEMRESIFG3_SET } } impl R { # [doc = "Bit 0 - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_ris_ovifg (& self) -> INT_EVENT0_RIS_OVIFG_R { INT_EVENT0_RIS_OVIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Raw interrupt flag for sequence conversion trigger overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_ris_tovifg (& self) -> INT_EVENT0_RIS_TOVIFG_R { INT_EVENT0_RIS_TOVIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_ris_highifg (& self) -> INT_EVENT0_RIS_HIGHIFG_R { INT_EVENT0_RIS_HIGHIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_ris_lowifg (& self) -> INT_EVENT0_RIS_LOWIFG_R { INT_EVENT0_RIS_LOWIFG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
pub fn int_event0_ris_inifg (& self) -> INT_EVENT0_RIS_INIFG_R { INT_EVENT0_RIS_INIFG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_ris_dmadone (& self) -> INT_EVENT0_RIS_DMADONE_R { INT_EVENT0_RIS_DMADONE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
# [inline (always)]
pub fn int_event0_ris_uvifg (& self) -> INT_EVENT0_RIS_UVIFG_R { INT_EVENT0_RIS_UVIFG_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_ris_memresifg0 (& self) -> INT_EVENT0_RIS_MEMRESIFG0_R { INT_EVENT0_RIS_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_ris_memresifg1 (& self) -> INT_EVENT0_RIS_MEMRESIFG1_R { INT_EVENT0_RIS_MEMRESIFG1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_ris_memresifg2 (& self) -> INT_EVENT0_RIS_MEMRESIFG2_R { INT_EVENT0_RIS_MEMRESIFG2_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_ris_memresifg3 (& self) -> INT_EVENT0_RIS_MEMRESIFG3_R { INT_EVENT0_RIS_MEMRESIFG3_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_RIS to value 0"]
impl crate :: Resettable for INT_EVENT0_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_mis`]
module"]
pub type INT_EVENT0_MIS = crate :: Reg < int_event0_mis :: INT_EVENT0_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event0_mis { # [doc = "Register `INT_EVENT0_MIS` reader"]
pub type R = crate :: R < INT_EVENT0_MIS_SPEC > ; # [doc = "Field `INT_EVENT0_MIS_OVIFG` reader - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_MIS_OVIFG_R = crate :: BitReader < INT_EVENT0_MIS_OVIFG_A > ; # [doc = "Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_OVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_OVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_OVIFG_SET = 1 , } impl From < INT_EVENT0_MIS_OVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_OVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_OVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_OVIFG_A { match self . bits { false => INT_EVENT0_MIS_OVIFG_A :: INT_EVENT0_MIS_OVIFG_CLR , true => INT_EVENT0_MIS_OVIFG_A :: INT_EVENT0_MIS_OVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_ovifg_clr (& self) -> bool { * self == INT_EVENT0_MIS_OVIFG_A :: INT_EVENT0_MIS_OVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_ovifg_set (& self) -> bool { * self == INT_EVENT0_MIS_OVIFG_A :: INT_EVENT0_MIS_OVIFG_SET } } # [doc = "Field `INT_EVENT0_MIS_TOVIFG` reader - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_MIS_TOVIFG_R = crate :: BitReader < INT_EVENT0_MIS_TOVIFG_A > ; # [doc = "Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_TOVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_TOVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_TOVIFG_SET = 1 , } impl From < INT_EVENT0_MIS_TOVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_TOVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_TOVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_TOVIFG_A { match self . bits { false => INT_EVENT0_MIS_TOVIFG_A :: INT_EVENT0_MIS_TOVIFG_CLR , true => INT_EVENT0_MIS_TOVIFG_A :: INT_EVENT0_MIS_TOVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_tovifg_clr (& self) -> bool { * self == INT_EVENT0_MIS_TOVIFG_A :: INT_EVENT0_MIS_TOVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_tovifg_set (& self) -> bool { * self == INT_EVENT0_MIS_TOVIFG_A :: INT_EVENT0_MIS_TOVIFG_SET } } # [doc = "Field `INT_EVENT0_MIS_HIGHIFG` reader - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_MIS_HIGHIFG_R = crate :: BitReader < INT_EVENT0_MIS_HIGHIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_HIGHIFG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_HIGHIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_HIGHIFG_SET = 1 , } impl From < INT_EVENT0_MIS_HIGHIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_HIGHIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_HIGHIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_HIGHIFG_A { match self . bits { false => INT_EVENT0_MIS_HIGHIFG_A :: INT_EVENT0_MIS_HIGHIFG_CLR , true => INT_EVENT0_MIS_HIGHIFG_A :: INT_EVENT0_MIS_HIGHIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_highifg_clr (& self) -> bool { * self == INT_EVENT0_MIS_HIGHIFG_A :: INT_EVENT0_MIS_HIGHIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_highifg_set (& self) -> bool { * self == INT_EVENT0_MIS_HIGHIFG_A :: INT_EVENT0_MIS_HIGHIFG_SET } } # [doc = "Field `INT_EVENT0_MIS_LOWIFG` reader - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_MIS_LOWIFG_R = crate :: BitReader < INT_EVENT0_MIS_LOWIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_LOWIFG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_LOWIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_LOWIFG_SET = 1 , } impl From < INT_EVENT0_MIS_LOWIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_LOWIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_LOWIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_LOWIFG_A { match self . bits { false => INT_EVENT0_MIS_LOWIFG_A :: INT_EVENT0_MIS_LOWIFG_CLR , true => INT_EVENT0_MIS_LOWIFG_A :: INT_EVENT0_MIS_LOWIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_lowifg_clr (& self) -> bool { * self == INT_EVENT0_MIS_LOWIFG_A :: INT_EVENT0_MIS_LOWIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_lowifg_set (& self) -> bool { * self == INT_EVENT0_MIS_LOWIFG_A :: INT_EVENT0_MIS_LOWIFG_SET } } # [doc = "Field `INT_EVENT0_MIS_INIFG` reader - Mask INIFG in MIS_EX register."]
pub type INT_EVENT0_MIS_INIFG_R = crate :: BitReader < INT_EVENT0_MIS_INIFG_A > ; # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_INIFG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_INIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_INIFG_SET = 1 , } impl From < INT_EVENT0_MIS_INIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_INIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_INIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_INIFG_A { match self . bits { false => INT_EVENT0_MIS_INIFG_A :: INT_EVENT0_MIS_INIFG_CLR , true => INT_EVENT0_MIS_INIFG_A :: INT_EVENT0_MIS_INIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_inifg_clr (& self) -> bool { * self == INT_EVENT0_MIS_INIFG_A :: INT_EVENT0_MIS_INIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_inifg_set (& self) -> bool { * self == INT_EVENT0_MIS_INIFG_A :: INT_EVENT0_MIS_INIFG_SET } } # [doc = "Field `INT_EVENT0_MIS_DMADONE` reader - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_MIS_DMADONE_R = crate :: BitReader < INT_EVENT0_MIS_DMADONE_A > ; # [doc = "Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_DMADONE_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_DMADONE_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_DMADONE_SET = 1 , } impl From < INT_EVENT0_MIS_DMADONE_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_DMADONE_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_DMADONE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_DMADONE_A { match self . bits { false => INT_EVENT0_MIS_DMADONE_A :: INT_EVENT0_MIS_DMADONE_CLR , true => INT_EVENT0_MIS_DMADONE_A :: INT_EVENT0_MIS_DMADONE_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_dmadone_clr (& self) -> bool { * self == INT_EVENT0_MIS_DMADONE_A :: INT_EVENT0_MIS_DMADONE_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_dmadone_set (& self) -> bool { * self == INT_EVENT0_MIS_DMADONE_A :: INT_EVENT0_MIS_DMADONE_SET } } # [doc = "Field `INT_EVENT0_MIS_UVIFG` reader - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
pub type INT_EVENT0_MIS_UVIFG_R = crate :: BitReader < INT_EVENT0_MIS_UVIFG_A > ; # [doc = "Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_UVIFG_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_UVIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_UVIFG_SET = 1 , } impl From < INT_EVENT0_MIS_UVIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_UVIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_UVIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_UVIFG_A { match self . bits { false => INT_EVENT0_MIS_UVIFG_A :: INT_EVENT0_MIS_UVIFG_CLR , true => INT_EVENT0_MIS_UVIFG_A :: INT_EVENT0_MIS_UVIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_uvifg_clr (& self) -> bool { * self == INT_EVENT0_MIS_UVIFG_A :: INT_EVENT0_MIS_UVIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_uvifg_set (& self) -> bool { * self == INT_EVENT0_MIS_UVIFG_A :: INT_EVENT0_MIS_UVIFG_SET } } # [doc = "Field `INT_EVENT0_MIS_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_MIS_MEMRESIFG0_R = crate :: BitReader < INT_EVENT0_MIS_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT0_MIS_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MEMRESIFG0_A { match self . bits { false => INT_EVENT0_MIS_MEMRESIFG0_A :: INT_EVENT0_MIS_MEMRESIFG0_CLR , true => INT_EVENT0_MIS_MEMRESIFG0_A :: INT_EVENT0_MIS_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg0_clr (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG0_A :: INT_EVENT0_MIS_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg0_set (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG0_A :: INT_EVENT0_MIS_MEMRESIFG0_SET } } # [doc = "Field `INT_EVENT0_MIS_MEMRESIFG1` reader - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_MIS_MEMRESIFG1_R = crate :: BitReader < INT_EVENT0_MIS_MEMRESIFG1_A > ; # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MEMRESIFG1_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MEMRESIFG1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT0_MIS_MEMRESIFG1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MEMRESIFG1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MEMRESIFG1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MEMRESIFG1_A { match self . bits { false => INT_EVENT0_MIS_MEMRESIFG1_A :: INT_EVENT0_MIS_MEMRESIFG1_CLR , true => INT_EVENT0_MIS_MEMRESIFG1_A :: INT_EVENT0_MIS_MEMRESIFG1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg1_clr (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG1_A :: INT_EVENT0_MIS_MEMRESIFG1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg1_set (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG1_A :: INT_EVENT0_MIS_MEMRESIFG1_SET } } # [doc = "Field `INT_EVENT0_MIS_MEMRESIFG2` reader - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_MIS_MEMRESIFG2_R = crate :: BitReader < INT_EVENT0_MIS_MEMRESIFG2_A > ; # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MEMRESIFG2_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MEMRESIFG2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT0_MIS_MEMRESIFG2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MEMRESIFG2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MEMRESIFG2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MEMRESIFG2_A { match self . bits { false => INT_EVENT0_MIS_MEMRESIFG2_A :: INT_EVENT0_MIS_MEMRESIFG2_CLR , true => INT_EVENT0_MIS_MEMRESIFG2_A :: INT_EVENT0_MIS_MEMRESIFG2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg2_clr (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG2_A :: INT_EVENT0_MIS_MEMRESIFG2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg2_set (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG2_A :: INT_EVENT0_MIS_MEMRESIFG2_SET } } # [doc = "Field `INT_EVENT0_MIS_MEMRESIFG3` reader - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_MIS_MEMRESIFG3_R = crate :: BitReader < INT_EVENT0_MIS_MEMRESIFG3_A > ; # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_MIS_MEMRESIFG3_A { # [doc = "0: CLR"]
INT_EVENT0_MIS_MEMRESIFG3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT0_MIS_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT0_MIS_MEMRESIFG3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_MIS_MEMRESIFG3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT0_MIS_MEMRESIFG3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT0_MIS_MEMRESIFG3_A { match self . bits { false => INT_EVENT0_MIS_MEMRESIFG3_A :: INT_EVENT0_MIS_MEMRESIFG3_CLR , true => INT_EVENT0_MIS_MEMRESIFG3_A :: INT_EVENT0_MIS_MEMRESIFG3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg3_clr (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG3_A :: INT_EVENT0_MIS_MEMRESIFG3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event0_mis_memresifg3_set (& self) -> bool { * self == INT_EVENT0_MIS_MEMRESIFG3_A :: INT_EVENT0_MIS_MEMRESIFG3_SET } } impl R { # [doc = "Bit 0 - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_mis_ovifg (& self) -> INT_EVENT0_MIS_OVIFG_R { INT_EVENT0_MIS_OVIFG_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_mis_tovifg (& self) -> INT_EVENT0_MIS_TOVIFG_R { INT_EVENT0_MIS_TOVIFG_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_mis_highifg (& self) -> INT_EVENT0_MIS_HIGHIFG_R { INT_EVENT0_MIS_HIGHIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_mis_lowifg (& self) -> INT_EVENT0_MIS_LOWIFG_R { INT_EVENT0_MIS_LOWIFG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
pub fn int_event0_mis_inifg (& self) -> INT_EVENT0_MIS_INIFG_R { INT_EVENT0_MIS_INIFG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event0_mis_dmadone (& self) -> INT_EVENT0_MIS_DMADONE_R { INT_EVENT0_MIS_DMADONE_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 6 - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR is set to 1."]
# [inline (always)]
pub fn int_event0_mis_uvifg (& self) -> INT_EVENT0_MIS_UVIFG_R { INT_EVENT0_MIS_UVIFG_R :: new (((self . bits >> 6) & 1) != 0) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_mis_memresifg0 (& self) -> INT_EVENT0_MIS_MEMRESIFG0_R { INT_EVENT0_MIS_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_mis_memresifg1 (& self) -> INT_EVENT0_MIS_MEMRESIFG1_R { INT_EVENT0_MIS_MEMRESIFG1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_mis_memresifg2 (& self) -> INT_EVENT0_MIS_MEMRESIFG2_R { INT_EVENT0_MIS_MEMRESIFG2_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event0_mis_memresifg3 (& self) -> INT_EVENT0_MIS_MEMRESIFG3_R { INT_EVENT0_MIS_MEMRESIFG3_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event0_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event0_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT0_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT0_MIS to value 0"]
impl crate :: Resettable for INT_EVENT0_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iset`]
module"]
pub type INT_EVENT0_ISET = crate :: Reg < int_event0_iset :: INT_EVENT0_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event0_iset { # [doc = "Register `INT_EVENT0_ISET` writer"]
pub type W = crate :: W < INT_EVENT0_ISET_SPEC > ; # [doc = "Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_OVIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_OVIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_OVIFG_SET = 1 , } impl From < INT_EVENT0_ISET_OVIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_OVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_OVIFG` writer - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ISET_OVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_OVIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_OVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_ovifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVIFG_AW :: INT_EVENT0_ISET_OVIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_ovifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_OVIFG_AW :: INT_EVENT0_ISET_OVIFG_SET) } } # [doc = "Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_TOVIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_TOVIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_TOVIFG_SET = 1 , } impl From < INT_EVENT0_ISET_TOVIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_TOVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_TOVIFG` writer - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ISET_TOVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_TOVIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_TOVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_tovifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TOVIFG_AW :: INT_EVENT0_ISET_TOVIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_tovifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_TOVIFG_AW :: INT_EVENT0_ISET_TOVIFG_SET) } } # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_HIGHIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_HIGHIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_HIGHIFG_SET = 1 , } impl From < INT_EVENT0_ISET_HIGHIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_HIGHIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_HIGHIFG` writer - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ISET_HIGHIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_HIGHIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_HIGHIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_highifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_HIGHIFG_AW :: INT_EVENT0_ISET_HIGHIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_highifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_HIGHIFG_AW :: INT_EVENT0_ISET_HIGHIFG_SET) } } # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_LOWIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_LOWIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_LOWIFG_SET = 1 , } impl From < INT_EVENT0_ISET_LOWIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_LOWIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_LOWIFG` writer - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ISET_LOWIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_LOWIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_LOWIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_lowifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LOWIFG_AW :: INT_EVENT0_ISET_LOWIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_lowifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_LOWIFG_AW :: INT_EVENT0_ISET_LOWIFG_SET) } } # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_INIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_INIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_INIFG_SET = 1 , } impl From < INT_EVENT0_ISET_INIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_INIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_INIFG` writer - Mask INIFG in MIS_EX register."]
pub type INT_EVENT0_ISET_INIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_INIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_INIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_inifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INIFG_AW :: INT_EVENT0_ISET_INIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_inifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_INIFG_AW :: INT_EVENT0_ISET_INIFG_SET) } } # [doc = "Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_DMADONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_DMADONE_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_DMADONE_SET = 1 , } impl From < INT_EVENT0_ISET_DMADONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_DMADONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_DMADONE` writer - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ISET_DMADONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_DMADONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_DMADONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_dmadone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMADONE_AW :: INT_EVENT0_ISET_DMADONE_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_dmadone_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_DMADONE_AW :: INT_EVENT0_ISET_DMADONE_SET) } } # [doc = "Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_UVIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_UVIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_UVIFG_SET = 1 , } impl From < INT_EVENT0_ISET_UVIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_UVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_UVIFG` writer - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ISET_UVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_UVIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_UVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_uvifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_UVIFG_AW :: INT_EVENT0_ISET_UVIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_uvifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_UVIFG_AW :: INT_EVENT0_ISET_UVIFG_SET) } } # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MEMRESIFG0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MEMRESIFG0_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT0_ISET_MEMRESIFG0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MEMRESIFG0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ISET_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MEMRESIFG0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_memresifg0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG0_AW :: INT_EVENT0_ISET_MEMRESIFG0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_memresifg0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG0_AW :: INT_EVENT0_ISET_MEMRESIFG0_SET) } } # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MEMRESIFG1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MEMRESIFG1_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT0_ISET_MEMRESIFG1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MEMRESIFG1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MEMRESIFG1` writer - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ISET_MEMRESIFG1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MEMRESIFG1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MEMRESIFG1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_memresifg1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG1_AW :: INT_EVENT0_ISET_MEMRESIFG1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_memresifg1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG1_AW :: INT_EVENT0_ISET_MEMRESIFG1_SET) } } # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MEMRESIFG2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MEMRESIFG2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT0_ISET_MEMRESIFG2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MEMRESIFG2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MEMRESIFG2` writer - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ISET_MEMRESIFG2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MEMRESIFG2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MEMRESIFG2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_memresifg2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG2_AW :: INT_EVENT0_ISET_MEMRESIFG2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_memresifg2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG2_AW :: INT_EVENT0_ISET_MEMRESIFG2_SET) } } # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ISET_MEMRESIFG3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ISET_MEMRESIFG3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT0_ISET_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT0_ISET_MEMRESIFG3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ISET_MEMRESIFG3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ISET_MEMRESIFG3` writer - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ISET_MEMRESIFG3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ISET_MEMRESIFG3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ISET_MEMRESIFG3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iset_memresifg3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG3_AW :: INT_EVENT0_ISET_MEMRESIFG3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event0_iset_memresifg3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ISET_MEMRESIFG3_AW :: INT_EVENT0_ISET_MEMRESIFG3_SET) } } impl W { # [doc = "Bit 0 - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_ovifg (& mut self) -> INT_EVENT0_ISET_OVIFG_W < INT_EVENT0_ISET_SPEC , 0 > { INT_EVENT0_ISET_OVIFG_W :: new (self) } # [doc = "Bit 1 - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_tovifg (& mut self) -> INT_EVENT0_ISET_TOVIFG_W < INT_EVENT0_ISET_SPEC , 1 > { INT_EVENT0_ISET_TOVIFG_W :: new (self) } # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_highifg (& mut self) -> INT_EVENT0_ISET_HIGHIFG_W < INT_EVENT0_ISET_SPEC , 2 > { INT_EVENT0_ISET_HIGHIFG_W :: new (self) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_lowifg (& mut self) -> INT_EVENT0_ISET_LOWIFG_W < INT_EVENT0_ISET_SPEC , 3 > { INT_EVENT0_ISET_LOWIFG_W :: new (self) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_inifg (& mut self) -> INT_EVENT0_ISET_INIFG_W < INT_EVENT0_ISET_SPEC , 4 > { INT_EVENT0_ISET_INIFG_W :: new (self) } # [doc = "Bit 5 - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_dmadone (& mut self) -> INT_EVENT0_ISET_DMADONE_W < INT_EVENT0_ISET_SPEC , 5 > { INT_EVENT0_ISET_DMADONE_W :: new (self) } # [doc = "Bit 6 - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_uvifg (& mut self) -> INT_EVENT0_ISET_UVIFG_W < INT_EVENT0_ISET_SPEC , 6 > { INT_EVENT0_ISET_UVIFG_W :: new (self) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_memresifg0 (& mut self) -> INT_EVENT0_ISET_MEMRESIFG0_W < INT_EVENT0_ISET_SPEC , 8 > { INT_EVENT0_ISET_MEMRESIFG0_W :: new (self) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_memresifg1 (& mut self) -> INT_EVENT0_ISET_MEMRESIFG1_W < INT_EVENT0_ISET_SPEC , 9 > { INT_EVENT0_ISET_MEMRESIFG1_W :: new (self) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_memresifg2 (& mut self) -> INT_EVENT0_ISET_MEMRESIFG2_W < INT_EVENT0_ISET_SPEC , 10 > { INT_EVENT0_ISET_MEMRESIFG2_W :: new (self) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iset_memresifg3 (& mut self) -> INT_EVENT0_ISET_MEMRESIFG3_W < INT_EVENT0_ISET_SPEC , 11 > { INT_EVENT0_ISET_MEMRESIFG3_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ISET to value 0"]
impl crate :: Resettable for INT_EVENT0_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT0_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event0_iclr`]
module"]
pub type INT_EVENT0_ICLR = crate :: Reg < int_event0_iclr :: INT_EVENT0_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event0_iclr { # [doc = "Register `INT_EVENT0_ICLR` writer"]
pub type W = crate :: W < INT_EVENT0_ICLR_SPEC > ; # [doc = "Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_OVIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_OVIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_OVIFG_CLR = 1 , } impl From < INT_EVENT0_ICLR_OVIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_OVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_OVIFG` writer - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ICLR_OVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_OVIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_OVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_ovifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVIFG_AW :: INT_EVENT0_ICLR_OVIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_ovifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_OVIFG_AW :: INT_EVENT0_ICLR_OVIFG_CLR) } } # [doc = "Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_TOVIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_TOVIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_TOVIFG_CLR = 1 , } impl From < INT_EVENT0_ICLR_TOVIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_TOVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_TOVIFG` writer - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ICLR_TOVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_TOVIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_TOVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_tovifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TOVIFG_AW :: INT_EVENT0_ICLR_TOVIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_tovifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_TOVIFG_AW :: INT_EVENT0_ICLR_TOVIFG_CLR) } } # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_HIGHIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_HIGHIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_HIGHIFG_CLR = 1 , } impl From < INT_EVENT0_ICLR_HIGHIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_HIGHIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_HIGHIFG` writer - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ICLR_HIGHIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_HIGHIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_HIGHIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_highifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_HIGHIFG_AW :: INT_EVENT0_ICLR_HIGHIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_highifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_HIGHIFG_AW :: INT_EVENT0_ICLR_HIGHIFG_CLR) } } # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_LOWIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_LOWIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_LOWIFG_CLR = 1 , } impl From < INT_EVENT0_ICLR_LOWIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_LOWIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_LOWIFG` writer - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ICLR_LOWIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_LOWIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_LOWIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_lowifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LOWIFG_AW :: INT_EVENT0_ICLR_LOWIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_lowifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_LOWIFG_AW :: INT_EVENT0_ICLR_LOWIFG_CLR) } } # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_INIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_INIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_INIFG_CLR = 1 , } impl From < INT_EVENT0_ICLR_INIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_INIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_INIFG` writer - Mask INIFG in MIS_EX register."]
pub type INT_EVENT0_ICLR_INIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_INIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_INIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_inifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_INIFG_AW :: INT_EVENT0_ICLR_INIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_inifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_INIFG_AW :: INT_EVENT0_ICLR_INIFG_CLR) } } # [doc = "Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_DMADONE_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_DMADONE_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_DMADONE_CLR = 1 , } impl From < INT_EVENT0_ICLR_DMADONE_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_DMADONE_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_DMADONE` writer - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ICLR_DMADONE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_DMADONE_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_DMADONE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_dmadone_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMADONE_AW :: INT_EVENT0_ICLR_DMADONE_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_dmadone_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_DMADONE_AW :: INT_EVENT0_ICLR_DMADONE_CLR) } } # [doc = "Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_UVIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_UVIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_UVIFG_CLR = 1 , } impl From < INT_EVENT0_ICLR_UVIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_UVIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_UVIFG` writer - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT0_ICLR_UVIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_UVIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_UVIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_uvifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_UVIFG_AW :: INT_EVENT0_ICLR_UVIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_uvifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_UVIFG_AW :: INT_EVENT0_ICLR_UVIFG_CLR) } } # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MEMRESIFG0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MEMRESIFG0_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MEMRESIFG0_CLR = 1 , } impl From < INT_EVENT0_ICLR_MEMRESIFG0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MEMRESIFG0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ICLR_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MEMRESIFG0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_memresifg0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG0_AW :: INT_EVENT0_ICLR_MEMRESIFG0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_memresifg0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG0_AW :: INT_EVENT0_ICLR_MEMRESIFG0_CLR) } } # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MEMRESIFG1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MEMRESIFG1_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MEMRESIFG1_CLR = 1 , } impl From < INT_EVENT0_ICLR_MEMRESIFG1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MEMRESIFG1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MEMRESIFG1` writer - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ICLR_MEMRESIFG1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MEMRESIFG1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MEMRESIFG1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_memresifg1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG1_AW :: INT_EVENT0_ICLR_MEMRESIFG1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_memresifg1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG1_AW :: INT_EVENT0_ICLR_MEMRESIFG1_CLR) } } # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MEMRESIFG2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MEMRESIFG2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MEMRESIFG2_CLR = 1 , } impl From < INT_EVENT0_ICLR_MEMRESIFG2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MEMRESIFG2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MEMRESIFG2` writer - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ICLR_MEMRESIFG2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MEMRESIFG2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MEMRESIFG2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_memresifg2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG2_AW :: INT_EVENT0_ICLR_MEMRESIFG2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_memresifg2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG2_AW :: INT_EVENT0_ICLR_MEMRESIFG2_CLR) } } # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT0_ICLR_MEMRESIFG3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT0_ICLR_MEMRESIFG3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT0_ICLR_MEMRESIFG3_CLR = 1 , } impl From < INT_EVENT0_ICLR_MEMRESIFG3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT0_ICLR_MEMRESIFG3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT0_ICLR_MEMRESIFG3` writer - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT0_ICLR_MEMRESIFG3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT0_ICLR_MEMRESIFG3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT0_ICLR_MEMRESIFG3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event0_iclr_memresifg3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG3_AW :: INT_EVENT0_ICLR_MEMRESIFG3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event0_iclr_memresifg3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT0_ICLR_MEMRESIFG3_AW :: INT_EVENT0_ICLR_MEMRESIFG3_CLR) } } impl W { # [doc = "Bit 0 - Raw interrupt flag for MEMRESx overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_ovifg (& mut self) -> INT_EVENT0_ICLR_OVIFG_W < INT_EVENT0_ICLR_SPEC , 0 > { INT_EVENT0_ICLR_OVIFG_W :: new (self) } # [doc = "Bit 1 - Raw interrupt flag for sequence conversion timeout overflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_tovifg (& mut self) -> INT_EVENT0_ICLR_TOVIFG_W < INT_EVENT0_ICLR_SPEC , 1 > { INT_EVENT0_ICLR_TOVIFG_W :: new (self) } # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_highifg (& mut self) -> INT_EVENT0_ICLR_HIGHIFG_W < INT_EVENT0_ICLR_SPEC , 2 > { INT_EVENT0_ICLR_HIGHIFG_W :: new (self) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_lowifg (& mut self) -> INT_EVENT0_ICLR_LOWIFG_W < INT_EVENT0_ICLR_SPEC , 3 > { INT_EVENT0_ICLR_LOWIFG_W :: new (self) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_inifg (& mut self) -> INT_EVENT0_ICLR_INIFG_W < INT_EVENT0_ICLR_SPEC , 4 > { INT_EVENT0_ICLR_INIFG_W :: new (self) } # [doc = "Bit 5 - Raw interrupt flag for DMADONE. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_dmadone (& mut self) -> INT_EVENT0_ICLR_DMADONE_W < INT_EVENT0_ICLR_SPEC , 5 > { INT_EVENT0_ICLR_DMADONE_W :: new (self) } # [doc = "Bit 6 - Raw interrupt flag for MEMRESx underflow. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_uvifg (& mut self) -> INT_EVENT0_ICLR_UVIFG_W < INT_EVENT0_ICLR_SPEC , 6 > { INT_EVENT0_ICLR_UVIFG_W :: new (self) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_memresifg0 (& mut self) -> INT_EVENT0_ICLR_MEMRESIFG0_W < INT_EVENT0_ICLR_SPEC , 8 > { INT_EVENT0_ICLR_MEMRESIFG0_W :: new (self) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_memresifg1 (& mut self) -> INT_EVENT0_ICLR_MEMRESIFG1_W < INT_EVENT0_ICLR_SPEC , 9 > { INT_EVENT0_ICLR_MEMRESIFG1_W :: new (self) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_memresifg2 (& mut self) -> INT_EVENT0_ICLR_MEMRESIFG2_W < INT_EVENT0_ICLR_SPEC , 10 > { INT_EVENT0_ICLR_MEMRESIFG2_W :: new (self) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event0_iclr_memresifg3 (& mut self) -> INT_EVENT0_ICLR_MEMRESIFG3_W < INT_EVENT0_ICLR_SPEC , 11 > { INT_EVENT0_ICLR_MEMRESIFG3_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event0_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT0_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT0_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event0_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT0_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT0_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT0_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iidx`]
module"]
pub type INT_EVENT1_IIDX = crate :: Reg < int_event1_iidx :: INT_EVENT1_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event1_iidx { # [doc = "Register `INT_EVENT1_IIDX` reader"]
pub type R = crate :: R < INT_EVENT1_IIDX_SPEC > ; # [doc = "Field `INT_EVENT1_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT1_IIDX_STAT_R = crate :: FieldReader < INT_EVENT1_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u16)]
pub enum INT_EVENT1_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT1_IIDX_STAT_NO_INTR = 0 , # [doc = "3: HIGHIFG"]
INT_EVENT1_IIDX_STAT_HIGHIFG = 3 , # [doc = "4: LOWIFG"]
INT_EVENT1_IIDX_STAT_LOWIFG = 4 , # [doc = "5: INIFG"]
INT_EVENT1_IIDX_STAT_INIFG = 5 , # [doc = "9: MEMRESIFG0"]
INT_EVENT1_IIDX_STAT_MEMRESIFG0 = 9 , } impl From < INT_EVENT1_IIDX_STAT_A > for u16 { # [inline (always)]
fn from (variant : INT_EVENT1_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT1_IIDX_STAT_A { type Ux = u16 ; } impl INT_EVENT1_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT1_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR) , 3 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_HIGHIFG) , 4 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_LOWIFG) , 5 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_INIFG) , 9 => Some (INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MEMRESIFG0) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_NO_INTR } # [doc = "HIGHIFG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_highifg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_HIGHIFG } # [doc = "LOWIFG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_lowifg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_LOWIFG } # [doc = "INIFG"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_inifg (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_INIFG } # [doc = "MEMRESIFG0"]
# [inline (always)]
pub fn is_int_event1_iidx_stat_memresifg0 (& self) -> bool { * self == INT_EVENT1_IIDX_STAT_A :: INT_EVENT1_IIDX_STAT_MEMRESIFG0 } } impl R { # [doc = "Bits 0:9 - Interrupt index status"]
# [inline (always)]
pub fn int_event1_iidx_stat (& self) -> INT_EVENT1_IIDX_STAT_R { INT_EVENT1_IIDX_STAT_R :: new ((self . bits & 0x03ff) as u16) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT1_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_imask`]
module"]
pub type INT_EVENT1_IMASK = crate :: Reg < int_event1_imask :: INT_EVENT1_IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod int_event1_imask { # [doc = "Register `INT_EVENT1_IMASK` reader"]
pub type R = crate :: R < INT_EVENT1_IMASK_SPEC > ; # [doc = "Register `INT_EVENT1_IMASK` writer"]
pub type W = crate :: W < INT_EVENT1_IMASK_SPEC > ; # [doc = "Field `INT_EVENT1_IMASK_HIGHIFG` reader - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_IMASK_HIGHIFG_R = crate :: BitReader < INT_EVENT1_IMASK_HIGHIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_HIGHIFG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_HIGHIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_HIGHIFG_SET = 1 , } impl From < INT_EVENT1_IMASK_HIGHIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_HIGHIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_HIGHIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_HIGHIFG_A { match self . bits { false => INT_EVENT1_IMASK_HIGHIFG_A :: INT_EVENT1_IMASK_HIGHIFG_CLR , true => INT_EVENT1_IMASK_HIGHIFG_A :: INT_EVENT1_IMASK_HIGHIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_highifg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_HIGHIFG_A :: INT_EVENT1_IMASK_HIGHIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_highifg_set (& self) -> bool { * self == INT_EVENT1_IMASK_HIGHIFG_A :: INT_EVENT1_IMASK_HIGHIFG_SET } } # [doc = "Field `INT_EVENT1_IMASK_HIGHIFG` writer - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_IMASK_HIGHIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_HIGHIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_HIGHIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_highifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_HIGHIFG_A :: INT_EVENT1_IMASK_HIGHIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_highifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_HIGHIFG_A :: INT_EVENT1_IMASK_HIGHIFG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_LOWIFG` reader - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_IMASK_LOWIFG_R = crate :: BitReader < INT_EVENT1_IMASK_LOWIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_LOWIFG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_LOWIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_LOWIFG_SET = 1 , } impl From < INT_EVENT1_IMASK_LOWIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_LOWIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_LOWIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_LOWIFG_A { match self . bits { false => INT_EVENT1_IMASK_LOWIFG_A :: INT_EVENT1_IMASK_LOWIFG_CLR , true => INT_EVENT1_IMASK_LOWIFG_A :: INT_EVENT1_IMASK_LOWIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_lowifg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_LOWIFG_A :: INT_EVENT1_IMASK_LOWIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_lowifg_set (& self) -> bool { * self == INT_EVENT1_IMASK_LOWIFG_A :: INT_EVENT1_IMASK_LOWIFG_SET } } # [doc = "Field `INT_EVENT1_IMASK_LOWIFG` writer - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_IMASK_LOWIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_LOWIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_LOWIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_lowifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_LOWIFG_A :: INT_EVENT1_IMASK_LOWIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_lowifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_LOWIFG_A :: INT_EVENT1_IMASK_LOWIFG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_INIFG` reader - Mask INIFG in MIS_EX register."]
pub type INT_EVENT1_IMASK_INIFG_R = crate :: BitReader < INT_EVENT1_IMASK_INIFG_A > ; # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_INIFG_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_INIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_INIFG_SET = 1 , } impl From < INT_EVENT1_IMASK_INIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_INIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_INIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_INIFG_A { match self . bits { false => INT_EVENT1_IMASK_INIFG_A :: INT_EVENT1_IMASK_INIFG_CLR , true => INT_EVENT1_IMASK_INIFG_A :: INT_EVENT1_IMASK_INIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_inifg_clr (& self) -> bool { * self == INT_EVENT1_IMASK_INIFG_A :: INT_EVENT1_IMASK_INIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_inifg_set (& self) -> bool { * self == INT_EVENT1_IMASK_INIFG_A :: INT_EVENT1_IMASK_INIFG_SET } } # [doc = "Field `INT_EVENT1_IMASK_INIFG` writer - Mask INIFG in MIS_EX register."]
pub type INT_EVENT1_IMASK_INIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_INIFG_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_INIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_inifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_INIFG_A :: INT_EVENT1_IMASK_INIFG_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_inifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_INIFG_A :: INT_EVENT1_IMASK_INIFG_SET) } } # [doc = "Field `INT_EVENT1_IMASK_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT1_IMASK_MEMRESIFG0_R = crate :: BitReader < INT_EVENT1_IMASK_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_IMASK_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT1_IMASK_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_IMASK_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT1_IMASK_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_IMASK_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_IMASK_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_IMASK_MEMRESIFG0_A { match self . bits { false => INT_EVENT1_IMASK_MEMRESIFG0_A :: INT_EVENT1_IMASK_MEMRESIFG0_CLR , true => INT_EVENT1_IMASK_MEMRESIFG0_A :: INT_EVENT1_IMASK_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_imask_memresifg0_clr (& self) -> bool { * self == INT_EVENT1_IMASK_MEMRESIFG0_A :: INT_EVENT1_IMASK_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_imask_memresifg0_set (& self) -> bool { * self == INT_EVENT1_IMASK_MEMRESIFG0_A :: INT_EVENT1_IMASK_MEMRESIFG0_SET } } # [doc = "Field `INT_EVENT1_IMASK_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT1_IMASK_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_IMASK_MEMRESIFG0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT1_IMASK_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_imask_memresifg0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MEMRESIFG0_A :: INT_EVENT1_IMASK_MEMRESIFG0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_imask_memresifg0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_IMASK_MEMRESIFG0_A :: INT_EVENT1_IMASK_MEMRESIFG0_SET) } } impl R { # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event1_imask_highifg (& self) -> INT_EVENT1_IMASK_HIGHIFG_R { INT_EVENT1_IMASK_HIGHIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event1_imask_lowifg (& self) -> INT_EVENT1_IMASK_LOWIFG_R { INT_EVENT1_IMASK_LOWIFG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
pub fn int_event1_imask_inifg (& self) -> INT_EVENT1_IMASK_INIFG_R { INT_EVENT1_IMASK_INIFG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event1_imask_memresifg0 (& self) -> INT_EVENT1_IMASK_MEMRESIFG0_R { INT_EVENT1_IMASK_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } } impl W { # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_highifg (& mut self) -> INT_EVENT1_IMASK_HIGHIFG_W < INT_EVENT1_IMASK_SPEC , 2 > { INT_EVENT1_IMASK_HIGHIFG_W :: new (self) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_lowifg (& mut self) -> INT_EVENT1_IMASK_LOWIFG_W < INT_EVENT1_IMASK_SPEC , 3 > { INT_EVENT1_IMASK_LOWIFG_W :: new (self) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_inifg (& mut self) -> INT_EVENT1_IMASK_INIFG_W < INT_EVENT1_IMASK_SPEC , 4 > { INT_EVENT1_IMASK_INIFG_W :: new (self) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event1_imask_memresifg0 (& mut self) -> INT_EVENT1_IMASK_MEMRESIFG0_W < INT_EVENT1_IMASK_SPEC , 8 > { INT_EVENT1_IMASK_MEMRESIFG0_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event1_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT1_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_ris`]
module"]
pub type INT_EVENT1_RIS = crate :: Reg < int_event1_ris :: INT_EVENT1_RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod int_event1_ris { # [doc = "Register `INT_EVENT1_RIS` reader"]
pub type R = crate :: R < INT_EVENT1_RIS_SPEC > ; # [doc = "Field `INT_EVENT1_RIS_HIGHIFG` reader - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_RIS_HIGHIFG_R = crate :: BitReader < INT_EVENT1_RIS_HIGHIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_HIGHIFG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_HIGHIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_HIGHIFG_SET = 1 , } impl From < INT_EVENT1_RIS_HIGHIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_HIGHIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_HIGHIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_HIGHIFG_A { match self . bits { false => INT_EVENT1_RIS_HIGHIFG_A :: INT_EVENT1_RIS_HIGHIFG_CLR , true => INT_EVENT1_RIS_HIGHIFG_A :: INT_EVENT1_RIS_HIGHIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_highifg_clr (& self) -> bool { * self == INT_EVENT1_RIS_HIGHIFG_A :: INT_EVENT1_RIS_HIGHIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_highifg_set (& self) -> bool { * self == INT_EVENT1_RIS_HIGHIFG_A :: INT_EVENT1_RIS_HIGHIFG_SET } } # [doc = "Field `INT_EVENT1_RIS_LOWIFG` reader - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_RIS_LOWIFG_R = crate :: BitReader < INT_EVENT1_RIS_LOWIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_LOWIFG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_LOWIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_LOWIFG_SET = 1 , } impl From < INT_EVENT1_RIS_LOWIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_LOWIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_LOWIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_LOWIFG_A { match self . bits { false => INT_EVENT1_RIS_LOWIFG_A :: INT_EVENT1_RIS_LOWIFG_CLR , true => INT_EVENT1_RIS_LOWIFG_A :: INT_EVENT1_RIS_LOWIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_lowifg_clr (& self) -> bool { * self == INT_EVENT1_RIS_LOWIFG_A :: INT_EVENT1_RIS_LOWIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_lowifg_set (& self) -> bool { * self == INT_EVENT1_RIS_LOWIFG_A :: INT_EVENT1_RIS_LOWIFG_SET } } # [doc = "Field `INT_EVENT1_RIS_INIFG` reader - Mask INIFG in MIS_EX register."]
pub type INT_EVENT1_RIS_INIFG_R = crate :: BitReader < INT_EVENT1_RIS_INIFG_A > ; # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_INIFG_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_INIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_INIFG_SET = 1 , } impl From < INT_EVENT1_RIS_INIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_INIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_INIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_INIFG_A { match self . bits { false => INT_EVENT1_RIS_INIFG_A :: INT_EVENT1_RIS_INIFG_CLR , true => INT_EVENT1_RIS_INIFG_A :: INT_EVENT1_RIS_INIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_inifg_clr (& self) -> bool { * self == INT_EVENT1_RIS_INIFG_A :: INT_EVENT1_RIS_INIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_inifg_set (& self) -> bool { * self == INT_EVENT1_RIS_INIFG_A :: INT_EVENT1_RIS_INIFG_SET } } # [doc = "Field `INT_EVENT1_RIS_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT1_RIS_MEMRESIFG0_R = crate :: BitReader < INT_EVENT1_RIS_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_RIS_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT1_RIS_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_RIS_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT1_RIS_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_RIS_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_RIS_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_RIS_MEMRESIFG0_A { match self . bits { false => INT_EVENT1_RIS_MEMRESIFG0_A :: INT_EVENT1_RIS_MEMRESIFG0_CLR , true => INT_EVENT1_RIS_MEMRESIFG0_A :: INT_EVENT1_RIS_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_ris_memresifg0_clr (& self) -> bool { * self == INT_EVENT1_RIS_MEMRESIFG0_A :: INT_EVENT1_RIS_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_ris_memresifg0_set (& self) -> bool { * self == INT_EVENT1_RIS_MEMRESIFG0_A :: INT_EVENT1_RIS_MEMRESIFG0_SET } } impl R { # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event1_ris_highifg (& self) -> INT_EVENT1_RIS_HIGHIFG_R { INT_EVENT1_RIS_HIGHIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event1_ris_lowifg (& self) -> INT_EVENT1_RIS_LOWIFG_R { INT_EVENT1_RIS_LOWIFG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
pub fn int_event1_ris_inifg (& self) -> INT_EVENT1_RIS_INIFG_R { INT_EVENT1_RIS_INIFG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event1_ris_memresifg0 (& self) -> INT_EVENT1_RIS_MEMRESIFG0_R { INT_EVENT1_RIS_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_RIS to value 0"]
impl crate :: Resettable for INT_EVENT1_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_mis`]
module"]
pub type INT_EVENT1_MIS = crate :: Reg < int_event1_mis :: INT_EVENT1_MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod int_event1_mis { # [doc = "Register `INT_EVENT1_MIS` reader"]
pub type R = crate :: R < INT_EVENT1_MIS_SPEC > ; # [doc = "Field `INT_EVENT1_MIS_HIGHIFG` reader - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_MIS_HIGHIFG_R = crate :: BitReader < INT_EVENT1_MIS_HIGHIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_HIGHIFG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_HIGHIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_HIGHIFG_SET = 1 , } impl From < INT_EVENT1_MIS_HIGHIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_HIGHIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_HIGHIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_HIGHIFG_A { match self . bits { false => INT_EVENT1_MIS_HIGHIFG_A :: INT_EVENT1_MIS_HIGHIFG_CLR , true => INT_EVENT1_MIS_HIGHIFG_A :: INT_EVENT1_MIS_HIGHIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_highifg_clr (& self) -> bool { * self == INT_EVENT1_MIS_HIGHIFG_A :: INT_EVENT1_MIS_HIGHIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_highifg_set (& self) -> bool { * self == INT_EVENT1_MIS_HIGHIFG_A :: INT_EVENT1_MIS_HIGHIFG_SET } } # [doc = "Field `INT_EVENT1_MIS_LOWIFG` reader - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_MIS_LOWIFG_R = crate :: BitReader < INT_EVENT1_MIS_LOWIFG_A > ; # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_LOWIFG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_LOWIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_LOWIFG_SET = 1 , } impl From < INT_EVENT1_MIS_LOWIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_LOWIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_LOWIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_LOWIFG_A { match self . bits { false => INT_EVENT1_MIS_LOWIFG_A :: INT_EVENT1_MIS_LOWIFG_CLR , true => INT_EVENT1_MIS_LOWIFG_A :: INT_EVENT1_MIS_LOWIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_lowifg_clr (& self) -> bool { * self == INT_EVENT1_MIS_LOWIFG_A :: INT_EVENT1_MIS_LOWIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_lowifg_set (& self) -> bool { * self == INT_EVENT1_MIS_LOWIFG_A :: INT_EVENT1_MIS_LOWIFG_SET } } # [doc = "Field `INT_EVENT1_MIS_INIFG` reader - Mask INIFG in MIS_EX register."]
pub type INT_EVENT1_MIS_INIFG_R = crate :: BitReader < INT_EVENT1_MIS_INIFG_A > ; # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_INIFG_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_INIFG_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_INIFG_SET = 1 , } impl From < INT_EVENT1_MIS_INIFG_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_INIFG_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_INIFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_INIFG_A { match self . bits { false => INT_EVENT1_MIS_INIFG_A :: INT_EVENT1_MIS_INIFG_CLR , true => INT_EVENT1_MIS_INIFG_A :: INT_EVENT1_MIS_INIFG_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_inifg_clr (& self) -> bool { * self == INT_EVENT1_MIS_INIFG_A :: INT_EVENT1_MIS_INIFG_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_inifg_set (& self) -> bool { * self == INT_EVENT1_MIS_INIFG_A :: INT_EVENT1_MIS_INIFG_SET } } # [doc = "Field `INT_EVENT1_MIS_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT1_MIS_MEMRESIFG0_R = crate :: BitReader < INT_EVENT1_MIS_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_MIS_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT1_MIS_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT1_MIS_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT1_MIS_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_MIS_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT1_MIS_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT1_MIS_MEMRESIFG0_A { match self . bits { false => INT_EVENT1_MIS_MEMRESIFG0_A :: INT_EVENT1_MIS_MEMRESIFG0_CLR , true => INT_EVENT1_MIS_MEMRESIFG0_A :: INT_EVENT1_MIS_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event1_mis_memresifg0_clr (& self) -> bool { * self == INT_EVENT1_MIS_MEMRESIFG0_A :: INT_EVENT1_MIS_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event1_mis_memresifg0_set (& self) -> bool { * self == INT_EVENT1_MIS_MEMRESIFG0_A :: INT_EVENT1_MIS_MEMRESIFG0_SET } } impl R { # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event1_mis_highifg (& self) -> INT_EVENT1_MIS_HIGHIFG_R { INT_EVENT1_MIS_HIGHIFG_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
pub fn int_event1_mis_lowifg (& self) -> INT_EVENT1_MIS_LOWIFG_R { INT_EVENT1_MIS_LOWIFG_R :: new (((self . bits >> 3) & 1) != 0) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
pub fn int_event1_mis_inifg (& self) -> INT_EVENT1_MIS_INIFG_R { INT_EVENT1_MIS_INIFG_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event1_mis_memresifg0 (& self) -> INT_EVENT1_MIS_MEMRESIFG0_R { INT_EVENT1_MIS_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event1_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event1_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT1_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT1_MIS to value 0"]
impl crate :: Resettable for INT_EVENT1_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iset`]
module"]
pub type INT_EVENT1_ISET = crate :: Reg < int_event1_iset :: INT_EVENT1_ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod int_event1_iset { # [doc = "Register `INT_EVENT1_ISET` writer"]
pub type W = crate :: W < INT_EVENT1_ISET_SPEC > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_HIGHIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_HIGHIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_HIGHIFG_SET = 1 , } impl From < INT_EVENT1_ISET_HIGHIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_HIGHIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_HIGHIFG` writer - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_ISET_HIGHIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_HIGHIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_HIGHIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_highifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_HIGHIFG_AW :: INT_EVENT1_ISET_HIGHIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_highifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_HIGHIFG_AW :: INT_EVENT1_ISET_HIGHIFG_SET) } } # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_LOWIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_LOWIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_LOWIFG_SET = 1 , } impl From < INT_EVENT1_ISET_LOWIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_LOWIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_LOWIFG` writer - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_ISET_LOWIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_LOWIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_LOWIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_lowifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_LOWIFG_AW :: INT_EVENT1_ISET_LOWIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_lowifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_LOWIFG_AW :: INT_EVENT1_ISET_LOWIFG_SET) } } # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_INIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_INIFG_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_INIFG_SET = 1 , } impl From < INT_EVENT1_ISET_INIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_INIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_INIFG` writer - Mask INIFG in MIS_EX register."]
pub type INT_EVENT1_ISET_INIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_INIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_INIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_inifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_INIFG_AW :: INT_EVENT1_ISET_INIFG_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_inifg_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_INIFG_AW :: INT_EVENT1_ISET_INIFG_SET) } } # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ISET_MEMRESIFG0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ISET_MEMRESIFG0_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT1_ISET_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT1_ISET_MEMRESIFG0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ISET_MEMRESIFG0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ISET_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT1_ISET_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ISET_MEMRESIFG0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ISET_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iset_memresifg0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MEMRESIFG0_AW :: INT_EVENT1_ISET_MEMRESIFG0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event1_iset_memresifg0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ISET_MEMRESIFG0_AW :: INT_EVENT1_ISET_MEMRESIFG0_SET) } } impl W { # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_highifg (& mut self) -> INT_EVENT1_ISET_HIGHIFG_W < INT_EVENT1_ISET_SPEC , 2 > { INT_EVENT1_ISET_HIGHIFG_W :: new (self) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_lowifg (& mut self) -> INT_EVENT1_ISET_LOWIFG_W < INT_EVENT1_ISET_SPEC , 3 > { INT_EVENT1_ISET_LOWIFG_W :: new (self) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_inifg (& mut self) -> INT_EVENT1_ISET_INIFG_W < INT_EVENT1_ISET_SPEC , 4 > { INT_EVENT1_ISET_INIFG_W :: new (self) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event1_iset_memresifg0 (& mut self) -> INT_EVENT1_ISET_MEMRESIFG0_W < INT_EVENT1_ISET_SPEC , 8 > { INT_EVENT1_ISET_MEMRESIFG0_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ISET to value 0"]
impl crate :: Resettable for INT_EVENT1_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT1_ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event1_iclr`]
module"]
pub type INT_EVENT1_ICLR = crate :: Reg < int_event1_iclr :: INT_EVENT1_ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod int_event1_iclr { # [doc = "Register `INT_EVENT1_ICLR` writer"]
pub type W = crate :: W < INT_EVENT1_ICLR_SPEC > ; # [doc = "Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_HIGHIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_HIGHIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_HIGHIFG_CLR = 1 , } impl From < INT_EVENT1_ICLR_HIGHIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_HIGHIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_HIGHIFG` writer - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_ICLR_HIGHIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_HIGHIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_HIGHIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_highifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_HIGHIFG_AW :: INT_EVENT1_ICLR_HIGHIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_highifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_HIGHIFG_AW :: INT_EVENT1_ICLR_HIGHIFG_CLR) } } # [doc = "Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_LOWIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_LOWIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_LOWIFG_CLR = 1 , } impl From < INT_EVENT1_ICLR_LOWIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_LOWIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_LOWIFG` writer - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
pub type INT_EVENT1_ICLR_LOWIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_LOWIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_LOWIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_lowifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_LOWIFG_AW :: INT_EVENT1_ICLR_LOWIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_lowifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_LOWIFG_AW :: INT_EVENT1_ICLR_LOWIFG_CLR) } } # [doc = "Mask INIFG in MIS_EX register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_INIFG_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_INIFG_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_INIFG_CLR = 1 , } impl From < INT_EVENT1_ICLR_INIFG_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_INIFG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_INIFG` writer - Mask INIFG in MIS_EX register."]
pub type INT_EVENT1_ICLR_INIFG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_INIFG_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_INIFG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_inifg_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_INIFG_AW :: INT_EVENT1_ICLR_INIFG_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_inifg_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_INIFG_AW :: INT_EVENT1_ICLR_INIFG_CLR) } } # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT1_ICLR_MEMRESIFG0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT1_ICLR_MEMRESIFG0_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT1_ICLR_MEMRESIFG0_CLR = 1 , } impl From < INT_EVENT1_ICLR_MEMRESIFG0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT1_ICLR_MEMRESIFG0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT1_ICLR_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT1_ICLR_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT1_ICLR_MEMRESIFG0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT1_ICLR_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event1_iclr_memresifg0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MEMRESIFG0_AW :: INT_EVENT1_ICLR_MEMRESIFG0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event1_iclr_memresifg0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT1_ICLR_MEMRESIFG0_AW :: INT_EVENT1_ICLR_MEMRESIFG0_CLR) } } impl W { # [doc = "Bit 2 - Raw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_highifg (& mut self) -> INT_EVENT1_ICLR_HIGHIFG_W < INT_EVENT1_ICLR_SPEC , 2 > { INT_EVENT1_ICLR_HIGHIFG_W :: new (self) } # [doc = "Bit 3 - Raw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator. This bit is reset to 0 by IIDX read or when corresponding bit in ICLR_EX is set to 1."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_lowifg (& mut self) -> INT_EVENT1_ICLR_LOWIFG_W < INT_EVENT1_ICLR_SPEC , 3 > { INT_EVENT1_ICLR_LOWIFG_W :: new (self) } # [doc = "Bit 4 - Mask INIFG in MIS_EX register."]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_inifg (& mut self) -> INT_EVENT1_ICLR_INIFG_W < INT_EVENT1_ICLR_SPEC , 4 > { INT_EVENT1_ICLR_INIFG_W :: new (self) } # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event1_iclr_memresifg0 (& mut self) -> INT_EVENT1_ICLR_MEMRESIFG0_W < INT_EVENT1_ICLR_SPEC , 8 > { INT_EVENT1_ICLR_MEMRESIFG0_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event1_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT1_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT1_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event1_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT1_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT1_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT1_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iidx`]
module"]
pub type INT_EVENT2_IIDX = crate :: Reg < int_event2_iidx :: INT_EVENT2_IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod int_event2_iidx { # [doc = "Register `INT_EVENT2_IIDX` reader"]
pub type R = crate :: R < INT_EVENT2_IIDX_SPEC > ; # [doc = "Field `INT_EVENT2_IIDX_STAT` reader - Interrupt index status"]
pub type INT_EVENT2_IIDX_STAT_R = crate :: FieldReader < INT_EVENT2_IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u16)]
pub enum INT_EVENT2_IIDX_STAT_A { # [doc = "0: NO_INTR"]
INT_EVENT2_IIDX_STAT_NO_INTR = 0 , # [doc = "9: MEMRESIFG0"]
INT_EVENT2_IIDX_STAT_MEMRESIFG0 = 9 , # [doc = "10: MEMRESIFG1"]
INT_EVENT2_IIDX_STAT_MEMRESIFG1 = 10 , # [doc = "11: MEMRESIFG2"]
INT_EVENT2_IIDX_STAT_MEMRESIFG2 = 11 , # [doc = "12: MEMRESIFG3"]
INT_EVENT2_IIDX_STAT_MEMRESIFG3 = 12 , # [doc = "13: MEMRESIFG4"]
INT_EVENT2_IIDX_STAT_MEMRESIFG4 = 13 , # [doc = "14: MEMRESIFG5"]
INT_EVENT2_IIDX_STAT_MEMRESIFG5 = 14 , # [doc = "15: MEMRESIFG6"]
INT_EVENT2_IIDX_STAT_MEMRESIFG6 = 15 , # [doc = "16: MEMRESIFG7"]
INT_EVENT2_IIDX_STAT_MEMRESIFG7 = 16 , # [doc = "17: MEMRESIFG8"]
INT_EVENT2_IIDX_STAT_MEMRESIFG8 = 17 , # [doc = "18: MEMRESIFG9"]
INT_EVENT2_IIDX_STAT_MEMRESIFG9 = 18 , # [doc = "19: MEMRESIFG10"]
INT_EVENT2_IIDX_STAT_MEMRESIFG10 = 19 , # [doc = "20: MEMRESIFG11"]
INT_EVENT2_IIDX_STAT_MEMRESIFG11 = 20 , # [doc = "21: MEMRESIFG12"]
INT_EVENT2_IIDX_STAT_MEMRESIFG12 = 21 , # [doc = "22: MEMRESIFG13"]
INT_EVENT2_IIDX_STAT_MEMRESIFG13 = 22 , # [doc = "23: MEMRESIFG14"]
INT_EVENT2_IIDX_STAT_MEMRESIFG14 = 23 , # [doc = "24: MEMRESIFG15"]
INT_EVENT2_IIDX_STAT_MEMRESIFG15 = 24 , # [doc = "25: MEMRESIFG16"]
INT_EVENT2_IIDX_STAT_MEMRESIFG16 = 25 , # [doc = "26: MEMRESIFG17"]
INT_EVENT2_IIDX_STAT_MEMRESIFG17 = 26 , # [doc = "27: MEMRESIFG18"]
INT_EVENT2_IIDX_STAT_MEMRESIFG18 = 27 , # [doc = "28: MEMRESIFG19"]
INT_EVENT2_IIDX_STAT_MEMRESIFG19 = 28 , # [doc = "29: MEMRESIFG20"]
INT_EVENT2_IIDX_STAT_MEMRESIFG20 = 29 , # [doc = "30: MEMRESIFG21"]
INT_EVENT2_IIDX_STAT_MEMRESIFG21 = 30 , # [doc = "31: MEMRESIFG22"]
INT_EVENT2_IIDX_STAT_MEMRESIFG22 = 31 , # [doc = "32: MEMRESIFG23"]
INT_EVENT2_IIDX_STAT_MEMRESIFG23 = 32 , } impl From < INT_EVENT2_IIDX_STAT_A > for u16 { # [inline (always)]
fn from (variant : INT_EVENT2_IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for INT_EVENT2_IIDX_STAT_A { type Ux = u16 ; } impl INT_EVENT2_IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < INT_EVENT2_IIDX_STAT_A > { match self . bits { 0 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR) , 9 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG0) , 10 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG1) , 11 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG2) , 12 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG3) , 13 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG4) , 14 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG5) , 15 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG6) , 16 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG7) , 17 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG8) , 18 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG9) , 19 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG10) , 20 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG11) , 21 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG12) , 22 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG13) , 23 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG14) , 24 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG15) , 25 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG16) , 26 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG17) , 27 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG18) , 28 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG19) , 29 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG20) , 30 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG21) , 31 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG22) , 32 => Some (INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG23) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_no_intr (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_NO_INTR } # [doc = "MEMRESIFG0"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg0 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG0 } # [doc = "MEMRESIFG1"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg1 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG1 } # [doc = "MEMRESIFG2"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg2 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG2 } # [doc = "MEMRESIFG3"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg3 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG3 } # [doc = "MEMRESIFG4"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg4 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG4 } # [doc = "MEMRESIFG5"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg5 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG5 } # [doc = "MEMRESIFG6"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg6 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG6 } # [doc = "MEMRESIFG7"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg7 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG7 } # [doc = "MEMRESIFG8"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg8 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG8 } # [doc = "MEMRESIFG9"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg9 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG9 } # [doc = "MEMRESIFG10"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg10 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG10 } # [doc = "MEMRESIFG11"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg11 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG11 } # [doc = "MEMRESIFG12"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg12 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG12 } # [doc = "MEMRESIFG13"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg13 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG13 } # [doc = "MEMRESIFG14"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg14 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG14 } # [doc = "MEMRESIFG15"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg15 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG15 } # [doc = "MEMRESIFG16"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg16 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG16 } # [doc = "MEMRESIFG17"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg17 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG17 } # [doc = "MEMRESIFG18"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg18 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG18 } # [doc = "MEMRESIFG19"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg19 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG19 } # [doc = "MEMRESIFG20"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg20 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG20 } # [doc = "MEMRESIFG21"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg21 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG21 } # [doc = "MEMRESIFG22"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg22 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG22 } # [doc = "MEMRESIFG23"]
# [inline (always)]
pub fn is_int_event2_iidx_stat_memresifg23 (& self) -> bool { * self == INT_EVENT2_IIDX_STAT_A :: INT_EVENT2_IIDX_STAT_MEMRESIFG23 } } impl R { # [doc = "Bits 0:9 - Interrupt index status"]
# [inline (always)]
pub fn int_event2_iidx_stat (& self) -> INT_EVENT2_IIDX_STAT_R { INT_EVENT2_IIDX_STAT_R :: new ((self . bits & 0x03ff) as u16) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IIDX_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_iidx::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IIDX_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_IIDX to value 0"]
impl crate :: Resettable for INT_EVENT2_IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_IMASK (rw) register accessor: Interrupt mask extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_imask`]
module"]
pub type INT_EVENT2_IMASK = crate :: Reg < int_event2_imask :: INT_EVENT2_IMASK_SPEC > ; # [doc = "Interrupt mask extension"]
pub mod int_event2_imask { # [doc = "Register `INT_EVENT2_IMASK` reader"]
pub type R = crate :: R < INT_EVENT2_IMASK_SPEC > ; # [doc = "Register `INT_EVENT2_IMASK` writer"]
pub type W = crate :: W < INT_EVENT2_IMASK_SPEC > ; # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG0_R = crate :: BitReader < INT_EVENT2_IMASK_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT2_IMASK_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MEMRESIFG0_A { match self . bits { false => INT_EVENT2_IMASK_MEMRESIFG0_A :: INT_EVENT2_IMASK_MEMRESIFG0_CLR , true => INT_EVENT2_IMASK_MEMRESIFG0_A :: INT_EVENT2_IMASK_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg0_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG0_A :: INT_EVENT2_IMASK_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg0_set (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG0_A :: INT_EVENT2_IMASK_MEMRESIFG0_SET } } # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MEMRESIFG0_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_memresifg0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG0_A :: INT_EVENT2_IMASK_MEMRESIFG0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_memresifg0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG0_A :: INT_EVENT2_IMASK_MEMRESIFG0_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG1` reader - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG1_R = crate :: BitReader < INT_EVENT2_IMASK_MEMRESIFG1_A > ; # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MEMRESIFG1_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MEMRESIFG1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT2_IMASK_MEMRESIFG1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MEMRESIFG1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MEMRESIFG1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MEMRESIFG1_A { match self . bits { false => INT_EVENT2_IMASK_MEMRESIFG1_A :: INT_EVENT2_IMASK_MEMRESIFG1_CLR , true => INT_EVENT2_IMASK_MEMRESIFG1_A :: INT_EVENT2_IMASK_MEMRESIFG1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg1_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG1_A :: INT_EVENT2_IMASK_MEMRESIFG1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg1_set (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG1_A :: INT_EVENT2_IMASK_MEMRESIFG1_SET } } # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG1` writer - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MEMRESIFG1_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MEMRESIFG1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_memresifg1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG1_A :: INT_EVENT2_IMASK_MEMRESIFG1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_memresifg1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG1_A :: INT_EVENT2_IMASK_MEMRESIFG1_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG2` reader - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG2_R = crate :: BitReader < INT_EVENT2_IMASK_MEMRESIFG2_A > ; # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MEMRESIFG2_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MEMRESIFG2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT2_IMASK_MEMRESIFG2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MEMRESIFG2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MEMRESIFG2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MEMRESIFG2_A { match self . bits { false => INT_EVENT2_IMASK_MEMRESIFG2_A :: INT_EVENT2_IMASK_MEMRESIFG2_CLR , true => INT_EVENT2_IMASK_MEMRESIFG2_A :: INT_EVENT2_IMASK_MEMRESIFG2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg2_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG2_A :: INT_EVENT2_IMASK_MEMRESIFG2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg2_set (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG2_A :: INT_EVENT2_IMASK_MEMRESIFG2_SET } } # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG2` writer - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MEMRESIFG2_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MEMRESIFG2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_memresifg2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG2_A :: INT_EVENT2_IMASK_MEMRESIFG2_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_memresifg2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG2_A :: INT_EVENT2_IMASK_MEMRESIFG2_SET) } } # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG3` reader - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG3_R = crate :: BitReader < INT_EVENT2_IMASK_MEMRESIFG3_A > ; # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_IMASK_MEMRESIFG3_A { # [doc = "0: CLR"]
INT_EVENT2_IMASK_MEMRESIFG3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_IMASK_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT2_IMASK_MEMRESIFG3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_IMASK_MEMRESIFG3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_IMASK_MEMRESIFG3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_IMASK_MEMRESIFG3_A { match self . bits { false => INT_EVENT2_IMASK_MEMRESIFG3_A :: INT_EVENT2_IMASK_MEMRESIFG3_CLR , true => INT_EVENT2_IMASK_MEMRESIFG3_A :: INT_EVENT2_IMASK_MEMRESIFG3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg3_clr (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG3_A :: INT_EVENT2_IMASK_MEMRESIFG3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_imask_memresifg3_set (& self) -> bool { * self == INT_EVENT2_IMASK_MEMRESIFG3_A :: INT_EVENT2_IMASK_MEMRESIFG3_SET } } # [doc = "Field `INT_EVENT2_IMASK_MEMRESIFG3` writer - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_IMASK_MEMRESIFG3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_IMASK_MEMRESIFG3_A > ; impl < 'a , REG , const O : u8 > INT_EVENT2_IMASK_MEMRESIFG3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_imask_memresifg3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG3_A :: INT_EVENT2_IMASK_MEMRESIFG3_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_imask_memresifg3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_IMASK_MEMRESIFG3_A :: INT_EVENT2_IMASK_MEMRESIFG3_SET) } } impl R { # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_imask_memresifg0 (& self) -> INT_EVENT2_IMASK_MEMRESIFG0_R { INT_EVENT2_IMASK_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_imask_memresifg1 (& self) -> INT_EVENT2_IMASK_MEMRESIFG1_R { INT_EVENT2_IMASK_MEMRESIFG1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_imask_memresifg2 (& self) -> INT_EVENT2_IMASK_MEMRESIFG2_R { INT_EVENT2_IMASK_MEMRESIFG2_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_imask_memresifg3 (& self) -> INT_EVENT2_IMASK_MEMRESIFG3_R { INT_EVENT2_IMASK_MEMRESIFG3_R :: new (((self . bits >> 11) & 1) != 0) } } impl W { # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_memresifg0 (& mut self) -> INT_EVENT2_IMASK_MEMRESIFG0_W < INT_EVENT2_IMASK_SPEC , 8 > { INT_EVENT2_IMASK_MEMRESIFG0_W :: new (self) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_memresifg1 (& mut self) -> INT_EVENT2_IMASK_MEMRESIFG1_W < INT_EVENT2_IMASK_SPEC , 9 > { INT_EVENT2_IMASK_MEMRESIFG1_W :: new (self) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_memresifg2 (& mut self) -> INT_EVENT2_IMASK_MEMRESIFG2_W < INT_EVENT2_IMASK_SPEC , 10 > { INT_EVENT2_IMASK_MEMRESIFG2_W :: new (self) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_imask_memresifg3 (& mut self) -> INT_EVENT2_IMASK_MEMRESIFG3_W < INT_EVENT2_IMASK_SPEC , 11 > { INT_EVENT2_IMASK_MEMRESIFG3_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_IMASK_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_imask::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`int_event2_imask::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_IMASK to value 0"]
impl crate :: Resettable for INT_EVENT2_IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_RIS (r) register accessor: Raw interrupt status extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_ris`]
module"]
pub type INT_EVENT2_RIS = crate :: Reg < int_event2_ris :: INT_EVENT2_RIS_SPEC > ; # [doc = "Raw interrupt status extension"]
pub mod int_event2_ris { # [doc = "Register `INT_EVENT2_RIS` reader"]
pub type R = crate :: R < INT_EVENT2_RIS_SPEC > ; # [doc = "Field `INT_EVENT2_RIS_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_RIS_MEMRESIFG0_R = crate :: BitReader < INT_EVENT2_RIS_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT2_RIS_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MEMRESIFG0_A { match self . bits { false => INT_EVENT2_RIS_MEMRESIFG0_A :: INT_EVENT2_RIS_MEMRESIFG0_CLR , true => INT_EVENT2_RIS_MEMRESIFG0_A :: INT_EVENT2_RIS_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg0_clr (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG0_A :: INT_EVENT2_RIS_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg0_set (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG0_A :: INT_EVENT2_RIS_MEMRESIFG0_SET } } # [doc = "Field `INT_EVENT2_RIS_MEMRESIFG1` reader - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_RIS_MEMRESIFG1_R = crate :: BitReader < INT_EVENT2_RIS_MEMRESIFG1_A > ; # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MEMRESIFG1_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MEMRESIFG1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT2_RIS_MEMRESIFG1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MEMRESIFG1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MEMRESIFG1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MEMRESIFG1_A { match self . bits { false => INT_EVENT2_RIS_MEMRESIFG1_A :: INT_EVENT2_RIS_MEMRESIFG1_CLR , true => INT_EVENT2_RIS_MEMRESIFG1_A :: INT_EVENT2_RIS_MEMRESIFG1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg1_clr (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG1_A :: INT_EVENT2_RIS_MEMRESIFG1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg1_set (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG1_A :: INT_EVENT2_RIS_MEMRESIFG1_SET } } # [doc = "Field `INT_EVENT2_RIS_MEMRESIFG2` reader - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_RIS_MEMRESIFG2_R = crate :: BitReader < INT_EVENT2_RIS_MEMRESIFG2_A > ; # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MEMRESIFG2_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MEMRESIFG2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT2_RIS_MEMRESIFG2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MEMRESIFG2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MEMRESIFG2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MEMRESIFG2_A { match self . bits { false => INT_EVENT2_RIS_MEMRESIFG2_A :: INT_EVENT2_RIS_MEMRESIFG2_CLR , true => INT_EVENT2_RIS_MEMRESIFG2_A :: INT_EVENT2_RIS_MEMRESIFG2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg2_clr (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG2_A :: INT_EVENT2_RIS_MEMRESIFG2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg2_set (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG2_A :: INT_EVENT2_RIS_MEMRESIFG2_SET } } # [doc = "Field `INT_EVENT2_RIS_MEMRESIFG3` reader - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_RIS_MEMRESIFG3_R = crate :: BitReader < INT_EVENT2_RIS_MEMRESIFG3_A > ; # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_RIS_MEMRESIFG3_A { # [doc = "0: CLR"]
INT_EVENT2_RIS_MEMRESIFG3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_RIS_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT2_RIS_MEMRESIFG3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_RIS_MEMRESIFG3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_RIS_MEMRESIFG3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_RIS_MEMRESIFG3_A { match self . bits { false => INT_EVENT2_RIS_MEMRESIFG3_A :: INT_EVENT2_RIS_MEMRESIFG3_CLR , true => INT_EVENT2_RIS_MEMRESIFG3_A :: INT_EVENT2_RIS_MEMRESIFG3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg3_clr (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG3_A :: INT_EVENT2_RIS_MEMRESIFG3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_ris_memresifg3_set (& self) -> bool { * self == INT_EVENT2_RIS_MEMRESIFG3_A :: INT_EVENT2_RIS_MEMRESIFG3_SET } } impl R { # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_ris_memresifg0 (& self) -> INT_EVENT2_RIS_MEMRESIFG0_R { INT_EVENT2_RIS_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_ris_memresifg1 (& self) -> INT_EVENT2_RIS_MEMRESIFG1_R { INT_EVENT2_RIS_MEMRESIFG1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_ris_memresifg2 (& self) -> INT_EVENT2_RIS_MEMRESIFG2_R { INT_EVENT2_RIS_MEMRESIFG2_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_ris_memresifg3 (& self) -> INT_EVENT2_RIS_MEMRESIFG3_R { INT_EVENT2_RIS_MEMRESIFG3_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Raw interrupt status extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_RIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_ris::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_RIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_RIS to value 0"]
impl crate :: Resettable for INT_EVENT2_RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_MIS (r) register accessor: Masked interrupt status extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_mis`]
module"]
pub type INT_EVENT2_MIS = crate :: Reg < int_event2_mis :: INT_EVENT2_MIS_SPEC > ; # [doc = "Masked interrupt status extension"]
pub mod int_event2_mis { # [doc = "Register `INT_EVENT2_MIS` reader"]
pub type R = crate :: R < INT_EVENT2_MIS_SPEC > ; # [doc = "Field `INT_EVENT2_MIS_MEMRESIFG0` reader - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_MIS_MEMRESIFG0_R = crate :: BitReader < INT_EVENT2_MIS_MEMRESIFG0_A > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MEMRESIFG0_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MEMRESIFG0_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT2_MIS_MEMRESIFG0_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MEMRESIFG0_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MEMRESIFG0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MEMRESIFG0_A { match self . bits { false => INT_EVENT2_MIS_MEMRESIFG0_A :: INT_EVENT2_MIS_MEMRESIFG0_CLR , true => INT_EVENT2_MIS_MEMRESIFG0_A :: INT_EVENT2_MIS_MEMRESIFG0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg0_clr (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG0_A :: INT_EVENT2_MIS_MEMRESIFG0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg0_set (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG0_A :: INT_EVENT2_MIS_MEMRESIFG0_SET } } # [doc = "Field `INT_EVENT2_MIS_MEMRESIFG1` reader - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_MIS_MEMRESIFG1_R = crate :: BitReader < INT_EVENT2_MIS_MEMRESIFG1_A > ; # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MEMRESIFG1_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MEMRESIFG1_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT2_MIS_MEMRESIFG1_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MEMRESIFG1_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MEMRESIFG1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MEMRESIFG1_A { match self . bits { false => INT_EVENT2_MIS_MEMRESIFG1_A :: INT_EVENT2_MIS_MEMRESIFG1_CLR , true => INT_EVENT2_MIS_MEMRESIFG1_A :: INT_EVENT2_MIS_MEMRESIFG1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg1_clr (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG1_A :: INT_EVENT2_MIS_MEMRESIFG1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg1_set (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG1_A :: INT_EVENT2_MIS_MEMRESIFG1_SET } } # [doc = "Field `INT_EVENT2_MIS_MEMRESIFG2` reader - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_MIS_MEMRESIFG2_R = crate :: BitReader < INT_EVENT2_MIS_MEMRESIFG2_A > ; # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MEMRESIFG2_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MEMRESIFG2_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT2_MIS_MEMRESIFG2_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MEMRESIFG2_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MEMRESIFG2_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MEMRESIFG2_A { match self . bits { false => INT_EVENT2_MIS_MEMRESIFG2_A :: INT_EVENT2_MIS_MEMRESIFG2_CLR , true => INT_EVENT2_MIS_MEMRESIFG2_A :: INT_EVENT2_MIS_MEMRESIFG2_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg2_clr (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG2_A :: INT_EVENT2_MIS_MEMRESIFG2_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg2_set (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG2_A :: INT_EVENT2_MIS_MEMRESIFG2_SET } } # [doc = "Field `INT_EVENT2_MIS_MEMRESIFG3` reader - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_MIS_MEMRESIFG3_R = crate :: BitReader < INT_EVENT2_MIS_MEMRESIFG3_A > ; # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_MIS_MEMRESIFG3_A { # [doc = "0: CLR"]
INT_EVENT2_MIS_MEMRESIFG3_CLR = 0 , # [doc = "1: SET"]
INT_EVENT2_MIS_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT2_MIS_MEMRESIFG3_A > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_MIS_MEMRESIFG3_A) -> Self { variant as u8 != 0 } } impl INT_EVENT2_MIS_MEMRESIFG3_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> INT_EVENT2_MIS_MEMRESIFG3_A { match self . bits { false => INT_EVENT2_MIS_MEMRESIFG3_A :: INT_EVENT2_MIS_MEMRESIFG3_CLR , true => INT_EVENT2_MIS_MEMRESIFG3_A :: INT_EVENT2_MIS_MEMRESIFG3_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg3_clr (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG3_A :: INT_EVENT2_MIS_MEMRESIFG3_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_int_event2_mis_memresifg3_set (& self) -> bool { * self == INT_EVENT2_MIS_MEMRESIFG3_A :: INT_EVENT2_MIS_MEMRESIFG3_SET } } impl R { # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_mis_memresifg0 (& self) -> INT_EVENT2_MIS_MEMRESIFG0_R { INT_EVENT2_MIS_MEMRESIFG0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_mis_memresifg1 (& self) -> INT_EVENT2_MIS_MEMRESIFG1_R { INT_EVENT2_MIS_MEMRESIFG1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_mis_memresifg2 (& self) -> INT_EVENT2_MIS_MEMRESIFG2_R { INT_EVENT2_MIS_MEMRESIFG2_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
pub fn int_event2_mis_memresifg3 (& self) -> INT_EVENT2_MIS_MEMRESIFG3_R { INT_EVENT2_MIS_MEMRESIFG3_R :: new (((self . bits >> 11) & 1) != 0) } } # [doc = "Masked interrupt status extension\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_event2_mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_MIS_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`int_event2_mis::R`](R) reader structure"]
impl crate :: Readable for INT_EVENT2_MIS_SPEC { } # [doc = "`reset()` method sets INT_EVENT2_MIS to value 0"]
impl crate :: Resettable for INT_EVENT2_MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ISET (w) register accessor: Interrupt set extension\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iset`]
module"]
pub type INT_EVENT2_ISET = crate :: Reg < int_event2_iset :: INT_EVENT2_ISET_SPEC > ; # [doc = "Interrupt set extension"]
pub mod int_event2_iset { # [doc = "Register `INT_EVENT2_ISET` writer"]
pub type W = crate :: W < INT_EVENT2_ISET_SPEC > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MEMRESIFG0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MEMRESIFG0_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MEMRESIFG0_SET = 1 , } impl From < INT_EVENT2_ISET_MEMRESIFG0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MEMRESIFG0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ISET_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MEMRESIFG0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_memresifg0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG0_AW :: INT_EVENT2_ISET_MEMRESIFG0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_memresifg0_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG0_AW :: INT_EVENT2_ISET_MEMRESIFG0_SET) } } # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MEMRESIFG1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MEMRESIFG1_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MEMRESIFG1_SET = 1 , } impl From < INT_EVENT2_ISET_MEMRESIFG1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MEMRESIFG1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MEMRESIFG1` writer - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ISET_MEMRESIFG1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MEMRESIFG1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MEMRESIFG1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_memresifg1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG1_AW :: INT_EVENT2_ISET_MEMRESIFG1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_memresifg1_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG1_AW :: INT_EVENT2_ISET_MEMRESIFG1_SET) } } # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MEMRESIFG2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MEMRESIFG2_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MEMRESIFG2_SET = 1 , } impl From < INT_EVENT2_ISET_MEMRESIFG2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MEMRESIFG2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MEMRESIFG2` writer - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ISET_MEMRESIFG2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MEMRESIFG2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MEMRESIFG2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_memresifg2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG2_AW :: INT_EVENT2_ISET_MEMRESIFG2_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_memresifg2_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG2_AW :: INT_EVENT2_ISET_MEMRESIFG2_SET) } } # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ISET_MEMRESIFG3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ISET_MEMRESIFG3_NO_EFFECT = 0 , # [doc = "1: SET"]
INT_EVENT2_ISET_MEMRESIFG3_SET = 1 , } impl From < INT_EVENT2_ISET_MEMRESIFG3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ISET_MEMRESIFG3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ISET_MEMRESIFG3` writer - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ISET_MEMRESIFG3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ISET_MEMRESIFG3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ISET_MEMRESIFG3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iset_memresifg3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG3_AW :: INT_EVENT2_ISET_MEMRESIFG3_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn int_event2_iset_memresifg3_set (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ISET_MEMRESIFG3_AW :: INT_EVENT2_ISET_MEMRESIFG3_SET) } } impl W { # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_memresifg0 (& mut self) -> INT_EVENT2_ISET_MEMRESIFG0_W < INT_EVENT2_ISET_SPEC , 8 > { INT_EVENT2_ISET_MEMRESIFG0_W :: new (self) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_memresifg1 (& mut self) -> INT_EVENT2_ISET_MEMRESIFG1_W < INT_EVENT2_ISET_SPEC , 9 > { INT_EVENT2_ISET_MEMRESIFG1_W :: new (self) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_memresifg2 (& mut self) -> INT_EVENT2_ISET_MEMRESIFG2_W < INT_EVENT2_ISET_SPEC , 10 > { INT_EVENT2_ISET_MEMRESIFG2_W :: new (self) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iset_memresifg3 (& mut self) -> INT_EVENT2_ISET_MEMRESIFG3_W < INT_EVENT2_ISET_SPEC , 11 > { INT_EVENT2_ISET_MEMRESIFG3_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set extension\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ISET_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iset::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ISET to value 0"]
impl crate :: Resettable for INT_EVENT2_ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "INT_EVENT2_ICLR (w) register accessor: Interrupt clear extension\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_event2_iclr`]
module"]
pub type INT_EVENT2_ICLR = crate :: Reg < int_event2_iclr :: INT_EVENT2_ICLR_SPEC > ; # [doc = "Interrupt clear extension"]
pub mod int_event2_iclr { # [doc = "Register `INT_EVENT2_ICLR` writer"]
pub type W = crate :: W < INT_EVENT2_ICLR_SPEC > ; # [doc = "Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MEMRESIFG0_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MEMRESIFG0_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MEMRESIFG0_CLR = 1 , } impl From < INT_EVENT2_ICLR_MEMRESIFG0_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MEMRESIFG0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MEMRESIFG0` writer - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ICLR_MEMRESIFG0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MEMRESIFG0_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MEMRESIFG0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_memresifg0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG0_AW :: INT_EVENT2_ICLR_MEMRESIFG0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_memresifg0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG0_AW :: INT_EVENT2_ICLR_MEMRESIFG0_CLR) } } # [doc = "Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MEMRESIFG1_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MEMRESIFG1_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MEMRESIFG1_CLR = 1 , } impl From < INT_EVENT2_ICLR_MEMRESIFG1_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MEMRESIFG1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MEMRESIFG1` writer - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ICLR_MEMRESIFG1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MEMRESIFG1_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MEMRESIFG1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_memresifg1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG1_AW :: INT_EVENT2_ICLR_MEMRESIFG1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_memresifg1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG1_AW :: INT_EVENT2_ICLR_MEMRESIFG1_CLR) } } # [doc = "Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MEMRESIFG2_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MEMRESIFG2_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MEMRESIFG2_CLR = 1 , } impl From < INT_EVENT2_ICLR_MEMRESIFG2_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MEMRESIFG2_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MEMRESIFG2` writer - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ICLR_MEMRESIFG2_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MEMRESIFG2_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MEMRESIFG2_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_memresifg2_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG2_AW :: INT_EVENT2_ICLR_MEMRESIFG2_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_memresifg2_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG2_AW :: INT_EVENT2_ICLR_MEMRESIFG2_CLR) } } # [doc = "Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum INT_EVENT2_ICLR_MEMRESIFG3_AW { # [doc = "0: NO_EFFECT"]
INT_EVENT2_ICLR_MEMRESIFG3_NO_EFFECT = 0 , # [doc = "1: CLR"]
INT_EVENT2_ICLR_MEMRESIFG3_CLR = 1 , } impl From < INT_EVENT2_ICLR_MEMRESIFG3_AW > for bool { # [inline (always)]
fn from (variant : INT_EVENT2_ICLR_MEMRESIFG3_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `INT_EVENT2_ICLR_MEMRESIFG3` writer - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
pub type INT_EVENT2_ICLR_MEMRESIFG3_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , INT_EVENT2_ICLR_MEMRESIFG3_AW > ; impl < 'a , REG , const O : u8 > INT_EVENT2_ICLR_MEMRESIFG3_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn int_event2_iclr_memresifg3_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG3_AW :: INT_EVENT2_ICLR_MEMRESIFG3_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn int_event2_iclr_memresifg3_clr (self) -> & 'a mut crate :: W < REG > { self . variant (INT_EVENT2_ICLR_MEMRESIFG3_AW :: INT_EVENT2_ICLR_MEMRESIFG3_CLR) } } impl W { # [doc = "Bit 8 - Raw interrupt status for MEMRES0. This bit is set to 1 when MEMRES0 is loaded with a new conversion result. Reading MEMRES0 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_memresifg0 (& mut self) -> INT_EVENT2_ICLR_MEMRESIFG0_W < INT_EVENT2_ICLR_SPEC , 8 > { INT_EVENT2_ICLR_MEMRESIFG0_W :: new (self) } # [doc = "Bit 9 - Raw interrupt status for MEMRES1. This bit is set to 1 when MEMRES1 is loaded with a new conversion result. Reading MEMRES1 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_memresifg1 (& mut self) -> INT_EVENT2_ICLR_MEMRESIFG1_W < INT_EVENT2_ICLR_SPEC , 9 > { INT_EVENT2_ICLR_MEMRESIFG1_W :: new (self) } # [doc = "Bit 10 - Raw interrupt status for MEMRES2. This bit is set to 1 when MEMRES2 is loaded with a new conversion result. Reading MEMRES2 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_memresifg2 (& mut self) -> INT_EVENT2_ICLR_MEMRESIFG2_W < INT_EVENT2_ICLR_SPEC , 10 > { INT_EVENT2_ICLR_MEMRESIFG2_W :: new (self) } # [doc = "Bit 11 - Raw interrupt status for MEMRES3. This bit is set to 1 when MEMRES3 is loaded with a new conversion result. Reading MEMRES3 register will clear this bit, or when the corresponding bit in ICLR is set to 1"]
# [inline (always)]
# [must_use]
pub fn int_event2_iclr_memresifg3 (& mut self) -> INT_EVENT2_ICLR_MEMRESIFG3_W < INT_EVENT2_ICLR_SPEC , 11 > { INT_EVENT2_ICLR_MEMRESIFG3_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear extension\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_event2_iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct INT_EVENT2_ICLR_SPEC ; impl crate :: RegisterSpec for INT_EVENT2_ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`int_event2_iclr::W`](W) writer structure"]
impl crate :: Writable for INT_EVENT2_ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets INT_EVENT2_ICLR to value 0"]
impl crate :: Resettable for INT_EVENT2_ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (r) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_INT0_CFG` reader - Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0"]
pub type EVT_MODE_INT0_CFG_R = crate :: FieldReader < EVT_MODE_INT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_INT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_INT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_INT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_INT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_INT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_INT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_INT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_INT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_INT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE) , 1 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_disable (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_software (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_int0_cfg_hardware (& self) -> bool { * self == EVT_MODE_INT0_CFG_A :: EVT_MODE_INT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0"]
# [inline (always)]
pub fn evt_mode_int0_cfg (& self) -> EVT_MODE_INT0_CFG_R { EVT_MODE_INT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to IPSTANDARD.INT_EVENT1"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`reset()` method sets EVT_MODE to value 0"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl0`]
module"]
pub type CTL0 = crate :: Reg < ctl0 :: CTL0_SPEC > ; # [doc = "Control Register 0"]
pub mod ctl0 { # [doc = "Register `CTL0` reader"]
pub type R = crate :: R < CTL0_SPEC > ; # [doc = "Register `CTL0` writer"]
pub type W = crate :: W < CTL0_SPEC > ; # [doc = "Field `CTL0_ENC` reader - Enable conversion"]
pub type CTL0_ENC_R = crate :: BitReader < CTL0_ENC_A > ; # [doc = "Enable conversion\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_ENC_A { # [doc = "0: OFF"]
CTL0_ENC_OFF = 0 , # [doc = "1: ON"]
CTL0_ENC_ON = 1 , } impl From < CTL0_ENC_A > for bool { # [inline (always)]
fn from (variant : CTL0_ENC_A) -> Self { variant as u8 != 0 } } impl CTL0_ENC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_ENC_A { match self . bits { false => CTL0_ENC_A :: CTL0_ENC_OFF , true => CTL0_ENC_A :: CTL0_ENC_ON , } } # [doc = "OFF"]
# [inline (always)]
pub fn is_ctl0_enc_off (& self) -> bool { * self == CTL0_ENC_A :: CTL0_ENC_OFF } # [doc = "ON"]
# [inline (always)]
pub fn is_ctl0_enc_on (& self) -> bool { * self == CTL0_ENC_A :: CTL0_ENC_ON } } # [doc = "Field `CTL0_ENC` writer - Enable conversion"]
pub type CTL0_ENC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_ENC_A > ; impl < 'a , REG , const O : u8 > CTL0_ENC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "OFF"]
# [inline (always)]
pub fn ctl0_enc_off (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENC_A :: CTL0_ENC_OFF) } # [doc = "ON"]
# [inline (always)]
pub fn ctl0_enc_on (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_ENC_A :: CTL0_ENC_ON) } } # [doc = "Field `CTL0_PWRDN` reader - Power down policy"]
pub type CTL0_PWRDN_R = crate :: BitReader < CTL0_PWRDN_A > ; # [doc = "Power down policy\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL0_PWRDN_A { # [doc = "0: AUTO"]
CTL0_PWRDN_AUTO = 0 , # [doc = "1: MANUAL"]
CTL0_PWRDN_MANUAL = 1 , } impl From < CTL0_PWRDN_A > for bool { # [inline (always)]
fn from (variant : CTL0_PWRDN_A) -> Self { variant as u8 != 0 } } impl CTL0_PWRDN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_PWRDN_A { match self . bits { false => CTL0_PWRDN_A :: CTL0_PWRDN_AUTO , true => CTL0_PWRDN_A :: CTL0_PWRDN_MANUAL , } } # [doc = "AUTO"]
# [inline (always)]
pub fn is_ctl0_pwrdn_auto (& self) -> bool { * self == CTL0_PWRDN_A :: CTL0_PWRDN_AUTO } # [doc = "MANUAL"]
# [inline (always)]
pub fn is_ctl0_pwrdn_manual (& self) -> bool { * self == CTL0_PWRDN_A :: CTL0_PWRDN_MANUAL } } # [doc = "Field `CTL0_PWRDN` writer - Power down policy"]
pub type CTL0_PWRDN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL0_PWRDN_A > ; impl < 'a , REG , const O : u8 > CTL0_PWRDN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "AUTO"]
# [inline (always)]
pub fn ctl0_pwrdn_auto (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_PWRDN_A :: CTL0_PWRDN_AUTO) } # [doc = "MANUAL"]
# [inline (always)]
pub fn ctl0_pwrdn_manual (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_PWRDN_A :: CTL0_PWRDN_MANUAL) } } # [doc = "Field `CTL0_SCLKDIV` reader - Sample clock divider"]
pub type CTL0_SCLKDIV_R = crate :: FieldReader < CTL0_SCLKDIV_A > ; # [doc = "Sample clock divider\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL0_SCLKDIV_A { # [doc = "0: DIV_BY_1"]
CTL0_SCLKDIV_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CTL0_SCLKDIV_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_4"]
CTL0_SCLKDIV_DIV_BY_4 = 2 , # [doc = "3: DIV_BY_8"]
CTL0_SCLKDIV_DIV_BY_8 = 3 , # [doc = "4: DIV_BY_16"]
CTL0_SCLKDIV_DIV_BY_16 = 4 , # [doc = "5: DIV_BY_24"]
CTL0_SCLKDIV_DIV_BY_24 = 5 , # [doc = "6: DIV_BY_32"]
CTL0_SCLKDIV_DIV_BY_32 = 6 , # [doc = "7: DIV_BY_48"]
CTL0_SCLKDIV_DIV_BY_48 = 7 , } impl From < CTL0_SCLKDIV_A > for u8 { # [inline (always)]
fn from (variant : CTL0_SCLKDIV_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL0_SCLKDIV_A { type Ux = u8 ; } impl CTL0_SCLKDIV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL0_SCLKDIV_A { match self . bits { 0 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_1 , 1 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_2 , 2 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_4 , 3 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_8 , 4 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_16 , 5 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_24 , 6 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_32 , 7 => CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_48 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_1 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_2 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_2 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_4 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_4 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_8 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_8 } # [doc = "DIV_BY_16"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_16 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_16 } # [doc = "DIV_BY_24"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_24 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_24 } # [doc = "DIV_BY_32"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_32 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_32 } # [doc = "DIV_BY_48"]
# [inline (always)]
pub fn is_ctl0_sclkdiv_div_by_48 (& self) -> bool { * self == CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_48 } } # [doc = "Field `CTL0_SCLKDIV` writer - Sample clock divider"]
pub type CTL0_SCLKDIV_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CTL0_SCLKDIV_A > ; impl < 'a , REG , const O : u8 > CTL0_SCLKDIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_2) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_4) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_8) } # [doc = "DIV_BY_16"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_16) } # [doc = "DIV_BY_24"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_24 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_24) } # [doc = "DIV_BY_32"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_32 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_32) } # [doc = "DIV_BY_48"]
# [inline (always)]
pub fn ctl0_sclkdiv_div_by_48 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL0_SCLKDIV_A :: CTL0_SCLKDIV_DIV_BY_48) } } impl R { # [doc = "Bit 0 - Enable conversion"]
# [inline (always)]
pub fn ctl0_enc (& self) -> CTL0_ENC_R { CTL0_ENC_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 16 - Power down policy"]
# [inline (always)]
pub fn ctl0_pwrdn (& self) -> CTL0_PWRDN_R { CTL0_PWRDN_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bits 24:26 - Sample clock divider"]
# [inline (always)]
pub fn ctl0_sclkdiv (& self) -> CTL0_SCLKDIV_R { CTL0_SCLKDIV_R :: new (((self . bits >> 24) & 7) as u8) } } impl W { # [doc = "Bit 0 - Enable conversion"]
# [inline (always)]
# [must_use]
pub fn ctl0_enc (& mut self) -> CTL0_ENC_W < CTL0_SPEC , 0 > { CTL0_ENC_W :: new (self) } # [doc = "Bit 16 - Power down policy"]
# [inline (always)]
# [must_use]
pub fn ctl0_pwrdn (& mut self) -> CTL0_PWRDN_W < CTL0_SPEC , 16 > { CTL0_PWRDN_W :: new (self) } # [doc = "Bits 24:26 - Sample clock divider"]
# [inline (always)]
# [must_use]
pub fn ctl0_sclkdiv (& mut self) -> CTL0_SCLKDIV_W < CTL0_SPEC , 24 > { CTL0_SCLKDIV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL0_SPEC ; impl crate :: RegisterSpec for CTL0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl0::R`](R) reader structure"]
impl crate :: Readable for CTL0_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl0::W`](W) writer structure"]
impl crate :: Writable for CTL0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL0 to value 0"]
impl crate :: Resettable for CTL0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl1`]
module"]
pub type CTL1 = crate :: Reg < ctl1 :: CTL1_SPEC > ; # [doc = "Control Register 1"]
pub mod ctl1 { # [doc = "Register `CTL1` reader"]
pub type R = crate :: R < CTL1_SPEC > ; # [doc = "Register `CTL1` writer"]
pub type W = crate :: W < CTL1_SPEC > ; # [doc = "Field `CTL1_TRIGSRC` reader - Sample trigger source"]
pub type CTL1_TRIGSRC_R = crate :: BitReader < CTL1_TRIGSRC_A > ; # [doc = "Sample trigger source\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_TRIGSRC_A { # [doc = "0: SOFTWARE"]
CTL1_TRIGSRC_SOFTWARE = 0 , # [doc = "1: EVENT"]
CTL1_TRIGSRC_EVENT = 1 , } impl From < CTL1_TRIGSRC_A > for bool { # [inline (always)]
fn from (variant : CTL1_TRIGSRC_A) -> Self { variant as u8 != 0 } } impl CTL1_TRIGSRC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_TRIGSRC_A { match self . bits { false => CTL1_TRIGSRC_A :: CTL1_TRIGSRC_SOFTWARE , true => CTL1_TRIGSRC_A :: CTL1_TRIGSRC_EVENT , } } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_ctl1_trigsrc_software (& self) -> bool { * self == CTL1_TRIGSRC_A :: CTL1_TRIGSRC_SOFTWARE } # [doc = "EVENT"]
# [inline (always)]
pub fn is_ctl1_trigsrc_event (& self) -> bool { * self == CTL1_TRIGSRC_A :: CTL1_TRIGSRC_EVENT } } # [doc = "Field `CTL1_TRIGSRC` writer - Sample trigger source"]
pub type CTL1_TRIGSRC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_TRIGSRC_A > ; impl < 'a , REG , const O : u8 > CTL1_TRIGSRC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "SOFTWARE"]
# [inline (always)]
pub fn ctl1_trigsrc_software (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_TRIGSRC_A :: CTL1_TRIGSRC_SOFTWARE) } # [doc = "EVENT"]
# [inline (always)]
pub fn ctl1_trigsrc_event (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_TRIGSRC_A :: CTL1_TRIGSRC_EVENT) } } # [doc = "Field `CTL1_SC` reader - Start of conversion"]
pub type CTL1_SC_R = crate :: BitReader < CTL1_SC_A > ; # [doc = "Start of conversion\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_SC_A { # [doc = "0: STOP"]
CTL1_SC_STOP = 0 , # [doc = "1: START"]
CTL1_SC_START = 1 , } impl From < CTL1_SC_A > for bool { # [inline (always)]
fn from (variant : CTL1_SC_A) -> Self { variant as u8 != 0 } } impl CTL1_SC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_SC_A { match self . bits { false => CTL1_SC_A :: CTL1_SC_STOP , true => CTL1_SC_A :: CTL1_SC_START , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_ctl1_sc_stop (& self) -> bool { * self == CTL1_SC_A :: CTL1_SC_STOP } # [doc = "START"]
# [inline (always)]
pub fn is_ctl1_sc_start (& self) -> bool { * self == CTL1_SC_A :: CTL1_SC_START } } # [doc = "Field `CTL1_SC` writer - Start of conversion"]
pub type CTL1_SC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_SC_A > ; impl < 'a , REG , const O : u8 > CTL1_SC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn ctl1_sc_stop (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SC_A :: CTL1_SC_STOP) } # [doc = "START"]
# [inline (always)]
pub fn ctl1_sc_start (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SC_A :: CTL1_SC_START) } } # [doc = "Field `CTL1_CONSEQ` reader - Conversion sequence mode"]
pub type CTL1_CONSEQ_R = crate :: FieldReader < CTL1_CONSEQ_A > ; # [doc = "Conversion sequence mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL1_CONSEQ_A { # [doc = "0: SINGLE"]
CTL1_CONSEQ_SINGLE = 0 , # [doc = "1: SEQUENCE"]
CTL1_CONSEQ_SEQUENCE = 1 , # [doc = "2: REPEATSINGLE"]
CTL1_CONSEQ_REPEATSINGLE = 2 , # [doc = "3: REPEATSEQUENCE"]
CTL1_CONSEQ_REPEATSEQUENCE = 3 , } impl From < CTL1_CONSEQ_A > for u8 { # [inline (always)]
fn from (variant : CTL1_CONSEQ_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL1_CONSEQ_A { type Ux = u8 ; } impl CTL1_CONSEQ_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_CONSEQ_A { match self . bits { 0 => CTL1_CONSEQ_A :: CTL1_CONSEQ_SINGLE , 1 => CTL1_CONSEQ_A :: CTL1_CONSEQ_SEQUENCE , 2 => CTL1_CONSEQ_A :: CTL1_CONSEQ_REPEATSINGLE , 3 => CTL1_CONSEQ_A :: CTL1_CONSEQ_REPEATSEQUENCE , _ => unreachable ! () , } } # [doc = "SINGLE"]
# [inline (always)]
pub fn is_ctl1_conseq_single (& self) -> bool { * self == CTL1_CONSEQ_A :: CTL1_CONSEQ_SINGLE } # [doc = "SEQUENCE"]
# [inline (always)]
pub fn is_ctl1_conseq_sequence (& self) -> bool { * self == CTL1_CONSEQ_A :: CTL1_CONSEQ_SEQUENCE } # [doc = "REPEATSINGLE"]
# [inline (always)]
pub fn is_ctl1_conseq_repeatsingle (& self) -> bool { * self == CTL1_CONSEQ_A :: CTL1_CONSEQ_REPEATSINGLE } # [doc = "REPEATSEQUENCE"]
# [inline (always)]
pub fn is_ctl1_conseq_repeatsequence (& self) -> bool { * self == CTL1_CONSEQ_A :: CTL1_CONSEQ_REPEATSEQUENCE } } # [doc = "Field `CTL1_CONSEQ` writer - Conversion sequence mode"]
pub type CTL1_CONSEQ_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CTL1_CONSEQ_A > ; impl < 'a , REG , const O : u8 > CTL1_CONSEQ_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SINGLE"]
# [inline (always)]
pub fn ctl1_conseq_single (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CONSEQ_A :: CTL1_CONSEQ_SINGLE) } # [doc = "SEQUENCE"]
# [inline (always)]
pub fn ctl1_conseq_sequence (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CONSEQ_A :: CTL1_CONSEQ_SEQUENCE) } # [doc = "REPEATSINGLE"]
# [inline (always)]
pub fn ctl1_conseq_repeatsingle (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CONSEQ_A :: CTL1_CONSEQ_REPEATSINGLE) } # [doc = "REPEATSEQUENCE"]
# [inline (always)]
pub fn ctl1_conseq_repeatsequence (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_CONSEQ_A :: CTL1_CONSEQ_REPEATSEQUENCE) } } # [doc = "Field `CTL1_SAMPMODE` reader - Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger."]
pub type CTL1_SAMPMODE_R = crate :: BitReader < CTL1_SAMPMODE_A > ; # [doc = "Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL1_SAMPMODE_A { # [doc = "0: AUTO"]
CTL1_SAMPMODE_AUTO = 0 , # [doc = "1: MANUAL"]
CTL1_SAMPMODE_MANUAL = 1 , } impl From < CTL1_SAMPMODE_A > for bool { # [inline (always)]
fn from (variant : CTL1_SAMPMODE_A) -> Self { variant as u8 != 0 } } impl CTL1_SAMPMODE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_SAMPMODE_A { match self . bits { false => CTL1_SAMPMODE_A :: CTL1_SAMPMODE_AUTO , true => CTL1_SAMPMODE_A :: CTL1_SAMPMODE_MANUAL , } } # [doc = "AUTO"]
# [inline (always)]
pub fn is_ctl1_sampmode_auto (& self) -> bool { * self == CTL1_SAMPMODE_A :: CTL1_SAMPMODE_AUTO } # [doc = "MANUAL"]
# [inline (always)]
pub fn is_ctl1_sampmode_manual (& self) -> bool { * self == CTL1_SAMPMODE_A :: CTL1_SAMPMODE_MANUAL } } # [doc = "Field `CTL1_SAMPMODE` writer - Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger."]
pub type CTL1_SAMPMODE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL1_SAMPMODE_A > ; impl < 'a , REG , const O : u8 > CTL1_SAMPMODE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "AUTO"]
# [inline (always)]
pub fn ctl1_sampmode_auto (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SAMPMODE_A :: CTL1_SAMPMODE_AUTO) } # [doc = "MANUAL"]
# [inline (always)]
pub fn ctl1_sampmode_manual (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_SAMPMODE_A :: CTL1_SAMPMODE_MANUAL) } } # [doc = "Field `CTL1_AVGN` reader - Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx."]
pub type CTL1_AVGN_R = crate :: FieldReader < CTL1_AVGN_A > ; # [doc = "Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL1_AVGN_A { # [doc = "0: DISABLE"]
CTL1_AVGN_DISABLE = 0 , # [doc = "1: AVG_2"]
CTL1_AVGN_AVG_2 = 1 , # [doc = "2: AVG_4"]
CTL1_AVGN_AVG_4 = 2 , # [doc = "3: AVG_8"]
CTL1_AVGN_AVG_8 = 3 , # [doc = "4: AVG_16"]
CTL1_AVGN_AVG_16 = 4 , # [doc = "5: AVG_32"]
CTL1_AVGN_AVG_32 = 5 , # [doc = "6: AVG_64"]
CTL1_AVGN_AVG_64 = 6 , # [doc = "7: AVG_128"]
CTL1_AVGN_AVG_128 = 7 , } impl From < CTL1_AVGN_A > for u8 { # [inline (always)]
fn from (variant : CTL1_AVGN_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL1_AVGN_A { type Ux = u8 ; } impl CTL1_AVGN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_AVGN_A { match self . bits { 0 => CTL1_AVGN_A :: CTL1_AVGN_DISABLE , 1 => CTL1_AVGN_A :: CTL1_AVGN_AVG_2 , 2 => CTL1_AVGN_A :: CTL1_AVGN_AVG_4 , 3 => CTL1_AVGN_A :: CTL1_AVGN_AVG_8 , 4 => CTL1_AVGN_A :: CTL1_AVGN_AVG_16 , 5 => CTL1_AVGN_A :: CTL1_AVGN_AVG_32 , 6 => CTL1_AVGN_A :: CTL1_AVGN_AVG_64 , 7 => CTL1_AVGN_A :: CTL1_AVGN_AVG_128 , _ => unreachable ! () , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl1_avgn_disable (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_DISABLE } # [doc = "AVG_2"]
# [inline (always)]
pub fn is_ctl1_avgn_avg_2 (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_AVG_2 } # [doc = "AVG_4"]
# [inline (always)]
pub fn is_ctl1_avgn_avg_4 (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_AVG_4 } # [doc = "AVG_8"]
# [inline (always)]
pub fn is_ctl1_avgn_avg_8 (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_AVG_8 } # [doc = "AVG_16"]
# [inline (always)]
pub fn is_ctl1_avgn_avg_16 (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_AVG_16 } # [doc = "AVG_32"]
# [inline (always)]
pub fn is_ctl1_avgn_avg_32 (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_AVG_32 } # [doc = "AVG_64"]
# [inline (always)]
pub fn is_ctl1_avgn_avg_64 (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_AVG_64 } # [doc = "AVG_128"]
# [inline (always)]
pub fn is_ctl1_avgn_avg_128 (& self) -> bool { * self == CTL1_AVGN_A :: CTL1_AVGN_AVG_128 } } # [doc = "Field `CTL1_AVGN` writer - Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx."]
pub type CTL1_AVGN_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CTL1_AVGN_A > ; impl < 'a , REG , const O : u8 > CTL1_AVGN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl1_avgn_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_DISABLE) } # [doc = "AVG_2"]
# [inline (always)]
pub fn ctl1_avgn_avg_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_AVG_2) } # [doc = "AVG_4"]
# [inline (always)]
pub fn ctl1_avgn_avg_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_AVG_4) } # [doc = "AVG_8"]
# [inline (always)]
pub fn ctl1_avgn_avg_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_AVG_8) } # [doc = "AVG_16"]
# [inline (always)]
pub fn ctl1_avgn_avg_16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_AVG_16) } # [doc = "AVG_32"]
# [inline (always)]
pub fn ctl1_avgn_avg_32 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_AVG_32) } # [doc = "AVG_64"]
# [inline (always)]
pub fn ctl1_avgn_avg_64 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_AVG_64) } # [doc = "AVG_128"]
# [inline (always)]
pub fn ctl1_avgn_avg_128 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGN_A :: CTL1_AVGN_AVG_128) } } # [doc = "Field `CTL1_AVGD` reader - Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated."]
pub type CTL1_AVGD_R = crate :: FieldReader < CTL1_AVGD_A > ; # [doc = "Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL1_AVGD_A { # [doc = "0: SHIFT0"]
CTL1_AVGD_SHIFT0 = 0 , # [doc = "1: SHIFT1"]
CTL1_AVGD_SHIFT1 = 1 , # [doc = "2: SHIFT2"]
CTL1_AVGD_SHIFT2 = 2 , # [doc = "3: SHIFT3"]
CTL1_AVGD_SHIFT3 = 3 , # [doc = "4: SHIFT4"]
CTL1_AVGD_SHIFT4 = 4 , # [doc = "5: SHIFT5"]
CTL1_AVGD_SHIFT5 = 5 , # [doc = "6: SHIFT6"]
CTL1_AVGD_SHIFT6 = 6 , # [doc = "7: SHIFT7"]
CTL1_AVGD_SHIFT7 = 7 , } impl From < CTL1_AVGD_A > for u8 { # [inline (always)]
fn from (variant : CTL1_AVGD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL1_AVGD_A { type Ux = u8 ; } impl CTL1_AVGD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL1_AVGD_A { match self . bits { 0 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT0 , 1 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT1 , 2 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT2 , 3 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT3 , 4 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT4 , 5 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT5 , 6 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT6 , 7 => CTL1_AVGD_A :: CTL1_AVGD_SHIFT7 , _ => unreachable ! () , } } # [doc = "SHIFT0"]
# [inline (always)]
pub fn is_ctl1_avgd_shift0 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT0 } # [doc = "SHIFT1"]
# [inline (always)]
pub fn is_ctl1_avgd_shift1 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT1 } # [doc = "SHIFT2"]
# [inline (always)]
pub fn is_ctl1_avgd_shift2 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT2 } # [doc = "SHIFT3"]
# [inline (always)]
pub fn is_ctl1_avgd_shift3 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT3 } # [doc = "SHIFT4"]
# [inline (always)]
pub fn is_ctl1_avgd_shift4 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT4 } # [doc = "SHIFT5"]
# [inline (always)]
pub fn is_ctl1_avgd_shift5 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT5 } # [doc = "SHIFT6"]
# [inline (always)]
pub fn is_ctl1_avgd_shift6 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT6 } # [doc = "SHIFT7"]
# [inline (always)]
pub fn is_ctl1_avgd_shift7 (& self) -> bool { * self == CTL1_AVGD_A :: CTL1_AVGD_SHIFT7 } } # [doc = "Field `CTL1_AVGD` writer - Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated."]
pub type CTL1_AVGD_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CTL1_AVGD_A > ; impl < 'a , REG , const O : u8 > CTL1_AVGD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SHIFT0"]
# [inline (always)]
pub fn ctl1_avgd_shift0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT0) } # [doc = "SHIFT1"]
# [inline (always)]
pub fn ctl1_avgd_shift1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT1) } # [doc = "SHIFT2"]
# [inline (always)]
pub fn ctl1_avgd_shift2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT2) } # [doc = "SHIFT3"]
# [inline (always)]
pub fn ctl1_avgd_shift3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT3) } # [doc = "SHIFT4"]
# [inline (always)]
pub fn ctl1_avgd_shift4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT4) } # [doc = "SHIFT5"]
# [inline (always)]
pub fn ctl1_avgd_shift5 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT5) } # [doc = "SHIFT6"]
# [inline (always)]
pub fn ctl1_avgd_shift6 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT6) } # [doc = "SHIFT7"]
# [inline (always)]
pub fn ctl1_avgd_shift7 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL1_AVGD_A :: CTL1_AVGD_SHIFT7) } } impl R { # [doc = "Bit 0 - Sample trigger source"]
# [inline (always)]
pub fn ctl1_trigsrc (& self) -> CTL1_TRIGSRC_R { CTL1_TRIGSRC_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 8 - Start of conversion"]
# [inline (always)]
pub fn ctl1_sc (& self) -> CTL1_SC_R { CTL1_SC_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 16:17 - Conversion sequence mode"]
# [inline (always)]
pub fn ctl1_conseq (& self) -> CTL1_CONSEQ_R { CTL1_CONSEQ_R :: new (((self . bits >> 16) & 3) as u8) } # [doc = "Bit 20 - Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger."]
# [inline (always)]
pub fn ctl1_sampmode (& self) -> CTL1_SAMPMODE_R { CTL1_SAMPMODE_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bits 24:26 - Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx."]
# [inline (always)]
pub fn ctl1_avgn (& self) -> CTL1_AVGN_R { CTL1_AVGN_R :: new (((self . bits >> 24) & 7) as u8) } # [doc = "Bits 28:30 - Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated."]
# [inline (always)]
pub fn ctl1_avgd (& self) -> CTL1_AVGD_R { CTL1_AVGD_R :: new (((self . bits >> 28) & 7) as u8) } } impl W { # [doc = "Bit 0 - Sample trigger source"]
# [inline (always)]
# [must_use]
pub fn ctl1_trigsrc (& mut self) -> CTL1_TRIGSRC_W < CTL1_SPEC , 0 > { CTL1_TRIGSRC_W :: new (self) } # [doc = "Bit 8 - Start of conversion"]
# [inline (always)]
# [must_use]
pub fn ctl1_sc (& mut self) -> CTL1_SC_W < CTL1_SPEC , 8 > { CTL1_SC_W :: new (self) } # [doc = "Bits 16:17 - Conversion sequence mode"]
# [inline (always)]
# [must_use]
pub fn ctl1_conseq (& mut self) -> CTL1_CONSEQ_W < CTL1_SPEC , 16 > { CTL1_CONSEQ_W :: new (self) } # [doc = "Bit 20 - Sample mode. This bit selects the source of the sampling signal. MANUAL option is not valid when TRIGSRC is selected as hardware event trigger."]
# [inline (always)]
# [must_use]
pub fn ctl1_sampmode (& mut self) -> CTL1_SAMPMODE_W < CTL1_SPEC , 20 > { CTL1_SAMPMODE_W :: new (self) } # [doc = "Bits 24:26 - Hardware averager numerator. Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD. Result will be stored in MEMRESx."]
# [inline (always)]
# [must_use]
pub fn ctl1_avgn (& mut self) -> CTL1_AVGN_W < CTL1_SPEC , 24 > { CTL1_AVGN_W :: new (self) } # [doc = "Bits 28:30 - Hardware averager denominator. The number to divide the accumulated value by (this is a shift). Note result register is maximum of 16-bits long so if not shifted appropirately result will be truncated."]
# [inline (always)]
# [must_use]
pub fn ctl1_avgd (& mut self) -> CTL1_AVGD_W < CTL1_SPEC , 28 > { CTL1_AVGD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL1_SPEC ; impl crate :: RegisterSpec for CTL1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl1::R`](R) reader structure"]
impl crate :: Readable for CTL1_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl1::W`](W) writer structure"]
impl crate :: Writable for CTL1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL1 to value 0"]
impl crate :: Resettable for CTL1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL2 (rw) register accessor: Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl2::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl2`]
module"]
pub type CTL2 = crate :: Reg < ctl2 :: CTL2_SPEC > ; # [doc = "Control Register 2"]
pub mod ctl2 { # [doc = "Register `CTL2` reader"]
pub type R = crate :: R < CTL2_SPEC > ; # [doc = "Register `CTL2` writer"]
pub type W = crate :: W < CTL2_SPEC > ; # [doc = "Field `CTL2_DF` reader - Data read-back format. Data is always stored in binary unsigned format."]
pub type CTL2_DF_R = crate :: BitReader < CTL2_DF_A > ; # [doc = "Data read-back format. Data is always stored in binary unsigned format.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_DF_A { # [doc = "0: UNSIGNED"]
CTL2_DF_UNSIGNED = 0 , # [doc = "1: SIGNED"]
CTL2_DF_SIGNED = 1 , } impl From < CTL2_DF_A > for bool { # [inline (always)]
fn from (variant : CTL2_DF_A) -> Self { variant as u8 != 0 } } impl CTL2_DF_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_DF_A { match self . bits { false => CTL2_DF_A :: CTL2_DF_UNSIGNED , true => CTL2_DF_A :: CTL2_DF_SIGNED , } } # [doc = "UNSIGNED"]
# [inline (always)]
pub fn is_ctl2_df_unsigned (& self) -> bool { * self == CTL2_DF_A :: CTL2_DF_UNSIGNED } # [doc = "SIGNED"]
# [inline (always)]
pub fn is_ctl2_df_signed (& self) -> bool { * self == CTL2_DF_A :: CTL2_DF_SIGNED } } # [doc = "Field `CTL2_DF` writer - Data read-back format. Data is always stored in binary unsigned format."]
pub type CTL2_DF_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_DF_A > ; impl < 'a , REG , const O : u8 > CTL2_DF_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "UNSIGNED"]
# [inline (always)]
pub fn ctl2_df_unsigned (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DF_A :: CTL2_DF_UNSIGNED) } # [doc = "SIGNED"]
# [inline (always)]
pub fn ctl2_df_signed (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DF_A :: CTL2_DF_SIGNED) } } # [doc = "Field `CTL2_RES` reader - Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution."]
pub type CTL2_RES_R = crate :: FieldReader < CTL2_RES_A > ; # [doc = "Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL2_RES_A { # [doc = "0: BIT_12"]
CTL2_RES_BIT_12 = 0 , # [doc = "1: BIT_10"]
CTL2_RES_BIT_10 = 1 , # [doc = "2: BIT_8"]
CTL2_RES_BIT_8 = 2 , } impl From < CTL2_RES_A > for u8 { # [inline (always)]
fn from (variant : CTL2_RES_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL2_RES_A { type Ux = u8 ; } impl CTL2_RES_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL2_RES_A > { match self . bits { 0 => Some (CTL2_RES_A :: CTL2_RES_BIT_12) , 1 => Some (CTL2_RES_A :: CTL2_RES_BIT_10) , 2 => Some (CTL2_RES_A :: CTL2_RES_BIT_8) , _ => None , } } # [doc = "BIT_12"]
# [inline (always)]
pub fn is_ctl2_res_bit_12 (& self) -> bool { * self == CTL2_RES_A :: CTL2_RES_BIT_12 } # [doc = "BIT_10"]
# [inline (always)]
pub fn is_ctl2_res_bit_10 (& self) -> bool { * self == CTL2_RES_A :: CTL2_RES_BIT_10 } # [doc = "BIT_8"]
# [inline (always)]
pub fn is_ctl2_res_bit_8 (& self) -> bool { * self == CTL2_RES_A :: CTL2_RES_BIT_8 } } # [doc = "Field `CTL2_RES` writer - Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution."]
pub type CTL2_RES_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTL2_RES_A > ; impl < 'a , REG , const O : u8 > CTL2_RES_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "BIT_12"]
# [inline (always)]
pub fn ctl2_res_bit_12 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_RES_A :: CTL2_RES_BIT_12) } # [doc = "BIT_10"]
# [inline (always)]
pub fn ctl2_res_bit_10 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_RES_A :: CTL2_RES_BIT_10) } # [doc = "BIT_8"]
# [inline (always)]
pub fn ctl2_res_bit_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_RES_A :: CTL2_RES_BIT_8) } } # [doc = "Field `CTL2_DMAEN` reader - Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers."]
pub type CTL2_DMAEN_R = crate :: BitReader < CTL2_DMAEN_A > ; # [doc = "Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_DMAEN_A { # [doc = "0: DISABLE"]
CTL2_DMAEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL2_DMAEN_ENABLE = 1 , } impl From < CTL2_DMAEN_A > for bool { # [inline (always)]
fn from (variant : CTL2_DMAEN_A) -> Self { variant as u8 != 0 } } impl CTL2_DMAEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_DMAEN_A { match self . bits { false => CTL2_DMAEN_A :: CTL2_DMAEN_DISABLE , true => CTL2_DMAEN_A :: CTL2_DMAEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl2_dmaen_disable (& self) -> bool { * self == CTL2_DMAEN_A :: CTL2_DMAEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl2_dmaen_enable (& self) -> bool { * self == CTL2_DMAEN_A :: CTL2_DMAEN_ENABLE } } # [doc = "Field `CTL2_DMAEN` writer - Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers."]
pub type CTL2_DMAEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_DMAEN_A > ; impl < 'a , REG , const O : u8 > CTL2_DMAEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl2_dmaen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DMAEN_A :: CTL2_DMAEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl2_dmaen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_DMAEN_A :: CTL2_DMAEN_ENABLE) } } # [doc = "Field `CTL2_FIFOEN` reader - Enable FIFO based operation"]
pub type CTL2_FIFOEN_R = crate :: BitReader < CTL2_FIFOEN_A > ; # [doc = "Enable FIFO based operation\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTL2_FIFOEN_A { # [doc = "0: DISABLE"]
CTL2_FIFOEN_DISABLE = 0 , # [doc = "1: ENABLE"]
CTL2_FIFOEN_ENABLE = 1 , } impl From < CTL2_FIFOEN_A > for bool { # [inline (always)]
fn from (variant : CTL2_FIFOEN_A) -> Self { variant as u8 != 0 } } impl CTL2_FIFOEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTL2_FIFOEN_A { match self . bits { false => CTL2_FIFOEN_A :: CTL2_FIFOEN_DISABLE , true => CTL2_FIFOEN_A :: CTL2_FIFOEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_ctl2_fifoen_disable (& self) -> bool { * self == CTL2_FIFOEN_A :: CTL2_FIFOEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_ctl2_fifoen_enable (& self) -> bool { * self == CTL2_FIFOEN_A :: CTL2_FIFOEN_ENABLE } } # [doc = "Field `CTL2_FIFOEN` writer - Enable FIFO based operation"]
pub type CTL2_FIFOEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTL2_FIFOEN_A > ; impl < 'a , REG , const O : u8 > CTL2_FIFOEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn ctl2_fifoen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_FIFOEN_A :: CTL2_FIFOEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn ctl2_fifoen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_FIFOEN_A :: CTL2_FIFOEN_ENABLE) } } # [doc = "Field `CTL2_SAMPCNT` reader - Number of ADC converted samples to be transferred on a DMA trigger"]
pub type CTL2_SAMPCNT_R = crate :: FieldReader < CTL2_SAMPCNT_A > ; # [doc = "Number of ADC converted samples to be transferred on a DMA trigger\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL2_SAMPCNT_A { # [doc = "0: MIN"]
CTL2_SAMPCNT_MIN = 0 , # [doc = "24: MAX"]
CTL2_SAMPCNT_MAX = 24 , } impl From < CTL2_SAMPCNT_A > for u8 { # [inline (always)]
fn from (variant : CTL2_SAMPCNT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL2_SAMPCNT_A { type Ux = u8 ; } impl CTL2_SAMPCNT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL2_SAMPCNT_A > { match self . bits { 0 => Some (CTL2_SAMPCNT_A :: CTL2_SAMPCNT_MIN) , 24 => Some (CTL2_SAMPCNT_A :: CTL2_SAMPCNT_MAX) , _ => None , } } # [doc = "MIN"]
# [inline (always)]
pub fn is_ctl2_sampcnt_min (& self) -> bool { * self == CTL2_SAMPCNT_A :: CTL2_SAMPCNT_MIN } # [doc = "MAX"]
# [inline (always)]
pub fn is_ctl2_sampcnt_max (& self) -> bool { * self == CTL2_SAMPCNT_A :: CTL2_SAMPCNT_MAX } } # [doc = "Field `CTL2_SAMPCNT` writer - Number of ADC converted samples to be transferred on a DMA trigger"]
pub type CTL2_SAMPCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , CTL2_SAMPCNT_A > ; impl < 'a , REG , const O : u8 > CTL2_SAMPCNT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "MIN"]
# [inline (always)]
pub fn ctl2_sampcnt_min (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_SAMPCNT_A :: CTL2_SAMPCNT_MIN) } # [doc = "MAX"]
# [inline (always)]
pub fn ctl2_sampcnt_max (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_SAMPCNT_A :: CTL2_SAMPCNT_MAX) } } # [doc = "Field `CTL2_STARTADD` reader - Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
pub type CTL2_STARTADD_R = crate :: FieldReader < CTL2_STARTADD_A > ; # [doc = "Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL2_STARTADD_A { # [doc = "0: ADDR_00"]
CTL2_STARTADD_ADDR_00 = 0 , # [doc = "1: ADDR_01"]
CTL2_STARTADD_ADDR_01 = 1 , # [doc = "2: ADDR_02"]
CTL2_STARTADD_ADDR_02 = 2 , # [doc = "3: ADDR_03"]
CTL2_STARTADD_ADDR_03 = 3 , # [doc = "4: ADDR_04"]
CTL2_STARTADD_ADDR_04 = 4 , # [doc = "5: ADDR_05"]
CTL2_STARTADD_ADDR_05 = 5 , # [doc = "6: ADDR_06"]
CTL2_STARTADD_ADDR_06 = 6 , # [doc = "7: ADDR_07"]
CTL2_STARTADD_ADDR_07 = 7 , # [doc = "8: ADDR_08"]
CTL2_STARTADD_ADDR_08 = 8 , # [doc = "9: ADDR_09"]
CTL2_STARTADD_ADDR_09 = 9 , # [doc = "10: ADDR_10"]
CTL2_STARTADD_ADDR_10 = 10 , # [doc = "11: ADDR_11"]
CTL2_STARTADD_ADDR_11 = 11 , # [doc = "12: ADDR_12"]
CTL2_STARTADD_ADDR_12 = 12 , # [doc = "13: ADDR_13"]
CTL2_STARTADD_ADDR_13 = 13 , # [doc = "14: ADDR_14"]
CTL2_STARTADD_ADDR_14 = 14 , # [doc = "15: ADDR_15"]
CTL2_STARTADD_ADDR_15 = 15 , # [doc = "16: ADDR_16"]
CTL2_STARTADD_ADDR_16 = 16 , # [doc = "17: ADDR_17"]
CTL2_STARTADD_ADDR_17 = 17 , # [doc = "18: ADDR_18"]
CTL2_STARTADD_ADDR_18 = 18 , # [doc = "19: ADDR_19"]
CTL2_STARTADD_ADDR_19 = 19 , # [doc = "20: ADDR_20"]
CTL2_STARTADD_ADDR_20 = 20 , # [doc = "21: ADDR_21"]
CTL2_STARTADD_ADDR_21 = 21 , # [doc = "22: ADDR_22"]
CTL2_STARTADD_ADDR_22 = 22 , # [doc = "23: ADDR_23"]
CTL2_STARTADD_ADDR_23 = 23 , } impl From < CTL2_STARTADD_A > for u8 { # [inline (always)]
fn from (variant : CTL2_STARTADD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL2_STARTADD_A { type Ux = u8 ; } impl CTL2_STARTADD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL2_STARTADD_A > { match self . bits { 0 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_00) , 1 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_01) , 2 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_02) , 3 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_03) , 4 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_04) , 5 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_05) , 6 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_06) , 7 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_07) , 8 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_08) , 9 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_09) , 10 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_10) , 11 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_11) , 12 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_12) , 13 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_13) , 14 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_14) , 15 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_15) , 16 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_16) , 17 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_17) , 18 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_18) , 19 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_19) , 20 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_20) , 21 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_21) , 22 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_22) , 23 => Some (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_23) , _ => None , } } # [doc = "ADDR_00"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_00 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_00 } # [doc = "ADDR_01"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_01 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_01 } # [doc = "ADDR_02"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_02 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_02 } # [doc = "ADDR_03"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_03 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_03 } # [doc = "ADDR_04"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_04 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_04 } # [doc = "ADDR_05"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_05 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_05 } # [doc = "ADDR_06"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_06 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_06 } # [doc = "ADDR_07"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_07 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_07 } # [doc = "ADDR_08"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_08 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_08 } # [doc = "ADDR_09"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_09 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_09 } # [doc = "ADDR_10"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_10 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_10 } # [doc = "ADDR_11"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_11 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_11 } # [doc = "ADDR_12"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_12 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_12 } # [doc = "ADDR_13"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_13 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_13 } # [doc = "ADDR_14"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_14 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_14 } # [doc = "ADDR_15"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_15 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_15 } # [doc = "ADDR_16"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_16 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_16 } # [doc = "ADDR_17"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_17 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_17 } # [doc = "ADDR_18"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_18 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_18 } # [doc = "ADDR_19"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_19 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_19 } # [doc = "ADDR_20"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_20 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_20 } # [doc = "ADDR_21"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_21 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_21 } # [doc = "ADDR_22"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_22 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_22 } # [doc = "ADDR_23"]
# [inline (always)]
pub fn is_ctl2_startadd_addr_23 (& self) -> bool { * self == CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_23 } } # [doc = "Field `CTL2_STARTADD` writer - Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
pub type CTL2_STARTADD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , CTL2_STARTADD_A > ; impl < 'a , REG , const O : u8 > CTL2_STARTADD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ADDR_00"]
# [inline (always)]
pub fn ctl2_startadd_addr_00 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_00) } # [doc = "ADDR_01"]
# [inline (always)]
pub fn ctl2_startadd_addr_01 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_01) } # [doc = "ADDR_02"]
# [inline (always)]
pub fn ctl2_startadd_addr_02 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_02) } # [doc = "ADDR_03"]
# [inline (always)]
pub fn ctl2_startadd_addr_03 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_03) } # [doc = "ADDR_04"]
# [inline (always)]
pub fn ctl2_startadd_addr_04 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_04) } # [doc = "ADDR_05"]
# [inline (always)]
pub fn ctl2_startadd_addr_05 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_05) } # [doc = "ADDR_06"]
# [inline (always)]
pub fn ctl2_startadd_addr_06 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_06) } # [doc = "ADDR_07"]
# [inline (always)]
pub fn ctl2_startadd_addr_07 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_07) } # [doc = "ADDR_08"]
# [inline (always)]
pub fn ctl2_startadd_addr_08 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_08) } # [doc = "ADDR_09"]
# [inline (always)]
pub fn ctl2_startadd_addr_09 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_09) } # [doc = "ADDR_10"]
# [inline (always)]
pub fn ctl2_startadd_addr_10 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_10) } # [doc = "ADDR_11"]
# [inline (always)]
pub fn ctl2_startadd_addr_11 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_11) } # [doc = "ADDR_12"]
# [inline (always)]
pub fn ctl2_startadd_addr_12 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_12) } # [doc = "ADDR_13"]
# [inline (always)]
pub fn ctl2_startadd_addr_13 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_13) } # [doc = "ADDR_14"]
# [inline (always)]
pub fn ctl2_startadd_addr_14 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_14) } # [doc = "ADDR_15"]
# [inline (always)]
pub fn ctl2_startadd_addr_15 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_15) } # [doc = "ADDR_16"]
# [inline (always)]
pub fn ctl2_startadd_addr_16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_16) } # [doc = "ADDR_17"]
# [inline (always)]
pub fn ctl2_startadd_addr_17 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_17) } # [doc = "ADDR_18"]
# [inline (always)]
pub fn ctl2_startadd_addr_18 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_18) } # [doc = "ADDR_19"]
# [inline (always)]
pub fn ctl2_startadd_addr_19 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_19) } # [doc = "ADDR_20"]
# [inline (always)]
pub fn ctl2_startadd_addr_20 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_20) } # [doc = "ADDR_21"]
# [inline (always)]
pub fn ctl2_startadd_addr_21 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_21) } # [doc = "ADDR_22"]
# [inline (always)]
pub fn ctl2_startadd_addr_22 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_22) } # [doc = "ADDR_23"]
# [inline (always)]
pub fn ctl2_startadd_addr_23 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_STARTADD_A :: CTL2_STARTADD_ADDR_23) } } # [doc = "Field `CTL2_ENDADD` reader - Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
pub type CTL2_ENDADD_R = crate :: FieldReader < CTL2_ENDADD_A > ; # [doc = "Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTL2_ENDADD_A { # [doc = "0: ADDR_00"]
CTL2_ENDADD_ADDR_00 = 0 , # [doc = "1: ADDR_01"]
CTL2_ENDADD_ADDR_01 = 1 , # [doc = "2: ADDR_02"]
CTL2_ENDADD_ADDR_02 = 2 , # [doc = "3: ADDR_03"]
CTL2_ENDADD_ADDR_03 = 3 , # [doc = "4: ADDR_04"]
CTL2_ENDADD_ADDR_04 = 4 , # [doc = "5: ADDR_05"]
CTL2_ENDADD_ADDR_05 = 5 , # [doc = "6: ADDR_06"]
CTL2_ENDADD_ADDR_06 = 6 , # [doc = "7: ADDR_07"]
CTL2_ENDADD_ADDR_07 = 7 , # [doc = "8: ADDR_08"]
CTL2_ENDADD_ADDR_08 = 8 , # [doc = "9: ADDR_09"]
CTL2_ENDADD_ADDR_09 = 9 , # [doc = "10: ADDR_10"]
CTL2_ENDADD_ADDR_10 = 10 , # [doc = "11: ADDR_11"]
CTL2_ENDADD_ADDR_11 = 11 , # [doc = "12: ADDR_12"]
CTL2_ENDADD_ADDR_12 = 12 , # [doc = "13: ADDR_13"]
CTL2_ENDADD_ADDR_13 = 13 , # [doc = "14: ADDR_14"]
CTL2_ENDADD_ADDR_14 = 14 , # [doc = "15: ADDR_15"]
CTL2_ENDADD_ADDR_15 = 15 , # [doc = "16: ADDR_16"]
CTL2_ENDADD_ADDR_16 = 16 , # [doc = "17: ADDR_17"]
CTL2_ENDADD_ADDR_17 = 17 , # [doc = "18: ADDR_18"]
CTL2_ENDADD_ADDR_18 = 18 , # [doc = "19: ADDR_19"]
CTL2_ENDADD_ADDR_19 = 19 , # [doc = "20: ADDR_20"]
CTL2_ENDADD_ADDR_20 = 20 , # [doc = "21: ADDR_21"]
CTL2_ENDADD_ADDR_21 = 21 , # [doc = "22: ADDR_22"]
CTL2_ENDADD_ADDR_22 = 22 , # [doc = "23: ADDR_23"]
CTL2_ENDADD_ADDR_23 = 23 , } impl From < CTL2_ENDADD_A > for u8 { # [inline (always)]
fn from (variant : CTL2_ENDADD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTL2_ENDADD_A { type Ux = u8 ; } impl CTL2_ENDADD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTL2_ENDADD_A > { match self . bits { 0 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_00) , 1 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_01) , 2 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_02) , 3 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_03) , 4 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_04) , 5 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_05) , 6 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_06) , 7 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_07) , 8 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_08) , 9 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_09) , 10 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_10) , 11 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_11) , 12 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_12) , 13 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_13) , 14 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_14) , 15 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_15) , 16 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_16) , 17 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_17) , 18 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_18) , 19 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_19) , 20 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_20) , 21 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_21) , 22 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_22) , 23 => Some (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_23) , _ => None , } } # [doc = "ADDR_00"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_00 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_00 } # [doc = "ADDR_01"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_01 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_01 } # [doc = "ADDR_02"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_02 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_02 } # [doc = "ADDR_03"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_03 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_03 } # [doc = "ADDR_04"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_04 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_04 } # [doc = "ADDR_05"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_05 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_05 } # [doc = "ADDR_06"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_06 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_06 } # [doc = "ADDR_07"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_07 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_07 } # [doc = "ADDR_08"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_08 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_08 } # [doc = "ADDR_09"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_09 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_09 } # [doc = "ADDR_10"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_10 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_10 } # [doc = "ADDR_11"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_11 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_11 } # [doc = "ADDR_12"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_12 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_12 } # [doc = "ADDR_13"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_13 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_13 } # [doc = "ADDR_14"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_14 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_14 } # [doc = "ADDR_15"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_15 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_15 } # [doc = "ADDR_16"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_16 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_16 } # [doc = "ADDR_17"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_17 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_17 } # [doc = "ADDR_18"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_18 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_18 } # [doc = "ADDR_19"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_19 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_19 } # [doc = "ADDR_20"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_20 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_20 } # [doc = "ADDR_21"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_21 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_21 } # [doc = "ADDR_22"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_22 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_22 } # [doc = "ADDR_23"]
# [inline (always)]
pub fn is_ctl2_endadd_addr_23 (& self) -> bool { * self == CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_23 } } # [doc = "Field `CTL2_ENDADD` writer - Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
pub type CTL2_ENDADD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , CTL2_ENDADD_A > ; impl < 'a , REG , const O : u8 > CTL2_ENDADD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "ADDR_00"]
# [inline (always)]
pub fn ctl2_endadd_addr_00 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_00) } # [doc = "ADDR_01"]
# [inline (always)]
pub fn ctl2_endadd_addr_01 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_01) } # [doc = "ADDR_02"]
# [inline (always)]
pub fn ctl2_endadd_addr_02 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_02) } # [doc = "ADDR_03"]
# [inline (always)]
pub fn ctl2_endadd_addr_03 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_03) } # [doc = "ADDR_04"]
# [inline (always)]
pub fn ctl2_endadd_addr_04 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_04) } # [doc = "ADDR_05"]
# [inline (always)]
pub fn ctl2_endadd_addr_05 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_05) } # [doc = "ADDR_06"]
# [inline (always)]
pub fn ctl2_endadd_addr_06 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_06) } # [doc = "ADDR_07"]
# [inline (always)]
pub fn ctl2_endadd_addr_07 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_07) } # [doc = "ADDR_08"]
# [inline (always)]
pub fn ctl2_endadd_addr_08 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_08) } # [doc = "ADDR_09"]
# [inline (always)]
pub fn ctl2_endadd_addr_09 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_09) } # [doc = "ADDR_10"]
# [inline (always)]
pub fn ctl2_endadd_addr_10 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_10) } # [doc = "ADDR_11"]
# [inline (always)]
pub fn ctl2_endadd_addr_11 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_11) } # [doc = "ADDR_12"]
# [inline (always)]
pub fn ctl2_endadd_addr_12 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_12) } # [doc = "ADDR_13"]
# [inline (always)]
pub fn ctl2_endadd_addr_13 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_13) } # [doc = "ADDR_14"]
# [inline (always)]
pub fn ctl2_endadd_addr_14 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_14) } # [doc = "ADDR_15"]
# [inline (always)]
pub fn ctl2_endadd_addr_15 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_15) } # [doc = "ADDR_16"]
# [inline (always)]
pub fn ctl2_endadd_addr_16 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_16) } # [doc = "ADDR_17"]
# [inline (always)]
pub fn ctl2_endadd_addr_17 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_17) } # [doc = "ADDR_18"]
# [inline (always)]
pub fn ctl2_endadd_addr_18 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_18) } # [doc = "ADDR_19"]
# [inline (always)]
pub fn ctl2_endadd_addr_19 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_19) } # [doc = "ADDR_20"]
# [inline (always)]
pub fn ctl2_endadd_addr_20 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_20) } # [doc = "ADDR_21"]
# [inline (always)]
pub fn ctl2_endadd_addr_21 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_21) } # [doc = "ADDR_22"]
# [inline (always)]
pub fn ctl2_endadd_addr_22 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_22) } # [doc = "ADDR_23"]
# [inline (always)]
pub fn ctl2_endadd_addr_23 (self) -> & 'a mut crate :: W < REG > { self . variant (CTL2_ENDADD_A :: CTL2_ENDADD_ADDR_23) } } impl R { # [doc = "Bit 0 - Data read-back format. Data is always stored in binary unsigned format."]
# [inline (always)]
pub fn ctl2_df (& self) -> CTL2_DF_R { CTL2_DF_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:2 - Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution."]
# [inline (always)]
pub fn ctl2_res (& self) -> CTL2_RES_R { CTL2_RES_R :: new (((self . bits >> 1) & 3) as u8) } # [doc = "Bit 8 - Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers."]
# [inline (always)]
pub fn ctl2_dmaen (& self) -> CTL2_DMAEN_R { CTL2_DMAEN_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 10 - Enable FIFO based operation"]
# [inline (always)]
pub fn ctl2_fifoen (& self) -> CTL2_FIFOEN_R { CTL2_FIFOEN_R :: new (((self . bits >> 10) & 1) != 0) } # [doc = "Bits 11:15 - Number of ADC converted samples to be transferred on a DMA trigger"]
# [inline (always)]
pub fn ctl2_sampcnt (& self) -> CTL2_SAMPCNT_R { CTL2_SAMPCNT_R :: new (((self . bits >> 11) & 0x1f) as u8) } # [doc = "Bits 16:20 - Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
# [inline (always)]
pub fn ctl2_startadd (& self) -> CTL2_STARTADD_R { CTL2_STARTADD_R :: new (((self . bits >> 16) & 0x1f) as u8) } # [doc = "Bits 24:28 - Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
# [inline (always)]
pub fn ctl2_endadd (& self) -> CTL2_ENDADD_R { CTL2_ENDADD_R :: new (((self . bits >> 24) & 0x1f) as u8) } } impl W { # [doc = "Bit 0 - Data read-back format. Data is always stored in binary unsigned format."]
# [inline (always)]
# [must_use]
pub fn ctl2_df (& mut self) -> CTL2_DF_W < CTL2_SPEC , 0 > { CTL2_DF_W :: new (self) } # [doc = "Bits 1:2 - Resolution. These bits define the resolutoin of ADC conversion result. Note : A value of 3 defaults to 12-bits resolution."]
# [inline (always)]
# [must_use]
pub fn ctl2_res (& mut self) -> CTL2_RES_W < CTL2_SPEC , 1 > { CTL2_RES_W :: new (self) } # [doc = "Bit 8 - Enable DMA trigger for data transfer. Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers."]
# [inline (always)]
# [must_use]
pub fn ctl2_dmaen (& mut self) -> CTL2_DMAEN_W < CTL2_SPEC , 8 > { CTL2_DMAEN_W :: new (self) } # [doc = "Bit 10 - Enable FIFO based operation"]
# [inline (always)]
# [must_use]
pub fn ctl2_fifoen (& mut self) -> CTL2_FIFOEN_W < CTL2_SPEC , 10 > { CTL2_FIFOEN_W :: new (self) } # [doc = "Bits 11:15 - Number of ADC converted samples to be transferred on a DMA trigger"]
# [inline (always)]
# [must_use]
pub fn ctl2_sampcnt (& mut self) -> CTL2_SAMPCNT_W < CTL2_SPEC , 11 > { CTL2_SAMPCNT_W :: new (self) } # [doc = "Bits 16:20 - Sequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode. The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
# [inline (always)]
# [must_use]
pub fn ctl2_startadd (& mut self) -> CTL2_STARTADD_W < CTL2_SPEC , 16 > { CTL2_STARTADD_W :: new (self) } # [doc = "Bits 24:28 - Sequence end address. These bits select which MEMCTLx is the last one for the sequence mode. The value of ENDADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23."]
# [inline (always)]
# [must_use]
pub fn ctl2_endadd (& mut self) -> CTL2_ENDADD_W < CTL2_SPEC , 24 > { CTL2_ENDADD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL2_SPEC ; impl crate :: RegisterSpec for CTL2_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl2::R`](R) reader structure"]
impl crate :: Readable for CTL2_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl2::W`](W) writer structure"]
impl crate :: Writable for CTL2_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL2 to value 0"]
impl crate :: Resettable for CTL2_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKFREQ (rw) register accessor: Sample Clock Frequency Range Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkfreq::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkfreq::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkfreq`]
module"]
pub type CLKFREQ = crate :: Reg < clkfreq :: CLKFREQ_SPEC > ; # [doc = "Sample Clock Frequency Range Register"]
pub mod clkfreq { # [doc = "Register `CLKFREQ` reader"]
pub type R = crate :: R < CLKFREQ_SPEC > ; # [doc = "Register `CLKFREQ` writer"]
pub type W = crate :: W < CLKFREQ_SPEC > ; # [doc = "Field `CLKFREQ_FRANGE` reader - Frequency Range."]
pub type CLKFREQ_FRANGE_R = crate :: FieldReader < CLKFREQ_FRANGE_A > ; # [doc = "Frequency Range.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKFREQ_FRANGE_A { # [doc = "0: RANGE1TO4"]
CLKFREQ_FRANGE_RANGE1TO4 = 0 , # [doc = "1: RANGE4TO8"]
CLKFREQ_FRANGE_RANGE4TO8 = 1 , # [doc = "2: RANGE8TO16"]
CLKFREQ_FRANGE_RANGE8TO16 = 2 , # [doc = "3: RANGE16TO20"]
CLKFREQ_FRANGE_RANGE16TO20 = 3 , # [doc = "4: RANGE20TO24"]
CLKFREQ_FRANGE_RANGE20TO24 = 4 , # [doc = "5: RANGE24TO32"]
CLKFREQ_FRANGE_RANGE24TO32 = 5 , # [doc = "6: RANGE32TO40"]
CLKFREQ_FRANGE_RANGE32TO40 = 6 , # [doc = "7: RANGE40TO48"]
CLKFREQ_FRANGE_RANGE40TO48 = 7 , } impl From < CLKFREQ_FRANGE_A > for u8 { # [inline (always)]
fn from (variant : CLKFREQ_FRANGE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKFREQ_FRANGE_A { type Ux = u8 ; } impl CLKFREQ_FRANGE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKFREQ_FRANGE_A { match self . bits { 0 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE1TO4 , 1 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE4TO8 , 2 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE8TO16 , 3 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE16TO20 , 4 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE20TO24 , 5 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE24TO32 , 6 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE32TO40 , 7 => CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE40TO48 , _ => unreachable ! () , } } # [doc = "RANGE1TO4"]
# [inline (always)]
pub fn is_clkfreq_frange_range1to4 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE1TO4 } # [doc = "RANGE4TO8"]
# [inline (always)]
pub fn is_clkfreq_frange_range4to8 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE4TO8 } # [doc = "RANGE8TO16"]
# [inline (always)]
pub fn is_clkfreq_frange_range8to16 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE8TO16 } # [doc = "RANGE16TO20"]
# [inline (always)]
pub fn is_clkfreq_frange_range16to20 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE16TO20 } # [doc = "RANGE20TO24"]
# [inline (always)]
pub fn is_clkfreq_frange_range20to24 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE20TO24 } # [doc = "RANGE24TO32"]
# [inline (always)]
pub fn is_clkfreq_frange_range24to32 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE24TO32 } # [doc = "RANGE32TO40"]
# [inline (always)]
pub fn is_clkfreq_frange_range32to40 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE32TO40 } # [doc = "RANGE40TO48"]
# [inline (always)]
pub fn is_clkfreq_frange_range40to48 (& self) -> bool { * self == CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE40TO48 } } # [doc = "Field `CLKFREQ_FRANGE` writer - Frequency Range."]
pub type CLKFREQ_FRANGE_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKFREQ_FRANGE_A > ; impl < 'a , REG , const O : u8 > CLKFREQ_FRANGE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "RANGE1TO4"]
# [inline (always)]
pub fn clkfreq_frange_range1to4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE1TO4) } # [doc = "RANGE4TO8"]
# [inline (always)]
pub fn clkfreq_frange_range4to8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE4TO8) } # [doc = "RANGE8TO16"]
# [inline (always)]
pub fn clkfreq_frange_range8to16 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE8TO16) } # [doc = "RANGE16TO20"]
# [inline (always)]
pub fn clkfreq_frange_range16to20 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE16TO20) } # [doc = "RANGE20TO24"]
# [inline (always)]
pub fn clkfreq_frange_range20to24 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE20TO24) } # [doc = "RANGE24TO32"]
# [inline (always)]
pub fn clkfreq_frange_range24to32 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE24TO32) } # [doc = "RANGE32TO40"]
# [inline (always)]
pub fn clkfreq_frange_range32to40 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE32TO40) } # [doc = "RANGE40TO48"]
# [inline (always)]
pub fn clkfreq_frange_range40to48 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKFREQ_FRANGE_A :: CLKFREQ_FRANGE_RANGE40TO48) } } impl R { # [doc = "Bits 0:2 - Frequency Range."]
# [inline (always)]
pub fn clkfreq_frange (& self) -> CLKFREQ_FRANGE_R { CLKFREQ_FRANGE_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Frequency Range."]
# [inline (always)]
# [must_use]
pub fn clkfreq_frange (& mut self) -> CLKFREQ_FRANGE_W < CLKFREQ_SPEC , 0 > { CLKFREQ_FRANGE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Sample Clock Frequency Range Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkfreq::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkfreq::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKFREQ_SPEC ; impl crate :: RegisterSpec for CLKFREQ_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkfreq::R`](R) reader structure"]
impl crate :: Readable for CLKFREQ_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkfreq::W`](W) writer structure"]
impl crate :: Writable for CLKFREQ_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKFREQ to value 0"]
impl crate :: Resettable for CLKFREQ_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTL3 (rw) register accessor: Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl3::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl3::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctl3`]
module"]
pub type CTL3 = crate :: Reg < ctl3 :: CTL3_SPEC > ; # [doc = "Control Register 3"]
pub mod ctl3 { # [doc = "Register `CTL3` reader"]
pub type R = crate :: R < CTL3_SPEC > ; # [doc = "Register `CTL3` writer"]
pub type W = crate :: W < CTL3_SPEC > ; # [doc = "Field `CTL3_ASCCHSEL` reader - ASC channel select."]
pub type CTL3_ASCCHSEL_R = crate :: FieldReader ; # [doc = "Field `CTL3_ASCCHSEL` writer - ASC channel select."]
pub type CTL3_ASCCHSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O > ; # [doc = "Field `CTL3_ASCSTIME` reader - ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation."]
pub type CTL3_ASCSTIME_R = crate :: BitReader ; # [doc = "Field `CTL3_ASCSTIME` writer - ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation."]
pub type CTL3_ASCSTIME_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `CTL3_ASCVRSEL` reader - Selects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected."]
pub type CTL3_ASCVRSEL_R = crate :: FieldReader ; # [doc = "Field `CTL3_ASCVRSEL` writer - Selects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected."]
pub type CTL3_ASCVRSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O > ; impl R { # [doc = "Bits 0:4 - ASC channel select."]
# [inline (always)]
pub fn ctl3_ascchsel (& self) -> CTL3_ASCCHSEL_R { CTL3_ASCCHSEL_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bit 8 - ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation."]
# [inline (always)]
pub fn ctl3_ascstime (& self) -> CTL3_ASCSTIME_R { CTL3_ASCSTIME_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bits 12:13 - Selects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected."]
# [inline (always)]
pub fn ctl3_ascvrsel (& self) -> CTL3_ASCVRSEL_R { CTL3_ASCVRSEL_R :: new (((self . bits >> 12) & 3) as u8) } } impl W { # [doc = "Bits 0:4 - ASC channel select."]
# [inline (always)]
# [must_use]
pub fn ctl3_ascchsel (& mut self) -> CTL3_ASCCHSEL_W < CTL3_SPEC , 0 > { CTL3_ASCCHSEL_W :: new (self) } # [doc = "Bit 8 - ASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation."]
# [inline (always)]
# [must_use]
pub fn ctl3_ascstime (& mut self) -> CTL3_ASCSTIME_W < CTL3_SPEC , 8 > { CTL3_ASCSTIME_W :: new (self) } # [doc = "Bits 12:13 - Selects voltage reference for ASC operation. VEREFM must be connected to on-board ground when external reference option is selected."]
# [inline (always)]
# [must_use]
pub fn ctl3_ascvrsel (& mut self) -> CTL3_ASCVRSEL_W < CTL3_SPEC , 12 > { CTL3_ASCVRSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Control Register 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctl3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctl3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTL3_SPEC ; impl crate :: RegisterSpec for CTL3_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctl3::R`](R) reader structure"]
impl crate :: Readable for CTL3_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctl3::W`](W) writer structure"]
impl crate :: Writable for CTL3_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTL3 to value 0"]
impl crate :: Resettable for CTL3_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SCOMP0 (rw) register accessor: Sample Time Compare 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scomp0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scomp0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scomp0`]
module"]
pub type SCOMP0 = crate :: Reg < scomp0 :: SCOMP0_SPEC > ; # [doc = "Sample Time Compare 0 Register"]
pub mod scomp0 { # [doc = "Register `SCOMP0` reader"]
pub type R = crate :: R < SCOMP0_SPEC > ; # [doc = "Register `SCOMP0` writer"]
pub type W = crate :: W < SCOMP0_SPEC > ; # [doc = "Field `SCOMP0_VAL` reader - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
pub type SCOMP0_VAL_R = crate :: FieldReader < u16 > ; # [doc = "Field `SCOMP0_VAL` writer - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
pub type SCOMP0_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; impl R { # [doc = "Bits 0:9 - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
# [inline (always)]
pub fn scomp0_val (& self) -> SCOMP0_VAL_R { SCOMP0_VAL_R :: new ((self . bits & 0x03ff) as u16) } } impl W { # [doc = "Bits 0:9 - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
# [inline (always)]
# [must_use]
pub fn scomp0_val (& mut self) -> SCOMP0_VAL_W < SCOMP0_SPEC , 0 > { SCOMP0_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Sample Time Compare 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scomp0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scomp0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SCOMP0_SPEC ; impl crate :: RegisterSpec for SCOMP0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`scomp0::R`](R) reader structure"]
impl crate :: Readable for SCOMP0_SPEC { } # [doc = "`write(|w| ..)` method takes [`scomp0::W`](W) writer structure"]
impl crate :: Writable for SCOMP0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCOMP0 to value 0"]
impl crate :: Resettable for SCOMP0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "SCOMP1 (rw) register accessor: Sample Time Compare 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scomp1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scomp1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@scomp1`]
module"]
pub type SCOMP1 = crate :: Reg < scomp1 :: SCOMP1_SPEC > ; # [doc = "Sample Time Compare 1 Register"]
pub mod scomp1 { # [doc = "Register `SCOMP1` reader"]
pub type R = crate :: R < SCOMP1_SPEC > ; # [doc = "Register `SCOMP1` writer"]
pub type W = crate :: W < SCOMP1_SPEC > ; # [doc = "Field `SCOMP1_VAL` reader - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
pub type SCOMP1_VAL_R = crate :: FieldReader < u16 > ; # [doc = "Field `SCOMP1_VAL` writer - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
pub type SCOMP1_VAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 10 , O , u16 > ; impl R { # [doc = "Bits 0:9 - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
# [inline (always)]
pub fn scomp1_val (& self) -> SCOMP1_VAL_R { SCOMP1_VAL_R :: new ((self . bits & 0x03ff) as u16) } } impl W { # [doc = "Bits 0:9 - Specifies the number of sample clocks. When VAL = 0 or 1, number of sample clocks = Sample clock divide value. When VAL &amp;gt; 1, number of sample clocks = VAL x Sample clock divide value. Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4). Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles."]
# [inline (always)]
# [must_use]
pub fn scomp1_val (& mut self) -> SCOMP1_VAL_W < SCOMP1_SPEC , 0 > { SCOMP1_VAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Sample Time Compare 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`scomp1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`scomp1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SCOMP1_SPEC ; impl crate :: RegisterSpec for SCOMP1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`scomp1::R`](R) reader structure"]
impl crate :: Readable for SCOMP1_SPEC { } # [doc = "`write(|w| ..)` method takes [`scomp1::W`](W) writer structure"]
impl crate :: Writable for SCOMP1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets SCOMP1 to value 0"]
impl crate :: Resettable for SCOMP1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "REFCFG (rw) register accessor: Reference Buffer Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refcfg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refcfg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@refcfg`]
module"]
pub type REFCFG = crate :: Reg < refcfg :: REFCFG_SPEC > ; # [doc = "Reference Buffer Configuration Register"]
pub mod refcfg { # [doc = "Register `REFCFG` reader"]
pub type R = crate :: R < REFCFG_SPEC > ; # [doc = "Register `REFCFG` writer"]
pub type W = crate :: W < REFCFG_SPEC > ; # [doc = "Field `REFCFG_REFEN` reader - Reference buffer enable"]
pub type REFCFG_REFEN_R = crate :: BitReader ; # [doc = "Field `REFCFG_REFEN` writer - Reference buffer enable"]
pub type REFCFG_REFEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `REFCFG_REFVSEL` reader - Configures reference buffer output voltage."]
pub type REFCFG_REFVSEL_R = crate :: BitReader ; # [doc = "Field `REFCFG_REFVSEL` writer - Configures reference buffer output voltage."]
pub type REFCFG_REFVSEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O > ; # [doc = "Field `REFCFG_IBPROG` reader - Configures reference buffer bias current output value."]
pub type REFCFG_IBPROG_R = crate :: FieldReader ; # [doc = "Field `REFCFG_IBPROG` writer - Configures reference buffer bias current output value."]
pub type REFCFG_IBPROG_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O > ; impl R { # [doc = "Bit 0 - Reference buffer enable"]
# [inline (always)]
pub fn refcfg_refen (& self) -> REFCFG_REFEN_R { REFCFG_REFEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Configures reference buffer output voltage."]
# [inline (always)]
pub fn refcfg_refvsel (& self) -> REFCFG_REFVSEL_R { REFCFG_REFVSEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 3:4 - Configures reference buffer bias current output value."]
# [inline (always)]
pub fn refcfg_ibprog (& self) -> REFCFG_IBPROG_R { REFCFG_IBPROG_R :: new (((self . bits >> 3) & 3) as u8) } } impl W { # [doc = "Bit 0 - Reference buffer enable"]
# [inline (always)]
# [must_use]
pub fn refcfg_refen (& mut self) -> REFCFG_REFEN_W < REFCFG_SPEC , 0 > { REFCFG_REFEN_W :: new (self) } # [doc = "Bit 1 - Configures reference buffer output voltage."]
# [inline (always)]
# [must_use]
pub fn refcfg_refvsel (& mut self) -> REFCFG_REFVSEL_W < REFCFG_SPEC , 1 > { REFCFG_REFVSEL_W :: new (self) } # [doc = "Bits 3:4 - Configures reference buffer bias current output value."]
# [inline (always)]
# [must_use]
pub fn refcfg_ibprog (& mut self) -> REFCFG_IBPROG_W < REFCFG_SPEC , 3 > { REFCFG_IBPROG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reference Buffer Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`refcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`refcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct REFCFG_SPEC ; impl crate :: RegisterSpec for REFCFG_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`refcfg::R`](R) reader structure"]
impl crate :: Readable for REFCFG_SPEC { } # [doc = "`write(|w| ..)` method takes [`refcfg::W`](W) writer structure"]
impl crate :: Writable for REFCFG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets REFCFG to value 0"]
impl crate :: Resettable for REFCFG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "WCLOW (rw) register accessor: Window Comparator Low Threshold Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wclow::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wclow::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wclow`]
module"]
pub type WCLOW = crate :: Reg < wclow :: WCLOW_SPEC > ; # [doc = "Window Comparator Low Threshold Register"]
pub mod wclow { # [doc = "Register `WCLOW` reader"]
pub type R = crate :: R < WCLOW_SPEC > ; # [doc = "Register `WCLOW` writer"]
pub type W = crate :: W < WCLOW_SPEC > ; # [doc = "Field `WCLOW_DATA` reader - If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s."]
pub type WCLOW_DATA_R = crate :: FieldReader < u16 > ; # [doc = "Field `WCLOW_DATA` writer - If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s."]
pub type WCLOW_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s."]
# [inline (always)]
pub fn wclow_data (& self) -> WCLOW_DATA_R { WCLOW_DATA_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - If DF = 0, unsigned binary format has to be used. The value based on the resolution has to be right aligned with the MSB on the left. For 10-bits and 8-bits resolution, unused bits have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bits have to be 0s."]
# [inline (always)]
# [must_use]
pub fn wclow_data (& mut self) -> WCLOW_DATA_W < WCLOW_SPEC , 0 > { WCLOW_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Comparator Low Threshold Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wclow::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wclow::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WCLOW_SPEC ; impl crate :: RegisterSpec for WCLOW_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wclow::R`](R) reader structure"]
impl crate :: Readable for WCLOW_SPEC { } # [doc = "`write(|w| ..)` method takes [`wclow::W`](W) writer structure"]
impl crate :: Writable for WCLOW_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WCLOW to value 0"]
impl crate :: Resettable for WCLOW_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "WCHIGH (rw) register accessor: Window Comparator High Threshold Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wchigh::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wchigh::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@wchigh`]
module"]
pub type WCHIGH = crate :: Reg < wchigh :: WCHIGH_SPEC > ; # [doc = "Window Comparator High Threshold Register"]
pub mod wchigh { # [doc = "Register `WCHIGH` reader"]
pub type R = crate :: R < WCHIGH_SPEC > ; # [doc = "Register `WCHIGH` writer"]
pub type W = crate :: W < WCHIGH_SPEC > ; # [doc = "Field `WCHIGH_DATA` reader - If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s."]
pub type WCHIGH_DATA_R = crate :: FieldReader < u16 > ; # [doc = "Field `WCHIGH_DATA` writer - If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s."]
pub type WCHIGH_DATA_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s."]
# [inline (always)]
pub fn wchigh_data (& self) -> WCHIGH_DATA_R { WCHIGH_DATA_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - If DF = 0, unsigned binary format has to be used. The threshold value has to be right aligned, with the MSB on the left. For 10-bits and 8-bits resolution, unused bit have to be 0s. If DF = 1, 2s-complement format has to be used. The value based on the resolution has to be left aligned with the LSB on the right. For 10-bits and 8-bits resolution, unused bit have to be 0s."]
# [inline (always)]
# [must_use]
pub fn wchigh_data (& mut self) -> WCHIGH_DATA_W < WCHIGH_SPEC , 0 > { WCHIGH_DATA_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Window Comparator High Threshold Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`wchigh::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`wchigh::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct WCHIGH_SPEC ; impl crate :: RegisterSpec for WCHIGH_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`wchigh::R`](R) reader structure"]
impl crate :: Readable for WCHIGH_SPEC { } # [doc = "`write(|w| ..)` method takes [`wchigh::W`](W) writer structure"]
impl crate :: Writable for WCHIGH_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets WCHIGH to value 0"]
impl crate :: Resettable for WCHIGH_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MEMCTL (rw) register accessor: Conversion Memory Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`memctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`memctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@memctl`]
module"]
pub type MEMCTL = crate :: Reg < memctl :: MEMCTL_SPEC > ; # [doc = "Conversion Memory Control Register"]
pub mod memctl { # [doc = "Register `MEMCTL[%s]` reader"]
pub type R = crate :: R < MEMCTL_SPEC > ; # [doc = "Register `MEMCTL[%s]` writer"]
pub type W = crate :: W < MEMCTL_SPEC > ; # [doc = "Field `MEMCTL_CHANSEL` reader - Input channel select."]
pub type MEMCTL_CHANSEL_R = crate :: FieldReader < MEMCTL_CHANSEL_A > ; # [doc = "Input channel select.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum MEMCTL_CHANSEL_A { # [doc = "0: CHAN_0"]
MEMCTL_CHANSEL_CHAN_0 = 0 , # [doc = "1: CHAN_1"]
MEMCTL_CHANSEL_CHAN_1 = 1 , # [doc = "2: CHAN_2"]
MEMCTL_CHANSEL_CHAN_2 = 2 , # [doc = "3: CHAN_3"]
MEMCTL_CHANSEL_CHAN_3 = 3 , # [doc = "4: CHAN_4"]
MEMCTL_CHANSEL_CHAN_4 = 4 , # [doc = "5: CHAN_5"]
MEMCTL_CHANSEL_CHAN_5 = 5 , # [doc = "6: CHAN_6"]
MEMCTL_CHANSEL_CHAN_6 = 6 , # [doc = "7: CHAN_7"]
MEMCTL_CHANSEL_CHAN_7 = 7 , # [doc = "8: CHAN_8"]
MEMCTL_CHANSEL_CHAN_8 = 8 , # [doc = "9: CHAN_9"]
MEMCTL_CHANSEL_CHAN_9 = 9 , # [doc = "10: CHAN_10"]
MEMCTL_CHANSEL_CHAN_10 = 10 , # [doc = "11: CHAN_11"]
MEMCTL_CHANSEL_CHAN_11 = 11 , # [doc = "12: CHAN_12"]
MEMCTL_CHANSEL_CHAN_12 = 12 , # [doc = "13: CHAN_13"]
MEMCTL_CHANSEL_CHAN_13 = 13 , # [doc = "14: CHAN_14"]
MEMCTL_CHANSEL_CHAN_14 = 14 , # [doc = "15: CHAN_15"]
MEMCTL_CHANSEL_CHAN_15 = 15 , # [doc = "16: CHAN_16"]
MEMCTL_CHANSEL_CHAN_16 = 16 , # [doc = "17: CHAN_17"]
MEMCTL_CHANSEL_CHAN_17 = 17 , # [doc = "18: CHAN_18"]
MEMCTL_CHANSEL_CHAN_18 = 18 , # [doc = "19: CHAN_19"]
MEMCTL_CHANSEL_CHAN_19 = 19 , # [doc = "20: CHAN_20"]
MEMCTL_CHANSEL_CHAN_20 = 20 , # [doc = "21: CHAN_21"]
MEMCTL_CHANSEL_CHAN_21 = 21 , # [doc = "22: CHAN_22"]
MEMCTL_CHANSEL_CHAN_22 = 22 , # [doc = "23: CHAN_23"]
MEMCTL_CHANSEL_CHAN_23 = 23 , # [doc = "24: CHAN_24"]
MEMCTL_CHANSEL_CHAN_24 = 24 , # [doc = "25: CHAN_25"]
MEMCTL_CHANSEL_CHAN_25 = 25 , # [doc = "26: CHAN_26"]
MEMCTL_CHANSEL_CHAN_26 = 26 , # [doc = "27: CHAN_27"]
MEMCTL_CHANSEL_CHAN_27 = 27 , # [doc = "28: CHAN_28"]
MEMCTL_CHANSEL_CHAN_28 = 28 , # [doc = "29: CHAN_29"]
MEMCTL_CHANSEL_CHAN_29 = 29 , # [doc = "30: CHAN_30"]
MEMCTL_CHANSEL_CHAN_30 = 30 , # [doc = "31: CHAN_31"]
MEMCTL_CHANSEL_CHAN_31 = 31 , } impl From < MEMCTL_CHANSEL_A > for u8 { # [inline (always)]
fn from (variant : MEMCTL_CHANSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for MEMCTL_CHANSEL_A { type Ux = u8 ; } impl MEMCTL_CHANSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MEMCTL_CHANSEL_A { match self . bits { 0 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_0 , 1 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_1 , 2 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_2 , 3 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_3 , 4 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_4 , 5 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_5 , 6 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_6 , 7 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_7 , 8 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_8 , 9 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_9 , 10 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_10 , 11 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_11 , 12 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_12 , 13 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_13 , 14 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_14 , 15 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_15 , 16 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_16 , 17 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_17 , 18 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_18 , 19 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_19 , 20 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_20 , 21 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_21 , 22 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_22 , 23 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_23 , 24 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_24 , 25 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_25 , 26 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_26 , 27 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_27 , 28 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_28 , 29 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_29 , 30 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_30 , 31 => MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_31 , _ => unreachable ! () , } } # [doc = "CHAN_0"]
# [inline (always)]
pub fn is_memctl_chansel_chan_0 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_0 } # [doc = "CHAN_1"]
# [inline (always)]
pub fn is_memctl_chansel_chan_1 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_1 } # [doc = "CHAN_2"]
# [inline (always)]
pub fn is_memctl_chansel_chan_2 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_2 } # [doc = "CHAN_3"]
# [inline (always)]
pub fn is_memctl_chansel_chan_3 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_3 } # [doc = "CHAN_4"]
# [inline (always)]
pub fn is_memctl_chansel_chan_4 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_4 } # [doc = "CHAN_5"]
# [inline (always)]
pub fn is_memctl_chansel_chan_5 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_5 } # [doc = "CHAN_6"]
# [inline (always)]
pub fn is_memctl_chansel_chan_6 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_6 } # [doc = "CHAN_7"]
# [inline (always)]
pub fn is_memctl_chansel_chan_7 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_7 } # [doc = "CHAN_8"]
# [inline (always)]
pub fn is_memctl_chansel_chan_8 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_8 } # [doc = "CHAN_9"]
# [inline (always)]
pub fn is_memctl_chansel_chan_9 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_9 } # [doc = "CHAN_10"]
# [inline (always)]
pub fn is_memctl_chansel_chan_10 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_10 } # [doc = "CHAN_11"]
# [inline (always)]
pub fn is_memctl_chansel_chan_11 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_11 } # [doc = "CHAN_12"]
# [inline (always)]
pub fn is_memctl_chansel_chan_12 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_12 } # [doc = "CHAN_13"]
# [inline (always)]
pub fn is_memctl_chansel_chan_13 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_13 } # [doc = "CHAN_14"]
# [inline (always)]
pub fn is_memctl_chansel_chan_14 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_14 } # [doc = "CHAN_15"]
# [inline (always)]
pub fn is_memctl_chansel_chan_15 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_15 } # [doc = "CHAN_16"]
# [inline (always)]
pub fn is_memctl_chansel_chan_16 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_16 } # [doc = "CHAN_17"]
# [inline (always)]
pub fn is_memctl_chansel_chan_17 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_17 } # [doc = "CHAN_18"]
# [inline (always)]
pub fn is_memctl_chansel_chan_18 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_18 } # [doc = "CHAN_19"]
# [inline (always)]
pub fn is_memctl_chansel_chan_19 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_19 } # [doc = "CHAN_20"]
# [inline (always)]
pub fn is_memctl_chansel_chan_20 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_20 } # [doc = "CHAN_21"]
# [inline (always)]
pub fn is_memctl_chansel_chan_21 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_21 } # [doc = "CHAN_22"]
# [inline (always)]
pub fn is_memctl_chansel_chan_22 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_22 } # [doc = "CHAN_23"]
# [inline (always)]
pub fn is_memctl_chansel_chan_23 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_23 } # [doc = "CHAN_24"]
# [inline (always)]
pub fn is_memctl_chansel_chan_24 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_24 } # [doc = "CHAN_25"]
# [inline (always)]
pub fn is_memctl_chansel_chan_25 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_25 } # [doc = "CHAN_26"]
# [inline (always)]
pub fn is_memctl_chansel_chan_26 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_26 } # [doc = "CHAN_27"]
# [inline (always)]
pub fn is_memctl_chansel_chan_27 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_27 } # [doc = "CHAN_28"]
# [inline (always)]
pub fn is_memctl_chansel_chan_28 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_28 } # [doc = "CHAN_29"]
# [inline (always)]
pub fn is_memctl_chansel_chan_29 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_29 } # [doc = "CHAN_30"]
# [inline (always)]
pub fn is_memctl_chansel_chan_30 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_30 } # [doc = "CHAN_31"]
# [inline (always)]
pub fn is_memctl_chansel_chan_31 (& self) -> bool { * self == MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_31 } } # [doc = "Field `MEMCTL_CHANSEL` writer - Input channel select."]
pub type MEMCTL_CHANSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 5 , O , MEMCTL_CHANSEL_A > ; impl < 'a , REG , const O : u8 > MEMCTL_CHANSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CHAN_0"]
# [inline (always)]
pub fn memctl_chansel_chan_0 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_0) } # [doc = "CHAN_1"]
# [inline (always)]
pub fn memctl_chansel_chan_1 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_1) } # [doc = "CHAN_2"]
# [inline (always)]
pub fn memctl_chansel_chan_2 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_2) } # [doc = "CHAN_3"]
# [inline (always)]
pub fn memctl_chansel_chan_3 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_3) } # [doc = "CHAN_4"]
# [inline (always)]
pub fn memctl_chansel_chan_4 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_4) } # [doc = "CHAN_5"]
# [inline (always)]
pub fn memctl_chansel_chan_5 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_5) } # [doc = "CHAN_6"]
# [inline (always)]
pub fn memctl_chansel_chan_6 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_6) } # [doc = "CHAN_7"]
# [inline (always)]
pub fn memctl_chansel_chan_7 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_7) } # [doc = "CHAN_8"]
# [inline (always)]
pub fn memctl_chansel_chan_8 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_8) } # [doc = "CHAN_9"]
# [inline (always)]
pub fn memctl_chansel_chan_9 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_9) } # [doc = "CHAN_10"]
# [inline (always)]
pub fn memctl_chansel_chan_10 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_10) } # [doc = "CHAN_11"]
# [inline (always)]
pub fn memctl_chansel_chan_11 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_11) } # [doc = "CHAN_12"]
# [inline (always)]
pub fn memctl_chansel_chan_12 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_12) } # [doc = "CHAN_13"]
# [inline (always)]
pub fn memctl_chansel_chan_13 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_13) } # [doc = "CHAN_14"]
# [inline (always)]
pub fn memctl_chansel_chan_14 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_14) } # [doc = "CHAN_15"]
# [inline (always)]
pub fn memctl_chansel_chan_15 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_15) } # [doc = "CHAN_16"]
# [inline (always)]
pub fn memctl_chansel_chan_16 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_16) } # [doc = "CHAN_17"]
# [inline (always)]
pub fn memctl_chansel_chan_17 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_17) } # [doc = "CHAN_18"]
# [inline (always)]
pub fn memctl_chansel_chan_18 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_18) } # [doc = "CHAN_19"]
# [inline (always)]
pub fn memctl_chansel_chan_19 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_19) } # [doc = "CHAN_20"]
# [inline (always)]
pub fn memctl_chansel_chan_20 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_20) } # [doc = "CHAN_21"]
# [inline (always)]
pub fn memctl_chansel_chan_21 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_21) } # [doc = "CHAN_22"]
# [inline (always)]
pub fn memctl_chansel_chan_22 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_22) } # [doc = "CHAN_23"]
# [inline (always)]
pub fn memctl_chansel_chan_23 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_23) } # [doc = "CHAN_24"]
# [inline (always)]
pub fn memctl_chansel_chan_24 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_24) } # [doc = "CHAN_25"]
# [inline (always)]
pub fn memctl_chansel_chan_25 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_25) } # [doc = "CHAN_26"]
# [inline (always)]
pub fn memctl_chansel_chan_26 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_26) } # [doc = "CHAN_27"]
# [inline (always)]
pub fn memctl_chansel_chan_27 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_27) } # [doc = "CHAN_28"]
# [inline (always)]
pub fn memctl_chansel_chan_28 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_28) } # [doc = "CHAN_29"]
# [inline (always)]
pub fn memctl_chansel_chan_29 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_29) } # [doc = "CHAN_30"]
# [inline (always)]
pub fn memctl_chansel_chan_30 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_30) } # [doc = "CHAN_31"]
# [inline (always)]
pub fn memctl_chansel_chan_31 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_CHANSEL_A :: MEMCTL_CHANSEL_CHAN_31) } } # [doc = "Field `MEMCTL_VRSEL` reader - Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF."]
pub type MEMCTL_VRSEL_R = crate :: FieldReader < MEMCTL_VRSEL_A > ; # [doc = "Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum MEMCTL_VRSEL_A { # [doc = "0: VDDA"]
MEMCTL_VRSEL_VDDA = 0 , # [doc = "1: EXTREF"]
MEMCTL_VRSEL_EXTREF = 1 , # [doc = "2: INTREF"]
MEMCTL_VRSEL_INTREF = 2 , } impl From < MEMCTL_VRSEL_A > for u8 { # [inline (always)]
fn from (variant : MEMCTL_VRSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for MEMCTL_VRSEL_A { type Ux = u8 ; } impl MEMCTL_VRSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < MEMCTL_VRSEL_A > { match self . bits { 0 => Some (MEMCTL_VRSEL_A :: MEMCTL_VRSEL_VDDA) , 1 => Some (MEMCTL_VRSEL_A :: MEMCTL_VRSEL_EXTREF) , 2 => Some (MEMCTL_VRSEL_A :: MEMCTL_VRSEL_INTREF) , _ => None , } } # [doc = "VDDA"]
# [inline (always)]
pub fn is_memctl_vrsel_vdda (& self) -> bool { * self == MEMCTL_VRSEL_A :: MEMCTL_VRSEL_VDDA } # [doc = "EXTREF"]
# [inline (always)]
pub fn is_memctl_vrsel_extref (& self) -> bool { * self == MEMCTL_VRSEL_A :: MEMCTL_VRSEL_EXTREF } # [doc = "INTREF"]
# [inline (always)]
pub fn is_memctl_vrsel_intref (& self) -> bool { * self == MEMCTL_VRSEL_A :: MEMCTL_VRSEL_INTREF } } # [doc = "Field `MEMCTL_VRSEL` writer - Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF."]
pub type MEMCTL_VRSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , MEMCTL_VRSEL_A > ; impl < 'a , REG , const O : u8 > MEMCTL_VRSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "VDDA"]
# [inline (always)]
pub fn memctl_vrsel_vdda (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_VRSEL_A :: MEMCTL_VRSEL_VDDA) } # [doc = "EXTREF"]
# [inline (always)]
pub fn memctl_vrsel_extref (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_VRSEL_A :: MEMCTL_VRSEL_EXTREF) } # [doc = "INTREF"]
# [inline (always)]
pub fn memctl_vrsel_intref (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_VRSEL_A :: MEMCTL_VRSEL_INTREF) } } # [doc = "Field `MEMCTL_STIME` reader - Selects the source of sample timer period between SCOMP0 and SCOMP1."]
pub type MEMCTL_STIME_R = crate :: BitReader < MEMCTL_STIME_A > ; # [doc = "Selects the source of sample timer period between SCOMP0 and SCOMP1.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MEMCTL_STIME_A { # [doc = "0: SEL_SCOMP0"]
MEMCTL_STIME_SEL_SCOMP0 = 0 , # [doc = "1: SEL_SCOMP1"]
MEMCTL_STIME_SEL_SCOMP1 = 1 , } impl From < MEMCTL_STIME_A > for bool { # [inline (always)]
fn from (variant : MEMCTL_STIME_A) -> Self { variant as u8 != 0 } } impl MEMCTL_STIME_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MEMCTL_STIME_A { match self . bits { false => MEMCTL_STIME_A :: MEMCTL_STIME_SEL_SCOMP0 , true => MEMCTL_STIME_A :: MEMCTL_STIME_SEL_SCOMP1 , } } # [doc = "SEL_SCOMP0"]
# [inline (always)]
pub fn is_memctl_stime_sel_scomp0 (& self) -> bool { * self == MEMCTL_STIME_A :: MEMCTL_STIME_SEL_SCOMP0 } # [doc = "SEL_SCOMP1"]
# [inline (always)]
pub fn is_memctl_stime_sel_scomp1 (& self) -> bool { * self == MEMCTL_STIME_A :: MEMCTL_STIME_SEL_SCOMP1 } } # [doc = "Field `MEMCTL_STIME` writer - Selects the source of sample timer period between SCOMP0 and SCOMP1."]
pub type MEMCTL_STIME_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MEMCTL_STIME_A > ; impl < 'a , REG , const O : u8 > MEMCTL_STIME_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "SEL_SCOMP0"]
# [inline (always)]
pub fn memctl_stime_sel_scomp0 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_STIME_A :: MEMCTL_STIME_SEL_SCOMP0) } # [doc = "SEL_SCOMP1"]
# [inline (always)]
pub fn memctl_stime_sel_scomp1 (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_STIME_A :: MEMCTL_STIME_SEL_SCOMP1) } } # [doc = "Field `MEMCTL_AVGEN` reader - Enable hardware averaging."]
pub type MEMCTL_AVGEN_R = crate :: BitReader < MEMCTL_AVGEN_A > ; # [doc = "Enable hardware averaging.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MEMCTL_AVGEN_A { # [doc = "0: DISABLE"]
MEMCTL_AVGEN_DISABLE = 0 , # [doc = "1: ENABLE"]
MEMCTL_AVGEN_ENABLE = 1 , } impl From < MEMCTL_AVGEN_A > for bool { # [inline (always)]
fn from (variant : MEMCTL_AVGEN_A) -> Self { variant as u8 != 0 } } impl MEMCTL_AVGEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MEMCTL_AVGEN_A { match self . bits { false => MEMCTL_AVGEN_A :: MEMCTL_AVGEN_DISABLE , true => MEMCTL_AVGEN_A :: MEMCTL_AVGEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_memctl_avgen_disable (& self) -> bool { * self == MEMCTL_AVGEN_A :: MEMCTL_AVGEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_memctl_avgen_enable (& self) -> bool { * self == MEMCTL_AVGEN_A :: MEMCTL_AVGEN_ENABLE } } # [doc = "Field `MEMCTL_AVGEN` writer - Enable hardware averaging."]
pub type MEMCTL_AVGEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MEMCTL_AVGEN_A > ; impl < 'a , REG , const O : u8 > MEMCTL_AVGEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn memctl_avgen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_AVGEN_A :: MEMCTL_AVGEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn memctl_avgen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_AVGEN_A :: MEMCTL_AVGEN_ENABLE) } } # [doc = "Field `MEMCTL_BCSEN` reader - Enable burn out current source."]
pub type MEMCTL_BCSEN_R = crate :: BitReader < MEMCTL_BCSEN_A > ; # [doc = "Enable burn out current source.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MEMCTL_BCSEN_A { # [doc = "0: DISABLE"]
MEMCTL_BCSEN_DISABLE = 0 , # [doc = "1: ENABLE"]
MEMCTL_BCSEN_ENABLE = 1 , } impl From < MEMCTL_BCSEN_A > for bool { # [inline (always)]
fn from (variant : MEMCTL_BCSEN_A) -> Self { variant as u8 != 0 } } impl MEMCTL_BCSEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MEMCTL_BCSEN_A { match self . bits { false => MEMCTL_BCSEN_A :: MEMCTL_BCSEN_DISABLE , true => MEMCTL_BCSEN_A :: MEMCTL_BCSEN_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_memctl_bcsen_disable (& self) -> bool { * self == MEMCTL_BCSEN_A :: MEMCTL_BCSEN_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_memctl_bcsen_enable (& self) -> bool { * self == MEMCTL_BCSEN_A :: MEMCTL_BCSEN_ENABLE } } # [doc = "Field `MEMCTL_BCSEN` writer - Enable burn out current source."]
pub type MEMCTL_BCSEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MEMCTL_BCSEN_A > ; impl < 'a , REG , const O : u8 > MEMCTL_BCSEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn memctl_bcsen_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_BCSEN_A :: MEMCTL_BCSEN_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn memctl_bcsen_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_BCSEN_A :: MEMCTL_BCSEN_ENABLE) } } # [doc = "Field `MEMCTL_TRIG` reader - Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions."]
pub type MEMCTL_TRIG_R = crate :: BitReader < MEMCTL_TRIG_A > ; # [doc = "Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MEMCTL_TRIG_A { # [doc = "0: AUTO_NEXT"]
MEMCTL_TRIG_AUTO_NEXT = 0 , # [doc = "1: TRIGGER_NEXT"]
MEMCTL_TRIG_TRIGGER_NEXT = 1 , } impl From < MEMCTL_TRIG_A > for bool { # [inline (always)]
fn from (variant : MEMCTL_TRIG_A) -> Self { variant as u8 != 0 } } impl MEMCTL_TRIG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MEMCTL_TRIG_A { match self . bits { false => MEMCTL_TRIG_A :: MEMCTL_TRIG_AUTO_NEXT , true => MEMCTL_TRIG_A :: MEMCTL_TRIG_TRIGGER_NEXT , } } # [doc = "AUTO_NEXT"]
# [inline (always)]
pub fn is_memctl_trig_auto_next (& self) -> bool { * self == MEMCTL_TRIG_A :: MEMCTL_TRIG_AUTO_NEXT } # [doc = "TRIGGER_NEXT"]
# [inline (always)]
pub fn is_memctl_trig_trigger_next (& self) -> bool { * self == MEMCTL_TRIG_A :: MEMCTL_TRIG_TRIGGER_NEXT } } # [doc = "Field `MEMCTL_TRIG` writer - Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions."]
pub type MEMCTL_TRIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MEMCTL_TRIG_A > ; impl < 'a , REG , const O : u8 > MEMCTL_TRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "AUTO_NEXT"]
# [inline (always)]
pub fn memctl_trig_auto_next (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_TRIG_A :: MEMCTL_TRIG_AUTO_NEXT) } # [doc = "TRIGGER_NEXT"]
# [inline (always)]
pub fn memctl_trig_trigger_next (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_TRIG_A :: MEMCTL_TRIG_TRIGGER_NEXT) } } # [doc = "Field `MEMCTL_WINCOMP` reader - Enable window comparator."]
pub type MEMCTL_WINCOMP_R = crate :: BitReader < MEMCTL_WINCOMP_A > ; # [doc = "Enable window comparator.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MEMCTL_WINCOMP_A { # [doc = "0: DISABLE"]
MEMCTL_WINCOMP_DISABLE = 0 , # [doc = "1: ENABLE"]
MEMCTL_WINCOMP_ENABLE = 1 , } impl From < MEMCTL_WINCOMP_A > for bool { # [inline (always)]
fn from (variant : MEMCTL_WINCOMP_A) -> Self { variant as u8 != 0 } } impl MEMCTL_WINCOMP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MEMCTL_WINCOMP_A { match self . bits { false => MEMCTL_WINCOMP_A :: MEMCTL_WINCOMP_DISABLE , true => MEMCTL_WINCOMP_A :: MEMCTL_WINCOMP_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_memctl_wincomp_disable (& self) -> bool { * self == MEMCTL_WINCOMP_A :: MEMCTL_WINCOMP_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_memctl_wincomp_enable (& self) -> bool { * self == MEMCTL_WINCOMP_A :: MEMCTL_WINCOMP_ENABLE } } # [doc = "Field `MEMCTL_WINCOMP` writer - Enable window comparator."]
pub type MEMCTL_WINCOMP_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , MEMCTL_WINCOMP_A > ; impl < 'a , REG , const O : u8 > MEMCTL_WINCOMP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn memctl_wincomp_disable (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_WINCOMP_A :: MEMCTL_WINCOMP_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn memctl_wincomp_enable (self) -> & 'a mut crate :: W < REG > { self . variant (MEMCTL_WINCOMP_A :: MEMCTL_WINCOMP_ENABLE) } } impl R { # [doc = "Bits 0:4 - Input channel select."]
# [inline (always)]
pub fn memctl_chansel (& self) -> MEMCTL_CHANSEL_R { MEMCTL_CHANSEL_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bits 8:9 - Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF."]
# [inline (always)]
pub fn memctl_vrsel (& self) -> MEMCTL_VRSEL_R { MEMCTL_VRSEL_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 12 - Selects the source of sample timer period between SCOMP0 and SCOMP1."]
# [inline (always)]
pub fn memctl_stime (& self) -> MEMCTL_STIME_R { MEMCTL_STIME_R :: new (((self . bits >> 12) & 1) != 0) } # [doc = "Bit 16 - Enable hardware averaging."]
# [inline (always)]
pub fn memctl_avgen (& self) -> MEMCTL_AVGEN_R { MEMCTL_AVGEN_R :: new (((self . bits >> 16) & 1) != 0) } # [doc = "Bit 20 - Enable burn out current source."]
# [inline (always)]
pub fn memctl_bcsen (& self) -> MEMCTL_BCSEN_R { MEMCTL_BCSEN_R :: new (((self . bits >> 20) & 1) != 0) } # [doc = "Bit 24 - Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions."]
# [inline (always)]
pub fn memctl_trig (& self) -> MEMCTL_TRIG_R { MEMCTL_TRIG_R :: new (((self . bits >> 24) & 1) != 0) } # [doc = "Bit 28 - Enable window comparator."]
# [inline (always)]
pub fn memctl_wincomp (& self) -> MEMCTL_WINCOMP_R { MEMCTL_WINCOMP_R :: new (((self . bits >> 28) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - Input channel select."]
# [inline (always)]
# [must_use]
pub fn memctl_chansel (& mut self) -> MEMCTL_CHANSEL_W < MEMCTL_SPEC , 0 > { MEMCTL_CHANSEL_W :: new (self) } # [doc = "Bits 8:9 - Voltage reference selection. VEREFM must be connected to on-board ground when external reference option is selected. Note: Writing value 0x3 defaults to INTREF."]
# [inline (always)]
# [must_use]
pub fn memctl_vrsel (& mut self) -> MEMCTL_VRSEL_W < MEMCTL_SPEC , 8 > { MEMCTL_VRSEL_W :: new (self) } # [doc = "Bit 12 - Selects the source of sample timer period between SCOMP0 and SCOMP1."]
# [inline (always)]
# [must_use]
pub fn memctl_stime (& mut self) -> MEMCTL_STIME_W < MEMCTL_SPEC , 12 > { MEMCTL_STIME_W :: new (self) } # [doc = "Bit 16 - Enable hardware averaging."]
# [inline (always)]
# [must_use]
pub fn memctl_avgen (& mut self) -> MEMCTL_AVGEN_W < MEMCTL_SPEC , 16 > { MEMCTL_AVGEN_W :: new (self) } # [doc = "Bit 20 - Enable burn out current source."]
# [inline (always)]
# [must_use]
pub fn memctl_bcsen (& mut self) -> MEMCTL_BCSEN_W < MEMCTL_SPEC , 20 > { MEMCTL_BCSEN_W :: new (self) } # [doc = "Bit 24 - Trigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions."]
# [inline (always)]
# [must_use]
pub fn memctl_trig (& mut self) -> MEMCTL_TRIG_W < MEMCTL_SPEC , 24 > { MEMCTL_TRIG_W :: new (self) } # [doc = "Bit 28 - Enable window comparator."]
# [inline (always)]
# [must_use]
pub fn memctl_wincomp (& mut self) -> MEMCTL_WINCOMP_W < MEMCTL_SPEC , 28 > { MEMCTL_WINCOMP_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Conversion Memory Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`memctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`memctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MEMCTL_SPEC ; impl crate :: RegisterSpec for MEMCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`memctl::R`](R) reader structure"]
impl crate :: Readable for MEMCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`memctl::W`](W) writer structure"]
impl crate :: Writable for MEMCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets MEMCTL[%s]
to value 0"]
impl crate :: Resettable for MEMCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
module"]
pub type STATUS = crate :: Reg < status :: STATUS_SPEC > ; # [doc = "Status Register"]
pub mod status { # [doc = "Register `STATUS` reader"]
pub type R = crate :: R < STATUS_SPEC > ; # [doc = "Field `STATUS_BUSY` reader - Busy. This bit indicates that an active ADC sample or conversion operation is in progress."]
pub type STATUS_BUSY_R = crate :: BitReader < STATUS_BUSY_A > ; # [doc = "Busy. This bit indicates that an active ADC sample or conversion operation is in progress.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATUS_BUSY_A { # [doc = "0: IDLE"]
STATUS_BUSY_IDLE = 0 , # [doc = "1: ACTIVE"]
STATUS_BUSY_ACTIVE = 1 , } impl From < STATUS_BUSY_A > for bool { # [inline (always)]
fn from (variant : STATUS_BUSY_A) -> Self { variant as u8 != 0 } } impl STATUS_BUSY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATUS_BUSY_A { match self . bits { false => STATUS_BUSY_A :: STATUS_BUSY_IDLE , true => STATUS_BUSY_A :: STATUS_BUSY_ACTIVE , } } # [doc = "IDLE"]
# [inline (always)]
pub fn is_status_busy_idle (& self) -> bool { * self == STATUS_BUSY_A :: STATUS_BUSY_IDLE } # [doc = "ACTIVE"]
# [inline (always)]
pub fn is_status_busy_active (& self) -> bool { * self == STATUS_BUSY_A :: STATUS_BUSY_ACTIVE } } # [doc = "Field `STATUS_REFBUFRDY` reader - Indicates reference buffer is powered up and ready."]
pub type STATUS_REFBUFRDY_R = crate :: BitReader < STATUS_REFBUFRDY_A > ; # [doc = "Indicates reference buffer is powered up and ready.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STATUS_REFBUFRDY_A { # [doc = "0: NOTREADY"]
STATUS_REFBUFRDY_NOTREADY = 0 , # [doc = "1: READY"]
STATUS_REFBUFRDY_READY = 1 , } impl From < STATUS_REFBUFRDY_A > for bool { # [inline (always)]
fn from (variant : STATUS_REFBUFRDY_A) -> Self { variant as u8 != 0 } } impl STATUS_REFBUFRDY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STATUS_REFBUFRDY_A { match self . bits { false => STATUS_REFBUFRDY_A :: STATUS_REFBUFRDY_NOTREADY , true => STATUS_REFBUFRDY_A :: STATUS_REFBUFRDY_READY , } } # [doc = "NOTREADY"]
# [inline (always)]
pub fn is_status_refbufrdy_notready (& self) -> bool { * self == STATUS_REFBUFRDY_A :: STATUS_REFBUFRDY_NOTREADY } # [doc = "READY"]
# [inline (always)]
pub fn is_status_refbufrdy_ready (& self) -> bool { * self == STATUS_REFBUFRDY_A :: STATUS_REFBUFRDY_READY } } impl R { # [doc = "Bit 0 - Busy. This bit indicates that an active ADC sample or conversion operation is in progress."]
# [inline (always)]
pub fn status_busy (& self) -> STATUS_BUSY_R { STATUS_BUSY_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Indicates reference buffer is powered up and ready."]
# [inline (always)]
pub fn status_refbufrdy (& self) -> STATUS_REFBUFRDY_R { STATUS_REFBUFRDY_R :: new (((self . bits >> 1) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STATUS_SPEC ; impl crate :: RegisterSpec for STATUS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`status::R`](R) reader structure"]
impl crate :: Readable for STATUS_SPEC { } # [doc = "`reset()` method sets STATUS to value 0"]
impl crate :: Resettable for STATUS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGIONSVT"]
pub struct ADC0_SVT { _marker : PhantomData < * const () > } unsafe impl Send for ADC0_SVT { } impl ADC0_SVT { # [doc = r"Pointer to the register block"]
pub const PTR : * const adc0_svt :: RegisterBlock = 0x4055_a000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const adc0_svt :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for ADC0_SVT { type Target = adc0_svt :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for ADC0_SVT { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("ADC0_SVT") . finish () } } # [doc = "PERIPHERALREGIONSVT"]
pub mod adc0_svt { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0160]
, # [doc = "0x160 - FIFO Data Register"]
pub fifodata : FIFODATA , _reserved1 : [u8 ; 0x011c]
, # [doc = "0x280..0x290 - Memory Result Register"]
pub memres : [MEMRES ; 4]
, } # [doc = "FIFODATA (r) register accessor: FIFO Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifodata::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifodata`]
module"]
pub type FIFODATA = crate :: Reg < fifodata :: FIFODATA_SPEC > ; # [doc = "FIFO Data Register"]
pub mod fifodata { # [doc = "Register `FIFODATA` reader"]
pub type R = crate :: R < FIFODATA_SPEC > ; # [doc = "Field `FIFODATA_DATA` reader - Read from this data field returns the ADC sample from FIFO."]
pub type FIFODATA_DATA_R = crate :: FieldReader < u32 > ; impl R { # [doc = "Bits 0:31 - Read from this data field returns the ADC sample from FIFO."]
# [inline (always)]
pub fn fifodata_data (& self) -> FIFODATA_DATA_R { FIFODATA_DATA_R :: new (self . bits) } } # [doc = "FIFO Data Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifodata::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FIFODATA_SPEC ; impl crate :: RegisterSpec for FIFODATA_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fifodata::R`](R) reader structure"]
impl crate :: Readable for FIFODATA_SPEC { } # [doc = "`reset()` method sets FIFODATA to value 0"]
impl crate :: Resettable for FIFODATA_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MEMRES (r) register accessor: Memory Result Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`memres::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@memres`]
module"]
pub type MEMRES = crate :: Reg < memres :: MEMRES_SPEC > ; # [doc = "Memory Result Register"]
pub mod memres { # [doc = "Register `MEMRES[%s]` reader"]
pub type R = crate :: R < MEMRES_SPEC > ; # [doc = "Field `MEMRES_DATA` reader - MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back."]
pub type MEMRES_DATA_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:15 - MEMRES result register. If DF = 0, unsigned binary: The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0. If DF = 1, 2s-complement format: The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0. The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back."]
# [inline (always)]
pub fn memres_data (& self) -> MEMRES_DATA_R { MEMRES_DATA_R :: new ((self . bits & 0xffff) as u16) } } # [doc = "Memory Result Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`memres::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MEMRES_SPEC ; impl crate :: RegisterSpec for MEMRES_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`memres::R`](R) reader structure"]
impl crate :: Readable for MEMRES_SPEC { } # [doc = "`reset()` method sets MEMRES[%s]
to value 0"]
impl crate :: Resettable for MEMRES_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct WUC { _marker : PhantomData < * const () > } unsafe impl Send for WUC { } impl WUC { # [doc = r"Pointer to the register block"]
pub const PTR : * const wuc :: RegisterBlock = 0x4042_4000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const wuc :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for WUC { type Target = wuc :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for WUC { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("WUC") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod wuc { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subscriber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , } # [doc = "FSUB_0 (rw) register accessor: Subscriber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subscriber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [doc = "PERIPHERALREGION"]
pub struct TIMG0 { _marker : PhantomData < * const () > } unsafe impl Send for TIMG0 { } impl TIMG0 { # [doc = r"Pointer to the register block"]
pub const PTR : * const timg0 :: RegisterBlock = 0x4008_4000 as * const _ ; # [doc = r"Return the pointer to the register block"]
# [inline (always)]
pub const fn ptr () -> * const timg0 :: RegisterBlock { Self :: PTR } # [doc = r" Steal an instance of this peripheral"]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
# [doc = r" that may race with any existing instances, for example by only"]
# [doc = r" accessing read-only or write-only registers, or by consuming the"]
# [doc = r" original peripheral and using critical sections to coordinate"]
# [doc = r" access between multiple new instances."]
# [doc = r""]
# [doc = r" Additionally, other software such as HALs may rely on only one"]
# [doc = r" peripheral instance existing to ensure memory safety; ensure"]
# [doc = r" no stolen instances are passed to such software."]
pub unsafe fn steal () -> Self { Self { _marker : PhantomData } } } impl Deref for TIMG0 { type Target = timg0 :: RegisterBlock ; # [inline (always)]
fn deref (& self) -> & Self :: Target { unsafe { & * Self :: PTR } } } impl core :: fmt :: Debug for TIMG0 { fn fmt (& self , f : & mut core :: fmt :: Formatter) -> core :: fmt :: Result { f . debug_struct ("TIMG0") . finish () } } # [doc = "PERIPHERALREGION"]
pub mod timg0 { # [doc = r"Register block"]
# [repr (C)]
pub struct RegisterBlock { _reserved0 : [u8 ; 0x0400]
, # [doc = "0x400 - Subsciber Port 0"]
pub fsub_0 : FSUB_0 , # [doc = "0x404 - Subscriber Port 1"]
pub fsub_1 : FSUB_1 , _reserved2 : [u8 ; 0x3c]
, # [doc = "0x444 - Publisher Port 0"]
pub fpub_0 : FPUB_0 , # [doc = "0x448 - Publisher Port 1"]
pub fpub_1 : FPUB_1 , _reserved4 : [u8 ; 0x03b4]
, # [doc = "0x800 - Power enable"]
pub pwren : PWREN , # [doc = "0x804 - Reset Control"]
pub rstctl : RSTCTL , _reserved6 : [u8 ; 0x0c]
, # [doc = "0x814 - Status Register"]
pub stat : STAT , _reserved7 : [u8 ; 0x07e8]
, # [doc = "0x1000 - Clock Divider"]
pub clkdiv : CLKDIV , _reserved8 : [u8 ; 0x04]
, # [doc = "0x1008 - Clock Select for Ultra Low Power peripherals"]
pub clksel : CLKSEL , _reserved9 : [u8 ; 0x0c]
, # [doc = "0x1018 - Peripheral Debug Control"]
pub pdbgctl : PDBGCTL , _reserved10 : [u8 ; 0x04]
, # [doc = "0x1020 - Interrupt index"]
pub iidx : IIDX , _reserved11 : [u8 ; 0x04]
, # [doc = "0x1028 - Interrupt mask"]
pub imask : IMASK , _reserved12 : [u8 ; 0x04]
, # [doc = "0x1030 - Raw interrupt status"]
pub ris : RIS , _reserved13 : [u8 ; 0x04]
, # [doc = "0x1038 - Masked interrupt status"]
pub mis : MIS , _reserved14 : [u8 ; 0x04]
, # [doc = "0x1040 - Interrupt set"]
pub iset : ISET , _reserved15 : [u8 ; 0x04]
, # [doc = "0x1048 - Interrupt clear"]
pub iclr : ICLR , _reserved16 : [u8 ; 0x94]
, # [doc = "0x10e0 - Event Mode"]
pub evt_mode : EVT_MODE , _reserved17 : [u8 ; 0x18]
, # [doc = "0x10fc - Module Description"]
pub desc : DESC , # [doc = "0x1100 - CCP Direction"]
pub ccpd : CCPD , # [doc = "0x1104 - Output Disable"]
pub odis : ODIS , # [doc = "0x1108 - Counter Clock Control Register"]
pub cclkctl : CCLKCTL , # [doc = "0x110c - Clock Prescale Register"]
pub cps : CPS , # [doc = "0x1110 - Clock prescale count status register"]
pub cpsv : CPSV , # [doc = "0x1114 - Timer Cross Trigger Control Register"]
pub cttrigctl : CTTRIGCTL , _reserved24 : [u8 ; 0x04]
, # [doc = "0x111c - Timer Cross Trigger Register"]
pub cttrig : CTTRIG , _reserved25 : [u8 ; 0x06e0]
, # [doc = "0x1800 - Counter Register"]
pub ctr : CTR , # [doc = "0x1804 - Counter Control Register"]
pub ctrctl : CTRCTL , # [doc = "0x1808 - Load Register"]
pub load : LOAD , _reserved28 : [u8 ; 0x04]
, # [doc = "0x1810..0x1818 - Capture or Compare Register 0 to Capture or Compare Register 1"]
pub cc_01 : [CC_01 ; 2]
, _reserved29 : [u8 ; 0x18]
, # [doc = "0x1830..0x1838 - Capture or Compare Control Registers"]
pub ccctl_01 : [CCCTL_01 ; 2]
, _reserved30 : [u8 ; 0x18]
, # [doc = "0x1850..0x1858 - CCP Output Control Registers"]
pub octl_01 : [OCTL_01 ; 2]
, _reserved31 : [u8 ; 0x18]
, # [doc = "0x1870..0x1878 - Capture or Compare Action Registers"]
pub ccact_01 : [CCACT_01 ; 2]
, _reserved32 : [u8 ; 0x08]
, # [doc = "0x1880..0x1888 - Input Filter Control Register"]
pub ifctl_01 : [IFCTL_01 ; 2]
, _reserved33 : [u8 ; 0x28]
, # [doc = "0x18b0 - Trigger Select"]
pub tsel : TSEL , } # [doc = "FSUB_0 (rw) register accessor: Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_0`]
module"]
pub type FSUB_0 = crate :: Reg < fsub_0 :: FSUB_0_SPEC > ; # [doc = "Subsciber Port 0"]
pub mod fsub_0 { # [doc = "Register `FSUB_0` reader"]
pub type R = crate :: R < FSUB_0_SPEC > ; # [doc = "Register `FSUB_0` writer"]
pub type W = crate :: W < FSUB_0_SPEC > ; # [doc = "Field `FSUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_R = crate :: FieldReader < FSUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_0_CHANID_UNCONNECTED = 0 , } impl From < FSUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_0_CHANID_A { type Ux = u8 ; } impl FSUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_0_CHANID_A > { match self . bits { 0 => Some (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_0_chanid_unconnected (& self) -> bool { * self == FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_0_CHANID_A :: FSUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_0_chanid (& self) -> FSUB_0_CHANID_R { FSUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_0_chanid (& mut self) -> FSUB_0_CHANID_W < FSUB_0_SPEC , 0 > { FSUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subsciber Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_0_SPEC ; impl crate :: RegisterSpec for FSUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_0::R`](R) reader structure"]
impl crate :: Readable for FSUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_0::W`](W) writer structure"]
impl crate :: Writable for FSUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_0 to value 0"]
impl crate :: Resettable for FSUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FSUB_1 (rw) register accessor: Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsub_1`]
module"]
pub type FSUB_1 = crate :: Reg < fsub_1 :: FSUB_1_SPEC > ; # [doc = "Subscriber Port 1"]
pub mod fsub_1 { # [doc = "Register `FSUB_1` reader"]
pub type R = crate :: R < FSUB_1_SPEC > ; # [doc = "Register `FSUB_1` writer"]
pub type W = crate :: W < FSUB_1_SPEC > ; # [doc = "Field `FSUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_R = crate :: FieldReader < FSUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FSUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FSUB_1_CHANID_UNCONNECTED = 0 , } impl From < FSUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FSUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FSUB_1_CHANID_A { type Ux = u8 ; } impl FSUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FSUB_1_CHANID_A > { match self . bits { 0 => Some (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fsub_1_chanid_unconnected (& self) -> bool { * self == FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FSUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FSUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FSUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FSUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fsub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FSUB_1_CHANID_A :: FSUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fsub_1_chanid (& self) -> FSUB_1_CHANID_R { FSUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fsub_1_chanid (& mut self) -> FSUB_1_CHANID_W < FSUB_1_SPEC , 0 > { FSUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Subscriber Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FSUB_1_SPEC ; impl crate :: RegisterSpec for FSUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fsub_1::R`](R) reader structure"]
impl crate :: Readable for FSUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fsub_1::W`](W) writer structure"]
impl crate :: Writable for FSUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FSUB_1 to value 0"]
impl crate :: Resettable for FSUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_0 (rw) register accessor: Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_0`]
module"]
pub type FPUB_0 = crate :: Reg < fpub_0 :: FPUB_0_SPEC > ; # [doc = "Publisher Port 0"]
pub mod fpub_0 { # [doc = "Register `FPUB_0` reader"]
pub type R = crate :: R < FPUB_0_SPEC > ; # [doc = "Register `FPUB_0` writer"]
pub type W = crate :: W < FPUB_0_SPEC > ; # [doc = "Field `FPUB_0_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_R = crate :: FieldReader < FPUB_0_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_0_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_0_CHANID_UNCONNECTED = 0 , } impl From < FPUB_0_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_0_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_0_CHANID_A { type Ux = u8 ; } impl FPUB_0_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_0_CHANID_A > { match self . bits { 0 => Some (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_0_chanid_unconnected (& self) -> bool { * self == FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_0_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_0_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_0_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_0_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_0_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_0_CHANID_A :: FPUB_0_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_0_chanid (& self) -> FPUB_0_CHANID_R { FPUB_0_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_0_chanid (& mut self) -> FPUB_0_CHANID_W < FPUB_0_SPEC , 0 > { FPUB_0_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_0_SPEC ; impl crate :: RegisterSpec for FPUB_0_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_0::R`](R) reader structure"]
impl crate :: Readable for FPUB_0_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_0::W`](W) writer structure"]
impl crate :: Writable for FPUB_0_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_0 to value 0"]
impl crate :: Resettable for FPUB_0_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "FPUB_1 (rw) register accessor: Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fpub_1`]
module"]
pub type FPUB_1 = crate :: Reg < fpub_1 :: FPUB_1_SPEC > ; # [doc = "Publisher Port 1"]
pub mod fpub_1 { # [doc = "Register `FPUB_1` reader"]
pub type R = crate :: R < FPUB_1_SPEC > ; # [doc = "Register `FPUB_1` writer"]
pub type W = crate :: W < FPUB_1_SPEC > ; # [doc = "Field `FPUB_1_CHANID` reader - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_R = crate :: FieldReader < FPUB_1_CHANID_A > ; # [doc = "0 = disconnected. 1-15 = connected to channelID = CHANID.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum FPUB_1_CHANID_A { # [doc = "0: UNCONNECTED"]
FPUB_1_CHANID_UNCONNECTED = 0 , } impl From < FPUB_1_CHANID_A > for u8 { # [inline (always)]
fn from (variant : FPUB_1_CHANID_A) -> Self { variant as _ } } impl crate :: FieldSpec for FPUB_1_CHANID_A { type Ux = u8 ; } impl FPUB_1_CHANID_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < FPUB_1_CHANID_A > { match self . bits { 0 => Some (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) , _ => None , } } # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn is_fpub_1_chanid_unconnected (& self) -> bool { * self == FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED } } # [doc = "Field `FPUB_1_CHANID` writer - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
pub type FPUB_1_CHANID_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , FPUB_1_CHANID_A > ; impl < 'a , REG , const O : u8 > FPUB_1_CHANID_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "UNCONNECTED"]
# [inline (always)]
pub fn fpub_1_chanid_unconnected (self) -> & 'a mut crate :: W < REG > { self . variant (FPUB_1_CHANID_A :: FPUB_1_CHANID_UNCONNECTED) } } impl R { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
pub fn fpub_1_chanid (& self) -> FPUB_1_CHANID_R { FPUB_1_CHANID_R :: new ((self . bits & 3) as u8) } } impl W { # [doc = "Bits 0:1 - 0 = disconnected. 1-15 = connected to channelID = CHANID."]
# [inline (always)]
# [must_use]
pub fn fpub_1_chanid (& mut self) -> FPUB_1_CHANID_W < FPUB_1_SPEC , 0 > { FPUB_1_CHANID_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Publisher Port 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fpub_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fpub_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FPUB_1_SPEC ; impl crate :: RegisterSpec for FPUB_1_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`fpub_1::R`](R) reader structure"]
impl crate :: Readable for FPUB_1_SPEC { } # [doc = "`write(|w| ..)` method takes [`fpub_1::W`](W) writer structure"]
impl crate :: Writable for FPUB_1_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets FPUB_1 to value 0"]
impl crate :: Resettable for FPUB_1_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PWREN (rw) register accessor: Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwren`]
module"]
pub type PWREN = crate :: Reg < pwren :: PWREN_SPEC > ; # [doc = "Power enable"]
pub mod pwren { # [doc = "Register `PWREN` reader"]
pub type R = crate :: R < PWREN_SPEC > ; # [doc = "Register `PWREN` writer"]
pub type W = crate :: W < PWREN_SPEC > ; # [doc = "Field `PWREN_ENABLE` reader - Enable the power"]
pub type PWREN_ENABLE_R = crate :: BitReader < PWREN_ENABLE_A > ; # [doc = "Enable the power\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PWREN_ENABLE_A { # [doc = "0: DISABLE"]
PWREN_ENABLE_DISABLE = 0 , # [doc = "1: ENABLE"]
PWREN_ENABLE_ENABLE = 1 , } impl From < PWREN_ENABLE_A > for bool { # [inline (always)]
fn from (variant : PWREN_ENABLE_A) -> Self { variant as u8 != 0 } } impl PWREN_ENABLE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PWREN_ENABLE_A { match self . bits { false => PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE , true => PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_pwren_enable_disable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_pwren_enable_enable (& self) -> bool { * self == PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE } } # [doc = "Field `PWREN_ENABLE` writer - Enable the power"]
pub type PWREN_ENABLE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PWREN_ENABLE_A > ; impl < 'a , REG , const O : u8 > PWREN_ENABLE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn pwren_enable_disable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn pwren_enable_enable (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_ENABLE_A :: PWREN_ENABLE_ENABLE) } } # [doc = "KEY to allow Power State Change\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum PWREN_KEY_AW { # [doc = "38: _TO_UNLOCK_W_"]
PWREN_KEY_UNLOCK_W = 38 , } impl From < PWREN_KEY_AW > for u8 { # [inline (always)]
fn from (variant : PWREN_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for PWREN_KEY_AW { type Ux = u8 ; } # [doc = "Field `PWREN_KEY` writer - KEY to allow Power State Change"]
pub type PWREN_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , PWREN_KEY_AW > ; impl < 'a , REG , const O : u8 > PWREN_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn pwren_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (PWREN_KEY_AW :: PWREN_KEY_UNLOCK_W) } } impl R { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
pub fn pwren_enable (& self) -> PWREN_ENABLE_R { PWREN_ENABLE_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Enable the power"]
# [inline (always)]
# [must_use]
pub fn pwren_enable (& mut self) -> PWREN_ENABLE_W < PWREN_SPEC , 0 > { PWREN_ENABLE_W :: new (self) } # [doc = "Bits 24:31 - KEY to allow Power State Change"]
# [inline (always)]
# [must_use]
pub fn pwren_key (& mut self) -> PWREN_KEY_W < PWREN_SPEC , 24 > { PWREN_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Power enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pwren::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pwren::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PWREN_SPEC ; impl crate :: RegisterSpec for PWREN_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pwren::R`](R) reader structure"]
impl crate :: Readable for PWREN_SPEC { } # [doc = "`write(|w| ..)` method takes [`pwren::W`](W) writer structure"]
impl crate :: Writable for PWREN_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PWREN to value 0"]
impl crate :: Resettable for PWREN_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RSTCTL (w) register accessor: Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rstctl`]
module"]
pub type RSTCTL = crate :: Reg < rstctl :: RSTCTL_SPEC > ; # [doc = "Reset Control"]
pub mod rstctl { # [doc = "Register `RSTCTL` writer"]
pub type W = crate :: W < RSTCTL_SPEC > ; # [doc = "Assert reset to the peripheral\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETASSERT_AW { # [doc = "0: NOP"]
RSTCTL_RESETASSERT_NOP = 0 , # [doc = "1: ASSERT"]
RSTCTL_RESETASSERT_ASSERT = 1 , } impl From < RSTCTL_RESETASSERT_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETASSERT_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETASSERT` writer - Assert reset to the peripheral"]
pub type RSTCTL_RESETASSERT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETASSERT_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETASSERT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetassert_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_NOP) } # [doc = "ASSERT"]
# [inline (always)]
pub fn rstctl_resetassert_assert (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETASSERT_AW :: RSTCTL_RESETASSERT_ASSERT) } } # [doc = "Clear the RESETSTKY bit in the STAT register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RSTCTL_RESETSTKYCLR_AW { # [doc = "0: NOP"]
RSTCTL_RESETSTKYCLR_NOP = 0 , # [doc = "1: CLR"]
RSTCTL_RESETSTKYCLR_CLR = 1 , } impl From < RSTCTL_RESETSTKYCLR_AW > for bool { # [inline (always)]
fn from (variant : RSTCTL_RESETSTKYCLR_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `RSTCTL_RESETSTKYCLR` writer - Clear the RESETSTKY bit in the STAT register"]
pub type RSTCTL_RESETSTKYCLR_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , RSTCTL_RESETSTKYCLR_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_RESETSTKYCLR_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOP"]
# [inline (always)]
pub fn rstctl_resetstkyclr_nop (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_NOP) } # [doc = "CLR"]
# [inline (always)]
pub fn rstctl_resetstkyclr_clr (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_RESETSTKYCLR_AW :: RSTCTL_RESETSTKYCLR_CLR) } } # [doc = "Unlock key\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum RSTCTL_KEY_AW { # [doc = "177: _TO_UNLOCK_W_"]
RSTCTL_KEY_UNLOCK_W = 177 , } impl From < RSTCTL_KEY_AW > for u8 { # [inline (always)]
fn from (variant : RSTCTL_KEY_AW) -> Self { variant as _ } } impl crate :: FieldSpec for RSTCTL_KEY_AW { type Ux = u8 ; } # [doc = "Field `RSTCTL_KEY` writer - Unlock key"]
pub type RSTCTL_KEY_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O , RSTCTL_KEY_AW > ; impl < 'a , REG , const O : u8 > RSTCTL_KEY_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_TO_UNLOCK_W_"]
# [inline (always)]
pub fn rstctl_key_unlock_w (self) -> & 'a mut crate :: W < REG > { self . variant (RSTCTL_KEY_AW :: RSTCTL_KEY_UNLOCK_W) } } impl W { # [doc = "Bit 0 - Assert reset to the peripheral"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetassert (& mut self) -> RSTCTL_RESETASSERT_W < RSTCTL_SPEC , 0 > { RSTCTL_RESETASSERT_W :: new (self) } # [doc = "Bit 1 - Clear the RESETSTKY bit in the STAT register"]
# [inline (always)]
# [must_use]
pub fn rstctl_resetstkyclr (& mut self) -> RSTCTL_RESETSTKYCLR_W < RSTCTL_SPEC , 1 > { RSTCTL_RESETSTKYCLR_W :: new (self) } # [doc = "Bits 24:31 - Unlock key"]
# [inline (always)]
# [must_use]
pub fn rstctl_key (& mut self) -> RSTCTL_KEY_W < RSTCTL_SPEC , 24 > { RSTCTL_KEY_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Reset Control\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rstctl::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RSTCTL_SPEC ; impl crate :: RegisterSpec for RSTCTL_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`rstctl::W`](W) writer structure"]
impl crate :: Writable for RSTCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets RSTCTL to value 0"]
impl crate :: Resettable for RSTCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "STAT (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@stat`]
module"]
pub type STAT = crate :: Reg < stat :: STAT_SPEC > ; # [doc = "Status Register"]
pub mod stat { # [doc = "Register `STAT` reader"]
pub type R = crate :: R < STAT_SPEC > ; # [doc = "Field `STAT_RESETSTKY` reader - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
pub type STAT_RESETSTKY_R = crate :: BitReader < STAT_RESETSTKY_A > ; # [doc = "This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum STAT_RESETSTKY_A { # [doc = "0: NORES"]
STAT_RESETSTKY_NORES = 0 , # [doc = "1: RESET"]
STAT_RESETSTKY_RESET = 1 , } impl From < STAT_RESETSTKY_A > for bool { # [inline (always)]
fn from (variant : STAT_RESETSTKY_A) -> Self { variant as u8 != 0 } } impl STAT_RESETSTKY_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> STAT_RESETSTKY_A { match self . bits { false => STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES , true => STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET , } } # [doc = "NORES"]
# [inline (always)]
pub fn is_stat_resetstky_nores (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_NORES } # [doc = "RESET"]
# [inline (always)]
pub fn is_stat_resetstky_reset (& self) -> bool { * self == STAT_RESETSTKY_A :: STAT_RESETSTKY_RESET } } impl R { # [doc = "Bit 16 - This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register"]
# [inline (always)]
pub fn stat_resetstky (& self) -> STAT_RESETSTKY_R { STAT_RESETSTKY_R :: new (((self . bits >> 16) & 1) != 0) } } # [doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stat::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct STAT_SPEC ; impl crate :: RegisterSpec for STAT_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`stat::R`](R) reader structure"]
impl crate :: Readable for STAT_SPEC { } # [doc = "`reset()` method sets STAT to value 0"]
impl crate :: Resettable for STAT_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKDIV (rw) register accessor: Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
module"]
pub type CLKDIV = crate :: Reg < clkdiv :: CLKDIV_SPEC > ; # [doc = "Clock Divider"]
pub mod clkdiv { # [doc = "Register `CLKDIV` reader"]
pub type R = crate :: R < CLKDIV_SPEC > ; # [doc = "Register `CLKDIV` writer"]
pub type W = crate :: W < CLKDIV_SPEC > ; # [doc = "Field `CLKDIV_RATIO` reader - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_R = crate :: FieldReader < CLKDIV_RATIO_A > ; # [doc = "Selects divide ratio of module clock\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CLKDIV_RATIO_A { # [doc = "0: DIV_BY_1"]
CLKDIV_RATIO_DIV_BY_1 = 0 , # [doc = "1: DIV_BY_2"]
CLKDIV_RATIO_DIV_BY_2 = 1 , # [doc = "2: DIV_BY_3"]
CLKDIV_RATIO_DIV_BY_3 = 2 , # [doc = "3: DIV_BY_4"]
CLKDIV_RATIO_DIV_BY_4 = 3 , # [doc = "4: DIV_BY_5"]
CLKDIV_RATIO_DIV_BY_5 = 4 , # [doc = "5: DIV_BY_6"]
CLKDIV_RATIO_DIV_BY_6 = 5 , # [doc = "6: DIV_BY_7"]
CLKDIV_RATIO_DIV_BY_7 = 6 , # [doc = "7: DIV_BY_8"]
CLKDIV_RATIO_DIV_BY_8 = 7 , } impl From < CLKDIV_RATIO_A > for u8 { # [inline (always)]
fn from (variant : CLKDIV_RATIO_A) -> Self { variant as _ } } impl crate :: FieldSpec for CLKDIV_RATIO_A { type Ux = u8 ; } impl CLKDIV_RATIO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKDIV_RATIO_A { match self . bits { 0 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 , 1 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 , 2 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 , 3 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 , 4 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 , 5 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 , 6 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 , 7 => CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 , _ => unreachable ! () , } } # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_1 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1 } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_2 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2 } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_3 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3 } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_4 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4 } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_5 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5 } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_6 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6 } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_7 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7 } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn is_clkdiv_ratio_div_by_8 (& self) -> bool { * self == CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8 } } # [doc = "Field `CLKDIV_RATIO` writer - Selects divide ratio of module clock"]
pub type CLKDIV_RATIO_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 3 , O , CLKDIV_RATIO_A > ; impl < 'a , REG , const O : u8 > CLKDIV_RATIO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DIV_BY_1"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_1) } # [doc = "DIV_BY_2"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_2) } # [doc = "DIV_BY_3"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_3) } # [doc = "DIV_BY_4"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_4) } # [doc = "DIV_BY_5"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_5 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_5) } # [doc = "DIV_BY_6"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_6 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_6) } # [doc = "DIV_BY_7"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_7 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_7) } # [doc = "DIV_BY_8"]
# [inline (always)]
pub fn clkdiv_ratio_div_by_8 (self) -> & 'a mut crate :: W < REG > { self . variant (CLKDIV_RATIO_A :: CLKDIV_RATIO_DIV_BY_8) } } impl R { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
pub fn clkdiv_ratio (& self) -> CLKDIV_RATIO_R { CLKDIV_RATIO_R :: new ((self . bits & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Selects divide ratio of module clock"]
# [inline (always)]
# [must_use]
pub fn clkdiv_ratio (& mut self) -> CLKDIV_RATIO_W < CLKDIV_SPEC , 0 > { CLKDIV_RATIO_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKDIV_SPEC ; impl crate :: RegisterSpec for CLKDIV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clkdiv::R`](R) reader structure"]
impl crate :: Readable for CLKDIV_SPEC { } # [doc = "`write(|w| ..)` method takes [`clkdiv::W`](W) writer structure"]
impl crate :: Writable for CLKDIV_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKDIV to value 0"]
impl crate :: Resettable for CLKDIV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CLKSEL (rw) register accessor: Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clksel`]
module"]
pub type CLKSEL = crate :: Reg < clksel :: CLKSEL_SPEC > ; # [doc = "Clock Select for Ultra Low Power peripherals"]
pub mod clksel { # [doc = "Register `CLKSEL` reader"]
pub type R = crate :: R < CLKSEL_SPEC > ; # [doc = "Register `CLKSEL` writer"]
pub type W = crate :: W < CLKSEL_SPEC > ; # [doc = "Field `CLKSEL_LFCLK_SEL` reader - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_R = crate :: BitReader < CLKSEL_LFCLK_SEL_A > ; # [doc = "Selects LFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_LFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_LFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_LFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_LFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_LFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_LFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_LFCLK_SEL_A { match self . bits { false => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE , true => CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_disable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_lfclk_sel_enable (& self) -> bool { * self == CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_LFCLK_SEL` writer - Selects LFCLK as clock source if enabled"]
pub type CLKSEL_LFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_LFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_LFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_lfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_LFCLK_SEL_A :: CLKSEL_LFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_MFCLK_SEL` reader - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_R = crate :: BitReader < CLKSEL_MFCLK_SEL_A > ; # [doc = "Selects MFCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_MFCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_MFCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_MFCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_MFCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_MFCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_MFCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_MFCLK_SEL_A { match self . bits { false => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE , true => CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_disable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_mfclk_sel_enable (& self) -> bool { * self == CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_MFCLK_SEL` writer - Selects MFCLK as clock source if enabled"]
pub type CLKSEL_MFCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_MFCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_MFCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_mfclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_MFCLK_SEL_A :: CLKSEL_MFCLK_SEL_ENABLE) } } # [doc = "Field `CLKSEL_BUSCLK_SEL` reader - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_R = crate :: BitReader < CLKSEL_BUSCLK_SEL_A > ; # [doc = "Selects BUSCLK as clock source if enabled\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CLKSEL_BUSCLK_SEL_A { # [doc = "0: DISABLE"]
CLKSEL_BUSCLK_SEL_DISABLE = 0 , # [doc = "1: ENABLE"]
CLKSEL_BUSCLK_SEL_ENABLE = 1 , } impl From < CLKSEL_BUSCLK_SEL_A > for bool { # [inline (always)]
fn from (variant : CLKSEL_BUSCLK_SEL_A) -> Self { variant as u8 != 0 } } impl CLKSEL_BUSCLK_SEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CLKSEL_BUSCLK_SEL_A { match self . bits { false => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE , true => CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_disable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_clksel_busclk_sel_enable (& self) -> bool { * self == CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE } } # [doc = "Field `CLKSEL_BUSCLK_SEL` writer - Selects BUSCLK as clock source if enabled"]
pub type CLKSEL_BUSCLK_SEL_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CLKSEL_BUSCLK_SEL_A > ; impl < 'a , REG , const O : u8 > CLKSEL_BUSCLK_SEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_disable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_DISABLE) } # [doc = "ENABLE"]
# [inline (always)]
pub fn clksel_busclk_sel_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CLKSEL_BUSCLK_SEL_A :: CLKSEL_BUSCLK_SEL_ENABLE) } } impl R { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_lfclk_sel (& self) -> CLKSEL_LFCLK_SEL_R { CLKSEL_LFCLK_SEL_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_mfclk_sel (& self) -> CLKSEL_MFCLK_SEL_R { CLKSEL_MFCLK_SEL_R :: new (((self . bits >> 2) & 1) != 0) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
pub fn clksel_busclk_sel (& self) -> CLKSEL_BUSCLK_SEL_R { CLKSEL_BUSCLK_SEL_R :: new (((self . bits >> 3) & 1) != 0) } } impl W { # [doc = "Bit 1 - Selects LFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_lfclk_sel (& mut self) -> CLKSEL_LFCLK_SEL_W < CLKSEL_SPEC , 1 > { CLKSEL_LFCLK_SEL_W :: new (self) } # [doc = "Bit 2 - Selects MFCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_mfclk_sel (& mut self) -> CLKSEL_MFCLK_SEL_W < CLKSEL_SPEC , 2 > { CLKSEL_MFCLK_SEL_W :: new (self) } # [doc = "Bit 3 - Selects BUSCLK as clock source if enabled"]
# [inline (always)]
# [must_use]
pub fn clksel_busclk_sel (& mut self) -> CLKSEL_BUSCLK_SEL_W < CLKSEL_SPEC , 3 > { CLKSEL_BUSCLK_SEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Select for Ultra Low Power peripherals\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clksel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clksel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CLKSEL_SPEC ; impl crate :: RegisterSpec for CLKSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`clksel::R`](R) reader structure"]
impl crate :: Readable for CLKSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`clksel::W`](W) writer structure"]
impl crate :: Writable for CLKSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CLKSEL to value 0"]
impl crate :: Resettable for CLKSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "PDBGCTL (rw) register accessor: Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pdbgctl`]
module"]
pub type PDBGCTL = crate :: Reg < pdbgctl :: PDBGCTL_SPEC > ; # [doc = "Peripheral Debug Control"]
pub mod pdbgctl { # [doc = "Register `PDBGCTL` reader"]
pub type R = crate :: R < PDBGCTL_SPEC > ; # [doc = "Register `PDBGCTL` writer"]
pub type W = crate :: W < PDBGCTL_SPEC > ; # [doc = "Field `PDBGCTL_FREE` reader - Free run control"]
pub type PDBGCTL_FREE_R = crate :: BitReader < PDBGCTL_FREE_A > ; # [doc = "Free run control\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_FREE_A { # [doc = "0: STOP"]
PDBGCTL_FREE_STOP = 0 , # [doc = "1: RUN"]
PDBGCTL_FREE_RUN = 1 , } impl From < PDBGCTL_FREE_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_FREE_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_FREE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_FREE_A { match self . bits { false => PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP , true => PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN , } } # [doc = "STOP"]
# [inline (always)]
pub fn is_pdbgctl_free_stop (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP } # [doc = "RUN"]
# [inline (always)]
pub fn is_pdbgctl_free_run (& self) -> bool { * self == PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN } } # [doc = "Field `PDBGCTL_FREE` writer - Free run control"]
pub type PDBGCTL_FREE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_FREE_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_FREE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "STOP"]
# [inline (always)]
pub fn pdbgctl_free_stop (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_STOP) } # [doc = "RUN"]
# [inline (always)]
pub fn pdbgctl_free_run (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_FREE_A :: PDBGCTL_FREE_RUN) } } # [doc = "Field `PDBGCTL_SOFT` reader - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_R = crate :: BitReader < PDBGCTL_SOFT_A > ; # [doc = "Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum PDBGCTL_SOFT_A { # [doc = "0: IMMEDIATE"]
PDBGCTL_SOFT_IMMEDIATE = 0 , # [doc = "1: DELAYED"]
PDBGCTL_SOFT_DELAYED = 1 , } impl From < PDBGCTL_SOFT_A > for bool { # [inline (always)]
fn from (variant : PDBGCTL_SOFT_A) -> Self { variant as u8 != 0 } } impl PDBGCTL_SOFT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> PDBGCTL_SOFT_A { match self . bits { false => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE , true => PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED , } } # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn is_pdbgctl_soft_immediate (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE } # [doc = "DELAYED"]
# [inline (always)]
pub fn is_pdbgctl_soft_delayed (& self) -> bool { * self == PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED } } # [doc = "Field `PDBGCTL_SOFT` writer - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
pub type PDBGCTL_SOFT_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , PDBGCTL_SOFT_A > ; impl < 'a , REG , const O : u8 > PDBGCTL_SOFT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "IMMEDIATE"]
# [inline (always)]
pub fn pdbgctl_soft_immediate (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_IMMEDIATE) } # [doc = "DELAYED"]
# [inline (always)]
pub fn pdbgctl_soft_delayed (self) -> & 'a mut crate :: W < REG > { self . variant (PDBGCTL_SOFT_A :: PDBGCTL_SOFT_DELAYED) } } impl R { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
pub fn pdbgctl_free (& self) -> PDBGCTL_FREE_R { PDBGCTL_FREE_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
pub fn pdbgctl_soft (& self) -> PDBGCTL_SOFT_R { PDBGCTL_SOFT_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Free run control"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_free (& mut self) -> PDBGCTL_FREE_W < PDBGCTL_SPEC , 0 > { PDBGCTL_FREE_W :: new (self) } # [doc = "Bit 1 - Soft halt boundary control. This function is only available, if \\[FREE\\]
is set to 'STOP'"]
# [inline (always)]
# [must_use]
pub fn pdbgctl_soft (& mut self) -> PDBGCTL_SOFT_W < PDBGCTL_SPEC , 1 > { PDBGCTL_SOFT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Peripheral Debug Control\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pdbgctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pdbgctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PDBGCTL_SPEC ; impl crate :: RegisterSpec for PDBGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`pdbgctl::R`](R) reader structure"]
impl crate :: Readable for PDBGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`pdbgctl::W`](W) writer structure"]
impl crate :: Writable for PDBGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets PDBGCTL to value 0"]
impl crate :: Resettable for PDBGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IIDX (r) register accessor: Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iidx`]
module"]
pub type IIDX = crate :: Reg < iidx :: IIDX_SPEC > ; # [doc = "Interrupt index"]
pub mod iidx { # [doc = "Register `IIDX` reader"]
pub type R = crate :: R < IIDX_SPEC > ; # [doc = "Field `IIDX_STAT` reader - Interrupt index status"]
pub type IIDX_STAT_R = crate :: FieldReader < IIDX_STAT_A > ; # [doc = "Interrupt index status\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IIDX_STAT_A { # [doc = "0: NO_INTR"]
IIDX_STAT_NO_INTR = 0 , # [doc = "1: Z"]
IIDX_STAT_Z = 1 , # [doc = "2: L"]
IIDX_STAT_L = 2 , # [doc = "5: CCD0"]
IIDX_STAT_CCD0 = 5 , # [doc = "6: CCD1"]
IIDX_STAT_CCD1 = 6 , # [doc = "7: CCD2"]
IIDX_STAT_CCD2 = 7 , # [doc = "8: CCD3"]
IIDX_STAT_CCD3 = 8 , # [doc = "9: CCU0"]
IIDX_STAT_CCU0 = 9 , # [doc = "10: CCU1"]
IIDX_STAT_CCU1 = 10 , # [doc = "11: CCU2"]
IIDX_STAT_CCU2 = 11 , # [doc = "12: CCU3"]
IIDX_STAT_CCU3 = 12 , # [doc = "13: CCD4"]
IIDX_STAT_CCD4 = 13 , # [doc = "14: CCD5"]
IIDX_STAT_CCD5 = 14 , # [doc = "15: CCU4"]
IIDX_STAT_CCU4 = 15 , # [doc = "16: CCU5"]
IIDX_STAT_CCU5 = 16 , # [doc = "25: F"]
IIDX_STAT_F = 25 , # [doc = "26: TOV"]
IIDX_STAT_TOV = 26 , # [doc = "27: REPC"]
IIDX_STAT_REPC = 27 , # [doc = "28: DC"]
IIDX_STAT_DC = 28 , # [doc = "29: QEIERR"]
IIDX_STAT_QEIERR = 29 , } impl From < IIDX_STAT_A > for u8 { # [inline (always)]
fn from (variant : IIDX_STAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for IIDX_STAT_A { type Ux = u8 ; } impl IIDX_STAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IIDX_STAT_A > { match self . bits { 0 => Some (IIDX_STAT_A :: IIDX_STAT_NO_INTR) , 1 => Some (IIDX_STAT_A :: IIDX_STAT_Z) , 2 => Some (IIDX_STAT_A :: IIDX_STAT_L) , 5 => Some (IIDX_STAT_A :: IIDX_STAT_CCD0) , 6 => Some (IIDX_STAT_A :: IIDX_STAT_CCD1) , 7 => Some (IIDX_STAT_A :: IIDX_STAT_CCD2) , 8 => Some (IIDX_STAT_A :: IIDX_STAT_CCD3) , 9 => Some (IIDX_STAT_A :: IIDX_STAT_CCU0) , 10 => Some (IIDX_STAT_A :: IIDX_STAT_CCU1) , 11 => Some (IIDX_STAT_A :: IIDX_STAT_CCU2) , 12 => Some (IIDX_STAT_A :: IIDX_STAT_CCU3) , 13 => Some (IIDX_STAT_A :: IIDX_STAT_CCD4) , 14 => Some (IIDX_STAT_A :: IIDX_STAT_CCD5) , 15 => Some (IIDX_STAT_A :: IIDX_STAT_CCU4) , 16 => Some (IIDX_STAT_A :: IIDX_STAT_CCU5) , 25 => Some (IIDX_STAT_A :: IIDX_STAT_F) , 26 => Some (IIDX_STAT_A :: IIDX_STAT_TOV) , 27 => Some (IIDX_STAT_A :: IIDX_STAT_REPC) , 28 => Some (IIDX_STAT_A :: IIDX_STAT_DC) , 29 => Some (IIDX_STAT_A :: IIDX_STAT_QEIERR) , _ => None , } } # [doc = "NO_INTR"]
# [inline (always)]
pub fn is_iidx_stat_no_intr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_NO_INTR } # [doc = "Z"]
# [inline (always)]
pub fn is_iidx_stat_z (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_Z } # [doc = "L"]
# [inline (always)]
pub fn is_iidx_stat_l (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_iidx_stat_ccd0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_iidx_stat_ccd1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_iidx_stat_ccd2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_iidx_stat_ccd3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_iidx_stat_ccu0 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_iidx_stat_ccu1 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_iidx_stat_ccu2 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_iidx_stat_ccu3 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU3 } # [doc = "CCD4"]
# [inline (always)]
pub fn is_iidx_stat_ccd4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD4 } # [doc = "CCD5"]
# [inline (always)]
pub fn is_iidx_stat_ccd5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCD5 } # [doc = "CCU4"]
# [inline (always)]
pub fn is_iidx_stat_ccu4 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU4 } # [doc = "CCU5"]
# [inline (always)]
pub fn is_iidx_stat_ccu5 (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_CCU5 } # [doc = "F"]
# [inline (always)]
pub fn is_iidx_stat_f (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_F } # [doc = "TOV"]
# [inline (always)]
pub fn is_iidx_stat_tov (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_TOV } # [doc = "REPC"]
# [inline (always)]
pub fn is_iidx_stat_repc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_REPC } # [doc = "DC"]
# [inline (always)]
pub fn is_iidx_stat_dc (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_DC } # [doc = "QEIERR"]
# [inline (always)]
pub fn is_iidx_stat_qeierr (& self) -> bool { * self == IIDX_STAT_A :: IIDX_STAT_QEIERR } } impl R { # [doc = "Bits 0:7 - Interrupt index status"]
# [inline (always)]
pub fn iidx_stat (& self) -> IIDX_STAT_R { IIDX_STAT_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Interrupt index\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iidx::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IIDX_SPEC ; impl crate :: RegisterSpec for IIDX_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`iidx::R`](R) reader structure"]
impl crate :: Readable for IIDX_SPEC { } # [doc = "`reset()` method sets IIDX to value 0"]
impl crate :: Resettable for IIDX_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IMASK (rw) register accessor: Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@imask`]
module"]
pub type IMASK = crate :: Reg < imask :: IMASK_SPEC > ; # [doc = "Interrupt mask"]
pub mod imask { # [doc = "Register `IMASK` reader"]
pub type R = crate :: R < IMASK_SPEC > ; # [doc = "Register `IMASK` writer"]
pub type W = crate :: W < IMASK_SPEC > ; # [doc = "Field `IMASK_Z` reader - Zero Event mask"]
pub type IMASK_Z_R = crate :: BitReader < IMASK_Z_A > ; # [doc = "Zero Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_Z_A { # [doc = "0: CLR"]
IMASK_Z_CLR = 0 , # [doc = "1: SET"]
IMASK_Z_SET = 1 , } impl From < IMASK_Z_A > for bool { # [inline (always)]
fn from (variant : IMASK_Z_A) -> Self { variant as u8 != 0 } } impl IMASK_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_Z_A { match self . bits { false => IMASK_Z_A :: IMASK_Z_CLR , true => IMASK_Z_A :: IMASK_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_z_clr (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_z_set (& self) -> bool { * self == IMASK_Z_A :: IMASK_Z_SET } } # [doc = "Field `IMASK_Z` writer - Zero Event mask"]
pub type IMASK_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_Z_A > ; impl < 'a , REG , const O : u8 > IMASK_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_Z_A :: IMASK_Z_SET) } } # [doc = "Field `IMASK_L` reader - Load Event mask"]
pub type IMASK_L_R = crate :: BitReader < IMASK_L_A > ; # [doc = "Load Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_L_A { # [doc = "0: CLR"]
IMASK_L_CLR = 0 , # [doc = "1: SET"]
IMASK_L_SET = 1 , } impl From < IMASK_L_A > for bool { # [inline (always)]
fn from (variant : IMASK_L_A) -> Self { variant as u8 != 0 } } impl IMASK_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_L_A { match self . bits { false => IMASK_L_A :: IMASK_L_CLR , true => IMASK_L_A :: IMASK_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_l_clr (& self) -> bool { * self == IMASK_L_A :: IMASK_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_l_set (& self) -> bool { * self == IMASK_L_A :: IMASK_L_SET } } # [doc = "Field `IMASK_L` writer - Load Event mask"]
pub type IMASK_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_L_A > ; impl < 'a , REG , const O : u8 > IMASK_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_L_A :: IMASK_L_SET) } } # [doc = "Field `IMASK_CCD0` reader - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_R = crate :: BitReader < IMASK_CCD0_A > ; # [doc = "Capture or Compare DN event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD0_A { # [doc = "0: CLR"]
IMASK_CCD0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD0_SET = 1 , } impl From < IMASK_CCD0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD0_A { match self . bits { false => IMASK_CCD0_A :: IMASK_CCD0_CLR , true => IMASK_CCD0_A :: IMASK_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd0_clr (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd0_set (& self) -> bool { * self == IMASK_CCD0_A :: IMASK_CCD0_SET } } # [doc = "Field `IMASK_CCD0` writer - Capture or Compare DN event mask CCP0"]
pub type IMASK_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD0_A :: IMASK_CCD0_SET) } } # [doc = "Field `IMASK_CCD1` reader - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_R = crate :: BitReader < IMASK_CCD1_A > ; # [doc = "Capture or Compare DN event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCD1_A { # [doc = "0: CLR"]
IMASK_CCD1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCD1_SET = 1 , } impl From < IMASK_CCD1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCD1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCD1_A { match self . bits { false => IMASK_CCD1_A :: IMASK_CCD1_CLR , true => IMASK_CCD1_A :: IMASK_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccd1_clr (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccd1_set (& self) -> bool { * self == IMASK_CCD1_A :: IMASK_CCD1_SET } } # [doc = "Field `IMASK_CCD1` writer - Capture or Compare DN event mask CCP1"]
pub type IMASK_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCD1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCD1_A :: IMASK_CCD1_SET) } } # [doc = "Field `IMASK_CCU0` reader - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_R = crate :: BitReader < IMASK_CCU0_A > ; # [doc = "Capture or Compare UP event mask CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU0_A { # [doc = "0: CLR"]
IMASK_CCU0_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU0_SET = 1 , } impl From < IMASK_CCU0_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU0_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU0_A { match self . bits { false => IMASK_CCU0_A :: IMASK_CCU0_CLR , true => IMASK_CCU0_A :: IMASK_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu0_clr (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu0_set (& self) -> bool { * self == IMASK_CCU0_A :: IMASK_CCU0_SET } } # [doc = "Field `IMASK_CCU0` writer - Capture or Compare UP event mask CCP0"]
pub type IMASK_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU0_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU0_A :: IMASK_CCU0_SET) } } # [doc = "Field `IMASK_CCU1` reader - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_R = crate :: BitReader < IMASK_CCU1_A > ; # [doc = "Capture or Compare UP event mask CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_CCU1_A { # [doc = "0: CLR"]
IMASK_CCU1_CLR = 0 , # [doc = "1: SET"]
IMASK_CCU1_SET = 1 , } impl From < IMASK_CCU1_A > for bool { # [inline (always)]
fn from (variant : IMASK_CCU1_A) -> Self { variant as u8 != 0 } } impl IMASK_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_CCU1_A { match self . bits { false => IMASK_CCU1_A :: IMASK_CCU1_CLR , true => IMASK_CCU1_A :: IMASK_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_ccu1_clr (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_ccu1_set (& self) -> bool { * self == IMASK_CCU1_A :: IMASK_CCU1_SET } } # [doc = "Field `IMASK_CCU1` writer - Capture or Compare UP event mask CCP1"]
pub type IMASK_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_CCU1_A > ; impl < 'a , REG , const O : u8 > IMASK_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_CCU1_A :: IMASK_CCU1_SET) } } # [doc = "Field `IMASK_TOV` reader - Trigger Overflow Event mask"]
pub type IMASK_TOV_R = crate :: BitReader < IMASK_TOV_A > ; # [doc = "Trigger Overflow Event mask\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IMASK_TOV_A { # [doc = "0: CLR"]
IMASK_TOV_CLR = 0 , # [doc = "1: SET"]
IMASK_TOV_SET = 1 , } impl From < IMASK_TOV_A > for bool { # [inline (always)]
fn from (variant : IMASK_TOV_A) -> Self { variant as u8 != 0 } } impl IMASK_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IMASK_TOV_A { match self . bits { false => IMASK_TOV_A :: IMASK_TOV_CLR , true => IMASK_TOV_A :: IMASK_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_imask_tov_clr (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_imask_tov_set (& self) -> bool { * self == IMASK_TOV_A :: IMASK_TOV_SET } } # [doc = "Field `IMASK_TOV` writer - Trigger Overflow Event mask"]
pub type IMASK_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IMASK_TOV_A > ; impl < 'a , REG , const O : u8 > IMASK_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CLR"]
# [inline (always)]
pub fn imask_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_CLR) } # [doc = "SET"]
# [inline (always)]
pub fn imask_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (IMASK_TOV_A :: IMASK_TOV_SET) } } impl R { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
pub fn imask_z (& self) -> IMASK_Z_R { IMASK_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
pub fn imask_l (& self) -> IMASK_L_R { IMASK_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
pub fn imask_ccd0 (& self) -> IMASK_CCD0_R { IMASK_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
pub fn imask_ccd1 (& self) -> IMASK_CCD1_R { IMASK_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
pub fn imask_ccu0 (& self) -> IMASK_CCU0_R { IMASK_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
pub fn imask_ccu1 (& self) -> IMASK_CCU1_R { IMASK_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
pub fn imask_tov (& self) -> IMASK_TOV_R { IMASK_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } impl W { # [doc = "Bit 0 - Zero Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_z (& mut self) -> IMASK_Z_W < IMASK_SPEC , 0 > { IMASK_Z_W :: new (self) } # [doc = "Bit 1 - Load Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_l (& mut self) -> IMASK_L_W < IMASK_SPEC , 1 > { IMASK_L_W :: new (self) } # [doc = "Bit 4 - Capture or Compare DN event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccd0 (& mut self) -> IMASK_CCD0_W < IMASK_SPEC , 4 > { IMASK_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or Compare DN event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccd1 (& mut self) -> IMASK_CCD1_W < IMASK_SPEC , 5 > { IMASK_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or Compare UP event mask CCP0"]
# [inline (always)]
# [must_use]
pub fn imask_ccu0 (& mut self) -> IMASK_CCU0_W < IMASK_SPEC , 8 > { IMASK_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or Compare UP event mask CCP1"]
# [inline (always)]
# [must_use]
pub fn imask_ccu1 (& mut self) -> IMASK_CCU1_W < IMASK_SPEC , 9 > { IMASK_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow Event mask"]
# [inline (always)]
# [must_use]
pub fn imask_tov (& mut self) -> IMASK_TOV_W < IMASK_SPEC , 25 > { IMASK_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt mask\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`imask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`imask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IMASK_SPEC ; impl crate :: RegisterSpec for IMASK_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`imask::R`](R) reader structure"]
impl crate :: Readable for IMASK_SPEC { } # [doc = "`write(|w| ..)` method takes [`imask::W`](W) writer structure"]
impl crate :: Writable for IMASK_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IMASK to value 0"]
impl crate :: Resettable for IMASK_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "RIS (r) register accessor: Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ris`]
module"]
pub type RIS = crate :: Reg < ris :: RIS_SPEC > ; # [doc = "Raw interrupt status"]
pub mod ris { # [doc = "Register `RIS` reader"]
pub type R = crate :: R < RIS_SPEC > ; # [doc = "Field `RIS_Z` reader - Zero event generated an interrupt."]
pub type RIS_Z_R = crate :: BitReader < RIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_Z_A { # [doc = "0: CLR"]
RIS_Z_CLR = 0 , # [doc = "1: SET"]
RIS_Z_SET = 1 , } impl From < RIS_Z_A > for bool { # [inline (always)]
fn from (variant : RIS_Z_A) -> Self { variant as u8 != 0 } } impl RIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_Z_A { match self . bits { false => RIS_Z_A :: RIS_Z_CLR , true => RIS_Z_A :: RIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_z_clr (& self) -> bool { * self == RIS_Z_A :: RIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_z_set (& self) -> bool { * self == RIS_Z_A :: RIS_Z_SET } } # [doc = "Field `RIS_L` reader - Load event generated an interrupt."]
pub type RIS_L_R = crate :: BitReader < RIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_L_A { # [doc = "0: CLR"]
RIS_L_CLR = 0 , # [doc = "1: SET"]
RIS_L_SET = 1 , } impl From < RIS_L_A > for bool { # [inline (always)]
fn from (variant : RIS_L_A) -> Self { variant as u8 != 0 } } impl RIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_L_A { match self . bits { false => RIS_L_A :: RIS_L_CLR , true => RIS_L_A :: RIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_l_clr (& self) -> bool { * self == RIS_L_A :: RIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_l_set (& self) -> bool { * self == RIS_L_A :: RIS_L_SET } } # [doc = "Field `RIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type RIS_CCD0_R = crate :: BitReader < RIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD0_A { # [doc = "0: CLR"]
RIS_CCD0_CLR = 0 , # [doc = "1: SET"]
RIS_CCD0_SET = 1 , } impl From < RIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD0_A) -> Self { variant as u8 != 0 } } impl RIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD0_A { match self . bits { false => RIS_CCD0_A :: RIS_CCD0_CLR , true => RIS_CCD0_A :: RIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd0_clr (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd0_set (& self) -> bool { * self == RIS_CCD0_A :: RIS_CCD0_SET } } # [doc = "Field `RIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type RIS_CCD1_R = crate :: BitReader < RIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCD1_A { # [doc = "0: CLR"]
RIS_CCD1_CLR = 0 , # [doc = "1: SET"]
RIS_CCD1_SET = 1 , } impl From < RIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCD1_A) -> Self { variant as u8 != 0 } } impl RIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCD1_A { match self . bits { false => RIS_CCD1_A :: RIS_CCD1_CLR , true => RIS_CCD1_A :: RIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccd1_clr (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccd1_set (& self) -> bool { * self == RIS_CCD1_A :: RIS_CCD1_SET } } # [doc = "Field `RIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type RIS_CCU0_R = crate :: BitReader < RIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU0_A { # [doc = "0: CLR"]
RIS_CCU0_CLR = 0 , # [doc = "1: SET"]
RIS_CCU0_SET = 1 , } impl From < RIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU0_A) -> Self { variant as u8 != 0 } } impl RIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU0_A { match self . bits { false => RIS_CCU0_A :: RIS_CCU0_CLR , true => RIS_CCU0_A :: RIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu0_clr (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu0_set (& self) -> bool { * self == RIS_CCU0_A :: RIS_CCU0_SET } } # [doc = "Field `RIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type RIS_CCU1_R = crate :: BitReader < RIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_CCU1_A { # [doc = "0: CLR"]
RIS_CCU1_CLR = 0 , # [doc = "1: SET"]
RIS_CCU1_SET = 1 , } impl From < RIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : RIS_CCU1_A) -> Self { variant as u8 != 0 } } impl RIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_CCU1_A { match self . bits { false => RIS_CCU1_A :: RIS_CCU1_CLR , true => RIS_CCU1_A :: RIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_ccu1_clr (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_ccu1_set (& self) -> bool { * self == RIS_CCU1_A :: RIS_CCU1_SET } } # [doc = "Field `RIS_TOV` reader - Trigger overflow"]
pub type RIS_TOV_R = crate :: BitReader < RIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum RIS_TOV_A { # [doc = "0: CLR"]
RIS_TOV_CLR = 0 , # [doc = "1: SET"]
RIS_TOV_SET = 1 , } impl From < RIS_TOV_A > for bool { # [inline (always)]
fn from (variant : RIS_TOV_A) -> Self { variant as u8 != 0 } } impl RIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> RIS_TOV_A { match self . bits { false => RIS_TOV_A :: RIS_TOV_CLR , true => RIS_TOV_A :: RIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_ris_tov_clr (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_ris_tov_set (& self) -> bool { * self == RIS_TOV_A :: RIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn ris_z (& self) -> RIS_Z_R { RIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn ris_l (& self) -> RIS_L_R { RIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccd0 (& self) -> RIS_CCD0_R { RIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccd1 (& self) -> RIS_CCD1_R { RIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn ris_ccu0 (& self) -> RIS_CCU0_R { RIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn ris_ccu1 (& self) -> RIS_CCU1_R { RIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn ris_tov (& self) -> RIS_TOV_R { RIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Raw interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ris::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RIS_SPEC ; impl crate :: RegisterSpec for RIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ris::R`](R) reader structure"]
impl crate :: Readable for RIS_SPEC { } # [doc = "`reset()` method sets RIS to value 0"]
impl crate :: Resettable for RIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "MIS (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mis`]
module"]
pub type MIS = crate :: Reg < mis :: MIS_SPEC > ; # [doc = "Masked interrupt status"]
pub mod mis { # [doc = "Register `MIS` reader"]
pub type R = crate :: R < MIS_SPEC > ; # [doc = "Field `MIS_Z` reader - Zero event generated an interrupt."]
pub type MIS_Z_R = crate :: BitReader < MIS_Z_A > ; # [doc = "Zero event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_Z_A { # [doc = "0: CLR"]
MIS_Z_CLR = 0 , # [doc = "1: SET"]
MIS_Z_SET = 1 , } impl From < MIS_Z_A > for bool { # [inline (always)]
fn from (variant : MIS_Z_A) -> Self { variant as u8 != 0 } } impl MIS_Z_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_Z_A { match self . bits { false => MIS_Z_A :: MIS_Z_CLR , true => MIS_Z_A :: MIS_Z_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_z_clr (& self) -> bool { * self == MIS_Z_A :: MIS_Z_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_z_set (& self) -> bool { * self == MIS_Z_A :: MIS_Z_SET } } # [doc = "Field `MIS_L` reader - Load event generated an interrupt."]
pub type MIS_L_R = crate :: BitReader < MIS_L_A > ; # [doc = "Load event generated an interrupt.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_L_A { # [doc = "0: CLR"]
MIS_L_CLR = 0 , # [doc = "1: SET"]
MIS_L_SET = 1 , } impl From < MIS_L_A > for bool { # [inline (always)]
fn from (variant : MIS_L_A) -> Self { variant as u8 != 0 } } impl MIS_L_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_L_A { match self . bits { false => MIS_L_A :: MIS_L_CLR , true => MIS_L_A :: MIS_L_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_l_clr (& self) -> bool { * self == MIS_L_A :: MIS_L_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_l_set (& self) -> bool { * self == MIS_L_A :: MIS_L_SET } } # [doc = "Field `MIS_CCD0` reader - Capture or compare down event generated an interrupt CCP0"]
pub type MIS_CCD0_R = crate :: BitReader < MIS_CCD0_A > ; # [doc = "Capture or compare down event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD0_A { # [doc = "0: CLR"]
MIS_CCD0_CLR = 0 , # [doc = "1: SET"]
MIS_CCD0_SET = 1 , } impl From < MIS_CCD0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD0_A) -> Self { variant as u8 != 0 } } impl MIS_CCD0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD0_A { match self . bits { false => MIS_CCD0_A :: MIS_CCD0_CLR , true => MIS_CCD0_A :: MIS_CCD0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd0_clr (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd0_set (& self) -> bool { * self == MIS_CCD0_A :: MIS_CCD0_SET } } # [doc = "Field `MIS_CCD1` reader - Capture or compare down event generated an interrupt CCP1"]
pub type MIS_CCD1_R = crate :: BitReader < MIS_CCD1_A > ; # [doc = "Capture or compare down event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCD1_A { # [doc = "0: CLR"]
MIS_CCD1_CLR = 0 , # [doc = "1: SET"]
MIS_CCD1_SET = 1 , } impl From < MIS_CCD1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCD1_A) -> Self { variant as u8 != 0 } } impl MIS_CCD1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCD1_A { match self . bits { false => MIS_CCD1_A :: MIS_CCD1_CLR , true => MIS_CCD1_A :: MIS_CCD1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccd1_clr (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccd1_set (& self) -> bool { * self == MIS_CCD1_A :: MIS_CCD1_SET } } # [doc = "Field `MIS_CCU0` reader - Capture or compare up event generated an interrupt CCP0"]
pub type MIS_CCU0_R = crate :: BitReader < MIS_CCU0_A > ; # [doc = "Capture or compare up event generated an interrupt CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU0_A { # [doc = "0: CLR"]
MIS_CCU0_CLR = 0 , # [doc = "1: SET"]
MIS_CCU0_SET = 1 , } impl From < MIS_CCU0_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU0_A) -> Self { variant as u8 != 0 } } impl MIS_CCU0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU0_A { match self . bits { false => MIS_CCU0_A :: MIS_CCU0_CLR , true => MIS_CCU0_A :: MIS_CCU0_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu0_clr (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu0_set (& self) -> bool { * self == MIS_CCU0_A :: MIS_CCU0_SET } } # [doc = "Field `MIS_CCU1` reader - Capture or compare up event generated an interrupt CCP1"]
pub type MIS_CCU1_R = crate :: BitReader < MIS_CCU1_A > ; # [doc = "Capture or compare up event generated an interrupt CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_CCU1_A { # [doc = "0: CLR"]
MIS_CCU1_CLR = 0 , # [doc = "1: SET"]
MIS_CCU1_SET = 1 , } impl From < MIS_CCU1_A > for bool { # [inline (always)]
fn from (variant : MIS_CCU1_A) -> Self { variant as u8 != 0 } } impl MIS_CCU1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_CCU1_A { match self . bits { false => MIS_CCU1_A :: MIS_CCU1_CLR , true => MIS_CCU1_A :: MIS_CCU1_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_ccu1_clr (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_ccu1_set (& self) -> bool { * self == MIS_CCU1_A :: MIS_CCU1_SET } } # [doc = "Field `MIS_TOV` reader - Trigger overflow"]
pub type MIS_TOV_R = crate :: BitReader < MIS_TOV_A > ; # [doc = "Trigger overflow\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum MIS_TOV_A { # [doc = "0: CLR"]
MIS_TOV_CLR = 0 , # [doc = "1: SET"]
MIS_TOV_SET = 1 , } impl From < MIS_TOV_A > for bool { # [inline (always)]
fn from (variant : MIS_TOV_A) -> Self { variant as u8 != 0 } } impl MIS_TOV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> MIS_TOV_A { match self . bits { false => MIS_TOV_A :: MIS_TOV_CLR , true => MIS_TOV_A :: MIS_TOV_SET , } } # [doc = "CLR"]
# [inline (always)]
pub fn is_mis_tov_clr (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_CLR } # [doc = "SET"]
# [inline (always)]
pub fn is_mis_tov_set (& self) -> bool { * self == MIS_TOV_A :: MIS_TOV_SET } } impl R { # [doc = "Bit 0 - Zero event generated an interrupt."]
# [inline (always)]
pub fn mis_z (& self) -> MIS_Z_R { MIS_Z_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Load event generated an interrupt."]
# [inline (always)]
pub fn mis_l (& self) -> MIS_L_R { MIS_L_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bit 4 - Capture or compare down event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccd0 (& self) -> MIS_CCD0_R { MIS_CCD0_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - Capture or compare down event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccd1 (& self) -> MIS_CCD1_R { MIS_CCD1_R :: new (((self . bits >> 5) & 1) != 0) } # [doc = "Bit 8 - Capture or compare up event generated an interrupt CCP0"]
# [inline (always)]
pub fn mis_ccu0 (& self) -> MIS_CCU0_R { MIS_CCU0_R :: new (((self . bits >> 8) & 1) != 0) } # [doc = "Bit 9 - Capture or compare up event generated an interrupt CCP1"]
# [inline (always)]
pub fn mis_ccu1 (& self) -> MIS_CCU1_R { MIS_CCU1_R :: new (((self . bits >> 9) & 1) != 0) } # [doc = "Bit 25 - Trigger overflow"]
# [inline (always)]
pub fn mis_tov (& self) -> MIS_TOV_R { MIS_TOV_R :: new (((self . bits >> 25) & 1) != 0) } } # [doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mis::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct MIS_SPEC ; impl crate :: RegisterSpec for MIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`mis::R`](R) reader structure"]
impl crate :: Readable for MIS_SPEC { } # [doc = "`reset()` method sets MIS to value 0"]
impl crate :: Resettable for MIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ISET (w) register accessor: Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iset`]
module"]
pub type ISET = crate :: Reg < iset :: ISET_SPEC > ; # [doc = "Interrupt set"]
pub mod iset { # [doc = "Register `ISET` writer"]
pub type W = crate :: W < ISET_SPEC > ; # [doc = "Zero event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_Z_AW { # [doc = "0: NO_EFFECT"]
ISET_Z_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_Z_SET = 1 , } impl From < ISET_Z_AW > for bool { # [inline (always)]
fn from (variant : ISET_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_Z` writer - Zero event SET"]
pub type ISET_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_Z_AW > ; impl < 'a , REG , const O : u8 > ISET_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_z_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_Z_AW :: ISET_Z_SET) } } # [doc = "Load event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_L_AW { # [doc = "0: NO_EFFECT"]
ISET_L_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_L_SET = 1 , } impl From < ISET_L_AW > for bool { # [inline (always)]
fn from (variant : ISET_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_L` writer - Load event SET"]
pub type ISET_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_L_AW > ; impl < 'a , REG , const O : u8 > ISET_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_l_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_L_AW :: ISET_L_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD0_SET = 1 , } impl From < ISET_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD0` writer - Capture or compare down event SET"]
pub type ISET_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD0_AW :: ISET_CCD0_SET) } } # [doc = "Capture or compare down event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCD1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCD1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCD1_SET = 1 , } impl From < ISET_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCD1` writer - Capture or compare down event SET"]
pub type ISET_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCD1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccd1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCD1_AW :: ISET_CCD1_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU0_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU0_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU0_SET = 1 , } impl From < ISET_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU0` writer - Capture or compare up event SET"]
pub type ISET_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU0_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu0_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU0_AW :: ISET_CCU0_SET) } } # [doc = "Capture or compare up event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_CCU1_AW { # [doc = "0: NO_EFFECT"]
ISET_CCU1_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_CCU1_SET = 1 , } impl From < ISET_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ISET_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_CCU1` writer - Capture or compare up event SET"]
pub type ISET_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_CCU1_AW > ; impl < 'a , REG , const O : u8 > ISET_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_ccu1_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_CCU1_AW :: ISET_CCU1_SET) } } # [doc = "Trigger Overflow event SET\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ISET_TOV_AW { # [doc = "0: NO_EFFECT"]
ISET_TOV_NO_EFFECT = 0 , # [doc = "1: SET"]
ISET_TOV_SET = 1 , } impl From < ISET_TOV_AW > for bool { # [inline (always)]
fn from (variant : ISET_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ISET_TOV` writer - Trigger Overflow event SET"]
pub type ISET_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ISET_TOV_AW > ; impl < 'a , REG , const O : u8 > ISET_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iset_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_NO_EFFECT) } # [doc = "SET"]
# [inline (always)]
pub fn iset_tov_set (self) -> & 'a mut crate :: W < REG > { self . variant (ISET_TOV_AW :: ISET_TOV_SET) } } impl W { # [doc = "Bit 0 - Zero event SET"]
# [inline (always)]
# [must_use]
pub fn iset_z (& mut self) -> ISET_Z_W < ISET_SPEC , 0 > { ISET_Z_W :: new (self) } # [doc = "Bit 1 - Load event SET"]
# [inline (always)]
# [must_use]
pub fn iset_l (& mut self) -> ISET_L_W < ISET_SPEC , 1 > { ISET_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd0 (& mut self) -> ISET_CCD0_W < ISET_SPEC , 4 > { ISET_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccd1 (& mut self) -> ISET_CCD1_W < ISET_SPEC , 5 > { ISET_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu0 (& mut self) -> ISET_CCU0_W < ISET_SPEC , 8 > { ISET_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event SET"]
# [inline (always)]
# [must_use]
pub fn iset_ccu1 (& mut self) -> ISET_CCU1_W < ISET_SPEC , 9 > { ISET_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event SET"]
# [inline (always)]
# [must_use]
pub fn iset_tov (& mut self) -> ISET_TOV_W < ISET_SPEC , 25 > { ISET_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt set\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iset::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ISET_SPEC ; impl crate :: RegisterSpec for ISET_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iset::W`](W) writer structure"]
impl crate :: Writable for ISET_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ISET to value 0"]
impl crate :: Resettable for ISET_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ICLR (w) register accessor: Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@iclr`]
module"]
pub type ICLR = crate :: Reg < iclr :: ICLR_SPEC > ; # [doc = "Interrupt clear"]
pub mod iclr { # [doc = "Register `ICLR` writer"]
pub type W = crate :: W < ICLR_SPEC > ; # [doc = "Zero event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_Z_AW { # [doc = "0: NO_EFFECT"]
ICLR_Z_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_Z_CLR = 1 , } impl From < ICLR_Z_AW > for bool { # [inline (always)]
fn from (variant : ICLR_Z_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_Z` writer - Zero event CLEAR"]
pub type ICLR_Z_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_Z_AW > ; impl < 'a , REG , const O : u8 > ICLR_Z_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_z_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_z_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_Z_AW :: ICLR_Z_CLR) } } # [doc = "Load event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_L_AW { # [doc = "0: NO_EFFECT"]
ICLR_L_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_L_CLR = 1 , } impl From < ICLR_L_AW > for bool { # [inline (always)]
fn from (variant : ICLR_L_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_L` writer - Load event CLEAR"]
pub type ICLR_L_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_L_AW > ; impl < 'a , REG , const O : u8 > ICLR_L_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_l_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_l_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_L_AW :: ICLR_L_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD0_CLR = 1 , } impl From < ICLR_CCD0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD0` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD0_AW :: ICLR_CCD0_CLR) } } # [doc = "Capture or compare down event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCD1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCD1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCD1_CLR = 1 , } impl From < ICLR_CCD1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCD1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCD1` writer - Capture or compare down event CLEAR"]
pub type ICLR_CCD1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCD1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCD1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccd1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccd1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCD1_AW :: ICLR_CCD1_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU0_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU0_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU0_CLR = 1 , } impl From < ICLR_CCU0_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU0_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU0` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU0_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu0_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu0_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU0_AW :: ICLR_CCU0_CLR) } } # [doc = "Capture or compare up event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_CCU1_AW { # [doc = "0: NO_EFFECT"]
ICLR_CCU1_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_CCU1_CLR = 1 , } impl From < ICLR_CCU1_AW > for bool { # [inline (always)]
fn from (variant : ICLR_CCU1_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_CCU1` writer - Capture or compare up event CLEAR"]
pub type ICLR_CCU1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_CCU1_AW > ; impl < 'a , REG , const O : u8 > ICLR_CCU1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_ccu1_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_ccu1_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_CCU1_AW :: ICLR_CCU1_CLR) } } # [doc = "Trigger Overflow event CLEAR\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ICLR_TOV_AW { # [doc = "0: NO_EFFECT"]
ICLR_TOV_NO_EFFECT = 0 , # [doc = "1: CLR"]
ICLR_TOV_CLR = 1 , } impl From < ICLR_TOV_AW > for bool { # [inline (always)]
fn from (variant : ICLR_TOV_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `ICLR_TOV` writer - Trigger Overflow event CLEAR"]
pub type ICLR_TOV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ICLR_TOV_AW > ; impl < 'a , REG , const O : u8 > ICLR_TOV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NO_EFFECT"]
# [inline (always)]
pub fn iclr_tov_no_effect (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_NO_EFFECT) } # [doc = "CLR"]
# [inline (always)]
pub fn iclr_tov_clr (self) -> & 'a mut crate :: W < REG > { self . variant (ICLR_TOV_AW :: ICLR_TOV_CLR) } } impl W { # [doc = "Bit 0 - Zero event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_z (& mut self) -> ICLR_Z_W < ICLR_SPEC , 0 > { ICLR_Z_W :: new (self) } # [doc = "Bit 1 - Load event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_l (& mut self) -> ICLR_L_W < ICLR_SPEC , 1 > { ICLR_L_W :: new (self) } # [doc = "Bit 4 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd0 (& mut self) -> ICLR_CCD0_W < ICLR_SPEC , 4 > { ICLR_CCD0_W :: new (self) } # [doc = "Bit 5 - Capture or compare down event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccd1 (& mut self) -> ICLR_CCD1_W < ICLR_SPEC , 5 > { ICLR_CCD1_W :: new (self) } # [doc = "Bit 8 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu0 (& mut self) -> ICLR_CCU0_W < ICLR_SPEC , 8 > { ICLR_CCU0_W :: new (self) } # [doc = "Bit 9 - Capture or compare up event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_ccu1 (& mut self) -> ICLR_CCU1_W < ICLR_SPEC , 9 > { ICLR_CCU1_W :: new (self) } # [doc = "Bit 25 - Trigger Overflow event CLEAR"]
# [inline (always)]
# [must_use]
pub fn iclr_tov (& mut self) -> ICLR_TOV_W < ICLR_SPEC , 25 > { ICLR_TOV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Interrupt clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iclr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ICLR_SPEC ; impl crate :: RegisterSpec for ICLR_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`iclr::W`](W) writer structure"]
impl crate :: Writable for ICLR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ICLR to value 0"]
impl crate :: Resettable for ICLR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "EVT_MODE (rw) register accessor: Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@evt_mode`]
module"]
pub type EVT_MODE = crate :: Reg < evt_mode :: EVT_MODE_SPEC > ; # [doc = "Event Mode"]
pub mod evt_mode { # [doc = "Register `EVT_MODE` reader"]
pub type R = crate :: R < EVT_MODE_SPEC > ; # [doc = "Register `EVT_MODE` writer"]
pub type W = crate :: W < EVT_MODE_SPEC > ; # [doc = "Field `EVT_MODE_EVT0_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
pub type EVT_MODE_EVT0_CFG_R = crate :: FieldReader < EVT_MODE_EVT0_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]\n\nValue on reset: 1"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT0_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT0_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT0_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT0_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT0_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT0_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT0_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT0_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT0_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_software (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt0_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT0_CFG_A :: EVT_MODE_EVT0_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT1_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT1_CFG_R = crate :: FieldReader < EVT_MODE_EVT1_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT1_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT1_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT1_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT1_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT1_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT1_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT1_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT1_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT1_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_software (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt1_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT1_CFG_A :: EVT_MODE_EVT1_CFG_HARDWARE } } # [doc = "Field `EVT_MODE_EVT2_CFG` reader - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
pub type EVT_MODE_EVT2_CFG_R = crate :: FieldReader < EVT_MODE_EVT2_CFG_A > ; # [doc = "Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]\n\nValue on reset: 2"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum EVT_MODE_EVT2_CFG_A { # [doc = "0: DISABLE"]
EVT_MODE_EVT2_CFG_DISABLE = 0 , # [doc = "1: SOFTWARE"]
EVT_MODE_EVT2_CFG_SOFTWARE = 1 , # [doc = "2: HARDWARE"]
EVT_MODE_EVT2_CFG_HARDWARE = 2 , } impl From < EVT_MODE_EVT2_CFG_A > for u8 { # [inline (always)]
fn from (variant : EVT_MODE_EVT2_CFG_A) -> Self { variant as _ } } impl crate :: FieldSpec for EVT_MODE_EVT2_CFG_A { type Ux = u8 ; } impl EVT_MODE_EVT2_CFG_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < EVT_MODE_EVT2_CFG_A > { match self . bits { 0 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE) , 1 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE) , 2 => Some (EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE) , _ => None , } } # [doc = "DISABLE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_disable (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_DISABLE } # [doc = "SOFTWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_software (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_SOFTWARE } # [doc = "HARDWARE"]
# [inline (always)]
pub fn is_evt_mode_evt2_cfg_hardware (& self) -> bool { * self == EVT_MODE_EVT2_CFG_A :: EVT_MODE_EVT2_CFG_HARDWARE } } impl R { # [doc = "Bits 0:1 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[0\\]"]
# [inline (always)]
pub fn evt_mode_evt0_cfg (& self) -> EVT_MODE_EVT0_CFG_R { EVT_MODE_EVT0_CFG_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 2:3 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt1_cfg (& self) -> EVT_MODE_EVT1_CFG_R { EVT_MODE_EVT1_CFG_R :: new (((self . bits >> 2) & 3) as u8) } # [doc = "Bits 4:5 - Event line mode select for event corresponding to \\[IPSTANDARD.INT_EVENT\\]\\[1\\]"]
# [inline (always)]
pub fn evt_mode_evt2_cfg (& self) -> EVT_MODE_EVT2_CFG_R { EVT_MODE_EVT2_CFG_R :: new (((self . bits >> 4) & 3) as u8) } } impl W { # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Event Mode\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`evt_mode::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`evt_mode::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct EVT_MODE_SPEC ; impl crate :: RegisterSpec for EVT_MODE_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`evt_mode::R`](R) reader structure"]
impl crate :: Readable for EVT_MODE_SPEC { } # [doc = "`write(|w| ..)` method takes [`evt_mode::W`](W) writer structure"]
impl crate :: Writable for EVT_MODE_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets EVT_MODE to value 0x29"]
impl crate :: Resettable for EVT_MODE_SPEC { const RESET_VALUE : Self :: Ux = 0x29 ; } } # [doc = "DESC (r) register accessor: Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@desc`]
module"]
pub type DESC = crate :: Reg < desc :: DESC_SPEC > ; # [doc = "Module Description"]
pub mod desc { # [doc = "Register `DESC` reader"]
pub type R = crate :: R < DESC_SPEC > ; # [doc = "Field `DESC_MINREV` reader - Minor rev of the IP"]
pub type DESC_MINREV_R = crate :: FieldReader ; # [doc = "Field `DESC_MAJREV` reader - Major rev of the IP"]
pub type DESC_MAJREV_R = crate :: FieldReader ; # [doc = "Field `DESC_INSTNUM` reader - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
pub type DESC_INSTNUM_R = crate :: FieldReader ; # [doc = "Field `DESC_FEATUREVER` reader - Feature Set for the module *instance*"]
pub type DESC_FEATUREVER_R = crate :: FieldReader ; # [doc = "Field `DESC_MODULEID` reader - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
pub type DESC_MODULEID_R = crate :: FieldReader < u16 > ; impl R { # [doc = "Bits 0:3 - Minor rev of the IP"]
# [inline (always)]
pub fn desc_minrev (& self) -> DESC_MINREV_R { DESC_MINREV_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bits 4:7 - Major rev of the IP"]
# [inline (always)]
pub fn desc_majrev (& self) -> DESC_MAJREV_R { DESC_MAJREV_R :: new (((self . bits >> 4) & 0x0f) as u8) } # [doc = "Bits 8:11 - Instance Number within the device. This will be a parameter to the RTL for modules that can have multiple instances"]
# [inline (always)]
pub fn desc_instnum (& self) -> DESC_INSTNUM_R { DESC_INSTNUM_R :: new (((self . bits >> 8) & 0x0f) as u8) } # [doc = "Bits 12:15 - Feature Set for the module *instance*"]
# [inline (always)]
pub fn desc_featurever (& self) -> DESC_FEATUREVER_R { DESC_FEATUREVER_R :: new (((self . bits >> 12) & 0x0f) as u8) } # [doc = "Bits 16:31 - Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness."]
# [inline (always)]
pub fn desc_moduleid (& self) -> DESC_MODULEID_R { DESC_MODULEID_R :: new (((self . bits >> 16) & 0xffff) as u16) } } # [doc = "Module Description\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`desc::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct DESC_SPEC ; impl crate :: RegisterSpec for DESC_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`desc::R`](R) reader structure"]
impl crate :: Readable for DESC_SPEC { } # [doc = "`reset()` method sets DESC to value 0"]
impl crate :: Resettable for DESC_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCPD (rw) register accessor: CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccpd`]
module"]
pub type CCPD = crate :: Reg < ccpd :: CCPD_SPEC > ; # [doc = "CCP Direction"]
pub mod ccpd { # [doc = "Register `CCPD` reader"]
pub type R = crate :: R < CCPD_SPEC > ; # [doc = "Register `CCPD` writer"]
pub type W = crate :: W < CCPD_SPEC > ; # [doc = "Field `CCPD_C0CCP0` reader - Counter CCP0"]
pub type CCPD_C0CCP0_R = crate :: BitReader < CCPD_C0CCP0_A > ; # [doc = "Counter CCP0\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP0_A { # [doc = "0: INPUT"]
CCPD_C0CCP0_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP0_OUTPUT = 1 , } impl From < CCPD_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP0_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP0_A { match self . bits { false => CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT , true => CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_input (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp0_output (& self) -> bool { * self == CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT } } # [doc = "Field `CCPD_C0CCP0` writer - Counter CCP0"]
pub type CCPD_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP0_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp0_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP0_A :: CCPD_C0CCP0_OUTPUT) } } # [doc = "Field `CCPD_C0CCP1` reader - Counter CCP1"]
pub type CCPD_C0CCP1_R = crate :: BitReader < CCPD_C0CCP1_A > ; # [doc = "Counter CCP1\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCPD_C0CCP1_A { # [doc = "0: INPUT"]
CCPD_C0CCP1_INPUT = 0 , # [doc = "1: OUTPUT"]
CCPD_C0CCP1_OUTPUT = 1 , } impl From < CCPD_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : CCPD_C0CCP1_A) -> Self { variant as u8 != 0 } } impl CCPD_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCPD_C0CCP1_A { match self . bits { false => CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT , true => CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT , } } # [doc = "INPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_input (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT } # [doc = "OUTPUT"]
# [inline (always)]
pub fn is_ccpd_c0ccp1_output (& self) -> bool { * self == CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT } } # [doc = "Field `CCPD_C0CCP1` writer - Counter CCP1"]
pub type CCPD_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCPD_C0CCP1_A > ; impl < 'a , REG , const O : u8 > CCPD_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "INPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_input (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_INPUT) } # [doc = "OUTPUT"]
# [inline (always)]
pub fn ccpd_c0ccp1_output (self) -> & 'a mut crate :: W < REG > { self . variant (CCPD_C0CCP1_A :: CCPD_C0CCP1_OUTPUT) } } impl R { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
pub fn ccpd_c0ccp0 (& self) -> CCPD_C0CCP0_R { CCPD_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
pub fn ccpd_c0ccp1 (& self) -> CCPD_C0CCP1_R { CCPD_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp0 (& mut self) -> CCPD_C0CCP0_W < CCPD_SPEC , 0 > { CCPD_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1"]
# [inline (always)]
# [must_use]
pub fn ccpd_c0ccp1 (& mut self) -> CCPD_C0CCP1_W < CCPD_SPEC , 1 > { CCPD_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Direction\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccpd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccpd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCPD_SPEC ; impl crate :: RegisterSpec for CCPD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccpd::R`](R) reader structure"]
impl crate :: Readable for CCPD_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccpd::W`](W) writer structure"]
impl crate :: Writable for CCPD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCPD to value 0"]
impl crate :: Resettable for CCPD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "ODIS (rw) register accessor: Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@odis`]
module"]
pub type ODIS = crate :: Reg < odis :: ODIS_SPEC > ; # [doc = "Output Disable"]
pub mod odis { # [doc = "Register `ODIS` reader"]
pub type R = crate :: R < ODIS_SPEC > ; # [doc = "Register `ODIS` writer"]
pub type W = crate :: W < ODIS_SPEC > ; # [doc = "Field `ODIS_C0CCP0` reader - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_R = crate :: BitReader < ODIS_C0CCP0_A > ; # [doc = "Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP0_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP0_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP0_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP0_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP0_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP0_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP0_A { match self . bits { false => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL , true => ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp0_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP0` writer - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP0_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP0_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP0_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp0_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP0_A :: ODIS_C0CCP0_CCP_OUTPUT_LOW) } } # [doc = "Field `ODIS_C0CCP1` reader - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_R = crate :: BitReader < ODIS_C0CCP1_A > ; # [doc = "Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum ODIS_C0CCP1_A { # [doc = "0: CCP_OUTPUT_OCTL"]
ODIS_C0CCP1_CCP_OUTPUT_OCTL = 0 , # [doc = "1: CCP_OUTPUT_LOW"]
ODIS_C0CCP1_CCP_OUTPUT_LOW = 1 , } impl From < ODIS_C0CCP1_A > for bool { # [inline (always)]
fn from (variant : ODIS_C0CCP1_A) -> Self { variant as u8 != 0 } } impl ODIS_C0CCP1_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> ODIS_C0CCP1_A { match self . bits { false => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL , true => ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW , } } # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_octl (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn is_odis_c0ccp1_ccp_output_low (& self) -> bool { * self == ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW } } # [doc = "Field `ODIS_C0CCP1` writer - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
pub type ODIS_C0CCP1_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , ODIS_C0CCP1_A > ; impl < 'a , REG , const O : u8 > ODIS_C0CCP1_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CCP_OUTPUT_OCTL"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_octl (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_OCTL) } # [doc = "CCP_OUTPUT_LOW"]
# [inline (always)]
pub fn odis_c0ccp1_ccp_output_low (self) -> & 'a mut crate :: W < REG > { self . variant (ODIS_C0CCP1_A :: ODIS_C0CCP1_CCP_OUTPUT_LOW) } } impl R { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp0 (& self) -> ODIS_C0CCP0_R { ODIS_C0CCP0_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
pub fn odis_c0ccp1 (& self) -> ODIS_C0CCP1_R { ODIS_C0CCP1_R :: new (((self . bits >> 1) & 1) != 0) } } impl W { # [doc = "Bit 0 - Counter CCP0 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp0 (& mut self) -> ODIS_C0CCP0_W < ODIS_SPEC , 0 > { ODIS_C0CCP0_W :: new (self) } # [doc = "Bit 1 - Counter CCP1 Disable Mask Defines whether CCP0 of Counter n is forced low or not"]
# [inline (always)]
# [must_use]
pub fn odis_c0ccp1 (& mut self) -> ODIS_C0CCP1_W < ODIS_SPEC , 1 > { ODIS_C0CCP1_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Output Disable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`odis::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`odis::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct ODIS_SPEC ; impl crate :: RegisterSpec for ODIS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`odis::R`](R) reader structure"]
impl crate :: Readable for ODIS_SPEC { } # [doc = "`write(|w| ..)` method takes [`odis::W`](W) writer structure"]
impl crate :: Writable for ODIS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets ODIS to value 0"]
impl crate :: Resettable for ODIS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCLKCTL (rw) register accessor: Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cclkctl`]
module"]
pub type CCLKCTL = crate :: Reg < cclkctl :: CCLKCTL_SPEC > ; # [doc = "Counter Clock Control Register"]
pub mod cclkctl { # [doc = "Register `CCLKCTL` reader"]
pub type R = crate :: R < CCLKCTL_SPEC > ; # [doc = "Register `CCLKCTL` writer"]
pub type W = crate :: W < CCLKCTL_SPEC > ; # [doc = "Field `CCLKCTL_CLKEN` reader - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_R = crate :: BitReader < CCLKCTL_CLKEN_A > ; # [doc = "Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCLKCTL_CLKEN_A { # [doc = "0: DISABLED"]
CCLKCTL_CLKEN_DISABLED = 0 , # [doc = "1: ENABLED"]
CCLKCTL_CLKEN_ENABLED = 1 , } impl From < CCLKCTL_CLKEN_A > for bool { # [inline (always)]
fn from (variant : CCLKCTL_CLKEN_A) -> Self { variant as u8 != 0 } } impl CCLKCTL_CLKEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCLKCTL_CLKEN_A { match self . bits { false => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED , true => CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_disabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_cclkctl_clken_enabled (& self) -> bool { * self == CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED } } # [doc = "Field `CCLKCTL_CLKEN` writer - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
pub type CCLKCTL_CLKEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCLKCTL_CLKEN_A > ; impl < 'a , REG , const O : u8 > CCLKCTL_CLKEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cclkctl_clken_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn cclkctl_clken_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCLKCTL_CLKEN_A :: CCLKCTL_CLKEN_ENABLED) } } impl R { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
pub fn cclkctl_clken (& self) -> CCLKCTL_CLKEN_R { CCLKCTL_CLKEN_R :: new ((self . bits & 1) != 0) } } impl W { # [doc = "Bit 0 - Clock Enable Disables the clock gating to the module. SW has to explicitly program the value to 0 to gate the clock."]
# [inline (always)]
# [must_use]
pub fn cclkctl_clken (& mut self) -> CCLKCTL_CLKEN_W < CCLKCTL_SPEC , 0 > { CCLKCTL_CLKEN_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cclkctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cclkctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCLKCTL_SPEC ; impl crate :: RegisterSpec for CCLKCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cclkctl::R`](R) reader structure"]
impl crate :: Readable for CCLKCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cclkctl::W`](W) writer structure"]
impl crate :: Writable for CCLKCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCLKCTL to value 0"]
impl crate :: Resettable for CCLKCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPS (rw) register accessor: Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cps`]
module"]
pub type CPS = crate :: Reg < cps :: CPS_SPEC > ; # [doc = "Clock Prescale Register"]
pub mod cps { # [doc = "Register `CPS` reader"]
pub type R = crate :: R < CPS_SPEC > ; # [doc = "Register `CPS` writer"]
pub type W = crate :: W < CPS_SPEC > ; # [doc = "Field `CPS_PCNT` reader - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_R = crate :: FieldReader ; # [doc = "Field `CPS_PCNT` writer - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
pub type CPS_PCNT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 8 , O > ; impl R { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
pub fn cps_pcnt (& self) -> CPS_PCNT_R { CPS_PCNT_R :: new ((self . bits & 0xff) as u8) } } impl W { # [doc = "Bits 0:7 - Pre-Scale Count This field specifies the pre-scale count value. The selected TIMCLK source is divided by a value of (PCNT+1). A PCNT value of 0 divides TIMCLK by 1, effectively bypassing the divider. A PCNT value of greater than 0 divides the TIMCLK source generating a slower clock"]
# [inline (always)]
# [must_use]
pub fn cps_pcnt (& mut self) -> CPS_PCNT_W < CPS_SPEC , 0 > { CPS_PCNT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Clock Prescale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cps::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cps::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPS_SPEC ; impl crate :: RegisterSpec for CPS_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cps::R`](R) reader structure"]
impl crate :: Readable for CPS_SPEC { } # [doc = "`write(|w| ..)` method takes [`cps::W`](W) writer structure"]
impl crate :: Writable for CPS_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CPS to value 0"]
impl crate :: Resettable for CPS_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CPSV (r) register accessor: Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cpsv`]
module"]
pub type CPSV = crate :: Reg < cpsv :: CPSV_SPEC > ; # [doc = "Clock prescale count status register"]
pub mod cpsv { # [doc = "Register `CPSV` reader"]
pub type R = crate :: R < CPSV_SPEC > ; # [doc = "Field `CPSV_CPSVAL` reader - Current Prescale Count Value"]
pub type CPSV_CPSVAL_R = crate :: FieldReader ; impl R { # [doc = "Bits 0:7 - Current Prescale Count Value"]
# [inline (always)]
pub fn cpsv_cpsval (& self) -> CPSV_CPSVAL_R { CPSV_CPSVAL_R :: new ((self . bits & 0xff) as u8) } } # [doc = "Clock prescale count status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpsv::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CPSV_SPEC ; impl crate :: RegisterSpec for CPSV_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cpsv::R`](R) reader structure"]
impl crate :: Readable for CPSV_SPEC { } # [doc = "`reset()` method sets CPSV to value 0"]
impl crate :: Resettable for CPSV_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIGCTL (rw) register accessor: Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrigctl`]
module"]
pub type CTTRIGCTL = crate :: Reg < cttrigctl :: CTTRIGCTL_SPEC > ; # [doc = "Timer Cross Trigger Control Register"]
pub mod cttrigctl { # [doc = "Register `CTTRIGCTL` reader"]
pub type R = crate :: R < CTTRIGCTL_SPEC > ; # [doc = "Register `CTTRIGCTL` writer"]
pub type W = crate :: W < CTTRIGCTL_SPEC > ; # [doc = "Field `CTTRIGCTL_CTEN` reader - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_R = crate :: BitReader < CTTRIGCTL_CTEN_A > ; # [doc = "Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_CTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_CTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_CTEN_ENABLE = 1 , } impl From < CTTRIGCTL_CTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_CTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_CTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_CTEN_A { match self . bits { false => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED , true => CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_cten_disabled (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_cten_enable (& self) -> bool { * self == CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_CTEN` writer - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
pub type CTTRIGCTL_CTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_CTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_CTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_cten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_cten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_CTEN_A :: CTTRIGCTL_CTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTEN` reader - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_R = crate :: BitReader < CTTRIGCTL_EVTCTEN_A > ; # [doc = "Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIGCTL_EVTCTEN_A { # [doc = "0: DISABLED"]
CTTRIGCTL_EVTCTEN_DISABLED = 0 , # [doc = "1: ENABLE"]
CTTRIGCTL_EVTCTEN_ENABLE = 1 , } impl From < CTTRIGCTL_EVTCTEN_A > for bool { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTEN_A) -> Self { variant as u8 != 0 } } impl CTTRIGCTL_EVTCTEN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTTRIGCTL_EVTCTEN_A { match self . bits { false => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED , true => CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_disabled (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED } # [doc = "ENABLE"]
# [inline (always)]
pub fn is_cttrigctl_evtcten_enable (& self) -> bool { * self == CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE } } # [doc = "Field `CTTRIGCTL_EVTCTEN` writer - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTEN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIGCTL_EVTCTEN_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTEN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrigctl_evtcten_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_DISABLED) } # [doc = "ENABLE"]
# [inline (always)]
pub fn cttrigctl_evtcten_enable (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTEN_A :: CTTRIGCTL_EVTCTEN_ENABLE) } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` reader - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_R = crate :: FieldReader < CTTRIGCTL_EVTCTTRIGSEL_A > ; # [doc = "Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTTRIGCTL_EVTCTTRIGSEL_A { # [doc = "0: FSUB0"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB0 = 0 , # [doc = "1: FSUB1"]
CTTRIGCTL_EVTCTTRIGSEL_FSUB1 = 1 , # [doc = "2: Z"]
CTTRIGCTL_EVTCTTRIGSEL_Z = 2 , # [doc = "3: L"]
CTTRIGCTL_EVTCTTRIGSEL_L = 3 , # [doc = "4: CCD0"]
CTTRIGCTL_EVTCTTRIGSEL_CCD0 = 4 , # [doc = "5: CCD1"]
CTTRIGCTL_EVTCTTRIGSEL_CCD1 = 5 , # [doc = "6: CCD2"]
CTTRIGCTL_EVTCTTRIGSEL_CCD2 = 6 , # [doc = "7: CCD3"]
CTTRIGCTL_EVTCTTRIGSEL_CCD3 = 7 , # [doc = "8: CCU0"]
CTTRIGCTL_EVTCTTRIGSEL_CCU0 = 8 , # [doc = "9: CCU1"]
CTTRIGCTL_EVTCTTRIGSEL_CCU1 = 9 , # [doc = "10: CCU2"]
CTTRIGCTL_EVTCTTRIGSEL_CCU2 = 10 , # [doc = "11: CCU3"]
CTTRIGCTL_EVTCTTRIGSEL_CCU3 = 11 , } impl From < CTTRIGCTL_EVTCTTRIGSEL_A > for u8 { # [inline (always)]
fn from (variant : CTTRIGCTL_EVTCTTRIGSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTTRIGCTL_EVTCTTRIGSEL_A { type Ux = u8 ; } impl CTTRIGCTL_EVTCTTRIGSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTTRIGCTL_EVTCTTRIGSEL_A > { match self . bits { 0 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) , 1 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) , 2 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) , 3 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) , 4 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) , 5 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) , 6 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) , 7 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) , 8 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) , 9 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) , 10 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) , 11 => Some (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) , _ => None , } } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_fsub1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1 } # [doc = "Z"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_z (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z } # [doc = "L"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_l (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L } # [doc = "CCD0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0 } # [doc = "CCD1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1 } # [doc = "CCD2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2 } # [doc = "CCD3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccd3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3 } # [doc = "CCU0"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu0 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0 } # [doc = "CCU1"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu1 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1 } # [doc = "CCU2"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu2 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2 } # [doc = "CCU3"]
# [inline (always)]
pub fn is_cttrigctl_evtcttrigsel_ccu3 (& self) -> bool { * self == CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3 } } # [doc = "Field `CTTRIGCTL_EVTCTTRIGSEL` writer - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
pub type CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , CTTRIGCTL_EVTCTTRIGSEL_A > ; impl < 'a , REG , const O : u8 > CTTRIGCTL_EVTCTTRIGSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FSUB0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_FSUB1) } # [doc = "Z"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_z (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_Z) } # [doc = "L"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_l (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_L) } # [doc = "CCD0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD0) } # [doc = "CCD1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD1) } # [doc = "CCD2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD2) } # [doc = "CCD3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCD3) } # [doc = "CCU0"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU0) } # [doc = "CCU1"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU1) } # [doc = "CCU2"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU2) } # [doc = "CCU3"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIGCTL_EVTCTTRIGSEL_A :: CTTRIGCTL_EVTCTTRIGSEL_CCU3) } } impl R { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
pub fn cttrigctl_cten (& self) -> CTTRIGCTL_CTEN_R { CTTRIGCTL_CTEN_R :: new ((self . bits & 1) != 0) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcten (& self) -> CTTRIGCTL_EVTCTEN_R { CTTRIGCTL_EVTCTEN_R :: new (((self . bits >> 1) & 1) != 0) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
pub fn cttrigctl_evtcttrigsel (& self) -> CTTRIGCTL_EVTCTTRIGSEL_R { CTTRIGCTL_EVTCTTRIGSEL_R :: new (((self . bits >> 16) & 0x0f) as u8) } } impl W { # [doc = "Bit 0 - Timer Cross trigger enable. This field is used to enable whether the SW or HW logic can generate a timer cross trigger event in the system. These cross triggers are connected to the respective timer trigger in of the other timer IPs in the SOC power domain. The timer cross trigger is essentially the combined logic of the HW and SW conditions controlling EN bit in the CTRCTL register."]
# [inline (always)]
# [must_use]
pub fn cttrigctl_cten (& mut self) -> CTTRIGCTL_CTEN_W < CTTRIGCTL_SPEC , 0 > { CTTRIGCTL_CTEN_W :: new (self) } # [doc = "Bit 1 - Enable the Input Trigger Conditions to the Timer module as a condition for Cross Triggers. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcten (& mut self) -> CTTRIGCTL_EVTCTEN_W < CTTRIGCTL_SPEC , 1 > { CTTRIGCTL_EVTCTEN_W :: new (self) } # [doc = "Bits 16:19 - Used to Select the subscriber port that should be used for input cross trigger. Refer Figure 8 Cross Trigger Generation Path"]
# [inline (always)]
# [must_use]
pub fn cttrigctl_evtcttrigsel (& mut self) -> CTTRIGCTL_EVTCTTRIGSEL_W < CTTRIGCTL_SPEC , 16 > { CTTRIGCTL_EVTCTTRIGSEL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cttrigctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrigctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIGCTL_SPEC ; impl crate :: RegisterSpec for CTTRIGCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cttrigctl::R`](R) reader structure"]
impl crate :: Readable for CTTRIGCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`cttrigctl::W`](W) writer structure"]
impl crate :: Writable for CTTRIGCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIGCTL to value 0"]
impl crate :: Resettable for CTTRIGCTL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTTRIG (w) register accessor: Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cttrig`]
module"]
pub type CTTRIG = crate :: Reg < cttrig :: CTTRIG_SPEC > ; # [doc = "Timer Cross Trigger Register"]
pub mod cttrig { # [doc = "Register `CTTRIG` writer"]
pub type W = crate :: W < CTTRIG_SPEC > ; # [doc = "Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTTRIG_TRIG_AW { # [doc = "0: DISABLED"]
CTTRIG_TRIG_DISABLED = 0 , # [doc = "1: GENERATE"]
CTTRIG_TRIG_GENERATE = 1 , } impl From < CTTRIG_TRIG_AW > for bool { # [inline (always)]
fn from (variant : CTTRIG_TRIG_AW) -> Self { variant as u8 != 0 } } # [doc = "Field `CTTRIG_TRIG` writer - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
pub type CTTRIG_TRIG_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTTRIG_TRIG_AW > ; impl < 'a , REG , const O : u8 > CTTRIG_TRIG_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn cttrig_trig_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_DISABLED) } # [doc = "GENERATE"]
# [inline (always)]
pub fn cttrig_trig_generate (self) -> & 'a mut crate :: W < REG > { self . variant (CTTRIG_TRIG_AW :: CTTRIG_TRIG_GENERATE) } } impl W { # [doc = "Bit 0 - Generate Cross Trigger This bit when programmed will generate a synchronized trigger condition all the cross trigger enabled Timer instances including current timer instance."]
# [inline (always)]
# [must_use]
pub fn cttrig_trig (& mut self) -> CTTRIG_TRIG_W < CTTRIG_SPEC , 0 > { CTTRIG_TRIG_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Timer Cross Trigger Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cttrig::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTTRIG_SPEC ; impl crate :: RegisterSpec for CTTRIG_SPEC { type Ux = u32 ; } # [doc = "`write(|w| ..)` method takes [`cttrig::W`](W) writer structure"]
impl crate :: Writable for CTTRIG_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTTRIG to value 0"]
impl crate :: Resettable for CTTRIG_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTR (rw) register accessor: Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctr`]
module"]
pub type CTR = crate :: Reg < ctr :: CTR_SPEC > ; # [doc = "Counter Register"]
pub mod ctr { # [doc = "Register `CTR` reader"]
pub type R = crate :: R < CTR_SPEC > ; # [doc = "Register `CTR` writer"]
pub type W = crate :: W < CTR_SPEC > ; # [doc = "Field `CTR_CCTR` reader - Current Counter value"]
pub type CTR_CCTR_R = crate :: FieldReader < u16 > ; # [doc = "Field `CTR_CCTR` writer - Current Counter value"]
pub type CTR_CCTR_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
pub fn ctr_cctr (& self) -> CTR_CCTR_R { CTR_CCTR_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Current Counter value"]
# [inline (always)]
# [must_use]
pub fn ctr_cctr (& mut self) -> CTR_CCTR_W < CTR_SPEC , 0 > { CTR_CCTR_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTR_SPEC ; impl crate :: RegisterSpec for CTR_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctr::R`](R) reader structure"]
impl crate :: Readable for CTR_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
impl crate :: Writable for CTR_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTR to value 0"]
impl crate :: Resettable for CTR_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CTRCTL (rw) register accessor: Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrctl`]
module"]
pub type CTRCTL = crate :: Reg < ctrctl :: CTRCTL_SPEC > ; # [doc = "Counter Control Register"]
pub mod ctrctl { # [doc = "Register `CTRCTL` reader"]
pub type R = crate :: R < CTRCTL_SPEC > ; # [doc = "Register `CTRCTL` writer"]
pub type W = crate :: W < CTRCTL_SPEC > ; # [doc = "Field `CTRCTL_EN` reader - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_R = crate :: BitReader < CTRCTL_EN_A > ; # [doc = "Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_EN_A { # [doc = "0: DISABLED"]
CTRCTL_EN_DISABLED = 0 , # [doc = "1: ENABLED"]
CTRCTL_EN_ENABLED = 1 , } impl From < CTRCTL_EN_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_EN_A) -> Self { variant as u8 != 0 } } impl CTRCTL_EN_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_EN_A { match self . bits { false => CTRCTL_EN_A :: CTRCTL_EN_DISABLED , true => CTRCTL_EN_A :: CTRCTL_EN_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ctrctl_en_disabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ctrctl_en_enabled (& self) -> bool { * self == CTRCTL_EN_A :: CTRCTL_EN_ENABLED } } # [doc = "Field `CTRCTL_EN` writer - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
pub type CTRCTL_EN_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_EN_A > ; impl < 'a , REG , const O : u8 > CTRCTL_EN_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ctrctl_en_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ctrctl_en_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_EN_A :: CTRCTL_EN_ENABLED) } } # [doc = "Field `CTRCTL_REPEAT` reader - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_R = crate :: FieldReader < CTRCTL_REPEAT_A > ; # [doc = "Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_REPEAT_A { # [doc = "0: REPEAT_0"]
CTRCTL_REPEAT_REPEAT_0 = 0 , # [doc = "1: REPEAT_1"]
CTRCTL_REPEAT_REPEAT_1 = 1 , # [doc = "2: REPEAT_2"]
CTRCTL_REPEAT_REPEAT_2 = 2 , # [doc = "3: REPEAT_3"]
CTRCTL_REPEAT_REPEAT_3 = 3 , # [doc = "4: REPEAT_4"]
CTRCTL_REPEAT_REPEAT_4 = 4 , } impl From < CTRCTL_REPEAT_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_REPEAT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_REPEAT_A { type Ux = u8 ; } impl CTRCTL_REPEAT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_REPEAT_A > { match self . bits { 0 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) , 1 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) , 2 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) , 3 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) , 4 => Some (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) , _ => None , } } # [doc = "REPEAT_0"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_0 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0 } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_1 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1 } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_2 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2 } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_3 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3 } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn is_ctrctl_repeat_repeat_4 (& self) -> bool { * self == CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4 } } # [doc = "Field `CTRCTL_REPEAT` writer - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
pub type CTRCTL_REPEAT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_REPEAT_A > ; impl < 'a , REG , const O : u8 > CTRCTL_REPEAT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "REPEAT_0"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_0 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_0) } # [doc = "REPEAT_1"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_1 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_1) } # [doc = "REPEAT_2"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_2 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_2) } # [doc = "REPEAT_3"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_3 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_3) } # [doc = "REPEAT_4"]
# [inline (always)]
pub fn ctrctl_repeat_repeat_4 (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_REPEAT_A :: CTRCTL_REPEAT_REPEAT_4) } } # [doc = "Field `CTRCTL_CM` reader - Count Mode"]
pub type CTRCTL_CM_R = crate :: FieldReader < CTRCTL_CM_A > ; # [doc = "Count Mode\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CM_A { # [doc = "0: DOWN"]
CTRCTL_CM_DOWN = 0 , # [doc = "1: UP_DOWN"]
CTRCTL_CM_UP_DOWN = 1 , # [doc = "2: UP"]
CTRCTL_CM_UP = 2 , } impl From < CTRCTL_CM_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CM_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CM_A { type Ux = u8 ; } impl CTRCTL_CM_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CM_A > { match self . bits { 0 => Some (CTRCTL_CM_A :: CTRCTL_CM_DOWN) , 1 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) , 2 => Some (CTRCTL_CM_A :: CTRCTL_CM_UP) , _ => None , } } # [doc = "DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_DOWN } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn is_ctrctl_cm_up_down (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN } # [doc = "UP"]
# [inline (always)]
pub fn is_ctrctl_cm_up (& self) -> bool { * self == CTRCTL_CM_A :: CTRCTL_CM_UP } } # [doc = "Field `CTRCTL_CM` writer - Count Mode"]
pub type CTRCTL_CM_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CM_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CM_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DOWN"]
# [inline (always)]
pub fn ctrctl_cm_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_DOWN) } # [doc = "UP_DOWN"]
# [inline (always)]
pub fn ctrctl_cm_up_down (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP_DOWN) } # [doc = "UP"]
# [inline (always)]
pub fn ctrctl_cm_up (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CM_A :: CTRCTL_CM_UP) } } # [doc = "Field `CTRCTL_CLC` reader - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_R = crate :: FieldReader < CTRCTL_CLC_A > ; # [doc = "Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CLC_A { # [doc = "0: CCCTL0_LCOND"]
CTRCTL_CLC_CCCTL0_LCOND = 0 , # [doc = "1: CCCTL1_LCOND"]
CTRCTL_CLC_CCCTL1_LCOND = 1 , # [doc = "2: CCCTL2_LCOND"]
CTRCTL_CLC_CCCTL2_LCOND = 2 , # [doc = "3: CCCTL3_LCOND"]
CTRCTL_CLC_CCCTL3_LCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CLC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CLC_QEI_3INP = 5 , } impl From < CTRCTL_CLC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CLC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CLC_A { type Ux = u8 ; } impl CTRCTL_CLC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CLC_A > { match self . bits { 0 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) , 1 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) , 2 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) , 3 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) , 4 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) , 5 => Some (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl0_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl1_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl2_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn is_ctrctl_clc_ccctl3_lcond (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_2inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_clc_qei_3inp (& self) -> bool { * self == CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP } } # [doc = "Field `CTRCTL_CLC` writer - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CLC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CLC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CLC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl0_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL0_LCOND) } # [doc = "CCCTL1_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl1_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL1_LCOND) } # [doc = "CCCTL2_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl2_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL2_LCOND) } # [doc = "CCCTL3_LCOND"]
# [inline (always)]
pub fn ctrctl_clc_ccctl3_lcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_CCCTL3_LCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_clc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CLC_A :: CTRCTL_CLC_QEI_3INP) } } # [doc = "Field `CTRCTL_CAC` reader - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_R = crate :: FieldReader < CTRCTL_CAC_A > ; # [doc = "Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CAC_A { # [doc = "0: CCCTL0_ACOND"]
CTRCTL_CAC_CCCTL0_ACOND = 0 , # [doc = "1: CCCTL1_ACOND"]
CTRCTL_CAC_CCCTL1_ACOND = 1 , # [doc = "2: CCCTL2_ACOND"]
CTRCTL_CAC_CCCTL2_ACOND = 2 , # [doc = "3: CCCTL3_ACOND"]
CTRCTL_CAC_CCCTL3_ACOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CAC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CAC_QEI_3INP = 5 , } impl From < CTRCTL_CAC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CAC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CAC_A { type Ux = u8 ; } impl CTRCTL_CAC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CAC_A > { match self . bits { 0 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) , 1 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) , 2 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) , 3 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) , 4 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) , 5 => Some (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl0_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl1_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl2_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn is_ctrctl_cac_ccctl3_acond (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_2inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_cac_qei_3inp (& self) -> bool { * self == CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP } } # [doc = "Field `CTRCTL_CAC` writer - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CAC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CAC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CAC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl0_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL0_ACOND) } # [doc = "CCCTL1_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl1_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL1_ACOND) } # [doc = "CCCTL2_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl2_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL2_ACOND) } # [doc = "CCCTL3_ACOND"]
# [inline (always)]
pub fn ctrctl_cac_ccctl3_acond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_CCCTL3_ACOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_cac_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CAC_A :: CTRCTL_CAC_QEI_3INP) } } # [doc = "Field `CTRCTL_CZC` reader - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_R = crate :: FieldReader < CTRCTL_CZC_A > ; # [doc = "Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved.\n\nValue on reset: 7"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CZC_A { # [doc = "0: CCCTL0_ZCOND"]
CTRCTL_CZC_CCCTL0_ZCOND = 0 , # [doc = "1: CCCTL1_ZCOND"]
CTRCTL_CZC_CCCTL1_ZCOND = 1 , # [doc = "2: CCCTL2_ZCOND"]
CTRCTL_CZC_CCCTL2_ZCOND = 2 , # [doc = "3: CCCTL3_ZCOND"]
CTRCTL_CZC_CCCTL3_ZCOND = 3 , # [doc = "4: QEI_2INP"]
CTRCTL_CZC_QEI_2INP = 4 , # [doc = "5: QEI_3INP"]
CTRCTL_CZC_QEI_3INP = 5 , } impl From < CTRCTL_CZC_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CZC_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CZC_A { type Ux = u8 ; } impl CTRCTL_CZC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CZC_A > { match self . bits { 0 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) , 1 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) , 2 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) , 3 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) , 4 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) , 5 => Some (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) , _ => None , } } # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl0_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl1_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl2_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn is_ctrctl_czc_ccctl3_zcond (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_2inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn is_ctrctl_czc_qei_3inp (& self) -> bool { * self == CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP } } # [doc = "Field `CTRCTL_CZC` writer - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
pub type CTRCTL_CZC_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CTRCTL_CZC_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CZC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCCTL0_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl0_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL0_ZCOND) } # [doc = "CCCTL1_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl1_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL1_ZCOND) } # [doc = "CCCTL2_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl2_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL2_ZCOND) } # [doc = "CCCTL3_ZCOND"]
# [inline (always)]
pub fn ctrctl_czc_ccctl3_zcond (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_CCCTL3_ZCOND) } # [doc = "QEI_2INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_2inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_2INP) } # [doc = "QEI_3INP"]
# [inline (always)]
pub fn ctrctl_czc_qei_3inp (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CZC_A :: CTRCTL_CZC_QEI_3INP) } } # [doc = "Field `CTRCTL_DRB` reader - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_R = crate :: BitReader < CTRCTL_DRB_A > ; # [doc = "Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CTRCTL_DRB_A { # [doc = "0: RESUME"]
CTRCTL_DRB_RESUME = 0 , # [doc = "1: CVAE_ACTION"]
CTRCTL_DRB_CVAE_ACTION = 1 , } impl From < CTRCTL_DRB_A > for bool { # [inline (always)]
fn from (variant : CTRCTL_DRB_A) -> Self { variant as u8 != 0 } } impl CTRCTL_DRB_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CTRCTL_DRB_A { match self . bits { false => CTRCTL_DRB_A :: CTRCTL_DRB_RESUME , true => CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION , } } # [doc = "RESUME"]
# [inline (always)]
pub fn is_ctrctl_drb_resume (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_RESUME } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn is_ctrctl_drb_cvae_action (& self) -> bool { * self == CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION } } # [doc = "Field `CTRCTL_DRB` writer - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
pub type CTRCTL_DRB_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CTRCTL_DRB_A > ; impl < 'a , REG , const O : u8 > CTRCTL_DRB_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "RESUME"]
# [inline (always)]
pub fn ctrctl_drb_resume (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_RESUME) } # [doc = "CVAE_ACTION"]
# [inline (always)]
pub fn ctrctl_drb_cvae_action (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_DRB_A :: CTRCTL_DRB_CVAE_ACTION) } } # [doc = "Field `CTRCTL_CVAE` reader - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_R = crate :: FieldReader < CTRCTL_CVAE_A > ; # [doc = "Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CTRCTL_CVAE_A { # [doc = "0: LDVAL"]
CTRCTL_CVAE_LDVAL = 0 , # [doc = "1: NOCHANGE"]
CTRCTL_CVAE_NOCHANGE = 1 , # [doc = "2: ZEROVAL"]
CTRCTL_CVAE_ZEROVAL = 2 , } impl From < CTRCTL_CVAE_A > for u8 { # [inline (always)]
fn from (variant : CTRCTL_CVAE_A) -> Self { variant as _ } } impl crate :: FieldSpec for CTRCTL_CVAE_A { type Ux = u8 ; } impl CTRCTL_CVAE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CTRCTL_CVAE_A > { match self . bits { 0 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) , 1 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) , 2 => Some (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) , _ => None , } } # [doc = "LDVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_ldval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn is_ctrctl_cvae_nochange (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn is_ctrctl_cvae_zeroval (& self) -> bool { * self == CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL } } # [doc = "Field `CTRCTL_CVAE` writer - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
pub type CTRCTL_CVAE_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CTRCTL_CVAE_A > ; impl < 'a , REG , const O : u8 > CTRCTL_CVAE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "LDVAL"]
# [inline (always)]
pub fn ctrctl_cvae_ldval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_LDVAL) } # [doc = "NOCHANGE"]
# [inline (always)]
pub fn ctrctl_cvae_nochange (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_NOCHANGE) } # [doc = "ZEROVAL"]
# [inline (always)]
pub fn ctrctl_cvae_zeroval (self) -> & 'a mut crate :: W < REG > { self . variant (CTRCTL_CVAE_A :: CTRCTL_CVAE_ZEROVAL) } } impl R { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
pub fn ctrctl_en (& self) -> CTRCTL_EN_R { CTRCTL_EN_R :: new ((self . bits & 1) != 0) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
pub fn ctrctl_repeat (& self) -> CTRCTL_REPEAT_R { CTRCTL_REPEAT_R :: new (((self . bits >> 1) & 7) as u8) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
pub fn ctrctl_cm (& self) -> CTRCTL_CM_R { CTRCTL_CM_R :: new (((self . bits >> 4) & 3) as u8) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_clc (& self) -> CTRCTL_CLC_R { CTRCTL_CLC_R :: new (((self . bits >> 7) & 7) as u8) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_cac (& self) -> CTRCTL_CAC_R { CTRCTL_CAC_R :: new (((self . bits >> 10) & 7) as u8) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
pub fn ctrctl_czc (& self) -> CTRCTL_CZC_R { CTRCTL_CZC_R :: new (((self . bits >> 13) & 7) as u8) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
pub fn ctrctl_drb (& self) -> CTRCTL_DRB_R { CTRCTL_DRB_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
pub fn ctrctl_cvae (& self) -> CTRCTL_CVAE_R { CTRCTL_CVAE_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bit 0 - Counter Enable. This bit allows the timer to advance This bit is automatically cleared if REPEAT=0 (do not automatically reload) and the counter value equals zero. CPU Write: A register write that sets the EN bit, the counter value is set per the CVAE value. Hardware: This bit may also be set as the result of an LCOND or ZCOND condition being met and the counter value changed to the load value or zero value, respectively."]
# [inline (always)]
# [must_use]
pub fn ctrctl_en (& mut self) -> CTRCTL_EN_W < CTRCTL_SPEC , 0 > { CTRCTL_EN_W :: new (self) } # [doc = "Bits 1:3 - Repeat. The repeat bit controls whether the counter continues to advance following a zero event, or the exiting of a debug or fault condition. If counting down, a zero event is followed by a load at the next advance condition. If counting up-down, a zero event is followed by an advance event (+1). The intent of encoding 3 is that if the debug condition is in effect, the generation of the load pulse is deferred until the debug condition is over. This allows the counter to reach zero before counting is suspended."]
# [inline (always)]
# [must_use]
pub fn ctrctl_repeat (& mut self) -> CTRCTL_REPEAT_W < CTRCTL_SPEC , 1 > { CTRCTL_REPEAT_W :: new (self) } # [doc = "Bits 4:5 - Count Mode"]
# [inline (always)]
# [must_use]
pub fn ctrctl_cm (& mut self) -> CTRCTL_CM_W < CTRCTL_SPEC , 4 > { CTRCTL_CM_W :: new (self) } # [doc = "Bits 7:9 - Counter Load Control. This field specifies what controls the counter operation with respect to setting the counter to the LD register value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_clc (& mut self) -> CTRCTL_CLC_W < CTRCTL_SPEC , 7 > { CTRCTL_CLC_W :: new (self) } # [doc = "Bits 10:12 - Counter Advance Control. This field specifies what controls the counter operation with respect to advancing (incrementing or decrementing) the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cac (& mut self) -> CTRCTL_CAC_W < CTRCTL_SPEC , 10 > { CTRCTL_CAC_W :: new (self) } # [doc = "Bits 13:15 - Counter Zero Control This field specifies what controls the counter operation with respect to zeroing the counter value. Encodings 1-3 are present based on the CCPC parameter value. Bits 4-5 are present based on the HQEI parameter value. Any encodings not provided are documented as reserved."]
# [inline (always)]
# [must_use]
pub fn ctrctl_czc (& mut self) -> CTRCTL_CZC_W < CTRCTL_SPEC , 13 > { CTRCTL_CZC_W :: new (self) } # [doc = "Bit 17 - Debug Resume Behavior This bit specifies what the device does following the release/exit of debug mode."]
# [inline (always)]
# [must_use]
pub fn ctrctl_drb (& mut self) -> CTRCTL_DRB_W < CTRCTL_SPEC , 17 > { CTRCTL_DRB_W :: new (self) } # [doc = "Bits 28:29 - Counter Value After Enable. This field specifies the initialization condition of the counter when the EN bit is changed from 0 to 1 by a write to the CTRCTL register. Note that an external event can also cause the EN bit to go active."]
# [inline (always)]
# [must_use]
pub fn ctrctl_cvae (& mut self) -> CTRCTL_CVAE_W < CTRCTL_SPEC , 28 > { CTRCTL_CVAE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Counter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CTRCTL_SPEC ; impl crate :: RegisterSpec for CTRCTL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ctrctl::R`](R) reader structure"]
impl crate :: Readable for CTRCTL_SPEC { } # [doc = "`write(|w| ..)` method takes [`ctrctl::W`](W) writer structure"]
impl crate :: Writable for CTRCTL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CTRCTL to value 0xff80"]
impl crate :: Resettable for CTRCTL_SPEC { const RESET_VALUE : Self :: Ux = 0xff80 ; } } # [doc = "LOAD (rw) register accessor: Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@load`]
module"]
pub type LOAD = crate :: Reg < load :: LOAD_SPEC > ; # [doc = "Load Register"]
pub mod load { # [doc = "Register `LOAD` reader"]
pub type R = crate :: R < LOAD_SPEC > ; # [doc = "Register `LOAD` writer"]
pub type W = crate :: W < LOAD_SPEC > ; # [doc = "Field `LOAD_LD` reader - Load Value"]
pub type LOAD_LD_R = crate :: FieldReader < u16 > ; # [doc = "Field `LOAD_LD` writer - Load Value"]
pub type LOAD_LD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
pub fn load_ld (& self) -> LOAD_LD_R { LOAD_LD_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Load Value"]
# [inline (always)]
# [must_use]
pub fn load_ld (& mut self) -> LOAD_LD_W < LOAD_SPEC , 0 > { LOAD_LD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Load Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`load::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`load::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct LOAD_SPEC ; impl crate :: RegisterSpec for LOAD_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`load::R`](R) reader structure"]
impl crate :: Readable for LOAD_SPEC { } # [doc = "`write(|w| ..)` method takes [`load::W`](W) writer structure"]
impl crate :: Writable for LOAD_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets LOAD to value 0"]
impl crate :: Resettable for LOAD_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CC_01 (rw) register accessor: Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cc_01`]
module"]
pub type CC_01 = crate :: Reg < cc_01 :: CC_01_SPEC > ; # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1"]
pub mod cc_01 { # [doc = "Register `CC_01[%s]` reader"]
pub type R = crate :: R < CC_01_SPEC > ; # [doc = "Register `CC_01[%s]` writer"]
pub type W = crate :: W < CC_01_SPEC > ; # [doc = "Field `CC_01_CCVAL` reader - Capture or compare value"]
pub type CC_01_CCVAL_R = crate :: FieldReader < u16 > ; # [doc = "Field `CC_01_CCVAL` writer - Capture or compare value"]
pub type CC_01_CCVAL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 16 , O , u16 > ; impl R { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
pub fn cc_01_ccval (& self) -> CC_01_CCVAL_R { CC_01_CCVAL_R :: new ((self . bits & 0xffff) as u16) } } impl W { # [doc = "Bits 0:15 - Capture or compare value"]
# [inline (always)]
# [must_use]
pub fn cc_01_ccval (& mut self) -> CC_01_CCVAL_W < CC_01_SPEC , 0 > { CC_01_CCVAL_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Register 0 to Capture or Compare Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cc_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cc_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CC_01_SPEC ; impl crate :: RegisterSpec for CC_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`cc_01::R`](R) reader structure"]
impl crate :: Readable for CC_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`cc_01::W`](W) writer structure"]
impl crate :: Writable for CC_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CC_01[%s]
to value 0"]
impl crate :: Resettable for CC_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCCTL_01 (rw) register accessor: Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccctl_01`]
module"]
pub type CCCTL_01 = crate :: Reg < ccctl_01 :: CCCTL_01_SPEC > ; # [doc = "Capture or Compare Control Registers"]
pub mod ccctl_01 { # [doc = "Register `CCCTL_01[%s]` reader"]
pub type R = crate :: R < CCCTL_01_SPEC > ; # [doc = "Register `CCCTL_01[%s]` writer"]
pub type W = crate :: W < CCCTL_01_SPEC > ; # [doc = "Field `CCCTL_01_CCOND` reader - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_R = crate :: FieldReader < CCCTL_01_CCOND_A > ; # [doc = "Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCOND_A { # [doc = "0: NOCAPTURE"]
CCCTL_01_CCOND_NOCAPTURE = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_CCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_CCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_CCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_CCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCOND_A { type Ux = u8 ; } impl CCCTL_01_CCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCOND_A > { match self . bits { 0 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) , 1 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_nocapture (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_ccond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_CCOND` writer - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_CCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "NOCAPTURE"]
# [inline (always)]
pub fn ccctl_01_ccond_nocapture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_NOCAPTURE) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_ccond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCOND_A :: CCCTL_01_CCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ACOND` reader - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_R = crate :: FieldReader < CCCTL_01_ACOND_A > ; # [doc = "Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ACOND_A { # [doc = "0: TIMCLK"]
CCCTL_01_ACOND_TIMCLK = 0 , # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ACOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ACOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ACOND_CC_TRIG_EDGE = 3 , # [doc = "5: CC_TRIG_HIGH"]
CCCTL_01_ACOND_CC_TRIG_HIGH = 5 , } impl From < CCCTL_01_ACOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ACOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ACOND_A { type Ux = u8 ; } impl CCCTL_01_ACOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ACOND_A > { match self . bits { 0 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) , 1 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) , 5 => Some (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) , _ => None , } } # [doc = "TIMCLK"]
# [inline (always)]
pub fn is_ccctl_01_acond_timclk (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn is_ccctl_01_acond_cc_trig_high (& self) -> bool { * self == CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH } } # [doc = "Field `CCCTL_01_ACOND` writer - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
pub type CCCTL_01_ACOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ACOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ACOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TIMCLK"]
# [inline (always)]
pub fn ccctl_01_acond_timclk (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_TIMCLK) } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_EDGE) } # [doc = "CC_TRIG_HIGH"]
# [inline (always)]
pub fn ccctl_01_acond_cc_trig_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ACOND_A :: CCCTL_01_ACOND_CC_TRIG_HIGH) } } # [doc = "Field `CCCTL_01_LCOND` reader - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_R = crate :: FieldReader < CCCTL_01_LCOND_A > ; # [doc = "Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_LCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_LCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_LCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_LCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_LCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_LCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_LCOND_A { type Ux = u8 ; } impl CCCTL_01_LCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_LCOND_A > { match self . bits { 1 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_lcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_LCOND` writer - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_LCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_LCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_LCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_lcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_LCOND_A :: CCCTL_01_LCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_ZCOND` reader - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_R = crate :: FieldReader < CCCTL_01_ZCOND_A > ; # [doc = "Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_ZCOND_A { # [doc = "1: CC_TRIG_RISE"]
CCCTL_01_ZCOND_CC_TRIG_RISE = 1 , # [doc = "2: CC_TRIG_FALL"]
CCCTL_01_ZCOND_CC_TRIG_FALL = 2 , # [doc = "3: CC_TRIG_EDGE"]
CCCTL_01_ZCOND_CC_TRIG_EDGE = 3 , } impl From < CCCTL_01_ZCOND_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_ZCOND_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_ZCOND_A { type Ux = u8 ; } impl CCCTL_01_ZCOND_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_ZCOND_A > { match self . bits { 1 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) , 2 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) , 3 => Some (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) , _ => None , } } # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_rise (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_fall (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn is_ccctl_01_zcond_cc_trig_edge (& self) -> bool { * self == CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE } } # [doc = "Field `CCCTL_01_ZCOND` writer - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
pub type CCCTL_01_ZCOND_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_ZCOND_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_ZCOND_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CC_TRIG_RISE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_rise (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_RISE) } # [doc = "CC_TRIG_FALL"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_fall (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_FALL) } # [doc = "CC_TRIG_EDGE"]
# [inline (always)]
pub fn ccctl_01_zcond_cc_trig_edge (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_ZCOND_A :: CCCTL_01_ZCOND_CC_TRIG_EDGE) } } # [doc = "Field `CCCTL_01_COC` reader - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_R = crate :: BitReader < CCCTL_01_COC_A > ; # [doc = "Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum CCCTL_01_COC_A { # [doc = "0: COMPARE"]
CCCTL_01_COC_COMPARE = 0 , # [doc = "1: CAPTURE"]
CCCTL_01_COC_CAPTURE = 1 , } impl From < CCCTL_01_COC_A > for bool { # [inline (always)]
fn from (variant : CCCTL_01_COC_A) -> Self { variant as u8 != 0 } } impl CCCTL_01_COC_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCCTL_01_COC_A { match self . bits { false => CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE , true => CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE , } } # [doc = "COMPARE"]
# [inline (always)]
pub fn is_ccctl_01_coc_compare (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE } # [doc = "CAPTURE"]
# [inline (always)]
pub fn is_ccctl_01_coc_capture (& self) -> bool { * self == CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE } } # [doc = "Field `CCCTL_01_COC` writer - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
pub type CCCTL_01_COC_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , CCCTL_01_COC_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_COC_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "COMPARE"]
# [inline (always)]
pub fn ccctl_01_coc_compare (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_COMPARE) } # [doc = "CAPTURE"]
# [inline (always)]
pub fn ccctl_01_coc_capture (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_COC_A :: CCCTL_01_COC_CAPTURE) } } # [doc = "Field `CCCTL_01_CC2SELU` reader - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_R = crate :: FieldReader < CCCTL_01_CC2SELU_A > ; # [doc = "Selects the source second CCU event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELU_A { # [doc = "0: SEL_CCU0"]
CCCTL_01_CC2SELU_SEL_CCU0 = 0 , # [doc = "1: SEL_CCU1"]
CCCTL_01_CC2SELU_SEL_CCU1 = 1 , # [doc = "2: SEL_CCU2"]
CCCTL_01_CC2SELU_SEL_CCU2 = 2 , # [doc = "3: SEL_CCU3"]
CCCTL_01_CC2SELU_SEL_CCU3 = 3 , # [doc = "4: SEL_CCU4"]
CCCTL_01_CC2SELU_SEL_CCU4 = 4 , # [doc = "5: SEL_CCU5"]
CCCTL_01_CC2SELU_SEL_CCU5 = 5 , } impl From < CCCTL_01_CC2SELU_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELU_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELU_A { type Ux = u8 ; } impl CCCTL_01_CC2SELU_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELU_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) , 1 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) , 2 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) , 3 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) , 4 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) , 5 => Some (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) , _ => None , } } # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu0 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0 } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu1 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1 } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu2 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2 } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu3 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3 } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu4 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4 } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn is_ccctl_01_cc2selu_sel_ccu5 (& self) -> bool { * self == CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5 } } # [doc = "Field `CCCTL_01_CC2SELU` writer - Selects the source second CCU event."]
pub type CCCTL_01_CC2SELU_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELU_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELU_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCU0"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU0) } # [doc = "SEL_CCU1"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU1) } # [doc = "SEL_CCU2"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU2) } # [doc = "SEL_CCU3"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU3) } # [doc = "SEL_CCU4"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU4) } # [doc = "SEL_CCU5"]
# [inline (always)]
pub fn ccctl_01_cc2selu_sel_ccu5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELU_A :: CCCTL_01_CC2SELU_SEL_CCU5) } } # [doc = "Field `CCCTL_01_CCACTUPD` reader - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_R = crate :: FieldReader < CCCTL_01_CCACTUPD_A > ; # [doc = "CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CCACTUPD_A { # [doc = "0: IMMEDIATELY"]
CCCTL_01_CCACTUPD_IMMEDIATELY = 0 , # [doc = "1: ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_EVT = 1 , # [doc = "2: COMPARE_DOWN_EVT"]
CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT = 2 , # [doc = "3: COMPARE_UP_EVT"]
CCCTL_01_CCACTUPD_COMPARE_UP_EVT = 3 , # [doc = "4: ZERO_LOAD_EVT"]
CCCTL_01_CCACTUPD_ZERO_LOAD_EVT = 4 , # [doc = "5: ZERO_RC_ZERO_EVT"]
CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT = 5 , # [doc = "6: TRIG"]
CCCTL_01_CCACTUPD_TRIG = 6 , } impl From < CCCTL_01_CCACTUPD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CCACTUPD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CCACTUPD_A { type Ux = u8 ; } impl CCCTL_01_CCACTUPD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CCACTUPD_A > { match self . bits { 0 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) , 1 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) , 2 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) , 3 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) , 4 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) , 5 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) , 6 => Some (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) , _ => None , } } # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_immediately (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_down_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_compare_up_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_load_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_zero_rc_zero_evt (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT } # [doc = "TRIG"]
# [inline (always)]
pub fn is_ccctl_01_ccactupd_trig (& self) -> bool { * self == CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG } } # [doc = "Field `CCCTL_01_CCACTUPD` writer - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
pub type CCCTL_01_CCACTUPD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CCACTUPD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CCACTUPD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "IMMEDIATELY"]
# [inline (always)]
pub fn ccctl_01_ccactupd_immediately (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_IMMEDIATELY) } # [doc = "ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_EVT) } # [doc = "COMPARE_DOWN_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_down_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_DOWN_EVT) } # [doc = "COMPARE_UP_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_compare_up_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_COMPARE_UP_EVT) } # [doc = "ZERO_LOAD_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_load_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_LOAD_EVT) } # [doc = "ZERO_RC_ZERO_EVT"]
# [inline (always)]
pub fn ccctl_01_ccactupd_zero_rc_zero_evt (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_ZERO_RC_ZERO_EVT) } # [doc = "TRIG"]
# [inline (always)]
pub fn ccctl_01_ccactupd_trig (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CCACTUPD_A :: CCCTL_01_CCACTUPD_TRIG) } } # [doc = "Field `CCCTL_01_CC2SELD` reader - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_R = crate :: FieldReader < CCCTL_01_CC2SELD_A > ; # [doc = "Selects the source second CCD event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCCTL_01_CC2SELD_A { # [doc = "0: SEL_CCD0"]
CCCTL_01_CC2SELD_SEL_CCD0 = 0 , # [doc = "1: SEL_CCD1"]
CCCTL_01_CC2SELD_SEL_CCD1 = 1 , # [doc = "2: SEL_CCD2"]
CCCTL_01_CC2SELD_SEL_CCD2 = 2 , # [doc = "3: SEL_CCD3"]
CCCTL_01_CC2SELD_SEL_CCD3 = 3 , # [doc = "4: SEL_CCD4"]
CCCTL_01_CC2SELD_SEL_CCD4 = 4 , # [doc = "5: SEL_CCD5"]
CCCTL_01_CC2SELD_SEL_CCD5 = 5 , } impl From < CCCTL_01_CC2SELD_A > for u8 { # [inline (always)]
fn from (variant : CCCTL_01_CC2SELD_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCCTL_01_CC2SELD_A { type Ux = u8 ; } impl CCCTL_01_CC2SELD_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCCTL_01_CC2SELD_A > { match self . bits { 0 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) , 1 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) , 2 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) , 3 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) , 4 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) , 5 => Some (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) , _ => None , } } # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd0 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0 } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd1 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1 } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd2 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2 } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd3 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3 } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd4 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4 } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn is_ccctl_01_cc2seld_sel_ccd5 (& self) -> bool { * self == CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5 } } # [doc = "Field `CCCTL_01_CC2SELD` writer - Selects the source second CCD event."]
pub type CCCTL_01_CC2SELD_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 3 , O , CCCTL_01_CC2SELD_A > ; impl < 'a , REG , const O : u8 > CCCTL_01_CC2SELD_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "SEL_CCD0"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd0 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD0) } # [doc = "SEL_CCD1"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd1 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD1) } # [doc = "SEL_CCD2"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd2 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD2) } # [doc = "SEL_CCD3"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd3 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD3) } # [doc = "SEL_CCD4"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd4 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD4) } # [doc = "SEL_CCD5"]
# [inline (always)]
pub fn ccctl_01_cc2seld_sel_ccd5 (self) -> & 'a mut crate :: W < REG > { self . variant (CCCTL_01_CC2SELD_A :: CCCTL_01_CC2SELD_SEL_CCD5) } } impl R { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_ccond (& self) -> CCCTL_01_CCOND_R { CCCTL_01_CCOND_R :: new ((self . bits & 7) as u8) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_acond (& self) -> CCCTL_01_ACOND_R { CCCTL_01_ACOND_R :: new (((self . bits >> 4) & 7) as u8) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_lcond (& self) -> CCCTL_01_LCOND_R { CCCTL_01_LCOND_R :: new (((self . bits >> 8) & 7) as u8) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
pub fn ccctl_01_zcond (& self) -> CCCTL_01_ZCOND_R { CCCTL_01_ZCOND_R :: new (((self . bits >> 12) & 7) as u8) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
pub fn ccctl_01_coc (& self) -> CCCTL_01_COC_R { CCCTL_01_COC_R :: new (((self . bits >> 17) & 1) != 0) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
pub fn ccctl_01_cc2selu (& self) -> CCCTL_01_CC2SELU_R { CCCTL_01_CC2SELU_R :: new (((self . bits >> 22) & 7) as u8) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
pub fn ccctl_01_ccactupd (& self) -> CCCTL_01_CCACTUPD_R { CCCTL_01_CCACTUPD_R :: new (((self . bits >> 26) & 7) as u8) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
pub fn ccctl_01_cc2seld (& self) -> CCCTL_01_CC2SELD_R { CCCTL_01_CC2SELD_R :: new (((self . bits >> 29) & 7) as u8) } } impl W { # [doc = "Bits 0:2 - Capture Condition. #br# Specifies the condition that generates a capture pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccond (& mut self) -> CCCTL_01_CCOND_W < CCCTL_01_SPEC , 0 > { CCCTL_01_CCOND_W :: new (self) } # [doc = "Bits 4:6 - Advance Condition. #br# Specifies the condition that generates an advance pulse. 6h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_acond (& mut self) -> CCCTL_01_ACOND_W < CCCTL_01_SPEC , 4 > { CCCTL_01_ACOND_W :: new (self) } # [doc = "Bits 8:10 - Load Condition. #br# Specifies the condition that generates a load pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_lcond (& mut self) -> CCCTL_01_LCOND_W < CCCTL_01_SPEC , 8 > { CCCTL_01_LCOND_W :: new (self) } # [doc = "Bits 12:14 - Zero Condition. #br# This field specifies the condition that generates a zero pulse. 4h-Fh = Reserved"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_zcond (& mut self) -> CCCTL_01_ZCOND_W < CCCTL_01_SPEC , 12 > { CCCTL_01_ZCOND_W :: new (self) } # [doc = "Bit 17 - Capture or Compare. #br# Specifies whether the corresponding CC register is used as a capture register or a compare register (never both)."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_coc (& mut self) -> CCCTL_01_COC_W < CCCTL_01_SPEC , 17 > { CCCTL_01_COC_W :: new (self) } # [doc = "Bits 22:24 - Selects the source second CCU event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2selu (& mut self) -> CCCTL_01_CC2SELU_W < CCCTL_01_SPEC , 22 > { CCCTL_01_CC2SELU_W :: new (self) } # [doc = "Bits 26:28 - CCACT shadow register Update Method This field controls how updates to the CCCACT shadow register are performed"]
# [inline (always)]
# [must_use]
pub fn ccctl_01_ccactupd (& mut self) -> CCCTL_01_CCACTUPD_W < CCCTL_01_SPEC , 26 > { CCCTL_01_CCACTUPD_W :: new (self) } # [doc = "Bits 29:31 - Selects the source second CCD event."]
# [inline (always)]
# [must_use]
pub fn ccctl_01_cc2seld (& mut self) -> CCCTL_01_CC2SELD_W < CCCTL_01_SPEC , 29 > { CCCTL_01_CC2SELD_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCCTL_01_SPEC ; impl crate :: RegisterSpec for CCCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccctl_01::R`](R) reader structure"]
impl crate :: Readable for CCCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccctl_01::W`](W) writer structure"]
impl crate :: Writable for CCCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCCTL_01[%s]
to value 0"]
impl crate :: Resettable for CCCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "OCTL_01 (rw) register accessor: CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@octl_01`]
module"]
pub type OCTL_01 = crate :: Reg < octl_01 :: OCTL_01_SPEC > ; # [doc = "CCP Output Control Registers"]
pub mod octl_01 { # [doc = "Register `OCTL_01[%s]` reader"]
pub type R = crate :: R < OCTL_01_SPEC > ; # [doc = "Register `OCTL_01[%s]` writer"]
pub type W = crate :: W < OCTL_01_SPEC > ; # [doc = "Field `OCTL_01_CCPO` reader - CCP Output Source"]
pub type OCTL_01_CCPO_R = crate :: FieldReader < OCTL_01_CCPO_A > ; # [doc = "CCP Output Source\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum OCTL_01_CCPO_A { # [doc = "0: FUNCVAL"]
OCTL_01_CCPO_FUNCVAL = 0 , # [doc = "1: LOAD"]
OCTL_01_CCPO_LOAD = 1 , # [doc = "2: CMPVAL"]
OCTL_01_CCPO_CMPVAL = 2 , # [doc = "4: ZERO"]
OCTL_01_CCPO_ZERO = 4 , # [doc = "5: CAPCOND"]
OCTL_01_CCPO_CAPCOND = 5 , # [doc = "6: FAULTCOND"]
OCTL_01_CCPO_FAULTCOND = 6 , # [doc = "8: CC0_MIRROR_ALL"]
OCTL_01_CCPO_CC0_MIRROR_ALL = 8 , # [doc = "9: CC1_MIRROR_ALL"]
OCTL_01_CCPO_CC1_MIRROR_ALL = 9 , # [doc = "12: DEADBAND"]
OCTL_01_CCPO_DEADBAND = 12 , # [doc = "13: CNTDIR"]
OCTL_01_CCPO_CNTDIR = 13 , } impl From < OCTL_01_CCPO_A > for u8 { # [inline (always)]
fn from (variant : OCTL_01_CCPO_A) -> Self { variant as _ } } impl crate :: FieldSpec for OCTL_01_CCPO_A { type Ux = u8 ; } impl OCTL_01_CCPO_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < OCTL_01_CCPO_A > { match self . bits { 0 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) , 1 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) , 2 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) , 4 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) , 5 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) , 6 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) , 8 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) , 9 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) , 12 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) , 13 => Some (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) , _ => None , } } # [doc = "FUNCVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_funcval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL } # [doc = "LOAD"]
# [inline (always)]
pub fn is_octl_01_ccpo_load (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD } # [doc = "CMPVAL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cmpval (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL } # [doc = "ZERO"]
# [inline (always)]
pub fn is_octl_01_ccpo_zero (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO } # [doc = "CAPCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_capcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn is_octl_01_ccpo_faultcond (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc0_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn is_octl_01_ccpo_cc1_mirror_all (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL } # [doc = "DEADBAND"]
# [inline (always)]
pub fn is_octl_01_ccpo_deadband (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND } # [doc = "CNTDIR"]
# [inline (always)]
pub fn is_octl_01_ccpo_cntdir (& self) -> bool { * self == OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR } } # [doc = "Field `OCTL_01_CCPO` writer - CCP Output Source"]
pub type OCTL_01_CCPO_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , OCTL_01_CCPO_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPO_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "FUNCVAL"]
# [inline (always)]
pub fn octl_01_ccpo_funcval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FUNCVAL) } # [doc = "LOAD"]
# [inline (always)]
pub fn octl_01_ccpo_load (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_LOAD) } # [doc = "CMPVAL"]
# [inline (always)]
pub fn octl_01_ccpo_cmpval (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CMPVAL) } # [doc = "ZERO"]
# [inline (always)]
pub fn octl_01_ccpo_zero (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_ZERO) } # [doc = "CAPCOND"]
# [inline (always)]
pub fn octl_01_ccpo_capcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CAPCOND) } # [doc = "FAULTCOND"]
# [inline (always)]
pub fn octl_01_ccpo_faultcond (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_FAULTCOND) } # [doc = "CC0_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc0_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC0_MIRROR_ALL) } # [doc = "CC1_MIRROR_ALL"]
# [inline (always)]
pub fn octl_01_ccpo_cc1_mirror_all (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CC1_MIRROR_ALL) } # [doc = "DEADBAND"]
# [inline (always)]
pub fn octl_01_ccpo_deadband (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_DEADBAND) } # [doc = "CNTDIR"]
# [inline (always)]
pub fn octl_01_ccpo_cntdir (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPO_A :: OCTL_01_CCPO_CNTDIR) } } # [doc = "Field `OCTL_01_CCPOINV` reader - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_R = crate :: BitReader < OCTL_01_CCPOINV_A > ; # [doc = "CCP Output Invert The output as selected by CCPO is conditionally inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPOINV_A { # [doc = "0: NOINV"]
OCTL_01_CCPOINV_NOINV = 0 , # [doc = "1: INV"]
OCTL_01_CCPOINV_INV = 1 , } impl From < OCTL_01_CCPOINV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPOINV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPOINV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPOINV_A { match self . bits { false => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV , true => OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV , } } # [doc = "NOINV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_noinv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV } # [doc = "INV"]
# [inline (always)]
pub fn is_octl_01_ccpoinv_inv (& self) -> bool { * self == OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV } } # [doc = "Field `OCTL_01_CCPOINV` writer - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
pub type OCTL_01_CCPOINV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPOINV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPOINV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINV"]
# [inline (always)]
pub fn octl_01_ccpoinv_noinv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_NOINV) } # [doc = "INV"]
# [inline (always)]
pub fn octl_01_ccpoinv_inv (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPOINV_A :: OCTL_01_CCPOINV_INV) } } # [doc = "Field `OCTL_01_CCPIV` reader - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_R = crate :: BitReader < OCTL_01_CCPIV_A > ; # [doc = "CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0).\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum OCTL_01_CCPIV_A { # [doc = "0: LOW"]
OCTL_01_CCPIV_LOW = 0 , # [doc = "1: HIGH"]
OCTL_01_CCPIV_HIGH = 1 , } impl From < OCTL_01_CCPIV_A > for bool { # [inline (always)]
fn from (variant : OCTL_01_CCPIV_A) -> Self { variant as u8 != 0 } } impl OCTL_01_CCPIV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> OCTL_01_CCPIV_A { match self . bits { false => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW , true => OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH , } } # [doc = "LOW"]
# [inline (always)]
pub fn is_octl_01_ccpiv_low (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW } # [doc = "HIGH"]
# [inline (always)]
pub fn is_octl_01_ccpiv_high (& self) -> bool { * self == OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH } } # [doc = "Field `OCTL_01_CCPIV` writer - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
pub type OCTL_01_CCPIV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , OCTL_01_CCPIV_A > ; impl < 'a , REG , const O : u8 > OCTL_01_CCPIV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "LOW"]
# [inline (always)]
pub fn octl_01_ccpiv_low (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_LOW) } # [doc = "HIGH"]
# [inline (always)]
pub fn octl_01_ccpiv_high (self) -> & 'a mut crate :: W < REG > { self . variant (OCTL_01_CCPIV_A :: OCTL_01_CCPIV_HIGH) } } impl R { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
pub fn octl_01_ccpo (& self) -> OCTL_01_CCPO_R { OCTL_01_CCPO_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
pub fn octl_01_ccpoinv (& self) -> OCTL_01_CCPOINV_R { OCTL_01_CCPOINV_R :: new (((self . bits >> 4) & 1) != 0) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
pub fn octl_01_ccpiv (& self) -> OCTL_01_CCPIV_R { OCTL_01_CCPIV_R :: new (((self . bits >> 5) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - CCP Output Source"]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpo (& mut self) -> OCTL_01_CCPO_W < OCTL_01_SPEC , 0 > { OCTL_01_CCPO_W :: new (self) } # [doc = "Bit 4 - CCP Output Invert The output as selected by CCPO is conditionally inverted."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpoinv (& mut self) -> OCTL_01_CCPOINV_W < OCTL_01_SPEC , 4 > { OCTL_01_CCPOINV_W :: new (self) } # [doc = "Bit 5 - CCP Initial Value This bit specifies the logical value put on the signal generator state while the counter is disabled (CTRCTL.EN == 0)."]
# [inline (always)]
# [must_use]
pub fn octl_01_ccpiv (& mut self) -> OCTL_01_CCPIV_W < OCTL_01_SPEC , 5 > { OCTL_01_CCPIV_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "CCP Output Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`octl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`octl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct OCTL_01_SPEC ; impl crate :: RegisterSpec for OCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`octl_01::R`](R) reader structure"]
impl crate :: Readable for OCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`octl_01::W`](W) writer structure"]
impl crate :: Writable for OCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets OCTL_01[%s]
to value 0"]
impl crate :: Resettable for OCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "CCACT_01 (rw) register accessor: Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccact_01`]
module"]
pub type CCACT_01 = crate :: Reg < ccact_01 :: CCACT_01_SPEC > ; # [doc = "Capture or Compare Action Registers"]
pub mod ccact_01 { # [doc = "Register `CCACT_01[%s]` reader"]
pub type R = crate :: R < CCACT_01_SPEC > ; # [doc = "Register `CCACT_01[%s]` writer"]
pub type W = crate :: W < CCACT_01_SPEC > ; # [doc = "Field `CCACT_01_ZACT` reader - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_R = crate :: FieldReader < CCACT_01_ZACT_A > ; # [doc = "CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_ZACT_A { # [doc = "0: DISABLED"]
CCACT_01_ZACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_ZACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_ZACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_ZACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_ZACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_ZACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_ZACT_A { type Ux = u8 ; } impl CCACT_01_ZACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_ZACT_A { match self . bits { 0 => CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED , 1 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH , 2 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW , 3 => CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_zact_disabled (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_high (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_low (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_zact_ccp_toggle (& self) -> bool { * self == CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_ZACT` writer - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
pub type CCACT_01_ZACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_ZACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_ZACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_zact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_zact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_zact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_zact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_ZACT_A :: CCACT_01_ZACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_LACT` reader - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_R = crate :: FieldReader < CCACT_01_LACT_A > ; # [doc = "CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_LACT_A { # [doc = "0: DISABLED"]
CCACT_01_LACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_LACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_LACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_LACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_LACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_LACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_LACT_A { type Ux = u8 ; } impl CCACT_01_LACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_LACT_A { match self . bits { 0 => CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED , 1 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH , 2 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW , 3 => CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_lact_disabled (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_high (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_low (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_lact_ccp_toggle (& self) -> bool { * self == CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_LACT` writer - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
pub type CCACT_01_LACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_LACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_LACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_lact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_lact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_lact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_lact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_LACT_A :: CCACT_01_LACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CDACT` reader - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_R = crate :: FieldReader < CCACT_01_CDACT_A > ; # [doc = "CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CDACT_A { # [doc = "0: DISABLED"]
CCACT_01_CDACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CDACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CDACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CDACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CDACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CDACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CDACT_A { type Ux = u8 ; } impl CCACT_01_CDACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CDACT_A { match self . bits { 0 => CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED , 1 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH , 2 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW , 3 => CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cdact_disabled (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_high (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_low (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cdact_ccp_toggle (& self) -> bool { * self == CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CDACT` writer - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
pub type CCACT_01_CDACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CDACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CDACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cdact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cdact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CDACT_A :: CCACT_01_CDACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CUACT` reader - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_R = crate :: FieldReader < CCACT_01_CUACT_A > ; # [doc = "CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CUACT_A { # [doc = "0: DISABLED"]
CCACT_01_CUACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CUACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CUACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CUACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CUACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CUACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CUACT_A { type Ux = u8 ; } impl CCACT_01_CUACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CUACT_A { match self . bits { 0 => CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED , 1 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH , 2 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW , 3 => CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cuact_disabled (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_high (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_low (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cuact_ccp_toggle (& self) -> bool { * self == CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CUACT` writer - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
pub type CCACT_01_CUACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CUACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CUACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cuact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cuact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CUACT_A :: CCACT_01_CUACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2DACT` reader - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_R = crate :: FieldReader < CCACT_01_CC2DACT_A > ; # [doc = "CCP Output Action on CC2D event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2DACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2DACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2DACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2DACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2DACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2DACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2DACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2DACT_A { type Ux = u8 ; } impl CCACT_01_CC2DACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2DACT_A { match self . bits { 0 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED , 1 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH , 2 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW , 3 => CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_disabled (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_high (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_low (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2dact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2DACT` writer - CCP Output Action on CC2D event."]
pub type CCACT_01_CC2DACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2DACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2DACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2dact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2dact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2DACT_A :: CCACT_01_CC2DACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_CC2UACT` reader - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_R = crate :: FieldReader < CCACT_01_CC2UACT_A > ; # [doc = "CCP Output Action on CC2U event.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_CC2UACT_A { # [doc = "0: DISABLED"]
CCACT_01_CC2UACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_CC2UACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_CC2UACT_CCP_LOW = 2 , # [doc = "3: CCP_TOGGLE"]
CCACT_01_CC2UACT_CCP_TOGGLE = 3 , } impl From < CCACT_01_CC2UACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_CC2UACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_CC2UACT_A { type Ux = u8 ; } impl CCACT_01_CC2UACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> CCACT_01_CC2UACT_A { match self . bits { 0 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED , 1 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH , 2 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW , 3 => CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE , _ => unreachable ! () , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_disabled (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_high (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_low (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn is_ccact_01_cc2uact_ccp_toggle (& self) -> bool { * self == CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE } } # [doc = "Field `CCACT_01_CC2UACT` writer - CCP Output Action on CC2U event."]
pub type CCACT_01_CC2UACT_W < 'a , REG , const O : u8 > = crate :: FieldWriterSafe < 'a , REG , 2 , O , CCACT_01_CC2UACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_CC2UACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_cc2uact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_LOW) } # [doc = "CCP_TOGGLE"]
# [inline (always)]
pub fn ccact_01_cc2uact_ccp_toggle (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_CC2UACT_A :: CCACT_01_CC2UACT_CCP_TOGGLE) } } # [doc = "Field `CCACT_01_SWFRCACT` reader - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_R = crate :: FieldReader < CCACT_01_SWFRCACT_A > ; # [doc = "CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum CCACT_01_SWFRCACT_A { # [doc = "0: DISABLED"]
CCACT_01_SWFRCACT_DISABLED = 0 , # [doc = "1: CCP_HIGH"]
CCACT_01_SWFRCACT_CCP_HIGH = 1 , # [doc = "2: CCP_LOW"]
CCACT_01_SWFRCACT_CCP_LOW = 2 , } impl From < CCACT_01_SWFRCACT_A > for u8 { # [inline (always)]
fn from (variant : CCACT_01_SWFRCACT_A) -> Self { variant as _ } } impl crate :: FieldSpec for CCACT_01_SWFRCACT_A { type Ux = u8 ; } impl CCACT_01_SWFRCACT_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < CCACT_01_SWFRCACT_A > { match self . bits { 0 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) , 1 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) , 2 => Some (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) , _ => None , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_disabled (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_high (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn is_ccact_01_swfrcact_ccp_low (& self) -> bool { * self == CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW } } # [doc = "Field `CCACT_01_SWFRCACT` writer - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
pub type CCACT_01_SWFRCACT_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , CCACT_01_SWFRCACT_A > ; impl < 'a , REG , const O : u8 > CCACT_01_SWFRCACT_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "DISABLED"]
# [inline (always)]
pub fn ccact_01_swfrcact_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_DISABLED) } # [doc = "CCP_HIGH"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_high (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_HIGH) } # [doc = "CCP_LOW"]
# [inline (always)]
pub fn ccact_01_swfrcact_ccp_low (self) -> & 'a mut crate :: W < REG > { self . variant (CCACT_01_SWFRCACT_A :: CCACT_01_SWFRCACT_CCP_LOW) } } impl R { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
pub fn ccact_01_zact (& self) -> CCACT_01_ZACT_R { CCACT_01_ZACT_R :: new ((self . bits & 3) as u8) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
pub fn ccact_01_lact (& self) -> CCACT_01_LACT_R { CCACT_01_LACT_R :: new (((self . bits >> 3) & 3) as u8) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
pub fn ccact_01_cdact (& self) -> CCACT_01_CDACT_R { CCACT_01_CDACT_R :: new (((self . bits >> 6) & 3) as u8) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
pub fn ccact_01_cuact (& self) -> CCACT_01_CUACT_R { CCACT_01_CUACT_R :: new (((self . bits >> 9) & 3) as u8) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
pub fn ccact_01_cc2dact (& self) -> CCACT_01_CC2DACT_R { CCACT_01_CC2DACT_R :: new (((self . bits >> 12) & 3) as u8) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
pub fn ccact_01_cc2uact (& self) -> CCACT_01_CC2UACT_R { CCACT_01_CC2UACT_R :: new (((self . bits >> 15) & 3) as u8) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
pub fn ccact_01_swfrcact (& self) -> CCACT_01_SWFRCACT_R { CCACT_01_SWFRCACT_R :: new (((self . bits >> 28) & 3) as u8) } } impl W { # [doc = "Bits 0:1 - CCP Output Action on Zero Specifies what changes occur to CCP output as the result of a zero event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_zact (& mut self) -> CCACT_01_ZACT_W < CCACT_01_SPEC , 0 > { CCACT_01_ZACT_W :: new (self) } # [doc = "Bits 3:4 - CCP Output Action on Load Specifies what changes occur to CCP output as the result of a load event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_lact (& mut self) -> CCACT_01_LACT_W < CCACT_01_SPEC , 3 > { CCACT_01_LACT_W :: new (self) } # [doc = "Bits 6:7 - CCP Output Action on Compare (Down) This field describes the resulting action of the signal generator upon detecting a compare event while counting down."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cdact (& mut self) -> CCACT_01_CDACT_W < CCACT_01_SPEC , 6 > { CCACT_01_CDACT_W :: new (self) } # [doc = "Bits 9:10 - CCP Output Action on Compare (Up) This field describes the resulting action of the signal generator upon detecting a compare event while counting up."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cuact (& mut self) -> CCACT_01_CUACT_W < CCACT_01_SPEC , 9 > { CCACT_01_CUACT_W :: new (self) } # [doc = "Bits 12:13 - CCP Output Action on CC2D event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2dact (& mut self) -> CCACT_01_CC2DACT_W < CCACT_01_SPEC , 12 > { CCACT_01_CC2DACT_W :: new (self) } # [doc = "Bits 15:16 - CCP Output Action on CC2U event."]
# [inline (always)]
# [must_use]
pub fn ccact_01_cc2uact (& mut self) -> CCACT_01_CC2UACT_W < CCACT_01_SPEC , 15 > { CCACT_01_CC2UACT_W :: new (self) } # [doc = "Bits 28:29 - CCP Output Action on Software Froce Output This field describes the resulting action of software force. This action has a shadow register, which will be updated under specific condition. So that this register cannot take into effect immediately."]
# [inline (always)]
# [must_use]
pub fn ccact_01_swfrcact (& mut self) -> CCACT_01_SWFRCACT_W < CCACT_01_SPEC , 28 > { CCACT_01_SWFRCACT_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Capture or Compare Action Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccact_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccact_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CCACT_01_SPEC ; impl crate :: RegisterSpec for CCACT_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ccact_01::R`](R) reader structure"]
impl crate :: Readable for CCACT_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ccact_01::W`](W) writer structure"]
impl crate :: Writable for CCACT_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets CCACT_01[%s]
to value 0"]
impl crate :: Resettable for CCACT_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "IFCTL_01 (rw) register accessor: Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ifctl_01`]
module"]
pub type IFCTL_01 = crate :: Reg < ifctl_01 :: IFCTL_01_SPEC > ; # [doc = "Input Filter Control Register"]
pub mod ifctl_01 { # [doc = "Register `IFCTL_01[%s]` reader"]
pub type R = crate :: R < IFCTL_01_SPEC > ; # [doc = "Register `IFCTL_01[%s]` writer"]
pub type W = crate :: W < IFCTL_01_SPEC > ; # [doc = "Field `IFCTL_01_ISEL` reader - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_R = crate :: FieldReader < IFCTL_01_ISEL_A > ; # [doc = "Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_ISEL_A { # [doc = "0: CCPX_INPUT"]
IFCTL_01_ISEL_CCPX_INPUT = 0 , # [doc = "1: CCPX_INPUT_PAIR"]
IFCTL_01_ISEL_CCPX_INPUT_PAIR = 1 , # [doc = "2: CCP0_INPUT"]
IFCTL_01_ISEL_CCP0_INPUT = 2 , # [doc = "3: TRIG_INPUT"]
IFCTL_01_ISEL_TRIG_INPUT = 3 , # [doc = "4: CCP_XOR"]
IFCTL_01_ISEL_CCP_XOR = 4 , # [doc = "5: FSUB0"]
IFCTL_01_ISEL_FSUB0 = 5 , # [doc = "6: FSUB1"]
IFCTL_01_ISEL_FSUB1 = 6 , # [doc = "7: COMP0"]
IFCTL_01_ISEL_COMP0 = 7 , # [doc = "8: COMP1"]
IFCTL_01_ISEL_COMP1 = 8 , # [doc = "9: COMP2"]
IFCTL_01_ISEL_COMP2 = 9 , } impl From < IFCTL_01_ISEL_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_ISEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_ISEL_A { type Ux = u8 ; } impl IFCTL_01_ISEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_ISEL_A > { match self . bits { 0 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) , 1 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) , 2 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) , 3 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) , 4 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) , 5 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) , 6 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) , 7 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) , 8 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) , 9 => Some (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) , _ => None , } } # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccpx_input_pair (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp0_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn is_ifctl_01_isel_trig_input (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn is_ifctl_01_isel_ccp_xor (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR } # [doc = "FSUB0"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0 } # [doc = "FSUB1"]
# [inline (always)]
pub fn is_ifctl_01_isel_fsub1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1 } # [doc = "COMP0"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp0 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0 } # [doc = "COMP1"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp1 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1 } # [doc = "COMP2"]
# [inline (always)]
pub fn is_ifctl_01_isel_comp2 (& self) -> bool { * self == IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2 } } # [doc = "Field `IFCTL_01_ISEL` writer - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
pub type IFCTL_01_ISEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 4 , O , IFCTL_01_ISEL_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_ISEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "CCPX_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT) } # [doc = "CCPX_INPUT_PAIR"]
# [inline (always)]
pub fn ifctl_01_isel_ccpx_input_pair (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCPX_INPUT_PAIR) } # [doc = "CCP0_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_ccp0_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP0_INPUT) } # [doc = "TRIG_INPUT"]
# [inline (always)]
pub fn ifctl_01_isel_trig_input (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_TRIG_INPUT) } # [doc = "CCP_XOR"]
# [inline (always)]
pub fn ifctl_01_isel_ccp_xor (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_CCP_XOR) } # [doc = "FSUB0"]
# [inline (always)]
pub fn ifctl_01_isel_fsub0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB0) } # [doc = "FSUB1"]
# [inline (always)]
pub fn ifctl_01_isel_fsub1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_FSUB1) } # [doc = "COMP0"]
# [inline (always)]
pub fn ifctl_01_isel_comp0 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP0) } # [doc = "COMP1"]
# [inline (always)]
pub fn ifctl_01_isel_comp1 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP1) } # [doc = "COMP2"]
# [inline (always)]
pub fn ifctl_01_isel_comp2 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_ISEL_A :: IFCTL_01_ISEL_COMP2) } } # [doc = "Field `IFCTL_01_INV` reader - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_R = crate :: BitReader < IFCTL_01_INV_A > ; # [doc = "Input Inversion This bit controls whether the selected input is inverted.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_INV_A { # [doc = "0: NOINVERT"]
IFCTL_01_INV_NOINVERT = 0 , # [doc = "1: INVERT"]
IFCTL_01_INV_INVERT = 1 , } impl From < IFCTL_01_INV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_INV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_INV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_INV_A { match self . bits { false => IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT , true => IFCTL_01_INV_A :: IFCTL_01_INV_INVERT , } } # [doc = "NOINVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_noinvert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT } # [doc = "INVERT"]
# [inline (always)]
pub fn is_ifctl_01_inv_invert (& self) -> bool { * self == IFCTL_01_INV_A :: IFCTL_01_INV_INVERT } } # [doc = "Field `IFCTL_01_INV` writer - Input Inversion This bit controls whether the selected input is inverted."]
pub type IFCTL_01_INV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_INV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_INV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "NOINVERT"]
# [inline (always)]
pub fn ifctl_01_inv_noinvert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_NOINVERT) } # [doc = "INVERT"]
# [inline (always)]
pub fn ifctl_01_inv_invert (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_INV_A :: IFCTL_01_INV_INVERT) } } # [doc = "Field `IFCTL_01_FP` reader - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_R = crate :: FieldReader < IFCTL_01_FP_A > ; # [doc = "Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum IFCTL_01_FP_A { # [doc = "0: _3"]
IFCTL_01_FP__3 = 0 , # [doc = "1: _5"]
IFCTL_01_FP__5 = 1 , # [doc = "2: _8"]
IFCTL_01_FP__8 = 2 , } impl From < IFCTL_01_FP_A > for u8 { # [inline (always)]
fn from (variant : IFCTL_01_FP_A) -> Self { variant as _ } } impl crate :: FieldSpec for IFCTL_01_FP_A { type Ux = u8 ; } impl IFCTL_01_FP_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < IFCTL_01_FP_A > { match self . bits { 0 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__3) , 1 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__5) , 2 => Some (IFCTL_01_FP_A :: IFCTL_01_FP__8) , _ => None , } } # [doc = "_3"]
# [inline (always)]
pub fn is_ifctl_01_fp__3 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__3 } # [doc = "_5"]
# [inline (always)]
pub fn is_ifctl_01_fp__5 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__5 } # [doc = "_8"]
# [inline (always)]
pub fn is_ifctl_01_fp__8 (& self) -> bool { * self == IFCTL_01_FP_A :: IFCTL_01_FP__8 } } # [doc = "Field `IFCTL_01_FP` writer - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
pub type IFCTL_01_FP_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 2 , O , IFCTL_01_FP_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FP_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "_3"]
# [inline (always)]
pub fn ifctl_01_fp__3 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__3) } # [doc = "_5"]
# [inline (always)]
pub fn ifctl_01_fp__5 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__5) } # [doc = "_8"]
# [inline (always)]
pub fn ifctl_01_fp__8 (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FP_A :: IFCTL_01_FP__8) } } # [doc = "Field `IFCTL_01_CPV` reader - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_R = crate :: BitReader < IFCTL_01_CPV_A > ; # [doc = "Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_CPV_A { # [doc = "0: CONSECUTIVE"]
IFCTL_01_CPV_CONSECUTIVE = 0 , # [doc = "1: VOTING"]
IFCTL_01_CPV_VOTING = 1 , } impl From < IFCTL_01_CPV_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_CPV_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_CPV_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_CPV_A { match self . bits { false => IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE , true => IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING , } } # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn is_ifctl_01_cpv_consecutive (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE } # [doc = "VOTING"]
# [inline (always)]
pub fn is_ifctl_01_cpv_voting (& self) -> bool { * self == IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING } } # [doc = "Field `IFCTL_01_CPV` writer - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
pub type IFCTL_01_CPV_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_CPV_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_CPV_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "CONSECUTIVE"]
# [inline (always)]
pub fn ifctl_01_cpv_consecutive (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_CONSECUTIVE) } # [doc = "VOTING"]
# [inline (always)]
pub fn ifctl_01_cpv_voting (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_CPV_A :: IFCTL_01_CPV_VOTING) } } # [doc = "Field `IFCTL_01_FE` reader - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_R = crate :: BitReader < IFCTL_01_FE_A > ; # [doc = "Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum IFCTL_01_FE_A { # [doc = "0: DISABLED"]
IFCTL_01_FE_DISABLED = 0 , # [doc = "1: ENABLED"]
IFCTL_01_FE_ENABLED = 1 , } impl From < IFCTL_01_FE_A > for bool { # [inline (always)]
fn from (variant : IFCTL_01_FE_A) -> Self { variant as u8 != 0 } } impl IFCTL_01_FE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> IFCTL_01_FE_A { match self . bits { false => IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED , true => IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_disabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_ifctl_01_fe_enabled (& self) -> bool { * self == IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED } } # [doc = "Field `IFCTL_01_FE` writer - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
pub type IFCTL_01_FE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , IFCTL_01_FE_A > ; impl < 'a , REG , const O : u8 > IFCTL_01_FE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn ifctl_01_fe_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn ifctl_01_fe_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (IFCTL_01_FE_A :: IFCTL_01_FE_ENABLED) } } impl R { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
pub fn ifctl_01_isel (& self) -> IFCTL_01_ISEL_R { IFCTL_01_ISEL_R :: new ((self . bits & 0x0f) as u8) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
pub fn ifctl_01_inv (& self) -> IFCTL_01_INV_R { IFCTL_01_INV_R :: new (((self . bits >> 7) & 1) != 0) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
pub fn ifctl_01_fp (& self) -> IFCTL_01_FP_R { IFCTL_01_FP_R :: new (((self . bits >> 8) & 3) as u8) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
pub fn ifctl_01_cpv (& self) -> IFCTL_01_CPV_R { IFCTL_01_CPV_R :: new (((self . bits >> 11) & 1) != 0) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
pub fn ifctl_01_fe (& self) -> IFCTL_01_FE_R { IFCTL_01_FE_R :: new (((self . bits >> 12) & 1) != 0) } } impl W { # [doc = "Bits 0:3 - Input Select (CCP0) This field selects the input source to the filter input. 4h-7h = Reserved"]
# [inline (always)]
# [must_use]
pub fn ifctl_01_isel (& mut self) -> IFCTL_01_ISEL_W < IFCTL_01_SPEC , 0 > { IFCTL_01_ISEL_W :: new (self) } # [doc = "Bit 7 - Input Inversion This bit controls whether the selected input is inverted."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_inv (& mut self) -> IFCTL_01_INV_W < IFCTL_01_SPEC , 7 > { IFCTL_01_INV_W :: new (self) } # [doc = "Bits 8:9 - Filter Period. This field specifies the sample period for the input filter. I.e. The input is sampled for FP timer clocks during filtering."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fp (& mut self) -> IFCTL_01_FP_W < IFCTL_01_SPEC , 8 > { IFCTL_01_FP_W :: new (self) } # [doc = "Bit 11 - Consecutive Period/Voting Select This bit controls whether the input filter uses a stricter consecutive period count or majority voting."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_cpv (& mut self) -> IFCTL_01_CPV_W < IFCTL_01_SPEC , 11 > { IFCTL_01_CPV_W :: new (self) } # [doc = "Bit 12 - Filter Enable This bit controls whether the input is filtered by the input filter or bypasses to the edge detect."]
# [inline (always)]
# [must_use]
pub fn ifctl_01_fe (& mut self) -> IFCTL_01_FE_W < IFCTL_01_SPEC , 12 > { IFCTL_01_FE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Input Filter Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ifctl_01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ifctl_01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IFCTL_01_SPEC ; impl crate :: RegisterSpec for IFCTL_01_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`ifctl_01::R`](R) reader structure"]
impl crate :: Readable for IFCTL_01_SPEC { } # [doc = "`write(|w| ..)` method takes [`ifctl_01::W`](W) writer structure"]
impl crate :: Writable for IFCTL_01_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets IFCTL_01[%s]
to value 0"]
impl crate :: Resettable for IFCTL_01_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } # [doc = "TSEL (rw) register accessor: Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tsel`]
module"]
pub type TSEL = crate :: Reg < tsel :: TSEL_SPEC > ; # [doc = "Trigger Select"]
pub mod tsel { # [doc = "Register `TSEL` reader"]
pub type R = crate :: R < TSEL_SPEC > ; # [doc = "Register `TSEL` writer"]
pub type W = crate :: W < TSEL_SPEC > ; # [doc = "Field `TSEL_ETSEL` reader - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_R = crate :: FieldReader < TSEL_ETSEL_A > ; # [doc = "External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use.\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
# [repr (u8)]
pub enum TSEL_ETSEL_A { # [doc = "0: TRIG0"]
TSEL_ETSEL_TRIG0 = 0 , # [doc = "1: TRIG1"]
TSEL_ETSEL_TRIG1 = 1 , # [doc = "2: TRIG2"]
TSEL_ETSEL_TRIG2 = 2 , # [doc = "3: TRIG3"]
TSEL_ETSEL_TRIG3 = 3 , # [doc = "4: TRIG4"]
TSEL_ETSEL_TRIG4 = 4 , # [doc = "5: TRIG5"]
TSEL_ETSEL_TRIG5 = 5 , # [doc = "6: TRIG6"]
TSEL_ETSEL_TRIG6 = 6 , # [doc = "7: TRIG7"]
TSEL_ETSEL_TRIG7 = 7 , # [doc = "8: TRIG8"]
TSEL_ETSEL_TRIG8 = 8 , # [doc = "9: TRIG9"]
TSEL_ETSEL_TRIG9 = 9 , # [doc = "10: TRIG10"]
TSEL_ETSEL_TRIG10 = 10 , # [doc = "11: TRIG11"]
TSEL_ETSEL_TRIG11 = 11 , # [doc = "12: TRIG12"]
TSEL_ETSEL_TRIG12 = 12 , # [doc = "13: TRIG13"]
TSEL_ETSEL_TRIG13 = 13 , # [doc = "14: TRIG14"]
TSEL_ETSEL_TRIG14 = 14 , # [doc = "15: TRIG15"]
TSEL_ETSEL_TRIG15 = 15 , # [doc = "16: TRIG_SUB0"]
TSEL_ETSEL_TRIG_SUB0 = 16 , # [doc = "17: TRIG_SUB1"]
TSEL_ETSEL_TRIG_SUB1 = 17 , } impl From < TSEL_ETSEL_A > for u8 { # [inline (always)]
fn from (variant : TSEL_ETSEL_A) -> Self { variant as _ } } impl crate :: FieldSpec for TSEL_ETSEL_A { type Ux = u8 ; } impl TSEL_ETSEL_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> Option < TSEL_ETSEL_A > { match self . bits { 0 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) , 1 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) , 2 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) , 3 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) , 4 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) , 5 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) , 6 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) , 7 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) , 8 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) , 9 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) , 10 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) , 11 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) , 12 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) , 13 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) , 14 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) , 15 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) , 16 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) , 17 => Some (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) , _ => None , } } # [doc = "TRIG0"]
# [inline (always)]
pub fn is_tsel_etsel_trig0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0 } # [doc = "TRIG1"]
# [inline (always)]
pub fn is_tsel_etsel_trig1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1 } # [doc = "TRIG2"]
# [inline (always)]
pub fn is_tsel_etsel_trig2 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2 } # [doc = "TRIG3"]
# [inline (always)]
pub fn is_tsel_etsel_trig3 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3 } # [doc = "TRIG4"]
# [inline (always)]
pub fn is_tsel_etsel_trig4 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4 } # [doc = "TRIG5"]
# [inline (always)]
pub fn is_tsel_etsel_trig5 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5 } # [doc = "TRIG6"]
# [inline (always)]
pub fn is_tsel_etsel_trig6 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6 } # [doc = "TRIG7"]
# [inline (always)]
pub fn is_tsel_etsel_trig7 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7 } # [doc = "TRIG8"]
# [inline (always)]
pub fn is_tsel_etsel_trig8 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8 } # [doc = "TRIG9"]
# [inline (always)]
pub fn is_tsel_etsel_trig9 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9 } # [doc = "TRIG10"]
# [inline (always)]
pub fn is_tsel_etsel_trig10 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10 } # [doc = "TRIG11"]
# [inline (always)]
pub fn is_tsel_etsel_trig11 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11 } # [doc = "TRIG12"]
# [inline (always)]
pub fn is_tsel_etsel_trig12 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12 } # [doc = "TRIG13"]
# [inline (always)]
pub fn is_tsel_etsel_trig13 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13 } # [doc = "TRIG14"]
# [inline (always)]
pub fn is_tsel_etsel_trig14 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14 } # [doc = "TRIG15"]
# [inline (always)]
pub fn is_tsel_etsel_trig15 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15 } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub0 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0 } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn is_tsel_etsel_trig_sub1 (& self) -> bool { * self == TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1 } } # [doc = "Field `TSEL_ETSEL` writer - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
pub type TSEL_ETSEL_W < 'a , REG , const O : u8 > = crate :: FieldWriter < 'a , REG , 5 , O , TSEL_ETSEL_A > ; impl < 'a , REG , const O : u8 > TSEL_ETSEL_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , REG :: Ux : From < u8 > { # [doc = "TRIG0"]
# [inline (always)]
pub fn tsel_etsel_trig0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG0) } # [doc = "TRIG1"]
# [inline (always)]
pub fn tsel_etsel_trig1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG1) } # [doc = "TRIG2"]
# [inline (always)]
pub fn tsel_etsel_trig2 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG2) } # [doc = "TRIG3"]
# [inline (always)]
pub fn tsel_etsel_trig3 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG3) } # [doc = "TRIG4"]
# [inline (always)]
pub fn tsel_etsel_trig4 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG4) } # [doc = "TRIG5"]
# [inline (always)]
pub fn tsel_etsel_trig5 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG5) } # [doc = "TRIG6"]
# [inline (always)]
pub fn tsel_etsel_trig6 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG6) } # [doc = "TRIG7"]
# [inline (always)]
pub fn tsel_etsel_trig7 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG7) } # [doc = "TRIG8"]
# [inline (always)]
pub fn tsel_etsel_trig8 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG8) } # [doc = "TRIG9"]
# [inline (always)]
pub fn tsel_etsel_trig9 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG9) } # [doc = "TRIG10"]
# [inline (always)]
pub fn tsel_etsel_trig10 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG10) } # [doc = "TRIG11"]
# [inline (always)]
pub fn tsel_etsel_trig11 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG11) } # [doc = "TRIG12"]
# [inline (always)]
pub fn tsel_etsel_trig12 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG12) } # [doc = "TRIG13"]
# [inline (always)]
pub fn tsel_etsel_trig13 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG13) } # [doc = "TRIG14"]
# [inline (always)]
pub fn tsel_etsel_trig14 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG14) } # [doc = "TRIG15"]
# [inline (always)]
pub fn tsel_etsel_trig15 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG15) } # [doc = "TRIG_SUB0"]
# [inline (always)]
pub fn tsel_etsel_trig_sub0 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB0) } # [doc = "TRIG_SUB1"]
# [inline (always)]
pub fn tsel_etsel_trig_sub1 (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_ETSEL_A :: TSEL_ETSEL_TRIG_SUB1) } } # [doc = "Field `TSEL_TE` reader - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_R = crate :: BitReader < TSEL_TE_A > ; # [doc = "Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field\n\nValue on reset: 0"]
# [derive (Clone , Copy , Debug , PartialEq , Eq)]
pub enum TSEL_TE_A { # [doc = "0: DISABLED"]
TSEL_TE_DISABLED = 0 , # [doc = "1: ENABLED"]
TSEL_TE_ENABLED = 1 , } impl From < TSEL_TE_A > for bool { # [inline (always)]
fn from (variant : TSEL_TE_A) -> Self { variant as u8 != 0 } } impl TSEL_TE_R { # [doc = "Get enumerated values variant"]
# [inline (always)]
pub const fn variant (& self) -> TSEL_TE_A { match self . bits { false => TSEL_TE_A :: TSEL_TE_DISABLED , true => TSEL_TE_A :: TSEL_TE_ENABLED , } } # [doc = "DISABLED"]
# [inline (always)]
pub fn is_tsel_te_disabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_DISABLED } # [doc = "ENABLED"]
# [inline (always)]
pub fn is_tsel_te_enabled (& self) -> bool { * self == TSEL_TE_A :: TSEL_TE_ENABLED } } # [doc = "Field `TSEL_TE` writer - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
pub type TSEL_TE_W < 'a , REG , const O : u8 > = crate :: BitWriter < 'a , REG , O , TSEL_TE_A > ; impl < 'a , REG , const O : u8 > TSEL_TE_W < 'a , REG , O > where REG : crate :: Writable + crate :: RegisterSpec , { # [doc = "DISABLED"]
# [inline (always)]
pub fn tsel_te_disabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_DISABLED) } # [doc = "ENABLED"]
# [inline (always)]
pub fn tsel_te_enabled (self) -> & 'a mut crate :: W < REG > { self . variant (TSEL_TE_A :: TSEL_TE_ENABLED) } } impl R { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
pub fn tsel_etsel (& self) -> TSEL_ETSEL_R { TSEL_ETSEL_R :: new ((self . bits & 0x1f) as u8) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
pub fn tsel_te (& self) -> TSEL_TE_R { TSEL_TE_R :: new (((self . bits >> 9) & 1) != 0) } } impl W { # [doc = "Bits 0:4 - External Trigger Select. #br# This selects which System Event is used if the input filter selects trigger. Triggers 0-15 are used to connect triggers generated by other timer modules in the same power domain. Refer to the SoC datasheet to get details. Triggers 16 and 17 are connected to event manager subscriber ports. Event lines 18-31 are reserved for future use."]
# [inline (always)]
# [must_use]
pub fn tsel_etsel (& mut self) -> TSEL_ETSEL_W < TSEL_SPEC , 0 > { TSEL_ETSEL_W :: new (self) } # [doc = "Bit 9 - Trigger Enable. This selects whether a trigger is enabled or not for this counter 0x0 = Triggers are not used 0x1 = Triggers are used as selected by the ETSEL field"]
# [inline (always)]
# [must_use]
pub fn tsel_te (& mut self) -> TSEL_TE_W < TSEL_SPEC , 9 > { TSEL_TE_W :: new (self) } # [doc = r" Writes raw bits to the register."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
# [inline (always)]
pub unsafe fn bits (& mut self , bits : u32) -> & mut Self { self . bits = bits ; self } } # [doc = "Trigger Select\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct TSEL_SPEC ; impl crate :: RegisterSpec for TSEL_SPEC { type Ux = u32 ; } # [doc = "`read()` method returns [`tsel::R`](R) reader structure"]
impl crate :: Readable for TSEL_SPEC { } # [doc = "`write(|w| ..)` method takes [`tsel::W`](W) writer structure"]
impl crate :: Writable for TSEL_SPEC { const ZERO_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; const ONE_TO_MODIFY_FIELDS_BITMAP : Self :: Ux = 0 ; } # [doc = "`reset()` method sets TSEL to value 0"]
impl crate :: Resettable for TSEL_SPEC { const RESET_VALUE : Self :: Ux = 0 ; } } } # [no_mangle]
static mut DEVICE_PERIPHERALS : bool = false ; # [doc = r" All the peripherals."]
# [allow (non_snake_case)]
pub struct Peripherals { # [doc = "UART0"]
pub UART0 : UART0 , # [doc = "FLASHCTL"]
pub FLASHCTL : FLASHCTL , # [doc = "SPI0"]
pub SPI0 : SPI0 , # [doc = "I2C0"]
pub I2C0 : I2C0 , # [doc = "CPUSS"]
pub CPUSS : CPUSS , # [doc = "GPIOA"]
pub GPIOA : GPIOA , # [doc = "UART1"]
pub UART1 : UART1 , # [doc = "WWDT0"]
pub WWDT0 : WWDT0 , # [doc = "DEBUGSS"]
pub DEBUGSS : DEBUGSS , # [doc = "VREF"]
pub VREF : VREF , # [doc = "CRC"]
pub CRC : CRC , # [doc = "OPA0"]
pub OPA0 : OPA0 , # [doc = "TIMG1"]
pub TIMG1 : TIMG1 , # [doc = "DMA"]
pub DMA : DMA , # [doc = "COMP0"]
pub COMP0 : COMP0 , # [doc = "SYSCTL"]
pub SYSCTL : SYSCTL , # [doc = "OPA1"]
pub OPA1 : OPA1 , # [doc = "I2C1"]
pub I2C1 : I2C1 , # [doc = "IOMUX"]
pub IOMUX : IOMUX , # [doc = "TIMG2"]
pub TIMG2 : TIMG2 , # [doc = "TIMG4"]
pub TIMG4 : TIMG4 , # [doc = "ADC0"]
pub ADC0 : ADC0 , # [doc = "ADC0_SVT"]
pub ADC0_SVT : ADC0_SVT , # [doc = "WUC"]
pub WUC : WUC , # [doc = "TIMG0"]
pub TIMG0 : TIMG0 , } impl Peripherals { # [doc = r" Returns all the peripherals *once*."]
# [cfg (feature = "critical-section")]
# [inline]
pub fn take () -> Option < Self > { critical_section :: with (| _ | { if unsafe { DEVICE_PERIPHERALS } { return None } Some (unsafe { Peripherals :: steal () }) }) } # [doc = r" Unchecked version of `Peripherals::take`."]
# [doc = r""]
# [doc = r" # Safety"]
# [doc = r""]
# [doc = r" Each of the returned peripherals must be used at most once."]
# [inline]
pub unsafe fn steal () -> Self { DEVICE_PERIPHERALS = true ; Peripherals { UART0 : UART0 { _marker : PhantomData } , FLASHCTL : FLASHCTL { _marker : PhantomData } , SPI0 : SPI0 { _marker : PhantomData } , I2C0 : I2C0 { _marker : PhantomData } , CPUSS : CPUSS { _marker : PhantomData } , GPIOA : GPIOA { _marker : PhantomData } , UART1 : UART1 { _marker : PhantomData } , WWDT0 : WWDT0 { _marker : PhantomData } , DEBUGSS : DEBUGSS { _marker : PhantomData } , VREF : VREF { _marker : PhantomData } , CRC : CRC { _marker : PhantomData } , OPA0 : OPA0 { _marker : PhantomData } , TIMG1 : TIMG1 { _marker : PhantomData } , DMA : DMA { _marker : PhantomData } , COMP0 : COMP0 { _marker : PhantomData } , SYSCTL : SYSCTL { _marker : PhantomData } , OPA1 : OPA1 { _marker : PhantomData } , I2C1 : I2C1 { _marker : PhantomData } , IOMUX : IOMUX { _marker : PhantomData } , TIMG2 : TIMG2 { _marker : PhantomData } , TIMG4 : TIMG4 { _marker : PhantomData } , ADC0 : ADC0 { _marker : PhantomData } , ADC0_SVT : ADC0_SVT { _marker : PhantomData } , WUC : WUC { _marker : PhantomData } , TIMG0 : TIMG0 { _marker : PhantomData } , } } }