ARM Ltd. ARM Musca_B1 ARMv8-M Mainline 1.0 ARM 32-bit v8-M Mainline based device ARM Limited (ARM) is supplying this software for use with Cortex-M\n processor based microcontroller, but can be equally used for other\n suitable processor architectures. This file can be freely distributed.\n Modifications to this file shall be clearly marked.\n \n THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. CM33 r0p2 little true true 4 false 8 8 32 32 read-write 0x00000000 0xFFFFFFFF SYSINFO 1.0 System Information SYSINFO 0x40020000 32 read-only 0 0x1000 registers SYS_VERSION System Version Register 0x00 0x22041743 read-only PART_NUMBER Part Number for the SSE-200 [11:0] DESIGNER_ID Arm Product with designer code 0x41 [19:12] MINOR_REVISION Minor Revision [23:20] MAJOR_REVISION Major Revision [27:24] CONFIGURATION CONFIGURATION for SSE-200 r2: 0x2 [31:28] SYS_CONFIG System Hardware Configuration register 0x04 read-only SRAM_NUM_BANK SRAM Number of Banks [3:0] SRAM_ADDR_WIDTH SRAM Bank Address Width [8:4] CPU0_HAS_TCM CPU 0 has Data TCM: [9:9] No CPU 0 does not have Data TCM 0 Yes CPU 0 has Data TCM 1 CPU1_HAS_TCM CPU 1 has Data TCM: [10:10] No CPU 1 does not have Data TCM 0 Yes CPU 1 has Data TCM 1 HAS_CRYPTO Whether CryptoCell Included: [12:12] No CryptoCell Not Included 0 Yes CryptoCell Included 1 CPU0_TCM_BANK_NUM The SRAM Bank that maps CPU0 Data TCM [19:16] CPU1_TCM_BANK_NUM Number of SRAM banks [23:20] Four 4 SRAM Banks 0x3 Three 3 SRAM Banks 0x2 Two 2 SRAM Banks 0x1 Otherwise Otherwise 0x0 CPU0_TYPE CPU 0 Core Type [27:24] Not Exist Does Not Exist 0x0 CM33 Cortex-M33 Core 0x2 CPU1_TYPE CPU 1 Core Type [31:28] Not Exist Does Not Exist 0x0 CM33 Cortex-M33 Core 0x2 PIDR4 Peripheral ID 4 0xFD0 read-only 0x00000004 PIDR0 Peripheral ID 0 0xFE0 read-only 0x00000058 PIDR1 Peripheral ID 1 0xFE4 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 read-only 0x0000000B PIDR3 Peripheral ID 3 0xFEC read-only 0x00000000 CIDR0 Component ID 0 0xFF0 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 read-only 0x00000005 CIDR3 Component ID 3 0xFFC read-only 0x000000B1 SYSINFO_Secure System Information (Secure) SYSINFO (Secure) 0x50020000 SystemControl 1.0 System Control SYSCTRL 0x50021000 32 read-write 0 0x1000 registers SECDBGSTAT Secure Debug Configuration Status 0x00 read-only 0x00000000 DBGEN_I_STATUS Debug enable value [0:0] enable debug enable 1 disable debug disable 0 DBGEN_SEL_STATUS Debug enable selector value [1:1] enable debug enable selector 1 disable debug disable selector 0 NIDEN_I_STATUS Non-invasive debug enable value [2:2] enable non-invasive debug enable 1 disable non-invasive debug disable 0 NIDEN_SEL_STATUS Non-invasive debug enable selector value [3:3] enable non-invasive debug enable selector 1 disable non-invasive debug disable selector 0 SPIDEN_I_STATUS Secure privilege invasive debug enable value [4:4] enable Secure privilege invasive debug enable 1 disable Secure privilege invasive debug disable 0 SPIDEN_SEL_STATUS Secure privilege invasive debug enable selector value [5:5] enable Secure privilege invasive debug enable selector 1 disable Secure privilege invasive debug disable selector 0 SPNIDEN_STATUS Secure privilege non-invasive debug enable value [6:6] enable Secure privilege non-invasive debug enable 1 disable Secure privilege non-invasive debug disable 0 SPNIDEN_SEL_STATUS Secure privilege non-invasive debug enable selector value [7:7] enable Secure privilege non-invasive debug enable selector 1 disable Secure privilege non-invasive debug disable selector 0 SECDBGSET Secure Debug Configuration Set 0x04 write-only DBGEN_I_SET High active debug enable set control [0:0] DBGEN_SEL_SET Debug enable selector set control [1:1] enable debug enable selector set control 1 disable debug disable selector set control 0 NIDEN_I_SET Non-invasive debug enable set control [2:2] enable non-invasive debug enable set control 1 disable non-invasive debug disable set control 0 NIDEN_SEL_SET Non-invasive debug enable selector set control [3:3] enable non-invasive debug enable selector set control 1 disable non-invasive debug disable selector set control 0 SPIDEN_I_SET Secure privilege invasive debug enable set control [4:4] enable Secure privilege invasive debug enable set control 1 disable Secure privilege invasive debug disable set control 0 SPIDEN_SEL_SET Secure privilege invasive debug enable selector set control [5:5] enable Secure privilege invasive debug enable selector set control 1 disable Secure privilege invasive debug disable selector set control 0 SPNIDEN_I_SET Secure privilege non-invasive debug enable set control [6:6] enable Secure privilege non-invasive debug enable set control 1 disable Secure privilege non-invasive debug disable set control 0 SPNIDEN_SEL_SET Secure privilege non-invasive debug enable selector set control [7:7] enable Secure privilege non-invasive debug enable selector set control 1 disable Secure privilege non-invasive debug disable selector set control 0 SECDBGCLR Secure Debug Configuration Clear 0x08 write-only DBGEN_I_CLR Debug enable clear control [0:0] enable debug enable clear control 1 disable debug disable clear control 0 DBGEN_SEL_CLR Debug enable selector clear control [1:1] enable debug enable selector clear control 1 disable debug disable selector clear control 0 NIDEN_I_CLR Non-invasive debug enable clear control [2:2] enable non-invasive debug enable clear control 1 disable non-invasive debug disable clear control 0 NIDEN_SEL_CLR Non-invasive debug enable selector clear control [3:3] enable non-invasive debug enable selector clear control 1 disable non-invasive debug disable selector clear control 0 SPIDEN_I_CLR Secure privilege invasive debug enable clear control [4:4] enable Secure privilege invasive debug enable clear control 1 disable Secure privilege invasive debug disable clear control 0 SPIDEN_SEL_CLR Secure privilege invasive debug enable selector clear control [5:5] enable Secure privilege invasive debug enable selector clear control 1 disable Secure privilege invasive debug disable selector clear control 0 SPNIDEN_I_CLR Secure privilege non-invasive debug enable clear control [6:6] enable Secure privilege non-invasive debug enable clear control 1 disable Secure privilege non-invasive debug disable clear control 0 SPNIDEN_SEL_CLR Secure privilege non-invasive debug enable selector clear control [7:7] enable Secure privilege non-invasive debug enable selector clear control 1 disable Secure privilege non-invasive debug disable selector clear control 0 SCSECCTRL System Security Control 0x0C 0x00000000 read-write CERTDISABLE Control to disable certification path [0:0] disable control to disable certification path 1 enable control to enable certification path 0 CERTREADEN Control to enable read access on the certification path as long as CERTDISABLE is also LOW [1:1] enable control to enable read access on the certification path as long as CERTDISABLE is also LOW 1 disable control to disable read access on the certification path as long as CERTDISABLE is also LOW 0 SCSECCFGLOCK Control to disable writes to security-related control registers in this register block [2:2] disable control to disable writes to security-related control registers in this register block 1 enable control to enable writes to security-related control registers in this register block 0 CERTDISABLED Indicates that the Certification write path has been disabled [16:16] disabled Certification write path has been disabled 1 enabled Certification write path has been enabled 0 CERTREADENABLED Indicates whether the certification read access is enabled [17:17] enabled certification read access is enabled 1 disabled certification read access is disabled 0 FCLK_DIV Fast Clock Divider Configuration 0x10 read-write FCLKDIV FCLK from MAINCLK Clock Divider Ratio Request [4:0] FCLKDIV_CUR Clock Divider Current Value. [20:16] read-only SYSCLK_DIV System Clock Divider Configuration 0x14 read-write SYSCLKDIV SYSCLK from FCLK Clock Divider Ratio Request [4:0] SYSCLKDIV_CUR Clock Divider Current Value [20:16] read-only CLOCK_FORCE Clock Force 0x18 read-write MAINCLK_FORCE Force MAINCLK to run when set to HIGH [0:0] SYSSYSCLK_FORCE Force Base element Local SYSCLK to run when set to HIGH [1:1] SYSFCLK_FORCE Force Base element Local FCLK to run when set to HIGH [2:2] SRAMSYSCLK_FORCE Force SRAM Local SYSCLK to run when set to HIGH [3:3] SRAMFCLK_FORCE Force SRAM Local FCLK to run when set to HIGH [4:4] CPUSYSCLK_FORCE Force all CPU SYSCLK to run when set to HIGH [5:5] CPUFCLK_FORCE Force all CPU FCLK to run when set to HIGH [6:6] CRYPTOSYSCLK_FORCE Force all CryptoCell clocks to run when set to HIGH [7:7] FCLKHINTGATE_ENABLE Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF [8:8] enable Enable FCLK gating by HINTSYSCLKEN when CPU 1 is OFF 1 latency improve SRAM3 access latency at the cost of increased power consumption 0 RESET_SYNDROME Reset Syndrome 0x100 read-write 0x00000001 PoR Power-on [0:0] write-only NSWD Non-secure watchdog [1:1] write-only SWD Secure watchdog [2:2] write-only S32KWD Watchdog on the S32KCLK clock [3:3] write-only SYSRSTREQ0 CPU 0 System Reset Request [4:4] write-only SYSRSTREQ1 CPU 1 System Reset Request [5:5] write-only LOCKUP0 CPU 0 Lock-up Status [6:6] write-only LOCKUP1 CPU 1 Lock-up Status [7:7] write-only RESETREQ External Reset Request [8:8] write-only SWRESETREQ Software Reset Request [9:9] write-only RESET_MASK Reset Mask 0x104 read-write 0x00000030 NSWD_EN Enable NON-SECURE WATCHDOG Reset [1:1] read-write enabled Enable NON-SECURE WATCHDOG Reset 1 disabled Disabled NON-SECURE WATCHDOG Reset 0 SYSRSTREQ0_EN Enable Merging CPU 0 System Reset Request [4:4] read-write enabled Enable Merging CPU 0 System Reset Request 1 disabled Disabled Merging CPU 0 System Reset Request 0 SYSRSTREQ1_EN Enable Merging CPU 0 System Reset Request [5:5] read-write enabled Enable Merging CPU 1 System Reset Request 1 disabled Disabled Merging CPU 1 System Reset Request 0 SWRESET Software Reset 0x108 write-only 0x00000000 SWRESETREQ High Active Software Reset Request [9:9] write-only GRETREG General Purpose Retention 0x10C read-write 0x00000000 GRETREG General Purpose Retention Register [15:0] read-write INITSVRTOR0 Initial Secure Reset Vector Register For CPU 0 0x110 read-write INITSVTOR0 Default Secure Vector table offset at reset for CPU 0 [31:7] read-write INITSVRTOR1 Initial Secure Reset Vector Register For CPU 1 0x114 read-write INITSVTOR1 Default Secure Vector table offset at reset for CPU 1 [31:7] read-write CPUWAIT CPU Boot wait control after reset 0x118 read-write CPU0WAIT CPU 0 waits at boot and whether CPU1 powers up [0:0] read-write normally or power-up CPU0 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 powers up 0 wait or no power-up CPU0 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 do not power up 1 CPU1WAIT CPU 1 waits at boot and whether CPU0 powers up [1:1] read-write normally or power-up CPU1 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 powers up 0 wait or no power-up CPU1 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 0 do not power up 1 NMI_ENABLE NMI Enable Register 0x11C read-write 0x00000000 CPU0_INTNMI_ENABLE CPU0 Internally Sourced NMI Enable [0:0] read-write enable CPU0 Internally Sourced NMI Enabled 1 disabled CPU0 Internally Sourced NMI Disabled 0 CPU1_INTNMI_ENABLE CPU1 Internally Sourced NMI Enable [1:1] read-write enable CPU1 Internally Sourced NMI Enabled 1 disabled CPU1 Internally Sourced NMI Disabled 0 CPU0_EXPNMI_ENABLE CPU0 Externally Sourced NMI Enable [16:16] read-write enable CPU0 Externally Sourced NMI Enabled 1 disabled CPU0 Externally Sourced NMI Disabled 0 CPU1_EXPNMI_ENABLE CPU1 Externally Sourced NMI Enable [17:17] read-write enable CPU1 Externally Sourced NMI Enabled 1 disabled CPU1 Externally Sourced NMI Disabled 0 WICCTRL WIC request and acknowledge handshake 0x120 read-write 0x00000000 CPU0WICEN_STATUS CPU 0 WIC Enable Request Status [0:0] read-only enable CPU 0 WIC request enabled 1 disabled CPU 0 WIC request disabled 0 CPU1WICEN_STATUS CPU 1 WIC Enable Request Status [1:1] read-only enable CPU 1 WIC request enabled 1 disabled CPU 1 WIC request disabled 0 CPU0WICEN_SET High Active CPU 0 WIC Enable Request Set [4:4] write-only CPU1WICEN_SET High Active CPU 1 WIC Enable Request Set [5:5] write-only CPU0WICEN_CLR High Active CPU 0 WIC Enable Request Clear [8:8] write-only CPU1WICEN_CLR High Active CPU 1 WIC Enable Request Clear [9:9] write-only CPU0WICRDY CPU 0 WIC Enable Acknowledge [16:16] read-only enabled CPU 0 WIC Enabled 1 disabled CPU 0 WIC Disabled 0 CPU1WICRDY CPU 1 WIC Enable Acknowledge [17:17] read-only enabled CPU 1 WIC Enabled 1 disabled CPU 1 WIC Disabled 0 EWCTRL External Wakeup Control 0x124 read-write 0x00000000 EWC0EN_STATUS External Wakeup Controller 0 Enable [0:0] read-only enable External Wakeup Controller 0 Enabled 1 disabled External Wakeup Controller 0 Disabled 0 EWC1EN_STATUS External Wakeup Controller 1 Enable [1:1] read-only enable External Wakeup Controller 1 Enabled 1 disabled External Wakeup Controller 1 Disabled 0 EWC0EN_SET EHigh Active External Wakeup Controller 0 Set [4:4] write-only EWC1EN_SET High Active External Wakeup Controller 1 Set [5:5] write-only EWC0EN_CLR High Active External Wakeup Controller 0 Clear [8:8] write-only EWC1EN_CLR High Active External Wakeup Controller 1 Clear [9:9] write-only PDCM_PD_SYS_SENSE External Wakeup Control 0x200 read-write 0x0000007F S_PD_SYS_ON Enable PD_SYS ON Sensitivity [0:0] read-write enable Keep PD_SYS awake after powered ON 1 S_PD_CPU0CORE_ON Tied to HIGH [1:1] read-only high PD_SYS always tries to stay ON if PD_CPU0CORE is ON 1 S_PD_CPU1CORE_ON Tied to HIGH [2:2] read-only high PD_SYS always tries to stay ON if PD_CPU1CORE is ON 1 S_PD_SRAM0_ON Tied to HIGH [3:3] read-only high PD_SYS always tries to keep ON if SRAM0 power domain is ON 1 S_PD_SRAM1_ON Tied to HIGH [4:4] read-only high PD_SYS always tries to keep ON if SRAM1 power domain is ON 1 S_PD_SRAM2_ON Tied to HIGH [5:5] read-only high PD_SYS always tries to keep ON if SRAM2 power domain is ON 1 S_PD_SRAM3_ON Tied to HIGH [6:6] read-only high PD_SYS always tries to keep ON if SRAM3 power domain is ON 1 S_PD_CRYPTO_ON Tied to HIGH [12:12] read-only high PD_SYS always tries to keep ON if S_PD_CRYPTO_ON is ON 1 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity [16:16] read-write enable Enable PDEXPIN[0] signal Sensitivity. 1 disabled Disable PDEXPIN[0] signal Sensitivity. 0 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity [17:17] read-write enable Enable PDEXPIN[1] signal Sensitivity. 1 disabled Disable PDEXPIN[1] signal Sensitivity. 0 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity [18:18] read-write enable Enable PDEXPIN[2] signal Sensitivity. 1 disabled Disable PDEXPIN[2] signal Sensitivity. 0 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity [19:19] read-write enable Enable PDEXPIN[3] signal Sensitivity. 1 disabled Disable PDEXPIN[3] signal Sensitivity. 0 PDCM_PD_SRAM0_SENSE Power Control Depedendency Matrix PD_SRAM0 Power Domain Sensitivity 0x20C read-write 0x00000000 S_PD_SYS_ON Enable sensitivity to PD_SYS [0:0] read-write enable Enable sensitivity to PD_SYS 1 disable Disable sensitivity to PD_SYS 0 S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE [1:1] read-write enable Enable sensitivity to PD_CPU0CORE 1 disable Disable sensitivity to PD_CPU0CORE 0 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE [2:2] read-write enable Enable sensitivity to PD_CPU1CORE 1 disable Disable sensitivity to PD_CPU1CORE 0 S_PD_SRAM0_ON Enable sensitivity to PD_SRAM0 [3:3] read-write enable Enable sensitivity to PD_SRAM0 1 disable Disable sensitivity to PD_SRAM0 0 S_PD_SRAM1_ON Tied LOW [4:4] read-only Low Ignores PD_SRAM1 state 0 S_PD_SRAM2_ON Tied LOW [5:5] read-only Low Ignores PD_SRAM2 state 0 S_PD_SRAM3_ON Tied LOW [6:6] read-only Low Ignores PD_SRAM3 state 0 S_PD_CRYPTO_ON Tied LOW [12:12] read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity [16:16] read-write enable Enable PDEXPIN[0] signal Sensitivity 1 disable Disable PDEXPIN[0] signal Sensitivity 0 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity [17:17] read-write enable Enable PDEXPIN[1] signal Sensitivity 1 disable Disable PDEXPIN[1] signal Sensitivity 0 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity [18:18] read-write enable Enable PDEXPIN[2] signal Sensitivity 1 disable Disable PDEXPIN[2] signal Sensitivity 0 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity [19:19] read-write enable Enable PDEXPIN[3] signal Sensitivity 1 disable Disable PDEXPIN[3] signal Sensitivity 0 PDCM_PD_SRAM1_SENSE Power Control Depedendency Matrix PD_SRAM1 Power Domain Sensitivity 0x210 read-write 0x00000000 S_PD_SYS_ON Enable sensitivity to PD_SYS [0:0] read-write enable Enable sensitivity to PD_SYS 1 disable Disable sensitivity to PD_SYS 0 S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE [1:1] read-write enable Enable sensitivity to PD_CPU0CORE 1 disable Disable sensitivity to PD_CPU0CORE 0 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE [2:2] read-write enable Enable sensitivity to PD_CPU1CORE 1 disable Disable sensitivity to PD_CPU1CORE 0 S_PD_SRAM0_ON Tied LOW [3:3] read-only Low Ignores PD_SRAM0 state 0 S_PD_SRAM1_ON Enable sensitivity to PD_SRAM1 [4:4] read-write enable Enable sensitivity to PD_SRAM1 1 disable Disable sensitivity to PD_SRAM1 0 S_PD_SRAM2_ON Tied LOW [5:5] read-only Low Ignores PD_SRAM2 state 0 S_PD_SRAM3_ON Tied LOW [6:6] read-only Low Ignores PD_SRAM3 state 0 S_PD_CRYPTO_ON Tied LOW [12:12] read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity [16:16] read-write enable Enable PDEXPIN[0] signal Sensitivity 1 disable Disable PDEXPIN[0] signal Sensitivity 0 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity [17:17] read-write enable Enable PDEXPIN[1] signal Sensitivity 1 disable Disable PDEXPIN[1] signal Sensitivity 0 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity [18:18] read-write enable Enable PDEXPIN[2] signal Sensitivity 1 disable Disable PDEXPIN[2] signal Sensitivity 0 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity [19:19] read-write enable Enable PDEXPIN[3] signal Sensitivity 1 disable Disable PDEXPIN[3] signal Sensitivity 0 PDCM_PD_SRAM2_SENSE Power Control Depedendency Matrix PD_SRAM2 Power Domain Sensitivity 0x214 read-write 0x00000000 S_PD_SYS_ON Enable sensitivity to PD_SYS [0:0] read-write enable Enable sensitivity to PD_SYS 1 disable Disable sensitivity to PD_SYS 0 S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE [1:1] read-write enable Enable sensitivity to PD_CPU0CORE 1 disable Disable sensitivity to PD_CPU0CORE 0 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE [2:2] read-write enable Enable sensitivity to PD_CPU1CORE 1 disable Disable sensitivity to PD_CPU1CORE 0 S_PD_SRAM0_ON Tied LOW [3:3] read-only Low Ignores PD_SRAM0 state 0 S_PD_SRAM1_ON Tied LOW [4:4] read-only Low Ignores PD_SRAM1 state 0 S_PD_SRAM2_ON Enable sensitivity to PD_SRAM2 [5:5] read-write enable Enable sensitivity to PD_SRAM2 1 disable Disable sensitivity to PD_SRAM2 0 S_PD_SRAM3_ON Tied LOW [6:6] read-only Low Ignores PD_SRAM3 state 0 S_PD_CRYPTO_ON Tied LOW [12:12] read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity [16:16] read-write enable Enable PDEXPIN[0] signal Sensitivity 1 disable Disable PDEXPIN[0] signal Sensitivity 0 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity [17:17] read-write enable Enable PDEXPIN[1] signal Sensitivity 1 disable Disable PDEXPIN[1] signal Sensitivity 0 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity [18:18] read-write enable Enable PDEXPIN[2] signal Sensitivity 1 disable Disable PDEXPIN[2] signal Sensitivity 0 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity [19:19] read-write enable Enable PDEXPIN[3] signal Sensitivity 1 disable Disable PDEXPIN[3] signal Sensitivity 0 PDCM_PD_SRAM3_SENSE Power Control Depedendency Matrix PD_SRAM3 Power Domain Sensitivity 0x218 read-write 0x00000000 S_PD_SYS_ON Enable sensitivity to PD_SYS [0:0] read-write enable Enable sensitivity to PD_SYS 1 disable Disable sensitivity to PD_SYS 0 S_PD_CPU0CORE_ON Enable sensitivity to PD_CPU0CORE [1:1] read-write enable Enable sensitivity to PD_CPU0CORE 1 disable Disable sensitivity to PD_CPU0CORE 0 S_PD_CPU1CORE_ON Enable sensitivity to PD_CPU1CORE [2:2] read-write enable Enable sensitivity to PD_CPU1CORE 1 disable Disable sensitivity to PD_CPU1CORE 0 S_PD_SRAM0_ON Tied LOW [3:3] read-only Low Ignores PD_SRAM0 state 0 S_PD_SRAM1_ON Tied LOW [4:4] read-only Low Ignores PD_SRAM1 state 0 S_PD_SRAM2_ON Tied LOW [5:5] read-only Low Ignores PD_SRAM2 state 0 S_PD_SRAM3_ON Enable sensitivity to PD_SRAM3 [6:6] read-write enable Enable sensitivity to PD_SRAM3 1 disable Disable sensitivity to PD_SRAM3 0 S_PD_CRYPTO_ON Tied LOW [12:12] read-only Low Ignores PD_CRYPTO 0 S_PD_EXP0_IN Enable PDEXPIN[0] signal Sensitivity [16:16] read-write enable Enable PDEXPIN[0] signal Sensitivity 1 disable Disable PDEXPIN[0] signal Sensitivity 0 S_PD_EXP1_IN Enable PDEXPIN[1] signal Sensitivity [17:17] read-write enable Enable PDEXPIN[1] signal Sensitivity 1 disable Disable PDEXPIN[1] signal Sensitivity 0 S_PD_EXP2_IN Enable PDEXPIN[2] signal Sensitivity [18:18] read-write enable Enable PDEXPIN[2] signal Sensitivity 1 disable Disable PDEXPIN[2] signal Sensitivity 0 S_PD_EXP3_IN Enable PDEXPIN[3] signal Sensitivity [19:19] read-write enable Enable PDEXPIN[3] signal Sensitivity 1 disable Disable PDEXPIN[3] signal Sensitivity 0 PIDR4 Peripheral ID 4 0xFD0 read-only 0x00000004 PIDR0 Peripheral ID 0 0xFE0 read-only 0x00000054 PIDR1 Peripheral ID 1 0xFE4 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 read-only 0x0000001B PIDR3 Peripheral ID 3 0xFEC read-only 0x00000000 CIDR0 Component ID 0 0xFF0 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 read-only 0x00000005 CIDR3 Component ID 3 0xFFC read-only 0x000000B1 SAU 1.0 Security Attribution Unit SAU 0xE000EDD0 32 read-write 0 0x20 registers CTRL Control Register 0x00 ENABLE Enable [0:0] Disable SAU is disabled 0 Enable SAU is enabled 1 ALLNS Security attribution if SAU disabled [1:1] Secure Memory is marked as secure 0 Non_Secure Memory is marked as non-secure 1 TYPE Type Register 0x04 read-only SREGION Number of implemented SAU regions [7:0] RNR Region Number Register 0x08 REGION Currently selected SAU region [7:0] SAU_Region_0 Select SAU Region 0 0 SAU_Region_1 Select SAU Region 1 1 SAU_Region_2 Select SAU Region 2 2 SAU_Region_3 Select SAU Region 3 3 RBAR Region Base Address Register 0x0C BADDR Base Address [31:5] RLAR Region Limit Address Register 0x10 LADDR Limit Address [31:5] NSC Non-Secure Callable [1:1] ENABLE SAU Region enabled [0:0] SFSR Secure Fault Status Register 0x14 LSERR Lazy state error flag [7:7] SFARVALID Secure fault address valid [6:6] LSPERR Lazy state preservation error flag [5:5] INVTRAN Invalid transition flag [4:4] AUVIOL Attribution unit violation flag [3:3] INVER Invalid exception return flag [2:2] INVIS Invalid integrity signature flag [1:1] INVEP Invalid entry pointd [0:0] TIMER0 1.0 Timer 0 Timer 0x40000000 32 read-write 0 0x10 registers TIMER0 Timer 0 3 CTRL Control Register 0x000 ENABLE Enable [0:0] Disable Timer is disabled 0 Enable Timer is enabled 1 EXTIN External Input as Enable [1:1] Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 EXTCLK External Clock Enable [2:2] Disable External Clock is disabled 0 Enable External Clock is enabled 1 INTEN Interrupt Enable [3:3] Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 VALUE Current Timer Counter Value 0x004 RELOAD Counter Reload Value 0x008 INTSTATUS Timer Interrupt status register 0x00C read-only INTCLEAR Timer Interrupt clear register INTSTATUS 0x00C write-only oneToClear DUALTIMER 1.0 Dual Timer Timer 0x40002000 32 read-write 0 0x3C registers DUALTIMER Dual Timer 5 TIMER1LOAD Timer 1 Load Register 0x000 0x00000000 TIMER1VALUE Timer 1 Value Register 0x004 0xFFFFFFFF read-only TIMER1CONTROL Timer 1 Control Register 0x008 0x20 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0x00C 0x00000000 write-only INT Interrupt 0 1 oneToClear TIMER1RIS Timer 1 Raw Interrupt Status Register 0x010 0x0 read-only RIS Raw Timer Interrupt 0 1 TIMER1MIS Timer 1 Mask Interrupt Status Register 0x014 0x0 read-only MIS Masked Timer Interrupt 0 1 TIMER1BGLOAD Timer 1 Background Load Register 0x018 0x00000000 TIMER2LOAD Timer 2 Load Register 0x020 0x00000000 TIMER2VALUE Timer 2 Value Register 0x024 0xFFFFFFFF read-only TIMER2CONTROL Timer 2 Control Register 0x028 0x20 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x02C 0x00000000 write-only INT Interrupt 0 1 oneToClear TIMER2RIS Timer 2 Raw Interrupt Status Register 0x030 0x0 read-only RIS Raw Timer Interrupt 0 1 TIMER2MIS Timer 2 Mask Interrupt Status Register 0x034 0x0 read-only MIS Masked Timer Interrupt 0 1 TIMER2BGLOAD Timer 2 Background Load Register 0x038 0x00000000 GPTIMER 1.0 General-Purpose Timer Timer 0x4010C000 32 read-write 0 0x20 registers GPTIMERINTR General-Purpose Timer interrupt 33 GPTIMERINT0 General-Purpose Timer (Comparator 0) 73 GPTIMERINT1 General-Purpose Timer (Comparator 1) 72 GPTRESET Control Reset Register 0x0000 0x00000000 read-only GPTRESET CPU0 interrupt status [1:0] GPTINTM Masked interrupt status register 0x0004 0x00000000 read-write GPTINTM Current masked status of the interrupt [1:0] GPTINTC Interrupt clear register 0x0008 0x00000000 read-write GPTINTC Writing 0b1 disables the ALARM[n] interrupt [1:0] GPTALARM0 ALARM0 data value register 0x0010 0x00000000 read-write GPTALARM0_DATA Value that triggers the ALARM0 interrupt when the counter reaches that value [31:0] GPTALARM1 ALARM1 data value register 0x0014 0x00000000 read-write GPTALARM1_DATA Value that triggers the ALARM1 interrupt when the counter reaches that value [31:0] GPTINTR Raw interrupt status register 0x0018 0x00000000 read-only GPTINTR Raw interrupt state, before masking of GPTINTR interrupt [2:0] GPTCOUNTER Counter data value register 0x001C 0x00000000 read-only GPTCOUNTER Current value of 32-bit Timer Counter [31:0] TIMER0_Secure Timer 0 (Secure) Timer (Secure) 0x50000000 DUALTIMER_Secure Dual Timer (Secure) Timer (Secure) 0x50002000 GPTIMER_Secure General-Purpose Timer (Secure) Timer (Secure) 0x5010C000 GPIO0 1.0 General-purpose I/O 0 GPIO 0x41000000 32 read-write 0 0x3C registers GPIO0 GPIO 0 combined 68 DATA Data Register 0x000 DATAOUT Data Output Register 0x004 OUTENSET Ouptut enable set Register 0x010 OUTENCLR Ouptut enable clear Register 0x014 ALTFUNCSET Alternate function set Register 0x018 ALTFUNCCLR Alternate function clear Register 0x01C INTENSET Interrupt enable set Register 0x020 INTENCLR Interrupt enable clear Register 0x024 INTTYPESET Interrupt type set Register 0x028 INTTYPECLR Interrupt type clear Register 0x02C INTPOLSET Polarity-level, edge interrupt configuration set Register 0x030 INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x034 INTSTATUS Interrupt Status Register 0x038 read-only INTCLEAR Interrupt CLEAR Register INTSTATUS 0x038 write-only oneToClear GPIO0_Secure General-purpose I/O 0 (Secure) 0x51000000 GPIO (Secure) UART0 1.0 UART 0 UART 0x40105000 32 read-write 0 0x4C registers UARTRXINTR0 UART0 receive FIFO interrupt 39 UARTTXINTR0 UART0 transmit FIFO interrupt 40 UARTRTINTR0 UART0 receive timeout interrupt 41 UARTMSINTR0 UART0 modem status interrupt 42 UARTEINTR0 UART0 error interrupt 43 UARTINTR0 UART0 interrupt 44 UARTDR Data register 0x000 read-write Data Receive/Transmit data 0 8 FE Framing error: Indicates the received character did not had a valid stop bit 8 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 9 1 BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 10 1 OE Overrun error: Indicates if data is received and the receive FIFO is already full. 11 1 UARTRSR_UARTECR Receive status register/error clear register 0x004 0x00000000 read-write FE Framing error: Indicates the received character did not had a valid stop bit 0 1 PE Parity error: Indicates that the parity of the received data character does not match the parity selected 1 1 BE Break error: Indicates that the received data input was held LOW for longer than a full-word transmission time 2 1 OE Overrunerror: Indicates if data is received and the receive FIFO is already full. 3 1 UARTRFR Flag register 0x018 read-only CTS Clear to send 0 1 DSR Data set ready 1 1 DCD Data carrier detect 2 1 BUSY UART busy 3 1 RXFE Receive FIFO empty 4 1 TXFF Transmit FIFO full 5 1 RXFF Receive FIFO full 6 1 TXFE Transmit FIFO empty 7 1 RI Ring indicator 8 1 UARTILPR IrDA low-power counter register 0x020 0x00000000 read-write ILPDVSR 8-bit low-power divisor value 0 8 UARTIBRD Integer baud rate register 0x024 0x00000000 read-write BAUD_DIVINT The integer baud rate divisor 0 16 UARTFBRD Fractional baud rate register 0x028 0x00000000 read-write BAUD_DIVINT The integer baud rate divisor 0 6 UARTLCR_H Line control register 0x02C 0x00000000 read-write BRK Send break 0 1 PEN Parity enable 1 1 EPS Even parity select 2 1 STP2 Two stop bits select 3 1 FEN Enable FIFOs 4 1 WLEN Word length 5 2 SPS Stick parity select 7 1 UARTCR Control register 0x030 0x00000300 read-write UARTEN UART enable 0 1 Disable UART is disabled 0 Enable UART is enabled 1 SIREN SIR enable 1 1 Disable SIR is disabled 0 Enable SIR is enabled 1 SIRLP IrDA SIR low power mode 2 1 Disable SIR low power mode is disabled 0 Enable SIR low power mode is enabled 1 LBE Loop back enable 7 1 Disable Loop back mode is disabled 0 Enable Loop back mode is enabled 1 TXE Transmit enable 8 1 Disable Transmission is disabled. 0 Enable Transmission is enabled. 1 RXE Receive enable 9 1 Disable Reception is disabled 0 Enable Reception is enabled 1 DTR Data transmit ready 10 1 RTS Request to send 11 1 Out1 Complement of the UART Out1 12 1 Out2 Complement of the UART Out2 13 1 RTSEn RTS hardware flow control enable 14 1 Disable RTS hardware flow control is disabled 0 Enable RTS hardware flow control is enabled 1 CTSEn CTS hardware flow control enable 15 1 Disable CTS hardware flow control is disabled 0 Enable CTS hardware flow control is enabled 1 UARTIFLS Interrupt FIFO level select register 0x034 0x00000012 read-write TXIFLSEL Transmit interrupt FIFO level select 0 3 1/8 full Transmit FIFO becomes less than or equal to 1/8 full 0 1/4 full Transmit FIFO becomes less than or equal to 1/4 full 1 1/2 full Transmit FIFO becomes less than or equal to 1/2 full 2 3/4 full Transmit FIFO becomes less than or equal to 3/4 full 3 7/8 full Transmit FIFO becomes less than or equal to 7/8 full 4 RXIFLSEL Receive interrupt FIFO level select 3 3 1/8 full Receive FIFO becomes greater than or equal to 1/8 full 0 1/4 full Receive FIFO becomes greater than or equal to 1/4 full 1 1/2 full Receive FIFO becomes greater than or equal to 1/2 full 2 3/4 full Receive FIFO becomes greater than or equal to 3/4 full 3 7/8 full Receive FIFO becomes greater than or equal to 7/8 full 4 UARTIMSC Interrupt mask set/clear register 0x038 0x00000000 read-write RIMIM nUARTRI modem interrupt mask 0 1 Clear Clears the mask 0 Set Sets the mask 1 CTSMIM nUARTCTS modem interrupt mask. 1 1 Clear Clears the mask 0 Set Sets the mask 1 DCDMIM nUARTDCD modem interrupt mask 2 1 Clear Clears the mask 0 Set Sets the mask 1 DSRMIM nUARTDSR modem interrupt mask 3 1 Clear Clears the mask 0 Set Sets the mask 1 RXIM Receive interrupt mask 4 1 Clear Clears the mask 0 Set Sets the mask 1 TXIM Transmit interrupt mask 5 1 Clear Clears the mask 0 Set Sets the mask 1 RTIM Receive timeout interrupt mask 6 1 Clear Clears the mask 0 Set Sets the mask 1 FEIM Framing error interrupt mask 7 1 Clear Clears the mask 0 Set Sets the mask 1 PEIM Parity error interrupt mask 8 1 Clear Clears the mask 0 Set Sets the mask 1 BEIM Break error interrupt mask 9 1 Clear Clears the mask 0 Set Sets the mask 1 OEIM Overrun error interrupt mask 10 1 Clear Clears the mask 0 Set Sets the mask 1 UARTRIS Raw interrupt status register 0x03C read-only RIRMIS nUARTRI modem interrupt status 0 1 CTSRMIS nUARTCTS modem interrupt status. 1 1 DCDRMIS nUARTDCD modem interrupt status 2 1 DSRRMIS nUARTDSR modem interrupt status 3 1 RXRIS Receive interrupt status 4 1 TXRIS Transmit interrupt status 5 1 RTRIS Receive timeout interrupt status 6 1 FERIS Framing error interrupt status 7 1 PERIS Parity error interrupt status 8 1 BERIS Break error interrupt status 9 1 OERIS Overrun error interrupt status 10 1 UARTMIS Masked interrupt status register 0x040 read-only RIMMIS nUARTRI modem masked interrupt status 0 1 CTSMMIS nUARTCTS modem masked interrupt status. 1 1 DCDMMIS nUARTDCD modem masked interrupt status 2 1 DSRMMIS nUARTDSR modem masked interrupt status 3 1 RXMIS Receive masked interrupt status 4 1 TXMIS Transmit masked interrupt status 5 1 RTMIS Receive timeout masked interrupt status 6 1 FEMIS Framing error masked interrupt status 7 1 PEMIS Parity error masked interrupt status 8 1 BEMIS Break error masked interrupt status 9 1 OEMIS Overrun error masked interrupt status 10 1 UARTICR Interrupt clear register 0x044 write-only RIMIC nUARTRI modem interrupt clear, write 1 to clear, write 0 has no effect 0 1 CTSMIC nUARTCTS modem interrupt clear, write 1 to clear, write 0 has no effect 1 1 DCDMIC nUARTDCD modem interrupt clear, write 1 to clear, write 0 has no effect 2 1 DSRIC nUARTDSR modem interrupt clear, write 1 to clear, write 0 has no effect 3 1 RXIC Receive interrupt clear, write 1 to clear, write 0 has no effect 4 1 TXIC Transmit interrupt clear, write 1 to clear, write 0 has no effect 5 1 RTIC Receive timeout interrupt clear, write 1 to clear, write 0 has no effect 6 1 FEIC Framing error interrupt clear, write 1 to clear, write 0 has no effect 7 1 PEIC Parity error interrupt clear, write 1 to clear, write 0 has no effect 8 1 BEIC Break error interrupt clear, write 1 to clear, write 0 has no effect 9 1 OEIC Overrun error interrupt clear, write 1 to clear, write 0 has no effect 10 1 UARTDMACR DMA control register 0x048 0x00000000 read-write RXDMAE Receive DMA enable 0 1 Disable Receive DMA is disabled 0 Enable Receive DMA is enabled 1 TXDMAE Transmit DMA enable 1 1 Disable Transmit DMA is disabled 0 Enable Transmit DMA is enabled 1 DMAONERR DMA on error 2 1 Disable DMA receive request outputs are enabled when the UART error interrupt is asserted 0 Enable DMA receive request outputs are disabled when the UART error interrupt is asserted 1 UART0_Secure UART 0 (Secure) 0x50105000 UART (Secure) WATCHDOG Non-secure Watchdog Timer WATCHDOG 0x40081000 0 0xC04 registers NONSEC_WATCHDOG_IRQ Non-Secure Watchdog Interrupt 1 WDOGLOAD Watchdog Load Register 0x000 0xFFFFFFFF WDOGVALUE Watchdog Value Register 0x004 0xFFFFFFFF read-only WDOGCONTROL Watchdog Control Register 0x008 0x0 INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0x00C 0x00000000 write-only INT Interrupt 0 1 oneToClear WDOGRIS Watchdog Raw Interrupt Status Register 0x010 0x0 read-only RIS Raw watchdog Interrupt 0 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x014 0x0 read-only MIS Masked Watchdog Interrupt 0 1 WDOGLOCK Watchdog Lock Register 0xC00 0x00000000 Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 iCache 1.0 Cache Cache 0x50010000 32 read-write 0 0x1000 registers ICHWPARAMS Hardware Parameter Register 0x00 read-only CSIZE Cache size: Defines the size of the instruction cache 0 4 read-only STATS Presence of Statistic Functionality 4 1 read-only DMA Presence of DMA Engine 5 1 read-only Support The Instruction cache supports pre-fetch and locking 1 Unsupport The Instruction cache does not support pre-fetch and locking 0 INVMAT Indicates whether invalidate cache line on write match is enabled 6 1 read-only Enabled Indicates Invalidate Cache Line on Write Match is enabled 1 COFFSIZE Cacheable Block Size 12 4 read-only COFFSET Cacheable Offset Address 16 16 read-only ICCTRL Instruction Cache Control Register 0x04 0x0 read-write CACHEEN Enable Cache 0 1 read-write Enabled Caching is enabled 1 Disabled All accesses bypass the cache 0 FINV Full Cache Invalidate 2 1 write-only Invalidate Triggers the instruction cache to start invalidating all cache lines 1 STATEN Enable Statistic function 3 1 read-write Enabled Cache statistic counters are enabled 1 Disabled Cache statistic counters are disabled 0 STATC Clear Statistic values 4 1 write-only Clear Triggers the instruction cache to start clear all cache statistic counters 1 HALLOC Enable Handler Allocation 5 1 read-write LOW All incoming handler code fetches are not allocated a cache line if a miss occurs 0 HIGH Handler code access is treated like any other code access arriving at its interface 1 ICIRQSTAT Interrupt Request Status Register 0x100 0x00000000 read-only IC_STATUS Invalidate Complete IRQ Status 0 1 read-only Completed Indicates that a cache invalidation process has been completed 1 CDC_STATUS Cache Disable Complete IRQ Status 1 1 read-only Completed Indicates that a request to disable the cache has been completed 1 CEC_STATUS Cache Enable Complete IRQ Status 2 1 read-only Completed Indicates that a request to enable the cache has been completed 1 CFE_STATUS Cache Fill Error IRQ Status 3 1 read-only Err_Occurred Indicates that a bus error occurred while filling a cache line 1 SV_STATUS Security violation IRQ Status 4 1 read-only SS_STATUS Statistics Saturated Status 5 1 read-only Saturated Indicates that the internal statistic counters have saturated 1 ICIRQSCLR Interrupt Status Clear register 0x104 0x0 write-only IC_CLR Invalidate Complete IRQ Status Clear 0 1 write-only Clear Clear the Invalidate Complete IRQ Status 1 CDC_CLR Cache Disable Complete IRQ Status Clear 1 1 write-only Clear Clear Cache Disable Complete IRQ Status 1 CEC_CLR Cache Enable Complete IRQ Status Clear 2 1 write-only Clear Clear the Cache Enable Complete IRQ Status 1 CFE_CLR Cache Fill Error IRQ Status Clear 3 1 write-only Clear Clear the Cache Fill Error IRQ Status 1 SV_CLR Security violation IRQ Status Clear 4 1 write-only Clear Clear the Security violation IRQ Status 1 SS_CLR Statistics Saturated Status Clear 5 1 write-only Clear Clear the Statistics Saturated Status 1 ICIRQEN Interrupt Enable register 0x108 0x0 read-write IC_EN Invalidate Complete IRQ Enable 0 1 read-write Enabled Enable the Invalidate Complete IRQ 1 Disabled Disable the Invalidate Complete IRQ 0 CDC_EN Cache Disable Complete IRQ Enable 1 1 read-write Enabled Enable the Cache Disable Complete IRQ 1 Disabled Disable the Cache Disable Complete IRQ 0 CEC_EN Cache Enable Complete IRQ Enable 2 1 read-write Enabled Enable the Cache Enable Complete IRQ 1 Disabled Disable the Cache Enable Complete IRQ 0 CFE_EN Cache Fill Error IRQ Enable 3 1 read-write Enabled Enable the Cache Fill Error IRQ 1 Disabled Disable the Cache Fill Error IRQ 0 SV_EN Security violation IRQ Enable 4 1 read-write Enabled Enable the Security violation IRQ 1 Disabled Disable the Security violation IRQ 0 SS_EN Statistics Saturated Enable 5 1 read-write Enabled Enable the Statistics Saturated 1 Disabled Disable the Statistics Saturated 0 ICDBGFILLERR Address where the latest fill error was seen 0x10C 0x0 read-only ICSH Instruction Cache Statistic Hit Count register 0x300 0x0 read-only ICSM Instruction Cache Statistic Miss Count register 0x304 0x0 read-only ICSUC Instruction Cache Statistic Uncached Count register 0x308 0x0 read-only PIDR4 Product ID Register 4 0xFD0 32 read-only 0x04 PIDR5 Product ID Register 5 0xFD4 32 read-only 0x0 PIDR6 Product ID Register 6 0xFD8 32 read-only 0x0 PIDR7 Product ID Register 7 0xFDC 32 read-only 0x0 PIDR0 Product ID Register 0 0xFE0 32 read-only 0x57 PIDR1 Product ID Register 1 0xFE4 32 read-only 0xB8 PIDR2 Product ID Register 2 0xFE8 32 read-only 0x0B PIDR3 Product ID Register 3 0xFEC 32 read-only 0x0 CIDR0 Component ID Register 0 0xFF0 32 read-only 0x0D CIDR1 Component ID Register 1 0xFF4 32 read-only 0xF0 CIDR2 Component ID Register 2 0xFF8 32 read-only 0x05 CIDR3 Component ID Register 3 0xFFC 32 read-only 0xB1 PWM PWM_IP6512 PWM 0x40107000 0 0x020 registers PWMINT0 PWM0 interrupt 70 PWMINT1 PWM1 interrupt 74 PWMINT2 PWM2 interrupt 75 PWMCR PWM Control Register 0x000 0x0 read-write OUTPUT_SET Start stop bit for the pwm_output 0 1 read-write Enabled Generate programmed waveform on pwm_output 1 Disabled Set pwm_output continually high 0 PWMPR PWM Period Register. Number of system clock cycles indicating the period of PWM cycle.The minimum and maximum values have special significance. 0x0: pwm_output continually high 0xFFFFFFFF: pwm_output continually low 0x004 0x0 read-write PWMHR PWM High Iime Register. This register contains the number of system clock cycles for during which the pwm_output should be kept high in a PWM cycle 0x008 0x0 read-write PWMEI PWM Enable Interrupt Register 0x010 write-only Enable_BIT Determines whether the write accesses the Interrupt Enable register 0 1 write-only Enabled Enable the Interrupt generation 1 PWMDI PWM Disable Interrupt Register 0x014 write-only Disable_BIT Determines whether the write accesses the Interrupt Disable register 0 1 write-only Disabled Disable the Interrupt generation 1 PWMRI PWM Read Intr Enable Register.Reading from this address accesses the current state of the interrupt control registers 0x018 0x0 read-only Enable_BIT Check whether the Interrupt is Enabled 0 1 read-only Enabled Interrupt is Enabled 1 PWMIS PWM Read Interrupt Status Register 0x01c 0x0 read-only Status Reading from this address returns the current state of the PWM Interrupt output, and then sets the bit low 0 1 read-only Active Interrupt is active 1 Not active Interrupt is not active 0 WATCHDOG_Secure Watchdog (Secure) WATCHDOG (Secure) 0x50081000 S32KWATCHDOG S32K Watchdog (Secure) WATCHDOG (Secure) 0x5002E000 SCC Serial Communication Controller SCC 0x5010B000 0 0x1000 registers CLK_CTRL_SEL 0x000 32 read-write 0x00000072 sel_premux_clk 0: 32k 1: FASTCLK [0:0] sel_dapswmux_clk 0: PRE_MUX_CLK 1: TCK [1:1] sel_mainmux_clk 0: PLL0_CLK 1: PRE_MUX_CLK [2:2] sel_refmux_clk 0: PRE_MUX_CLK 1: PRE_PLL_CLK [3:3] sel_rm38kmux_clk 0: REF_MUX_CLK 1: RM38K [4:4] sel_sccmux_clk 0: SCCCLK 1: PRE_MUX_CLK [5:5] sel_rm38p4_premux_clk 0: SYSSYSSUGCLK 1: NRM138P4 [6:6] ctrl_sel_test_mux_clk ctrl_sel_test_mux_clk [11:7] CLK_PLL_PREDIV_CTRL 0x004 32 read-write 0x0 prediv_ctrl prediv_ctrl [9:0] CLK_POSTDIV_CTRL_FLASH 0x00C 32 read-write 0x1 postdiv_ctrl_flash_div postdiv_ctrl_flash_div [7:0] CLK_POSTDIV_CTRL_QSPI 0x010 32 read-write 0x1 postdiv_ctrl_qspi_div postdiv_ctrl_qspi_div [7:0] CLK_POSTDIV_CTRL_RTC 0x014 32 read-write 0xFFFFFFFF postdiv_ctrl_rtc_div postdiv_ctrl_rtc_div [31:0] CLK_POSTDIV_CTRL_SD 0x018 32 read-write 0x1 postdiv_ctrl_sd_div postdiv_ctrl_sd_div [7:0] CLK_POSTDIV_CTRL_TEST 0x01C 32 read-write 0xA postdiv_ctrl_test_div postdiv_ctrl_test_div [7:0] CTRL_BYPASS_DIV 0x020 32 read-write 0x1 bypass_div_pll_div_prediv_clk 0: Not bypass 1: bypass [0:0] bypass_qspi_div_clk 0: Not bypass 1: bypass [3:3] bypass_rtc_div_clk 0: Not bypass 1: bypass [4:4] bypass_sd_div_clk 0: Not bypass 1: bypass [5:5] bypass_test_div_clk 0: Not bypass 1: bypass [6:6] PLL_CTRL_PLL0_CLK 0x024 32 read-write 0x0 pd_pll0 Power down PLL0 [0:0] pd_foutpostdiv1pd Power down FOUTPOSTDIV1PD: [1:1] pd_foutpostdiv2pd Power down FOUTPOSTDIV2PD [2:2] pd_foutvcopd Power down FOUTVCOPD [3:3] bypass_pll0 Bypass PLL0 [4:4] PLL_POSTDIV_CTRL_PLL0_CLK 0x028 32 read-write 0x1 pll_postdiv_ctrl_pll0_clk pll_postdiv_ctrl_pll0_clk [3:0] PLL_CTRL_MULT_PLL0_CLK 0x02C 32 read-write 0x1388 pll_mult_ctrl_pll0_clk pll_mult_ctrl_pll0_clk [13:0] CLK_CTRL_ENABLE 0x030 32 read-write 0xFFFF ctrl_enable_1hz 0: Disable; 1: Enable [0:0] ctrl_enable_dapswclk 0: Disable; 1: Enable [1:1] ctrl_enable_gpiohclk 0: Disable; 1: Enable [2:2] ctrl_enable_i2sclk0 0: Disable; 1: Enable [3:3] ctrl_enable_i2sclk1 0: Disable; 1: Enable [4:4] ctrl_enable_i2sclk2 0: Disable; 1: Enable [5:5] ctrl_enable_mainclk 0: Disable; 1: Enable [8:8] ctrl_enable_qspi_phy_clk 0: Disable; 1: Enable [9:9] ctrl_enable_refclk 0: Disable; 1: Enable [10:10] ctrl_enable_rm38kclk 0: Disable; 1: Enable [11:11] ctrl_enable_sccclk 0: Disable; 1: Enable [12:12] ctrl_enable_sdphyclk 0: Disable; 1: Enable [13:13] ctrl_enable_testclk 0: Disable; 1: Enable [15:15] CLK_STATUS 0x034 32 read-only 0x3 status_out_clk_mainclk_ready Clock ready (active) [0:0] status_lock_signal_pll0_clk PLL Lock Status [1:1] RESET_CTRL 0x040 32 read-write 0xFFFFFFFF GPTIMER_RESET Reset Active low [1:1] I2C0_RESET Reset Active low [2:2] I2C1_RESET Reset Active low [3:3] I2S_RESET Reset Active low [4:4] SPI_RESET Reset Active low [5:5] QSPI_RESET Reset Active low [6:6] UART0_RESET Reset Active low [7:7] UART1_RESET Reset Active low [8:8] GPIO_RESET Reset Active low [9:9] PVT_RESET Reset Active low [10:10] PWM0_RESET Reset Active low [11:11] PWM1_RESET Reset Active low [12:12] PWM2_RESET Reset Active low [13:13] RTC_RESET Reset Active low [14:14] DBG_CTRL 0x048 32 read-write 0x1F SSE_200_DBGENIN 0: Not enable 1: Enable [0:0] SSE_200_NIDENIN 0: Not enable 1: Enable [1:1] SSE_200_SPIDENIN 0: Not enable 1: Enable [2:2] SSE_200_SPNIDENIN 0: Not enable 1: Enable [3:3] TODBGENSEL0 0: Enable 1: Mask or bypass [7:7] TODBGENSEL1 0: Enable 1: Mask or bypass [8:8] DBG_DCU_FORCE SSE-200 debug ports control [31:30] SRAM_CTRL 0x04C 32 read-write 0x48100000 CODE_SRAMx_PGEN SRAM cell power gate enable [15:0] INTR_CTRL 0x050 32 read-write 0x0 QSPI_MPC_CFG_INIT_VALUE 0: Secure mode 1: Non-secure mode [3:3] SRAM_MPC_CFG_INIT_VALUE 0: Secure mode 1: Non-secure mode [5:5] AZ_MPC_CFG_INIT_VALUE 0: Secure mode 1: Non-secure mode [6:6] CLK_TEST_CTRL 0x054 32 read-write 0x0 CLK_TEST_SEL Select TESTMUX input [4:0] CLK_TEST_EN 0: Not enable 1: Enable [5:5] CLK_MAIN_FORCE_RDY CLK_MAIN_FORCE_RDY [6:6] CPU0_VTOR 0x058 32 read-write 0x10000000 CPU0_VTOR_SECURE Reset vector for CPU0 secure mode [31:7] CPU1_VTOR 0x060 32 read-write 0x1A400000 CPU1_VTOR_SECURE Reset vector for CPU1 secure mode [31:7] AZ_CPU_VTOR 0x064 32 read-write 0x00A03800 AZ_ROM_REMAP Remap vector for Alcatraz ROM address space. [7:0] AZ_CODE_REMAP Remap vector for Alcatraz Code address space [15:8] AZ_SYS_REMAP Remap vector for Alcatraz System address space [23:16] IOMUX_MAIN_INSEL_0 0x068 32 read-write 0xFFFFFFFF iomux_main_insel_0 0: Select ATF1 1: Select Main Function [31:0] IOMUX_MAIN_INSEL_1 0x06C 32 read-write 0xFFFFFFFF iomux_main_insel_1 0: Select ATF1 1: Select Main Function [5:0] IOMUX_MAIN_OUTSEL_0 0x070 32 read-write 0xFFFFFFFF iomux_main_outsel_0 0: Select ATF1 1: Select Main Function [31:0] IOMUX_MAIN_OUTSEL_1 0x074 32 read-write 0xFFFFFFFF iomux_main_outsel_1 0: Select ATF1 1: Select Main Function [5:0] IOMUX_MAIN_OENSEL_0 0x078 32 read-write 0xFFFFFFFF iomux_main_oensel_0 0: Select ATF1 1: Select Main Function [31:0] IOMUX_MAIN_OENSEL_1 0x07C 32 read-write 0xFFFFFFFF iomux_main_oensel_1 0: Select ATF1 1: Select Main Function [5:0] IOMUX_MAIN_DEFAULT_IN_0 0x080 32 read-write 0x0 iomux_main_default_in_0 0: Default to 0 1: Default to 1 [31:0] IOMUX_MAIN_DEFAULT_IN_1 0x084 32 read-write 0x0 iomux_main_default_in_1 0: Default to 0 1: Default to 1 [5:0] IOMUX_ALTF1_INSEL_0 0x088 32 read-write 0x0 iomux_altf1_insel_0 0: Select ATF2 1: Select ATF1 [31:0] IOMUX_ALTF1_INSEL_1 0x08C 32 read-write 0x0 iomux_altf1_insel_1 0: Select ATF2 1: Select ATF1 [5:0] IOMUX_ALTF1_OUTSEL_0 0x090 32 read-write 0xFFFFFFFF iomux_altf1_outsel_0 0: Select ATF2 1: Select ATF1 [31:0] IOMUX_ALTF1_OUTSEL_1 0x094 32 read-write 0xFFFFFFFF iomux_altf1_outsel_1 0: Select ATF2 1: Select ATF1 [5:0] IOMUX_ALTF1_OENSEL_0 0x098 32 read-write 0xFFFFFFFF iomux_altf1_oensel_0 0: Select ATF2 1: Select ATF1 [31:0] IOMUX_ALTF1_OENSEL_1 0x09C 32 read-write 0xFFFFFFFF iomux_altf1_oensel_1 0: Select ATF2 1: Select ATF1 [5:0] IOMUX_ALTF1_DEFAULT_IN_0 0x0A0 32 read-write 0x0 iomux_altf1_default_in_0 0: Default to 0 1: Default to 1 [31:0] IOMUX_ALTF1_DEFAULT_IN_1 0x0A4 32 read-write 0x0 iomux_altf1_default_in_1 0: Default to 0 1: Default to 1 [5:0] IOMUX_ALTF2_INSEL_0 0x0A8 32 read-write 0x0 iomux_altf2_insel_0 0: Select ATF3 1: Select ATF2 [31:0] IOMUX_ALTF2_INSEL_1 0x0AC 32 read-write 0x0 iomux_altf2_insel_1 0: Select ATF3 1: Select ATF2 [5:0] IOMUX_ALTF2_OUTSEL_0 0x0B0 32 read-write 0xFFFFFFFF iomux_altf2_outsel_0 0: Select ATF3 1: Select ATF2 [31:0] IOMUX_ALTF2_OUTSEL_1 0x0B4 32 read-write 0xFFFFFFFF iomux_altf2_outsel_1 0: Select ATF3 1: Select ATF2 [5:0] IOMUX_ALTF2_OENSEL_0 0x0B8 32 read-write 0xFFFFFFFF iomux_altf2_oensel_0 0: Select ATF3 1: Select ATF2 [31:0] IOMUX_ALTF2_OENSEL_1 0x0BC 32 read-write 0xFFFFFFFF iomux_altf2_oensel_1 0: Select ATF3 1: Select ATF2 [5:0] IOMUX_ALTF2_DEFAULT_IN_0 0x0C0 32 read-write 0x0 iomux_altf2_default_in_0 0: Default to 0 1: Default to 1 [31:0] IOMUX_ALTF2_DEFAULT_IN_1 0x0C4 32 read-write 0x0 iomux_altf2_default_in_1 0: Default to 0 1: Default to 1 [5:0] IOPAD_DSO_0 0x0E8 32 read-write 0xFFF00000 drive_strength0 Least significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0 [31:0] IOPAD_DSO_1 0x0EC 32 read-write 0xFFFFFFFF drive_strength_0 Least significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32 [5:0] IOPAD_DS1_0 0x0F0 32 read-write 0xFFFFFFFF drive_strength1 Most significant bits of the two-bit values that define drive strengths of test chip I/O PA31-PA0 [31:0] IOPAD_DS1_1 0x0F4 32 read-write 0xFFFFFFFF drive_strength_1 Most significant bits of the two-bit values that define drive strengths of test chip I/O PA37-PA32 [5:0] IOPAD_PE_0 0x0F8 32 read-write 0xFFFFFFFF pull_enable Enables pull resistors of test chip I/O PA31-PA0 [31:0] IOPAD_PE_1 0x0FC 32 read-write 0xFFFFFFFF pull_enable Enables pull resistors of test chip I/O PA37-PA32 [5:0] IOPAD_PS_0 0x100 32 read-write 0xFFFFFFFF pull_select Enables pull resistors of test chip I/O PA31-PA0 [31:0] IOPAD_PS_1 0x104 32 read-write 0xFFFFFFFF pull_select Enables pull resistors of test chip I/O PA37-PA32 [5:0] IOPAD_SR_0 0x108 32 read-write 0xFFFFFFFF slew_rate Selects the slew rate of test chip I/O PA31-PA0 [31:0] IOPAD_SR_1 0x10C 32 read-write 0xFFFFFFFF slew_rate Selects the slew rate of test chip I/O PA37-PA32 [5:0] IOPAD_IS_0 0x110 32 read-write 0xFFFFFFFF input_select Selects input mode on test chip I/O PA31-PA0 [31:0] IOPAD_IS_1 0x114 32 read-write 0xFFFFFFFF input_select Selects input mode on test chip I/O PA37-PA32 [5:0] PVT_CTRL 0x118 32 read-write 0x0 TSTSENNUM Select PVT sensor to write to and read from [4:0] SPARE0 0x130 32 read-write 0x0 spare0 Spare read-write register for software [31:0] STATIC_CONF_SIG1 0x13C 32 read-write 0x0 TISBYPASSIN Cross Trigger Interface synchronous bypass on CTITRIGIN [7:0] TISBYPASSACK Cross Trigger Interface synchronous bypass on CTITRIGOUTACK [11:8] TIHSBYPASS Cross Trigger Interface handshake bypass on CTITRIGOUT [15:12] TINIDENSEL NIDEN mask on CTITRIGINT [23:16] TODBGENSEL DBGEN mask on CTITRIGOUT [27:24] FLASH_DIN_0 0x1A0 32 read-write 0x0 scc_flash_din0 eFlash 0 and eFlash 1 data input[31:0] [31:0] FLASH_DIN_1 0x1A4 32 read-write 0x0 scc_flash_din1 eFlash 0 and eFlash 1 data input{63:32] [31:0] FLASH_DIN_2 0x1A8 32 read-write 0x0 scc_flash_din2 eFlash 0 and eFlash 1 data input[95:64] [31:0] FLASH_DIN_3 0x1AC 32 read-write 0x0 scc_flash_din3 eFlash 0 and eFlash 1 data input[127:96] [31:0] FLASH0_DOUT_0 0x1C0 32 read-only 0xFFFFFFFF scc_flash0_dout0 eFlash 0 data output[31:0] [31:0] FLASH0_DOUT_1 0x1C4 32 read-only 0xFFFFFFFF scc_flash0_dout1 eFlash 0 data output[63:32] [31:0] FLASH0_DOUT_2 0x1C8 32 read-only 0xFFFFFFFF scc_flash0_dout2 eFlash 0 data output[95:64] [31:0] FLASH0_DOUT_3 0x1CC 32 read-only 0xFFFFFFFF scc_flash0_dout3 eFlash 0 data output[127:96] [31:0] FLASH1_DOUT_0 0x1D0 32 read-only 0xFFFFFFFF scc_flash1_dout0 eFlash 1 data output[31:0] [31:0] FLASH1_DOUT_1 0x1D4 32 read-only 0xFFFFFFFF scc_flash1_dout1 eFlash 1 data output[63:32] [31:0] FLASH1_DOUT_2 0x1D8 32 read-only 0xFFFFFFFF scc_flash1_dout2 eFlash 1 data output[95:64] [31:0] FLASH1_DOUT_3 0x1DC 32 read-only 0xFFFFFFFF scc_flash1_dout3 eFlash 1 data output[127:96] [31:0] SELECTION_CONTROL_REG 0x1E0 32 read-write 0x01000200 clock_phase_shifter_select QSPI input clock phase shift control [1:0] clock_phase_shifter_bypass QSPI input clock phase shift control [2:2] sdio_mask_delay SDIO mask delay [9:8] AZ_ROM_REMAP_MASK 0x1E4 32 read-write 0x0001FFFF az_rom_remap_mask Alcatraz ROM remap mask [31:0] AZ_ROM_REMAP_OFFSET 0x1E8 32 read-write 0x1A200000 az_rom_remap_offset Alcatraz ROM remap offset [31:0] AZ_CODE_REMAP_MASK 0x1EC 32 read-write 0x00FFFFFF az_code_remap_mask Alcatraz code remap mask [31:0] AZ_CODE_REMAP_OFFSET 0x1F0 32 read-write 0x0 az_code_remap_offset Alcatraz code remap offset [31:0] AZ_SYS_REMAP_MASK 0x1F4 32 read-write 0x0003FFFF az_sys_remap_mask Alcatraz system remap mask [31:0] AZ_SYS_REMAP_OFFSET 0x1F8 32 read-write 0x40010000 az_sys_remap_offset Alcatraz system remap offset [31:0] AZ_CTRL 0x200 32 read-write 0x00000600 AZ_BOOT_REMAP Alcatraz remap at boot [0:0] CPUWAIT Alcatraz CPU wait at boot: [1:1] REMOVE_CHACHA_ENGINE Alcatraz CryptoCell remove CHACHA engine [2:2] REMOVE_GHASH_ENGINE Alcatraz CryptoCell remove Ghash engine [3:3] CHSEC_ISO_ENB Alcatraz CryptoCell Secure Frame Isolation enable [4:4] CHSEC_MISC_7 Alcatraz CryptoCell secure Secure Frame control [5:5] DBGRESETn Alcatraz reset DBGRESETn [7:7] HRESETn Alcatraz reset HRESETn [8:8] SCC_nPORESETAON_nPORESET_SEL Alcatraz reset control [9:9] SCC_PSI_FEATURE_EN Value of SCC_PSI_FEATURE_EN from SCC [10:10] SCC_PSI_FEATURE_EN_SEL Select PSI_FEATURE_EN source [11:11] SSE_OTP_RD_DATA 0x208 32 read-only 0x0 sse_otp_rd_data SSE-200 OTP read data [31:0] AZ_OTP_RD_DATA 0x210 32 read-write 0x0 az_otp_rd_data Alcatraz OTP read data [31:0] SPARE_CTRL0 0x21C 32 read-write 0x0 spare_ctrl0 Spare control register [31:0] SPARE_CTRL1 0x220 32 read-write 0x0 spare_ctrl1 Spare control register [31:0] CHIP_ID 0x400 32 read-only 0x07D00477 chip_id Component ID information [31:0] SPCTRL Secure Privilege Control Block 0x50080000 0 0x1000 registers SPCSECTRL Secure Privilege Controller Secure Configuration Control register 0x0 32 read-write 0x0 BUSWAIT Bus Access wait control after reset 0x4 32 read-write SECRESPCFG Security Violation Response Configuration register 0x10 32 read-write 0x0 NSCCFG Non Secure Callable Configuration for IDAU 0x14 32 read-write 0x0 SECMPCINTSTATUS Secure MPC Interrupt Status 0x1C 32 read-only 0x0 SECPPCINTSTAT Secure PPC Interrupt Status 0x20 32 read-only 0x0 SECPPCINTCLR Secure PPC Interrupt Clear 0x24 32 write-only 0x0 SECPPCINTEN Secure PPC Interrupt Enable 0x28 32 read-write 0x0 SECMSCINTSTAT Secure MSC Interrupt Status 0x30 32 read-only 0x0 SECMSCINTCLR Secure MSC Interrupt Clear 0x34 32 read-write 0x0 SECMSCINTEN Secure MSC Interrupt Enable 0x38 32 read-write 0x0 BRGINTSTAT Bridge Buffer Error Interrupt Status 0x40 32 read-only 0x0 BRGINTCLR Bridge Buffer Error Interrupt Clear 0x44 32 write-only 0x0 BRGINTEN Bridge Buffer Error Interrupt Enable 0x48 32 read-write 0x0 AHBNSPPC0 Non-Secure Access AHB slave Peripheral Protection Control 0 0x50 32 read-write 0x0 AHBNSPPCEXP0 Expansion 0 Non_Secure Access AHB slave Peripheral Protection Control 0x60 32 read-write 0x0 AHBNSPPCEXP1 Expansion 1 Non_Secure Access AHB slave Peripheral Protection Control 0x64 32 read-write 0x0 AHBNSPPCEXP2 Expansion 2 Non_Secure Access AHB slave Peripheral Protection Control 0x68 32 read-write 0x0 AHBNSPPCEXP3 Expansion 3 Non_Secure Access AHB slave Peripheral Protection Control 0x6C 32 read-write 0x0 APBNSPPC0 Non-Secure Access APB slave Peripheral Protection Control 0 0x70 32 read-write 0x0 APBNSPPC1 Non-Secure Access APB slave Peripheral Protection Control 1 0x74 32 read-write 0x0 APBNSPPCEXP0 Expansion 0 Non_Secure Access APB slave Peripheral Protection Control 0x80 32 read-write 0x0 APBNSPPCEXP1 Expansion 1 Non_Secure Access APB slave Peripheral Protection Control 0x84 32 read-write 0x0 APBNSPPCEXP2 Expansion 2 Non_Secure Access APB slave Peripheral Protection Control 0x88 32 read-write 0x0 APBNSPPCEXP3 Expansion 3 Non_Secure Access APB slave Peripheral Protection Control 0x8C 32 read-write 0x0 AHBSPPPC0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0 0x90 32 read-only 0x0 AHBSPPPCEXP0 Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write 0x0 AHBSPPPCEXP1 Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write 0x0 AHBSPPPCEXP2 Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write 0x0 AHBSPPPCEXP3 Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write 0x0 APBSPPPC0 Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write 0x0 APBSPPPC1 Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write 0x0 APBSPPPCEXP0 Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write 0x0 APBSPPPCEXP1 Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write 0x0 APBSPPPCEXP2 Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write 0x0 APBSPPPCEXP3 Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write 0x0 NSMSCEXP Expansion MSC Non-Secure Configuration 0xD0 32 read-only 0x0 PID4 Peripheral ID 4 0xFD0 32 read-only 0x00000004 PID0 Peripheral ID 0 0xFE0 32 read-only 0x00000052 PID1 Peripheral ID 1 0xFE4 32 read-only 0x000000B8 PID2 Peripheral ID 2 0xFE8 32 read-only 0x0000000B PID3 Peripheral ID 3 0xFEC 32 read-only 0x0 CIDR0 Component ID 0 0xFF0 32 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 32 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 32 read-only 0x00000005 CIDR3 Component ID 3 0xFFC 32 read-only 0x000000B1 NSPCTRL Non-secure Privilege Control Block 0x40080000 0 0x1000 registers AHBNSPPPC0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control #0 0x90 32 read-write 0x0 AHBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write 0x0 AHBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write 0x0 AHBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write 0x0 AHBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write 0x0 APBNSPPPC0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write 0x0 APBNSPPPC1 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write 0x0 APBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write 0x0 APBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write 0x0 APBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write 0x0 APBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write 0x0 PIDR4 Peripheral ID 4 0xFD0 32 read-only 0x0 PIDR0 Peripheral ID 0 0xFE0 32 read-only 0x00000053 PIDR1 Peripheral ID 1 0xFE4 32 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 32 read-only 0x0000000B PIDR3 Peripheral ID 3 0xFEC 32 read-only 0x0 CIDR0 Component ID 0 0xFF0 32 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 32 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 32 read-only 0x00000005 CIDR3 Component ID 3 0xFFC 32 read-only 0x000000B1 SRAM0MPC Memory Protection Controller 0 SRAM_MPC 0x50083000 0 0x1000 registers MPC MPC Combined 9 CTRL MPC Control register 0x00 32 read-write bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 bit[31] Security lockdown 31 1 0x0 BLK_MAX Maximum value of block based index register 0x10 32 read-only bit[3_0] Block size 0 4 bit[31] Initialization in progress 31 1 BLK_CFG Block Configuration 0x14 32 read-only BLK_IDX Index value for accessing block based look up table 0x18 32 read-write 0x0 BLK_LUT Block based gating Look Up Table 0x1C 32 read-write INT_STAT Interrupt state 0x20 32 read-only bit[0] mpc_irq triggered 0 1 0x0 INT_CLEAR Interrupt clear 0x24 32 write-only bit[0] mpc_irq clear (cleared automatically) 0 1 0x0 INT_EN Interrupt enable 0x28 32 read-write bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 0x0 INT_INFO1 Interrupt information 1 0x2C 32 read-only 0x0 INT_INFO2 Interrupt information 2 0x30 32 read-only bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only bit[0] mpc_irq set. Debug purpose only 0 1 0x0 PIDR4 Peripheral ID 4 0xFD0 32 read-only bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 0x00000004 PIDR5 Peripheral ID 5 0xFD4 32 read-only bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 0x0 PIDR6 Peripheral ID 6 0xFD8 32 read-only 0x0 PIDR7 Peripheral ID 7 0xFDC 32 read-only 0x0 PIDR0 Peripheral ID 0 0xFE0 32 read-only 0x00000060 PIDR1 Peripheral ID 1 0xFE4 32 read-only 0x000000B8 PIDR2 Peripheral ID 2 0xFE8 32 read-only bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 0x0000000B PIDR3 Peripheral ID 3 0xFEC 32 read-only bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 0x0 CIDR0 Component ID 0 0xFF0 32 read-only 0x0000000D CIDR1 Component ID 1 0xFF4 32 read-only 0x000000F0 CIDR2 Component ID 2 0xFF8 32 read-only 0x00000005 CIDR3 Component ID 3 0xFFC 32 read-only 0x000000B1 SRAM1MPC SRAM 1 Memory Protection Controller SRAM_MPC 0x50084000 SRAM2MPC SRAM 2 Memory Protection Controller SRAM_MPC 0x50085000 SRAM3MPC SRAM 3 Memory Protection Controller SRAM_MPC 0x50086000 CODE_SRAM_MPC Code SRAM Memory Protection Controller SRAM_MPC 0x52100000 QSPI_MPC QSPI Flash Memory Protection Controller QSPI_MPC 0x52000000 EFLASH0_MPC EFlash0 Memory Protection Controller EFLASH0_MPC 0x52200000 EFLASH1_MPC EFlash1 Memory Protection Controller EFLASH1_MPC 0x52300000 QSPIFCTRL 1.0 QSPI Flash Controller QSPI 0x42800000 32 read-write 0 0xB0 registers QSPIINTR QSPI interrupt 38 QSPICFG QSPI Configuration Register 0x00 0x80780081 read-write PIPLIDLE Serial Interface and QSPI pipeline is IDLE [31:31] PIPLPHYEN Pipeline PHY Mode enable [25:25] DTREN Enable DTR Protocol [24:24] AHBDECEN Enable AHB Decoder [23:23] MAMOBRDIV Master mode baud rate divisor (2 to 32) [22:19] ENTRXIPMODEIMM Enter XIP Mode immediately [18:18] ENTRXIPMODEONR Enter XIP Mode on next READ [17:17] ENAHBADDRRM Enable AHB Address Re-mapping [16:16] ENDMAPIF Enable DMA Peripheral Interface [15:15] WPPINDRV Set to drive the WP pin of Flash device [14:14] PERCSLINES Peripheral chip select lines [13:10] ss0 n_ss_out: 0b1110 0bxxx0 ss1 n_ss_out: 0b1101 0bxx01 ss2 n_ss_out: 0b1011 0bx011 ss3 n_ss_out: 0b0111 0b0111 ssinactive n_ss_out: 0b1111 (no peripheral selected) 0b1111 PERSELDEC Peripheral select decode [9:9] Disabled Only 1 of 4 selects n_ss_out is active 0 Enabled Allow external 4-to-16 decode 1 LEGIPMODEEN Legacy IP Mode Enable [8:8] ENDIRACCCTR Enable Direct Access Controller [7:7] PHYMODEEN PHY Mode enable [3:3] CLKPHASE Clock phase, this maps to the standard SPI CPHA transfer format [2:2] CLKPOLARITY Clock polarity outside SPI word. This maps to the standard SPI CPOL transfer format [1:1] QSPIEN QSPI Enable [0:0] DEVREADINSTR Device Read Instruction Register 0x04 0x00000003 read-write READDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Read Instruction [28:24] MODEBITEN Mode Bit Enable [20:20] DATATRTYPESSPI Data Transfer Type for Standard SPI modes [17:16] ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes [13:12] DDRBITEN DDR Bit Enable [10:10] INSTRTYPE Instruction Type [9:8] ROPCODE Read Opcode to use when not in XIP mode [7:0] DEVWRITEINSTR Device Write Instruction Configuration Register 0x08 0x00000002 read-write WRITEDUMCLKCYCNUM Number of Dummy Clock Cycles required by device for Write Instruction [28:24] DATATRTYPESSPI Data Transfer Type for Standard SPI modes [17:16] ADDRTRTYPESSPI Address Transfer Type for Standard SPI modes [13:12] WELDISABLE WEL Disable [8:8] WROPCODE Write Opcode [7:0] DEVSIZE Device Size Configuration Register 0x14 0X00101002 read-write FDEVSIZECS3 Size of Flash Device connected to CS[3] pin [28:27] FDEVSIZECS2 Size of Flash Device connected to CS[2] pin [26:25] FDEVSIZECS1 Size of Flash Device connected to CS[1] pin [24:23] FDEVSIZECS0 Size of Flash Device connected to CS[0] pin [22:21] BYTEPERBLKNUM Number of bytes per block [20:16] BYTEPERDEVPGNUM Number of bytes per device page [15:4] ADDRBYTENUM Number of address bytes [3:0] REMAPADDR Remap Address Register 0x24 0x00000000 read-write FLASHCMDCTRL Flash Command Control Register 0x90 0x00000000 read-write CMDOPCODE Command Opcode [31:24] RDATAEN Read Data Enable [23:23] RDATABYTENUM Number of Read Data Bytes [22:20] CMDADDREN Command Address Enable [19:19] MODEBITEN Mode Bit Enable [18:18] ADDRBYTENUM Number of Address Bytes [17:16] WRDATAEN Write Data Enable [15:15] WRDATABYTENUM Number of Write Data Bytes [14:12] DUMCYCNUM Number of Dummy Cycles [11:7] CMDEXINPROG Command execution in progress [1:1] CMDEXEC Execute the command [0:0] FLASHCMDADDR Flash Command Address Register 0x94 0x00000000 read-write FLASHCMDRDATALOW Flash Command Read Data Register (Lower) 0xA0 0x00000000 read-only FLASHCMDRDATAUP Flash Command Read Data Register (Upper) 0xA4 0x00000000 read-only FLASHCMDWRDATALOW Flash Command Write Data Register (Lower) 0xA8 0x00000000 read-write FLASHCMDWRDATAUP Flash Command Write Data Register (Upper) 0xAC 0x00000000 read-write QSPIFCTRL_Secure QSPI Flash Controller (Secure) QSPI (Secure) 0x52800000