image/svg+xml Baudgen_tx clk clk_out clk_ena rstn Counter clk clk_baud rstn clear clear baudgen 4 bits Shift register clk rstn ser_in 10 bits clk_baud data Data register clk rstn 8 bits 8 load Controller 4 clk rstn clk D load baudgen bitc clk rstn uart-rx.v clear rx rcv data