image/svg+xml IDLE RCV LOAD load=0 bauden=0 rcv=0 rx_r = 0 1 clock cycle bitc < 11 clear=1 load=0 bauden=1 rcv=0 clear=0 bitc = 10 load=1 bauden=0 rcv=0 clear=0 DAV load=0 bauden=0 rcv=1 clear=0 1 clock cycle