image/svg+xml Baudgen_tx clk clk_out clk_ena rstn Counter clk clk_baud rstn load load baudgen 4 bits Shift register clk rstn ser_in 10 bits 1 clk_baud ser_out load data Data register clk rstn 8 bits 8 load Controller 4 clk rstn clk D Tx load baudgen clk D start ready bitc Data clk rstn start_r 8 uart-tx.v 0 1