(function() {var implementors = {}; implementors["nonminmax"] = [{"text":"impl PartialOrd<NonMaxU8> for NonMaxU8","synthetic":false,"types":["nonminmax::NonMaxU8"]},{"text":"impl PartialOrd<NonMaxU16> for NonMaxU16","synthetic":false,"types":["nonminmax::NonMaxU16"]},{"text":"impl PartialOrd<NonMaxU32> for NonMaxU32","synthetic":false,"types":["nonminmax::NonMaxU32"]},{"text":"impl PartialOrd<NonMaxU64> for NonMaxU64","synthetic":false,"types":["nonminmax::NonMaxU64"]},{"text":"impl PartialOrd<NonMaxU128> for NonMaxU128","synthetic":false,"types":["nonminmax::NonMaxU128"]},{"text":"impl PartialOrd<NonMaxUsize> for NonMaxUsize","synthetic":false,"types":["nonminmax::NonMaxUsize"]},{"text":"impl PartialOrd<NonMaxI8> for NonMaxI8","synthetic":false,"types":["nonminmax::NonMaxI8"]},{"text":"impl PartialOrd<NonMaxI16> for NonMaxI16","synthetic":false,"types":["nonminmax::NonMaxI16"]},{"text":"impl PartialOrd<NonMaxI32> for NonMaxI32","synthetic":false,"types":["nonminmax::NonMaxI32"]},{"text":"impl PartialOrd<NonMaxI64> for NonMaxI64","synthetic":false,"types":["nonminmax::NonMaxI64"]},{"text":"impl PartialOrd<NonMaxI128> for NonMaxI128","synthetic":false,"types":["nonminmax::NonMaxI128"]},{"text":"impl PartialOrd<NonMaxIsize> for NonMaxIsize","synthetic":false,"types":["nonminmax::NonMaxIsize"]},{"text":"impl PartialOrd<NonMinU8> for NonMinU8","synthetic":false,"types":["nonminmax::NonMinU8"]},{"text":"impl PartialOrd<NonMinU16> for NonMinU16","synthetic":false,"types":["nonminmax::NonMinU16"]},{"text":"impl PartialOrd<NonMinU32> for NonMinU32","synthetic":false,"types":["nonminmax::NonMinU32"]},{"text":"impl PartialOrd<NonMinU64> for NonMinU64","synthetic":false,"types":["nonminmax::NonMinU64"]},{"text":"impl PartialOrd<NonMinU128> for NonMinU128","synthetic":false,"types":["nonminmax::NonMinU128"]},{"text":"impl PartialOrd<NonMinUsize> for NonMinUsize","synthetic":false,"types":["nonminmax::NonMinUsize"]},{"text":"impl PartialOrd<NonMinI8> for NonMinI8","synthetic":false,"types":["nonminmax::NonMinI8"]},{"text":"impl PartialOrd<NonMinI16> for NonMinI16","synthetic":false,"types":["nonminmax::NonMinI16"]},{"text":"impl PartialOrd<NonMinI32> for NonMinI32","synthetic":false,"types":["nonminmax::NonMinI32"]},{"text":"impl PartialOrd<NonMinI64> for NonMinI64","synthetic":false,"types":["nonminmax::NonMinI64"]},{"text":"impl PartialOrd<NonMinI128> for NonMinI128","synthetic":false,"types":["nonminmax::NonMinI128"]},{"text":"impl PartialOrd<NonMinIsize> for NonMinIsize","synthetic":false,"types":["nonminmax::NonMinIsize"]}]; if (window.register_implementors) {window.register_implementors(implementors);} else {window.pending_implementors = implementors;}})()