Nordic Semiconductor Nordic nrf52840 nrf52 1 nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller Copyright (c) 2010 - 2018, Nordic Semiconductor ASA\n \n All rights reserved.\n \n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n \n 1. Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n \n 2. Redistributions in binary form, except as embedded into a Nordic\n Semiconductor ASA integrated circuit in a product or a software update for\n such product, must reproduce the above copyright notice, this list of\n conditions and the following disclaimer in the documentation and/or other\n materials provided with the distribution.\n \n 3. Neither the name of Nordic Semiconductor ASA nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n \n 4. This software, with or without modification, must only be used with a\n Nordic Semiconductor ASA integrated circuit.\n \n 5. Any software provided in binary form under this license must not be reverse\n engineered, decompiled, modified and/or disassembled.\n \n THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS\n OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\n OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)\n HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT\n LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT\n OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n 8 32 32 0x00000000 0xFFFFFFFF CM4 r0p1 little 1 1 3 0 system_nrf52840 NRF_ 2048 2048 112 FICR Factory information configuration registers 0x10000000 0 0x1000 registers FICR 0x20 CODEPAGESIZE Code memory page size 0x010 read-only 0xFFFFFFFF CODEPAGESIZE Code memory page size 0 31 CODESIZE Code memory size 0x014 read-only 0xFFFFFFFF CODESIZE Code memory size in number of pages 0 31 0x2 0x4 DEVICEID[%s] Description collection[n]: Device identifier 0x060 read-only 0xFFFFFFFF DEVICEID 64 bit unique device identifier 0 31 0x4 0x4 ER[%s] Description collection[n]: Encryption root, word n 0x080 read-only 0xFFFFFFFF ER Encryption root, word n 0 31 0x4 0x4 IR[%s] Description collection[n]: Identity Root, word n 0x090 read-only 0xFFFFFFFF IR Identity Root, word n 0 31 DEVICEADDRTYPE Device address type 0x0A0 read-only 0xFFFFFFFF DEVICEADDRTYPE Device address type 0 0 Public Public address 0 Random Random address 1 0x2 0x4 DEVICEADDR[%s] Description collection[n]: Device address n 0x0A4 read-only 0xFFFFFFFF DEVICEADDR 48 bit device address 0 31 INFO Device info FICR_INFO 0x100 PART Part code 0x000 read-only 0x00052840 PART Part code 0 31 N52840 nRF52840 0x52840 Unspecified Unspecified 0xFFFFFFFF VARIANT Build code (hardware version and production configuration) 0x004 read-only 0xFFFFFFFF VARIANT Build code (hardware version and production configuration). Encoded as ASCII. 0 31 AAAA AAAA 0x41414141 BAAA BAAA 0x42414141 CAAA CAAA 0x43414141 AABA AABA 0x41414241 AABB AABB 0x41414242 AACA AACA 0x41414341 AAAB AAAB 0x41414142 Unspecified Unspecified 0xFFFFFFFF PACKAGE Package option 0x008 read-only 0xFFFFFFFF PACKAGE Package option 0 31 QI QIxx - 73-pin aQFN 0x2004 Unspecified Unspecified 0xFFFFFFFF RAM RAM variant 0x00C read-only 0xFFFFFFFF RAM RAM variant 0 31 K16 16 kByte RAM 0x10 K32 32 kByte RAM 0x20 K64 64 kByte RAM 0x40 K128 128 kByte RAM 0x80 K256 256 kByte RAM 0x100 Unspecified Unspecified 0xFFFFFFFF FLASH Flash variant 0x010 read-only 0xFFFFFFFF FLASH Flash variant 0 31 K128 128 kByte FLASH 0x80 K256 256 kByte FLASH 0x100 K512 512 kByte FLASH 0x200 K1024 1 MByte FLASH 0x400 K2048 2 MByte FLASH 0x800 Unspecified Unspecified 0xFFFFFFFF 0x3 0x4 UNUSED8[%s] Unspecified 0x014 read-write 0x3 0x4 PRODTEST[%s] Description collection[n]: Production test signature n 0x350 read-only 0xFFFFFFFF PRODTEST Production test signature n 0 31 Done Production tests done 0xBB42319F NotDone Production tests not done 0xFFFFFFFF TEMP Registers storing factory TEMP module linearization coefficients FICR_TEMP 0x404 A0 Slope definition A0 0x000 read-only 0xFFFFF320 A A (slope definition) register. 0 11 A1 Slope definition A1 0x004 read-only 0xFFFFF343 A A (slope definition) register. 0 11 A2 Slope definition A2 0x008 read-only 0xFFFFF35D A A (slope definition) register. 0 11 A3 Slope definition A3 0x00C read-only 0xFFFFF400 A A (slope definition) register. 0 11 A4 Slope definition A4 0x010 read-only 0xFFFFF452 A A (slope definition) register. 0 11 A5 Slope definition A5 0x014 read-only 0xFFFFF37B A A (slope definition) register. 0 11 B0 Y-intercept B0 0x018 read-only 0xFFFF3FCC B B (y-intercept) 0 13 B1 Y-intercept B1 0x01C read-only 0xFFFF3F98 B B (y-intercept) 0 13 B2 Y-intercept B2 0x020 read-only 0xFFFF3F98 B B (y-intercept) 0 13 B3 Y-intercept B3 0x024 read-only 0xFFFF0012 B B (y-intercept) 0 13 B4 Y-intercept B4 0x028 read-only 0xFFFF004D B B (y-intercept) 0 13 B5 Y-intercept B5 0x02C read-only 0xFFFF3E10 B B (y-intercept) 0 13 T0 Segment end T0 0x030 read-only 0xFFFFFFE2 T T (segment end) register 0 7 T1 Segment end T1 0x034 read-only 0xFFFFFF00 T T (segment end) register 0 7 T2 Segment end T2 0x038 read-only 0xFFFFFF14 T T (segment end) register 0 7 T3 Segment end T3 0x03C read-only 0xFFFFFF19 T T (segment end) register 0 7 T4 Segment end T4 0x040 read-only 0xFFFFFF50 T T (segment end) register 0 7 NFC Unspecified FICR_NFC 0x450 TAGHEADER0 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. 0x000 read-only 0xFFFFFF5F MFGID Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F 0 7 UD1 Unique identifier byte 1 8 15 UD2 Unique identifier byte 2 16 23 UD3 Unique identifier byte 3 24 31 TAGHEADER1 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. 0x004 read-only 0xFFFFFFFF UD4 Unique identifier byte 4 0 7 UD5 Unique identifier byte 5 8 15 UD6 Unique identifier byte 6 16 23 UD7 Unique identifier byte 7 24 31 TAGHEADER2 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. 0x008 read-only 0xFFFFFFFF UD8 Unique identifier byte 8 0 7 UD9 Unique identifier byte 9 8 15 UD10 Unique identifier byte 10 16 23 UD11 Unique identifier byte 11 24 31 TAGHEADER3 Default header for NFC tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. 0x00C read-only 0xFFFFFFFF UD12 Unique identifier byte 12 0 7 UD13 Unique identifier byte 13 8 15 UD14 Unique identifier byte 14 16 23 UD15 Unique identifier byte 15 24 31 TRNG90B NIST800-90B RNG calibration data FICR_TRNG90B 0xC00 BYTES Amount of bytes for the required entropy bits 0x000 read-only 0xFFFFFFFF BYTES Amount of bytes for the required entropy bits 0 31 RCCUTOFF Repetition counter cutoff 0x004 read-only 0xFFFFFFFF RCCUTOFF Repetition counter cutoff 0 31 APCUTOFF Adaptive proportion cutoff 0x008 read-only 0xFFFFFFFF APCUTOFF Adaptive proportion cutoff 0 31 STARTUP Amount of bytes for the startup tests 0x00C read-only 0x00000210 STARTUP Amount of bytes for the startup tests 0 31 ROSC1 Sample count for ring oscillator 1 0x010 read-only 0xFFFFFFFF ROSC1 Sample count for ring oscillator 1 0 31 ROSC2 Sample count for ring oscillator 2 0x014 read-only 0xFFFFFFFF ROSC2 Sample count for ring oscillator 2 0 31 ROSC3 Sample count for ring oscillator 3 0x018 read-only 0xFFFFFFFF ROSC3 Sample count for ring oscillator 3 0 31 ROSC4 Sample count for ring oscillator 4 0x01C read-only 0xFFFFFFFF ROSC4 Sample count for ring oscillator 4 0 31 UICR User information configuration registers 0x10001000 0 0x1000 registers UICR 0x20 UNUSED0 Unspecified 0x000 read-write UNUSED1 Unspecified 0x004 read-write UNUSED2 Unspecified 0x008 read-write UNUSED3 Unspecified 0x010 read-write 0xF 0x4 NRFFW[%s] Description collection[n]: Reserved for Nordic firmware design 0x014 read-write 0xFFFFFFFF NRFFW Reserved for Nordic firmware design 0 31 0xC 0x4 NRFHW[%s] Description collection[n]: Reserved for Nordic hardware design 0x050 read-write 0xFFFFFFFF NRFHW Reserved for Nordic hardware design 0 31 0x20 0x4 CUSTOMER[%s] Description collection[n]: Reserved for customer 0x080 read-write 0xFFFFFFFF CUSTOMER Reserved for customer 0 31 0x2 0x4 PSELRESET[%s] Description collection[n]: Mapping of the nRESET function 0x200 read-write 0xFFFFFFFF PIN Pin number of PORT onto which nRESET is exposed 0 4 PORT Port number onto which nRESET is exposed 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 APPROTECT Access port protection 0x208 read-write 0xFFFFFFFF PALL Enable or disable access port protection. 0 7 Disabled Disable 0xFF Enabled Enable 0x00 NFCPINS Setting of pins dedicated to NFC functionality: NFC antenna or GPIO 0x20C read-write 0xFFFFFFFF PROTECT Setting of pins dedicated to NFC functionality 0 0 Disabled Operation as GPIO pins. Same protection as normal GPIO pins 0 NFC Operation as NFC antenna pins. Configures the protection for NFC operation 1 DEBUGCTRL Processor debug control 0x210 read-write 0xFFFFFFFF CPUNIDEN Configure CPU non-intrusive debug features 0 7 Enabled Enable CPU ITM and ETM functionality (default behavior) 0xFF Disabled Disable CPU ITM and ETM functionality 0x00 CPUFPBEN Configure CPU flash patch and breakpoint (FPB) unit behavior 8 15 Enabled Enable CPU FPB unit (default behavior) 0xFF Disabled Disable CPU FPB unit. Writes into the FPB registers will be ignored. 0x00 REGOUT0 GPIO reference voltage / external output supply voltage in high voltage mode 0x304 read-write 0xFFFFFFFF VOUT Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF. 0 2 1V8 1.8 V 0 2V1 2.1 V 1 2V4 2.4 V 2 2V7 2.7 V 3 3V0 3.0 V 4 3V3 3.3 V 5 DEFAULT Default voltage: 1.8 V 7 CLOCK Clock control 0x40000000 0 0x1000 registers POWER_CLOCK 0 CLOCK 0x20 TASKS_HFCLKSTART Start HFXO crystal oscillator 0x000 write-only TASKS_HFCLKSTART 0 0 TASKS_HFCLKSTOP Stop HFXO crystal oscillator 0x004 write-only TASKS_HFCLKSTOP 0 0 TASKS_LFCLKSTART Start LFCLK 0x008 write-only TASKS_LFCLKSTART 0 0 TASKS_LFCLKSTOP Stop LFCLK 0x00C write-only TASKS_LFCLKSTOP 0 0 TASKS_CAL Start calibration of LFRC 0x010 write-only TASKS_CAL 0 0 TASKS_CTSTART Start calibration timer 0x014 write-only TASKS_CTSTART 0 0 TASKS_CTSTOP Stop calibration timer 0x018 write-only TASKS_CTSTOP 0 0 EVENTS_HFCLKSTARTED HFXO crystal oscillator started 0x100 read-write EVENTS_HFCLKSTARTED 0 0 EVENTS_LFCLKSTARTED LFCLK started 0x104 read-write EVENTS_LFCLKSTARTED 0 0 EVENTS_DONE Calibration of LFRC completed 0x10C read-write EVENTS_DONE 0 0 EVENTS_CTTO Calibration timer timeout 0x110 read-write EVENTS_CTTO 0 0 EVENTS_CTSTARTED Calibration timer has been started and is ready to process new tasks 0x128 read-write EVENTS_CTSTARTED 0 0 EVENTS_CTSTOPPED Calibration timer has been stopped and is ready to process new tasks 0x12C read-write EVENTS_CTSTOPPED 0 0 INTENSET Enable interrupt 0x304 read-write HFCLKSTARTED Write '1' to enable interrupt for HFCLKSTARTED event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LFCLKSTARTED Write '1' to enable interrupt for LFCLKSTARTED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DONE Write '1' to enable interrupt for DONE event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CTTO Write '1' to enable interrupt for CTTO event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CTSTARTED Write '1' to enable interrupt for CTSTARTED event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CTSTOPPED Write '1' to enable interrupt for CTSTOPPED event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write HFCLKSTARTED Write '1' to disable interrupt for HFCLKSTARTED event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LFCLKSTARTED Write '1' to disable interrupt for LFCLKSTARTED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DONE Write '1' to disable interrupt for DONE event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CTTO Write '1' to disable interrupt for CTTO event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CTSTARTED Write '1' to disable interrupt for CTSTARTED event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CTSTOPPED Write '1' to disable interrupt for CTSTOPPED event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 HFCLKRUN Status indicating that HFCLKSTART task has been triggered 0x408 read-only STATUS HFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0 Triggered Task triggered 1 HFCLKSTAT HFCLK status 0x40C read-only SRC Source of HFCLK 0 0 RC 64 MHz internal oscillator (HFINT) 0 Xtal 64 MHz crystal oscillator (HFXO) 1 STATE HFCLK state 16 16 NotRunning HFCLK not running 0 Running HFCLK running 1 LFCLKRUN Status indicating that LFCLKSTART task has been triggered 0x414 read-only STATUS LFCLKSTART task triggered or not 0 0 NotTriggered Task not triggered 0 Triggered Task triggered 1 LFCLKSTAT LFCLK status 0x418 read-only SRC Source of LFCLK 0 1 RC 32.768 kHz RC oscillator (LFRC) 0 Xtal 32.768 kHz crystal oscillator (LFXO) 1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) 2 STATE LFCLK state 16 16 NotRunning LFCLK not running 0 Running LFCLK running 1 LFCLKSRCCOPY Copy of LFCLKSRC register, set when LFCLKSTART task was triggered 0x41C read-only SRC Clock source 0 1 RC 32.768 kHz RC oscillator (LFRC) 0 Xtal 32.768 kHz crystal oscillator (LFXO) 1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) 2 LFCLKSRC Clock source for the LFCLK 0x518 read-write SRC Clock source 0 1 RC 32.768 kHz RC oscillator (LFRC) 0 Xtal 32.768 kHz crystal oscillator (LFXO) 1 Synth 32.768 kHz synthesized from HFCLK (LFSYNT) 2 BYPASS Enable or disable bypass of LFCLK crystal oscillator with external clock source 16 16 Disabled Disable (use with Xtal or low-swing external source) 0 Enabled Enable (use with rail-to-rail external source) 1 EXTERNAL Enable or disable external source for LFCLK 17 17 Disabled Disable external source (use with Xtal) 0 Enabled Enable use of external source instead of Xtal (SRC needs to be set to Xtal) 1 HFXODEBOUNCE HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task. 0x528 read-write 0x00000010 HFXODEBOUNCE HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us. 0 7 Db256us 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals. 0x10 Db1024us 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals. 0x40 CTIV Calibration timer interval 0x538 read-write CTIV Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. 0 6 TRACECONFIG Clocking options for the trace port debug interface 0x55C read-write 0x00000000 TRACEPORTSPEED Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two. 0 1 32MHz 32 MHz trace port clock (TRACECLK = 16 MHz) 0 16MHz 16 MHz trace port clock (TRACECLK = 8 MHz) 1 8MHz 8 MHz trace port clock (TRACECLK = 4 MHz) 2 4MHz 4 MHz trace port clock (TRACECLK = 2 MHz) 3 TRACEMUX Pin multiplexing of trace signals. See pin assignment chapter for more details. 16 17 GPIO No trace signals routed to pins. All pins can be used as regular GPIOs. 0 Serial SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs. 1 Parallel All trace signals (TRACECLK and TRACEDATA[n]) routed to pins. 2 LFRCMODE LFRC mode configuration 0x5B4 read-write 0x00000000 MODE Set LFRC mode 0 0 Normal Normal mode 0 ULP Ultra-low power mode (ULP) 1 STATUS Active LFRC mode. This field is read only. 16 16 Normal Normal mode 0 ULP Ultra-low power mode (ULP) 1 POWER Power control 0x40000000 CLOCK 0 0x1000 registers POWER_CLOCK 0 POWER 0x20 TASKS_CONSTLAT Enable constant latency mode 0x78 write-only TASKS_CONSTLAT 0 0 TASKS_LOWPWR Enable low power mode (variable latency) 0x7C write-only TASKS_LOWPWR 0 0 EVENTS_POFWARN Power failure warning 0x108 read-write EVENTS_POFWARN 0 0 EVENTS_SLEEPENTER CPU entered WFI/WFE sleep 0x114 read-write EVENTS_SLEEPENTER 0 0 EVENTS_SLEEPEXIT CPU exited WFI/WFE sleep 0x118 read-write EVENTS_SLEEPEXIT 0 0 EVENTS_USBDETECTED Voltage supply detected on VBUS 0x11C read-write EVENTS_USBDETECTED 0 0 EVENTS_USBREMOVED Voltage supply removed from VBUS 0x120 read-write EVENTS_USBREMOVED 0 0 EVENTS_USBPWRRDY USB 3.3 V supply ready 0x124 read-write EVENTS_USBPWRRDY 0 0 INTENSET Enable interrupt 0x304 read-write POFWARN Write '1' to enable interrupt for POFWARN event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SLEEPENTER Write '1' to enable interrupt for SLEEPENTER event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SLEEPEXIT Write '1' to enable interrupt for SLEEPEXIT event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 USBDETECTED Write '1' to enable interrupt for USBDETECTED event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 USBREMOVED Write '1' to enable interrupt for USBREMOVED event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 USBPWRRDY Write '1' to enable interrupt for USBPWRRDY event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write POFWARN Write '1' to disable interrupt for POFWARN event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SLEEPENTER Write '1' to disable interrupt for SLEEPENTER event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SLEEPEXIT Write '1' to disable interrupt for SLEEPEXIT event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 USBDETECTED Write '1' to disable interrupt for USBDETECTED event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 USBREMOVED Write '1' to disable interrupt for USBREMOVED event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 USBPWRRDY Write '1' to disable interrupt for USBPWRRDY event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESETREAS Reset reason 0x400 read-write RESETPIN Reset from pin-reset detected 0 0 NotDetected Not detected 0 Detected Detected 1 DOG Reset from watchdog detected 1 1 NotDetected Not detected 0 Detected Detected 1 SREQ Reset from soft reset detected 2 2 NotDetected Not detected 0 Detected Detected 1 LOCKUP Reset from CPU lock-up detected 3 3 NotDetected Not detected 0 Detected Detected 1 OFF Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO 16 16 NotDetected Not detected 0 Detected Detected 1 LPCOMP Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP 17 17 NotDetected Not detected 0 Detected Detected 1 DIF Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode 18 18 NotDetected Not detected 0 Detected Detected 1 NFC Reset due to wake up from System OFF mode by NFC field detect 19 19 NotDetected Not detected 0 Detected Detected 1 VBUS Reset due to wake up from System OFF mode by VBUS rising into valid range 20 20 NotDetected Not detected 0 Detected Detected 1 RAMSTATUS Deprecated register - RAM status register 0x428 read-only 0x00000000 RAMBLOCK0 RAM block 0 is on or off/powering up 0 0 Off Off 0 On On 1 RAMBLOCK1 RAM block 1 is on or off/powering up 1 1 Off Off 0 On On 1 RAMBLOCK2 RAM block 2 is on or off/powering up 2 2 Off Off 0 On On 1 RAMBLOCK3 RAM block 3 is on or off/powering up 3 3 Off Off 0 On On 1 USBREGSTATUS USB supply status 0x438 read-only 0x00000000 VBUSDETECT VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information) 0 0 NoVbus VBUS voltage below valid threshold 0 VbusPresent VBUS voltage above valid threshold 1 OUTPUTRDY USB supply output settling time elapsed 1 1 NotReady USBREG output settling time not elapsed 0 Ready USBREG output settling time elapsed (same information as USBPWRRDY event) 1 SYSTEMOFF System OFF register 0x500 write-only SYSTEMOFF Enable System OFF mode 0 0 Enter Enable System OFF mode 1 POFCON Power-fail comparator configuration 0x510 read-write POF Enable or disable power failure warning 0 0 Disabled Disable 0 Enabled Enable 1 THRESHOLD Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages. 1 4 V17 Set threshold to 1.7 V 4 V18 Set threshold to 1.8 V 5 V19 Set threshold to 1.9 V 6 V20 Set threshold to 2.0 V 7 V21 Set threshold to 2.1 V 8 V22 Set threshold to 2.2 V 9 V23 Set threshold to 2.3 V 10 V24 Set threshold to 2.4 V 11 V25 Set threshold to 2.5 V 12 V26 Set threshold to 2.6 V 13 V27 Set threshold to 2.7 V 14 V28 Set threshold to 2.8 V 15 THRESHOLDVDDH Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH). 8 11 V27 Set threshold to 2.7 V 0 V28 Set threshold to 2.8 V 1 V29 Set threshold to 2.9 V 2 V30 Set threshold to 3.0 V 3 V31 Set threshold to 3.1 V 4 V32 Set threshold to 3.2 V 5 V33 Set threshold to 3.3 V 6 V34 Set threshold to 3.4 V 7 V35 Set threshold to 3.5 V 8 V36 Set threshold to 3.6 V 9 V37 Set threshold to 3.7 V 10 V38 Set threshold to 3.8 V 11 V39 Set threshold to 3.9 V 12 V40 Set threshold to 4.0 V 13 V41 Set threshold to 4.1 V 14 V42 Set threshold to 4.2 V 15 GPREGRET General purpose retention register 0x51C read-write GPREGRET General purpose retention register 0 7 GPREGRET2 General purpose retention register 0x520 read-write GPREGRET General purpose retention register 0 7 DCDCEN Enable DC/DC converter for REG1 stage. 0x578 read-write DCDCEN Enable DC/DC converter for REG1 stage. 0 0 Disabled Disable 0 Enabled Enable 1 DCDCEN0 Enable DC/DC converter for REG0 stage. 0x580 read-write DCDCEN Enable DC/DC converter for REG0 stage. 0 0 Disabled Disable 0 Enabled Enable 1 MAINREGSTATUS Main supply status 0x640 read-only 0x00000000 MAINREGSTATUS Main supply status 0 0 Normal Normal voltage mode. Voltage supplied on VDD. 0 High High voltage mode. Voltage supplied on VDDH. 1 9 0x010 RAM[%s] Unspecified POWER_RAM 0x900 POWER Description cluster[n]: RAMn power control register 0x000 read-write 0x0000FFFF S0POWER Keep RAM section S0 on or off in System ON mode. 0 0 Off Off 0 On On 1 S1POWER Keep RAM section S1 on or off in System ON mode. 1 1 Off Off 0 On On 1 S2POWER Keep RAM section S2 on or off in System ON mode. 2 2 Off Off 0 On On 1 S3POWER Keep RAM section S3 on or off in System ON mode. 3 3 Off Off 0 On On 1 S4POWER Keep RAM section S4 on or off in System ON mode. 4 4 Off Off 0 On On 1 S5POWER Keep RAM section S5 on or off in System ON mode. 5 5 Off Off 0 On On 1 S6POWER Keep RAM section S6 on or off in System ON mode. 6 6 Off Off 0 On On 1 S7POWER Keep RAM section S7 on or off in System ON mode. 7 7 Off Off 0 On On 1 S8POWER Keep RAM section S8 on or off in System ON mode. 8 8 Off Off 0 On On 1 S9POWER Keep RAM section S9 on or off in System ON mode. 9 9 Off Off 0 On On 1 S10POWER Keep RAM section S10 on or off in System ON mode. 10 10 Off Off 0 On On 1 S11POWER Keep RAM section S11 on or off in System ON mode. 11 11 Off Off 0 On On 1 S12POWER Keep RAM section S12 on or off in System ON mode. 12 12 Off Off 0 On On 1 S13POWER Keep RAM section S13 on or off in System ON mode. 13 13 Off Off 0 On On 1 S14POWER Keep RAM section S14 on or off in System ON mode. 14 14 Off Off 0 On On 1 S15POWER Keep RAM section S15 on or off in System ON mode. 15 15 Off Off 0 On On 1 S0RETENTION Keep retention on RAM section S0 when RAM section is off 16 16 Off Off 0 On On 1 S1RETENTION Keep retention on RAM section S1 when RAM section is off 17 17 Off Off 0 On On 1 S2RETENTION Keep retention on RAM section S2 when RAM section is off 18 18 Off Off 0 On On 1 S3RETENTION Keep retention on RAM section S3 when RAM section is off 19 19 Off Off 0 On On 1 S4RETENTION Keep retention on RAM section S4 when RAM section is off 20 20 Off Off 0 On On 1 S5RETENTION Keep retention on RAM section S5 when RAM section is off 21 21 Off Off 0 On On 1 S6RETENTION Keep retention on RAM section S6 when RAM section is off 22 22 Off Off 0 On On 1 S7RETENTION Keep retention on RAM section S7 when RAM section is off 23 23 Off Off 0 On On 1 S8RETENTION Keep retention on RAM section S8 when RAM section is off 24 24 Off Off 0 On On 1 S9RETENTION Keep retention on RAM section S9 when RAM section is off 25 25 Off Off 0 On On 1 S10RETENTION Keep retention on RAM section S10 when RAM section is off 26 26 Off Off 0 On On 1 S11RETENTION Keep retention on RAM section S11 when RAM section is off 27 27 Off Off 0 On On 1 S12RETENTION Keep retention on RAM section S12 when RAM section is off 28 28 Off Off 0 On On 1 S13RETENTION Keep retention on RAM section S13 when RAM section is off 29 29 Off Off 0 On On 1 S14RETENTION Keep retention on RAM section S14 when RAM section is off 30 30 Off Off 0 On On 1 S15RETENTION Keep retention on RAM section S15 when RAM section is off 31 31 Off Off 0 On On 1 POWERSET Description cluster[n]: RAMn power control set register 0x004 write-only 0x0000FFFF S0POWER Keep RAM section S0 of RAMn on or off in System ON mode 0 0 On On 1 S1POWER Keep RAM section S1 of RAMn on or off in System ON mode 1 1 On On 1 S2POWER Keep RAM section S2 of RAMn on or off in System ON mode 2 2 On On 1 S3POWER Keep RAM section S3 of RAMn on or off in System ON mode 3 3 On On 1 S4POWER Keep RAM section S4 of RAMn on or off in System ON mode 4 4 On On 1 S5POWER Keep RAM section S5 of RAMn on or off in System ON mode 5 5 On On 1 S6POWER Keep RAM section S6 of RAMn on or off in System ON mode 6 6 On On 1 S7POWER Keep RAM section S7 of RAMn on or off in System ON mode 7 7 On On 1 S8POWER Keep RAM section S8 of RAMn on or off in System ON mode 8 8 On On 1 S9POWER Keep RAM section S9 of RAMn on or off in System ON mode 9 9 On On 1 S10POWER Keep RAM section S10 of RAMn on or off in System ON mode 10 10 On On 1 S11POWER Keep RAM section S11 of RAMn on or off in System ON mode 11 11 On On 1 S12POWER Keep RAM section S12 of RAMn on or off in System ON mode 12 12 On On 1 S13POWER Keep RAM section S13 of RAMn on or off in System ON mode 13 13 On On 1 S14POWER Keep RAM section S14 of RAMn on or off in System ON mode 14 14 On On 1 S15POWER Keep RAM section S15 of RAMn on or off in System ON mode 15 15 On On 1 S0RETENTION Keep retention on RAM section S0 when RAM section is switched off 16 16 On On 1 S1RETENTION Keep retention on RAM section S1 when RAM section is switched off 17 17 On On 1 S2RETENTION Keep retention on RAM section S2 when RAM section is switched off 18 18 On On 1 S3RETENTION Keep retention on RAM section S3 when RAM section is switched off 19 19 On On 1 S4RETENTION Keep retention on RAM section S4 when RAM section is switched off 20 20 On On 1 S5RETENTION Keep retention on RAM section S5 when RAM section is switched off 21 21 On On 1 S6RETENTION Keep retention on RAM section S6 when RAM section is switched off 22 22 On On 1 S7RETENTION Keep retention on RAM section S7 when RAM section is switched off 23 23 On On 1 S8RETENTION Keep retention on RAM section S8 when RAM section is switched off 24 24 On On 1 S9RETENTION Keep retention on RAM section S9 when RAM section is switched off 25 25 On On 1 S10RETENTION Keep retention on RAM section S10 when RAM section is switched off 26 26 On On 1 S11RETENTION Keep retention on RAM section S11 when RAM section is switched off 27 27 On On 1 S12RETENTION Keep retention on RAM section S12 when RAM section is switched off 28 28 On On 1 S13RETENTION Keep retention on RAM section S13 when RAM section is switched off 29 29 On On 1 S14RETENTION Keep retention on RAM section S14 when RAM section is switched off 30 30 On On 1 S15RETENTION Keep retention on RAM section S15 when RAM section is switched off 31 31 On On 1 POWERCLR Description cluster[n]: RAMn power control clear register 0x008 write-only 0x0000FFFF S0POWER Keep RAM section S0 of RAMn on or off in System ON mode 0 0 Off Off 1 S1POWER Keep RAM section S1 of RAMn on or off in System ON mode 1 1 Off Off 1 S2POWER Keep RAM section S2 of RAMn on or off in System ON mode 2 2 Off Off 1 S3POWER Keep RAM section S3 of RAMn on or off in System ON mode 3 3 Off Off 1 S4POWER Keep RAM section S4 of RAMn on or off in System ON mode 4 4 Off Off 1 S5POWER Keep RAM section S5 of RAMn on or off in System ON mode 5 5 Off Off 1 S6POWER Keep RAM section S6 of RAMn on or off in System ON mode 6 6 Off Off 1 S7POWER Keep RAM section S7 of RAMn on or off in System ON mode 7 7 Off Off 1 S8POWER Keep RAM section S8 of RAMn on or off in System ON mode 8 8 Off Off 1 S9POWER Keep RAM section S9 of RAMn on or off in System ON mode 9 9 Off Off 1 S10POWER Keep RAM section S10 of RAMn on or off in System ON mode 10 10 Off Off 1 S11POWER Keep RAM section S11 of RAMn on or off in System ON mode 11 11 Off Off 1 S12POWER Keep RAM section S12 of RAMn on or off in System ON mode 12 12 Off Off 1 S13POWER Keep RAM section S13 of RAMn on or off in System ON mode 13 13 Off Off 1 S14POWER Keep RAM section S14 of RAMn on or off in System ON mode 14 14 Off Off 1 S15POWER Keep RAM section S15 of RAMn on or off in System ON mode 15 15 Off Off 1 S0RETENTION Keep retention on RAM section S0 when RAM section is switched off 16 16 Off Off 1 S1RETENTION Keep retention on RAM section S1 when RAM section is switched off 17 17 Off Off 1 S2RETENTION Keep retention on RAM section S2 when RAM section is switched off 18 18 Off Off 1 S3RETENTION Keep retention on RAM section S3 when RAM section is switched off 19 19 Off Off 1 S4RETENTION Keep retention on RAM section S4 when RAM section is switched off 20 20 Off Off 1 S5RETENTION Keep retention on RAM section S5 when RAM section is switched off 21 21 Off Off 1 S6RETENTION Keep retention on RAM section S6 when RAM section is switched off 22 22 Off Off 1 S7RETENTION Keep retention on RAM section S7 when RAM section is switched off 23 23 Off Off 1 S8RETENTION Keep retention on RAM section S8 when RAM section is switched off 24 24 Off Off 1 S9RETENTION Keep retention on RAM section S9 when RAM section is switched off 25 25 Off Off 1 S10RETENTION Keep retention on RAM section S10 when RAM section is switched off 26 26 Off Off 1 S11RETENTION Keep retention on RAM section S11 when RAM section is switched off 27 27 Off Off 1 S12RETENTION Keep retention on RAM section S12 when RAM section is switched off 28 28 Off Off 1 S13RETENTION Keep retention on RAM section S13 when RAM section is switched off 29 29 Off Off 1 S14RETENTION Keep retention on RAM section S14 when RAM section is switched off 30 30 Off Off 1 S15RETENTION Keep retention on RAM section S15 when RAM section is switched off 31 31 Off Off 1 RADIO 2.4 GHz radio 0x40001000 0 0x1000 registers RADIO 1 RADIO 0x20 TASKS_TXEN Enable RADIO in TX mode 0x000 write-only TASKS_TXEN 0 0 TASKS_RXEN Enable RADIO in RX mode 0x004 write-only TASKS_RXEN 0 0 TASKS_START Start RADIO 0x008 write-only TASKS_START 0 0 TASKS_STOP Stop RADIO 0x00C write-only TASKS_STOP 0 0 TASKS_DISABLE Disable RADIO 0x010 write-only TASKS_DISABLE 0 0 TASKS_RSSISTART Start the RSSI and take one single sample of the receive signal strength 0x014 write-only TASKS_RSSISTART 0 0 TASKS_RSSISTOP Stop the RSSI measurement 0x018 write-only TASKS_RSSISTOP 0 0 TASKS_BCSTART Start the bit counter 0x01C write-only TASKS_BCSTART 0 0 TASKS_BCSTOP Stop the bit counter 0x020 write-only TASKS_BCSTOP 0 0 TASKS_EDSTART Start the energy detect measurement used in IEEE 802.15.4 mode 0x024 write-only TASKS_EDSTART 0 0 TASKS_EDSTOP Stop the energy detect measurement 0x028 write-only TASKS_EDSTOP 0 0 TASKS_CCASTART Start the clear channel assessment used in IEEE 802.15.4 mode 0x02C write-only TASKS_CCASTART 0 0 TASKS_CCASTOP Stop the clear channel assessment 0x030 write-only TASKS_CCASTOP 0 0 EVENTS_READY RADIO has ramped up and is ready to be started 0x100 read-write EVENTS_READY 0 0 EVENTS_ADDRESS Address sent or received 0x104 read-write EVENTS_ADDRESS 0 0 EVENTS_PAYLOAD Packet payload sent or received 0x108 read-write EVENTS_PAYLOAD 0 0 EVENTS_END Packet sent or received 0x10C read-write EVENTS_END 0 0 EVENTS_DISABLED RADIO has been disabled 0x110 read-write EVENTS_DISABLED 0 0 EVENTS_DEVMATCH A device address match occurred on the last received packet 0x114 read-write EVENTS_DEVMATCH 0 0 EVENTS_DEVMISS No device address match occurred on the last received packet 0x118 read-write EVENTS_DEVMISS 0 0 EVENTS_RSSIEND Sampling of receive signal strength complete 0x11C read-write EVENTS_RSSIEND 0 0 EVENTS_BCMATCH Bit counter reached bit count value 0x128 read-write EVENTS_BCMATCH 0 0 EVENTS_CRCOK Packet received with CRC ok 0x130 read-write EVENTS_CRCOK 0 0 EVENTS_CRCERROR Packet received with CRC error 0x134 read-write EVENTS_CRCERROR 0 0 EVENTS_FRAMESTART IEEE 802.15.4 length field received 0x138 read-write EVENTS_FRAMESTART 0 0 EVENTS_EDEND Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register. 0x13C read-write EVENTS_EDEND 0 0 EVENTS_EDSTOPPED The sampling of energy detection has stopped 0x140 read-write EVENTS_EDSTOPPED 0 0 EVENTS_CCAIDLE Wireless medium in idle - clear to send 0x144 read-write EVENTS_CCAIDLE 0 0 EVENTS_CCABUSY Wireless medium busy - do not send 0x148 read-write EVENTS_CCABUSY 0 0 EVENTS_CCASTOPPED The CCA has stopped 0x14C read-write EVENTS_CCASTOPPED 0 0 EVENTS_RATEBOOST Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit. 0x150 read-write EVENTS_RATEBOOST 0 0 EVENTS_TXREADY RADIO has ramped up and is ready to be started TX path 0x154 read-write EVENTS_TXREADY 0 0 EVENTS_RXREADY RADIO has ramped up and is ready to be started RX path 0x158 read-write EVENTS_RXREADY 0 0 EVENTS_MHRMATCH MAC header match found 0x15C read-write EVENTS_MHRMATCH 0 0 EVENTS_PHYEND Generated in Ble_LR125Kbit, Ble_LR500Kbit and BleIeee802154_250Kbit modes when last bit is sent on air. 0x16C read-write EVENTS_PHYEND 0 0 SHORTS Shortcut register 0x200 read-write READY_START Shortcut between READY event and START task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 END_DISABLE Shortcut between END event and DISABLE task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DISABLED_TXEN Shortcut between DISABLED event and TXEN task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DISABLED_RXEN Shortcut between DISABLED event and RXEN task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ADDRESS_RSSISTART Shortcut between ADDRESS event and RSSISTART task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 END_START Shortcut between END event and START task 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ADDRESS_BCSTART Shortcut between ADDRESS event and BCSTART task 6 6 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DISABLED_RSSISTOP Shortcut between DISABLED event and RSSISTOP task 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 RXREADY_CCASTART Shortcut between RXREADY event and CCASTART task 11 11 Disabled Disable shortcut 0 Enabled Enable shortcut 1 CCAIDLE_TXEN Shortcut between CCAIDLE event and TXEN task 12 12 Disabled Disable shortcut 0 Enabled Enable shortcut 1 CCABUSY_DISABLE Shortcut between CCABUSY event and DISABLE task 13 13 Disabled Disable shortcut 0 Enabled Enable shortcut 1 FRAMESTART_BCSTART Shortcut between FRAMESTART event and BCSTART task 14 14 Disabled Disable shortcut 0 Enabled Enable shortcut 1 READY_EDSTART Shortcut between READY event and EDSTART task 15 15 Disabled Disable shortcut 0 Enabled Enable shortcut 1 EDEND_DISABLE Shortcut between EDEND event and DISABLE task 16 16 Disabled Disable shortcut 0 Enabled Enable shortcut 1 CCAIDLE_STOP Shortcut between CCAIDLE event and STOP task 17 17 Disabled Disable shortcut 0 Enabled Enable shortcut 1 TXREADY_START Shortcut between TXREADY event and START task 18 18 Disabled Disable shortcut 0 Enabled Enable shortcut 1 RXREADY_START Shortcut between RXREADY event and START task 19 19 Disabled Disable shortcut 0 Enabled Enable shortcut 1 PHYEND_DISABLE Shortcut between PHYEND event and DISABLE task 20 20 Disabled Disable shortcut 0 Enabled Enable shortcut 1 PHYEND_START Shortcut between PHYEND event and START task 21 21 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ADDRESS Write '1' to enable interrupt for ADDRESS event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PAYLOAD Write '1' to enable interrupt for PAYLOAD event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for END event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DISABLED Write '1' to enable interrupt for DISABLED event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DEVMATCH Write '1' to enable interrupt for DEVMATCH event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DEVMISS Write '1' to enable interrupt for DEVMISS event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RSSIEND Write '1' to enable interrupt for RSSIEND event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 BCMATCH Write '1' to enable interrupt for BCMATCH event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CRCOK Write '1' to enable interrupt for CRCOK event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CRCERROR Write '1' to enable interrupt for CRCERROR event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 FRAMESTART Write '1' to enable interrupt for FRAMESTART event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EDEND Write '1' to enable interrupt for EDEND event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EDSTOPPED Write '1' to enable interrupt for EDSTOPPED event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CCAIDLE Write '1' to enable interrupt for CCAIDLE event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CCABUSY Write '1' to enable interrupt for CCABUSY event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CCASTOPPED Write '1' to enable interrupt for CCASTOPPED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RATEBOOST Write '1' to enable interrupt for RATEBOOST event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXREADY Write '1' to enable interrupt for TXREADY event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXREADY Write '1' to enable interrupt for RXREADY event 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 MHRMATCH Write '1' to enable interrupt for MHRMATCH event 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PHYEND Write '1' to enable interrupt for PHYEND event 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ADDRESS Write '1' to disable interrupt for ADDRESS event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PAYLOAD Write '1' to disable interrupt for PAYLOAD event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for END event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DISABLED Write '1' to disable interrupt for DISABLED event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DEVMATCH Write '1' to disable interrupt for DEVMATCH event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DEVMISS Write '1' to disable interrupt for DEVMISS event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RSSIEND Write '1' to disable interrupt for RSSIEND event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 BCMATCH Write '1' to disable interrupt for BCMATCH event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CRCOK Write '1' to disable interrupt for CRCOK event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CRCERROR Write '1' to disable interrupt for CRCERROR event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 FRAMESTART Write '1' to disable interrupt for FRAMESTART event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EDEND Write '1' to disable interrupt for EDEND event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EDSTOPPED Write '1' to disable interrupt for EDSTOPPED event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CCAIDLE Write '1' to disable interrupt for CCAIDLE event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CCABUSY Write '1' to disable interrupt for CCABUSY event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CCASTOPPED Write '1' to disable interrupt for CCASTOPPED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RATEBOOST Write '1' to disable interrupt for RATEBOOST event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXREADY Write '1' to disable interrupt for TXREADY event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXREADY Write '1' to disable interrupt for RXREADY event 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 MHRMATCH Write '1' to disable interrupt for MHRMATCH event 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PHYEND Write '1' to disable interrupt for PHYEND event 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CRCSTATUS CRC status 0x400 read-only CRCSTATUS CRC status of packet received 0 0 CRCError Packet received with CRC error 0 CRCOk Packet received with CRC ok 1 RXMATCH Received address 0x408 read-only RXMATCH Received address 0 2 RXCRC CRC field of previously received packet 0x40C read-only RXCRC CRC field of previously received packet 0 23 DAI Device address match index 0x410 read-only DAI Device address match index 0 2 PDUSTAT Payload status 0x414 read-only PDUSTAT Status on payload length vs. PCNF1.MAXLEN 0 0 LessThan Payload less than PCNF1.MAXLEN 0 GreaterThan Payload greater than PCNF1.MAXLEN 1 CISTAT Status on what rate packet is received with in Long Range 1 2 LR125kbit Frame is received at 125kbps 0 LR500kbit Frame is received at 500kbps 1 PACKETPTR Packet pointer 0x504 read-write PACKETPTR Packet pointer 0 31 FREQUENCY Frequency 0x508 read-write 0x00000002 FREQUENCY Radio channel frequency 0 6 MAP Channel map selection. 8 8 Default Channel map between 2400 MHZ .. 2500 MHz 0 Low Channel map between 2360 MHZ .. 2460 MHz 1 TXPOWER Output power 0x50C read-write TXPOWER RADIO output power 0 7 Pos8dBm +8 dBm 0x8 Pos7dBm +7 dBm 0x7 Pos6dBm +6 dBm 0x6 Pos5dBm +5 dBm 0x5 Pos4dBm +4 dBm 0x4 Pos3dBm +3 dBm 0x3 Pos2dBm +2 dBm 0x2 0dBm 0 dBm 0x0 Neg4dBm -4 dBm 0xFC Neg8dBm -8 dBm 0xF8 Neg12dBm -12 dBm 0xF4 Neg16dBm -16 dBm 0xF0 Neg20dBm -20 dBm 0xEC Neg30dBm Deprecated enumerator - -40 dBm 0xFF Neg40dBm -40 dBm 0xD8 MODE Data rate and modulation 0x510 read-write MODE Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation. 0 3 Nrf_1Mbit 1 Mbit/s Nordic proprietary radio mode 0 Nrf_2Mbit 2 Mbit/s Nordic proprietary radio mode 1 Ble_1Mbit 1 Mbit/s BLE 3 Ble_2Mbit 2 Mbit/s BLE 4 Ble_LR125Kbit Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX 5 Ble_LR500Kbit Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX 6 Ieee802154_250Kbit IEEE 802.15.4-2006 250 kbit/s 15 PCNF0 Packet configuration register 0 0x514 read-write LFLEN Length on air of LENGTH field in number of bits. 0 3 S0LEN Length on air of S0 field in number of bytes. 8 8 S1LEN Length on air of S1 field in number of bits. 16 19 S1INCL Include or exclude S1 field in RAM 20 20 Automatic Include S1 field in RAM only if S1LEN > 0 0 Include Always include S1 field in RAM independent of S1LEN 1 CILEN Length of code indicator - long range 22 23 PLEN Length of preamble on air. Decision point: TASKS_START task 24 25 8bit 8-bit preamble 0 16bit 16-bit preamble 1 32bitZero 32-bit zero preamble - used for IEEE 802.15.4 2 LongRange Preamble - used for BLE long range 3 CRCINC Indicates if LENGTH field contains CRC or not 26 26 Exclude LENGTH does not contain CRC 0 Include LENGTH includes CRC 1 TERMLEN Length of TERM field in Long Range operation 29 30 PCNF1 Packet configuration register 1 0x518 read-write MAXLEN Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. 0 7 STATLEN Static length in number of bytes 8 15 BALEN Base address length in number of bytes 16 18 ENDIAN On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. 24 24 Little Least significant bit on air first 0 Big Most significant bit on air first 1 WHITEEN Enable or disable packet whitening 25 25 Disabled Disable 0 Enabled Enable 1 BASE0 Base address 0 0x51C read-write BASE0 Base address 0 0 31 BASE1 Base address 1 0x520 read-write BASE1 Base address 1 0 31 PREFIX0 Prefixes bytes for logical addresses 0-3 0x524 read-write AP0 Address prefix 0. 0 7 AP1 Address prefix 1. 8 15 AP2 Address prefix 2. 16 23 AP3 Address prefix 3. 24 31 PREFIX1 Prefixes bytes for logical addresses 4-7 0x528 read-write AP4 Address prefix 4. 0 7 AP5 Address prefix 5. 8 15 AP6 Address prefix 6. 16 23 AP7 Address prefix 7. 24 31 TXADDRESS Transmit address select 0x52C read-write TXADDRESS Transmit address select 0 2 RXADDRESSES Receive address select 0x530 read-write ADDR0 Enable or disable reception on logical address 0. 0 0 Disabled Disable 0 Enabled Enable 1 ADDR1 Enable or disable reception on logical address 1. 1 1 Disabled Disable 0 Enabled Enable 1 ADDR2 Enable or disable reception on logical address 2. 2 2 Disabled Disable 0 Enabled Enable 1 ADDR3 Enable or disable reception on logical address 3. 3 3 Disabled Disable 0 Enabled Enable 1 ADDR4 Enable or disable reception on logical address 4. 4 4 Disabled Disable 0 Enabled Enable 1 ADDR5 Enable or disable reception on logical address 5. 5 5 Disabled Disable 0 Enabled Enable 1 ADDR6 Enable or disable reception on logical address 6. 6 6 Disabled Disable 0 Enabled Enable 1 ADDR7 Enable or disable reception on logical address 7. 7 7 Disabled Disable 0 Enabled Enable 1 CRCCNF CRC configuration 0x534 read-write LEN CRC length in number of bytes. 0 1 Disabled CRC length is zero and CRC calculation is disabled 0 One CRC length is one byte and CRC calculation is enabled 1 Two CRC length is two bytes and CRC calculation is enabled 2 Three CRC length is three bytes and CRC calculation is enabled 3 SKIPADDR Include or exclude packet address field out of CRC calculation. 8 9 Include CRC calculation includes address field 0 Skip CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. 1 Ieee802154 CRC calculation as per 802.15.4 standard. Starting at first byte after length field. 2 CRCPOLY CRC polynomial 0x538 read-write 0x00000000 CRCPOLY CRC polynomial 0 23 CRCINIT CRC initial value 0x53C read-write CRCINIT CRC initial value 0 23 TIFS Interframe spacing in us 0x544 read-write TIFS Interframe spacing in us 0 9 RSSISAMPLE RSSI sample 0x548 read-only RSSISAMPLE RSSI sample 0 6 STATE Current radio state 0x550 read-only STATE Current radio state 0 3 Disabled RADIO is in the Disabled state 0 RxRu RADIO is in the RXRU state 1 RxIdle RADIO is in the RXIDLE state 2 Rx RADIO is in the RX state 3 RxDisable RADIO is in the RXDISABLED state 4 TxRu RADIO is in the TXRU state 9 TxIdle RADIO is in the TXIDLE state 10 Tx RADIO is in the TX state 11 TxDisable RADIO is in the TXDISABLED state 12 DATAWHITEIV Data whitening initial value 0x554 read-write 0x00000040 DATAWHITEIV Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. 0 6 BCC Bit counter compare 0x560 read-write BCC Bit counter compare 0 31 0x8 0x4 DAB[%s] Description collection[n]: Device address base segment n 0x600 read-write DAB Device address base segment n 0 31 0x8 0x4 DAP[%s] Description collection[n]: Device address prefix n 0x620 read-write DAP Device address prefix n 0 15 DACNF Device address match configuration 0x640 read-write ENA0 Enable or disable device address matching using device address 0 0 0 Disabled Disabled 0 Enabled Enabled 1 ENA1 Enable or disable device address matching using device address 1 1 1 Disabled Disabled 0 Enabled Enabled 1 ENA2 Enable or disable device address matching using device address 2 2 2 Disabled Disabled 0 Enabled Enabled 1 ENA3 Enable or disable device address matching using device address 3 3 3 Disabled Disabled 0 Enabled Enabled 1 ENA4 Enable or disable device address matching using device address 4 4 4 Disabled Disabled 0 Enabled Enabled 1 ENA5 Enable or disable device address matching using device address 5 5 5 Disabled Disabled 0 Enabled Enabled 1 ENA6 Enable or disable device address matching using device address 6 6 6 Disabled Disabled 0 Enabled Enabled 1 ENA7 Enable or disable device address matching using device address 7 7 7 Disabled Disabled 0 Enabled Enabled 1 TXADD0 TxAdd for device address 0 8 8 TXADD1 TxAdd for device address 1 9 9 TXADD2 TxAdd for device address 2 10 10 TXADD3 TxAdd for device address 3 11 11 TXADD4 TxAdd for device address 4 12 12 TXADD5 TxAdd for device address 5 13 13 TXADD6 TxAdd for device address 6 14 14 TXADD7 TxAdd for device address 7 15 15 MHRMATCHCONF Search pattern configuration 0x644 read-write MHRMATCHMAS Pattern mask 0x648 read-write MODECNF0 Radio mode configuration register 0 0x650 read-write 0x00000200 RU Radio ramp-up time 0 0 Default Default ramp-up time (tRXEN), compatible with firmware written for nRF51 0 Fast Fast ramp-up (tRXEN,FAST), see electrical specification for more information 1 DTX Default TX value 8 9 B1 Transmit '1' 0 B0 Transmit '0' 1 Center Transmit center frequency 2 SFD IEEE 802.15.4 start of frame delimiter 0x660 read-write 0x000000A7 SFD IEEE 802.15.4 start of frame delimiter 0 7 EDCNT IEEE 802.15.4 energy detect loop count 0x664 read-write 0x00000000 EDCNT IEEE 802.15.4 energy detect loop count 0 20 EDSAMPLE IEEE 802.15.4 energy detect level 0x668 read-write 0x00000000 EDLVL IEEE 802.15.4 energy detect level 0 7 CCACTRL IEEE 802.15.4 clear channel assessment control 0x66C read-write 0x00000000 CCAMODE CCA mode of operation 0 2 EdMode Energy above threshold 0 CarrierMode Carrier seen 1 CarrierAndEdMode Energy above threshold AND carrier seen 2 CarrierOrEdMode Energy above threshold OR carrier seen 3 EdModeTest1 Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging. 4 CCAEDTHRES CCA energy busy threshold. Used in all the CCA modes except CarrierMode. 8 15 CCACORRTHRES CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode. 16 23 CCACORRCNT Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled. 24 31 POWER Peripheral power control 0xFFC read-write 0x00000001 POWER Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. 0 0 Disabled Peripheral is powered off 0 Enabled Peripheral is powered on 1 UART0 Universal Asynchronous Receiver/Transmitter 0x40002000 UART 0 0x1000 registers UARTE0_UART0 2 UART 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only TASKS_STARTRX 0 0 TASKS_STOPRX Stop UART receiver 0x004 write-only TASKS_STOPRX 0 0 TASKS_STARTTX Start UART transmitter 0x008 write-only TASKS_STARTTX 0 0 TASKS_STOPTX Stop UART transmitter 0x00C write-only TASKS_STOPTX 0 0 TASKS_SUSPEND Suspend UART 0x01C write-only TASKS_SUSPEND 0 0 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write EVENTS_CTS 0 0 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write EVENTS_NCTS 0 0 EVENTS_RXDRDY Data received in RXD 0x108 read-write EVENTS_RXDRDY 0 0 EVENTS_TXDRDY Data sent from TXD 0x11C read-write EVENTS_TXDRDY 0 0 EVENTS_ERROR Error detected 0x124 read-write EVENTS_ERROR 0 0 EVENTS_RXTO Receiver timeout 0x144 read-write EVENTS_RXTO 0 0 SHORTS Shortcut register 0x200 read-write CTS_STARTRX Shortcut between CTS event and STARTRX task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 NCTS_STOPRX Shortcut between NCTS event and STOPRX task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write CTS Write '1' to enable interrupt for CTS event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NCTS Write '1' to enable interrupt for NCTS event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXDRDY Write '1' to enable interrupt for RXDRDY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXDRDY Write '1' to enable interrupt for TXDRDY event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXTO Write '1' to enable interrupt for RXTO event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write CTS Write '1' to disable interrupt for CTS event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NCTS Write '1' to disable interrupt for NCTS event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXDRDY Write '1' to disable interrupt for RXDRDY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXDRDY Write '1' to disable interrupt for TXDRDY event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXTO Write '1' to disable interrupt for RXTO event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x480 read-write oneToClear OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 PARITY Parity error 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0 Present Read: error present 1 BREAK Break condition 3 3 read NotPresent Read: error not present 0 Present Read: error present 1 ENABLE Enable UART 0x500 read-write ENABLE Enable or disable UART 0 3 Disabled Disable UART 0 Enabled Enable UART 4 PSEL Unspecified UART_PSEL 0x508 RTS Pin select for RTS 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TXD Pin select for TXD 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CTS Pin select for CTS 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Pin select for RXD 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD register 0x518 read-only modifyExternal RXD RX data received in previous transfers, double buffered 0 7 TXD TXD register 0x51C write-only TXD TX data to be transferred 0 7 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14414) 0x003B0000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28829) 0x0075F000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38462) 0x009D5000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57762) 0x00EBF000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115942) 0x01D7E000 Baud230400 230400 baud (actual rate: 231884) 0x03AFB000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 470588) 0x075F7000 Baud921600 921600 baud (actual rate: 941176) 0x0EBED000 Baud1M 1Mega baud 0x10000000 CONFIG Configuration of parity and hardware flow control 0x56C read-write HWFC Hardware flow control 0 0 Disabled Disabled 0 Enabled Enabled 1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include parity bit 0x7 UARTE0 UART with EasyDMA 0 0x40002000 UART0 UARTE 0 0x1000 registers UARTE0_UART0 2 UARTE 0x20 TASKS_STARTRX Start UART receiver 0x000 write-only TASKS_STARTRX 0 0 TASKS_STOPRX Stop UART receiver 0x004 write-only TASKS_STOPRX 0 0 TASKS_STARTTX Start UART transmitter 0x008 write-only TASKS_STARTTX 0 0 TASKS_STOPTX Stop UART transmitter 0x00C write-only TASKS_STOPTX 0 0 TASKS_FLUSHRX Flush RX FIFO into RX buffer 0x02C write-only TASKS_FLUSHRX 0 0 EVENTS_CTS CTS is activated (set low). Clear To Send. 0x100 read-write EVENTS_CTS 0 0 EVENTS_NCTS CTS is deactivated (set high). Not Clear To Send. 0x104 read-write EVENTS_NCTS 0 0 EVENTS_RXDRDY Data received in RXD (but potentially not yet transferred to Data RAM) 0x108 read-write EVENTS_RXDRDY 0 0 EVENTS_ENDRX Receive buffer is filled up 0x110 read-write EVENTS_ENDRX 0 0 EVENTS_TXDRDY Data sent from TXD 0x11C read-write EVENTS_TXDRDY 0 0 EVENTS_ENDTX Last TX byte transmitted 0x120 read-write EVENTS_ENDTX 0 0 EVENTS_ERROR Error detected 0x124 read-write EVENTS_ERROR 0 0 EVENTS_RXTO Receiver timeout 0x144 read-write EVENTS_RXTO 0 0 EVENTS_RXSTARTED UART receiver has started 0x14C read-write EVENTS_RXSTARTED 0 0 EVENTS_TXSTARTED UART transmitter has started 0x150 read-write EVENTS_TXSTARTED 0 0 EVENTS_TXSTOPPED Transmitter stopped 0x158 read-write EVENTS_TXSTOPPED 0 0 SHORTS Shortcut register 0x200 read-write ENDRX_STARTRX Shortcut between ENDRX event and STARTRX task 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ENDRX_STOPRX Shortcut between ENDRX event and STOPRX task 6 6 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write CTS Enable or disable interrupt for CTS event 0 0 Disabled Disable 0 Enabled Enable 1 NCTS Enable or disable interrupt for NCTS event 1 1 Disabled Disable 0 Enabled Enable 1 RXDRDY Enable or disable interrupt for RXDRDY event 2 2 Disabled Disable 0 Enabled Enable 1 ENDRX Enable or disable interrupt for ENDRX event 4 4 Disabled Disable 0 Enabled Enable 1 TXDRDY Enable or disable interrupt for TXDRDY event 7 7 Disabled Disable 0 Enabled Enable 1 ENDTX Enable or disable interrupt for ENDTX event 8 8 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for ERROR event 9 9 Disabled Disable 0 Enabled Enable 1 RXTO Enable or disable interrupt for RXTO event 17 17 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for RXSTARTED event 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for TXSTARTED event 20 20 Disabled Disable 0 Enabled Enable 1 TXSTOPPED Enable or disable interrupt for TXSTOPPED event 22 22 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write CTS Write '1' to enable interrupt for CTS event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NCTS Write '1' to enable interrupt for NCTS event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXDRDY Write '1' to enable interrupt for RXDRDY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for ENDRX event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXDRDY Write '1' to enable interrupt for TXDRDY event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDTX Write '1' to enable interrupt for ENDTX event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXTO Write '1' to enable interrupt for RXTO event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for RXSTARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for TXSTARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTOPPED Write '1' to enable interrupt for TXSTOPPED event 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write CTS Write '1' to disable interrupt for CTS event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NCTS Write '1' to disable interrupt for NCTS event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXDRDY Write '1' to disable interrupt for RXDRDY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for ENDRX event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXDRDY Write '1' to disable interrupt for TXDRDY event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDTX Write '1' to disable interrupt for ENDTX event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXTO Write '1' to disable interrupt for RXTO event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for RXSTARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for TXSTARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTOPPED Write '1' to disable interrupt for TXSTOPPED event 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source Note : this register is read / write one to clear. 0x480 read-write oneToClear OVERRUN Overrun error 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 PARITY Parity error 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 FRAMING Framing error occurred 2 2 read NotPresent Read: error not present 0 Present Read: error present 1 BREAK Break condition 3 3 read NotPresent Read: error not present 0 Present Read: error present 1 ENABLE Enable UART 0x500 read-write ENABLE Enable or disable UARTE 0 3 Disabled Disable UARTE 0 Enabled Enable UARTE 8 PSEL Unspecified UARTE_PSEL 0x508 RTS Pin select for RTS signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 TXD Pin select for TXD signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CTS Pin select for CTS signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Pin select for RXD signal 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 BAUDRATE Baud rate. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 BAUDRATE Baud rate 0 31 Baud1200 1200 baud (actual rate: 1205) 0x0004F000 Baud2400 2400 baud (actual rate: 2396) 0x0009D000 Baud4800 4800 baud (actual rate: 4808) 0x0013B000 Baud9600 9600 baud (actual rate: 9598) 0x00275000 Baud14400 14400 baud (actual rate: 14401) 0x003AF000 Baud19200 19200 baud (actual rate: 19208) 0x004EA000 Baud28800 28800 baud (actual rate: 28777) 0x0075C000 Baud31250 31250 baud 0x00800000 Baud38400 38400 baud (actual rate: 38369) 0x009D0000 Baud56000 56000 baud (actual rate: 55944) 0x00E50000 Baud57600 57600 baud (actual rate: 57554) 0x00EB0000 Baud76800 76800 baud (actual rate: 76923) 0x013A9000 Baud115200 115200 baud (actual rate: 115108) 0x01D60000 Baud230400 230400 baud (actual rate: 231884) 0x03B00000 Baud250000 250000 baud 0x04000000 Baud460800 460800 baud (actual rate: 457143) 0x07400000 Baud921600 921600 baud (actual rate: 941176) 0x0F000000 Baud1M 1Mega baud 0x10000000 RXD RXD EasyDMA channel UARTE_RXD 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 15 TXD TXD EasyDMA channel UARTE_TXD 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 15 CONFIG Configuration of parity and hardware flow control 0x56C read-write HWFC Hardware flow control 0 0 Disabled Disabled 0 Enabled Enabled 1 PARITY Parity 1 3 Excluded Exclude parity bit 0x0 Included Include even parity bit 0x7 STOP Stop bits 4 4 One One stop bit 0 Two Two stop bits 1 SPI0 Serial Peripheral Interface 0 0x40003000 SPI 0 0x1000 registers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 SPI 0x20 EVENTS_READY TXD byte sent and RXD byte received 0x108 read-write EVENTS_READY 0 0 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for READY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for READY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable SPI 0x500 read-write ENABLE Enable or disable SPI 0 3 Disabled Disable SPI 0 Enabled Enable SPI 1 PSEL Unspecified SPI_PSEL 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD register 0x518 read-only modifyExternal RXD RX data received. Double buffered 0 7 TXD TXD register 0x51C read-write TXD TX data to send. Double buffered 0 7 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 SPIM0 Serial Peripheral Interface Master with EasyDMA 0 0x40003000 SPI0 SPIM 0 0x1000 registers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 SPIM 0x20 TASKS_START Start SPI transaction 0x010 write-only TASKS_START 0 0 TASKS_STOP Stop SPI transaction 0x014 write-only TASKS_STOP 0 0 TASKS_SUSPEND Suspend SPI transaction 0x01C write-only TASKS_SUSPEND 0 0 TASKS_RESUME Resume SPI transaction 0x020 write-only TASKS_RESUME 0 0 EVENTS_STOPPED SPI transaction has stopped 0x104 read-write EVENTS_STOPPED 0 0 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write EVENTS_ENDRX 0 0 EVENTS_END End of RXD buffer and TXD buffer reached 0x118 read-write EVENTS_END 0 0 EVENTS_ENDTX End of TXD buffer reached 0x120 read-write EVENTS_ENDTX 0 0 EVENTS_STARTED Transaction started 0x14C read-write EVENTS_STARTED 0 0 SHORTS Shortcut register 0x200 read-write END_START Shortcut between END event and START task 17 17 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for ENDRX event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for END event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDTX Write '1' to enable interrupt for ENDTX event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STARTED Write '1' to enable interrupt for STARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for ENDRX event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for END event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDTX Write '1' to disable interrupt for ENDTX event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STARTED Write '1' to disable interrupt for STARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STALLSTAT Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU. 0x400 read-write 0x00000000 TX Stall status for EasyDMA RAM reads 0 0 NOSTALL No stall 0 STALL A stall has occurred 1 RX Stall status for EasyDMA RAM writes 1 1 NOSTALL No stall 0 STALL A stall has occurred 1 ENABLE Enable SPIM 0x500 read-write ENABLE Enable or disable SPIM 0 3 Disabled Disable SPIM 0 Enabled Enable SPIM 7 PSEL Unspecified SPIM_PSEL 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CSN Pin select for CSN 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 FREQUENCY SPI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY SPI master data rate 0 31 K125 125 kbps 0x02000000 K250 250 kbps 0x04000000 K500 500 kbps 0x08000000 M1 1 Mbps 0x10000000 M2 2 Mbps 0x20000000 M4 4 Mbps 0x40000000 M8 8 Mbps 0x80000000 M16 16 Mbps 0x0A000000 M32 32 Mbps 0x14000000 RXD RXD EasyDMA channel SPIM_RXD 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 15 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel SPIM_TXD 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 15 LIST EasyDMA list type 0x00C read-write LIST List type 0 1 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 IFTIMING Unspecified SPIM_IFTIMING 0x560 RXDELAY Sample delay for input serial data on MISO 0x000 read-write 0x00000002 RXDELAY Sample delay for input serial data on MISO. The value specifies the number of 64 MHz clock cycles (15.625 ns) delay from the the sampling edge of SCK (leading edge for CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until the input serial data is sampled. As en example, if RXDELAY = 0 and CONFIG.CPHA = 0, the input serial data is sampled on the rising edge of SCK. 0 2 CSNDUR Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions 0x004 read-write 0x00000002 CSNDUR Minimum duration between edge of CSN and edge of SCK and minimum duration CSN must stay high between transactions. The value is specified in number of 64 MHz clock cycles (15.625 ns). 0 7 CSNPOL Polarity of CSN output 0x568 read-write 0x00000000 CSNPOL Polarity of CSN output 0 0 LOW Active low (idle state high) 0 HIGH Active high (idle state low) 1 PSELDCX Pin select for DCX signal 0x56C read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 DCXCNT DCX configuration 0x570 read-write DCXCNT This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes. 0 3 ORC Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT 0x5C0 read-write ORC Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT. 0 7 SPIS0 SPI Slave 0 0x40003000 SPI0 SPIS 0 0x1000 registers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 SPIS 0x20 TASKS_ACQUIRE Acquire SPI semaphore 0x024 write-only TASKS_ACQUIRE 0 0 TASKS_RELEASE Release SPI semaphore, enabling the SPI slave to acquire it 0x028 write-only TASKS_RELEASE 0 0 EVENTS_END Granted transaction completed 0x104 read-write EVENTS_END 0 0 EVENTS_ENDRX End of RXD buffer reached 0x110 read-write EVENTS_ENDRX 0 0 EVENTS_ACQUIRED Semaphore acquired 0x128 read-write EVENTS_ACQUIRED 0 0 SHORTS Shortcut register 0x200 read-write END_ACQUIRE Shortcut between END event and ACQUIRE task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write END Write '1' to enable interrupt for END event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for ENDRX event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ACQUIRED Write '1' to enable interrupt for ACQUIRED event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write END Write '1' to disable interrupt for END event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for ENDRX event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ACQUIRED Write '1' to disable interrupt for ACQUIRED event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEMSTAT Semaphore status register 0x400 read-only 0x00000001 SEMSTAT Semaphore status 0 1 Free Semaphore is free 0 CPU Semaphore is assigned to CPU 1 SPIS Semaphore is assigned to SPI slave 2 CPUPending Semaphore is assigned to SPI but a handover to the CPU is pending 3 STATUS Status from last transaction 0x440 read-write OVERREAD TX buffer over-read detected, and prevented 0 0 read NotPresent Read: error not present 0 Present Read: error present 1 write Clear Write: clear error on writing '1' 1 OVERFLOW RX buffer overflow detected, and prevented 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 write Clear Write: clear error on writing '1' 1 ENABLE Enable SPI slave 0x500 read-write ENABLE Enable or disable SPI slave 0 3 Disabled Disable SPI slave 0 Enabled Enable SPI slave 2 PSEL Unspecified SPIS_PSEL 0x508 SCK Pin select for SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MISO Pin select for MISO signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 MOSI Pin select for MOSI signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CSN Pin select for CSN signal 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD Unspecified SPIS_RXD 0x534 PTR RXD data pointer 0x000 read-write PTR RXD data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes received in last granted transaction 0x008 read-only AMOUNT Number of bytes received in the last granted transaction 0 15 TXD Unspecified SPIS_TXD 0x544 PTR TXD data pointer 0x000 read-write PTR TXD data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transmitted in last granted transaction 0x008 read-only AMOUNT Number of bytes transmitted in last granted transaction 0 15 CONFIG Configuration register 0x554 read-write ORDER Bit order 0 0 MsbFirst Most significant bit shifted out first 0 LsbFirst Least significant bit shifted out first 1 CPHA Serial clock (SCK) phase 1 1 Leading Sample on leading edge of clock, shift serial data on trailing edge 0 Trailing Sample on trailing edge of clock, shift serial data on leading edge 1 CPOL Serial clock (SCK) polarity 2 2 ActiveHigh Active high 0 ActiveLow Active low 1 DEF Default character. Character clocked out in case of an ignored transaction. 0x55C read-write DEF Default character. Character clocked out in case of an ignored transaction. 0 7 ORC Over-read character 0x5C0 read-write ORC Over-read character. Character clocked out after an over-read of the transmit buffer. 0 7 TWI0 I2C compatible Two-Wire Interface 0 0x40003000 SPI0 TWI 0 0x1000 registers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 TWI 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only TASKS_STARTRX 0 0 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only TASKS_STARTTX 0 0 TASKS_STOP Stop TWI transaction 0x014 write-only TASKS_STOP 0 0 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND 0 0 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME 0 0 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED 0 0 EVENTS_RXDREADY TWI RXD byte received 0x108 read-write EVENTS_RXDREADY 0 0 EVENTS_TXDSENT TWI TXD byte sent 0x11C read-write EVENTS_TXDSENT 0 0 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR 0 0 EVENTS_BB TWI byte boundary, generated before each byte that is sent or received 0x138 read-write EVENTS_BB 0 0 EVENTS_SUSPENDED TWI entered the suspended state 0x148 read-write EVENTS_SUSPENDED 0 0 SHORTS Shortcut register 0x200 read-write BB_SUSPEND Shortcut between BB event and SUSPEND task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 BB_STOP Shortcut between BB event and STOP task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXDREADY Write '1' to enable interrupt for RXDREADY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXDSENT Write '1' to enable interrupt for TXDSENT event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 BB Write '1' to enable interrupt for BB event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SUSPENDED Write '1' to enable interrupt for SUSPENDED event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXDREADY Write '1' to disable interrupt for RXDREADY event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXDSENT Write '1' to disable interrupt for TXDSENT event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 BB Write '1' to disable interrupt for BB event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SUSPENDED Write '1' to disable interrupt for SUSPENDED event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4C4 read-write oneToClear OVERRUN Overrun error 0 0 read NotPresent Read: no overrun occured 0 Present Read: overrun occured 1 ANACK NACK received after sending the address (write '1' to clear) 1 1 read NotPresent Read: error not present 0 Present Read: error present 1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 read NotPresent Read: error not present 0 Present Read: error present 1 ENABLE Enable TWI 0x500 read-write ENABLE Enable or disable TWI 0 3 Disabled Disable TWI 0 Enabled Enable TWI 5 PSEL Unspecified TWI_PSEL 0x508 SCL Pin select for SCL 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD register 0x518 read-only modifyExternal RXD RXD register 0 7 TXD TXD register 0x51C read-write TXD TXD register 0 7 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps (actual rate 410.256 kbps) 0x06680000 ADDRESS Address used in the TWI transfer 0x588 read-write ADDRESS Address used in the TWI transfer 0 6 TWIM0 I2C compatible Two-Wire Master Interface with EasyDMA 0 0x40003000 SPI0 TWIM 0 0x1000 registers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 TWIM 0x20 TASKS_STARTRX Start TWI receive sequence 0x000 write-only TASKS_STARTRX 0 0 TASKS_STARTTX Start TWI transmit sequence 0x008 write-only TASKS_STARTTX 0 0 TASKS_STOP Stop TWI transaction. Must be issued while the TWI master is not suspended. 0x014 write-only TASKS_STOP 0 0 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND 0 0 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME 0 0 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED 0 0 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR 0 0 EVENTS_SUSPENDED Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended. 0x148 read-write EVENTS_SUSPENDED 0 0 EVENTS_RXSTARTED Receive sequence started 0x14C read-write EVENTS_RXSTARTED 0 0 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write EVENTS_TXSTARTED 0 0 EVENTS_LASTRX Byte boundary, starting to receive the last byte 0x15C read-write EVENTS_LASTRX 0 0 EVENTS_LASTTX Byte boundary, starting to transmit the last byte 0x160 read-write EVENTS_LASTTX 0 0 SHORTS Shortcut register 0x200 read-write LASTTX_STARTRX Shortcut between LASTTX event and STARTRX task 7 7 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTTX_SUSPEND Shortcut between LASTTX event and SUSPEND task 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTTX_STOP Shortcut between LASTTX event and STOP task 9 9 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_STARTTX Shortcut between LASTRX event and STARTTX task 10 10 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_SUSPEND Shortcut between LASTRX event and SUSPEND task 11 11 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LASTRX_STOP Shortcut between LASTRX event and STOP task 12 12 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for STOPPED event 1 1 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for ERROR event 9 9 Disabled Disable 0 Enabled Enable 1 SUSPENDED Enable or disable interrupt for SUSPENDED event 18 18 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for RXSTARTED event 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for TXSTARTED event 20 20 Disabled Disable 0 Enabled Enable 1 LASTRX Enable or disable interrupt for LASTRX event 23 23 Disabled Disable 0 Enabled Enable 1 LASTTX Enable or disable interrupt for LASTTX event 24 24 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SUSPENDED Write '1' to enable interrupt for SUSPENDED event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for RXSTARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for TXSTARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LASTRX Write '1' to enable interrupt for LASTRX event 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LASTTX Write '1' to enable interrupt for LASTTX event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SUSPENDED Write '1' to disable interrupt for SUSPENDED event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for RXSTARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for TXSTARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LASTRX Write '1' to disable interrupt for LASTRX event 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LASTTX Write '1' to disable interrupt for LASTTX event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4C4 read-write oneToClear OVERRUN Overrun error 0 0 NotReceived Error did not occur 0 Received Error occurred 1 ANACK NACK received after sending the address (write '1' to clear) 1 1 NotReceived Error did not occur 0 Received Error occurred 1 DNACK NACK received after sending a data byte (write '1' to clear) 2 2 NotReceived Error did not occur 0 Received Error occurred 1 ENABLE Enable TWIM 0x500 read-write ENABLE Enable or disable TWIM 0 3 Disabled Disable TWIM 0 Enabled Enable TWIM 6 PSEL Unspecified TWIM_PSEL 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 FREQUENCY TWI frequency. Accuracy depends on the HFCLK source selected. 0x524 read-write 0x04000000 FREQUENCY TWI master clock frequency 0 31 K100 100 kbps 0x01980000 K250 250 kbps 0x04000000 K400 400 kbps 0x06400000 RXD RXD EasyDMA channel TWIM_RXD 0x534 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in receive buffer 0x004 read-write MAXCNT Maximum number of bytes in receive buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 15 LIST EasyDMA list type 0x00C read-write LIST List type 0 2 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 TXD TXD EasyDMA channel TWIM_TXD 0x544 PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of bytes in transmit buffer 0x004 read-write MAXCNT Maximum number of bytes in transmit buffer 0 15 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. 0 15 LIST EasyDMA list type 0x00C read-write LIST List type 0 2 Disabled Disable EasyDMA list 0 ArrayList Use array list 1 ADDRESS Address used in the TWI transfer 0x588 read-write ADDRESS Address used in the TWI transfer 0 6 TWIS0 I2C compatible Two-Wire Slave Interface with EasyDMA 0 0x40003000 SPI0 TWIS 0 0x1000 registers SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 3 TWIS 0x20 TASKS_STOP Stop TWI transaction 0x014 write-only TASKS_STOP 0 0 TASKS_SUSPEND Suspend TWI transaction 0x01C write-only TASKS_SUSPEND 0 0 TASKS_RESUME Resume TWI transaction 0x020 write-only TASKS_RESUME 0 0 TASKS_PREPARERX Prepare the TWI slave to respond to a write command 0x030 write-only TASKS_PREPARERX 0 0 TASKS_PREPARETX Prepare the TWI slave to respond to a read command 0x034 write-only TASKS_PREPARETX 0 0 EVENTS_STOPPED TWI stopped 0x104 read-write EVENTS_STOPPED 0 0 EVENTS_ERROR TWI error 0x124 read-write EVENTS_ERROR 0 0 EVENTS_RXSTARTED Receive sequence started 0x14C read-write EVENTS_RXSTARTED 0 0 EVENTS_TXSTARTED Transmit sequence started 0x150 read-write EVENTS_TXSTARTED 0 0 EVENTS_WRITE Write command received 0x164 read-write EVENTS_WRITE 0 0 EVENTS_READ Read command received 0x168 read-write EVENTS_READ 0 0 SHORTS Shortcut register 0x200 read-write WRITE_SUSPEND Shortcut between WRITE event and SUSPEND task 13 13 Disabled Disable shortcut 0 Enabled Enable shortcut 1 READ_SUSPEND Shortcut between READ event and SUSPEND task 14 14 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for STOPPED event 1 1 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for ERROR event 9 9 Disabled Disable 0 Enabled Enable 1 RXSTARTED Enable or disable interrupt for RXSTARTED event 19 19 Disabled Disable 0 Enabled Enable 1 TXSTARTED Enable or disable interrupt for TXSTARTED event 20 20 Disabled Disable 0 Enabled Enable 1 WRITE Enable or disable interrupt for WRITE event 25 25 Disabled Disable 0 Enabled Enable 1 READ Enable or disable interrupt for READ event 26 26 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXSTARTED Write '1' to enable interrupt for RXSTARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXSTARTED Write '1' to enable interrupt for TXSTARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 WRITE Write '1' to enable interrupt for WRITE event 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 READ Write '1' to enable interrupt for READ event 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for ERROR event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXSTARTED Write '1' to disable interrupt for RXSTARTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXSTARTED Write '1' to disable interrupt for TXSTARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 WRITE Write '1' to disable interrupt for WRITE event 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 READ Write '1' to disable interrupt for READ event 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSRC Error source 0x4D0 read-write oneToClear OVERFLOW RX buffer overflow detected, and prevented 0 0 NotDetected Error did not occur 0 Detected Error occurred 1 DNACK NACK sent after receiving a data byte 2 2 NotReceived Error did not occur 0 Received Error occurred 1 OVERREAD TX buffer over-read detected, and prevented 3 3 NotDetected Error did not occur 0 Detected Error occurred 1 MATCH Status register indicating which address had a match 0x4D4 read-only MATCH Which of the addresses in {ADDRESS} matched the incoming address 0 0 ENABLE Enable TWIS 0x500 read-write ENABLE Enable or disable TWIS 0 3 Disabled Disable TWIS 0 Enabled Enable TWIS 9 PSEL Unspecified TWIS_PSEL 0x508 SCL Pin select for SCL signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDA Pin select for SDA signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 RXD RXD EasyDMA channel TWIS_RXD 0x534 PTR RXD Data pointer 0x000 read-write PTR RXD Data pointer 0 31 MAXCNT Maximum number of bytes in RXD buffer 0x004 read-write MAXCNT Maximum number of bytes in RXD buffer 0 15 AMOUNT Number of bytes transferred in the last RXD transaction 0x008 read-only AMOUNT Number of bytes transferred in the last RXD transaction 0 15 TXD TXD EasyDMA channel TWIS_TXD 0x544 PTR TXD Data pointer 0x000 read-write PTR TXD Data pointer 0 31 MAXCNT Maximum number of bytes in TXD buffer 0x004 read-write MAXCNT Maximum number of bytes in TXD buffer 0 15 AMOUNT Number of bytes transferred in the last TXD transaction 0x008 read-only AMOUNT Number of bytes transferred in the last TXD transaction 0 15 0x2 0x4 ADDRESS[%s] Description collection[n]: TWI slave address n 0x588 read-write ADDRESS TWI slave address 0 6 CONFIG Configuration register for the address match mechanism 0x594 read-write 0x00000001 ADDRESS0 Enable or disable address matching on ADDRESS[0] 0 0 Disabled Disabled 0 Enabled Enabled 1 ADDRESS1 Enable or disable address matching on ADDRESS[1] 1 1 Disabled Disabled 0 Enabled Enabled 1 ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0x5C0 read-write ORC Over-read character. Character sent out in case of an over-read of the transmit buffer. 0 7 SPI1 Serial Peripheral Interface 1 0x40004000 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 SPIM1 Serial Peripheral Interface Master with EasyDMA 1 0x40004000 SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 SPIS1 SPI Slave 1 0x40004000 SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 TWI1 I2C compatible Two-Wire Interface 1 0x40004000 SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 TWIM1 I2C compatible Two-Wire Master Interface with EasyDMA 1 0x40004000 SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 TWIS1 I2C compatible Two-Wire Slave Interface with EasyDMA 1 0x40004000 SPI1 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 4 NFCT NFC-A compatible radio 0x40005000 0 0x1000 registers NFCT 5 NFCT 0x20 TASKS_ACTIVATE Activate NFCT peripheral for incoming and outgoing frames, change state to activated 0x000 write-only TASKS_ACTIVATE 0 0 TASKS_DISABLE Disable NFCT peripheral 0x004 write-only TASKS_DISABLE 0 0 TASKS_SENSE Enable NFC sense field mode, change state to sense mode 0x008 write-only TASKS_SENSE 0 0 TASKS_STARTTX Start transmission of an outgoing frame, change state to transmit 0x00C write-only TASKS_STARTTX 0 0 TASKS_ENABLERXDATA Initializes the EasyDMA for receive. 0x01C write-only TASKS_ENABLERXDATA 0 0 TASKS_GOIDLE Force state machine to IDLE state 0x024 write-only TASKS_GOIDLE 0 0 TASKS_GOSLEEP Force state machine to SLEEP_A state 0x028 write-only TASKS_GOSLEEP 0 0 EVENTS_READY The NFCT peripheral is ready to receive and send frames 0x100 read-write EVENTS_READY 0 0 EVENTS_FIELDDETECTED Remote NFC field detected 0x104 read-write EVENTS_FIELDDETECTED 0 0 EVENTS_FIELDLOST Remote NFC field lost 0x108 read-write EVENTS_FIELDLOST 0 0 EVENTS_TXFRAMESTART Marks the start of the first symbol of a transmitted frame 0x10C read-write EVENTS_TXFRAMESTART 0 0 EVENTS_TXFRAMEEND Marks the end of the last transmitted on-air symbol of a frame 0x110 read-write EVENTS_TXFRAMEEND 0 0 EVENTS_RXFRAMESTART Marks the end of the first symbol of a received frame 0x114 read-write EVENTS_RXFRAMESTART 0 0 EVENTS_RXFRAMEEND Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer 0x118 read-write EVENTS_RXFRAMEEND 0 0 EVENTS_ERROR NFC error reported. The ERRORSTATUS register contains details on the source of the error. 0x11C read-write EVENTS_ERROR 0 0 EVENTS_RXERROR NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error. 0x128 read-write EVENTS_RXERROR 0 0 EVENTS_ENDRX RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. 0x12C read-write EVENTS_ENDRX 0 0 EVENTS_ENDTX Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer 0x130 read-write EVENTS_ENDTX 0 0 EVENTS_AUTOCOLRESSTARTED Auto collision resolution process has started 0x138 read-write EVENTS_AUTOCOLRESSTARTED 0 0 EVENTS_COLLISION NFC auto collision resolution error reported. 0x148 read-write EVENTS_COLLISION 0 0 EVENTS_SELECTED NFC auto collision resolution successfully completed 0x14C read-write EVENTS_SELECTED 0 0 EVENTS_STARTED EasyDMA is ready to receive or send frames. 0x150 read-write EVENTS_STARTED 0 0 SHORTS Shortcut register 0x200 read-write FIELDDETECTED_ACTIVATE Shortcut between FIELDDETECTED event and ACTIVATE task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 FIELDLOST_SENSE Shortcut between FIELDLOST event and SENSE task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 TXFRAMEEND_ENABLERXDATA Shortcut between TXFRAMEEND event and ENABLERXDATA task 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write READY Enable or disable interrupt for READY event 0 0 Disabled Disable 0 Enabled Enable 1 FIELDDETECTED Enable or disable interrupt for FIELDDETECTED event 1 1 Disabled Disable 0 Enabled Enable 1 FIELDLOST Enable or disable interrupt for FIELDLOST event 2 2 Disabled Disable 0 Enabled Enable 1 TXFRAMESTART Enable or disable interrupt for TXFRAMESTART event 3 3 Disabled Disable 0 Enabled Enable 1 TXFRAMEEND Enable or disable interrupt for TXFRAMEEND event 4 4 Disabled Disable 0 Enabled Enable 1 RXFRAMESTART Enable or disable interrupt for RXFRAMESTART event 5 5 Disabled Disable 0 Enabled Enable 1 RXFRAMEEND Enable or disable interrupt for RXFRAMEEND event 6 6 Disabled Disable 0 Enabled Enable 1 ERROR Enable or disable interrupt for ERROR event 7 7 Disabled Disable 0 Enabled Enable 1 RXERROR Enable or disable interrupt for RXERROR event 10 10 Disabled Disable 0 Enabled Enable 1 ENDRX Enable or disable interrupt for ENDRX event 11 11 Disabled Disable 0 Enabled Enable 1 ENDTX Enable or disable interrupt for ENDTX event 12 12 Disabled Disable 0 Enabled Enable 1 AUTOCOLRESSTARTED Enable or disable interrupt for AUTOCOLRESSTARTED event 14 14 Disabled Disable 0 Enabled Enable 1 COLLISION Enable or disable interrupt for COLLISION event 18 18 Disabled Disable 0 Enabled Enable 1 SELECTED Enable or disable interrupt for SELECTED event 19 19 Disabled Disable 0 Enabled Enable 1 STARTED Enable or disable interrupt for STARTED event 20 20 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 FIELDDETECTED Write '1' to enable interrupt for FIELDDETECTED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 FIELDLOST Write '1' to enable interrupt for FIELDLOST event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXFRAMESTART Write '1' to enable interrupt for TXFRAMESTART event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXFRAMEEND Write '1' to enable interrupt for TXFRAMEEND event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXFRAMESTART Write '1' to enable interrupt for RXFRAMESTART event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXFRAMEEND Write '1' to enable interrupt for RXFRAMEEND event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for ERROR event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RXERROR Write '1' to enable interrupt for RXERROR event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDRX Write '1' to enable interrupt for ENDRX event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDTX Write '1' to enable interrupt for ENDTX event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 AUTOCOLRESSTARTED Write '1' to enable interrupt for AUTOCOLRESSTARTED event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COLLISION Write '1' to enable interrupt for COLLISION event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SELECTED Write '1' to enable interrupt for SELECTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STARTED Write '1' to enable interrupt for STARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 FIELDDETECTED Write '1' to disable interrupt for FIELDDETECTED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 FIELDLOST Write '1' to disable interrupt for FIELDLOST event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXFRAMESTART Write '1' to disable interrupt for TXFRAMESTART event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXFRAMEEND Write '1' to disable interrupt for TXFRAMEEND event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXFRAMESTART Write '1' to disable interrupt for RXFRAMESTART event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXFRAMEEND Write '1' to disable interrupt for RXFRAMEEND event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for ERROR event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RXERROR Write '1' to disable interrupt for RXERROR event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDRX Write '1' to disable interrupt for ENDRX event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDTX Write '1' to disable interrupt for ENDTX event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 AUTOCOLRESSTARTED Write '1' to disable interrupt for AUTOCOLRESSTARTED event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COLLISION Write '1' to disable interrupt for COLLISION event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SELECTED Write '1' to disable interrupt for SELECTED event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STARTED Write '1' to disable interrupt for STARTED event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORSTATUS NFC Error Status register 0x404 read-write oneToClear FRAMEDELAYTIMEOUT No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX 0 0 FRAMESTATUS Unspecified NFCT_FRAMESTATUS 0x40C RX Result of last incoming frame 0x000 read-write oneToClear CRCERROR No valid end of frame (EoF) detected 0 0 CRCCorrect Valid CRC detected 0 CRCError CRC received does not match local check 1 PARITYSTATUS Parity status of received frame 2 2 ParityOK Frame received with parity OK 0 ParityError Frame received with parity error 1 OVERRUN Overrun detected 3 3 NoOverrun No overrun detected 0 Overrun Overrun error 1 NFCTAGSTATE NfcTag state register 0x410 read-only NFCTAGSTATE NfcTag state 0 2 Disabled Disabled or sense 0 RampUp RampUp 2 Idle Idle 3 Receive Receive 4 FrameDelay FrameDelay 5 Transmit Transmit 6 SLEEPSTATE Sleep state during automatic collision resolution 0x420 read-only 0x00000000 SLEEPSTATE Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task. 0 0 Idle State is IDLE. 0 SleepA State is SLEEP_A. 1 FIELDPRESENT Indicates the presence or not of a valid field 0x43C read-only FIELDPRESENT Indicates if a valid field is present. Available only in the activated state. 0 0 NoField No valid field detected 0 FieldPresent Valid field detected 1 LOCKDETECT Indicates if the low level has locked to the field 1 1 NotLocked Not locked to field 0 Locked Locked to field 1 FRAMEDELAYMIN Minimum frame delay 0x504 read-write 0x00000480 FRAMEDELAYMIN Minimum frame delay in number of 13.56 MHz clocks 0 15 FRAMEDELAYMAX Maximum frame delay 0x508 read-write 0x00001000 FRAMEDELAYMAX Maximum frame delay in number of 13.56 MHz clocks 0 19 FRAMEDELAYMODE Configuration register for the Frame Delay Timer 0x50C read-write 0x00000001 FRAMEDELAYMODE Configuration register for the Frame Delay Timer 0 1 FreeRun Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. 0 Window Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX 1 ExactVal Frame is transmitted exactly at FRAMEDELAYMAX 2 WindowGrid Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX 3 PACKETPTR Packet pointer for TXD and RXD data storage in Data RAM 0x510 read-write 0x00000000 PTR Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address. 0 31 MAXLEN Size of the RAM buffer allocated to TXD and RXD data storage each 0x514 read-write MAXLEN Size of the RAM buffer allocated to TXD and RXD data storage each 0 8 TXD Unspecified NFCT_TXD 0x518 FRAMECONFIG Configuration of outgoing frames 0x000 read-write 0x00000017 PARITY Indicates if parity is added to the frame 0 0 NoParity Parity is not added to TX frames 0 Parity Parity is added to TX frames 1 DISCARDMODE Discarding unused bits at start or end of a frame 1 1 DiscardEnd Unused bits are discarded at end of frame (EoF) 0 DiscardStart Unused bits are discarded at start of frame (SoF) 1 SOF Adding SoF or not in TX frames 2 2 NoSoF SoF symbol not added 0 SoF SoF symbol added 1 CRCMODETX CRC mode for outgoing frames 4 4 NoCRCTX CRC is not added to the frame 0 CRC16TX 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame 1 AMOUNT Size of outgoing frame 0x004 read-write TXDATABITS Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). 0 2 TXDATABYTES Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing 3 11 RXD Unspecified NFCT_RXD 0x520 FRAMECONFIG Configuration of incoming frames 0x000 read-write 0x00000015 PARITY Indicates if parity expected in RX frame 0 0 NoParity Parity is not expected in RX frames 0 Parity Parity is expected in RX frames 1 SOF SoF expected or not in RX frames 2 2 NoSoF SoF symbol is not expected in RX frames 0 SoF SoF symbol is expected in RX frames 1 CRCMODERX CRC mode for incoming frames 4 4 NoCRCRX CRC is not expected in RX frames 0 CRC16RX Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated 1 AMOUNT Size of last incoming frame 0x004 read-only RXDATABITS Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). 0 2 RXDATABYTES Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) 3 11 NFCID1_LAST Last NFCID1 part (4, 7 or 10 bytes ID) 0x590 read-write 0x00006363 NFCID1_Z NFCID1 byte Z (very last byte sent) 0 7 NFCID1_Y NFCID1 byte Y 8 15 NFCID1_X NFCID1 byte X 16 23 NFCID1_W NFCID1 byte W 24 31 NFCID1_2ND_LAST Second last NFCID1 part (7 or 10 bytes ID) 0x594 read-write NFCID1_V NFCID1 byte V 0 7 NFCID1_U NFCID1 byte U 8 15 NFCID1_T NFCID1 byte T 16 23 NFCID1_3RD_LAST Third last NFCID1 part (10 bytes ID) 0x598 read-write NFCID1_S NFCID1 byte S 0 7 NFCID1_R NFCID1 byte R 8 15 NFCID1_Q NFCID1 byte Q 16 23 AUTOCOLRESCONFIG Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled. 0x59C read-write 0x00000002 MODE Enables/disables auto collision resolution 0 0 Enabled Auto collision resolution enabled 0 Disabled Auto collision resolution disabled 1 SENSRES NFC-A SENS_RES auto-response settings 0x5A0 read-write 0x00000001 BITFRAMESDD Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 0 4 SDD00000 SDD pattern 00000 0 SDD00001 SDD pattern 00001 1 SDD00010 SDD pattern 00010 2 SDD00100 SDD pattern 00100 4 SDD01000 SDD pattern 01000 8 SDD10000 SDD pattern 10000 16 RFU5 Reserved for future use. Shall be 0. 5 5 NFCIDSIZE NFCID1 size. This value is used by the auto collision resolution engine. 6 7 NFCID1Single NFCID1 size: single (4 bytes) 0 NFCID1Double NFCID1 size: double (7 bytes) 1 NFCID1Triple NFCID1 size: triple (10 bytes) 2 PLATFCONFIG Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 8 11 RFU74 Reserved for future use. Shall be 0. 12 15 SELRES NFC-A SEL_RES auto-response settings 0x5A4 read-write RFU10 Reserved for future use. Shall be 0. 0 1 CASCADE Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0) 2 2 RFU43 Reserved for future use. Shall be 0. 3 4 PROTOCOL Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification 5 6 RFU7 Reserved for future use. Shall be 0. 7 7 GPIOTE GPIO Tasks and Events 0x40006000 0 0x1000 registers GPIOTE 6 GPIOTE 0x20 0x8 0x4 TASKS_OUT[%s] Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. 0x000 write-only TASKS_OUT 0 0 0x8 0x4 TASKS_SET[%s] Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. 0x030 write-only TASKS_SET 0 0 0x8 0x4 TASKS_CLR[%s] Description collection[n]: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. 0x060 write-only TASKS_CLR 0 0 0x8 0x4 EVENTS_IN[%s] Description collection[n]: Event generated from pin specified in CONFIG[n].PSEL 0x100 read-write EVENTS_IN 0 0 EVENTS_PORT Event generated from multiple input GPIO pins with SENSE mechanism enabled 0x17C read-write EVENTS_PORT 0 0 INTENSET Enable interrupt 0x304 read-write IN0 Write '1' to enable interrupt for IN[0] event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN1 Write '1' to enable interrupt for IN[1] event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN2 Write '1' to enable interrupt for IN[2] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN3 Write '1' to enable interrupt for IN[3] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN4 Write '1' to enable interrupt for IN[4] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN5 Write '1' to enable interrupt for IN[5] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN6 Write '1' to enable interrupt for IN[6] event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 IN7 Write '1' to enable interrupt for IN[7] event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PORT Write '1' to enable interrupt for PORT event 31 31 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write IN0 Write '1' to disable interrupt for IN[0] event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN1 Write '1' to disable interrupt for IN[1] event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN2 Write '1' to disable interrupt for IN[2] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN3 Write '1' to disable interrupt for IN[3] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN4 Write '1' to disable interrupt for IN[4] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN5 Write '1' to disable interrupt for IN[5] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN6 Write '1' to disable interrupt for IN[6] event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 IN7 Write '1' to disable interrupt for IN[7] event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PORT Write '1' to disable interrupt for PORT event 31 31 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 0x8 0x4 CONFIG[%s] Description collection[n]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event 0x510 read-write MODE Mode 0 1 Disabled Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. 0 Event Event mode 1 Task Task mode 3 PSEL GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event 8 12 PORT Port number 13 13 POLARITY When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. 16 17 None Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. 0 LoToHi Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. 1 HiToLo Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. 2 Toggle Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. 3 OUTINIT When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. 20 20 Low Task mode: Initial value of pin before task triggering is low 0 High Task mode: Initial value of pin before task triggering is high 1 SAADC Successive approximation register (SAR) analog-to-digital converter 0x40007000 0 0x1000 registers SAADC 7 SAADC 0x20 TASKS_START Starts the SAADC and prepares the result buffer in RAM 0x000 write-only TASKS_START 0 0 TASKS_SAMPLE Takes one SAADC sample 0x004 write-only TASKS_SAMPLE 0 0 TASKS_STOP Stops the SAADC and terminates all on-going conversions 0x008 write-only TASKS_STOP 0 0 TASKS_CALIBRATEOFFSET Starts offset auto-calibration 0x00C write-only TASKS_CALIBRATEOFFSET 0 0 EVENTS_STARTED The SAADC has started 0x100 read-write EVENTS_STARTED 0 0 EVENTS_END The SAADC has filled up the result buffer 0x104 read-write EVENTS_END 0 0 EVENTS_DONE A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM. 0x108 read-write EVENTS_DONE 0 0 EVENTS_RESULTDONE Result ready for transfer to RAM 0x10C read-write EVENTS_RESULTDONE 0 0 EVENTS_CALIBRATEDONE Calibration is complete 0x110 read-write EVENTS_CALIBRATEDONE 0 0 EVENTS_STOPPED The SAADC has stopped 0x114 read-write EVENTS_STOPPED 0 0 8 0x008 EVENTS_CH[%s] Unspecified SAADC_EVENTS_CH 0x118 LIMITH Description cluster[n]: Last result is equal or above CH[n].LIMIT.HIGH 0x000 read-write LIMITH 0 0 LIMITL Description cluster[n]: Last result is equal or below CH[n].LIMIT.LOW 0x004 read-write LIMITL 0 0 INTEN Enable or disable interrupt 0x300 read-write STARTED Enable or disable interrupt for STARTED event 0 0 Disabled Disable 0 Enabled Enable 1 END Enable or disable interrupt for END event 1 1 Disabled Disable 0 Enabled Enable 1 DONE Enable or disable interrupt for DONE event 2 2 Disabled Disable 0 Enabled Enable 1 RESULTDONE Enable or disable interrupt for RESULTDONE event 3 3 Disabled Disable 0 Enabled Enable 1 CALIBRATEDONE Enable or disable interrupt for CALIBRATEDONE event 4 4 Disabled Disable 0 Enabled Enable 1 STOPPED Enable or disable interrupt for STOPPED event 5 5 Disabled Disable 0 Enabled Enable 1 CH0LIMITH Enable or disable interrupt for CH[0].LIMITH event 6 6 Disabled Disable 0 Enabled Enable 1 CH0LIMITL Enable or disable interrupt for CH[0].LIMITL event 7 7 Disabled Disable 0 Enabled Enable 1 CH1LIMITH Enable or disable interrupt for CH[1].LIMITH event 8 8 Disabled Disable 0 Enabled Enable 1 CH1LIMITL Enable or disable interrupt for CH[1].LIMITL event 9 9 Disabled Disable 0 Enabled Enable 1 CH2LIMITH Enable or disable interrupt for CH[2].LIMITH event 10 10 Disabled Disable 0 Enabled Enable 1 CH2LIMITL Enable or disable interrupt for CH[2].LIMITL event 11 11 Disabled Disable 0 Enabled Enable 1 CH3LIMITH Enable or disable interrupt for CH[3].LIMITH event 12 12 Disabled Disable 0 Enabled Enable 1 CH3LIMITL Enable or disable interrupt for CH[3].LIMITL event 13 13 Disabled Disable 0 Enabled Enable 1 CH4LIMITH Enable or disable interrupt for CH[4].LIMITH event 14 14 Disabled Disable 0 Enabled Enable 1 CH4LIMITL Enable or disable interrupt for CH[4].LIMITL event 15 15 Disabled Disable 0 Enabled Enable 1 CH5LIMITH Enable or disable interrupt for CH[5].LIMITH event 16 16 Disabled Disable 0 Enabled Enable 1 CH5LIMITL Enable or disable interrupt for CH[5].LIMITL event 17 17 Disabled Disable 0 Enabled Enable 1 CH6LIMITH Enable or disable interrupt for CH[6].LIMITH event 18 18 Disabled Disable 0 Enabled Enable 1 CH6LIMITL Enable or disable interrupt for CH[6].LIMITL event 19 19 Disabled Disable 0 Enabled Enable 1 CH7LIMITH Enable or disable interrupt for CH[7].LIMITH event 20 20 Disabled Disable 0 Enabled Enable 1 CH7LIMITL Enable or disable interrupt for CH[7].LIMITL event 21 21 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STARTED Write '1' to enable interrupt for STARTED event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for END event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DONE Write '1' to enable interrupt for DONE event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RESULTDONE Write '1' to enable interrupt for RESULTDONE event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CALIBRATEDONE Write '1' to enable interrupt for CALIBRATEDONE event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for STOPPED event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH0LIMITH Write '1' to enable interrupt for CH[0].LIMITH event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH0LIMITL Write '1' to enable interrupt for CH[0].LIMITL event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH1LIMITH Write '1' to enable interrupt for CH[1].LIMITH event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH1LIMITL Write '1' to enable interrupt for CH[1].LIMITL event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH2LIMITH Write '1' to enable interrupt for CH[2].LIMITH event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH2LIMITL Write '1' to enable interrupt for CH[2].LIMITL event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH3LIMITH Write '1' to enable interrupt for CH[3].LIMITH event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH3LIMITL Write '1' to enable interrupt for CH[3].LIMITL event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH4LIMITH Write '1' to enable interrupt for CH[4].LIMITH event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH4LIMITL Write '1' to enable interrupt for CH[4].LIMITL event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH5LIMITH Write '1' to enable interrupt for CH[5].LIMITH event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH5LIMITL Write '1' to enable interrupt for CH[5].LIMITL event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH6LIMITH Write '1' to enable interrupt for CH[6].LIMITH event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH6LIMITL Write '1' to enable interrupt for CH[6].LIMITL event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH7LIMITH Write '1' to enable interrupt for CH[7].LIMITH event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CH7LIMITL Write '1' to enable interrupt for CH[7].LIMITL event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STARTED Write '1' to disable interrupt for STARTED event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for END event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DONE Write '1' to disable interrupt for DONE event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESULTDONE Write '1' to disable interrupt for RESULTDONE event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CALIBRATEDONE Write '1' to disable interrupt for CALIBRATEDONE event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for STOPPED event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH0LIMITH Write '1' to disable interrupt for CH[0].LIMITH event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH0LIMITL Write '1' to disable interrupt for CH[0].LIMITL event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH1LIMITH Write '1' to disable interrupt for CH[1].LIMITH event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH1LIMITL Write '1' to disable interrupt for CH[1].LIMITL event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH2LIMITH Write '1' to disable interrupt for CH[2].LIMITH event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH2LIMITL Write '1' to disable interrupt for CH[2].LIMITL event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH3LIMITH Write '1' to disable interrupt for CH[3].LIMITH event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH3LIMITL Write '1' to disable interrupt for CH[3].LIMITL event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH4LIMITH Write '1' to disable interrupt for CH[4].LIMITH event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH4LIMITL Write '1' to disable interrupt for CH[4].LIMITL event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH5LIMITH Write '1' to disable interrupt for CH[5].LIMITH event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH5LIMITL Write '1' to disable interrupt for CH[5].LIMITL event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH6LIMITH Write '1' to disable interrupt for CH[6].LIMITH event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH6LIMITL Write '1' to disable interrupt for CH[6].LIMITL event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH7LIMITH Write '1' to disable interrupt for CH[7].LIMITH event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CH7LIMITL Write '1' to disable interrupt for CH[7].LIMITL event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STATUS Status 0x400 read-only STATUS Status 0 0 Ready SAADC is ready. No on-going conversions. 0 Busy SAADC is busy. Conversion in progress. 1 ENABLE Enable or disable SAADC 0x500 read-write ENABLE Enable or disable SAADC 0 0 Disabled Disable SAADC 0 Enabled Enable SAADC 1 8 0x010 CH[%s] Unspecified SAADC_CH 0x510 PSELP Description cluster[n]: Input positive pin selection for CH[n] 0x000 read-write 0x00000000 PSELP Analog positive input channel 0 4 NC Not connected 0 AnalogInput0 AIN0 1 AnalogInput1 AIN1 2 AnalogInput2 AIN2 3 AnalogInput3 AIN3 4 AnalogInput4 AIN4 5 AnalogInput5 AIN5 6 AnalogInput6 AIN6 7 AnalogInput7 AIN7 8 VDD VDD 9 VDDHDIV5 VDDH/5 0x0D PSELN Description cluster[n]: Input negative pin selection for CH[n] 0x004 read-write 0x00000000 PSELN Analog negative input, enables differential channel 0 4 NC Not connected 0 AnalogInput0 AIN0 1 AnalogInput1 AIN1 2 AnalogInput2 AIN2 3 AnalogInput3 AIN3 4 AnalogInput4 AIN4 5 AnalogInput5 AIN5 6 AnalogInput6 AIN6 7 AnalogInput7 AIN7 8 VDD VDD 9 VDDHDIV5 VDDH/5 0x0D CONFIG Description cluster[n]: Input configuration for CH[n] 0x008 read-write 0x00020000 RESP Positive channel resistor control 0 1 Bypass Bypass resistor ladder 0 Pulldown Pull-down to GND 1 Pullup Pull-up to VDD 2 VDD1_2 Set input at VDD/2 3 RESN Negative channel resistor control 4 5 Bypass Bypass resistor ladder 0 Pulldown Pull-down to GND 1 Pullup Pull-up to VDD 2 VDD1_2 Set input at VDD/2 3 GAIN Gain control 8 10 Gain1_6 1/6 0 Gain1_5 1/5 1 Gain1_4 1/4 2 Gain1_3 1/3 3 Gain1_2 1/2 4 Gain1 1 5 Gain2 2 6 Gain4 4 7 REFSEL Reference control 12 12 Internal Internal reference (0.6 V) 0 VDD1_4 VDD/4 as reference 1 TACQ Acquisition time, the time the SAADC uses to sample the input voltage 16 18 3us 3 us 0 5us 5 us 1 10us 10 us 2 15us 15 us 3 20us 20 us 4 40us 40 us 5 MODE Enable differential mode 20 20 SE Single-ended, PSELN will be ignored, negative input to SAADC shorted to GND 0 Diff Differential 1 BURST Enable burst mode 24 24 Disabled Burst mode is disabled (normal operation) 0 Enabled Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 1 LIMIT Description cluster[n]: High/low limits for event monitoring of a channel 0x00C read-write 0x7FFF8000 LOW Low level limit 0 15 HIGH High level limit 16 31 RESOLUTION Resolution configuration 0x5F0 read-write 0x00000001 VAL Set the resolution 0 2 8bit 8 bits 0 10bit 10 bits 1 12bit 12 bits 2 14bit 14 bits 3 OVERSAMPLE Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. 0x5F4 read-write OVERSAMPLE Oversample control 0 3 Bypass Bypass oversampling 0 Over2x Oversample 2x 1 Over4x Oversample 4x 2 Over8x Oversample 8x 3 Over16x Oversample 16x 4 Over32x Oversample 32x 5 Over64x Oversample 64x 6 Over128x Oversample 128x 7 Over256x Oversample 256x 8 SAMPLERATE Controls normal or continuous sample rate 0x5F8 read-write CC Capture and compare value. Sample rate is 16 MHz/CC 0 10 MODE Select mode for sample rate control 12 12 Task Rate is controlled from SAMPLE task 0 Timers Rate is controlled from local timer (use CC to control the rate) 1 RESULT RESULT EasyDMA channel SAADC_RESULT 0x62C PTR Data pointer 0x000 read-write PTR Data pointer 0 31 MAXCNT Maximum number of 16-bit samples to be written to output RAM buffer 0x004 read-write MAXCNT Maximum number of 16-bit samples to be written to output RAM buffer 0 14 AMOUNT Number of 16-bit samples written to output RAM buffer since the previous START task 0x008 read-only AMOUNT Number of 16-bit samples written to output RAM buffer since the previous START task. This register can be read after an END or STOPPED event. 0 14 TIMER0 Timer/Counter 0 0x40008000 TIMER 0 0x1000 registers TIMER0 8 TIMER 0x20 TASKS_START Start Timer 0x000 write-only TASKS_START 0 0 TASKS_STOP Stop Timer 0x004 write-only TASKS_STOP 0 0 TASKS_COUNT Increment Timer (Counter mode only) 0x008 write-only TASKS_COUNT 0 0 TASKS_CLEAR Clear time 0x00C write-only TASKS_CLEAR 0 0 TASKS_SHUTDOWN Deprecated register - Shut down timer 0x010 write-only TASKS_SHUTDOWN 0 0 0x6 0x4 TASKS_CAPTURE[%s] Description collection[n]: Capture Timer value to CC[n] register 0x040 write-only TASKS_CAPTURE 0 0 0x6 0x4 EVENTS_COMPARE[%s] Description collection[n]: Compare event on CC[n] match 0x140 read-write EVENTS_COMPARE 0 0 SHORTS Shortcut register 0x200 read-write COMPARE0_CLEAR Shortcut between COMPARE[0] event and CLEAR task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE1_CLEAR Shortcut between COMPARE[1] event and CLEAR task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE2_CLEAR Shortcut between COMPARE[2] event and CLEAR task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE3_CLEAR Shortcut between COMPARE[3] event and CLEAR task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE4_CLEAR Shortcut between COMPARE[4] event and CLEAR task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE5_CLEAR Shortcut between COMPARE[5] event and CLEAR task 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE0_STOP Shortcut between COMPARE[0] event and STOP task 8 8 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE1_STOP Shortcut between COMPARE[1] event and STOP task 9 9 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE2_STOP Shortcut between COMPARE[2] event and STOP task 10 10 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE3_STOP Shortcut between COMPARE[3] event and STOP task 11 11 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE4_STOP Shortcut between COMPARE[4] event and STOP task 12 12 Disabled Disable shortcut 0 Enabled Enable shortcut 1 COMPARE5_STOP Shortcut between COMPARE[5] event and STOP task 13 13 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write COMPARE0 Write '1' to enable interrupt for COMPARE[0] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable interrupt for COMPARE[1] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable interrupt for COMPARE[2] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable interrupt for COMPARE[3] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE4 Write '1' to enable interrupt for COMPARE[4] event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE5 Write '1' to enable interrupt for COMPARE[5] event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write COMPARE0 Write '1' to disable interrupt for COMPARE[0] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable interrupt for COMPARE[1] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable interrupt for COMPARE[2] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable interrupt for COMPARE[3] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE4 Write '1' to disable interrupt for COMPARE[4] event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE5 Write '1' to disable interrupt for COMPARE[5] event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 MODE Timer mode selection 0x504 read-write MODE Timer mode 0 1 Timer Select Timer mode 0 Counter Deprecated enumerator - Select Counter mode 1 LowPowerCounter Select Low Power Counter mode 2 BITMODE Configure the number of bits used by the TIMER 0x508 read-write BITMODE Timer bit width 0 1 16Bit 16 bit timer bit width 0 08Bit 8 bit timer bit width 1 24Bit 24 bit timer bit width 2 32Bit 32 bit timer bit width 3 PRESCALER Timer prescaler register 0x510 read-write 0x00000004 PRESCALER Prescaler value 0 3 0x6 0x4 CC[%s] Description collection[n]: Capture/Compare register n 0x540 read-write CC Capture/Compare value 0 31 TIMER1 Timer/Counter 1 0x40009000 TIMER1 9 TIMER2 Timer/Counter 2 0x4000A000 TIMER2 10 RTC0 Real time counter 0 0x4000B000 RTC 0 0x1000 registers RTC0 11 RTC 0x20 TASKS_START Start RTC COUNTER 0x000 write-only TASKS_START 0 0 TASKS_STOP Stop RTC COUNTER 0x004 write-only TASKS_STOP 0 0 TASKS_CLEAR Clear RTC COUNTER 0x008 write-only TASKS_CLEAR 0 0 TASKS_TRIGOVRFLW Set COUNTER to 0xFFFFF0 0x00C write-only TASKS_TRIGOVRFLW 0 0 EVENTS_TICK Event on COUNTER increment 0x100 read-write EVENTS_TICK 0 0 EVENTS_OVRFLW Event on COUNTER overflow 0x104 read-write EVENTS_OVRFLW 0 0 0x4 0x4 EVENTS_COMPARE[%s] Description collection[n]: Compare event on CC[n] match 0x140 read-write EVENTS_COMPARE 0 0 INTENSET Enable interrupt 0x304 read-write TICK Write '1' to enable interrupt for TICK event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 OVRFLW Write '1' to enable interrupt for OVRFLW event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE0 Write '1' to enable interrupt for COMPARE[0] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable interrupt for COMPARE[1] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable interrupt for COMPARE[2] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable interrupt for COMPARE[3] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TICK Write '1' to disable interrupt for TICK event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 OVRFLW Write '1' to disable interrupt for OVRFLW event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE0 Write '1' to disable interrupt for COMPARE[0] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable interrupt for COMPARE[1] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable interrupt for COMPARE[2] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable interrupt for COMPARE[3] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EVTEN Enable or disable event routing 0x340 read-write TICK Enable or disable event routing for TICK event 0 0 Disabled Disable 0 Enabled Enable 1 OVRFLW Enable or disable event routing for OVRFLW event 1 1 Disabled Disable 0 Enabled Enable 1 COMPARE0 Enable or disable event routing for COMPARE[0] event 16 16 Disabled Disable 0 Enabled Enable 1 COMPARE1 Enable or disable event routing for COMPARE[1] event 17 17 Disabled Disable 0 Enabled Enable 1 COMPARE2 Enable or disable event routing for COMPARE[2] event 18 18 Disabled Disable 0 Enabled Enable 1 COMPARE3 Enable or disable event routing for COMPARE[3] event 19 19 Disabled Disable 0 Enabled Enable 1 EVTENSET Enable event routing 0x344 read-write TICK Write '1' to enable event routing for TICK event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 OVRFLW Write '1' to enable event routing for OVRFLW event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE0 Write '1' to enable event routing for COMPARE[0] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE1 Write '1' to enable event routing for COMPARE[1] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE2 Write '1' to enable event routing for COMPARE[2] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 COMPARE3 Write '1' to enable event routing for COMPARE[3] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EVTENCLR Disable event routing 0x348 read-write TICK Write '1' to disable event routing for TICK event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 OVRFLW Write '1' to disable event routing for OVRFLW event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE0 Write '1' to disable event routing for COMPARE[0] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE1 Write '1' to disable event routing for COMPARE[1] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE2 Write '1' to disable event routing for COMPARE[2] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COMPARE3 Write '1' to disable event routing for COMPARE[3] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 COUNTER Current COUNTER value 0x504 read-only COUNTER Counter value 0 23 PRESCALER 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped 0x508 read-write PRESCALER Prescaler value 0 11 0x4 0x4 CC[%s] Description collection[n]: Compare register n 0x540 read-write COMPARE Compare value 0 23 TEMP Temperature Sensor 0x4000C000 0 0x1000 registers TEMP 12 TEMP 0x20 TASKS_START Start temperature measurement 0x000 write-only TASKS_START 0 0 TASKS_STOP Stop temperature measurement 0x004 write-only TASKS_STOP 0 0 EVENTS_DATARDY Temperature measurement complete, data ready 0x100 read-write EVENTS_DATARDY 0 0 INTENSET Enable interrupt 0x304 read-write DATARDY Write '1' to enable interrupt for DATARDY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write DATARDY Write '1' to disable interrupt for DATARDY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TEMP Temperature in degC (0.25deg steps) 0x508 read-only int32_t TEMP Temperature in degC (0.25deg steps) 0 31 A0 Slope of 1st piece wise linear function 0x520 read-write 0x00000326 A0 Slope of 1st piece wise linear function 0 11 A1 Slope of 2nd piece wise linear function 0x524 read-write 0x00000348 A1 Slope of 2nd piece wise linear function 0 11 A2 Slope of 3rd piece wise linear function 0x528 read-write 0x000003AA A2 Slope of 3rd piece wise linear function 0 11 A3 Slope of 4th piece wise linear function 0x52C read-write 0x0000040E A3 Slope of 4th piece wise linear function 0 11 A4 Slope of 5th piece wise linear function 0x530 read-write 0x000004BD A4 Slope of 5th piece wise linear function 0 11 A5 Slope of 6th piece wise linear function 0x534 read-write 0x000005A3 A5 Slope of 6th piece wise linear function 0 11 B0 y-intercept of 1st piece wise linear function 0x540 read-write 0x00003FEF B0 y-intercept of 1st piece wise linear function 0 13 B1 y-intercept of 2nd piece wise linear function 0x544 read-write 0x00003FBE B1 y-intercept of 2nd piece wise linear function 0 13 B2 y-intercept of 3rd piece wise linear function 0x548 read-write 0x00003FBE B2 y-intercept of 3rd piece wise linear function 0 13 B3 y-intercept of 4th piece wise linear function 0x54C read-write 0x00000012 B3 y-intercept of 4th piece wise linear function 0 13 B4 y-intercept of 5th piece wise linear function 0x550 read-write 0x00000124 B4 y-intercept of 5th piece wise linear function 0 13 B5 y-intercept of 6th piece wise linear function 0x554 read-write 0x0000027C B5 y-intercept of 6th piece wise linear function 0 13 T0 End point of 1st piece wise linear function 0x560 read-write 0x000000E2 T0 End point of 1st piece wise linear function 0 7 T1 End point of 2nd piece wise linear function 0x564 read-write 0x00000000 T1 End point of 2nd piece wise linear function 0 7 T2 End point of 3rd piece wise linear function 0x568 read-write 0x00000019 T2 End point of 3rd piece wise linear function 0 7 T3 End point of 4th piece wise linear function 0x56C read-write 0x0000003C T3 End point of 4th piece wise linear function 0 7 T4 End point of 5th piece wise linear function 0x570 read-write 0x00000050 T4 End point of 5th piece wise linear function 0 7 RNG Random Number Generator 0x4000D000 0 0x1000 registers RNG 13 RNG 0x20 TASKS_START Task starting the random number generator 0x000 write-only TASKS_START 0 0 TASKS_STOP Task stopping the random number generator 0x004 write-only TASKS_STOP 0 0 EVENTS_VALRDY Event being generated for every new random number written to the VALUE register 0x100 read-write EVENTS_VALRDY 0 0 SHORTS Shortcut register 0x200 read-write VALRDY_STOP Shortcut between VALRDY event and STOP task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write VALRDY Write '1' to enable interrupt for VALRDY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write VALRDY Write '1' to disable interrupt for VALRDY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CONFIG Configuration register 0x504 read-write DERCEN Bias correction 0 0 Disabled Disabled 0 Enabled Enabled 1 VALUE Output random number 0x508 read-only VALUE Generated random number 0 7 ECB AES ECB Mode Encryption 0x4000E000 0 0x1000 registers ECB 14 ECB 0x20 TASKS_STARTECB Start ECB block encrypt 0x000 write-only TASKS_STARTECB 0 0 TASKS_STOPECB Abort a possible executing ECB operation 0x004 write-only TASKS_STOPECB 0 0 EVENTS_ENDECB ECB block encrypt complete 0x100 read-write EVENTS_ENDECB 0 0 EVENTS_ERRORECB ECB block encrypt aborted because of a STOPECB task or due to an error 0x104 read-write EVENTS_ERRORECB 0 0 INTENSET Enable interrupt 0x304 read-write ENDECB Write '1' to enable interrupt for ENDECB event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERRORECB Write '1' to enable interrupt for ERRORECB event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write ENDECB Write '1' to disable interrupt for ENDECB event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERRORECB Write '1' to disable interrupt for ERRORECB event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ECBDATAPTR ECB block encrypt memory pointers 0x504 read-write ECBDATAPTR Pointer to the ECB data structure (see Table 1 ECB data structure overview) 0 31 AAR Accelerated Address Resolver 0x4000F000 0 0x1000 registers CCM_AAR 15 AAR 0x20 TASKS_START Start resolving addresses based on IRKs specified in the IRK data structure 0x000 write-only TASKS_START 0 0 TASKS_STOP Stop resolving addresses 0x008 write-only TASKS_STOP 0 0 EVENTS_END Address resolution procedure complete 0x100 read-write EVENTS_END 0 0 EVENTS_RESOLVED Address resolved 0x104 read-write EVENTS_RESOLVED 0 0 EVENTS_NOTRESOLVED Address not resolved 0x108 read-write EVENTS_NOTRESOLVED 0 0 INTENSET Enable interrupt 0x304 read-write END Write '1' to enable interrupt for END event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 RESOLVED Write '1' to enable interrupt for RESOLVED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NOTRESOLVED Write '1' to enable interrupt for NOTRESOLVED event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write END Write '1' to disable interrupt for END event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESOLVED Write '1' to disable interrupt for RESOLVED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NOTRESOLVED Write '1' to disable interrupt for NOTRESOLVED event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STATUS Resolution status 0x400 read-only STATUS The IRK that was used last time an address was resolved 0 3 ENABLE Enable AAR 0x500 read-write ENABLE Enable or disable AAR 0 1 Disabled Disable 0 Enabled Enable 3 NIRK Number of IRKs 0x504 read-write 0x00000001 NIRK Number of Identity root keys available in the IRK data structure 0 4 IRKPTR Pointer to IRK data structure 0x508 read-write IRKPTR Pointer to the IRK data structure 0 31 ADDRPTR Pointer to the resolvable address 0x510 read-write ADDRPTR Pointer to the resolvable address (6-bytes) 0 31 SCRATCHPTR Pointer to data area used for temporary storage 0x514 read-write SCRATCHPTR Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. 0 31 CCM AES CCM Mode Encryption 0x4000F000 AAR 0 0x1000 registers CCM_AAR 15 CCM 0x20 TASKS_KSGEN Start generation of key-stream. This operation will stop by itself when completed. 0x000 write-only TASKS_KSGEN 0 0 TASKS_CRYPT Start encryption/decryption. This operation will stop by itself when completed. 0x004 write-only TASKS_CRYPT 0 0 TASKS_STOP Stop encryption/decryption 0x008 write-only TASKS_STOP 0 0 TASKS_RATEOVERRIDE Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption 0x00C write-only TASKS_RATEOVERRIDE 0 0 EVENTS_ENDKSGEN Key-stream generation complete 0x100 read-write EVENTS_ENDKSGEN 0 0 EVENTS_ENDCRYPT Encrypt/decrypt complete 0x104 read-write EVENTS_ENDCRYPT 0 0 EVENTS_ERROR Deprecated register - CCM error event 0x108 read-write EVENTS_ERROR 0 0 SHORTS Shortcut register 0x200 read-write ENDKSGEN_CRYPT Shortcut between ENDKSGEN event and CRYPT task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write ENDKSGEN Write '1' to enable interrupt for ENDKSGEN event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDCRYPT Write '1' to enable interrupt for ENDCRYPT event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ERROR Write '1' to enable interrupt for ERROR event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write ENDKSGEN Write '1' to disable interrupt for ENDKSGEN event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDCRYPT Write '1' to disable interrupt for ENDCRYPT event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ERROR Write '1' to disable interrupt for ERROR event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 MICSTATUS MIC check result 0x400 read-only MICSTATUS The result of the MIC check performed during the previous decryption operation 0 0 CheckFailed MIC check failed 0 CheckPassed MIC check passed 1 ENABLE Enable 0x500 read-write ENABLE Enable or disable CCM 0 1 Disabled Disable 0 Enabled Enable 2 MODE Operation mode 0x504 read-write 0x00000001 MODE The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered. 0 0 Encryption AES CCM packet encryption mode 0 Decryption AES CCM packet decryption mode 1 DATARATE Radio data rate that the CCM shall run synchronous with 16 17 1Mbit 1 Mbps 0 2Mbit 2 Mbps 1 125Kbps 125 Kbps 2 500Kbps 500 Kbps 3 LENGTH Packet length configuration 24 24 Default Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated. 0 Extended Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated. 1 CNFPTR Pointer to data structure holding AES key and NONCE vector 0x508 read-write CNFPTR Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) 0 31 INPTR Input pointer 0x50C read-write INPTR Input pointer 0 31 OUTPTR Output pointer 0x510 read-write OUTPTR Output pointer 0 31 SCRATCHPTR Pointer to data area used for temporary storage 0x514 read-write SCRATCHPTR Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. 0 31 MAXPACKETSIZE Length of key-stream generated when MODE.LENGTH = Extended. 0x518 read-write 0x000000FB MAXPACKETSIZE Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted. 0 7 RATEOVERRIDE Data rate override setting. 0x51C read-write 0x00000000 RATEOVERRIDE Data rate override setting. 0 1 1Mbit 1 Mbps 0 2Mbit 2 Mbps 1 125Kbps 125 Kbps 2 500Kbps 500 Kbps 3 WDT Watchdog Timer 0x40010000 0 0x1000 registers WDT 16 WDT 0x20 TASKS_START Start the watchdog 0x000 write-only TASKS_START 0 0 EVENTS_TIMEOUT Watchdog timeout 0x100 read-write EVENTS_TIMEOUT 0 0 INTENSET Enable interrupt 0x304 read-write TIMEOUT Write '1' to enable interrupt for TIMEOUT event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TIMEOUT Write '1' to disable interrupt for TIMEOUT event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RUNSTATUS Run status 0x400 read-only RUNSTATUS Indicates whether or not the watchdog is running 0 0 NotRunning Watchdog not running 0 Running Watchdog is running 1 REQSTATUS Request status 0x404 read-only 0x00000001 RR0 Request status for RR[0] register 0 0 DisabledOrRequested RR[0] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[0] register is enabled, and are not yet requesting reload 1 RR1 Request status for RR[1] register 1 1 DisabledOrRequested RR[1] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[1] register is enabled, and are not yet requesting reload 1 RR2 Request status for RR[2] register 2 2 DisabledOrRequested RR[2] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[2] register is enabled, and are not yet requesting reload 1 RR3 Request status for RR[3] register 3 3 DisabledOrRequested RR[3] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[3] register is enabled, and are not yet requesting reload 1 RR4 Request status for RR[4] register 4 4 DisabledOrRequested RR[4] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[4] register is enabled, and are not yet requesting reload 1 RR5 Request status for RR[5] register 5 5 DisabledOrRequested RR[5] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[5] register is enabled, and are not yet requesting reload 1 RR6 Request status for RR[6] register 6 6 DisabledOrRequested RR[6] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[6] register is enabled, and are not yet requesting reload 1 RR7 Request status for RR[7] register 7 7 DisabledOrRequested RR[7] register is not enabled, or are already requesting reload 0 EnabledAndUnrequested RR[7] register is enabled, and are not yet requesting reload 1 CRV Counter reload value 0x504 read-write 0xFFFFFFFF CRV Counter reload value in number of cycles of the 32.768 kHz clock 0 31 RREN Enable register for reload request registers 0x508 read-write 0x00000001 RR0 Enable or disable RR[0] register 0 0 Disabled Disable RR[0] register 0 Enabled Enable RR[0] register 1 RR1 Enable or disable RR[1] register 1 1 Disabled Disable RR[1] register 0 Enabled Enable RR[1] register 1 RR2 Enable or disable RR[2] register 2 2 Disabled Disable RR[2] register 0 Enabled Enable RR[2] register 1 RR3 Enable or disable RR[3] register 3 3 Disabled Disable RR[3] register 0 Enabled Enable RR[3] register 1 RR4 Enable or disable RR[4] register 4 4 Disabled Disable RR[4] register 0 Enabled Enable RR[4] register 1 RR5 Enable or disable RR[5] register 5 5 Disabled Disable RR[5] register 0 Enabled Enable RR[5] register 1 RR6 Enable or disable RR[6] register 6 6 Disabled Disable RR[6] register 0 Enabled Enable RR[6] register 1 RR7 Enable or disable RR[7] register 7 7 Disabled Disable RR[7] register 0 Enabled Enable RR[7] register 1 CONFIG Configuration register 0x50C read-write 0x00000001 SLEEP Configure the watchdog to either be paused, or kept running, while the CPU is sleeping 0 0 Pause Pause watchdog while the CPU is sleeping 0 Run Keep the watchdog running while the CPU is sleeping 1 HALT Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger 3 3 Pause Pause watchdog while the CPU is halted by the debugger 0 Run Keep the watchdog running while the CPU is halted by the debugger 1 0x8 0x4 RR[%s] Description collection[n]: Reload request n 0x600 write-only RR Reload request register 0 31 Reload Value to request a reload of the watchdog timer 0x6E524635 RTC1 Real time counter 1 0x40011000 RTC1 17 QDEC Quadrature Decoder 0x40012000 0 0x1000 registers QDEC 18 QDEC 0x20 TASKS_START Task starting the quadrature decoder 0x000 write-only TASKS_START 0 0 TASKS_STOP Task stopping the quadrature decoder 0x004 write-only TASKS_STOP 0 0 TASKS_READCLRACC Read and clear ACC and ACCDBL 0x008 write-only TASKS_READCLRACC 0 0 TASKS_RDCLRACC Read and clear ACC 0x00C write-only TASKS_RDCLRACC 0 0 TASKS_RDCLRDBL Read and clear ACCDBL 0x010 write-only TASKS_RDCLRDBL 0 0 EVENTS_SAMPLERDY Event being generated for every new sample value written to the SAMPLE register 0x100 read-write EVENTS_SAMPLERDY 0 0 EVENTS_REPORTRDY Non-null report ready 0x104 read-write EVENTS_REPORTRDY 0 0 EVENTS_ACCOF ACC or ACCDBL register overflow 0x108 read-write EVENTS_ACCOF 0 0 EVENTS_DBLRDY Double displacement(s) detected 0x10C read-write EVENTS_DBLRDY 0 0 EVENTS_STOPPED QDEC has been stopped 0x110 read-write EVENTS_STOPPED 0 0 SHORTS Shortcut register 0x200 read-write REPORTRDY_READCLRACC Shortcut between REPORTRDY event and READCLRACC task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 SAMPLERDY_STOP Shortcut between SAMPLERDY event and STOP task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 REPORTRDY_RDCLRACC Shortcut between REPORTRDY event and RDCLRACC task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 REPORTRDY_STOP Shortcut between REPORTRDY event and STOP task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DBLRDY_RDCLRDBL Shortcut between DBLRDY event and RDCLRDBL task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DBLRDY_STOP Shortcut between DBLRDY event and STOP task 5 5 Disabled Disable shortcut 0 Enabled Enable shortcut 1 SAMPLERDY_READCLRACC Shortcut between SAMPLERDY event and READCLRACC task 6 6 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write SAMPLERDY Write '1' to enable interrupt for SAMPLERDY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REPORTRDY Write '1' to enable interrupt for REPORTRDY event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ACCOF Write '1' to enable interrupt for ACCOF event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DBLRDY Write '1' to enable interrupt for DBLRDY event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for STOPPED event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write SAMPLERDY Write '1' to disable interrupt for SAMPLERDY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REPORTRDY Write '1' to disable interrupt for REPORTRDY event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ACCOF Write '1' to disable interrupt for ACCOF event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DBLRDY Write '1' to disable interrupt for DBLRDY event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for STOPPED event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable the quadrature decoder 0x500 read-write ENABLE Enable or disable the quadrature decoder 0 0 Disabled Disable 0 Enabled Enable 1 LEDPOL LED output pin polarity 0x504 read-write LEDPOL LED output pin polarity 0 0 ActiveLow Led active on output pin low 0 ActiveHigh Led active on output pin high 1 SAMPLEPER Sample period 0x508 read-write SAMPLEPER Sample period. The SAMPLE register will be updated for every new sample 0 3 128us 128 us 0 256us 256 us 1 512us 512 us 2 1024us 1024 us 3 2048us 2048 us 4 4096us 4096 us 5 8192us 8192 us 6 16384us 16384 us 7 32ms 32768 us 8 65ms 65536 us 9 131ms 131072 us 10 SAMPLE Motion sample value 0x50C read-only int32_t SAMPLE Last motion sample 0 31 REPORTPER Number of samples to be taken before REPORTRDY and DBLRDY events can be generated 0x510 read-write REPORTPER Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated 0 3 10Smpl 10 samples / report 0 40Smpl 40 samples / report 1 80Smpl 80 samples / report 2 120Smpl 120 samples / report 3 160Smpl 160 samples / report 4 200Smpl 200 samples / report 5 240Smpl 240 samples / report 6 280Smpl 280 samples / report 7 1Smpl 1 sample / report 8 ACC Register accumulating the valid transitions 0x514 read-only int32_t ACC Register accumulating all valid samples (not double transition) read from the SAMPLE register 0 31 ACCREAD Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task 0x518 read-only int32_t ACCREAD Snapshot of the ACC register. 0 31 PSEL Unspecified QDEC_PSEL 0x51C LED Pin select for LED signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 A Pin select for A signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 B Pin select for B signal 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 DBFEN Enable input debounce filters 0x528 read-write DBFEN Enable input debounce filters 0 0 Disabled Debounce input filters disabled 0 Enabled Debounce input filters enabled 1 LEDPRE Time period the LED is switched ON prior to sampling 0x540 read-write 0x00000010 LEDPRE Period in us the LED is switched on prior to sampling 0 8 ACCDBL Register accumulating the number of detected double transitions 0x544 read-only ACCDBL Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). 0 3 ACCDBLREAD Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task 0x548 read-only ACCDBLREAD Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. 0 3 COMP Comparator 0x40013000 0 0x1000 registers COMP_LPCOMP 19 COMP 0x20 TASKS_START Start comparator 0x000 write-only TASKS_START 0 0 TASKS_STOP Stop comparator 0x004 write-only TASKS_STOP 0 0 TASKS_SAMPLE Sample comparator value 0x008 write-only TASKS_SAMPLE 0 0 EVENTS_READY COMP is ready and output is valid 0x100 read-write EVENTS_READY 0 0 EVENTS_DOWN Downward crossing 0x104 read-write EVENTS_DOWN 0 0 EVENTS_UP Upward crossing 0x108 read-write EVENTS_UP 0 0 EVENTS_CROSS Downward or upward crossing 0x10C read-write EVENTS_CROSS 0 0 SHORTS Shortcut register 0x200 read-write READY_SAMPLE Shortcut between READY event and SAMPLE task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 READY_STOP Shortcut between READY event and STOP task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DOWN_STOP Shortcut between DOWN event and STOP task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 UP_STOP Shortcut between UP event and STOP task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 CROSS_STOP Shortcut between CROSS event and STOP task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write READY Enable or disable interrupt for READY event 0 0 Disabled Disable 0 Enabled Enable 1 DOWN Enable or disable interrupt for DOWN event 1 1 Disabled Disable 0 Enabled Enable 1 UP Enable or disable interrupt for UP event 2 2 Disabled Disable 0 Enabled Enable 1 CROSS Enable or disable interrupt for CROSS event 3 3 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DOWN Write '1' to enable interrupt for DOWN event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 UP Write '1' to enable interrupt for UP event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CROSS Write '1' to enable interrupt for CROSS event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DOWN Write '1' to disable interrupt for DOWN event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 UP Write '1' to disable interrupt for UP event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CROSS Write '1' to disable interrupt for CROSS event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESULT Compare result 0x400 read-only RESULT Result of last compare. Decision point SAMPLE task. 0 0 Below Input voltage is below the threshold (VIN+ < VIN-) 0 Above Input voltage is above the threshold (VIN+ > VIN-) 1 ENABLE COMP enable 0x500 read-write ENABLE Enable or disable COMP 0 1 Disabled Disable 0 Enabled Enable 2 PSEL Pin select 0x504 read-write PSEL Analog pin select 0 2 AnalogInput0 AIN0 selected as analog input 0 AnalogInput1 AIN1 selected as analog input 1 AnalogInput2 AIN2 selected as analog input 2 AnalogInput3 AIN3 selected as analog input 3 AnalogInput4 AIN4 selected as analog input 4 AnalogInput5 AIN5 selected as analog input 5 AnalogInput6 AIN6 selected as analog input 6 AnalogInput7 AIN7 selected as analog input 7 REFSEL Reference source select for single-ended mode 0x508 read-write 0x00000004 REFSEL Reference select 0 2 Int1V2 VREF = internal 1.2 V reference (VDD >= 1.7 V) 0 Int1V8 VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) 1 Int2V4 VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) 2 VDD VREF = VDD 4 ARef VREF = AREF (VDD >= VREF >= AREFMIN) 5 EXTREFSEL External reference select 0x50C read-write EXTREFSEL External analog reference select 0 2 AnalogReference0 Use AIN0 as external analog reference 0 AnalogReference1 Use AIN1 as external analog reference 1 AnalogReference2 Use AIN2 as external analog reference 2 AnalogReference3 Use AIN3 as external analog reference 3 AnalogReference4 Use AIN4 as external analog reference 4 AnalogReference5 Use AIN5 as external analog reference 5 AnalogReference6 Use AIN6 as external analog reference 6 AnalogReference7 Use AIN7 as external analog reference 7 TH Threshold configuration for hysteresis unit 0x530 read-write 0x00000000 THDOWN VDOWN = (THDOWN+1)/64*VREF 0 5 THUP VUP = (THUP+1)/64*VREF 8 13 MODE Mode configuration 0x534 read-write SP Speed and power modes 0 1 Low Low-power mode 0 Normal Normal mode 1 High High-speed mode 2 MAIN Main operation modes 8 8 SE Single-ended mode 0 Diff Differential mode 1 HYST Comparator hysteresis enable 0x538 read-write HYST Comparator hysteresis 0 0 NoHyst Comparator hysteresis disabled 0 Hyst50mV Comparator hysteresis enabled 1 LPCOMP Low Power Comparator 0x40013000 COMP 0 0x1000 registers COMP_LPCOMP 19 LPCOMP 0x20 TASKS_START Start comparator 0x000 write-only TASKS_START 0 0 TASKS_STOP Stop comparator 0x004 write-only TASKS_STOP 0 0 TASKS_SAMPLE Sample comparator value 0x008 write-only TASKS_SAMPLE 0 0 EVENTS_READY LPCOMP is ready and output is valid 0x100 read-write EVENTS_READY 0 0 EVENTS_DOWN Downward crossing 0x104 read-write EVENTS_DOWN 0 0 EVENTS_UP Upward crossing 0x108 read-write EVENTS_UP 0 0 EVENTS_CROSS Downward or upward crossing 0x10C read-write EVENTS_CROSS 0 0 SHORTS Shortcut register 0x200 read-write READY_SAMPLE Shortcut between READY event and SAMPLE task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 READY_STOP Shortcut between READY event and STOP task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 DOWN_STOP Shortcut between DOWN event and STOP task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 UP_STOP Shortcut between UP event and STOP task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 CROSS_STOP Shortcut between CROSS event and STOP task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 DOWN Write '1' to enable interrupt for DOWN event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 UP Write '1' to enable interrupt for UP event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 CROSS Write '1' to enable interrupt for CROSS event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 DOWN Write '1' to disable interrupt for DOWN event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 UP Write '1' to disable interrupt for UP event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 CROSS Write '1' to disable interrupt for CROSS event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 RESULT Compare result 0x400 read-only RESULT Result of last compare. Decision point SAMPLE task. 0 0 Below Input voltage is below the reference threshold (VIN+ < VIN-). 0 Above Input voltage is above the reference threshold (VIN+ > VIN-). 1 ENABLE Enable LPCOMP 0x500 read-write ENABLE Enable or disable LPCOMP 0 1 Disabled Disable 0 Enabled Enable 1 PSEL Input pin select 0x504 read-write PSEL Analog pin select 0 2 AnalogInput0 AIN0 selected as analog input 0 AnalogInput1 AIN1 selected as analog input 1 AnalogInput2 AIN2 selected as analog input 2 AnalogInput3 AIN3 selected as analog input 3 AnalogInput4 AIN4 selected as analog input 4 AnalogInput5 AIN5 selected as analog input 5 AnalogInput6 AIN6 selected as analog input 6 AnalogInput7 AIN7 selected as analog input 7 REFSEL Reference select 0x508 read-write 0x00000004 REFSEL Reference select 0 3 Ref1_8Vdd VDD * 1/8 selected as reference 0 Ref2_8Vdd VDD * 2/8 selected as reference 1 Ref3_8Vdd VDD * 3/8 selected as reference 2 Ref4_8Vdd VDD * 4/8 selected as reference 3 Ref5_8Vdd VDD * 5/8 selected as reference 4 Ref6_8Vdd VDD * 6/8 selected as reference 5 Ref7_8Vdd VDD * 7/8 selected as reference 6 ARef External analog reference selected 7 Ref1_16Vdd VDD * 1/16 selected as reference 8 Ref3_16Vdd VDD * 3/16 selected as reference 9 Ref5_16Vdd VDD * 5/16 selected as reference 10 Ref7_16Vdd VDD * 7/16 selected as reference 11 Ref9_16Vdd VDD * 9/16 selected as reference 12 Ref11_16Vdd VDD * 11/16 selected as reference 13 Ref13_16Vdd VDD * 13/16 selected as reference 14 Ref15_16Vdd VDD * 15/16 selected as reference 15 EXTREFSEL External reference select 0x50C read-write EXTREFSEL External analog reference select 0 0 AnalogReference0 Use AIN0 as external analog reference 0 AnalogReference1 Use AIN1 as external analog reference 1 ANADETECT Analog detect configuration 0x520 read-write ANADETECT Analog detect configuration 0 1 Cross Generate ANADETECT on crossing, both upward crossing and downward crossing 0 Up Generate ANADETECT on upward crossing only 1 Down Generate ANADETECT on downward crossing only 2 HYST Comparator hysteresis enable 0x538 read-write HYST Comparator hysteresis enable 0 0 Disabled Comparator hysteresis disabled 0 Enabled Comparator hysteresis enabled 1 EGU0 Event Generator Unit 0 0x40014000 EGU 0 0x1000 registers SWI0_EGU0 20 EGU 0x20 0x10 0x4 TASKS_TRIGGER[%s] Description collection[n]: Trigger n for triggering the corresponding TRIGGERED[n] event 0x000 write-only TASKS_TRIGGER 0 0 0x10 0x4 EVENTS_TRIGGERED[%s] Description collection[n]: Event number n generated by triggering the corresponding TRIGGER[n] task 0x100 read-write EVENTS_TRIGGERED 0 0 INTEN Enable or disable interrupt 0x300 read-write TRIGGERED0 Enable or disable interrupt for TRIGGERED[0] event 0 0 Disabled Disable 0 Enabled Enable 1 TRIGGERED1 Enable or disable interrupt for TRIGGERED[1] event 1 1 Disabled Disable 0 Enabled Enable 1 TRIGGERED2 Enable or disable interrupt for TRIGGERED[2] event 2 2 Disabled Disable 0 Enabled Enable 1 TRIGGERED3 Enable or disable interrupt for TRIGGERED[3] event 3 3 Disabled Disable 0 Enabled Enable 1 TRIGGERED4 Enable or disable interrupt for TRIGGERED[4] event 4 4 Disabled Disable 0 Enabled Enable 1 TRIGGERED5 Enable or disable interrupt for TRIGGERED[5] event 5 5 Disabled Disable 0 Enabled Enable 1 TRIGGERED6 Enable or disable interrupt for TRIGGERED[6] event 6 6 Disabled Disable 0 Enabled Enable 1 TRIGGERED7 Enable or disable interrupt for TRIGGERED[7] event 7 7 Disabled Disable 0 Enabled Enable 1 TRIGGERED8 Enable or disable interrupt for TRIGGERED[8] event 8 8 Disabled Disable 0 Enabled Enable 1 TRIGGERED9 Enable or disable interrupt for TRIGGERED[9] event 9 9 Disabled Disable 0 Enabled Enable 1 TRIGGERED10 Enable or disable interrupt for TRIGGERED[10] event 10 10 Disabled Disable 0 Enabled Enable 1 TRIGGERED11 Enable or disable interrupt for TRIGGERED[11] event 11 11 Disabled Disable 0 Enabled Enable 1 TRIGGERED12 Enable or disable interrupt for TRIGGERED[12] event 12 12 Disabled Disable 0 Enabled Enable 1 TRIGGERED13 Enable or disable interrupt for TRIGGERED[13] event 13 13 Disabled Disable 0 Enabled Enable 1 TRIGGERED14 Enable or disable interrupt for TRIGGERED[14] event 14 14 Disabled Disable 0 Enabled Enable 1 TRIGGERED15 Enable or disable interrupt for TRIGGERED[15] event 15 15 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write TRIGGERED0 Write '1' to enable interrupt for TRIGGERED[0] event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED1 Write '1' to enable interrupt for TRIGGERED[1] event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED2 Write '1' to enable interrupt for TRIGGERED[2] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED3 Write '1' to enable interrupt for TRIGGERED[3] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED4 Write '1' to enable interrupt for TRIGGERED[4] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED5 Write '1' to enable interrupt for TRIGGERED[5] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED6 Write '1' to enable interrupt for TRIGGERED[6] event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED7 Write '1' to enable interrupt for TRIGGERED[7] event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED8 Write '1' to enable interrupt for TRIGGERED[8] event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED9 Write '1' to enable interrupt for TRIGGERED[9] event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED10 Write '1' to enable interrupt for TRIGGERED[10] event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED11 Write '1' to enable interrupt for TRIGGERED[11] event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED12 Write '1' to enable interrupt for TRIGGERED[12] event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED13 Write '1' to enable interrupt for TRIGGERED[13] event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED14 Write '1' to enable interrupt for TRIGGERED[14] event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TRIGGERED15 Write '1' to enable interrupt for TRIGGERED[15] event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write TRIGGERED0 Write '1' to disable interrupt for TRIGGERED[0] event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED1 Write '1' to disable interrupt for TRIGGERED[1] event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED2 Write '1' to disable interrupt for TRIGGERED[2] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED3 Write '1' to disable interrupt for TRIGGERED[3] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED4 Write '1' to disable interrupt for TRIGGERED[4] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED5 Write '1' to disable interrupt for TRIGGERED[5] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED6 Write '1' to disable interrupt for TRIGGERED[6] event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED7 Write '1' to disable interrupt for TRIGGERED[7] event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED8 Write '1' to disable interrupt for TRIGGERED[8] event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED9 Write '1' to disable interrupt for TRIGGERED[9] event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED10 Write '1' to disable interrupt for TRIGGERED[10] event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED11 Write '1' to disable interrupt for TRIGGERED[11] event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED12 Write '1' to disable interrupt for TRIGGERED[12] event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED13 Write '1' to disable interrupt for TRIGGERED[13] event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED14 Write '1' to disable interrupt for TRIGGERED[14] event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TRIGGERED15 Write '1' to disable interrupt for TRIGGERED[15] event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SWI0 Software interrupt 0 0x40014000 EGU0 SWI 0 0x1000 registers SWI0_EGU0 20 SWI 0x20 UNUSED Unused. 0x000 0x00000000 read-only EGU1 Event Generator Unit 1 0x40015000 SWI1_EGU1 21 SWI1 Software interrupt 1 0x40015000 EGU1 SWI1_EGU1 21 EGU2 Event Generator Unit 2 0x40016000 SWI2_EGU2 22 SWI2 Software interrupt 2 0x40016000 EGU2 SWI2_EGU2 22 EGU3 Event Generator Unit 3 0x40017000 SWI3_EGU3 23 SWI3 Software interrupt 3 0x40017000 EGU3 SWI3_EGU3 23 EGU4 Event Generator Unit 4 0x40018000 SWI4_EGU4 24 SWI4 Software interrupt 4 0x40018000 EGU4 SWI4_EGU4 24 EGU5 Event Generator Unit 5 0x40019000 SWI5_EGU5 25 SWI5 Software interrupt 5 0x40019000 EGU5 SWI5_EGU5 25 TIMER3 Timer/Counter 3 0x4001A000 TIMER3 26 TIMER4 Timer/Counter 4 0x4001B000 TIMER4 27 PWM0 Pulse width modulation unit 0 0x4001C000 PWM 0 0x1000 registers PWM0 28 PWM 0x20 TASKS_STOP Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 0x004 write-only TASKS_STOP 0 0 0x2 0x4 TASKS_SEQSTART[%s] Description collection[n]: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. 0x008 write-only TASKS_SEQSTART 0 0 TASKS_NEXTSTEP Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. 0x010 write-only TASKS_NEXTSTEP 0 0 EVENTS_STOPPED Response to STOP task, emitted when PWM pulses are no longer generated 0x104 read-write EVENTS_STOPPED 0 0 0x2 0x4 EVENTS_SEQSTARTED[%s] Description collection[n]: First PWM period started on sequence n 0x108 read-write EVENTS_SEQSTARTED 0 0 0x2 0x4 EVENTS_SEQEND[%s] Description collection[n]: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter 0x110 read-write EVENTS_SEQEND 0 0 EVENTS_PWMPERIODEND Emitted at the end of each PWM period 0x118 read-write EVENTS_PWMPERIODEND 0 0 EVENTS_LOOPSDONE Concatenated sequences have been played the amount of times defined in LOOP.CNT 0x11C read-write EVENTS_LOOPSDONE 0 0 SHORTS Shortcut register 0x200 read-write SEQEND0_STOP Shortcut between SEQEND[0] event and STOP task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 SEQEND1_STOP Shortcut between SEQEND[1] event and STOP task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LOOPSDONE_SEQSTART0 Shortcut between LOOPSDONE event and SEQSTART[0] task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LOOPSDONE_SEQSTART1 Shortcut between LOOPSDONE event and SEQSTART[1] task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 LOOPSDONE_STOP Shortcut between LOOPSDONE event and STOP task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write STOPPED Enable or disable interrupt for STOPPED event 1 1 Disabled Disable 0 Enabled Enable 1 SEQSTARTED0 Enable or disable interrupt for SEQSTARTED[0] event 2 2 Disabled Disable 0 Enabled Enable 1 SEQSTARTED1 Enable or disable interrupt for SEQSTARTED[1] event 3 3 Disabled Disable 0 Enabled Enable 1 SEQEND0 Enable or disable interrupt for SEQEND[0] event 4 4 Disabled Disable 0 Enabled Enable 1 SEQEND1 Enable or disable interrupt for SEQEND[1] event 5 5 Disabled Disable 0 Enabled Enable 1 PWMPERIODEND Enable or disable interrupt for PWMPERIODEND event 6 6 Disabled Disable 0 Enabled Enable 1 LOOPSDONE Enable or disable interrupt for LOOPSDONE event 7 7 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STOPPED Write '1' to enable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQSTARTED0 Write '1' to enable interrupt for SEQSTARTED[0] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQSTARTED1 Write '1' to enable interrupt for SEQSTARTED[1] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQEND0 Write '1' to enable interrupt for SEQEND[0] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SEQEND1 Write '1' to enable interrupt for SEQEND[1] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PWMPERIODEND Write '1' to enable interrupt for PWMPERIODEND event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 LOOPSDONE Write '1' to enable interrupt for LOOPSDONE event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STOPPED Write '1' to disable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQSTARTED0 Write '1' to disable interrupt for SEQSTARTED[0] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQSTARTED1 Write '1' to disable interrupt for SEQSTARTED[1] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQEND0 Write '1' to disable interrupt for SEQEND[0] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SEQEND1 Write '1' to disable interrupt for SEQEND[1] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PWMPERIODEND Write '1' to disable interrupt for PWMPERIODEND event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 LOOPSDONE Write '1' to disable interrupt for LOOPSDONE event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE PWM module enable register 0x500 read-write 0x00000000 ENABLE Enable or disable PWM module 0 0 Disabled Disabled 0 Enabled Enable 1 MODE Selects operating mode of the wave counter 0x504 read-write 0x00000000 UPDOWN Selects up mode or up-and-down mode for the counter 0 0 Up Up counter, edge-aligned PWM duty cycle 0 UpAndDown Up and down counter, center-aligned PWM duty cycle 1 COUNTERTOP Value up to which the pulse generator counter counts 0x508 read-write 0x000003FF COUNTERTOP Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 0 14 PRESCALER Configuration for PWM_CLK 0x50C read-write 0x00000000 PRESCALER Prescaler of PWM_CLK 0 2 DIV_1 Divide by 1 (16 MHz) 0 DIV_2 Divide by 2 (8 MHz) 1 DIV_4 Divide by 4 (4 MHz) 2 DIV_8 Divide by 8 (2 MHz) 3 DIV_16 Divide by 16 (1 MHz) 4 DIV_32 Divide by 32 (500 kHz) 5 DIV_64 Divide by 64 (250 kHz) 6 DIV_128 Divide by 128 (125 kHz) 7 DECODER Configuration of the decoder 0x510 read-write 0x00000000 LOAD How a sequence is read from RAM and spread to the compare register 0 1 Common 1st half word (16-bit) used in all PWM channels 0..3 0 Grouped 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 1 Individual 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 2 WaveForm 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP 3 MODE Selects source for advancing the active sequence 8 8 RefreshCount SEQ[n].REFRESH is used to determine loading internal compare registers 0 NextStep NEXTSTEP task causes a new value to be loaded to internal compare registers 1 LOOP Number of playbacks of a loop 0x514 read-write 0x00000000 CNT Number of playbacks of pattern cycles 0 15 Disabled Looping disabled (stop at the end of the sequence) 0 2 0x020 SEQ[%s] Unspecified PWM_SEQ 0x520 PTR Description cluster[n]: Beginning address in RAM of this sequence 0x000 read-write 0x00000000 PTR Beginning address in RAM of this sequence 0 31 CNT Description cluster[n]: Number of values (duty cycles) in this sequence 0x004 read-write 0x00000000 CNT Number of values (duty cycles) in this sequence 0 14 Disabled Sequence is disabled, and shall not be started as it is empty 0 REFRESH Description cluster[n]: Number of additional PWM periods between samples loaded into compare register 0x008 read-write 0x00000001 CNT Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) 0 23 Continuous Update every PWM period 0 ENDDELAY Description cluster[n]: Time added after the sequence 0x00C read-write 0x00000000 CNT Time added after the sequence in PWM periods 0 23 PSEL Unspecified PWM_PSEL 0x560 0x4 0x4 OUT[%s] Description collection[n]: Output pin select for PWM channel n 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 PDM Pulse Density Modulation (Digital Microphone) Interface 0x4001D000 0 0x1000 registers PDM 29 PDM 0x20 TASKS_START Starts continuous PDM transfer 0x000 write-only TASKS_START 0 0 TASKS_STOP Stops PDM transfer 0x004 write-only TASKS_STOP 0 0 EVENTS_STARTED PDM transfer has started 0x100 read-write EVENTS_STARTED 0 0 EVENTS_STOPPED PDM transfer has finished 0x104 read-write EVENTS_STOPPED 0 0 EVENTS_END The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM 0x108 read-write EVENTS_END 0 0 INTEN Enable or disable interrupt 0x300 read-write STARTED Enable or disable interrupt for STARTED event 0 0 Disabled Disable 0 Enabled Enable 1 STOPPED Enable or disable interrupt for STOPPED event 1 1 Disabled Disable 0 Enabled Enable 1 END Enable or disable interrupt for END event 2 2 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write STARTED Write '1' to enable interrupt for STARTED event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 END Write '1' to enable interrupt for END event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write STARTED Write '1' to disable interrupt for STARTED event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for STOPPED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 END Write '1' to disable interrupt for END event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE PDM module enable register 0x500 read-write 0x00000000 ENABLE Enable or disable PDM module 0 0 Disabled Disable 0 Enabled Enable 1 PDMCLKCTRL PDM clock generator control 0x504 read-write 0x08400000 FREQ PDM_CLK frequency 0 31 1000K PDM_CLK = 32 MHz / 32 = 1.000 MHz 0x08000000 Default PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64. 0x08400000 1067K PDM_CLK = 32 MHz / 30 = 1.067 MHz 0x08800000 1231K PDM_CLK = 32 MHz / 26 = 1.231 MHz 0x09800000 1280K PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. 0x0A000000 1333K PDM_CLK = 32 MHz / 24 = 1.333 MHz 0x0A800000 MODE Defines the routing of the connected PDM microphones' signals 0x508 read-write 0x00000000 OPERATION Mono or stereo operation 0 0 Stereo Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] 0 Mono Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] 1 EDGE Defines on which PDM_CLK edge Left (or mono) is sampled 1 1 LeftFalling Left (or mono) is sampled on falling edge of PDM_CLK 0 LeftRising Left (or mono) is sampled on rising edge of PDM_CLK 1 GAINL Left output gain adjustment 0x518 read-write 0x00000028 GAINL Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust 0 6 MinGain -20dB gain adjustment (minimum) 0x00 DefaultGain 0dB gain adjustment 0x28 MaxGain +20dB gain adjustment (maximum) 0x50 GAINR Right output gain adjustment 0x51C read-write 0x00000028 GAINR Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0 6 MinGain -20dB gain adjustment (minimum) 0x00 DefaultGain 0dB gain adjustment 0x28 MaxGain +20dB gain adjustment (maximum) 0x50 RATIO Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. 0x520 read-write 0x00000000 RATIO Selects the ratio between PDM_CLK and output sample rate 0 0 Ratio64 Ratio of 64 0 Ratio80 Ratio of 80 1 PSEL Unspecified PDM_PSEL 0x540 CLK Pin number configuration for PDM CLK signal 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 DIN Pin number configuration for PDM DIN signal 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SAMPLE Unspecified PDM_SAMPLE 0x560 PTR RAM address pointer to write samples to with EasyDMA 0x000 read-write SAMPLEPTR Address to write PDM samples to over DMA 0 31 MAXCNT Number of samples to allocate memory for in EasyDMA mode 0x004 read-write BUFFSIZE Length of DMA RAM allocation in number of samples 0 14 ACL Access control lists 0x4001E000 0 0x1000 registers ACL 0x20 8 0x010 ACL[%s] Unspecified ACL_ACL 0x800 ADDR Description cluster[n]: Configure the word-aligned start address of region n to protect 0x000 read-write 0x00000000 ADDR Valid word-aligned start address of region n to protect. Address must point to a flash page boundary. 0 31 SIZE Description cluster[n]: Size of region to protect counting from address ACL[n].ADDR. Write '0' as no effect. 0x004 read-write 0x00000000 SIZE Size of flash region n in bytes. Must be a multiple of the flash page size, and the maximum region size is limited to 512kB. 0 31 PERM Description cluster[n]: Access permissions for region n as defined by start address ACL[n].ADDR and size ACL[n].SIZE 0x008 read-write 0x00000000 WRITE Configure write and erase permissions for region n. Write '0' has no effect. 1 1 Enable Allow write and erase instructions to region n 0 Disable Block write and erase instructions to region n 1 READ Configure read permissions for region n. Write '0' has no effect. 2 2 Enable Allow read instructions to region n 0 Disable Block read instructions to region n 1 UNUSED0 Unspecified 0x00C read-write NVMC Non Volatile Memory Controller 0x4001E000 ACL 0 0x1000 registers NVMC 0x20 READY Ready flag 0x400 read-only 0x00000001 READY NVMC is ready or busy 0 0 Busy NVMC is busy (on-going write or erase operation) 0 Ready NVMC is ready 1 READYNEXT Ready flag 0x408 read-only READYNEXT NVMC can accept a new write operation 0 0 Busy NVMC cannot accept any write operation 0 Ready NVMC is ready 1 CONFIG Configuration register 0x504 read-write WEN Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. 0 1 Ren Read only access 0 Wen Write enabled 1 Een Erase enabled 2 ERASEPAGE Register for erasing a page in code area 0x508 read-write ERASEPAGE Register for starting erase of a page in code area 0 31 ERASEPCR1 Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. 0x508 read-write ERASEPAGE ERASEPCR1 Register for erasing a page in code area. Equivalent to ERASEPAGE. 0 31 ERASEALL Register for erasing all non-volatile user memory 0x50C read-write ERASEALL Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased. 0 0 NoOperation No operation 0 Erase Start chip erase 1 ERASEPCR0 Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE. 0x510 read-write ERASEPCR0 Register for starting erase of a page in code area. Equivalent to ERASEPAGE. 0 31 ERASEUICR Register for erasing user information configuration registers 0x514 read-write ERASEUICR Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased. 0 0 NoOperation No operation 0 Erase Start erase of UICR 1 ERASEPAGEPARTIAL Register for partial erase of a page in code area 0x518 read-write ERASEPAGEPARTIAL Register for starting partial erase of a page in code area 0 31 ERASEPAGEPARTIALCFG Register for partial erase configuration 0x51C read-write 0x0000000A DURATION Duration of the partial erase in milliseconds 0 6 ICACHECNF I-code cache configuration register. 0x540 read-write 0x00000000 CACHEEN Cache enable 0 0 Disabled Disable cache. Invalidates all cache entries. 0 Enabled Enable cache 1 CACHEPROFEN Cache profiling enable 8 8 Disabled Disable cache profiling 0 Enabled Enable cache profiling 1 IHIT I-code cache hit counter. 0x548 read-write HITS Number of cache hits 0 31 IMISS I-code cache miss counter. 0x54C read-write MISSES Number of cache misses 0 31 PPI Programmable Peripheral Interconnect 0x4001F000 0 0x1000 registers PPI 0x20 6 0x008 TASKS_CHG[%s] Channel group tasks PPI_TASKS_CHG 0x000 EN Description cluster[n]: Enable channel group n 0x000 write-only EN 0 0 DIS Description cluster[n]: Disable channel group n 0x004 write-only DIS 0 0 CHEN Channel enable register 0x500 read-write CH0 Enable or disable channel 0 0 0 Disabled Disable channel 0 Enabled Enable channel 1 CH1 Enable or disable channel 1 1 1 Disabled Disable channel 0 Enabled Enable channel 1 CH2 Enable or disable channel 2 2 2 Disabled Disable channel 0 Enabled Enable channel 1 CH3 Enable or disable channel 3 3 3 Disabled Disable channel 0 Enabled Enable channel 1 CH4 Enable or disable channel 4 4 4 Disabled Disable channel 0 Enabled Enable channel 1 CH5 Enable or disable channel 5 5 5 Disabled Disable channel 0 Enabled Enable channel 1 CH6 Enable or disable channel 6 6 6 Disabled Disable channel 0 Enabled Enable channel 1 CH7 Enable or disable channel 7 7 7 Disabled Disable channel 0 Enabled Enable channel 1 CH8 Enable or disable channel 8 8 8 Disabled Disable channel 0 Enabled Enable channel 1 CH9 Enable or disable channel 9 9 9 Disabled Disable channel 0 Enabled Enable channel 1 CH10 Enable or disable channel 10 10 10 Disabled Disable channel 0 Enabled Enable channel 1 CH11 Enable or disable channel 11 11 11 Disabled Disable channel 0 Enabled Enable channel 1 CH12 Enable or disable channel 12 12 12 Disabled Disable channel 0 Enabled Enable channel 1 CH13 Enable or disable channel 13 13 13 Disabled Disable channel 0 Enabled Enable channel 1 CH14 Enable or disable channel 14 14 14 Disabled Disable channel 0 Enabled Enable channel 1 CH15 Enable or disable channel 15 15 15 Disabled Disable channel 0 Enabled Enable channel 1 CH16 Enable or disable channel 16 16 16 Disabled Disable channel 0 Enabled Enable channel 1 CH17 Enable or disable channel 17 17 17 Disabled Disable channel 0 Enabled Enable channel 1 CH18 Enable or disable channel 18 18 18 Disabled Disable channel 0 Enabled Enable channel 1 CH19 Enable or disable channel 19 19 19 Disabled Disable channel 0 Enabled Enable channel 1 CH20 Enable or disable channel 20 20 20 Disabled Disable channel 0 Enabled Enable channel 1 CH21 Enable or disable channel 21 21 21 Disabled Disable channel 0 Enabled Enable channel 1 CH22 Enable or disable channel 22 22 22 Disabled Disable channel 0 Enabled Enable channel 1 CH23 Enable or disable channel 23 23 23 Disabled Disable channel 0 Enabled Enable channel 1 CH24 Enable or disable channel 24 24 24 Disabled Disable channel 0 Enabled Enable channel 1 CH25 Enable or disable channel 25 25 25 Disabled Disable channel 0 Enabled Enable channel 1 CH26 Enable or disable channel 26 26 26 Disabled Disable channel 0 Enabled Enable channel 1 CH27 Enable or disable channel 27 27 27 Disabled Disable channel 0 Enabled Enable channel 1 CH28 Enable or disable channel 28 28 28 Disabled Disable channel 0 Enabled Enable channel 1 CH29 Enable or disable channel 29 29 29 Disabled Disable channel 0 Enabled Enable channel 1 CH30 Enable or disable channel 30 30 30 Disabled Disable channel 0 Enabled Enable channel 1 CH31 Enable or disable channel 31 31 31 Disabled Disable channel 0 Enabled Enable channel 1 CHENSET Channel enable set register 0x504 read-write oneToSet CH0 Channel 0 enable set register. Writing '0' has no effect 0 0 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH1 Channel 1 enable set register. Writing '0' has no effect 1 1 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH2 Channel 2 enable set register. Writing '0' has no effect 2 2 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH3 Channel 3 enable set register. Writing '0' has no effect 3 3 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH4 Channel 4 enable set register. Writing '0' has no effect 4 4 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH5 Channel 5 enable set register. Writing '0' has no effect 5 5 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH6 Channel 6 enable set register. Writing '0' has no effect 6 6 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH7 Channel 7 enable set register. Writing '0' has no effect 7 7 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH8 Channel 8 enable set register. Writing '0' has no effect 8 8 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH9 Channel 9 enable set register. Writing '0' has no effect 9 9 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH10 Channel 10 enable set register. Writing '0' has no effect 10 10 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH11 Channel 11 enable set register. Writing '0' has no effect 11 11 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH12 Channel 12 enable set register. Writing '0' has no effect 12 12 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH13 Channel 13 enable set register. Writing '0' has no effect 13 13 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH14 Channel 14 enable set register. Writing '0' has no effect 14 14 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH15 Channel 15 enable set register. Writing '0' has no effect 15 15 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH16 Channel 16 enable set register. Writing '0' has no effect 16 16 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH17 Channel 17 enable set register. Writing '0' has no effect 17 17 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH18 Channel 18 enable set register. Writing '0' has no effect 18 18 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH19 Channel 19 enable set register. Writing '0' has no effect 19 19 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH20 Channel 20 enable set register. Writing '0' has no effect 20 20 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH21 Channel 21 enable set register. Writing '0' has no effect 21 21 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH22 Channel 22 enable set register. Writing '0' has no effect 22 22 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH23 Channel 23 enable set register. Writing '0' has no effect 23 23 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH24 Channel 24 enable set register. Writing '0' has no effect 24 24 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH25 Channel 25 enable set register. Writing '0' has no effect 25 25 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH26 Channel 26 enable set register. Writing '0' has no effect 26 26 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH27 Channel 27 enable set register. Writing '0' has no effect 27 27 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH28 Channel 28 enable set register. Writing '0' has no effect 28 28 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH29 Channel 29 enable set register. Writing '0' has no effect 29 29 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH30 Channel 30 enable set register. Writing '0' has no effect 30 30 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CH31 Channel 31 enable set register. Writing '0' has no effect 31 31 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Set Write: Enable channel 1 CHENCLR Channel enable clear register 0x508 read-write oneToClear CH0 Channel 0 enable clear register. Writing '0' has no effect 0 0 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH1 Channel 1 enable clear register. Writing '0' has no effect 1 1 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH2 Channel 2 enable clear register. Writing '0' has no effect 2 2 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH3 Channel 3 enable clear register. Writing '0' has no effect 3 3 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH4 Channel 4 enable clear register. Writing '0' has no effect 4 4 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH5 Channel 5 enable clear register. Writing '0' has no effect 5 5 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH6 Channel 6 enable clear register. Writing '0' has no effect 6 6 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH7 Channel 7 enable clear register. Writing '0' has no effect 7 7 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH8 Channel 8 enable clear register. Writing '0' has no effect 8 8 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH9 Channel 9 enable clear register. Writing '0' has no effect 9 9 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH10 Channel 10 enable clear register. Writing '0' has no effect 10 10 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH11 Channel 11 enable clear register. Writing '0' has no effect 11 11 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH12 Channel 12 enable clear register. Writing '0' has no effect 12 12 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH13 Channel 13 enable clear register. Writing '0' has no effect 13 13 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH14 Channel 14 enable clear register. Writing '0' has no effect 14 14 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH15 Channel 15 enable clear register. Writing '0' has no effect 15 15 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH16 Channel 16 enable clear register. Writing '0' has no effect 16 16 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH17 Channel 17 enable clear register. Writing '0' has no effect 17 17 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH18 Channel 18 enable clear register. Writing '0' has no effect 18 18 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH19 Channel 19 enable clear register. Writing '0' has no effect 19 19 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH20 Channel 20 enable clear register. Writing '0' has no effect 20 20 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH21 Channel 21 enable clear register. Writing '0' has no effect 21 21 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH22 Channel 22 enable clear register. Writing '0' has no effect 22 22 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH23 Channel 23 enable clear register. Writing '0' has no effect 23 23 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH24 Channel 24 enable clear register. Writing '0' has no effect 24 24 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH25 Channel 25 enable clear register. Writing '0' has no effect 25 25 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH26 Channel 26 enable clear register. Writing '0' has no effect 26 26 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH27 Channel 27 enable clear register. Writing '0' has no effect 27 27 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH28 Channel 28 enable clear register. Writing '0' has no effect 28 28 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH29 Channel 29 enable clear register. Writing '0' has no effect 29 29 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH30 Channel 30 enable clear register. Writing '0' has no effect 30 30 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 CH31 Channel 31 enable clear register. Writing '0' has no effect 31 31 read Disabled Read: channel disabled 0 Enabled Read: channel enabled 1 write Clear Write: disable channel 1 20 0x008 CH[%s] PPI Channel PPI_CH 0x510 EEP Description cluster[n]: Channel n event end-point 0x000 read-write EEP Pointer to event register. Accepts only addresses to registers from the Event group. 0 31 TEP Description cluster[n]: Channel n task end-point 0x004 read-write TEP Pointer to task register. Accepts only addresses to registers from the Task group. 0 31 0x6 0x4 CHG[%s] Description collection[n]: Channel group n 0x800 read-write CH0 Include or exclude channel 0 0 0 Excluded Exclude 0 Included Include 1 CH1 Include or exclude channel 1 1 1 Excluded Exclude 0 Included Include 1 CH2 Include or exclude channel 2 2 2 Excluded Exclude 0 Included Include 1 CH3 Include or exclude channel 3 3 3 Excluded Exclude 0 Included Include 1 CH4 Include or exclude channel 4 4 4 Excluded Exclude 0 Included Include 1 CH5 Include or exclude channel 5 5 5 Excluded Exclude 0 Included Include 1 CH6 Include or exclude channel 6 6 6 Excluded Exclude 0 Included Include 1 CH7 Include or exclude channel 7 7 7 Excluded Exclude 0 Included Include 1 CH8 Include or exclude channel 8 8 8 Excluded Exclude 0 Included Include 1 CH9 Include or exclude channel 9 9 9 Excluded Exclude 0 Included Include 1 CH10 Include or exclude channel 10 10 10 Excluded Exclude 0 Included Include 1 CH11 Include or exclude channel 11 11 11 Excluded Exclude 0 Included Include 1 CH12 Include or exclude channel 12 12 12 Excluded Exclude 0 Included Include 1 CH13 Include or exclude channel 13 13 13 Excluded Exclude 0 Included Include 1 CH14 Include or exclude channel 14 14 14 Excluded Exclude 0 Included Include 1 CH15 Include or exclude channel 15 15 15 Excluded Exclude 0 Included Include 1 CH16 Include or exclude channel 16 16 16 Excluded Exclude 0 Included Include 1 CH17 Include or exclude channel 17 17 17 Excluded Exclude 0 Included Include 1 CH18 Include or exclude channel 18 18 18 Excluded Exclude 0 Included Include 1 CH19 Include or exclude channel 19 19 19 Excluded Exclude 0 Included Include 1 CH20 Include or exclude channel 20 20 20 Excluded Exclude 0 Included Include 1 CH21 Include or exclude channel 21 21 21 Excluded Exclude 0 Included Include 1 CH22 Include or exclude channel 22 22 22 Excluded Exclude 0 Included Include 1 CH23 Include or exclude channel 23 23 23 Excluded Exclude 0 Included Include 1 CH24 Include or exclude channel 24 24 24 Excluded Exclude 0 Included Include 1 CH25 Include or exclude channel 25 25 25 Excluded Exclude 0 Included Include 1 CH26 Include or exclude channel 26 26 26 Excluded Exclude 0 Included Include 1 CH27 Include or exclude channel 27 27 27 Excluded Exclude 0 Included Include 1 CH28 Include or exclude channel 28 28 28 Excluded Exclude 0 Included Include 1 CH29 Include or exclude channel 29 29 29 Excluded Exclude 0 Included Include 1 CH30 Include or exclude channel 30 30 30 Excluded Exclude 0 Included Include 1 CH31 Include or exclude channel 31 31 31 Excluded Exclude 0 Included Include 1 32 0x004 FORK[%s] Fork PPI_FORK 0x910 TEP Description cluster[n]: Channel n task end-point 0x000 read-write TEP Pointer to task register 0 31 MWU Memory Watch Unit 0x40020000 0 0x1000 registers MWU 32 MWU 0x20 4 0x008 EVENTS_REGION[%s] Unspecified MWU_EVENTS_REGION 0x100 WA Description cluster[n]: Write access to region n detected 0x000 read-write WA 0 0 RA Description cluster[n]: Read access to region n detected 0x004 read-write RA 0 0 2 0x008 EVENTS_PREGION[%s] Unspecified MWU_EVENTS_PREGION 0x160 WA Description cluster[n]: Write access to peripheral region n detected 0x000 read-write WA 0 0 RA Description cluster[n]: Read access to peripheral region n detected 0x004 read-write RA 0 0 INTEN Enable or disable interrupt 0x300 read-write REGION0WA Enable or disable interrupt for REGION[0].WA event 0 0 Disabled Disable 0 Enabled Enable 1 REGION0RA Enable or disable interrupt for REGION[0].RA event 1 1 Disabled Disable 0 Enabled Enable 1 REGION1WA Enable or disable interrupt for REGION[1].WA event 2 2 Disabled Disable 0 Enabled Enable 1 REGION1RA Enable or disable interrupt for REGION[1].RA event 3 3 Disabled Disable 0 Enabled Enable 1 REGION2WA Enable or disable interrupt for REGION[2].WA event 4 4 Disabled Disable 0 Enabled Enable 1 REGION2RA Enable or disable interrupt for REGION[2].RA event 5 5 Disabled Disable 0 Enabled Enable 1 REGION3WA Enable or disable interrupt for REGION[3].WA event 6 6 Disabled Disable 0 Enabled Enable 1 REGION3RA Enable or disable interrupt for REGION[3].RA event 7 7 Disabled Disable 0 Enabled Enable 1 PREGION0WA Enable or disable interrupt for PREGION[0].WA event 24 24 Disabled Disable 0 Enabled Enable 1 PREGION0RA Enable or disable interrupt for PREGION[0].RA event 25 25 Disabled Disable 0 Enabled Enable 1 PREGION1WA Enable or disable interrupt for PREGION[1].WA event 26 26 Disabled Disable 0 Enabled Enable 1 PREGION1RA Enable or disable interrupt for PREGION[1].RA event 27 27 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write REGION0WA Write '1' to enable interrupt for REGION[0].WA event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION0RA Write '1' to enable interrupt for REGION[0].RA event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION1WA Write '1' to enable interrupt for REGION[1].WA event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION1RA Write '1' to enable interrupt for REGION[1].RA event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION2WA Write '1' to enable interrupt for REGION[2].WA event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION2RA Write '1' to enable interrupt for REGION[2].RA event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION3WA Write '1' to enable interrupt for REGION[3].WA event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION3RA Write '1' to enable interrupt for REGION[3].RA event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION0WA Write '1' to enable interrupt for PREGION[0].WA event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION0RA Write '1' to enable interrupt for PREGION[0].RA event 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION1WA Write '1' to enable interrupt for PREGION[1].WA event 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION1RA Write '1' to enable interrupt for PREGION[1].RA event 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write REGION0WA Write '1' to disable interrupt for REGION[0].WA event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION0RA Write '1' to disable interrupt for REGION[0].RA event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION1WA Write '1' to disable interrupt for REGION[1].WA event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION1RA Write '1' to disable interrupt for REGION[1].RA event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION2WA Write '1' to disable interrupt for REGION[2].WA event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION2RA Write '1' to disable interrupt for REGION[2].RA event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION3WA Write '1' to disable interrupt for REGION[3].WA event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION3RA Write '1' to disable interrupt for REGION[3].RA event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION0WA Write '1' to disable interrupt for PREGION[0].WA event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION0RA Write '1' to disable interrupt for PREGION[0].RA event 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION1WA Write '1' to disable interrupt for PREGION[1].WA event 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION1RA Write '1' to disable interrupt for PREGION[1].RA event 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 NMIEN Enable or disable non-maskable interrupt 0x320 read-write REGION0WA Enable or disable non-maskable interrupt for REGION[0].WA event 0 0 Disabled Disable 0 Enabled Enable 1 REGION0RA Enable or disable non-maskable interrupt for REGION[0].RA event 1 1 Disabled Disable 0 Enabled Enable 1 REGION1WA Enable or disable non-maskable interrupt for REGION[1].WA event 2 2 Disabled Disable 0 Enabled Enable 1 REGION1RA Enable or disable non-maskable interrupt for REGION[1].RA event 3 3 Disabled Disable 0 Enabled Enable 1 REGION2WA Enable or disable non-maskable interrupt for REGION[2].WA event 4 4 Disabled Disable 0 Enabled Enable 1 REGION2RA Enable or disable non-maskable interrupt for REGION[2].RA event 5 5 Disabled Disable 0 Enabled Enable 1 REGION3WA Enable or disable non-maskable interrupt for REGION[3].WA event 6 6 Disabled Disable 0 Enabled Enable 1 REGION3RA Enable or disable non-maskable interrupt for REGION[3].RA event 7 7 Disabled Disable 0 Enabled Enable 1 PREGION0WA Enable or disable non-maskable interrupt for PREGION[0].WA event 24 24 Disabled Disable 0 Enabled Enable 1 PREGION0RA Enable or disable non-maskable interrupt for PREGION[0].RA event 25 25 Disabled Disable 0 Enabled Enable 1 PREGION1WA Enable or disable non-maskable interrupt for PREGION[1].WA event 26 26 Disabled Disable 0 Enabled Enable 1 PREGION1RA Enable or disable non-maskable interrupt for PREGION[1].RA event 27 27 Disabled Disable 0 Enabled Enable 1 NMIENSET Enable non-maskable interrupt 0x324 read-write REGION0WA Write '1' to enable non-maskable interrupt for REGION[0].WA event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION0RA Write '1' to enable non-maskable interrupt for REGION[0].RA event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION1WA Write '1' to enable non-maskable interrupt for REGION[1].WA event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION1RA Write '1' to enable non-maskable interrupt for REGION[1].RA event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION2WA Write '1' to enable non-maskable interrupt for REGION[2].WA event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION2RA Write '1' to enable non-maskable interrupt for REGION[2].RA event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION3WA Write '1' to enable non-maskable interrupt for REGION[3].WA event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 REGION3RA Write '1' to enable non-maskable interrupt for REGION[3].RA event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION0WA Write '1' to enable non-maskable interrupt for PREGION[0].WA event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION0RA Write '1' to enable non-maskable interrupt for PREGION[0].RA event 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION1WA Write '1' to enable non-maskable interrupt for PREGION[1].WA event 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 PREGION1RA Write '1' to enable non-maskable interrupt for PREGION[1].RA event 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 NMIENCLR Disable non-maskable interrupt 0x328 read-write REGION0WA Write '1' to disable non-maskable interrupt for REGION[0].WA event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION0RA Write '1' to disable non-maskable interrupt for REGION[0].RA event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION1WA Write '1' to disable non-maskable interrupt for REGION[1].WA event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION1RA Write '1' to disable non-maskable interrupt for REGION[1].RA event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION2WA Write '1' to disable non-maskable interrupt for REGION[2].WA event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION2RA Write '1' to disable non-maskable interrupt for REGION[2].RA event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION3WA Write '1' to disable non-maskable interrupt for REGION[3].WA event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 REGION3RA Write '1' to disable non-maskable interrupt for REGION[3].RA event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION0WA Write '1' to disable non-maskable interrupt for PREGION[0].WA event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION0RA Write '1' to disable non-maskable interrupt for PREGION[0].RA event 25 25 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION1WA Write '1' to disable non-maskable interrupt for PREGION[1].WA event 26 26 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 PREGION1RA Write '1' to disable non-maskable interrupt for PREGION[1].RA event 27 27 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 2 0x008 PERREGION[%s] Unspecified MWU_PERREGION 0x400 SUBSTATWA Description cluster[n]: Source of event/interrupt in region n, write access detected while corresponding subregion was enabled for watching 0x000 read-write oneToClear SR0 Subregion 0 in region n (write '1' to clear) 0 0 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR1 Subregion 1 in region n (write '1' to clear) 1 1 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR2 Subregion 2 in region n (write '1' to clear) 2 2 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR3 Subregion 3 in region n (write '1' to clear) 3 3 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR4 Subregion 4 in region n (write '1' to clear) 4 4 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR5 Subregion 5 in region n (write '1' to clear) 5 5 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR6 Subregion 6 in region n (write '1' to clear) 6 6 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR7 Subregion 7 in region n (write '1' to clear) 7 7 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR8 Subregion 8 in region n (write '1' to clear) 8 8 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR9 Subregion 9 in region n (write '1' to clear) 9 9 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR10 Subregion 10 in region n (write '1' to clear) 10 10 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR11 Subregion 11 in region n (write '1' to clear) 11 11 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR12 Subregion 12 in region n (write '1' to clear) 12 12 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR13 Subregion 13 in region n (write '1' to clear) 13 13 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR14 Subregion 14 in region n (write '1' to clear) 14 14 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR15 Subregion 15 in region n (write '1' to clear) 15 15 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR16 Subregion 16 in region n (write '1' to clear) 16 16 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR17 Subregion 17 in region n (write '1' to clear) 17 17 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR18 Subregion 18 in region n (write '1' to clear) 18 18 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR19 Subregion 19 in region n (write '1' to clear) 19 19 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR20 Subregion 20 in region n (write '1' to clear) 20 20 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR21 Subregion 21 in region n (write '1' to clear) 21 21 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR22 Subregion 22 in region n (write '1' to clear) 22 22 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR23 Subregion 23 in region n (write '1' to clear) 23 23 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR24 Subregion 24 in region n (write '1' to clear) 24 24 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR25 Subregion 25 in region n (write '1' to clear) 25 25 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR26 Subregion 26 in region n (write '1' to clear) 26 26 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR27 Subregion 27 in region n (write '1' to clear) 27 27 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR28 Subregion 28 in region n (write '1' to clear) 28 28 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR29 Subregion 29 in region n (write '1' to clear) 29 29 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR30 Subregion 30 in region n (write '1' to clear) 30 30 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SR31 Subregion 31 in region n (write '1' to clear) 31 31 NoAccess No write access occurred in this subregion 0 Access Write access(es) occurred in this subregion 1 SUBSTATRA Description cluster[n]: Source of event/interrupt in region n, read access detected while corresponding subregion was enabled for watching 0x004 read-write oneToClear SR0 Subregion 0 in region n (write '1' to clear) 0 0 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR1 Subregion 1 in region n (write '1' to clear) 1 1 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR2 Subregion 2 in region n (write '1' to clear) 2 2 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR3 Subregion 3 in region n (write '1' to clear) 3 3 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR4 Subregion 4 in region n (write '1' to clear) 4 4 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR5 Subregion 5 in region n (write '1' to clear) 5 5 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR6 Subregion 6 in region n (write '1' to clear) 6 6 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR7 Subregion 7 in region n (write '1' to clear) 7 7 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR8 Subregion 8 in region n (write '1' to clear) 8 8 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR9 Subregion 9 in region n (write '1' to clear) 9 9 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR10 Subregion 10 in region n (write '1' to clear) 10 10 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR11 Subregion 11 in region n (write '1' to clear) 11 11 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR12 Subregion 12 in region n (write '1' to clear) 12 12 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR13 Subregion 13 in region n (write '1' to clear) 13 13 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR14 Subregion 14 in region n (write '1' to clear) 14 14 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR15 Subregion 15 in region n (write '1' to clear) 15 15 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR16 Subregion 16 in region n (write '1' to clear) 16 16 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR17 Subregion 17 in region n (write '1' to clear) 17 17 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR18 Subregion 18 in region n (write '1' to clear) 18 18 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR19 Subregion 19 in region n (write '1' to clear) 19 19 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR20 Subregion 20 in region n (write '1' to clear) 20 20 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR21 Subregion 21 in region n (write '1' to clear) 21 21 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR22 Subregion 22 in region n (write '1' to clear) 22 22 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR23 Subregion 23 in region n (write '1' to clear) 23 23 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR24 Subregion 24 in region n (write '1' to clear) 24 24 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR25 Subregion 25 in region n (write '1' to clear) 25 25 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR26 Subregion 26 in region n (write '1' to clear) 26 26 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR27 Subregion 27 in region n (write '1' to clear) 27 27 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR28 Subregion 28 in region n (write '1' to clear) 28 28 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR29 Subregion 29 in region n (write '1' to clear) 29 29 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR30 Subregion 30 in region n (write '1' to clear) 30 30 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 SR31 Subregion 31 in region n (write '1' to clear) 31 31 NoAccess No read access occurred in this subregion 0 Access Read access(es) occurred in this subregion 1 REGIONEN Enable/disable regions watch 0x510 read-write RGN0WA Enable/disable write access watch in region[0] 0 0 Disable Disable write access watch in this region 0 Enable Enable write access watch in this region 1 RGN0RA Enable/disable read access watch in region[0] 1 1 Disable Disable read access watch in this region 0 Enable Enable read access watch in this region 1 RGN1WA Enable/disable write access watch in region[1] 2 2 Disable Disable write access watch in this region 0 Enable Enable write access watch in this region 1 RGN1RA Enable/disable read access watch in region[1] 3 3 Disable Disable read access watch in this region 0 Enable Enable read access watch in this region 1 RGN2WA Enable/disable write access watch in region[2] 4 4 Disable Disable write access watch in this region 0 Enable Enable write access watch in this region 1 RGN2RA Enable/disable read access watch in region[2] 5 5 Disable Disable read access watch in this region 0 Enable Enable read access watch in this region 1 RGN3WA Enable/disable write access watch in region[3] 6 6 Disable Disable write access watch in this region 0 Enable Enable write access watch in this region 1 RGN3RA Enable/disable read access watch in region[3] 7 7 Disable Disable read access watch in this region 0 Enable Enable read access watch in this region 1 PRGN0WA Enable/disable write access watch in PREGION[0] 24 24 Disable Disable write access watch in this PREGION 0 Enable Enable write access watch in this PREGION 1 PRGN0RA Enable/disable read access watch in PREGION[0] 25 25 Disable Disable read access watch in this PREGION 0 Enable Enable read access watch in this PREGION 1 PRGN1WA Enable/disable write access watch in PREGION[1] 26 26 Disable Disable write access watch in this PREGION 0 Enable Enable write access watch in this PREGION 1 PRGN1RA Enable/disable read access watch in PREGION[1] 27 27 Disable Disable read access watch in this PREGION 0 Enable Enable read access watch in this PREGION 1 REGIONENSET Enable regions watch 0x514 read-write RGN0WA Enable write access watch in region[0] 0 0 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Set Enable write access watch in this region 1 RGN0RA Enable read access watch in region[0] 1 1 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Set Enable read access watch in this region 1 RGN1WA Enable write access watch in region[1] 2 2 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Set Enable write access watch in this region 1 RGN1RA Enable read access watch in region[1] 3 3 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Set Enable read access watch in this region 1 RGN2WA Enable write access watch in region[2] 4 4 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Set Enable write access watch in this region 1 RGN2RA Enable read access watch in region[2] 5 5 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Set Enable read access watch in this region 1 RGN3WA Enable write access watch in region[3] 6 6 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Set Enable write access watch in this region 1 RGN3RA Enable read access watch in region[3] 7 7 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Set Enable read access watch in this region 1 PRGN0WA Enable write access watch in PREGION[0] 24 24 read Disabled Write access watch in this PREGION is disabled 0 Enabled Write access watch in this PREGION is enabled 1 write Set Enable write access watch in this PREGION 1 PRGN0RA Enable read access watch in PREGION[0] 25 25 read Disabled Read access watch in this PREGION is disabled 0 Enabled Read access watch in this PREGION is enabled 1 write Set Enable read access watch in this PREGION 1 PRGN1WA Enable write access watch in PREGION[1] 26 26 read Disabled Write access watch in this PREGION is disabled 0 Enabled Write access watch in this PREGION is enabled 1 write Set Enable write access watch in this PREGION 1 PRGN1RA Enable read access watch in PREGION[1] 27 27 read Disabled Read access watch in this PREGION is disabled 0 Enabled Read access watch in this PREGION is enabled 1 write Set Enable read access watch in this PREGION 1 REGIONENCLR Disable regions watch 0x518 read-write RGN0WA Disable write access watch in region[0] 0 0 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Clear Disable write access watch in this region 1 RGN0RA Disable read access watch in region[0] 1 1 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Clear Disable read access watch in this region 1 RGN1WA Disable write access watch in region[1] 2 2 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Clear Disable write access watch in this region 1 RGN1RA Disable read access watch in region[1] 3 3 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Clear Disable read access watch in this region 1 RGN2WA Disable write access watch in region[2] 4 4 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Clear Disable write access watch in this region 1 RGN2RA Disable read access watch in region[2] 5 5 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Clear Disable read access watch in this region 1 RGN3WA Disable write access watch in region[3] 6 6 read Disabled Write access watch in this region is disabled 0 Enabled Write access watch in this region is enabled 1 write Clear Disable write access watch in this region 1 RGN3RA Disable read access watch in region[3] 7 7 read Disabled Read access watch in this region is disabled 0 Enabled Read access watch in this region is enabled 1 write Clear Disable read access watch in this region 1 PRGN0WA Disable write access watch in PREGION[0] 24 24 read Disabled Write access watch in this PREGION is disabled 0 Enabled Write access watch in this PREGION is enabled 1 write Clear Disable write access watch in this PREGION 1 PRGN0RA Disable read access watch in PREGION[0] 25 25 read Disabled Read access watch in this PREGION is disabled 0 Enabled Read access watch in this PREGION is enabled 1 write Clear Disable read access watch in this PREGION 1 PRGN1WA Disable write access watch in PREGION[1] 26 26 read Disabled Write access watch in this PREGION is disabled 0 Enabled Write access watch in this PREGION is enabled 1 write Clear Disable write access watch in this PREGION 1 PRGN1RA Disable read access watch in PREGION[1] 27 27 read Disabled Read access watch in this PREGION is disabled 0 Enabled Read access watch in this PREGION is enabled 1 write Clear Disable read access watch in this PREGION 1 4 0x010 REGION[%s] Unspecified MWU_REGION 0x600 START Description cluster[n]: Start address for region n 0x000 read-write 0x00000000 START Start address for region 0 31 END Description cluster[n]: End address of region n 0x004 read-write END End address of region. 0 31 2 0x010 PREGION[%s] Unspecified MWU_PREGION 0x6C0 START Description cluster[n]: Reserved for future use 0x000 read-only START Reserved for future use 0 31 END Description cluster[n]: Reserved for future use 0x004 read-only END Reserved for future use 0 31 SUBS Description cluster[n]: Subregions of region n 0x008 read-write 0x00000000 SR0 Include or exclude subregion 0 in region 0 0 Exclude Exclude 0 Include Include 1 SR1 Include or exclude subregion 1 in region 1 1 Exclude Exclude 0 Include Include 1 SR2 Include or exclude subregion 2 in region 2 2 Exclude Exclude 0 Include Include 1 SR3 Include or exclude subregion 3 in region 3 3 Exclude Exclude 0 Include Include 1 SR4 Include or exclude subregion 4 in region 4 4 Exclude Exclude 0 Include Include 1 SR5 Include or exclude subregion 5 in region 5 5 Exclude Exclude 0 Include Include 1 SR6 Include or exclude subregion 6 in region 6 6 Exclude Exclude 0 Include Include 1 SR7 Include or exclude subregion 7 in region 7 7 Exclude Exclude 0 Include Include 1 SR8 Include or exclude subregion 8 in region 8 8 Exclude Exclude 0 Include Include 1 SR9 Include or exclude subregion 9 in region 9 9 Exclude Exclude 0 Include Include 1 SR10 Include or exclude subregion 10 in region 10 10 Exclude Exclude 0 Include Include 1 SR11 Include or exclude subregion 11 in region 11 11 Exclude Exclude 0 Include Include 1 SR12 Include or exclude subregion 12 in region 12 12 Exclude Exclude 0 Include Include 1 SR13 Include or exclude subregion 13 in region 13 13 Exclude Exclude 0 Include Include 1 SR14 Include or exclude subregion 14 in region 14 14 Exclude Exclude 0 Include Include 1 SR15 Include or exclude subregion 15 in region 15 15 Exclude Exclude 0 Include Include 1 SR16 Include or exclude subregion 16 in region 16 16 Exclude Exclude 0 Include Include 1 SR17 Include or exclude subregion 17 in region 17 17 Exclude Exclude 0 Include Include 1 SR18 Include or exclude subregion 18 in region 18 18 Exclude Exclude 0 Include Include 1 SR19 Include or exclude subregion 19 in region 19 19 Exclude Exclude 0 Include Include 1 SR20 Include or exclude subregion 20 in region 20 20 Exclude Exclude 0 Include Include 1 SR21 Include or exclude subregion 21 in region 21 21 Exclude Exclude 0 Include Include 1 SR22 Include or exclude subregion 22 in region 22 22 Exclude Exclude 0 Include Include 1 SR23 Include or exclude subregion 23 in region 23 23 Exclude Exclude 0 Include Include 1 SR24 Include or exclude subregion 24 in region 24 24 Exclude Exclude 0 Include Include 1 SR25 Include or exclude subregion 25 in region 25 25 Exclude Exclude 0 Include Include 1 SR26 Include or exclude subregion 26 in region 26 26 Exclude Exclude 0 Include Include 1 SR27 Include or exclude subregion 27 in region 27 27 Exclude Exclude 0 Include Include 1 SR28 Include or exclude subregion 28 in region 28 28 Exclude Exclude 0 Include Include 1 SR29 Include or exclude subregion 29 in region 29 29 Exclude Exclude 0 Include Include 1 SR30 Include or exclude subregion 30 in region 30 30 Exclude Exclude 0 Include Include 1 SR31 Include or exclude subregion 31 in region 31 31 Exclude Exclude 0 Include Include 1 PWM1 Pulse width modulation unit 1 0x40021000 PWM1 33 PWM2 Pulse width modulation unit 2 0x40022000 PWM2 34 SPI2 Serial Peripheral Interface 2 0x40023000 SPIM2_SPIS2_SPI2 35 SPIM2 Serial Peripheral Interface Master with EasyDMA 2 0x40023000 SPI2 SPIM2_SPIS2_SPI2 35 SPIS2 SPI Slave 2 0x40023000 SPI2 SPIM2_SPIS2_SPI2 35 RTC2 Real time counter 2 0x40024000 RTC2 36 I2S Inter-IC Sound 0x40025000 0 0x1000 registers I2S 37 I2S 0x20 TASKS_START Starts continuous I2S transfer. Also starts MCK generator when this is enabled. 0x000 write-only TASKS_START 0 0 TASKS_STOP Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated. 0x004 write-only TASKS_STOP 0 0 EVENTS_RXPTRUPD The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 0x104 read-write EVENTS_RXPTRUPD 0 0 EVENTS_STOPPED I2S transfer stopped. 0x108 read-write EVENTS_STOPPED 0 0 EVENTS_TXPTRUPD The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 0x114 read-write EVENTS_TXPTRUPD 0 0 INTEN Enable or disable interrupt 0x300 read-write RXPTRUPD Enable or disable interrupt for RXPTRUPD event 1 1 Disabled Disable 0 Enabled Enable 1 STOPPED Enable or disable interrupt for STOPPED event 2 2 Disabled Disable 0 Enabled Enable 1 TXPTRUPD Enable or disable interrupt for TXPTRUPD event 5 5 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write RXPTRUPD Write '1' to enable interrupt for RXPTRUPD event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STOPPED Write '1' to enable interrupt for STOPPED event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 TXPTRUPD Write '1' to enable interrupt for TXPTRUPD event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write RXPTRUPD Write '1' to disable interrupt for RXPTRUPD event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STOPPED Write '1' to disable interrupt for STOPPED event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 TXPTRUPD Write '1' to disable interrupt for TXPTRUPD event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable I2S module. 0x500 read-write 0x00000000 ENABLE Enable I2S module. 0 0 Disabled Disable 0 Enabled Enable 1 CONFIG Unspecified I2S_CONFIG 0x504 MODE I2S mode. 0x000 read-write 0x00000000 MODE I2S mode. 0 0 Master Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. 0 Slave Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx 1 RXEN Reception (RX) enable. 0x004 read-write 0x00000000 RXEN Reception (RX) enable. 0 0 Disabled Reception disabled and now data will be written to the RXD.PTR address. 0 Enabled Reception enabled. 1 TXEN Transmission (TX) enable. 0x008 read-write 0x00000001 TXEN Transmission (TX) enable. 0 0 Disabled Transmission disabled and now data will be read from the RXD.TXD address. 0 Enabled Transmission enabled. 1 MCKEN Master clock generator enable. 0x00C read-write 0x00000001 MCKEN Master clock generator enable. 0 0 Disabled Master clock generator disabled and PSEL.MCK not connected(available as GPIO). 0 Enabled Master clock generator running and MCK output on PSEL.MCK. 1 MCKFREQ Master clock generator frequency. 0x010 read-write 0x20000000 MCKFREQ Master clock generator frequency. 0 31 32MDIV2 32 MHz / 2 = 16.0 MHz 0x80000000 32MDIV3 32 MHz / 3 = 10.6666667 MHz 0x50000000 32MDIV4 32 MHz / 4 = 8.0 MHz 0x40000000 32MDIV5 32 MHz / 5 = 6.4 MHz 0x30000000 32MDIV6 32 MHz / 6 = 5.3333333 MHz 0x28000000 32MDIV8 32 MHz / 8 = 4.0 MHz 0x20000000 32MDIV10 32 MHz / 10 = 3.2 MHz 0x18000000 32MDIV11 32 MHz / 11 = 2.9090909 MHz 0x16000000 32MDIV15 32 MHz / 15 = 2.1333333 MHz 0x11000000 32MDIV16 32 MHz / 16 = 2.0 MHz 0x10000000 32MDIV21 32 MHz / 21 = 1.5238095 0x0C000000 32MDIV23 32 MHz / 23 = 1.3913043 MHz 0x0B000000 32MDIV30 32 MHz / 30 = 1.0666667 MHz 0x08800000 32MDIV31 32 MHz / 31 = 1.0322581 MHz 0x08400000 32MDIV32 32 MHz / 32 = 1.0 MHz 0x08000000 32MDIV42 32 MHz / 42 = 0.7619048 MHz 0x06000000 32MDIV63 32 MHz / 63 = 0.5079365 MHz 0x04100000 32MDIV125 32 MHz / 125 = 0.256 MHz 0x020C0000 RATIO MCK / LRCK ratio. 0x014 read-write 0x00000006 RATIO MCK / LRCK ratio. 0 3 32X LRCK = MCK / 32 0 48X LRCK = MCK / 48 1 64X LRCK = MCK / 64 2 96X LRCK = MCK / 96 3 128X LRCK = MCK / 128 4 192X LRCK = MCK / 192 5 256X LRCK = MCK / 256 6 384X LRCK = MCK / 384 7 512X LRCK = MCK / 512 8 SWIDTH Sample width. 0x018 read-write 0x00000001 SWIDTH Sample width. 0 1 8Bit 8 bit. 0 16Bit 16 bit. 1 24Bit 24 bit. 2 ALIGN Alignment of sample within a frame. 0x01C read-write 0x00000000 ALIGN Alignment of sample within a frame. 0 0 Left Left-aligned. 0 Right Right-aligned. 1 FORMAT Frame format. 0x020 read-write 0x00000000 FORMAT Frame format. 0 0 I2S Original I2S format. 0 Aligned Alternate (left- or right-aligned) format. 1 CHANNELS Enable channels. 0x024 read-write 0x00000000 CHANNELS Enable channels. 0 1 Stereo Stereo. 0 Left Left only. 1 Right Right only. 2 RXD Unspecified I2S_RXD 0x538 PTR Receive buffer RAM start address. 0x000 read-write 0x00000000 PTR Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. 0 31 TXD Unspecified I2S_TXD 0x540 PTR Transmit buffer RAM start address. 0x000 read-write 0x00000000 PTR Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. 0 31 RXTXD Unspecified I2S_RXTXD 0x550 MAXCNT Size of RXD and TXD buffers. 0x000 read-write 0x00000000 MAXCNT Size of RXD and TXD buffers in number of 32 bit words. 0 13 PSEL Unspecified I2S_PSEL 0x560 MCK Pin select for MCK signal. 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SCK Pin select for SCK signal. 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 LRCK Pin select for LRCK signal. 0x008 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDIN Pin select for SDIN signal. 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 SDOUT Pin select for SDOUT signal. 0x010 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 FPU FPU 0x40026000 0 0x1000 registers FPU 38 FPU 0x20 UNUSED Unused. 0x000 0x00000000 read-only USBD Universal serial bus device 0x40027000 0 0x1000 registers USBD 39 USBD 0x20 0x8 0x4 TASKS_STARTEPIN[%s] Description collection[n]: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host 0x004 write-only TASKS_STARTEPIN 0 0 TASKS_STARTISOIN Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint 0x024 write-only TASKS_STARTISOIN 0 0 0x8 0x4 TASKS_STARTEPOUT[%s] Description collection[n]: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host 0x028 write-only TASKS_STARTEPOUT 0 0 TASKS_STARTISOOUT Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint 0x048 write-only TASKS_STARTISOOUT 0 0 TASKS_EP0RCVOUT Allows OUT data stage on control endpoint 0 0x04C write-only TASKS_EP0RCVOUT 0 0 TASKS_EP0STATUS Allows status stage on control endpoint 0 0x050 write-only TASKS_EP0STATUS 0 0 TASKS_EP0STALL Stalls data and status stage on control endpoint 0 0x054 write-only TASKS_EP0STALL 0 0 TASKS_DPDMDRIVE Forces D+ and D- lines into the state defined in the DPDMVALUE register 0x058 write-only TASKS_DPDMDRIVE 0 0 TASKS_DPDMNODRIVE Stops forcing D+ and D- lines into any state (USB engine takes control) 0x05C write-only TASKS_DPDMNODRIVE 0 0 EVENTS_USBRESET Signals that a USB reset condition has been detected on USB lines 0x100 read-write EVENTS_USBRESET 0 0 EVENTS_STARTED Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register 0x104 read-write EVENTS_STARTED 0 0 0x8 0x4 EVENTS_ENDEPIN[%s] Description collection[n]: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0x108 read-write EVENTS_ENDEPIN 0 0 EVENTS_EP0DATADONE An acknowledged data transfer has taken place on the control endpoint 0x128 read-write EVENTS_EP0DATADONE 0 0 EVENTS_ENDISOIN The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software. 0x12C read-write EVENTS_ENDISOIN 0 0 0x8 0x4 EVENTS_ENDEPOUT[%s] Description collection[n]: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software. 0x130 read-write EVENTS_ENDEPOUT 0 0 EVENTS_ENDISOOUT The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software. 0x150 read-write EVENTS_ENDISOOUT 0 0 EVENTS_SOF Signals that a SOF (start of frame) condition has been detected on USB lines 0x154 read-write EVENTS_SOF 0 0 EVENTS_USBEVENT An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause. 0x158 read-write EVENTS_USBEVENT 0 0 EVENTS_EP0SETUP A valid SETUP token has been received (and acknowledged) on the control endpoint 0x15C read-write EVENTS_EP0SETUP 0 0 EVENTS_EPDATA A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register 0x160 read-write EVENTS_EPDATA 0 0 SHORTS Shortcut register 0x200 read-write EP0DATADONE_STARTEPIN0 Shortcut between EP0DATADONE event and STARTEPIN[0] task 0 0 Disabled Disable shortcut 0 Enabled Enable shortcut 1 EP0DATADONE_STARTEPOUT0 Shortcut between EP0DATADONE event and STARTEPOUT[0] task 1 1 Disabled Disable shortcut 0 Enabled Enable shortcut 1 EP0DATADONE_EP0STATUS Shortcut between EP0DATADONE event and EP0STATUS task 2 2 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ENDEPOUT0_EP0STATUS Shortcut between ENDEPOUT[0] event and EP0STATUS task 3 3 Disabled Disable shortcut 0 Enabled Enable shortcut 1 ENDEPOUT0_EP0RCVOUT Shortcut between ENDEPOUT[0] event and EP0RCVOUT task 4 4 Disabled Disable shortcut 0 Enabled Enable shortcut 1 INTEN Enable or disable interrupt 0x300 read-write USBRESET Enable or disable interrupt for USBRESET event 0 0 Disabled Disable 0 Enabled Enable 1 STARTED Enable or disable interrupt for STARTED event 1 1 Disabled Disable 0 Enabled Enable 1 ENDEPIN0 Enable or disable interrupt for ENDEPIN[0] event 2 2 Disabled Disable 0 Enabled Enable 1 ENDEPIN1 Enable or disable interrupt for ENDEPIN[1] event 3 3 Disabled Disable 0 Enabled Enable 1 ENDEPIN2 Enable or disable interrupt for ENDEPIN[2] event 4 4 Disabled Disable 0 Enabled Enable 1 ENDEPIN3 Enable or disable interrupt for ENDEPIN[3] event 5 5 Disabled Disable 0 Enabled Enable 1 ENDEPIN4 Enable or disable interrupt for ENDEPIN[4] event 6 6 Disabled Disable 0 Enabled Enable 1 ENDEPIN5 Enable or disable interrupt for ENDEPIN[5] event 7 7 Disabled Disable 0 Enabled Enable 1 ENDEPIN6 Enable or disable interrupt for ENDEPIN[6] event 8 8 Disabled Disable 0 Enabled Enable 1 ENDEPIN7 Enable or disable interrupt for ENDEPIN[7] event 9 9 Disabled Disable 0 Enabled Enable 1 EP0DATADONE Enable or disable interrupt for EP0DATADONE event 10 10 Disabled Disable 0 Enabled Enable 1 ENDISOIN Enable or disable interrupt for ENDISOIN event 11 11 Disabled Disable 0 Enabled Enable 1 ENDEPOUT0 Enable or disable interrupt for ENDEPOUT[0] event 12 12 Disabled Disable 0 Enabled Enable 1 ENDEPOUT1 Enable or disable interrupt for ENDEPOUT[1] event 13 13 Disabled Disable 0 Enabled Enable 1 ENDEPOUT2 Enable or disable interrupt for ENDEPOUT[2] event 14 14 Disabled Disable 0 Enabled Enable 1 ENDEPOUT3 Enable or disable interrupt for ENDEPOUT[3] event 15 15 Disabled Disable 0 Enabled Enable 1 ENDEPOUT4 Enable or disable interrupt for ENDEPOUT[4] event 16 16 Disabled Disable 0 Enabled Enable 1 ENDEPOUT5 Enable or disable interrupt for ENDEPOUT[5] event 17 17 Disabled Disable 0 Enabled Enable 1 ENDEPOUT6 Enable or disable interrupt for ENDEPOUT[6] event 18 18 Disabled Disable 0 Enabled Enable 1 ENDEPOUT7 Enable or disable interrupt for ENDEPOUT[7] event 19 19 Disabled Disable 0 Enabled Enable 1 ENDISOOUT Enable or disable interrupt for ENDISOOUT event 20 20 Disabled Disable 0 Enabled Enable 1 SOF Enable or disable interrupt for SOF event 21 21 Disabled Disable 0 Enabled Enable 1 USBEVENT Enable or disable interrupt for USBEVENT event 22 22 Disabled Disable 0 Enabled Enable 1 EP0SETUP Enable or disable interrupt for EP0SETUP event 23 23 Disabled Disable 0 Enabled Enable 1 EPDATA Enable or disable interrupt for EPDATA event 24 24 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write USBRESET Write '1' to enable interrupt for USBRESET event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 STARTED Write '1' to enable interrupt for STARTED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN0 Write '1' to enable interrupt for ENDEPIN[0] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN1 Write '1' to enable interrupt for ENDEPIN[1] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN2 Write '1' to enable interrupt for ENDEPIN[2] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN3 Write '1' to enable interrupt for ENDEPIN[3] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN4 Write '1' to enable interrupt for ENDEPIN[4] event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN5 Write '1' to enable interrupt for ENDEPIN[5] event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN6 Write '1' to enable interrupt for ENDEPIN[6] event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPIN7 Write '1' to enable interrupt for ENDEPIN[7] event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EP0DATADONE Write '1' to enable interrupt for EP0DATADONE event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDISOIN Write '1' to enable interrupt for ENDISOIN event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT0 Write '1' to enable interrupt for ENDEPOUT[0] event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT1 Write '1' to enable interrupt for ENDEPOUT[1] event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT2 Write '1' to enable interrupt for ENDEPOUT[2] event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT3 Write '1' to enable interrupt for ENDEPOUT[3] event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT4 Write '1' to enable interrupt for ENDEPOUT[4] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT5 Write '1' to enable interrupt for ENDEPOUT[5] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT6 Write '1' to enable interrupt for ENDEPOUT[6] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDEPOUT7 Write '1' to enable interrupt for ENDEPOUT[7] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 ENDISOOUT Write '1' to enable interrupt for ENDISOOUT event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 SOF Write '1' to enable interrupt for SOF event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 USBEVENT Write '1' to enable interrupt for USBEVENT event 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EP0SETUP Write '1' to enable interrupt for EP0SETUP event 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 EPDATA Write '1' to enable interrupt for EPDATA event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write USBRESET Write '1' to disable interrupt for USBRESET event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 STARTED Write '1' to disable interrupt for STARTED event 1 1 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN0 Write '1' to disable interrupt for ENDEPIN[0] event 2 2 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN1 Write '1' to disable interrupt for ENDEPIN[1] event 3 3 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN2 Write '1' to disable interrupt for ENDEPIN[2] event 4 4 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN3 Write '1' to disable interrupt for ENDEPIN[3] event 5 5 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN4 Write '1' to disable interrupt for ENDEPIN[4] event 6 6 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN5 Write '1' to disable interrupt for ENDEPIN[5] event 7 7 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN6 Write '1' to disable interrupt for ENDEPIN[6] event 8 8 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPIN7 Write '1' to disable interrupt for ENDEPIN[7] event 9 9 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EP0DATADONE Write '1' to disable interrupt for EP0DATADONE event 10 10 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDISOIN Write '1' to disable interrupt for ENDISOIN event 11 11 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT0 Write '1' to disable interrupt for ENDEPOUT[0] event 12 12 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT1 Write '1' to disable interrupt for ENDEPOUT[1] event 13 13 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT2 Write '1' to disable interrupt for ENDEPOUT[2] event 14 14 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT3 Write '1' to disable interrupt for ENDEPOUT[3] event 15 15 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT4 Write '1' to disable interrupt for ENDEPOUT[4] event 16 16 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT5 Write '1' to disable interrupt for ENDEPOUT[5] event 17 17 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT6 Write '1' to disable interrupt for ENDEPOUT[6] event 18 18 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDEPOUT7 Write '1' to disable interrupt for ENDEPOUT[7] event 19 19 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENDISOOUT Write '1' to disable interrupt for ENDISOOUT event 20 20 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 SOF Write '1' to disable interrupt for SOF event 21 21 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 USBEVENT Write '1' to disable interrupt for USBEVENT event 22 22 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EP0SETUP Write '1' to disable interrupt for EP0SETUP event 23 23 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EPDATA Write '1' to disable interrupt for EPDATA event 24 24 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 EVENTCAUSE Details on what caused the USBEVENT event 0x400 read-write oneToClear ISOOUTCRC CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear. 0 0 NotDetected No error detected 0 Detected Error detected 1 SUSPEND Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear. 8 8 NotDetected Suspend not detected 0 Detected Suspend detected 1 RESUME Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear. 9 9 NotDetected Resume not detected 0 Detected Resume detected 1 USBWUALLOWED USB MAC has been woken up and operational. Write '1' to clear. 10 10 NotAllowed Wake up not allowed 0 Allowed Wake up allowed 1 READY USB device is ready for normal operation. Write '1' to clear. 11 11 NotDetected USBEVENT was not issued due to USBD peripheral ready 0 Ready USBD peripheral is ready 1 HALTED Unspecified USBD_HALTED 0x420 0x8 0x4 EPIN[%s] Description collection[n]: IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0x000 read-only GETSTATUS IN endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0 15 NotHalted Endpoint is not halted 0 Halted Endpoint is halted 1 0x8 0x4 EPOUT[%s] Description collection[n]: OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0x024 read-only GETSTATUS OUT endpoint halted status. Can be used as is as response to a GetStatus() request to endpoint. 0 15 NotHalted Endpoint is not halted 0 Halted Endpoint is halted 1 EPSTATUS Provides information on which endpoint's EasyDMA registers have been captured 0x468 read-write oneToClear EPIN0 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 0 0 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN1 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 1 1 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN2 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 2 2 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN3 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 3 3 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN4 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 4 4 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN5 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 5 5 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN6 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 6 6 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN7 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 7 7 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPIN8 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 8 8 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT0 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 16 16 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT1 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 17 17 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT2 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 18 18 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT3 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 19 19 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT4 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 20 20 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT5 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 21 21 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT6 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 22 22 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT7 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 23 23 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPOUT8 Captured state of endpoint's EasyDMA registers. Write '1' to clear. 24 24 NoData EasyDMA registers have not been captured for this endpoint 0 DataDone EasyDMA registers have been captured for this endpoint 1 EPDATASTATUS Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event) 0x46C read-write oneToClear EPIN1 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 1 1 NotDone No acknowledged data transfer on this endpoint 0 DataDone Acknowledged data transfer on this endpoint has occurred 1 EPIN2 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 2 2 NotDone No acknowledged data transfer on this endpoint 0 DataDone Acknowledged data transfer on this endpoint has occurred 1 EPIN3 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 3 3 NotDone No acknowledged data transfer on this endpoint 0 DataDone Acknowledged data transfer on this endpoint has occurred 1 EPIN4 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 4 4 NotDone No acknowledged data transfer on this endpoint 0 DataDone Acknowledged data transfer on this endpoint has occurred 1 EPIN5 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 5 5 NotDone No acknowledged data transfer on this endpoint 0 DataDone Acknowledged data transfer on this endpoint has occurred 1 EPIN6 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 6 6 NotDone No acknowledged data transfer on this endpoint 0 DataDone Acknowledged data transfer on this endpoint has occurred 1 EPIN7 Acknowledged data transfer on this IN endpoint. Write '1' to clear. 7 7 NotDone No acknowledged data transfer on this endpoint 0 DataDone Acknowledged data transfer on this endpoint has occurred 1 EPOUT1 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 17 17 NotStarted No acknowledged data transfer on this endpoint 0 Started Acknowledged data transfer on this endpoint has occurred 1 EPOUT2 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 18 18 NotStarted No acknowledged data transfer on this endpoint 0 Started Acknowledged data transfer on this endpoint has occurred 1 EPOUT3 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 19 19 NotStarted No acknowledged data transfer on this endpoint 0 Started Acknowledged data transfer on this endpoint has occurred 1 EPOUT4 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 20 20 NotStarted No acknowledged data transfer on this endpoint 0 Started Acknowledged data transfer on this endpoint has occurred 1 EPOUT5 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 21 21 NotStarted No acknowledged data transfer on this endpoint 0 Started Acknowledged data transfer on this endpoint has occurred 1 EPOUT6 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 22 22 NotStarted No acknowledged data transfer on this endpoint 0 Started Acknowledged data transfer on this endpoint has occurred 1 EPOUT7 Acknowledged data transfer on this OUT endpoint. Write '1' to clear. 23 23 NotStarted No acknowledged data transfer on this endpoint 0 Started Acknowledged data transfer on this endpoint has occurred 1 USBADDR Device USB address 0x470 read-only ADDR Device USB address 0 6 BMREQUESTTYPE SETUP data, byte 0, bmRequestType 0x480 read-only 0x00000000 RECIPIENT Data transfer type 0 4 Device Device 0 Interface Interface 1 Endpoint Endpoint 2 Other Other 3 TYPE Data transfer type 5 6 Standard Standard 0 Class Class 1 Vendor Vendor 2 DIRECTION Data transfer direction 7 7 HostToDevice Host-to-device 0 DeviceToHost Device-to-host 1 BREQUEST SETUP data, byte 1, bRequest 0x484 read-only 0x00000000 BREQUEST SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values. 0 7 STD_GET_STATUS Standard request GET_STATUS 0 STD_CLEAR_FEATURE Standard request CLEAR_FEATURE 1 STD_SET_FEATURE Standard request SET_FEATURE 3 STD_SET_ADDRESS Standard request SET_ADDRESS 5 STD_GET_DESCRIPTOR Standard request GET_DESCRIPTOR 6 STD_SET_DESCRIPTOR Standard request SET_DESCRIPTOR 7 STD_GET_CONFIGURATION Standard request GET_CONFIGURATION 8 STD_SET_CONFIGURATION Standard request SET_CONFIGURATION 9 STD_GET_INTERFACE Standard request GET_INTERFACE 10 STD_SET_INTERFACE Standard request SET_INTERFACE 11 STD_SYNCH_FRAME Standard request SYNCH_FRAME 12 WVALUEL SETUP data, byte 2, LSB of wValue 0x488 read-only 0x00000000 WVALUEL SETUP data, byte 2, LSB of wValue 0 7 WVALUEH SETUP data, byte 3, MSB of wValue 0x48C read-only 0x00000000 WVALUEH SETUP data, byte 3, MSB of wValue 0 7 WINDEXL SETUP data, byte 4, LSB of wIndex 0x490 read-only 0x00000000 WINDEXL SETUP data, byte 4, LSB of wIndex 0 7 WINDEXH SETUP data, byte 5, MSB of wIndex 0x494 read-only 0x00000000 WINDEXH SETUP data, byte 5, MSB of wIndex 0 7 WLENGTHL SETUP data, byte 6, LSB of wLength 0x498 read-only 0x00000000 WLENGTHL SETUP data, byte 6, LSB of wLength 0 7 WLENGTHH SETUP data, byte 7, MSB of wLength 0x49C read-only 0x00000000 WLENGTHH SETUP data, byte 7, MSB of wLength 0 7 SIZE Unspecified USBD_SIZE 0x4A0 0x8 0x4 EPOUT[%s] Description collection[n]: Number of bytes received last in the data stage of this OUT endpoint 0x000 read-write SIZE Number of bytes received last in the data stage of this OUT endpoint 0 6 ISOOUT Number of bytes received last on this ISO OUT data endpoint 0x020 read-only 0x00010000 SIZE Number of bytes received last on this ISO OUT data endpoint 0 9 ZERO Zero-length data packet received 16 16 Normal No zero-length data received, use value in SIZE 0 ZeroData Zero-length data received, ignore value in SIZE 1 ENABLE Enable USB 0x500 read-write ENABLE Enable USB 0 0 Disabled USB peripheral is disabled 0 Enabled USB peripheral is enabled 1 USBPULLUP Control of the USB pull-up 0x504 read-write CONNECT Control of the USB pull-up on the D+ line 0 0 Disabled Pull-up is disconnected 0 Enabled Pull-up is connected to D+ 1 DPDMVALUE State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing). 0x508 read-write STATE State D+ and D- lines will be forced into by the DPDMDRIVE task 0 4 Resume D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state) 1 J D+ forced high, D- forced low (J state) 2 K D+ forced low, D- forced high (K state) 4 DTOGGLE Data toggle control and status 0x50C read-write 0x00000100 EP Select bulk endpoint number 0 2 IO Selects IN or OUT endpoint 7 7 Out Selects OUT endpoint 0 In Selects IN endpoint 1 VALUE Data toggle value 8 9 Nop No action on data toggle when writing the register with this value 0 Data0 Data toggle is DATA0 on endpoint set by EP and IO 1 Data1 Data toggle is DATA1 on endpoint set by EP and IO 2 EPINEN Endpoint IN enable 0x510 read-write 0x00000001 IN0 Enable IN endpoint 0 0 0 Disable Disable endpoint IN 0 (no response to IN tokens) 0 Enable Enable endpoint IN 0 (response to IN tokens) 1 IN1 Enable IN endpoint 1 1 1 Disable Disable endpoint IN 1 (no response to IN tokens) 0 Enable Enable endpoint IN 1 (response to IN tokens) 1 IN2 Enable IN endpoint 2 2 2 Disable Disable endpoint IN 2 (no response to IN tokens) 0 Enable Enable endpoint IN 2 (response to IN tokens) 1 IN3 Enable IN endpoint 3 3 3 Disable Disable endpoint IN 3 (no response to IN tokens) 0 Enable Enable endpoint IN 3 (response to IN tokens) 1 IN4 Enable IN endpoint 4 4 4 Disable Disable endpoint IN 4 (no response to IN tokens) 0 Enable Enable endpoint IN 4 (response to IN tokens) 1 IN5 Enable IN endpoint 5 5 5 Disable Disable endpoint IN 5 (no response to IN tokens) 0 Enable Enable endpoint IN 5 (response to IN tokens) 1 IN6 Enable IN endpoint 6 6 6 Disable Disable endpoint IN 6 (no response to IN tokens) 0 Enable Enable endpoint IN 6 (response to IN tokens) 1 IN7 Enable IN endpoint 7 7 7 Disable Disable endpoint IN 7 (no response to IN tokens) 0 Enable Enable endpoint IN 7 (response to IN tokens) 1 ISOIN Enable ISO IN endpoint 8 8 Disable Disable ISO IN endpoint 8 0 Enable Enable ISO IN endpoint 8 1 EPOUTEN Endpoint OUT enable 0x514 read-write 0x00000001 OUT0 Enable OUT endpoint 0 0 0 Disable Disable endpoint OUT 0 (no response to OUT tokens) 0 Enable Enable endpoint OUT 0 (response to OUT tokens) 1 OUT1 Enable OUT endpoint 1 1 1 Disable Disable endpoint OUT 1 (no response to OUT tokens) 0 Enable Enable endpoint OUT 1 (response to OUT tokens) 1 OUT2 Enable OUT endpoint 2 2 2 Disable Disable endpoint OUT 2 (no response to OUT tokens) 0 Enable Enable endpoint OUT 2 (response to OUT tokens) 1 OUT3 Enable OUT endpoint 3 3 3 Disable Disable endpoint OUT 3 (no response to OUT tokens) 0 Enable Enable endpoint OUT 3 (response to OUT tokens) 1 OUT4 Enable OUT endpoint 4 4 4 Disable Disable endpoint OUT 4 (no response to OUT tokens) 0 Enable Enable endpoint OUT 4 (response to OUT tokens) 1 OUT5 Enable OUT endpoint 5 5 5 Disable Disable endpoint OUT 5 (no response to OUT tokens) 0 Enable Enable endpoint OUT 5 (response to OUT tokens) 1 OUT6 Enable OUT endpoint 6 6 6 Disable Disable endpoint OUT 6 (no response to OUT tokens) 0 Enable Enable endpoint OUT 6 (response to OUT tokens) 1 OUT7 Enable OUT endpoint 7 7 7 Disable Disable endpoint OUT 7 (no response to OUT tokens) 0 Enable Enable endpoint OUT 7 (response to OUT tokens) 1 ISOOUT Enable ISO OUT endpoint 8 8 8 Disable Disable ISO OUT endpoint 8 0 Enable Enable ISO OUT endpoint 8 1 EPSTALL STALL endpoints 0x518 write-only 0x00000000 modifyExternal EP Select endpoint number 0 2 IO Selects IN or OUT endpoint 7 7 Out Selects OUT endpoint 0 In Selects IN endpoint 1 STALL Stall selected endpoint 8 8 UnStall Don't stall selected endpoint 0 Stall Stall selected endpoint 1 ISOSPLIT Controls the split of ISO buffers 0x51C read-write SPLIT Controls the split of ISO buffers 0 15 OneDir Full buffer dedicated to either iso IN or OUT 0x0000 HalfIN Lower half for IN, upper half for OUT 0x0080 FRAMECNTR Returns the current value of the start of frame counter 0x520 read-only FRAMECNTR Returns the current value of the start of frame counter 0 10 LOWPOWER Controls USBD peripheral low power mode during USB suspend 0x52C read-write 0x00000000 LOWPOWER Controls USBD peripheral low-power mode during USB suspend 0 0 ForceNormal Software must write this value to exit low power mode and before performing a remote wake-up 0 LowPower Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral 1 ISOINCONFIG Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent 0x530 read-write RESPONSE Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent 0 0 NoResp Endpoint does not respond in that case 0 ZeroData Endpoint responds with a zero-length data packet in that case 1 8 0x014 EPIN[%s] Unspecified USBD_EPIN 0x600 PTR Description cluster[n]: Data pointer 0x000 read-write PTR Data pointer. Accepts any address in Data RAM. 0 31 MAXCNT Description cluster[n]: Maximum number of bytes to transfer 0x004 read-write MAXCNT Maximum number of bytes to transfer 0 6 AMOUNT Description cluster[n]: Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 6 ISOIN Unspecified USBD_ISOIN 0x6A0 PTR Data pointer 0x000 read-write PTR Data pointer. Accepts any address in Data RAM. 0 31 MAXCNT Maximum number of bytes to transfer 0x004 read-write MAXCNT Maximum number of bytes to transfer 0 9 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 9 8 0x014 EPOUT[%s] Unspecified USBD_EPOUT 0x700 PTR Description cluster[n]: Data pointer 0x000 read-write PTR Data pointer. Accepts any address in Data RAM. 0 31 MAXCNT Description cluster[n]: Maximum number of bytes to transfer 0x004 read-write MAXCNT Maximum number of bytes to transfer 0 6 AMOUNT Description cluster[n]: Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 6 ISOOUT Unspecified USBD_ISOOUT 0x7A0 PTR Data pointer 0x000 read-write PTR Data pointer. Accepts any address in Data RAM. 0 31 MAXCNT Maximum number of bytes to transfer 0x004 read-write MAXCNT Maximum number of bytes to transfer 0 9 AMOUNT Number of bytes transferred in the last transaction 0x008 read-only AMOUNT Number of bytes transferred in the last transaction 0 9 UARTE1 UART with EasyDMA 1 0x40028000 UARTE1 40 QSPI External flash interface 0x40029000 0 0x1000 registers QSPI 41 QSPI 0x20 TASKS_ACTIVATE Activate QSPI interface 0x000 write-only TASKS_ACTIVATE 0 0 TASKS_READSTART Start transfer from external flash memory to internal RAM 0x004 write-only TASKS_READSTART 0 0 TASKS_WRITESTART Start transfer from internal RAM to external flash memory 0x008 write-only TASKS_WRITESTART 0 0 TASKS_ERASESTART Start external flash memory erase operation 0x00C write-only TASKS_ERASESTART 0 0 TASKS_DEACTIVATE Deactivate QSPI interface 0x010 write-only TASKS_DEACTIVATE 0 0 EVENTS_READY QSPI peripheral is ready. This event will be generated as a response to any QSPI task. 0x100 read-write EVENTS_READY 0 0 INTEN Enable or disable interrupt 0x300 read-write READY Enable or disable interrupt for READY event 0 0 Disabled Disable 0 Enabled Enable 1 INTENSET Enable interrupt 0x304 read-write READY Write '1' to enable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Set Enable 1 INTENCLR Disable interrupt 0x308 read-write READY Write '1' to disable interrupt for READY event 0 0 read Disabled Read: Disabled 0 Enabled Read: Enabled 1 write Clear Disable 1 ENABLE Enable QSPI peripheral and acquire the pins selected in PSELn registers 0x500 read-write ENABLE Enable or disable QSPI 0 0 Disabled Disable QSPI 0 Enabled Enable QSPI 1 READ Unspecified QSPI_READ 0x504 SRC Flash memory source address 0x000 read-write SRC Word-aligned flash memory source address. 0 31 DST RAM destination address 0x004 read-write DST Word-aligned RAM destination address. 0 31 CNT Read transfer length 0x008 read-write CNT Read transfer length in number of bytes. The length must be a multiple of 4 bytes. 0 20 WRITE Unspecified QSPI_WRITE 0x510 DST Flash destination address 0x000 read-write DST Word-aligned flash destination address. 0 31 SRC RAM source address 0x004 read-write SRC Word-aligned RAM source address. 0 31 CNT Write transfer length 0x008 read-write CNT Write transfer length in number of bytes. The length must be a multiple of 4 bytes. 0 20 ERASE Unspecified QSPI_ERASE 0x51C PTR Start address of flash block to be erased 0x000 read-write PTR Word-aligned start address of block to be erased. 0 31 LEN Size of block to be erased. 0x004 read-write LEN LEN 0 1 4KB Erase 4 kB block (flash command 0x20) 0 64KB Erase 64 kB block (flash command 0xD8) 1 All Erase all (flash command 0xC7) 2 PSEL Unspecified QSPI_PSEL 0x524 SCK Pin select for serial clock SCK 0x000 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 CSN Pin select for chip select signal CSN. 0x004 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 IO0 Pin select for serial data MOSI/IO0. 0x00C read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 IO1 Pin select for serial data MISO/IO1. 0x010 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 IO2 Pin select for serial data IO2. 0x014 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 IO3 Pin select for serial data IO3. 0x018 read-write 0xFFFFFFFF PIN Pin number 0 4 PORT Port number 5 5 CONNECT Connection 31 31 Disconnected Disconnect 1 Connected Connect 0 XIPOFFSET Address offset into the external memory for Execute in Place operation. 0x540 read-write XIPOFFSET Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4. 0 31 IFCONFIG0 Interface configuration. 0x544 read-write READOC Configure number of data lines and opcode used for reading. 0 2 FASTREAD Single data line SPI. FAST_READ (opcode 0x0B). 0 READ2O Dual data line SPI. READ2O (opcode 0x3B). 1 READ2IO Dual data line SPI. READ2IO (opcode 0xBB). 2 READ4O Quad data line SPI. READ4O (opcode 0x6B). 3 READ4IO Quad data line SPI. READ4IO (opcode 0xEB). 4 WRITEOC Configure number of data lines and opcode used for writing. 3 5 PP Single data line SPI. PP (opcode 0x02). 0 PP2O Dual data line SPI. PP2O (opcode 0xA2). 1 PP4O Quad data line SPI. PP4O (opcode 0x32). 2 PP4IO Quad data line SPI. PP4IO (opcode 0x38). 3 ADDRMODE Addressing mode. 6 6 24BIT 24-bit addressing. 0 32BIT 32-bit addressing. 1 DPMENABLE Enable deep power-down mode (DPM) feature. 7 7 Disable Disable DPM feature. 0 Enable Enable DPM feature. 1 PPSIZE Page size for commands PP, PP2O, PP4O and PP4IO. 12 12 256Bytes 256 bytes. 0 512Bytes 512 bytes. 1 IFCONFIG1 Interface configuration. 0x600 read-write 0x00040480 SCKDELAY Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns). 0 7 DPMEN Enter/exit deep power-down mode (DPM) for external flash memory. 24 24 Exit Exit DPM. 0 Enter Enter DPM. 1 SPIMODE Select SPI mode. 25 25 MODE0 Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0). 0 MODE3 Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1). 1 SCKFREQ SCK frequency is given as 32 MHz / (SCKFREQ + 1). 28 31 STATUS Status register. 0x604 read-only DPM Deep power-down mode (DPM) status of external flash. 2 2 Disabled External flash is not in DPM. 0 Enabled External flash is in DPM. 1 READY Ready status. 3 3 READY QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM. 1 BUSY QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM. 0 SREG Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte. 24 31 DPMDUR Set the duration required to enter/exit deep power-down mode (DPM). 0x614 read-write 0xFFFFFFFF ENTER Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns. 0 15 EXIT Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns. 16 31 ADDRCONF Extended address configuration. 0x624 read-write 0x000000B7 OPCODE Opcode that enters the 32-bit addressing mode. 0 7 BYTE0 Byte 0 following opcode. 8 15 BYTE1 Byte 1 following byte 0. 16 23 MODE Extended addressing mode. 24 25 NoInstr Do not send any instruction. 0 Opcode Send opcode. 1 OpByte0 Send opcode, byte0. 2 All Send opcode, byte0, byte1. 3 WIPWAIT Wait for write complete before sending command. 26 26 Disable No wait. 0 Enable Wait. 1 WREN Send WREN (write enable opcode 0x06) before instruction. 27 27 Disable Do not send WREN. 0 Enable Send WREN. 1 CINSTRCONF Custom instruction configuration register. 0x634 read-write 0x00002000 OPCODE Opcode of Custom instruction. 0 7 LENGTH Length of custom instruction in number of bytes. 8 11 1B Send opcode only. 1 2B Send opcode, CINSTRDAT0.BYTE0. 2 3B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1. 3 4B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2. 4 5B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3. 5 6B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4. 6 7B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5. 7 8B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6. 8 9B Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7. 9 LIO2 Level of the IO2 pin (if connected) during transmission of custom instruction. 12 12 LIO3 Level of the IO3 pin (if connected) during transmission of custom instruction. 13 13 WIPWAIT Wait for write complete before sending command. 14 14 Disable No wait. 0 Enable Wait. 1 WREN Send WREN (write enable opcode 0x06) before instruction. 15 15 Disable Do not send WREN. 0 Enable Send WREN. 1 LFEN Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field. 16 16 Disable Long frame mode disabled 0 Enable Long frame mode enabled 1 LFSTOP Stop (finalize) long frame transaction 17 17 Stop Stop 1 CINSTRDAT0 Custom instruction data register 0. 0x638 read-write BYTE0 Data byte 0 0 7 BYTE1 Data byte 1 8 15 BYTE2 Data byte 2 16 23 BYTE3 Data byte 3 24 31 CINSTRDAT1 Custom instruction data register 1. 0x63C read-write BYTE4 Data byte 4 0 7 BYTE5 Data byte 5 8 15 BYTE6 Data byte 6 16 23 BYTE7 Data byte 7 24 31 IFTIMING SPI interface timing. 0x640 read-write 0x00000200 RXDELAY Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK. 8 10 PWM3 Pulse width modulation unit 3 0x4002D000 PWM3 45 SPIM3 Serial Peripheral Interface Master with EasyDMA 3 0x4002F000 SPIM3 47 P0 GPIO Port 1 0x50000000 GPIO 0 0x1000 registers GPIO 0x20 OUT Write GPIO port 0x504 read-write PIN0 Pin 0 0 0 Low Pin driver is low 0 High Pin driver is high 1 PIN1 Pin 1 1 1 Low Pin driver is low 0 High Pin driver is high 1 PIN2 Pin 2 2 2 Low Pin driver is low 0 High Pin driver is high 1 PIN3 Pin 3 3 3 Low Pin driver is low 0 High Pin driver is high 1 PIN4 Pin 4 4 4 Low Pin driver is low 0 High Pin driver is high 1 PIN5 Pin 5 5 5 Low Pin driver is low 0 High Pin driver is high 1 PIN6 Pin 6 6 6 Low Pin driver is low 0 High Pin driver is high 1 PIN7 Pin 7 7 7 Low Pin driver is low 0 High Pin driver is high 1 PIN8 Pin 8 8 8 Low Pin driver is low 0 High Pin driver is high 1 PIN9 Pin 9 9 9 Low Pin driver is low 0 High Pin driver is high 1 PIN10 Pin 10 10 10 Low Pin driver is low 0 High Pin driver is high 1 PIN11 Pin 11 11 11 Low Pin driver is low 0 High Pin driver is high 1 PIN12 Pin 12 12 12 Low Pin driver is low 0 High Pin driver is high 1 PIN13 Pin 13 13 13 Low Pin driver is low 0 High Pin driver is high 1 PIN14 Pin 14 14 14 Low Pin driver is low 0 High Pin driver is high 1 PIN15 Pin 15 15 15 Low Pin driver is low 0 High Pin driver is high 1 PIN16 Pin 16 16 16 Low Pin driver is low 0 High Pin driver is high 1 PIN17 Pin 17 17 17 Low Pin driver is low 0 High Pin driver is high 1 PIN18 Pin 18 18 18 Low Pin driver is low 0 High Pin driver is high 1 PIN19 Pin 19 19 19 Low Pin driver is low 0 High Pin driver is high 1 PIN20 Pin 20 20 20 Low Pin driver is low 0 High Pin driver is high 1 PIN21 Pin 21 21 21 Low Pin driver is low 0 High Pin driver is high 1 PIN22 Pin 22 22 22 Low Pin driver is low 0 High Pin driver is high 1 PIN23 Pin 23 23 23 Low Pin driver is low 0 High Pin driver is high 1 PIN24 Pin 24 24 24 Low Pin driver is low 0 High Pin driver is high 1 PIN25 Pin 25 25 25 Low Pin driver is low 0 High Pin driver is high 1 PIN26 Pin 26 26 26 Low Pin driver is low 0 High Pin driver is high 1 PIN27 Pin 27 27 27 Low Pin driver is low 0 High Pin driver is high 1 PIN28 Pin 28 28 28 Low Pin driver is low 0 High Pin driver is high 1 PIN29 Pin 29 29 29 Low Pin driver is low 0 High Pin driver is high 1 PIN30 Pin 30 30 30 Low Pin driver is low 0 High Pin driver is high 1 PIN31 Pin 31 31 31 Low Pin driver is low 0 High Pin driver is high 1 OUTSET Set individual bits in GPIO port 0x508 read-write oneToSet PIN0 Pin 0 0 0 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Set Write: writing a '1' sets the pin high; writing a '0' has no effect 1 OUTCLR Clear individual bits in GPIO port 0x50C read-write oneToClear PIN0 Pin 0 0 0 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN1 Pin 1 1 1 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN2 Pin 2 2 2 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN3 Pin 3 3 3 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN4 Pin 4 4 4 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN5 Pin 5 5 5 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN6 Pin 6 6 6 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN7 Pin 7 7 7 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN8 Pin 8 8 8 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN9 Pin 9 9 9 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN10 Pin 10 10 10 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN11 Pin 11 11 11 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN12 Pin 12 12 12 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN13 Pin 13 13 13 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN14 Pin 14 14 14 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN15 Pin 15 15 15 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN16 Pin 16 16 16 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN17 Pin 17 17 17 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN18 Pin 18 18 18 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN19 Pin 19 19 19 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN20 Pin 20 20 20 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN21 Pin 21 21 21 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN22 Pin 22 22 22 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN23 Pin 23 23 23 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN24 Pin 24 24 24 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN25 Pin 25 25 25 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN26 Pin 26 26 26 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN27 Pin 27 27 27 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN28 Pin 28 28 28 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN29 Pin 29 29 29 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN30 Pin 30 30 30 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 PIN31 Pin 31 31 31 read Low Read: pin driver is low 0 High Read: pin driver is high 1 write Clear Write: writing a '1' sets the pin low; writing a '0' has no effect 1 IN Read GPIO port 0x510 read-only PIN0 Pin 0 0 0 Low Pin input is low 0 High Pin input is high 1 PIN1 Pin 1 1 1 Low Pin input is low 0 High Pin input is high 1 PIN2 Pin 2 2 2 Low Pin input is low 0 High Pin input is high 1 PIN3 Pin 3 3 3 Low Pin input is low 0 High Pin input is high 1 PIN4 Pin 4 4 4 Low Pin input is low 0 High Pin input is high 1 PIN5 Pin 5 5 5 Low Pin input is low 0 High Pin input is high 1 PIN6 Pin 6 6 6 Low Pin input is low 0 High Pin input is high 1 PIN7 Pin 7 7 7 Low Pin input is low 0 High Pin input is high 1 PIN8 Pin 8 8 8 Low Pin input is low 0 High Pin input is high 1 PIN9 Pin 9 9 9 Low Pin input is low 0 High Pin input is high 1 PIN10 Pin 10 10 10 Low Pin input is low 0 High Pin input is high 1 PIN11 Pin 11 11 11 Low Pin input is low 0 High Pin input is high 1 PIN12 Pin 12 12 12 Low Pin input is low 0 High Pin input is high 1 PIN13 Pin 13 13 13 Low Pin input is low 0 High Pin input is high 1 PIN14 Pin 14 14 14 Low Pin input is low 0 High Pin input is high 1 PIN15 Pin 15 15 15 Low Pin input is low 0 High Pin input is high 1 PIN16 Pin 16 16 16 Low Pin input is low 0 High Pin input is high 1 PIN17 Pin 17 17 17 Low Pin input is low 0 High Pin input is high 1 PIN18 Pin 18 18 18 Low Pin input is low 0 High Pin input is high 1 PIN19 Pin 19 19 19 Low Pin input is low 0 High Pin input is high 1 PIN20 Pin 20 20 20 Low Pin input is low 0 High Pin input is high 1 PIN21 Pin 21 21 21 Low Pin input is low 0 High Pin input is high 1 PIN22 Pin 22 22 22 Low Pin input is low 0 High Pin input is high 1 PIN23 Pin 23 23 23 Low Pin input is low 0 High Pin input is high 1 PIN24 Pin 24 24 24 Low Pin input is low 0 High Pin input is high 1 PIN25 Pin 25 25 25 Low Pin input is low 0 High Pin input is high 1 PIN26 Pin 26 26 26 Low Pin input is low 0 High Pin input is high 1 PIN27 Pin 27 27 27 Low Pin input is low 0 High Pin input is high 1 PIN28 Pin 28 28 28 Low Pin input is low 0 High Pin input is high 1 PIN29 Pin 29 29 29 Low Pin input is low 0 High Pin input is high 1 PIN30 Pin 30 30 30 Low Pin input is low 0 High Pin input is high 1 PIN31 Pin 31 31 31 Low Pin input is low 0 High Pin input is high 1 DIR Direction of GPIO pins 0x514 read-write PIN0 Pin 0 0 0 Input Pin set as input 0 Output Pin set as output 1 PIN1 Pin 1 1 1 Input Pin set as input 0 Output Pin set as output 1 PIN2 Pin 2 2 2 Input Pin set as input 0 Output Pin set as output 1 PIN3 Pin 3 3 3 Input Pin set as input 0 Output Pin set as output 1 PIN4 Pin 4 4 4 Input Pin set as input 0 Output Pin set as output 1 PIN5 Pin 5 5 5 Input Pin set as input 0 Output Pin set as output 1 PIN6 Pin 6 6 6 Input Pin set as input 0 Output Pin set as output 1 PIN7 Pin 7 7 7 Input Pin set as input 0 Output Pin set as output 1 PIN8 Pin 8 8 8 Input Pin set as input 0 Output Pin set as output 1 PIN9 Pin 9 9 9 Input Pin set as input 0 Output Pin set as output 1 PIN10 Pin 10 10 10 Input Pin set as input 0 Output Pin set as output 1 PIN11 Pin 11 11 11 Input Pin set as input 0 Output Pin set as output 1 PIN12 Pin 12 12 12 Input Pin set as input 0 Output Pin set as output 1 PIN13 Pin 13 13 13 Input Pin set as input 0 Output Pin set as output 1 PIN14 Pin 14 14 14 Input Pin set as input 0 Output Pin set as output 1 PIN15 Pin 15 15 15 Input Pin set as input 0 Output Pin set as output 1 PIN16 Pin 16 16 16 Input Pin set as input 0 Output Pin set as output 1 PIN17 Pin 17 17 17 Input Pin set as input 0 Output Pin set as output 1 PIN18 Pin 18 18 18 Input Pin set as input 0 Output Pin set as output 1 PIN19 Pin 19 19 19 Input Pin set as input 0 Output Pin set as output 1 PIN20 Pin 20 20 20 Input Pin set as input 0 Output Pin set as output 1 PIN21 Pin 21 21 21 Input Pin set as input 0 Output Pin set as output 1 PIN22 Pin 22 22 22 Input Pin set as input 0 Output Pin set as output 1 PIN23 Pin 23 23 23 Input Pin set as input 0 Output Pin set as output 1 PIN24 Pin 24 24 24 Input Pin set as input 0 Output Pin set as output 1 PIN25 Pin 25 25 25 Input Pin set as input 0 Output Pin set as output 1 PIN26 Pin 26 26 26 Input Pin set as input 0 Output Pin set as output 1 PIN27 Pin 27 27 27 Input Pin set as input 0 Output Pin set as output 1 PIN28 Pin 28 28 28 Input Pin set as input 0 Output Pin set as output 1 PIN29 Pin 29 29 29 Input Pin set as input 0 Output Pin set as output 1 PIN30 Pin 30 30 30 Input Pin set as input 0 Output Pin set as output 1 PIN31 Pin 31 31 31 Input Pin set as input 0 Output Pin set as output 1 DIRSET DIR set register 0x518 read-write oneToSet PIN0 Set as output pin 0 0 0 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN1 Set as output pin 1 1 1 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN2 Set as output pin 2 2 2 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN3 Set as output pin 3 3 3 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN4 Set as output pin 4 4 4 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN5 Set as output pin 5 5 5 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN6 Set as output pin 6 6 6 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN7 Set as output pin 7 7 7 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN8 Set as output pin 8 8 8 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN9 Set as output pin 9 9 9 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN10 Set as output pin 10 10 10 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN11 Set as output pin 11 11 11 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN12 Set as output pin 12 12 12 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN13 Set as output pin 13 13 13 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN14 Set as output pin 14 14 14 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN15 Set as output pin 15 15 15 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN16 Set as output pin 16 16 16 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN17 Set as output pin 17 17 17 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN18 Set as output pin 18 18 18 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN19 Set as output pin 19 19 19 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN20 Set as output pin 20 20 20 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN21 Set as output pin 21 21 21 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN22 Set as output pin 22 22 22 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN23 Set as output pin 23 23 23 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN24 Set as output pin 24 24 24 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN25 Set as output pin 25 25 25 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN26 Set as output pin 26 26 26 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN27 Set as output pin 27 27 27 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN28 Set as output pin 28 28 28 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN29 Set as output pin 29 29 29 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN30 Set as output pin 30 30 30 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 PIN31 Set as output pin 31 31 31 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Set Write: writing a '1' sets pin to output; writing a '0' has no effect 1 DIRCLR DIR clear register 0x51C read-write oneToClear PIN0 Set as input pin 0 0 0 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN1 Set as input pin 1 1 1 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN2 Set as input pin 2 2 2 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN3 Set as input pin 3 3 3 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN4 Set as input pin 4 4 4 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN5 Set as input pin 5 5 5 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN6 Set as input pin 6 6 6 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN7 Set as input pin 7 7 7 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN8 Set as input pin 8 8 8 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN9 Set as input pin 9 9 9 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN10 Set as input pin 10 10 10 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN11 Set as input pin 11 11 11 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN12 Set as input pin 12 12 12 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN13 Set as input pin 13 13 13 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN14 Set as input pin 14 14 14 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN15 Set as input pin 15 15 15 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN16 Set as input pin 16 16 16 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN17 Set as input pin 17 17 17 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN18 Set as input pin 18 18 18 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN19 Set as input pin 19 19 19 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN20 Set as input pin 20 20 20 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN21 Set as input pin 21 21 21 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN22 Set as input pin 22 22 22 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN23 Set as input pin 23 23 23 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN24 Set as input pin 24 24 24 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN25 Set as input pin 25 25 25 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN26 Set as input pin 26 26 26 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN27 Set as input pin 27 27 27 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN28 Set as input pin 28 28 28 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN29 Set as input pin 29 29 29 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN30 Set as input pin 30 30 30 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 PIN31 Set as input pin 31 31 31 read Input Read: pin set as input 0 Output Read: pin set as output 1 write Clear Write: writing a '1' sets pin to input; writing a '0' has no effect 1 LATCH Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers 0x520 read-write PIN0 Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. 0 0 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN1 Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. 1 1 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN2 Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. 2 2 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN3 Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. 3 3 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN4 Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. 4 4 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN5 Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. 5 5 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN6 Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. 6 6 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN7 Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. 7 7 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN8 Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. 8 8 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN9 Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. 9 9 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN10 Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. 10 10 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN11 Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. 11 11 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN12 Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. 12 12 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN13 Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. 13 13 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN14 Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. 14 14 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN15 Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. 15 15 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN16 Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. 16 16 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN17 Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. 17 17 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN18 Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. 18 18 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN19 Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. 19 19 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN20 Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. 20 20 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN21 Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. 21 21 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN22 Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. 22 22 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN23 Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. 23 23 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN24 Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. 24 24 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN25 Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. 25 25 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN26 Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. 26 26 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN27 Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. 27 27 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN28 Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. 28 28 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN29 Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. 29 29 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN30 Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. 30 30 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 PIN31 Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. 31 31 NotLatched Criteria has not been met 0 Latched Criteria has been met 1 DETECTMODE Select between default DETECT signal behaviour and LDETECT mode 0x524 read-write DETECTMODE Select between default DETECT signal behaviour and LDETECT mode 0 0 Default DETECT directly connected to PIN DETECT signals 0 LDETECT Use the latched LDETECT behaviour 1 0x20 0x4 PIN_CNF[%s] Description collection[n]: Configuration of GPIO pins 0x700 read-write 0x00000002 DIR Pin direction. Same physical register as DIR register 0 0 Input Configure pin as an input pin 0 Output Configure pin as an output pin 1 INPUT Connect or disconnect input buffer 1 1 Connect Connect input buffer 0 Disconnect Disconnect input buffer 1 PULL Pull configuration 2 3 Disabled No pull 0 Pulldown Pull down on pin 1 Pullup Pull up on pin 3 DRIVE Drive configuration 8 10 S0S1 Standard '0', standard '1' 0 H0S1 High drive '0', standard '1' 1 S0H1 Standard '0', high drive '1' 2 H0H1 High drive '0', high 'drive '1'' 3 D0S1 Disconnect '0' standard '1' (normally used for wired-or connections) 4 D0H1 Disconnect '0', high drive '1' (normally used for wired-or connections) 5 S0D1 Standard '0'. disconnect '1' (normally used for wired-and connections) 6 H0D1 High drive '0', disconnect '1' (normally used for wired-and connections) 7 SENSE Pin sensing mechanism 16 17 Disabled Disabled 0 High Sense for high level 2 Low Sense for low level 3 P1 GPIO Port 2 0x50000300 P0 CC_HOST_RGF CRYPTOCELL HOST_RGF interface 0x5002A000 0 0x2000 registers CC_HOST_RGF 0x20 HOST_CRYPTOKEY_SEL AES hardware key select 0x1A38 read-write 0x00000000 HOST_CRYPTOKEY_SEL Select the source of the HW key that is used by the AES engine 0 1 K_DR Use device root key K_DR from CRYPTOCELL AO power domain 0 K_PRTL Use hard-coded RTL key K_PRTL 1 Session Use provided session key 2 HOST_IOT_KPRTL_LOCK This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A4C read-write 0x00000000 HOST_IOT_KPRTL_LOCK This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. 0 0 Disabled K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL 0 Enabled K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. 1 HOST_IOT_KDR0 This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. 0x1A50 read-write 0x00000000 HOST_IOT_KDR0 Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain 0 31 HOST_IOT_KDR1 This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A54 write-only 0x00000000 HOST_IOT_KDR1 K_DR bits 63:32 0 31 HOST_IOT_KDR2 This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A58 write-only 0x00000000 HOST_IOT_KDR2 K_DR bits 95:64 0 31 HOST_IOT_KDR3 This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 0x1A5C write-only 0x00000000 HOST_IOT_KDR3 K_DR bits 127:96 0 31 HOST_IOT_LCS Controls lifecycle state (LCS) for CRYPTOCELL subsystem 0x1A60 read-write 0x00000002 LCS Lifecycle state value. This field is write-once per reset. 0 2 Debug CC310 operates in debug mode 0 Secure CC310 operates in secure mode 2 LCS_IS_VALID This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset 8 8 Invalid A valid LCS is not yet retained in the CRYPTOCELL AO power domain 0 Valid A valid LCS is successfully retained in the CRYPTOCELL AO power domain 1 CRYPTOCELL ARM TrustZone CryptoCell register interface 0x5002A000 CC_HOST_RGF 0 0x2000 registers CRYPTOCELL 42 CRYPTOCELL 0x20 ENABLE Enable CRYPTOCELL subsystem 0x500 read-write 0x00000000 ENABLE Enable or disable the CRYPTOCELL subsystem 0 0 Disabled CRYPTOCELL subsystem disabled 0 Enabled CRYPTOCELL subsystem enabled 1