/*
 * ******************************************************************************************
 * Copyright (c) 2019 Pascal Kuthe. This file is part of the OpenVAF project.
 * It is subject to the license terms in the LICENSE file found in the top-level directory
 *  of this distribution and at  https://gitlab.com/DSPOM/OpenVAF/blob/master/LICENSE.
 *  No part of OpenVAF, including this file, may be copied, modified, propagated, or
 *  distributed except according to the terms contained in the LICENSE file.
 * *****************************************************************************************
 */
module test1;
endmodule

module test2 (a,b,c,d,e,f,g);
    output a;
    input signed b;
    inout wire c;
    inout electrical d;
    output electrical e,f;
    inout electrical wire signed g;
endmodule

module test3 (output a,input electrical b,inout electrical tri c);
   /*
    * lel
    *lele
    */
endmodule