; BTOR description generated by Yosys 0.20+42 (git sha1 1c36f4cc2, clang 10.0.0-4ubuntu1 -fPIC -Os) for module i2c_master_top.
1 sort bitvec 1
2 input 1 sda_pad_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:132.9-132.18
3 input 1 scl_pad_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:129.9-129.18
4 input 1 wb_cyc_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:123.9-123.17
5 input 1 wb_stb_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:122.9-122.17
6 input 1 wb_we_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:121.9-121.16
7 sort bitvec 8
8 input 7 wb_dat_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:119.15-119.23
9 sort bitvec 3
10 input 9 wb_adr_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:118.15-118.23
11 input 1 arst_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:117.9-117.15
12 input 1 wb_rst_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:116.9-116.17
13 input 1 wb_clk_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:115.9-115.17
14 state 1 byte_controller.bit_controller.sda_oen
15 output 14 sda_padoen_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:134.10-134.22
16 const 1 0
17 output 16 sda_pad_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:133.10-133.19
18 state 1 byte_controller.bit_controller.scl_oen
19 output 18 scl_padoen_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:131.10-131.22
20 output 16 scl_pad_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:130.10-130.19
21 state 1
22 output 21 wb_inta_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:125.10-125.19
23 state 1
24 output 23 wb_ack_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:124.10-124.18
25 state 7
26 output 25 wb_dat_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:120.16-120.24
27 uext 1 13 0 byte_controller.clk ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:82.8-82.11
28 uext 1 12 0 byte_controller.rst ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:83.8-83.11
29 state 1 $anyconst$46 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:69.52-69.61
30 next 1 29 29
31 state 1 $anyconst$1 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:24.66-24.75
32 next 1 31 31
33 ite 1 31 29 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:151$91 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:151.39-151.95
34 xor 1 11 33 $xor$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:151$92 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:151.29-151.96
35 uext 1 34 0 byte_controller.nReset ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:84.8-84.14
36 sort bitvec 32
37 state 7 ctr
38 uext 36 37 24
39 const 36 00000000000000000000000000000111
40 state 36 $anyconst$78 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:101.61-101.70
41 next 36 40 40
42 state 1 $anyconst$33 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:56.68-56.77
43 next 1 42 42
44 ite 36 42 40 39 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:204$145 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:204.24-204.75
45 srl 36 38 44
46 neg 36 44
47 sll 36 38 46
48 const 36 00000000000000000000000000000000
49 slt 1 44 48
50 ite 36 49 47 45 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$146 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
51 slice 1 50 0 0
52 uext 1 51 0 byte_controller.ena ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:85.8-85.11
53 sort bitvec 16
54 state 53 prer
55 uext 53 54 0 byte_controller.clk_cnt ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:87.15-87.22
56 state 7 cr
57 uext 36 56 24
58 state 36 $anyconst$72 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:95.61-95.70
59 next 36 58 58
60 state 1 $anyconst$27 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:50.68-50.77
61 next 1 60 60
62 ite 36 60 58 39 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:198$132 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:198.28-198.79
63 srl 36 57 62
64 neg 36 62
65 sll 36 57 64
66 slt 1 62 48
67 ite 36 66 65 63 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$133 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
68 slice 1 67 0 0
69 uext 1 68 0 byte_controller.start ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:90.14-90.19
70 uext 36 56 24
71 const 36 00000000000000000000000000000110
72 state 36 $anyconst$73 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:96.61-96.70
73 next 36 72 72
74 state 1 $anyconst$28 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:51.68-51.77
75 next 1 74 74
76 ite 36 74 72 71 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:199$134 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:199.28-199.79
77 srl 36 70 76
78 neg 36 76
79 sll 36 70 78
80 slt 1 76 48
81 ite 36 80 79 77 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$135 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
82 slice 1 81 0 0
83 uext 1 82 0 byte_controller.stop ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:91.14-91.18
84 uext 36 56 24
85 const 36 00000000000000000000000000000101
86 state 36 $anyconst$74 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:97.61-97.70
87 next 36 86 86
88 state 1 $anyconst$29 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:52.68-52.77
89 next 1 88 88
90 ite 36 88 86 85 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:200$136 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:200.26-200.77
91 srl 36 84 90
92 neg 36 90
93 sll 36 84 92
94 slt 1 90 48
95 ite 36 94 93 91 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$137 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
96 slice 1 95 0 0
97 uext 1 96 0 byte_controller.read ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:92.14-92.18
98 uext 36 56 24
99 const 36 00000000000000000000000000000100
100 state 36 $anyconst$75 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:98.61-98.70
101 next 36 100 100
102 state 1 $anyconst$30 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:53.68-53.77
103 next 1 102 102
104 ite 36 102 100 99 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:201$138 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:201.26-201.77
105 srl 36 98 104
106 neg 36 104
107 sll 36 98 106
108 slt 1 104 48
109 ite 36 108 107 105 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$139 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
110 slice 1 109 0 0
111 uext 1 110 0 byte_controller.write ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:93.14-93.19
112 uext 36 56 24
113 const 36 00000000000000000000000000000011
114 state 36 $anyconst$76 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:99.61-99.70
115 next 36 114 114
116 state 1 $anyconst$31 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:54.68-54.77
117 next 1 116 116
118 ite 36 116 114 113 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:202$140 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:202.28-202.79
119 srl 36 112 118
120 neg 36 118
121 sll 36 112 120
122 slt 1 118 48
123 ite 36 122 121 119 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$141 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
124 slice 1 123 0 0
125 uext 1 124 0 byte_controller.ack_in ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:94.14-94.20
126 state 7 txr
127 uext 7 126 0 byte_controller.din ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:95.14-95.17
128 state 1 byte_controller.cmd_ack
129 state 1 byte_controller.ack_out
130 state 1 byte_controller.bit_controller.busy
131 uext 1 130 0 byte_controller.i2c_busy ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:102.15-102.23
132 state 1 byte_controller.bit_controller.al
133 uext 1 132 0 byte_controller.i2c_al ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:103.15-103.21
134 state 7 byte_controller.sr
135 uext 7 134 0 byte_controller.dout ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:104.15-104.19
136 uext 1 3 0 byte_controller.scl_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:107.9-107.14
137 uext 1 16 0 byte_controller.scl_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:108.9-108.14
138 uext 1 18 0 byte_controller.scl_oen ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:109.9-109.16
139 uext 1 2 0 byte_controller.sda_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:110.9-110.14
140 uext 1 16 0 byte_controller.sda_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:111.9-111.14
141 uext 1 14 0 byte_controller.sda_oen ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:112.9-112.16
142 sort bitvec 4
143 state 142 byte_controller.core_cmd
144 state 1 byte_controller.core_txd
145 state 1 byte_controller.bit_controller.cmd_ack
146 uext 1 145 0 byte_controller.core_ack ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:130.13-130.21
147 state 1 byte_controller.bit_controller.dout
148 uext 1 147 0 byte_controller.core_rxd ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:130.23-130.31
149 state 1 byte_controller.shift
150 state 1 byte_controller.ld
151 or 1 96 110 $flatten\byte_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167$173 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167.15-167.27
152 or 1 151 82 $flatten\byte_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167$174 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167.15-167.34
153 not 1 128 $flatten\byte_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167$175 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167.38-167.46
154 and 1 152 153 $flatten\byte_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167$176 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:167.14-167.46
155 uext 1 154 0 byte_controller.go ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:137.13-137.15
156 state 9 byte_controller.dcnt
157 redor 1 156 $flatten\byte_controller.$reduce_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:194$182 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:194.22-194.27
158 not 1 157 $flatten\byte_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:194$183 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:194.20-194.28
159 uext 1 158 0 byte_controller.cnt_done ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:139.13-139.21
160 sort bitvec 5
161 state 160 byte_controller.c_state
162 state 1 byte_controller.bit_controller.cmd_stop
163 state 1 byte_controller.bit_controller.sto_condition
164 state 1 byte_controller.bit_controller.sta_condition
165 state 1 byte_controller.bit_controller.dSCL
166 state 1 byte_controller.bit_controller.sSCL
167 not 1 166 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:204$197 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:204.30-204.35|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
168 and 1 165 167 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:204$198 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:204.23-204.35|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
169 and 1 168 18 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:204$199 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:204.23-204.45|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
170 uext 1 169 0 byte_controller.bit_controller.scl_sync ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:204.10-204.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
171 sort bitvec 18
172 state 171 byte_controller.bit_controller.c_state
173 sort bitvec 14
174 state 173 byte_controller.bit_controller.filter_cnt
175 state 53 byte_controller.bit_controller.cnt
176 state 1 byte_controller.bit_controller.slave_wait
177 state 1 byte_controller.bit_controller.clk_en
178 state 1 byte_controller.bit_controller.sda_chk
179 state 1 byte_controller.bit_controller.dscl_oen
180 state 1 byte_controller.bit_controller.dSDA
181 state 1 byte_controller.bit_controller.sSDA
182 state 9 byte_controller.bit_controller.fSDA
183 state 9 byte_controller.bit_controller.fSCL
184 sort bitvec 2
185 state 184 byte_controller.bit_controller.cSDA
186 state 184 byte_controller.bit_controller.cSCL
187 uext 1 16 0 byte_controller.bit_controller.sda_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:163.23-163.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
188 uext 1 2 0 byte_controller.bit_controller.sda_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:162.23-162.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
189 uext 1 16 0 byte_controller.bit_controller.scl_o ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:160.23-160.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
190 uext 1 3 0 byte_controller.bit_controller.scl_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:159.23-159.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
191 uext 1 144 0 byte_controller.bit_controller.din ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:156.23-156.26|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
192 uext 142 143 0 byte_controller.bit_controller.cmd ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:151.23-151.26|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
193 uext 53 54 0 byte_controller.bit_controller.clk_cnt ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:149.23-149.30|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
194 uext 1 51 0 byte_controller.bit_controller.ena ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:147.23-147.26|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
195 uext 1 34 0 byte_controller.bit_controller.nReset ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:146.23-146.29|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
196 uext 1 12 0 byte_controller.bit_controller.rst ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:145.23-145.26|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
197 uext 1 13 0 byte_controller.bit_controller.clk ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:144.23-144.26|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
198 uext 36 56 24
199 state 7 $anyconst$77 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:100.60-100.69
200 next 7 199 199
201 uext 36 199 24
202 state 1 $anyconst$32 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:55.68-55.77
203 next 1 202 202
204 ite 36 202 201 48 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:203$143 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:203.30-203.81
205 srl 36 198 204
206 neg 36 204
207 sll 36 198 206
208 slt 1 204 48
209 ite 36 208 207 205 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$144 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
210 slice 1 209 0 0
211 uext 1 210 0 iack ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:203.8-203.12
212 uext 1 124 0 ack ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:202.8-202.11
213 uext 1 110 0 wr ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:201.8-201.10
214 uext 1 96 0 rd ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:200.8-200.10
215 uext 1 82 0 sto ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:199.8-199.11
216 uext 1 68 0 sta ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:198.8-198.11
217 and 1 6 23 $and$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:152$93 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:152.33-152.51
218 uext 1 217 0 wb_wacc ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:152.8-152.15
219 uext 1 34 0 rst_i ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:151.8-151.13
220 state 1 al
221 uext 1 132 0 i2c_al ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:149.8-149.14
222 uext 1 130 0 i2c_busy ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:148.8-148.16
223 state 1 irq_flag
224 state 1 tip
225 state 1 rxack
226 uext 1 129 0 irxack ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:144.8-144.14
227 uext 36 37 24
228 state 36 $anyconst$79 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:102.61-102.70
229 next 36 228 228
230 state 1 $anyconst$34 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:57.68-57.77
231 next 1 230 230
232 ite 36 230 228 71 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:205$147 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:205.20-205.71
233 srl 36 227 232
234 neg 36 232
235 sll 36 227 234
236 slt 1 232 48
237 ite 36 236 235 233 $shiftx$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0$148 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0
238 slice 1 237 0 0
239 uext 1 238 0 ien ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:143.8-143.11
240 uext 1 51 0 core_en ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:142.8-142.15
241 uext 1 128 0 done ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:141.8-141.12
242 const 9 000
243 state 9 $anyconst$90 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:113.60-113.69
244 next 9 243 243
245 state 1 $anyconst$45 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:68.68-68.77
246 next 1 245 245
247 ite 9 245 243 242 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:260$172 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:260.20-260.74
248 concat 184 224 223
249 concat 160 247 248
250 sort bitvec 6
251 concat 250 220 249
252 sort bitvec 7
253 concat 252 130 251
254 concat 7 225 253
255 uext 7 254 0 sr ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:140.14-140.16
256 uext 7 134 0 rxr ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:138.14-138.17
257 uext 9 243 0 __synth_literal_44 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:113.13-113.31
258 state 1 $anyconst$89 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:112.54-112.63
259 next 1 258 258
260 uext 1 258 0 __synth_literal_43 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:112.7-112.25
261 state 1 $anyconst$88 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:111.54-111.63
262 next 1 261 261
263 uext 1 261 0 __synth_literal_42 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:111.7-111.25
264 state 1 $anyconst$87 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:110.54-110.63
265 next 1 264 264
266 uext 1 264 0 __synth_literal_41 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:110.7-110.25
267 state 1 $anyconst$86 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:109.54-109.63
268 next 1 267 267
269 uext 1 267 0 __synth_literal_40 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:109.7-109.25
270 state 1 $anyconst$85 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:108.54-108.63
271 next 1 270 270
272 uext 1 270 0 __synth_literal_39 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:108.7-108.25
273 state 1 $anyconst$84 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:107.54-107.63
274 next 1 273 273
275 uext 1 273 0 __synth_literal_38 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:107.7-107.25
276 state 1 $anyconst$83 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:106.54-106.63
277 next 1 276 276
278 uext 1 276 0 __synth_literal_37 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:106.7-106.25
279 state 1 $anyconst$82 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:105.54-105.63
280 next 1 279 279
281 uext 1 279 0 __synth_literal_36 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:105.7-105.25
282 state 1 $anyconst$81 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:104.54-104.63
283 next 1 282 282
284 uext 1 282 0 __synth_literal_35 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:104.7-104.25
285 state 1 $anyconst$80 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:103.54-103.63
286 next 1 285 285
287 uext 1 285 0 __synth_literal_34 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:103.7-103.25
288 uext 36 228 0 __synth_literal_33 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:102.14-102.32
289 uext 36 40 0 __synth_literal_32 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:101.14-101.32
290 uext 7 199 0 __synth_literal_31 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:100.13-100.31
291 uext 36 114 0 __synth_literal_30 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:99.14-99.32
292 uext 36 100 0 __synth_literal_29 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:98.14-98.32
293 uext 36 86 0 __synth_literal_28 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:97.14-97.32
294 uext 36 72 0 __synth_literal_27 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:96.14-96.32
295 uext 36 58 0 __synth_literal_26 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:95.14-95.32
296 state 7 $anyconst$71 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:94.60-94.69
297 next 7 296 296
298 uext 7 296 0 __synth_literal_25 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:94.13-94.31
299 state 7 $anyconst$70 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:93.60-93.69
300 next 7 299 299
301 uext 7 299 0 __synth_literal_24 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:93.13-93.31
302 state 9 $anyconst$69 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:92.60-92.69
303 next 9 302 302
304 uext 9 302 0 __synth_literal_23 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:92.13-92.31
305 state 1 $anyconst$68 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:91.54-91.63
306 next 1 305 305
307 uext 1 305 0 __synth_literal_22 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:91.7-91.25
308 state 184 $anyconst$67 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:90.60-90.69
309 next 184 308 308
310 uext 184 308 0 __synth_literal_21 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:90.13-90.31
311 state 142 $anyconst$66 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:89.60-89.69
312 next 142 311 311
313 uext 142 311 0 __synth_literal_20 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:89.13-89.31
314 state 7 $anyconst$65 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:88.60-88.69
315 next 7 314 314
316 uext 7 314 0 __synth_literal_19 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:88.13-88.31
317 state 7 $anyconst$64 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:87.60-87.69
318 next 7 317 317
319 uext 7 317 0 __synth_literal_18 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:87.13-87.31
320 state 53 $anyconst$63 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:86.61-86.70
321 next 53 320 320
322 uext 53 320 0 __synth_literal_17 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:86.14-86.32
323 state 7 $anyconst$62 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:85.60-85.69
324 next 7 323 323
325 uext 7 323 0 __synth_literal_16 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:85.13-85.31
326 state 7 $anyconst$61 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:84.60-84.69
327 next 7 326 326
328 uext 7 326 0 __synth_literal_15 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:84.13-84.31
329 state 53 $anyconst$60 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:83.61-83.70
330 next 53 329 329
331 uext 53 329 0 __synth_literal_14 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:83.14-83.32
332 state 9 $anyconst$59 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:82.60-82.69
333 next 9 332 332
334 uext 9 332 0 __synth_literal_13 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:82.13-82.31
335 state 9 $anyconst$58 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:81.60-81.69
336 next 9 335 335
337 uext 9 335 0 __synth_literal_12 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:81.13-81.31
338 state 9 $anyconst$57 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:80.60-80.69
339 next 9 338 338
340 uext 9 338 0 __synth_literal_11 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:80.13-80.31
341 state 9 $anyconst$56 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:79.60-79.69
342 next 9 341 341
343 uext 9 341 0 __synth_literal_10 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:79.13-79.31
344 state 7 $anyconst$55 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:78.58-78.67
345 next 7 344 344
346 uext 7 344 0 __synth_literal_9 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:78.13-78.30
347 state 9 $anyconst$54 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:77.58-77.67
348 next 9 347 347
349 uext 9 347 0 __synth_literal_8 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:77.13-77.30
350 state 9 $anyconst$53 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:76.58-76.67
351 next 9 350 350
352 uext 9 350 0 __synth_literal_7 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:76.13-76.30
353 state 9 $anyconst$52 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:75.58-75.67
354 next 9 353 353
355 uext 9 353 0 __synth_literal_6 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:75.13-75.30
356 state 9 $anyconst$51 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:74.58-74.67
357 next 9 356 356
358 uext 9 356 0 __synth_literal_5 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:74.13-74.30
359 state 9 $anyconst$50 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:73.58-73.67
360 next 9 359 359
361 uext 9 359 0 __synth_literal_4 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:73.13-73.30
362 state 9 $anyconst$49 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:72.58-72.67
363 next 9 362 362
364 uext 9 362 0 __synth_literal_3 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:72.13-72.30
365 state 9 $anyconst$48 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:71.58-71.67
366 next 9 365 365
367 uext 9 365 0 __synth_literal_2 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:71.13-71.30
368 state 9 $anyconst$47 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:70.58-70.67
369 next 9 368 368
370 uext 9 368 0 __synth_literal_1 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:70.13-70.30
371 uext 1 29 0 __synth_literal_0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:69.7-69.24
372 uext 1 245 0 __synth_change_literal_44 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:68.7-68.32
373 state 1 $anyconst$44 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:67.68-67.77
374 next 1 373 373
375 uext 1 373 0 __synth_change_literal_43 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:67.7-67.32
376 state 1 $anyconst$43 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:66.68-66.77
377 next 1 376 376
378 uext 1 376 0 __synth_change_literal_42 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:66.7-66.32
379 state 1 $anyconst$42 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:65.68-65.77
380 next 1 379 379
381 uext 1 379 0 __synth_change_literal_41 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:65.7-65.32
382 state 1 $anyconst$41 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:64.68-64.77
383 next 1 382 382
384 uext 1 382 0 __synth_change_literal_40 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:64.7-64.32
385 state 1 $anyconst$40 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:63.68-63.77
386 next 1 385 385
387 uext 1 385 0 __synth_change_literal_39 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:63.7-63.32
388 state 1 $anyconst$39 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:62.68-62.77
389 next 1 388 388
390 uext 1 388 0 __synth_change_literal_38 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:62.7-62.32
391 state 1 $anyconst$38 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:61.68-61.77
392 next 1 391 391
393 uext 1 391 0 __synth_change_literal_37 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:61.7-61.32
394 state 1 $anyconst$37 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:60.68-60.77
395 next 1 394 394
396 uext 1 394 0 __synth_change_literal_36 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:60.7-60.32
397 state 1 $anyconst$36 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:59.68-59.77
398 next 1 397 397
399 uext 1 397 0 __synth_change_literal_35 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:59.7-59.32
400 state 1 $anyconst$35 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:58.68-58.77
401 next 1 400 400
402 uext 1 400 0 __synth_change_literal_34 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:58.7-58.32
403 uext 1 230 0 __synth_change_literal_33 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:57.7-57.32
404 uext 1 42 0 __synth_change_literal_32 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:56.7-56.32
405 uext 1 202 0 __synth_change_literal_31 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:55.7-55.32
406 uext 1 116 0 __synth_change_literal_30 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:54.7-54.32
407 uext 1 102 0 __synth_change_literal_29 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:53.7-53.32
408 uext 1 88 0 __synth_change_literal_28 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:52.7-52.32
409 uext 1 74 0 __synth_change_literal_27 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:51.7-51.32
410 uext 1 60 0 __synth_change_literal_26 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:50.7-50.32
411 state 1 $anyconst$26 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:49.68-49.77
412 next 1 411 411
413 uext 1 411 0 __synth_change_literal_25 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:49.7-49.32
414 state 1 $anyconst$25 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:48.68-48.77
415 next 1 414 414
416 uext 1 414 0 __synth_change_literal_24 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:48.7-48.32
417 state 1 $anyconst$24 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:47.68-47.77
418 next 1 417 417
419 uext 1 417 0 __synth_change_literal_23 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:47.7-47.32
420 state 1 $anyconst$23 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:46.68-46.77
421 next 1 420 420
422 uext 1 420 0 __synth_change_literal_22 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:46.7-46.32
423 state 1 $anyconst$22 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:45.68-45.77
424 next 1 423 423
425 uext 1 423 0 __synth_change_literal_21 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:45.7-45.32
426 state 1 $anyconst$21 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:44.68-44.77
427 next 1 426 426
428 uext 1 426 0 __synth_change_literal_20 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:44.7-44.32
429 state 1 $anyconst$20 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:43.68-43.77
430 next 1 429 429
431 uext 1 429 0 __synth_change_literal_19 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:43.7-43.32
432 state 1 $anyconst$19 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:42.68-42.77
433 next 1 432 432
434 uext 1 432 0 __synth_change_literal_18 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:42.7-42.32
435 state 1 $anyconst$18 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:41.68-41.77
436 next 1 435 435
437 uext 1 435 0 __synth_change_literal_17 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:41.7-41.32
438 state 1 $anyconst$17 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:40.68-40.77
439 next 1 438 438
440 uext 1 438 0 __synth_change_literal_16 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:40.7-40.32
441 state 1 $anyconst$16 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:39.68-39.77
442 next 1 441 441
443 uext 1 441 0 __synth_change_literal_15 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:39.7-39.32
444 state 1 $anyconst$15 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:38.68-38.77
445 next 1 444 444
446 uext 1 444 0 __synth_change_literal_14 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:38.7-38.32
447 state 1 $anyconst$14 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:37.68-37.77
448 next 1 447 447
449 uext 1 447 0 __synth_change_literal_13 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:37.7-37.32
450 state 1 $anyconst$13 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:36.68-36.77
451 next 1 450 450
452 uext 1 450 0 __synth_change_literal_12 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:36.7-36.32
453 state 1 $anyconst$12 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:35.68-35.77
454 next 1 453 453
455 uext 1 453 0 __synth_change_literal_11 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:35.7-35.32
456 state 1 $anyconst$11 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:34.68-34.77
457 next 1 456 456
458 uext 1 456 0 __synth_change_literal_10 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:34.7-34.32
459 state 1 $anyconst$10 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:33.66-33.75
460 next 1 459 459
461 uext 1 459 0 __synth_change_literal_9 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:33.7-33.31
462 state 1 $anyconst$9 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:32.66-32.75
463 next 1 462 462
464 uext 1 462 0 __synth_change_literal_8 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:32.7-32.31
465 state 1 $anyconst$8 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:31.66-31.75
466 next 1 465 465
467 uext 1 465 0 __synth_change_literal_7 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:31.7-31.31
468 state 1 $anyconst$7 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:30.66-30.75
469 next 1 468 468
470 uext 1 468 0 __synth_change_literal_6 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:30.7-30.31
471 state 1 $anyconst$6 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:29.66-29.75
472 next 1 471 471
473 uext 1 471 0 __synth_change_literal_5 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:29.7-29.31
474 state 1 $anyconst$5 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:28.66-28.75
475 next 1 474 474
476 uext 1 474 0 __synth_change_literal_4 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:28.7-28.31
477 state 1 $anyconst$4 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:27.66-27.75
478 next 1 477 477
479 uext 1 477 0 __synth_change_literal_3 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:27.7-27.31
480 state 1 $anyconst$3 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:26.66-26.75
481 next 1 480 480
482 uext 1 480 0 __synth_change_literal_2 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:26.7-26.31
483 state 1 $anyconst$2 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:25.66-25.75
484 next 1 483 483
485 uext 1 483 0 __synth_change_literal_1 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:25.7-25.31
486 uext 1 31 0 __synth_change_literal_0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:24.7-24.31
487 const 171 010000000000000000
488 eq 1 172 487 $flatten\byte_controller.\bit_controller.$procmux$345_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
489 ite 1 488 144 14
490 const 171 001000000000000000
491 eq 1 172 490 $flatten\byte_controller.\bit_controller.$procmux$346_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
492 ite 1 491 144 489
493 const 171 000100000000000000
494 eq 1 172 493 $flatten\byte_controller.\bit_controller.$procmux$347_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
495 ite 1 494 144 492
496 const 171 000010000000000000
497 eq 1 172 496 $flatten\byte_controller.\bit_controller.$procmux$348_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
498 ite 1 497 144 495
499 const 1 1
500 const 171 000001000000000000
501 eq 1 172 500 $flatten\byte_controller.\bit_controller.$procmux$349_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
502 ite 1 501 499 498
503 const 171 000000100000000000
504 eq 1 172 503 $flatten\byte_controller.\bit_controller.$procmux$350_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
505 ite 1 504 499 502
506 const 171 000000010000000000
507 eq 1 172 506 $flatten\byte_controller.\bit_controller.$procmux$351_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
508 ite 1 507 499 505
509 const 171 000000001000000000
510 eq 1 172 509 $flatten\byte_controller.\bit_controller.$procmux$352_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
511 ite 1 510 499 508
512 const 171 000000000100000000
513 eq 1 172 512 $flatten\byte_controller.\bit_controller.$procmux$353_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
514 ite 1 513 499 511
515 const 171 000000000010000000
516 eq 1 172 515 $flatten\byte_controller.\bit_controller.$procmux$354_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
517 ite 1 516 16 514
518 const 171 000000000001000000
519 eq 1 172 518 $flatten\byte_controller.\bit_controller.$procmux$355_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
520 ite 1 519 16 517
521 const 171 000000000000100000
522 eq 1 172 521 $flatten\byte_controller.\bit_controller.$procmux$356_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
523 ite 1 522 16 520
524 const 171 000000000000010000
525 eq 1 172 524 $flatten\byte_controller.\bit_controller.$procmux$357_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
526 ite 1 525 16 523
527 const 171 000000000000001000
528 eq 1 172 527 $flatten\byte_controller.\bit_controller.$procmux$358_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
529 ite 1 528 16 526
530 const 171 000000000000000100
531 eq 1 172 530 $flatten\byte_controller.\bit_controller.$procmux$359_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
532 ite 1 531 16 529
533 const 171 000000000000000010
534 eq 1 172 533 $flatten\byte_controller.\bit_controller.$procmux$360_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
535 ite 1 534 499 532
536 const 171 000000000000000001
537 eq 1 172 536 $flatten\byte_controller.\bit_controller.$procmux$361_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
538 ite 1 537 499 535 $flatten\byte_controller.\bit_controller.$procmux$344 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
539 ite 1 177 538 14 $flatten\byte_controller.\bit_controller.$procmux$362 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.15-405.21|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.11-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
540 or 1 12 132 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393$266 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.16-393.24|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
541 ite 1 540 499 539 $flatten\byte_controller.\bit_controller.$procmux$365 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.16-393.24|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.12-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
542 not 1 34 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385$265 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.11-385.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
543 ite 1 542 499 541 $flatten\byte_controller.\bit_controller.$procmux$368 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.11-385.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.7-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
544 next 1 14 543 $flatten\byte_controller.\bit_controller.$procdff$865 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:384.5-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
545 eq 1 172 487 $flatten\byte_controller.\bit_controller.$procmux$372_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
546 ite 1 545 16 18
547 eq 1 172 490 $flatten\byte_controller.\bit_controller.$procmux$373_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
548 ite 1 547 499 546
549 eq 1 172 493 $flatten\byte_controller.\bit_controller.$procmux$374_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
550 ite 1 549 499 548
551 eq 1 172 496 $flatten\byte_controller.\bit_controller.$procmux$375_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
552 ite 1 551 16 550
553 eq 1 172 500 $flatten\byte_controller.\bit_controller.$procmux$376_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
554 ite 1 553 16 552
555 eq 1 172 503 $flatten\byte_controller.\bit_controller.$procmux$377_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
556 ite 1 555 499 554
557 eq 1 172 506 $flatten\byte_controller.\bit_controller.$procmux$378_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
558 ite 1 557 499 556
559 eq 1 172 509 $flatten\byte_controller.\bit_controller.$procmux$379_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
560 ite 1 559 16 558
561 eq 1 172 512 $flatten\byte_controller.\bit_controller.$procmux$380_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
562 ite 1 561 499 560
563 eq 1 172 515 $flatten\byte_controller.\bit_controller.$procmux$381_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
564 ite 1 563 499 562
565 eq 1 172 518 $flatten\byte_controller.\bit_controller.$procmux$382_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
566 ite 1 565 499 564
567 eq 1 172 521 $flatten\byte_controller.\bit_controller.$procmux$383_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
568 ite 1 567 16 566
569 eq 1 172 524 $flatten\byte_controller.\bit_controller.$procmux$384_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
570 ite 1 569 16 568
571 eq 1 172 527 $flatten\byte_controller.\bit_controller.$procmux$385_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
572 ite 1 571 499 570
573 eq 1 172 530 $flatten\byte_controller.\bit_controller.$procmux$386_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
574 ite 1 573 499 572
575 eq 1 172 533 $flatten\byte_controller.\bit_controller.$procmux$387_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
576 ite 1 575 499 574 $flatten\byte_controller.\bit_controller.$procmux$371 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
577 ite 1 177 576 18 $flatten\byte_controller.\bit_controller.$procmux$388 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.15-405.21|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.11-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
578 ite 1 540 499 577 $flatten\byte_controller.\bit_controller.$procmux$391 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.16-393.24|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.12-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
579 ite 1 542 499 578 $flatten\byte_controller.\bit_controller.$procmux$394 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.11-385.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.7-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
580 next 1 18 579 $flatten\byte_controller.\bit_controller.$procdff$864 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:384.5-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
581 and 1 223 238 $logic_and$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:255$171 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:255.24-255.39
582 ite 1 376 261 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:254$170 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:254.37-254.91
583 ite 1 12 582 581 $procmux$714 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:254.11-254.19|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:254.8-255.40
584 ite 1 373 258 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:253$169 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:253.57-253.111
585 not 1 34 $logic_not$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:253$168 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:253.33-253.39
586 ite 1 585 584 583 $procmux$717 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:253.33-253.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:253.30-255.40
587 next 1 21 586 $procdff$896 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:253.3-255.40
588 and 1 4 5 $and$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:154$95 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:154.45-154.64
589 not 1 23 $not$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:154$96 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:154.67-154.76
590 and 1 588 589 $and$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:154$97 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:154.45-154.76
591 next 1 23 590 $procdff$906 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:154.3-154.77
592 uext 36 344 24
593 ite 36 459 592 48 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:166$108 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:166.78-166.127
594 slice 7 593 7 0
595 const 9 111
596 ite 9 462 347 595 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:166$106 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:166.7-166.61
597 eq 1 10 596 $procmux$848_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
598 ite 7 597 594 25 $procmux$847 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
599 const 9 110
600 ite 9 465 350 599 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:165$105 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:165.7-165.61
601 eq 1 10 600 $procmux$850_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
602 ite 7 601 56 598 $procmux$849 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
603 const 9 101
604 ite 9 468 353 603 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:164$104 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:164.7-164.61
605 eq 1 10 604 $procmux$852_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
606 ite 7 605 126 602 $procmux$851 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
607 const 9 100
608 ite 9 471 356 607 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:163$103 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:163.7-163.61
609 eq 1 10 608 $procmux$854_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
610 ite 7 609 254 606 $procmux$853 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
611 const 9 011
612 ite 9 474 359 611 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:162$102 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:162.7-162.61
613 eq 1 10 612 $procmux$856_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
614 ite 7 613 134 610 $procmux$855 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
615 const 9 010
616 ite 9 477 362 615 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:161$101 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:161.7-161.61
617 eq 1 10 616 $procmux$858_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
618 ite 7 617 37 614 $procmux$857 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
619 slice 7 54 15 8
620 const 9 001
621 ite 9 480 365 620 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:160$100 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:160.7-160.61
622 eq 1 10 621 $procmux$860_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
623 ite 7 622 619 618 $procmux$859 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
624 slice 7 54 7 0
625 ite 9 483 368 242 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:159$99 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:159.7-159.61
626 eq 1 10 625 $procmux$862_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
627 ite 7 626 624 623 $procmux$861 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:158.5-167.12
628 next 7 25 627 $procdff$905 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:157.3-168.6
629 ite 9 450 335 615 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:182$119 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:182.5-182.61
630 eq 1 10 629 $procmux$818_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
631 ite 7 630 8 37 $procmux$817 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
632 ite 9 453 338 620 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:181$118 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:181.5-181.61
633 eq 1 10 632 $procmux$820_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
634 ite 7 633 37 631 $procmux$819 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
635 ite 9 456 341 242 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:180$117 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:180.5-180.61
636 eq 1 10 635 $procmux$822_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
637 ite 7 636 37 634 $procmux$821 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
638 ite 7 217 637 37 $procmux$823 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.15-179.22|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.12-185.10
639 const 7 00000000
640 ite 7 441 326 639 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:177$115 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:177.15-177.69
641 ite 7 12 640 638 $procmux$826 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.15-175.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.12-185.10
642 ite 7 432 317 639 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:173$112 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:173.15-173.69
643 not 1 34 $logic_not$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171$110 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.33-171.39
644 ite 7 643 642 641 $procmux$829 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.33-171.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.30-185.10
645 next 7 37 644 $procdff$903 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.3-185.10
646 eq 1 10 635 $procmux$807_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
647 ite 7 646 8 624 $procmux$806 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
648 ite 7 217 647 624 $procmux$808 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.15-179.22|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.12-185.10
649 const 53 1111111111111111
650 ite 53 444 329 649 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:176$114 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:176.16-176.74
651 slice 7 650 7 0
652 ite 7 12 651 648 $procmux$811 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.15-175.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.12-185.10
653 ite 53 435 320 649 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:172$111 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:172.16-172.74
654 slice 7 653 7 0
655 ite 7 643 654 652 $procmux$814 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.33-171.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.30-185.10
656 eq 1 10 632 $procmux$792_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
657 ite 7 656 8 619 $procmux$791 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
658 eq 1 10 635 $procmux$794_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
659 ite 7 658 619 657 $procmux$793 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
660 ite 7 217 659 619 $procmux$795 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.15-179.22|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.12-185.10
661 slice 7 650 15 8
662 ite 7 12 661 660 $procmux$798 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.15-175.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.12-185.10
663 slice 7 653 15 8
664 ite 7 643 663 662 $procmux$801 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.33-171.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.30-185.10
665 concat 53 664 655
666 next 53 54 665 $procdff$902 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.3-185.10
667 ite 1 420 305 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:195$131 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:195.17-195.71
668 slice 1 56 0 0
669 slice 1 8 0 0
670 ite 9 417 302 607 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191$125 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.32-191.88
671 eq 1 10 670 $eq$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191$126 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.19-191.89
672 and 1 51 671 $and$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191$127 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.8-191.90
673 ite 1 672 669 668 $procmux$779 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.8-191.90|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.5-191.110
674 ite 1 217 673 667 $procmux$781 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.11-190.18|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.8-196.6
675 ite 7 414 299 639 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189$124 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.30-189.84
676 slice 1 675 0 0
677 ite 1 12 676 674 $procmux$784 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.11-189.19|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.8-196.6
678 ite 7 411 296 639 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188$123 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.50-188.104
679 slice 1 678 0 0
680 not 1 34 $logic_not$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188$122 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.33-188.39
681 ite 1 680 679 677 $procmux$787 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.33-188.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.30-196.6
682 const 184 00
683 ite 184 423 308 682 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:194$130 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:194.19-194.73
684 slice 184 56 2 1
685 slice 184 8 2 1
686 ite 184 672 685 684 $procmux$768 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.8-191.90|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.5-191.110
687 ite 184 217 686 683 $procmux$770 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.11-190.18|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.8-196.6
688 slice 184 675 2 1
689 ite 184 12 688 687 $procmux$773 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.11-189.19|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.8-196.6
690 slice 184 678 2 1
691 ite 184 680 690 689 $procmux$776 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.33-188.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.30-196.6
692 slice 1 56 3 3
693 slice 1 8 3 3
694 ite 1 672 693 692 $procmux$757 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.8-191.90|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.5-191.110
695 ite 1 217 694 692 $procmux$759 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.11-190.18|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.8-196.6
696 slice 1 675 3 3
697 ite 1 12 696 695 $procmux$762 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.11-189.19|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.8-196.6
698 slice 1 678 3 3
699 ite 1 680 698 697 $procmux$765 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.33-188.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.30-196.6
700 slice 142 56 7 4
701 const 142 0000
702 ite 142 426 311 701 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:193$129 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:193.37-193.91
703 or 1 128 132 $or$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:193$128 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:193.8-193.21
704 ite 142 703 702 700 $procmux$743 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:193.8-193.21|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:193.5-193.92
705 slice 142 8 7 4
706 ite 142 672 705 700 $procmux$746 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.8-191.90|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:191.5-191.110
707 ite 142 217 706 704 $procmux$748 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.11-190.18|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:190.8-196.6
708 slice 142 675 7 4
709 ite 142 12 708 707 $procmux$751 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.11-189.19|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:189.8-196.6
710 slice 142 678 7 4
711 ite 142 680 710 709 $procmux$754 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.33-188.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.30-196.6
712 concat 9 691 681
713 concat 142 699 712
714 concat 7 711 713
715 next 7 56 714 $procdff$901 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:188.3-196.6
716 ite 9 447 332 611 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:183$120 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:183.5-183.61
717 eq 1 10 716 $procmux$832_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
718 ite 7 717 8 126 $procmux$831 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
719 eq 1 10 629 $procmux$834_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
720 ite 7 719 126 718 $procmux$833 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
721 eq 1 10 632 $procmux$836_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
722 ite 7 721 126 720 $procmux$835 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
723 eq 1 10 635 $procmux$838_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
724 ite 7 723 126 722 $procmux$837 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:0.0-0.0|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.24-185.10
725 ite 7 217 724 126 $procmux$839 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.15-179.22|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:179.12-185.10
726 ite 7 438 323 639 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:178$116 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:178.15-178.69
727 ite 7 12 726 725 $procmux$842 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.15-175.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:175.12-185.10
728 ite 7 429 314 639 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:174$113 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:174.15-174.69
729 ite 7 643 728 727 $procmux$845 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.33-171.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.30-185.10
730 next 7 126 729 $procdff$904 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:171.3-185.10
731 ite 1 145 499 16 $flatten\byte_controller.$procmux$512 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:333.12-340.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:333.16-333.24
732 const 160 10000
733 eq 1 161 732 $flatten\byte_controller.$procmux$515_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
734 ite 1 733 731 16
735 ite 1 82 16 499 $flatten\byte_controller.$procmux$518 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:310.17-322.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:310.21-310.25
736 ite 1 145 735 16 $flatten\byte_controller.$procmux$520 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.12-330.37|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.16-308.24
737 const 160 01000
738 eq 1 161 737 $flatten\byte_controller.$procmux$522_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
739 ite 1 738 736 734 $flatten\byte_controller.$procmux$514 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
740 or 1 12 132 $flatten\byte_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212$186 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
741 ite 1 740 16 739 $flatten\byte_controller.$procmux$524 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.9-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
742 not 1 34 $flatten\byte_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202$185 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
743 ite 1 742 16 741 $flatten\byte_controller.$procmux$527 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.4-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
744 next 1 128 743 $flatten\byte_controller.$procdff$887 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:201.2-343.7
745 ite 1 145 147 129 $flatten\byte_controller.$procmux$681 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.12-330.37|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.16-308.24
746 eq 1 161 737 $flatten\byte_controller.$procmux$684_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
747 ite 1 746 745 129 $flatten\byte_controller.$procmux$683 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
748 ite 1 740 16 747 $flatten\byte_controller.$procmux$686 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.9-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
749 ite 1 742 16 748 $flatten\byte_controller.$procmux$689 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.4-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
750 next 1 129 749 $flatten\byte_controller.$procdff$888 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:201.2-343.7
751 or 1 164 130 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:332$245 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:332.37-332.57|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
752 not 1 163 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:332$246 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:332.61-332.75|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
753 and 1 751 752 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:332$247 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:332.36-332.75|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
754 ite 1 12 16 753 $flatten\byte_controller.\bit_controller.$procmux$413 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:331.16-331.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:331.12-332.76|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
755 not 1 34 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:330$244 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:330.16-330.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
756 ite 1 755 16 754 $flatten\byte_controller.\bit_controller.$procmux$416 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:330.16-330.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:330.7-332.76|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
757 next 1 130 756 $flatten\byte_controller.\bit_controller.$procdff$871 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:329.5-332.76|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
758 not 1 181 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$253 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.31-354.36|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
759 and 1 178 758 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$254 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.21-354.36|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
760 and 1 759 14 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$255 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.21-354.46|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
761 redor 1 172 $flatten\byte_controller.\bit_controller.$reduce_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$256 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.51-354.59|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
762 and 1 761 163 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$257 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.51-354.75|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
763 not 1 162 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$258 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.78-354.87|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
764 and 1 762 763 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$259 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.51-354.87|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
765 or 1 760 764 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354$260 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:354.20-354.88|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
766 ite 1 12 16 765 $flatten\byte_controller.\bit_controller.$procmux$399 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:351.16-351.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:351.12-354.89|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
767 not 1 34 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:349$252 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:349.11-349.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
768 ite 1 767 16 766 $flatten\byte_controller.\bit_controller.$procmux$402 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:349.11-349.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:349.7-354.89|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
769 next 1 132 768 $flatten\byte_controller.\bit_controller.$procdff$869 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:348.5-354.89|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
770 slice 252 134 6 0
771 concat 7 770 147
772 ite 7 149 771 134 $flatten\byte_controller.$procmux$702 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:180.9-181.35|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:180.13-180.18
773 ite 7 150 126 772 $flatten\byte_controller.$procmux$705 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:178.9-181.35|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:178.13-178.15
774 ite 7 12 639 773 $flatten\byte_controller.$procmux$708 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:176.9-181.35|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:176.13-176.16
775 not 1 34 $flatten\byte_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:174$178 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:174.8-174.15
776 ite 7 775 639 774 $flatten\byte_controller.$procmux$711 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:174.4-181.35|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:174.8-174.15
777 next 7 134 776 $flatten\byte_controller.$procdff$895 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:173.2-181.35
778 ite 142 145 701 143 $flatten\byte_controller.$procmux$631 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:333.12-340.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:333.16-333.24
779 eq 1 161 732 $flatten\byte_controller.$procmux$634_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
780 ite 142 779 778 143
781 const 142 0010
782 ite 142 82 781 701 $flatten\byte_controller.$procmux$637 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:310.17-322.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:310.21-310.25
783 ite 142 145 782 143 $flatten\byte_controller.$procmux$639 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.12-330.37|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.16-308.24
784 eq 1 161 737 $flatten\byte_controller.$procmux$641_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
785 ite 142 784 783 780
786 const 142 1000
787 const 142 0100
788 ite 142 158 787 786 $flatten\byte_controller.$procmux$643 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:292.18-301.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:292.22-292.30
789 ite 142 145 788 143 $flatten\byte_controller.$procmux$645 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.12-305.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.16-290.24
790 const 160 00010
791 eq 1 161 790 $flatten\byte_controller.$procmux$647_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
792 ite 142 791 789 785
793 ite 142 158 786 787 $flatten\byte_controller.$procmux$649 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:277.14-287.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:277.18-277.26
794 ite 142 145 793 143 $flatten\byte_controller.$procmux$651 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:276.12-287.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:276.16-276.24
795 const 160 00100
796 eq 1 161 795 $flatten\byte_controller.$procmux$653_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
797 ite 142 796 794 792
798 ite 142 96 786 787 $flatten\byte_controller.$procmux$655 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:261.18-270.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:261.22-261.26
799 ite 142 145 798 143 $flatten\byte_controller.$procmux$657 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:259.12-273.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:259.16-259.24
800 const 160 00001
801 eq 1 161 800 $flatten\byte_controller.$procmux$659_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
802 ite 142 801 799 797
803 ite 142 110 787 781 $flatten\byte_controller.$procmux$661 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:244.23-253.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:244.27-244.32
804 ite 142 96 786 803 $flatten\byte_controller.$procmux$664 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:239.23-253.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:239.27-239.31
805 const 142 0001
806 ite 142 68 805 804 $flatten\byte_controller.$procmux$667 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:234.18-253.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:234.22-234.27
807 ite 142 154 806 143 $flatten\byte_controller.$procmux$669 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:232.12-256.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:232.16-232.18
808 const 160 00000
809 eq 1 161 808 $flatten\byte_controller.$procmux$671_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
810 ite 142 809 807 802 $flatten\byte_controller.$procmux$633 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
811 ite 142 740 701 810 $flatten\byte_controller.$procmux$673 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.9-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
812 ite 142 742 701 811 $flatten\byte_controller.$procmux$676 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.4-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
813 next 142 143 812 $flatten\byte_controller.$procdff$889 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:201.2-343.7
814 slice 1 134 7 7
815 ite 1 145 499 124 $flatten\byte_controller.$procmux$569 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.12-330.37|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.16-308.24
816 eq 1 161 737 $flatten\byte_controller.$procmux$572_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
817 ite 1 816 815 814
818 ite 1 145 124 814 $flatten\byte_controller.$procmux$573 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.12-305.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.16-290.24
819 eq 1 161 790 $flatten\byte_controller.$procmux$575_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
820 ite 1 819 818 817 $flatten\byte_controller.$procmux$571 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
821 ite 1 740 16 820 $flatten\byte_controller.$procmux$577 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.9-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
822 ite 1 742 16 821 $flatten\byte_controller.$procmux$580 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.4-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
823 next 1 144 822 $flatten\byte_controller.$procdff$890 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:201.2-343.7
824 eq 1 172 487 $flatten\byte_controller.\bit_controller.$procmux$269_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
825 ite 1 824 499 16
826 eq 1 172 500 $flatten\byte_controller.\bit_controller.$procmux$270_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
827 ite 1 826 499 825
828 eq 1 172 512 $flatten\byte_controller.\bit_controller.$procmux$271_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
829 ite 1 828 499 827
830 eq 1 172 524 $flatten\byte_controller.\bit_controller.$procmux$272_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
831 ite 1 830 499 829 $flatten\byte_controller.\bit_controller.$procmux$268 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
832 ite 1 177 831 16 $flatten\byte_controller.\bit_controller.$procmux$273 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.15-405.21|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.11-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
833 ite 1 540 16 832 $flatten\byte_controller.\bit_controller.$procmux$276 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.16-393.24|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.12-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
834 ite 1 542 16 833 $flatten\byte_controller.\bit_controller.$procmux$279 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.11-385.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.7-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
835 next 1 145 834 $flatten\byte_controller.\bit_controller.$procdff$863 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:384.5-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
836 not 1 165 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:359$262 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:359.18-359.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
837 and 1 166 836 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:359$263 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:359.11-359.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
838 ite 1 837 181 147 $flatten\byte_controller.\bit_controller.$procmux$396 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:359.11-359.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:359.7-359.41|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
839 next 1 147 838 $flatten\byte_controller.\bit_controller.$procdff$868 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:358.5-359.41|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
840 ite 1 145 499 16 $flatten\byte_controller.$procmux$550 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.12-305.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.16-290.24
841 eq 1 161 790 $flatten\byte_controller.$procmux$553_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
842 ite 1 841 840 16
843 ite 1 158 16 499 $flatten\byte_controller.$procmux$555 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:277.14-287.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:277.18-277.26
844 ite 1 145 843 16 $flatten\byte_controller.$procmux$557 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:276.12-287.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:276.16-276.24
845 eq 1 161 795 $flatten\byte_controller.$procmux$559_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
846 ite 1 845 844 842 $flatten\byte_controller.$procmux$552 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
847 ite 1 740 16 846 $flatten\byte_controller.$procmux$561 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.9-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
848 ite 1 742 16 847 $flatten\byte_controller.$procmux$564 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.4-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
849 next 1 149 848 $flatten\byte_controller.$procdff$891 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:201.2-343.7
850 ite 1 145 499 16 $flatten\byte_controller.$procmux$534 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:259.12-273.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:259.16-259.24
851 eq 1 161 800 $flatten\byte_controller.$procmux$537_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
852 ite 1 851 850 16
853 ite 1 154 499 16 $flatten\byte_controller.$procmux$538 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:232.12-256.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:232.16-232.18
854 eq 1 161 808 $flatten\byte_controller.$procmux$540_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
855 ite 1 854 853 852 $flatten\byte_controller.$procmux$536 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
856 ite 1 740 16 855 $flatten\byte_controller.$procmux$542 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.9-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
857 ite 1 742 16 856 $flatten\byte_controller.$procmux$545 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.4-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
858 next 1 150 857 $flatten\byte_controller.$procdff$892 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:201.2-343.7
859 sub 9 156 620 $flatten\byte_controller.$sub$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:192$181 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:192.17-192.28
860 ite 9 149 859 156 $flatten\byte_controller.$procmux$691 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:191.9-192.29|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:191.13-191.18
861 ite 9 150 595 860 $flatten\byte_controller.$procmux$694 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:189.9-192.29|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:189.13-189.15
862 ite 9 12 242 861 $flatten\byte_controller.$procmux$697 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:187.9-192.29|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:187.13-187.16
863 not 1 34 $flatten\byte_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:185$180 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:185.8-185.15
864 ite 9 863 242 862 $flatten\byte_controller.$procmux$700 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:185.4-192.29|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:185.8-185.15
865 next 9 156 864 $flatten\byte_controller.$procdff$894 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:184.2-192.29
866 ite 160 145 808 161 $flatten\byte_controller.$procmux$583 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:333.12-340.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:333.16-333.24
867 eq 1 161 732 $flatten\byte_controller.$procmux$586_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
868 ite 160 867 866 161
869 ite 160 82 732 808 $flatten\byte_controller.$procmux$589 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:310.17-322.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:310.21-310.25
870 ite 160 145 869 161 $flatten\byte_controller.$procmux$591 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.12-330.37|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:308.16-308.24
871 eq 1 161 737 $flatten\byte_controller.$procmux$593_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
872 ite 160 871 870 868
873 ite 160 158 737 790 $flatten\byte_controller.$procmux$595 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:292.18-301.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:292.22-292.30
874 ite 160 145 873 161 $flatten\byte_controller.$procmux$597 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.12-305.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:290.16-290.24
875 eq 1 161 790 $flatten\byte_controller.$procmux$599_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
876 ite 160 875 874 872
877 ite 160 158 737 795 $flatten\byte_controller.$procmux$601 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:277.14-287.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:277.18-277.26
878 ite 160 145 877 161 $flatten\byte_controller.$procmux$603 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:276.12-287.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:276.16-276.24
879 eq 1 161 795 $flatten\byte_controller.$procmux$605_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
880 ite 160 879 878 876
881 ite 160 96 790 795 $flatten\byte_controller.$procmux$607 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:261.18-270.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:261.22-261.26
882 ite 160 145 881 161 $flatten\byte_controller.$procmux$609 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:259.12-273.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:259.16-259.24
883 eq 1 161 800 $flatten\byte_controller.$procmux$611_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
884 ite 160 883 882 880
885 ite 160 110 795 732 $flatten\byte_controller.$procmux$613 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:244.23-253.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:244.27-244.32
886 ite 160 96 790 885 $flatten\byte_controller.$procmux$616 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:239.23-253.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:239.27-239.31
887 ite 160 68 800 886 $flatten\byte_controller.$procmux$619 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:234.18-253.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:234.22-234.27
888 ite 160 154 887 161 $flatten\byte_controller.$procmux$621 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:232.12-256.17|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:232.16-232.18
889 eq 1 161 808 $flatten\byte_controller.$procmux$623_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
890 ite 160 889 888 884 $flatten\byte_controller.$procmux$585 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:230.8-342.15|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:0.0-0.0
891 ite 160 740 808 890 $flatten\byte_controller.$procmux$625 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.9-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:212.13-212.25
892 ite 160 742 808 891 $flatten\byte_controller.$procmux$628 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.4-343.7|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:202.8-202.15
893 next 160 161 892 $flatten\byte_controller.$procdff$893 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:201.2-343.7
894 eq 1 143 781 $flatten\byte_controller.\bit_controller.$eq$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:346$250 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:346.26-346.40|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
895 ite 1 177 894 162 $flatten\byte_controller.\bit_controller.$procmux$404 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:345.16-345.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:345.12-346.41|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
896 ite 1 12 16 895 $flatten\byte_controller.\bit_controller.$procmux$407 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:343.16-343.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:343.12-346.41|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
897 not 1 34 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:341$249 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:341.11-341.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
898 ite 1 897 16 896 $flatten\byte_controller.\bit_controller.$procmux$410 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:341.11-341.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:341.7-346.41|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
899 next 1 162 898 $flatten\byte_controller.\bit_controller.$procdff$870 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:340.5-346.41|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
900 not 1 180 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:324$240 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:324.39-324.44|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
901 and 1 181 900 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:324$241 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:324.32-324.44|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
902 and 1 901 166 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:324$242 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:324.32-324.51|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
903 ite 1 12 16 902 $flatten\byte_controller.\bit_controller.$procmux$419 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:316.16-316.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:316.12-325.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
904 not 1 34 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:311$236 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:311.11-311.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
905 ite 1 904 16 903 $flatten\byte_controller.\bit_controller.$procmux$422 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:311.11-311.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:311.7-325.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
906 next 1 163 905 $flatten\byte_controller.\bit_controller.$procdff$873 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:310.5-325.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
907 not 1 181 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:323$237 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:323.31-323.36|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
908 and 1 907 180 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:323$238 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:323.31-323.44|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
909 and 1 908 166 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:323$239 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:323.31-323.51|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
910 ite 1 12 16 909 $flatten\byte_controller.\bit_controller.$procmux$425 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:316.16-316.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:316.12-325.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
911 ite 1 904 16 910 $flatten\byte_controller.\bit_controller.$procmux$428 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:311.11-311.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:311.7-325.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
912 next 1 164 911 $flatten\byte_controller.\bit_controller.$procdff$872 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:310.5-325.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
913 ite 1 12 499 166 $flatten\byte_controller.\bit_controller.$procmux$437 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.16-289.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.12-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
914 not 1 34 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281$224 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.11-281.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
915 ite 1 914 499 913 $flatten\byte_controller.\bit_controller.$procmux$440 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.11-281.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.7-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
916 next 1 165 915 $flatten\byte_controller.\bit_controller.$procdff$876 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:280.5-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
917 slice 184 183 2 1
918 redand 1 917 $flatten\byte_controller.\bit_controller.$reduce_and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299$225 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299.22-299.32|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
919 slice 184 183 1 0
920 redand 1 919 $flatten\byte_controller.\bit_controller.$reduce_and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299$226 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299.35-299.45|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
921 or 1 918 920 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299$227 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299.22-299.45|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
922 slice 1 183 2 2
923 slice 1 183 0 0
924 and 1 922 923 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299$228 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299.49-299.66|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
925 or 1 921 924 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299$229 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:299.22-299.67|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
926 ite 1 12 499 925 $flatten\byte_controller.\bit_controller.$procmux$449 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.16-289.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.12-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
927 ite 1 914 499 926 $flatten\byte_controller.\bit_controller.$procmux$452 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.11-281.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.7-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
928 next 1 166 927 $flatten\byte_controller.\bit_controller.$procdff$874 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:280.5-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
929 const 171 000000000000000000
930 eq 1 172 487 $flatten\byte_controller.\bit_controller.$procmux$311_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
931 ite 171 930 929 172
932 eq 1 172 490 $flatten\byte_controller.\bit_controller.$procmux$312_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
933 ite 171 932 487 931
934 eq 1 172 493 $flatten\byte_controller.\bit_controller.$procmux$313_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
935 ite 171 934 490 933
936 eq 1 172 496 $flatten\byte_controller.\bit_controller.$procmux$314_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
937 ite 171 936 493 935
938 eq 1 172 500 $flatten\byte_controller.\bit_controller.$procmux$315_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
939 ite 171 938 929 937
940 eq 1 172 503 $flatten\byte_controller.\bit_controller.$procmux$316_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
941 ite 171 940 500 939
942 eq 1 172 506 $flatten\byte_controller.\bit_controller.$procmux$317_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
943 ite 171 942 503 941
944 eq 1 172 509 $flatten\byte_controller.\bit_controller.$procmux$318_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
945 ite 171 944 506 943
946 eq 1 172 512 $flatten\byte_controller.\bit_controller.$procmux$319_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
947 ite 171 946 929 945
948 eq 1 172 515 $flatten\byte_controller.\bit_controller.$procmux$320_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
949 ite 171 948 512 947
950 eq 1 172 518 $flatten\byte_controller.\bit_controller.$procmux$321_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
951 ite 171 950 515 949
952 eq 1 172 521 $flatten\byte_controller.\bit_controller.$procmux$322_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
953 ite 171 952 518 951
954 eq 1 172 524 $flatten\byte_controller.\bit_controller.$procmux$323_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
955 ite 171 954 929 953
956 eq 1 172 527 $flatten\byte_controller.\bit_controller.$procmux$324_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
957 ite 171 956 524 955
958 eq 1 172 530 $flatten\byte_controller.\bit_controller.$procmux$325_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
959 ite 171 958 527 957
960 eq 1 172 533 $flatten\byte_controller.\bit_controller.$procmux$326_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
961 ite 171 960 530 959
962 eq 1 172 536 $flatten\byte_controller.\bit_controller.$procmux$327_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
963 ite 171 962 533 961
964 eq 1 143 786 $flatten\byte_controller.\bit_controller.$procmux$330_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:410.25-416.32|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
965 ite 171 964 509 929
966 eq 1 143 787 $flatten\byte_controller.\bit_controller.$procmux$331_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:410.25-416.32|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
967 ite 171 966 496 965
968 eq 1 143 781 $flatten\byte_controller.\bit_controller.$procmux$332_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:410.25-416.32|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
969 ite 171 968 521 967
970 eq 1 143 805 $flatten\byte_controller.\bit_controller.$procmux$333_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:410.25-416.32|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
971 ite 171 970 536 969 $flatten\byte_controller.\bit_controller.$procmux$329 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:410.25-416.32|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
972 eq 1 172 929 $flatten\byte_controller.\bit_controller.$procmux$334_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
973 ite 171 972 971 963 $flatten\byte_controller.\bit_controller.$procmux$310 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
974 ite 171 177 973 172 $flatten\byte_controller.\bit_controller.$procmux$335 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.15-405.21|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.11-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
975 ite 171 540 929 974 $flatten\byte_controller.\bit_controller.$procmux$338 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.16-393.24|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.12-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
976 ite 171 542 929 975 $flatten\byte_controller.\bit_controller.$procmux$341 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.11-385.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.7-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
977 next 171 172 976 $flatten\byte_controller.\bit_controller.$procdff$866 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:384.5-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
978 uext 36 174 18
979 const 36 00000000000000000000000000000001
980 sub 36 978 979 $flatten\byte_controller.\bit_controller.$sub$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:258$218 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:258.44-258.57|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
981 slice 173 980 13 0
982 uext 36 54 16
983 const 36 00000000000000000000000000000010
984 srl 36 982 983 $flatten\byte_controller.\bit_controller.$shr$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257$217 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257.44-257.56|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
985 slice 53 984 15 0
986 slice 173 985 13 0
987 redor 1 174 $flatten\byte_controller.\bit_controller.$reduce_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257$215 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257.16-257.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
988 not 1 987 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257$216 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257.16-257.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
989 ite 173 988 986 981 $flatten\byte_controller.\bit_controller.$procmux$471 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257.16-257.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:257.12-258.58|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
990 const 173 00000000000000
991 not 1 51 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:256$213 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:256.23-256.27|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
992 or 1 12 991 $flatten\byte_controller.\bit_controller.$logic_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:256$214 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:256.16-256.27|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
993 ite 173 992 990 989 $flatten\byte_controller.\bit_controller.$procmux$474 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:256.16-256.27|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:256.12-258.58|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
994 not 1 34 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:255$212 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:255.16-255.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
995 ite 173 994 990 993 $flatten\byte_controller.\bit_controller.$procmux$477 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:255.16-255.23|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:255.7-258.58|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
996 next 173 174 995 $flatten\byte_controller.\bit_controller.$procdff$880 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:254.5-258.58|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
997 const 53 0000000000000001
998 sub 53 175 997 $flatten\byte_controller.\bit_controller.$sub$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:226$208 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:226.24-226.35|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
999 ite 53 176 175 998 $flatten\byte_controller.\bit_controller.$procmux$500 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:219.16-219.26|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:219.12-228.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1000 redor 1 175 $flatten\byte_controller.\bit_controller.$reduce_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214$202 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.23-214.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1001 not 1 1000 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214$203 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.23-214.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1002 or 1 12 1001 $flatten\byte_controller.\bit_controller.$logic_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214$204 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.16-214.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1003 not 1 51 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214$205 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.32-214.36|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1004 or 1 1002 1003 $flatten\byte_controller.\bit_controller.$logic_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214$206 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.16-214.36|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1005 or 1 1004 169 $flatten\byte_controller.\bit_controller.$logic_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214$207 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.16-214.48|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1006 ite 53 1005 54 999 $flatten\byte_controller.\bit_controller.$procmux$503 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.16-214.48|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.12-228.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1007 const 53 0000000000000000
1008 not 1 34 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:209$201 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:209.11-209.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1009 ite 53 1008 1007 1006 $flatten\byte_controller.\bit_controller.$procmux$506 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:209.11-209.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:209.7-228.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1010 next 53 175 1009 $flatten\byte_controller.\bit_controller.$procdff$884 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:208.5-228.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1011 not 1 179 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200$190 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200.45-200.54|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1012 and 1 18 1011 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200$191 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200.35-200.54|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1013 not 1 166 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200$192 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200.57-200.62|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1014 and 1 1012 1013 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200$193 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200.35-200.62|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1015 not 1 166 $flatten\byte_controller.\bit_controller.$not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200$194 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200.80-200.85|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1016 and 1 176 1015 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200$195 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200.67-200.85|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1017 or 1 1014 1016 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200$196 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:200.34-200.86|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1018 not 1 34 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:199$189 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:199.11-199.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1019 ite 1 1018 16 1017 $flatten\byte_controller.\bit_controller.$procmux$509 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:199.11-199.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:199.7-200.87|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1020 next 1 176 1019 $flatten\byte_controller.\bit_controller.$procdff$885 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:198.5-200.87|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1021 ite 1 1005 499 16 $flatten\byte_controller.\bit_controller.$procmux$494 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.16-214.48|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:214.12-228.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1022 ite 1 1008 499 1021 $flatten\byte_controller.\bit_controller.$procmux$497 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:209.11-209.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:209.7-228.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1023 next 1 177 1022 $flatten\byte_controller.\bit_controller.$procdff$883 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:208.5-228.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1024 eq 1 172 487 $flatten\byte_controller.\bit_controller.$procmux$283_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1025 ite 1 1024 16 178
1026 eq 1 172 490 $flatten\byte_controller.\bit_controller.$procmux$284_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1027 ite 1 1026 499 1025
1028 eq 1 172 493 $flatten\byte_controller.\bit_controller.$procmux$285_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1029 ite 1 1028 16 1027
1030 eq 1 172 496 $flatten\byte_controller.\bit_controller.$procmux$286_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1031 ite 1 1030 16 1029
1032 eq 1 172 500 $flatten\byte_controller.\bit_controller.$procmux$287_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1033 ite 1 1032 16 1031
1034 eq 1 172 503 $flatten\byte_controller.\bit_controller.$procmux$288_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1035 ite 1 1034 16 1033
1036 eq 1 172 506 $flatten\byte_controller.\bit_controller.$procmux$289_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1037 ite 1 1036 16 1035
1038 eq 1 172 509 $flatten\byte_controller.\bit_controller.$procmux$290_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1039 ite 1 1038 16 1037
1040 eq 1 172 512 $flatten\byte_controller.\bit_controller.$procmux$291_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1041 ite 1 1040 16 1039
1042 eq 1 172 515 $flatten\byte_controller.\bit_controller.$procmux$292_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1043 ite 1 1042 16 1041
1044 eq 1 172 518 $flatten\byte_controller.\bit_controller.$procmux$293_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1045 ite 1 1044 16 1043
1046 eq 1 172 521 $flatten\byte_controller.\bit_controller.$procmux$294_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1047 ite 1 1046 16 1045
1048 eq 1 172 524 $flatten\byte_controller.\bit_controller.$procmux$295_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1049 ite 1 1048 16 1047
1050 eq 1 172 527 $flatten\byte_controller.\bit_controller.$procmux$296_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1051 ite 1 1050 16 1049
1052 eq 1 172 530 $flatten\byte_controller.\bit_controller.$procmux$297_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1053 ite 1 1052 16 1051
1054 eq 1 172 533 $flatten\byte_controller.\bit_controller.$procmux$298_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1055 ite 1 1054 16 1053
1056 eq 1 172 536 $flatten\byte_controller.\bit_controller.$procmux$299_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1057 ite 1 1056 16 1055
1058 eq 1 172 929 $flatten\byte_controller.\bit_controller.$procmux$300_CMP0 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1059 ite 1 1058 16 1057 $flatten\byte_controller.\bit_controller.$procmux$282 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:0.0-0.0|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:406.15-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1060 ite 1 177 1059 178 $flatten\byte_controller.\bit_controller.$procmux$301 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.15-405.21|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:405.11-568.22|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1061 ite 1 540 16 1060 $flatten\byte_controller.\bit_controller.$procmux$304 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.16-393.24|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:393.12-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1062 ite 1 542 16 1061 $flatten\byte_controller.\bit_controller.$procmux$307 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.11-385.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:385.7-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1063 next 1 178 1062 $flatten\byte_controller.\bit_controller.$procdff$867 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:384.5-569.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1064 next 1 179 18 $flatten\byte_controller.\bit_controller.$procdff$886 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:193.5-194.30|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1065 ite 1 12 499 181 $flatten\byte_controller.\bit_controller.$procmux$431 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.16-289.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.12-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1066 ite 1 914 499 1065 $flatten\byte_controller.\bit_controller.$procmux$434 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.11-281.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.7-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1067 next 1 180 1066 $flatten\byte_controller.\bit_controller.$procdff$877 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:280.5-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1068 slice 184 182 2 1
1069 redand 1 1068 $flatten\byte_controller.\bit_controller.$reduce_and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300$230 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300.22-300.32|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1070 slice 184 182 1 0
1071 redand 1 1070 $flatten\byte_controller.\bit_controller.$reduce_and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300$231 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300.35-300.45|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1072 or 1 1069 1071 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300$232 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300.22-300.45|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1073 slice 1 182 2 2
1074 slice 1 182 0 0
1075 and 1 1073 1074 $flatten\byte_controller.\bit_controller.$and$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300$233 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300.49-300.66|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1076 or 1 1072 1075 $flatten\byte_controller.\bit_controller.$or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300$234 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:300.22-300.67|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1077 ite 1 12 499 1076 $flatten\byte_controller.\bit_controller.$procmux$443 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.16-289.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:289.12-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1078 ite 1 914 499 1077 $flatten\byte_controller.\bit_controller.$procmux$446 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.11-281.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:281.7-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1079 next 1 181 1078 $flatten\byte_controller.\bit_controller.$procdff$875 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:280.5-304.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1080 slice 1 185 1 1
1081 slice 184 182 1 0
1082 concat 9 1081 1080
1083 redor 1 174 $flatten\byte_controller.\bit_controller.$reduce_or$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272$221 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272.16-272.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1084 not 1 1083 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272$222 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272.16-272.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1085 ite 9 1084 1082 182 $flatten\byte_controller.\bit_controller.$procmux$454 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272.16-272.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272.12-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1086 ite 9 12 595 1085 $flatten\byte_controller.\bit_controller.$procmux$457 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:267.16-267.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:267.12-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1087 not 1 34 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:262$220 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:262.11-262.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1088 ite 9 1087 595 1086 $flatten\byte_controller.\bit_controller.$procmux$460 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:262.11-262.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:262.7-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1089 next 9 182 1088 $flatten\byte_controller.\bit_controller.$procdff$879 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:261.5-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1090 slice 1 186 1 1
1091 slice 184 183 1 0
1092 concat 9 1091 1090
1093 ite 9 1084 1092 183 $flatten\byte_controller.\bit_controller.$procmux$462 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272.16-272.28|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:272.12-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1094 ite 9 12 595 1093 $flatten\byte_controller.\bit_controller.$procmux$465 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:267.16-267.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:267.12-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1095 ite 9 1087 595 1094 $flatten\byte_controller.\bit_controller.$procmux$468 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:262.11-262.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:262.7-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1096 next 9 183 1095 $flatten\byte_controller.\bit_controller.$procdff$878 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:261.5-276.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1097 slice 1 185 0 0
1098 concat 184 1097 2
1099 ite 184 12 682 1098 $flatten\byte_controller.\bit_controller.$procmux$480 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:241.16-241.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:241.12-250.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1100 not 1 34 $flatten\byte_controller.\bit_controller.$logic_not$/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:236$210 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:236.11-236.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1101 ite 184 1100 682 1099 $flatten\byte_controller.\bit_controller.$procmux$483 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:236.11-236.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:236.7-250.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1102 next 184 185 1101 $flatten\byte_controller.\bit_controller.$procdff$882 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:235.5-250.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1103 slice 1 186 0 0
1104 concat 184 1103 3
1105 ite 184 12 682 1104 $flatten\byte_controller.\bit_controller.$procmux$486 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:241.16-241.19|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:241.12-250.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1106 ite 184 1100 682 1105 $flatten\byte_controller.\bit_controller.$procmux$489 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:236.11-236.18|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:236.7-250.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1107 next 184 186 1106 $flatten\byte_controller.\bit_controller.$procdff$881 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:208.3-232.4|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_bit_ctrl.sync_reset.v:235.5-250.10|/home/kevin/d/rtl-repair/benchmarks/cirfix/opencores/i2c/i2c_master_byte_ctrl.sync_reset.v:146.22-164.3
1108 not 1 68 $not$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:246$159 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:246.28-246.32
1109 and 1 220 1108 $and$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:246$160 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:246.23-246.32
1110 or 1 132 1109 $or$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:246$161 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:246.14-246.32
1111 ite 1 400 285 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:241$155 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:241.14-241.68
1112 ite 1 12 1111 1110 $procmux$738 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.15-240.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.12-250.6
1113 ite 1 388 273 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:236$151 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:236.14-236.68
1114 not 1 34 $logic_not$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235$150 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.33-235.39
1115 ite 1 1114 1113 1112 $procmux$741 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.33-235.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.30-250.6
1116 next 1 220 1115 $procdff$900 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.3-250.6
1117 or 1 128 132 $or$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249$163 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249.21-249.34
1118 or 1 1117 223 $or$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249$164 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249.21-249.45
1119 not 1 210 $not$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249$165 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249.49-249.54
1120 and 1 1118 1119 $and$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249$166 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:249.20-249.54
1121 ite 1 391 276 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:244$158 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:244.20-244.74
1122 ite 1 12 1121 1120 $procmux$720 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.15-240.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.12-250.6
1123 ite 1 379 264 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:239$154 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:239.20-239.74
1124 ite 1 1114 1123 1122 $procmux$723 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.33-235.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.30-250.6
1125 next 1 223 1124 $procdff$899 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.3-250.6
1126 or 1 96 110 $or$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:248$162 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:248.15-248.22
1127 ite 1 394 279 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:243$157 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:243.15-243.69
1128 ite 1 12 1127 1126 $procmux$726 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.15-240.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.12-250.6
1129 ite 1 382 267 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:238$153 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:238.15-238.69
1130 ite 1 1114 1129 1128 $procmux$729 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.33-235.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.30-250.6
1131 next 1 224 1130 $procdff$898 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.3-250.6
1132 ite 1 397 282 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:242$156 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:242.17-242.71
1133 ite 1 12 1132 129 $procmux$732 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.15-240.23|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:240.12-250.6
1134 ite 1 385 270 16 $ternary$/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:237$152 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:237.17-237.71
1135 ite 1 1114 1134 1133 $procmux$735 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.33-235.39|/home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.30-250.6
1136 next 1 225 1135 $procdff$897 ; /home/kevin/d/rtl-repair/working-dir/i2c_master_original_fixed_x_prop_tb/1_replace_literals/i2c_master_top.sync_reset.instrumented.v:235.3-250.6
; end of yosys output