# Reference: /opt/homebrew/Cellar/open-ocd/0.11.0/share/openocd/scripts/board/
# Choose debugger and transport
source [find interface/cmsis-dap.cfg]
transport select swd
# stlink
# source [find interface/stlink.cfg]
#transport select hla_swd

# Set chip name
set CHIPNAME stm32h7b0xx

# Enable stmqspi
if {![info exists OCTOSPI1]} {
	set OCTOSPI1 1
	set OCTOSPI2 0
}

# Use built-in stm32h7 openocd configs
source [find target/stm32h7x.cfg]

# OCTOSPI initialization
proc octospi_init { octo } {
	global a b
	mmw 0x58024540 0x000006FF 0				;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
	mmw 0x58024534 0x00284000 0				;# RCC_AHB3ENR |= IOMNGREN, OSPI2EN, OSPI1EN (enable clocks)
	sleep 1									;# Wait for clock startup

	mww 0x5200B404 0x03010111				;# OCTOSPIM_P1CR: assign Port 1 to OCTOSPI1
	mww 0x5200B408 0x00000000				;# OCTOSPIM_P2CR: disable Port 2

	# AF mapping can be found in datasheet. For h7b0, see DS13196, page 54
	# PB02: OCSPI1_CLK, PB06: OCSPI1_NCS, PD11: OCSPI1_IO0, PD12: OCSPI1_IO1, PE2: OCSPI1_IO2, PD13: OCSPI1_IO3
	# Generate the GPIO config: perl resources/gpio_gen.pl -c "PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V"

	# mmw command: "memory modify word, modify only given bits"
	# usage: mmw "address setbits clearbits"

	# PB06:AF10:V, PB02:AF09:V, PD13:AF09:V, PD12:AF09:V, PD11:AF09:V, PE02:AF09:V
	# Port B: PB06:AF10:V, PB02:AF09:V
	mmw 0x58020400 0x00002020 0x00001010    ;# MODER
	mmw 0x58020408 0x00003030 0x00000000    ;# OSPEEDR
	mmw 0x5802040C 0x00000000 0x00003030    ;# PUPDR
	mmw 0x58020420 0x0A000900 0x05000600    ;# AFRL
	# Port D: PD13:AF09:V, PD12:AF09:V, PD11:AF09:V
	mmw 0x58020C00 0x0A800000 0x05400000    ;# MODER
	mmw 0x58020C08 0x0FC00000 0x00000000    ;# OSPEEDR
	mmw 0x58020C0C 0x00000000 0x0FC00000    ;# PUPDR
	mmw 0x58020C24 0x00999000 0x00666000    ;# AFRH
	# Port E: PE02:AF09:V
	mmw 0x58021000 0x00000020 0x00000010    ;# MODER
	mmw 0x58021008 0x00000030 0x00000000    ;# OSPEEDR
	mmw 0x5802100C 0x00000000 0x00000030    ;# PUPDR
	mmw 0x58021020 0x00000900 0x00000600    ;# AFRL

	# OCTOSPI1: Use 4-4-4 read and 0xeb read data command 
	mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=0x11, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
	mww 0x52005008 0x00160100				;# OCTOSPI_DCR1: MTYP=0x0, FSIZE=0x16=22=2^(22+1), CSHT=0x00, CKMODE=0, DLYBYP=0
	mww 0x5200500C 0x00000001				;# OCTOSPI_DCR2: WRAPSIZE=0x00, PRESCALER=0+1

	mww 0x52005108 0x00000008				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x8
	mww 0x52005100 0x03002303				;# OCTOSPI_CCR: SIOO=0, DMODE=011, ABMODE=0x0, ADSIZE=10, ADMODE=011, ISIZE=0x0, IMODE=011
	mww 0x52005110 0x000000EB				;# OCTOSPI_IR: INSTR=FastRead, 0xeb

	# OCTOSPI1: Use 1-1-1 read and 0x03 read data command
	# mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=01, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
	# mww 0x52005008 0x00160100				;# OCTOSPI_DCR1: MTYP=0x0, FSIZE=0x16=22=2^(22+1), CSHT=01, CKMODE=0, DLYBYP=0
	# mww 0x5200500C 0x00000001				;# OCTOSPI_DCR2: WRAPSIZE=0, PRESCALER=0+1

	# mww 0x52005100 0x01002101				;# OCTOSPI_CCR: SIOO=0, DMODE=001, ABSIZE=00, ABMODE=000, ADSIZE=10, ADMODE=001, ISIZE=0x0, IMODE=001
	# mww 0x52005108 0x00000000				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x0
	# mww 0x52005110 0x00000003				;# OCTOSPI_IR: INSTR=ReadData, 0x03
	# mww 0x52005130 0x00001000				;# OCTOSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full

	# mww 0x52005180 0x01002101				;# OCTOSPI_WCCR: SIOO=0, DMODE=011, ABSIZE=00, ABMODE=011, ADSIZE=10, ADMODE=011, ISIZE=0x0, IMODE=001
	# mww 0x52005188 0x00000000				;# OCTOSPI_WTCR: SSHIFT=0, DHQC=0, DCYC=0x0
	# mww 0x52005190 0x00000002				;# OCTOSPI_WIR: INSTR=PageProgram, 0x02
	# mww 0x520051a0 0x000000ff				;# OCTOSPI_WABR: alternate bytes register

	# OCTOSPI1: Use 1-4-4 read and 0xeb read data command -- 1-4-4 is NOT supported by openocd stmqspi
	# mww 0x52005000 0x3040000B				;# OCTOSPI_CR: FMODE=11, APMS=1, FTHRES=0, FSEL=0, DQM=0, TCEN=0
	# mww 0x52005008 0x00160100				;# OCTOSPI_DCR1: MTYP=0, FSIZE=0x16=22=2^(22+1), CSHT=0x01, CKMODE=0, DLYBYP=0
	# mww 0x5200500C 0x00000001				;# OCTOSPI_DCR2: WRAPSIZE=0x00, PRESCALER=0+1

	# mww 0x52005100 0x03032301				;# OCTOSPI_CCR: SIOO=0, DMODE=011, ABSIZE=00, ABMODE=011, ADSIZE=10, ADMODE=011, ISIZE=0x0, IMODE=001
	# mww 0x52005108 0x00000004				;# OCTOSPI_TCR: SSHIFT=0, DHQC=0, DCYC=0x4
	# mww 0x52005110 0x000000eb				;# OCTOSPI_IR: INSTR=FastRead, 0x03
	# mww 0x52005120 0x000000ff				;# OCTOSPI_ABR: alternate bytes register

	# mww 0x52005180 0x03002101				;# OCTOSPI_WCCR: SIOO=0, DMODE=011, ABSIZE=00, ABMODE=011, ADSIZE=10, ADMODE=011, ISIZE=0x0, IMODE=001
	# mww 0x52005188 0x00000000				;# OCTOSPI_WTCR: SSHIFT=0, DHQC=0, DCYC=0x4
	# mww 0x52005190 0x00000032				;# OCTOSPI_WIR: INSTR=FastRead, 0x03
	# mww 0x520051a0 0x000000ff				;# OCTOSPI_WABR: alternate bytes register
 
	sleep 1
	flash probe $a							;# load configuration from CR, TCR, CCR, IR register values
}

# RCC配置，然后调用octospi_init
$_CHIPNAME.cpu0 configure -event reset-init {
	global OCTOSPI1
	global OCTOSPI2

	mmw 0x52002000 0x00000004 0x0000000B	;# FLASH_ACR: 4 WS for  64MHZ HCLK

	mmw 0x58024400 0x00000001 0x00000018	;# RCC_CR: HSIDIV=1, HSI on
	mww 0x58024418 0x00000040				;# RCC_CDCFGR1: CDCPRE=1, CDPPRE=2, HPRE=1
	mww 0x5802441C 0x00000440				;# RCC_CDCFGR2: CDPPRE2=2, CDPPRE1=2
	mww 0x58024420 0x00000040				;# RCC_SRDCFGR: SRDPPRE=2
	mww 0x58024428 0x00404040				;# RCC_PLLCKSELR: DIVM3=4, DIVM2=4, DIVM1=4, PLLSRC=HSI
	mww 0x5802442C 0x01ff0ccc				;# RCC_PLLCFGR: PLLxRGE=8MHz to 16MHz, PLLxVCOSEL=wide
	mww 0x58024430 0x01010207				;# RCC_PLL1DIVR: 64MHz: DIVR1=2, DIVQ1=2, DIVP1=2, DIVN1=8
	mww 0x58024438 0x01010207				;# RCC_PLL2DIVR: 64MHz: DIVR2=2, DIVQ2=2, DIVP2=2, DIVN2=8
	mww 0x58024440 0x01010207				;# RCC_PLL3DIVR: 64MHz: DIVR3=2, DIVQ3=2, DIVP3=2, DIVN3=8
	mmw 0x58024400 0x01000000 0				;# RCC_CR: PLL1ON=1
	sleep 1
	mmw 0x58024410 0x00000003 0				;# RCC_CFGR: PLL1 as system clock
	sleep 1

	if { $OCTOSPI1 } {
		octospi_init 1
	}
}

adapter speed 10000
reset_config none separate