8 Raspberry Pi RP2040 Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n \n SPDX-License-Identifier: BSD-3-Clause 0.1 32 CM0PLUS r0p1 little true false 2 1 false 26 0 0x0020 registers 0x14000000 QSPI flash execute-in-place block XIP_IRQ 6 XIP_CTRL 0x0000 Cache control read-write [3:3] When 1, the cache memories are powered down. They retain state,\n but can not be accessed. This reduces static power dissipation.\n Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n be enabled when powered down.\n Cache-as-SRAM accesses will produce a bus error response when\n the cache is powered down. POWER_DOWN read-write [1:1] When 1, writes to any alias other than 0x0 (caching, allocating)\n will produce a bus fault. When 0, these writes are silently ignored.\n In either case, writes to the 0x0 alias will deallocate on tag match,\n as usual. ERR_BADWRITE read-write [0:0] When 1, enable the cache. When the cache is disabled, all XIP accesses\n will go straight to the flash, without querying the cache. When enabled,\n cacheable XIP accesses will query the cache, and the flash will\n not be accessed if the tag matches and the valid bit is set.\n\n If the cache is enabled, cache-as-SRAM accesses have no effect on the\n cache data RAM, and will produce a bus error response. EN CTRL 0x00000003 0x0004 Cache Flush control read-write [0:0] Write 1 to flush the cache. This clears the tag memory, but\n the data memory retains its contents. (This means cache-as-SRAM\n contents is not affected by flush or reset.)\n Reading will hold the bus (stall the processor) until the flush\n completes. Alternatively STAT can be polled until completion. clear FLUSH FLUSH 0x00000000 0x0008 Cache Status read-only [2:2] When 1, indicates the XIP streaming FIFO is completely full.\n The streaming FIFO is 2 entries deep, so the full and empty\n flag allow its level to be ascertained. FIFO_FULL read-only [1:1] When 1, indicates the XIP streaming FIFO is completely empty. FIFO_EMPTY read-only [0:0] Reads as 0 while a cache flush is in progress, and 1 otherwise.\n The cache is flushed whenever the XIP block is reset, and also\n when requested via the FLUSH register. FLUSH_READY STAT 0x00000002 read-write 0x000c Cache Hit counter\n A 32 bit saturating counter that increments upon each cache hit,\n i.e. when an XIP access is serviced directly from cached data.\n Write any value to clear. oneToClear CTR_HIT 0x00000000 read-write 0x0010 Cache Access counter\n A 32 bit saturating counter that increments upon each XIP access,\n whether the cache is hit or not. This includes noncacheable accesses.\n Write any value to clear. oneToClear CTR_ACC 0x00000000 0x0014 FIFO stream address read-write [31:2] The address of the next word to be streamed from flash to the streaming FIFO.\n Increments automatically after each flash access.\n Write the initial access address here before starting a streaming read. STREAM_ADDR STREAM_ADDR 0x00000000 0x0018 FIFO stream control read-write [21:0] Write a nonzero value to start a streaming read. This will then\n progress in the background, using flash idle cycles to transfer\n a linear data block from flash to the streaming FIFO.\n Decrements automatically (1 at a time) as the stream\n progresses, and halts on reaching 0.\n Write 0 to halt an in-progress stream, and discard any in-flight\n read, so that a new stream can immediately be started (after\n draining the FIFO and reinitialising STREAM_ADDR) STREAM_CTR STREAM_CTR 0x00000000 read-only 0x001c FIFO stream data\n Streamed data is buffered here, for retrieval by the system DMA.\n This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n the DMA to bus stalls caused by other XIP traffic. STREAM_FIFO 0x00000000 32 1 0 0x0100 registers 0x18000000 DW_apb_ssi has the following features:\n * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n * APB3 and APB4 protocol support.\n * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n * Programmable Dual/Quad/Octal SPI support in Master Mode.\n * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n * Programmable features:\n - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n * Configured features:\n - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n - 1 slave select output.\n - Hardware slave-select – Dedicated hardware slave-select line.\n - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - Interrupt polarity – active high interrupt lines.\n - Serial clock polarity – low serial-clock polarity directly after reset.\n - Serial clock phase – capture on first edge of serial-clock directly after reset. XIP_SSI 0x0000 Control register 0 read-write [24:24] Slave select toggle enable SSTE read-write [22:21] SPI frame format Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex STD 0 Dual-SPI frame format; two bits per SCK, half-duplex DUAL 1 Quad-SPI frame format; four bits per SCK, half-duplex QUAD 2 SPI_FRF read-write [20:16] Data frame size in 32b transfer mode\n Value of n -> n+1 clocks per frame. DFS_32 read-write [15:12] Control frame size\n Value of n -> n+1 clocks per frame. CFS read-write [11:11] Shift register loop (test mode) SRL read-write [10:10] Slave output enable SLV_OE read-write [9:8] Transfer mode Both transmit and receive TX_AND_RX 0 Transmit only (not for FRF == 0, standard SPI mode) TX_ONLY 1 Receive only (not for FRF == 0, standard SPI mode) RX_ONLY 2 EEPROM read mode (TX then RX; RX starts after control data TX'd) EEPROM_READ 3 TMOD read-write [7:7] Serial clock polarity SCPOL read-write [6:6] Serial clock phase SCPH read-write [5:4] Frame format FRF read-write [3:0] Data frame size DFS CTRLR0 0x00000000 0x0004 Master Control register 1 read-write [15:0] Number of data frames NDF CTRLR1 0x00000000 0x0008 SSI Enable read-write [0:0] SSI enable SSI_EN SSIENR 0x00000000 0x000c Microwire Control read-write [2:2] Microwire handshaking MHS read-write [1:1] Microwire control MDD read-write [0:0] Microwire transfer mode MWMOD MWCR 0x00000000 0x0010 Slave enable read-write [0:0] For each bit:\n 0 -> slave not selected\n 1 -> slave selected SER SER 0x00000000 0x0014 Baud rate read-write [15:0] SSI clock divider SCKDV BAUDR 0x00000000 0x0018 TX FIFO threshold level read-write [7:0] Transmit FIFO threshold TFT TXFTLR 0x00000000 0x001c RX FIFO threshold level read-write [7:0] Receive FIFO threshold RFT RXFTLR 0x00000000 0x0020 TX FIFO level read-only [7:0] Transmit FIFO level TFTFL TXFLR 0x00000000 0x0024 RX FIFO level read-only [7:0] Receive FIFO level RXTFL RXFLR 0x00000000 0x0028 Status register read-only [6:6] Data collision error DCOL read-only [5:5] Transmission error TXE read-only [4:4] Receive FIFO full RFF read-only [3:3] Receive FIFO not empty RFNE read-only [2:2] Transmit FIFO empty TFE read-only [1:1] Transmit FIFO not full TFNF read-only [0:0] SSI busy flag BUSY SR 0x00000000 0x002c Interrupt mask read-write [5:5] Multi-master contention interrupt mask MSTIM read-write [4:4] Receive FIFO full interrupt mask RXFIM read-write [3:3] Receive FIFO overflow interrupt mask RXOIM read-write [2:2] Receive FIFO underflow interrupt mask RXUIM read-write [1:1] Transmit FIFO overflow interrupt mask TXOIM read-write [0:0] Transmit FIFO empty interrupt mask TXEIM IMR 0x00000000 0x0030 Interrupt status read-only [5:5] Multi-master contention interrupt status MSTIS read-only [4:4] Receive FIFO full interrupt status RXFIS read-only [3:3] Receive FIFO overflow interrupt status RXOIS read-only [2:2] Receive FIFO underflow interrupt status RXUIS read-only [1:1] Transmit FIFO overflow interrupt status TXOIS read-only [0:0] Transmit FIFO empty interrupt status TXEIS ISR 0x00000000 0x0034 Raw interrupt status read-only [5:5] Multi-master contention raw interrupt status MSTIR read-only [4:4] Receive FIFO full raw interrupt status RXFIR read-only [3:3] Receive FIFO overflow raw interrupt status RXOIR read-only [2:2] Receive FIFO underflow raw interrupt status RXUIR read-only [1:1] Transmit FIFO overflow raw interrupt status TXOIR read-only [0:0] Transmit FIFO empty raw interrupt status TXEIR RISR 0x00000000 0x0038 TX FIFO overflow interrupt clear read-only [0:0] Clear-on-read transmit FIFO overflow interrupt TXOICR TXOICR 0x00000000 0x003c RX FIFO overflow interrupt clear read-only [0:0] Clear-on-read receive FIFO overflow interrupt RXOICR RXOICR 0x00000000 0x0040 RX FIFO underflow interrupt clear read-only [0:0] Clear-on-read receive FIFO underflow interrupt RXUICR RXUICR 0x00000000 0x0044 Multi-master interrupt clear read-only [0:0] Clear-on-read multi-master contention interrupt MSTICR MSTICR 0x00000000 0x0048 Interrupt clear read-only [0:0] Clear-on-read all active interrupts ICR ICR 0x00000000 0x004c DMA control read-write [1:1] Transmit DMA enable TDMAE read-write [0:0] Receive DMA enable RDMAE DMACR 0x00000000 0x0050 DMA TX data level read-write [7:0] Transmit data watermark level DMATDL DMATDLR 0x00000000 0x0054 DMA RX data level read-write [7:0] Receive data watermark level (DMARDLR+1) DMARDL DMARDLR 0x00000000 0x0058 Identification register read-only [31:0] Peripheral dentification code IDCODE IDR 0x51535049 0x005c Version ID read-only [31:0] SNPS component version (format X.YY) SSI_COMP_VERSION SSI_VERSION_ID 0x3430312a 0x0060 Data Register 0 (of 36) read-write [31:0] First data register of 36 DR DR0 0x00000000 0x00f0 RX sample delay read-write [7:0] RXD sample delay (in SCLK cycles) RSD RX_SAMPLE_DLY 0x00000000 0x00f4 SPI control read-write [31:24] SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) XIP_CMD read-write [18:18] Read data strobe enable SPI_RXDS_EN read-write [17:17] Instruction DDR transfer enable INST_DDR_EN read-write [16:16] SPI DDR transfer enable SPI_DDR_EN read-write [15:11] Wait cycles between control frame transmit and data reception (in SCLK cycles) WAIT_CYCLES read-write [9:8] Instruction length (0/4/8/16b) No instruction NONE 0 4-bit instruction 4B 1 8-bit instruction 8B 2 16-bit instruction 16B 3 INST_L read-write [5:2] Address length (0b-60b in 4b increments) ADDR_L read-write [1:0] Address and instruction transfer format Command and address both in standard SPI frame format 1C1A 0 Command in standard SPI format, address in format specified by FRF 1C2A 1 Command and address both in format specified by FRF (e.g. Dual-SPI) 2C2A 2 TRANS_TYPE SPI_CTRLR0 0x03000000 0x00f8 TX drive edge read-write [7:0] TXD drive edge TDE TXD_DRIVE_EDGE 0x00000000 32 1 0 0x1000 registers 0x40000000 SYSINFO 0x0000 JEDEC JEP-106 compliant chip identifier. read-only [31:28] REVISION read-only [27:12] PART read-only [11:0] MANUFACTURER CHIP_ID 0x00000000 0x0004 Platform register. Allows software to know what environment it is running in. read-only [1:1] ASIC read-only [0:0] FPGA PLATFORM 0x00000000 read-only 0x0040 Git hash of the chip source. Used to identify chip version. GITREF_RP2040 0x00000000 32 1 0 0x1000 registers 0x40004000 Register block for various chip control signals SYSCFG read-write 0x0000 Processor core 0 NMI source mask\n Set a bit high to enable NMI from that IRQ PROC0_NMI_MASK 0x00000000 read-write 0x0004 Processor core 1 NMI source mask\n Set a bit high to enable NMI from that IRQ PROC1_NMI_MASK 0x00000000 0x0008 Configuration for processors read-write [31:28] Configure proc1 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP PROC1_DAP_INSTID read-write [27:24] Configure proc0 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP PROC0_DAP_INSTID read-only [1:1] Indication that proc1 has halted PROC1_HALTED read-only [0:0] Indication that proc0 has halted PROC0_HALTED PROC_CONFIG 0x10000000 0x000c For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 0...29. read-write [29:0] PROC_IN_SYNC_BYPASS PROC_IN_SYNC_BYPASS 0x00000000 0x0010 For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 30...35 (the QSPI IOs). read-write [5:0] PROC_IN_SYNC_BYPASS_HI PROC_IN_SYNC_BYPASS_HI 0x00000000 0x0014 Directly control the SWD debug port of either processor read-write [7:7] Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. PROC1_ATTACH read-write [6:6] Directly drive processor 1 SWCLK, if PROC1_ATTACH is set PROC1_SWCLK read-write [5:5] Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set PROC1_SWDI read-only [4:4] Observe the value of processor 1 SWDIO output. PROC1_SWDO read-write [3:3] Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. PROC0_ATTACH read-write [2:2] Directly drive processor 0 SWCLK, if PROC0_ATTACH is set PROC0_SWCLK read-write [1:1] Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set PROC0_SWDI read-only [0:0] Observe the value of processor 0 SWDIO output. PROC0_SWDO DBGFORCE 0x00000066 0x0018 Control power downs to memories. Set high to power down memories.\n Use with extreme caution read-write [7:7] ROM read-write [6:6] USB read-write [5:5] SRAM5 read-write [4:4] SRAM4 read-write [3:3] SRAM3 read-write [2:2] SRAM2 read-write [1:1] SRAM1 read-write [0:0] SRAM0 MEMPOWERDOWN 0x00000000 32 1 0 0x1000 registers 0x40008000 CLOCKS_IRQ 17 CLOCKS 0x0000 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT0_CTRL 0x00000000 0x0004 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT0_DIV 0x00000100 read-only 0x0008 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT0_SELECTED 0x00000001 0x000c Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT1_CTRL 0x00000000 0x0010 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT1_DIV 0x00000100 read-only 0x0014 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT1_SELECTED 0x00000001 0x0018 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc_ph 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT2_CTRL 0x00000000 0x001c Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT2_DIV 0x00000100 read-only 0x0020 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT2_SELECTED 0x00000001 0x0024 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc_ph 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT3_CTRL 0x00000000 0x0028 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT3_DIV 0x00000100 read-only 0x002c Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_GPOUT3_SELECTED 0x00000001 0x0030 Clock control, can be changed on-the-fly (except for auxsrc) read-write [6:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_gpin0 1 clksrc_gpin1 2 AUXSRC read-write [1:0] Selects the clock source glitchlessly, can be changed on-the-fly rosc_clksrc_ph 0 clksrc_clk_ref_aux 1 xosc_clksrc 2 SRC CLK_REF_CTRL 0x00000000 0x0034 Clock divisor, can be changed on-the-fly read-write [9:8] Integer component of the divisor, 0 -> divide by 2^16 INT CLK_REF_DIV 0x00000100 read-only 0x0038 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. CLK_REF_SELECTED 0x00000001 0x003c Clock control, can be changed on-the-fly (except for auxsrc) read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_pll_usb 1 rosc_clksrc 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC read-write [0:0] Selects the clock source glitchlessly, can be changed on-the-fly clk_ref 0 clksrc_clk_sys_aux 1 SRC CLK_SYS_CTRL 0x00000000 0x0040 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_SYS_DIV 0x00000100 read-only 0x0044 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. CLK_SYS_SELECTED 0x00000001 0x0048 Clock control, can be changed on-the-fly (except for auxsrc) read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clk_sys 0 clksrc_pll_sys 1 clksrc_pll_usb 2 rosc_clksrc_ph 3 xosc_clksrc 4 clksrc_gpin0 5 clksrc_gpin1 6 AUXSRC CLK_PERI_CTRL 0x00000000 read-only 0x0050 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_PERI_SELECTED 0x00000001 0x0054 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC CLK_USB_CTRL 0x00000000 0x0058 Clock divisor, can be changed on-the-fly read-write [9:8] Integer component of the divisor, 0 -> divide by 2^16 INT CLK_USB_DIV 0x00000100 read-only 0x005c Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_USB_SELECTED 0x00000001 0x0060 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC CLK_ADC_CTRL 0x00000000 0x0064 Clock divisor, can be changed on-the-fly read-write [9:8] Integer component of the divisor, 0 -> divide by 2^16 INT CLK_ADC_DIV 0x00000100 read-only 0x0068 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_ADC_SELECTED 0x00000001 0x006c Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC CLK_RTC_CTRL 0x00000000 0x0070 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_RTC_DIV 0x00000100 read-only 0x0074 Indicates which SRC is currently selected by the glitchless mux (one-hot).\n This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. CLK_RTC_SELECTED 0x00000001 0x0078 read-write [16:16] For clearing the resus after the fault that triggered it has been corrected CLEAR read-write [12:12] Force a resus, for test purposes only FRCE read-write [8:8] Enable resus ENABLE read-write [7:0] This is expressed as a number of clk_ref cycles\n and must be >= 2x clk_ref_freq/min_clk_tst_freq TIMEOUT CLK_SYS_RESUS_CTRL 0x000000ff 0x007c read-only [0:0] Clock has been resuscitated, correct the error then send ctrl_clear=1 RESUSSED CLK_SYS_RESUS_STATUS 0x00000000 0x0080 Reference clock frequency in kHz read-write [19:0] FC0_REF_KHZ FC0_REF_KHZ 0x00000000 0x0084 Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags read-write [24:0] FC0_MIN_KHZ FC0_MIN_KHZ 0x00000000 0x0088 Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags read-write [24:0] FC0_MAX_KHZ FC0_MAX_KHZ 0x01ffffff 0x008c Delays the start of frequency counting to allow the mux to settle\n Delay is measured in multiples of the reference clock period read-write [2:0] FC0_DELAY FC0_DELAY 0x00000001 0x0090 The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n The default gives a test interval of 250us read-write [3:0] FC0_INTERVAL FC0_INTERVAL 0x00000008 0x0094 Clock sent to frequency counter, set to 0 when not required\n Writing to this register initiates the frequency count read-write [7:0] NULL 0 pll_sys_clksrc_primary 1 pll_usb_clksrc_primary 2 rosc_clksrc 3 rosc_clksrc_ph 4 xosc_clksrc 5 clksrc_gpin0 6 clksrc_gpin1 7 clk_ref 8 clk_sys 9 clk_peri 10 clk_usb 11 clk_adc 12 clk_rtc 13 FC0_SRC FC0_SRC 0x00000000 0x0098 Frequency counter status read-only [28:28] Test clock stopped during test DIED read-only [24:24] Test clock faster than expected, only valid when status_done=1 FAST read-only [20:20] Test clock slower than expected, only valid when status_done=1 SLOW read-only [16:16] Test failed FAIL read-only [12:12] Waiting for test clock to start WAITING read-only [8:8] Test running RUNNING read-only [4:4] Test complete DONE read-only [0:0] Test passed PASS FC0_STATUS 0x00000000 0x009c Result of frequency measurement, only valid when status_done=1 read-only [29:5] KHZ read-only [4:0] FRAC FC0_RESULT 0x00000000 0x00a0 enable clock in wake mode read-write [31:31] clk_sys_sram3 read-write [30:30] clk_sys_sram2 read-write [29:29] clk_sys_sram1 read-write [28:28] clk_sys_sram0 read-write [27:27] clk_sys_spi1 read-write [26:26] clk_peri_spi1 read-write [25:25] clk_sys_spi0 read-write [24:24] clk_peri_spi0 read-write [23:23] clk_sys_sio read-write [22:22] clk_sys_rtc read-write [21:21] clk_rtc_rtc read-write [20:20] clk_sys_rosc read-write [19:19] clk_sys_rom read-write [18:18] clk_sys_resets read-write [17:17] clk_sys_pwm read-write [16:16] clk_sys_psm read-write [15:15] clk_sys_pll_usb read-write [14:14] clk_sys_pll_sys read-write [13:13] clk_sys_pio1 read-write [12:12] clk_sys_pio0 read-write [11:11] clk_sys_pads read-write [10:10] clk_sys_vreg_and_chip_reset read-write [9:9] clk_sys_jtag read-write [8:8] clk_sys_io read-write [7:7] clk_sys_i2c1 read-write [6:6] clk_sys_i2c0 read-write [5:5] clk_sys_dma read-write [4:4] clk_sys_busfabric read-write [3:3] clk_sys_busctrl read-write [2:2] clk_sys_adc read-write [1:1] clk_adc_adc read-write [0:0] clk_sys_clocks WAKE_EN0 0xffffffff 0x00a4 enable clock in wake mode read-write [14:14] clk_sys_xosc read-write [13:13] clk_sys_xip read-write [12:12] clk_sys_watchdog read-write [11:11] clk_usb_usbctrl read-write [10:10] clk_sys_usbctrl read-write [9:9] clk_sys_uart1 read-write [8:8] clk_peri_uart1 read-write [7:7] clk_sys_uart0 read-write [6:6] clk_peri_uart0 read-write [5:5] clk_sys_timer read-write [4:4] clk_sys_tbman read-write [3:3] clk_sys_sysinfo read-write [2:2] clk_sys_syscfg read-write [1:1] clk_sys_sram5 read-write [0:0] clk_sys_sram4 WAKE_EN1 0x00007fff 0x00a8 enable clock in sleep mode read-write [31:31] clk_sys_sram3 read-write [30:30] clk_sys_sram2 read-write [29:29] clk_sys_sram1 read-write [28:28] clk_sys_sram0 read-write [27:27] clk_sys_spi1 read-write [26:26] clk_peri_spi1 read-write [25:25] clk_sys_spi0 read-write [24:24] clk_peri_spi0 read-write [23:23] clk_sys_sio read-write [22:22] clk_sys_rtc read-write [21:21] clk_rtc_rtc read-write [20:20] clk_sys_rosc read-write [19:19] clk_sys_rom read-write [18:18] clk_sys_resets read-write [17:17] clk_sys_pwm read-write [16:16] clk_sys_psm read-write [15:15] clk_sys_pll_usb read-write [14:14] clk_sys_pll_sys read-write [13:13] clk_sys_pio1 read-write [12:12] clk_sys_pio0 read-write [11:11] clk_sys_pads read-write [10:10] clk_sys_vreg_and_chip_reset read-write [9:9] clk_sys_jtag read-write [8:8] clk_sys_io read-write [7:7] clk_sys_i2c1 read-write [6:6] clk_sys_i2c0 read-write [5:5] clk_sys_dma read-write [4:4] clk_sys_busfabric read-write [3:3] clk_sys_busctrl read-write [2:2] clk_sys_adc read-write [1:1] clk_adc_adc read-write [0:0] clk_sys_clocks SLEEP_EN0 0xffffffff 0x00ac enable clock in sleep mode read-write [14:14] clk_sys_xosc read-write [13:13] clk_sys_xip read-write [12:12] clk_sys_watchdog read-write [11:11] clk_usb_usbctrl read-write [10:10] clk_sys_usbctrl read-write [9:9] clk_sys_uart1 read-write [8:8] clk_peri_uart1 read-write [7:7] clk_sys_uart0 read-write [6:6] clk_peri_uart0 read-write [5:5] clk_sys_timer read-write [4:4] clk_sys_tbman read-write [3:3] clk_sys_sysinfo read-write [2:2] clk_sys_syscfg read-write [1:1] clk_sys_sram5 read-write [0:0] clk_sys_sram4 SLEEP_EN1 0x00007fff 0x00b0 indicates the state of the clock enable read-only [31:31] clk_sys_sram3 read-only [30:30] clk_sys_sram2 read-only [29:29] clk_sys_sram1 read-only [28:28] clk_sys_sram0 read-only [27:27] clk_sys_spi1 read-only [26:26] clk_peri_spi1 read-only [25:25] clk_sys_spi0 read-only [24:24] clk_peri_spi0 read-only [23:23] clk_sys_sio read-only [22:22] clk_sys_rtc read-only [21:21] clk_rtc_rtc read-only [20:20] clk_sys_rosc read-only [19:19] clk_sys_rom read-only [18:18] clk_sys_resets read-only [17:17] clk_sys_pwm read-only [16:16] clk_sys_psm read-only [15:15] clk_sys_pll_usb read-only [14:14] clk_sys_pll_sys read-only [13:13] clk_sys_pio1 read-only [12:12] clk_sys_pio0 read-only [11:11] clk_sys_pads read-only [10:10] clk_sys_vreg_and_chip_reset read-only [9:9] clk_sys_jtag read-only [8:8] clk_sys_io read-only [7:7] clk_sys_i2c1 read-only [6:6] clk_sys_i2c0 read-only [5:5] clk_sys_dma read-only [4:4] clk_sys_busfabric read-only [3:3] clk_sys_busctrl read-only [2:2] clk_sys_adc read-only [1:1] clk_adc_adc read-only [0:0] clk_sys_clocks ENABLED0 0x00000000 0x00b4 indicates the state of the clock enable read-only [14:14] clk_sys_xosc read-only [13:13] clk_sys_xip read-only [12:12] clk_sys_watchdog read-only [11:11] clk_usb_usbctrl read-only [10:10] clk_sys_usbctrl read-only [9:9] clk_sys_uart1 read-only [8:8] clk_peri_uart1 read-only [7:7] clk_sys_uart0 read-only [6:6] clk_peri_uart0 read-only [5:5] clk_sys_timer read-only [4:4] clk_sys_tbman read-only [3:3] clk_sys_sysinfo read-only [2:2] clk_sys_syscfg read-only [1:1] clk_sys_sram5 read-only [0:0] clk_sys_sram4 ENABLED1 0x00000000 0x00b8 Raw Interrupts read-only [0:0] CLK_SYS_RESUS INTR 0x00000000 0x00bc Interrupt Enable read-write [0:0] CLK_SYS_RESUS INTE 0x00000000 0x00c0 Interrupt Force read-write [0:0] CLK_SYS_RESUS INTF 0x00000000 0x00c4 Interrupt status after masking & forcing read-only [0:0] CLK_SYS_RESUS INTS 0x00000000 32 1 0 0x1000 registers 0x4000c000 RESETS 0x0000 Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. read-write [24:24] usbctrl read-write [23:23] uart1 read-write [22:22] uart0 read-write [21:21] timer read-write [20:20] tbman read-write [19:19] sysinfo read-write [18:18] syscfg read-write [17:17] spi1 read-write [16:16] spi0 read-write [15:15] rtc read-write [14:14] pwm read-write [13:13] pll_usb read-write [12:12] pll_sys read-write [11:11] pio1 read-write [10:10] pio0 read-write [9:9] pads_qspi read-write [8:8] pads_bank0 read-write [7:7] jtag read-write [6:6] io_qspi read-write [5:5] io_bank0 read-write [4:4] i2c1 read-write [3:3] i2c0 read-write [2:2] dma read-write [1:1] busctrl read-write [0:0] adc RESET 0x01ffffff 0x0004 Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. read-write [24:24] usbctrl read-write [23:23] uart1 read-write [22:22] uart0 read-write [21:21] timer read-write [20:20] tbman read-write [19:19] sysinfo read-write [18:18] syscfg read-write [17:17] spi1 read-write [16:16] spi0 read-write [15:15] rtc read-write [14:14] pwm read-write [13:13] pll_usb read-write [12:12] pll_sys read-write [11:11] pio1 read-write [10:10] pio0 read-write [9:9] pads_qspi read-write [8:8] pads_bank0 read-write [7:7] jtag read-write [6:6] io_qspi read-write [5:5] io_bank0 read-write [4:4] i2c1 read-write [3:3] i2c0 read-write [2:2] dma read-write [1:1] busctrl read-write [0:0] adc WDSEL 0x00000000 0x0008 Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. read-only [24:24] usbctrl read-only [23:23] uart1 read-only [22:22] uart0 read-only [21:21] timer read-only [20:20] tbman read-only [19:19] sysinfo read-only [18:18] syscfg read-only [17:17] spi1 read-only [16:16] spi0 read-only [15:15] rtc read-only [14:14] pwm read-only [13:13] pll_usb read-only [12:12] pll_sys read-only [11:11] pio1 read-only [10:10] pio0 read-only [9:9] pads_qspi read-only [8:8] pads_bank0 read-only [7:7] jtag read-only [6:6] io_qspi read-only [5:5] io_bank0 read-only [4:4] i2c1 read-only [3:3] i2c0 read-only [2:2] dma read-only [1:1] busctrl read-only [0:0] adc RESET_DONE 0x00000000 32 1 0 0x1000 registers 0x40010000 PSM 0x0000 Force block out of reset (i.e. power it on) read-write [16:16] proc1 read-write [15:15] proc0 read-write [14:14] sio read-write [13:13] vreg_and_chip_reset read-write [12:12] xip read-write [11:11] sram5 read-write [10:10] sram4 read-write [9:9] sram3 read-write [8:8] sram2 read-write [7:7] sram1 read-write [6:6] sram0 read-write [5:5] rom read-write [4:4] busfabric read-write [3:3] resets read-write [2:2] clocks read-write [1:1] xosc read-write [0:0] rosc FRCE_ON 0x00000000 0x0004 Force into reset (i.e. power it off) read-write [16:16] proc1 read-write [15:15] proc0 read-write [14:14] sio read-write [13:13] vreg_and_chip_reset read-write [12:12] xip read-write [11:11] sram5 read-write [10:10] sram4 read-write [9:9] sram3 read-write [8:8] sram2 read-write [7:7] sram1 read-write [6:6] sram0 read-write [5:5] rom read-write [4:4] busfabric read-write [3:3] resets read-write [2:2] clocks read-write [1:1] xosc read-write [0:0] rosc FRCE_OFF 0x00000000 0x0008 Set to 1 if this peripheral should be reset when the watchdog fires. read-write [16:16] proc1 read-write [15:15] proc0 read-write [14:14] sio read-write [13:13] vreg_and_chip_reset read-write [12:12] xip read-write [11:11] sram5 read-write [10:10] sram4 read-write [9:9] sram3 read-write [8:8] sram2 read-write [7:7] sram1 read-write [6:6] sram0 read-write [5:5] rom read-write [4:4] busfabric read-write [3:3] resets read-write [2:2] clocks read-write [1:1] xosc read-write [0:0] rosc WDSEL 0x00000000 0x000c Indicates the peripheral's registers are ready to access. read-only [16:16] proc1 read-only [15:15] proc0 read-only [14:14] sio read-only [13:13] vreg_and_chip_reset read-only [12:12] xip read-only [11:11] sram5 read-only [10:10] sram4 read-only [9:9] sram3 read-only [8:8] sram2 read-only [7:7] sram1 read-only [6:6] sram0 read-only [5:5] rom read-only [4:4] busfabric read-only [3:3] resets read-only [2:2] clocks read-only [1:1] xosc read-only [0:0] rosc DONE 0x00000000 32 1 0 0x1000 registers 0x40014000 IO_IRQ_BANK0 13 IO_BANK0 0x0000 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO0_STATUS 0x00000000 0x0004 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tck 0 spi0_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_0 4 sio_0 5 pio0_0 6 pio1_0 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO0_CTRL 0x0000001f 0x0008 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO1_STATUS 0x00000000 0x000c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tms 0 spi0_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_0 4 sio_1 5 pio0_1 6 pio1_1 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO1_CTRL 0x0000001f 0x0010 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO2_STATUS 0x00000000 0x0014 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tdi 0 spi0_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_1 4 sio_2 5 pio0_2 6 pio1_2 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO2_CTRL 0x0000001f 0x0018 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO3_STATUS 0x00000000 0x001c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tdo 0 spi0_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_1 4 sio_3 5 pio0_3 6 pio1_3 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO3_CTRL 0x0000001f 0x0020 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO4_STATUS 0x00000000 0x0024 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_2 4 sio_4 5 pio0_4 6 pio1_4 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO4_CTRL 0x0000001f 0x0028 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO5_STATUS 0x00000000 0x002c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_2 4 sio_5 5 pio0_5 6 pio1_5 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO5_CTRL 0x0000001f 0x0030 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO6_STATUS 0x00000000 0x0034 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_3 4 sio_6 5 pio0_6 6 pio1_6 7 usb_muxing_extphy_softcon 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO6_CTRL 0x0000001f 0x0038 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO7_STATUS 0x00000000 0x003c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_3 4 sio_7 5 pio0_7 6 pio1_7 7 usb_muxing_extphy_oe_n 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO7_CTRL 0x0000001f 0x0040 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO8_STATUS 0x00000000 0x0044 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_4 4 sio_8 5 pio0_8 6 pio1_8 7 usb_muxing_extphy_rcv 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO8_CTRL 0x0000001f 0x0048 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO9_STATUS 0x00000000 0x004c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_4 4 sio_9 5 pio0_9 6 pio1_9 7 usb_muxing_extphy_vp 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO9_CTRL 0x0000001f 0x0050 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO10_STATUS 0x00000000 0x0054 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_5 4 sio_10 5 pio0_10 6 pio1_10 7 usb_muxing_extphy_vm 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO10_CTRL 0x0000001f 0x0058 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO11_STATUS 0x00000000 0x005c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_5 4 sio_11 5 pio0_11 6 pio1_11 7 usb_muxing_extphy_suspnd 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO11_CTRL 0x0000001f 0x0060 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO12_STATUS 0x00000000 0x0064 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_6 4 sio_12 5 pio0_12 6 pio1_12 7 usb_muxing_extphy_speed 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO12_CTRL 0x0000001f 0x0068 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO13_STATUS 0x00000000 0x006c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_6 4 sio_13 5 pio0_13 6 pio1_13 7 usb_muxing_extphy_vpo 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO13_CTRL 0x0000001f 0x0070 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO14_STATUS 0x00000000 0x0074 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_7 4 sio_14 5 pio0_14 6 pio1_14 7 usb_muxing_extphy_vmo 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO14_CTRL 0x0000001f 0x0078 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO15_STATUS 0x00000000 0x007c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_7 4 sio_15 5 pio0_15 6 pio1_15 7 usb_muxing_digital_dp 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO15_CTRL 0x0000001f 0x0080 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO16_STATUS 0x00000000 0x0084 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_0 4 sio_16 5 pio0_16 6 pio1_16 7 usb_muxing_digital_dm 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO16_CTRL 0x0000001f 0x0088 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO17_STATUS 0x00000000 0x008c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_0 4 sio_17 5 pio0_17 6 pio1_17 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO17_CTRL 0x0000001f 0x0090 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO18_STATUS 0x00000000 0x0094 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_1 4 sio_18 5 pio0_18 6 pio1_18 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO18_CTRL 0x0000001f 0x0098 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO19_STATUS 0x00000000 0x009c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_1 4 sio_19 5 pio0_19 6 pio1_19 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO19_CTRL 0x0000001f 0x00a0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO20_STATUS 0x00000000 0x00a4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_2 4 sio_20 5 pio0_20 6 pio1_20 7 clocks_gpin_0 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO20_CTRL 0x0000001f 0x00a8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO21_STATUS 0x00000000 0x00ac GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_2 4 sio_21 5 pio0_21 6 pio1_21 7 clocks_gpout_0 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO21_CTRL 0x0000001f 0x00b0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO22_STATUS 0x00000000 0x00b4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_3 4 sio_22 5 pio0_22 6 pio1_22 7 clocks_gpin_1 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO22_CTRL 0x0000001f 0x00b8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO23_STATUS 0x00000000 0x00bc GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_3 4 sio_23 5 pio0_23 6 pio1_23 7 clocks_gpout_1 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO23_CTRL 0x0000001f 0x00c0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO24_STATUS 0x00000000 0x00c4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_4 4 sio_24 5 pio0_24 6 pio1_24 7 clocks_gpout_2 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO24_CTRL 0x0000001f 0x00c8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO25_STATUS 0x00000000 0x00cc GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_4 4 sio_25 5 pio0_25 6 pio1_25 7 clocks_gpout_3 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO25_CTRL 0x0000001f 0x00d0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO26_STATUS 0x00000000 0x00d4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_5 4 sio_26 5 pio0_26 6 pio1_26 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO26_CTRL 0x0000001f 0x00d8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO27_STATUS 0x00000000 0x00dc GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_5 4 sio_27 5 pio0_27 6 pio1_27 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO27_CTRL 0x0000001f 0x00e0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO28_STATUS 0x00000000 0x00e4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_6 4 sio_28 5 pio0_28 6 pio1_28 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO28_CTRL 0x0000001f 0x00e8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO29_STATUS 0x00000000 0x00ec GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_6 4 sio_29 5 pio0_29 6 pio1_29 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO29_CTRL 0x0000001f 0x00f0 Raw Interrupts read-write [31:31] oneToClear GPIO7_EDGE_HIGH read-write [30:30] oneToClear GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-write [27:27] oneToClear GPIO6_EDGE_HIGH read-write [26:26] oneToClear GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-write [23:23] oneToClear GPIO5_EDGE_HIGH read-write [22:22] oneToClear GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-write [19:19] oneToClear GPIO4_EDGE_HIGH read-write [18:18] oneToClear GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-write [15:15] oneToClear GPIO3_EDGE_HIGH read-write [14:14] oneToClear GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-write [11:11] oneToClear GPIO2_EDGE_HIGH read-write [10:10] oneToClear GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-write [7:7] oneToClear GPIO1_EDGE_HIGH read-write [6:6] oneToClear GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-write [3:3] oneToClear GPIO0_EDGE_HIGH read-write [2:2] oneToClear GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW INTR0 0x00000000 0x00f4 Raw Interrupts read-write [31:31] oneToClear GPIO15_EDGE_HIGH read-write [30:30] oneToClear GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-write [27:27] oneToClear GPIO14_EDGE_HIGH read-write [26:26] oneToClear GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-write [23:23] oneToClear GPIO13_EDGE_HIGH read-write [22:22] oneToClear GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-write [19:19] oneToClear GPIO12_EDGE_HIGH read-write [18:18] oneToClear GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-write [15:15] oneToClear GPIO11_EDGE_HIGH read-write [14:14] oneToClear GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-write [11:11] oneToClear GPIO10_EDGE_HIGH read-write [10:10] oneToClear GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-write [7:7] oneToClear GPIO9_EDGE_HIGH read-write [6:6] oneToClear GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-write [3:3] oneToClear GPIO8_EDGE_HIGH read-write [2:2] oneToClear GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW INTR1 0x00000000 0x00f8 Raw Interrupts read-write [31:31] oneToClear GPIO23_EDGE_HIGH read-write [30:30] oneToClear GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-write [27:27] oneToClear GPIO22_EDGE_HIGH read-write [26:26] oneToClear GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-write [23:23] oneToClear GPIO21_EDGE_HIGH read-write [22:22] oneToClear GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-write [19:19] oneToClear GPIO20_EDGE_HIGH read-write [18:18] oneToClear GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-write [15:15] oneToClear GPIO19_EDGE_HIGH read-write [14:14] oneToClear GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-write [11:11] oneToClear GPIO18_EDGE_HIGH read-write [10:10] oneToClear GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-write [7:7] oneToClear GPIO17_EDGE_HIGH read-write [6:6] oneToClear GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-write [3:3] oneToClear GPIO16_EDGE_HIGH read-write [2:2] oneToClear GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW INTR2 0x00000000 0x00fc Raw Interrupts read-write [23:23] oneToClear GPIO29_EDGE_HIGH read-write [22:22] oneToClear GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-write [19:19] oneToClear GPIO28_EDGE_HIGH read-write [18:18] oneToClear GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-write [15:15] oneToClear GPIO27_EDGE_HIGH read-write [14:14] oneToClear GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-write [11:11] oneToClear GPIO26_EDGE_HIGH read-write [10:10] oneToClear GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-write [7:7] oneToClear GPIO25_EDGE_HIGH read-write [6:6] oneToClear GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-write [3:3] oneToClear GPIO24_EDGE_HIGH read-write [2:2] oneToClear GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW INTR3 0x00000000 0x0100 Interrupt Enable for proc0 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC0_INTE0 0x00000000 0x0104 Interrupt Enable for proc0 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC0_INTE1 0x00000000 0x0108 Interrupt Enable for proc0 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC0_INTE2 0x00000000 0x010c Interrupt Enable for proc0 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC0_INTE3 0x00000000 0x0110 Interrupt Force for proc0 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC0_INTF0 0x00000000 0x0114 Interrupt Force for proc0 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC0_INTF1 0x00000000 0x0118 Interrupt Force for proc0 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC0_INTF2 0x00000000 0x011c Interrupt Force for proc0 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC0_INTF3 0x00000000 0x0120 Interrupt status after masking & forcing for proc0 read-only [31:31] GPIO7_EDGE_HIGH read-only [30:30] GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-only [27:27] GPIO6_EDGE_HIGH read-only [26:26] GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-only [23:23] GPIO5_EDGE_HIGH read-only [22:22] GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-only [19:19] GPIO4_EDGE_HIGH read-only [18:18] GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-only [15:15] GPIO3_EDGE_HIGH read-only [14:14] GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-only [11:11] GPIO2_EDGE_HIGH read-only [10:10] GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-only [7:7] GPIO1_EDGE_HIGH read-only [6:6] GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-only [3:3] GPIO0_EDGE_HIGH read-only [2:2] GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW PROC0_INTS0 0x00000000 0x0124 Interrupt status after masking & forcing for proc0 read-only [31:31] GPIO15_EDGE_HIGH read-only [30:30] GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-only [27:27] GPIO14_EDGE_HIGH read-only [26:26] GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-only [23:23] GPIO13_EDGE_HIGH read-only [22:22] GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-only [19:19] GPIO12_EDGE_HIGH read-only [18:18] GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-only [15:15] GPIO11_EDGE_HIGH read-only [14:14] GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-only [11:11] GPIO10_EDGE_HIGH read-only [10:10] GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-only [7:7] GPIO9_EDGE_HIGH read-only [6:6] GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-only [3:3] GPIO8_EDGE_HIGH read-only [2:2] GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW PROC0_INTS1 0x00000000 0x0128 Interrupt status after masking & forcing for proc0 read-only [31:31] GPIO23_EDGE_HIGH read-only [30:30] GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-only [27:27] GPIO22_EDGE_HIGH read-only [26:26] GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-only [23:23] GPIO21_EDGE_HIGH read-only [22:22] GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-only [19:19] GPIO20_EDGE_HIGH read-only [18:18] GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-only [15:15] GPIO19_EDGE_HIGH read-only [14:14] GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-only [11:11] GPIO18_EDGE_HIGH read-only [10:10] GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-only [7:7] GPIO17_EDGE_HIGH read-only [6:6] GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-only [3:3] GPIO16_EDGE_HIGH read-only [2:2] GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW PROC0_INTS2 0x00000000 0x012c Interrupt status after masking & forcing for proc0 read-only [23:23] GPIO29_EDGE_HIGH read-only [22:22] GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-only [19:19] GPIO28_EDGE_HIGH read-only [18:18] GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-only [15:15] GPIO27_EDGE_HIGH read-only [14:14] GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-only [11:11] GPIO26_EDGE_HIGH read-only [10:10] GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-only [7:7] GPIO25_EDGE_HIGH read-only [6:6] GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-only [3:3] GPIO24_EDGE_HIGH read-only [2:2] GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW PROC0_INTS3 0x00000000 0x0130 Interrupt Enable for proc1 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC1_INTE0 0x00000000 0x0134 Interrupt Enable for proc1 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC1_INTE1 0x00000000 0x0138 Interrupt Enable for proc1 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC1_INTE2 0x00000000 0x013c Interrupt Enable for proc1 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC1_INTE3 0x00000000 0x0140 Interrupt Force for proc1 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC1_INTF0 0x00000000 0x0144 Interrupt Force for proc1 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC1_INTF1 0x00000000 0x0148 Interrupt Force for proc1 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC1_INTF2 0x00000000 0x014c Interrupt Force for proc1 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC1_INTF3 0x00000000 0x0150 Interrupt status after masking & forcing for proc1 read-only [31:31] GPIO7_EDGE_HIGH read-only [30:30] GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-only [27:27] GPIO6_EDGE_HIGH read-only [26:26] GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-only [23:23] GPIO5_EDGE_HIGH read-only [22:22] GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-only [19:19] GPIO4_EDGE_HIGH read-only [18:18] GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-only [15:15] GPIO3_EDGE_HIGH read-only [14:14] GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-only [11:11] GPIO2_EDGE_HIGH read-only [10:10] GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-only [7:7] GPIO1_EDGE_HIGH read-only [6:6] GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-only [3:3] GPIO0_EDGE_HIGH read-only [2:2] GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW PROC1_INTS0 0x00000000 0x0154 Interrupt status after masking & forcing for proc1 read-only [31:31] GPIO15_EDGE_HIGH read-only [30:30] GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-only [27:27] GPIO14_EDGE_HIGH read-only [26:26] GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-only [23:23] GPIO13_EDGE_HIGH read-only [22:22] GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-only [19:19] GPIO12_EDGE_HIGH read-only [18:18] GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-only [15:15] GPIO11_EDGE_HIGH read-only [14:14] GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-only [11:11] GPIO10_EDGE_HIGH read-only [10:10] GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-only [7:7] GPIO9_EDGE_HIGH read-only [6:6] GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-only [3:3] GPIO8_EDGE_HIGH read-only [2:2] GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW PROC1_INTS1 0x00000000 0x0158 Interrupt status after masking & forcing for proc1 read-only [31:31] GPIO23_EDGE_HIGH read-only [30:30] GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-only [27:27] GPIO22_EDGE_HIGH read-only [26:26] GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-only [23:23] GPIO21_EDGE_HIGH read-only [22:22] GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-only [19:19] GPIO20_EDGE_HIGH read-only [18:18] GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-only [15:15] GPIO19_EDGE_HIGH read-only [14:14] GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-only [11:11] GPIO18_EDGE_HIGH read-only [10:10] GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-only [7:7] GPIO17_EDGE_HIGH read-only [6:6] GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-only [3:3] GPIO16_EDGE_HIGH read-only [2:2] GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW PROC1_INTS2 0x00000000 0x015c Interrupt status after masking & forcing for proc1 read-only [23:23] GPIO29_EDGE_HIGH read-only [22:22] GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-only [19:19] GPIO28_EDGE_HIGH read-only [18:18] GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-only [15:15] GPIO27_EDGE_HIGH read-only [14:14] GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-only [11:11] GPIO26_EDGE_HIGH read-only [10:10] GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-only [7:7] GPIO25_EDGE_HIGH read-only [6:6] GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-only [3:3] GPIO24_EDGE_HIGH read-only [2:2] GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW PROC1_INTS3 0x00000000 0x0160 Interrupt Enable for dormant_wake read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW DORMANT_WAKE_INTE0 0x00000000 0x0164 Interrupt Enable for dormant_wake read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW DORMANT_WAKE_INTE1 0x00000000 0x0168 Interrupt Enable for dormant_wake read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW DORMANT_WAKE_INTE2 0x00000000 0x016c Interrupt Enable for dormant_wake read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW DORMANT_WAKE_INTE3 0x00000000 0x0170 Interrupt Force for dormant_wake read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW DORMANT_WAKE_INTF0 0x00000000 0x0174 Interrupt Force for dormant_wake read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW DORMANT_WAKE_INTF1 0x00000000 0x0178 Interrupt Force for dormant_wake read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW DORMANT_WAKE_INTF2 0x00000000 0x017c Interrupt Force for dormant_wake read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW DORMANT_WAKE_INTF3 0x00000000 0x0180 Interrupt status after masking & forcing for dormant_wake read-only [31:31] GPIO7_EDGE_HIGH read-only [30:30] GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-only [27:27] GPIO6_EDGE_HIGH read-only [26:26] GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-only [23:23] GPIO5_EDGE_HIGH read-only [22:22] GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-only [19:19] GPIO4_EDGE_HIGH read-only [18:18] GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-only [15:15] GPIO3_EDGE_HIGH read-only [14:14] GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-only [11:11] GPIO2_EDGE_HIGH read-only [10:10] GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-only [7:7] GPIO1_EDGE_HIGH read-only [6:6] GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-only [3:3] GPIO0_EDGE_HIGH read-only [2:2] GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW DORMANT_WAKE_INTS0 0x00000000 0x0184 Interrupt status after masking & forcing for dormant_wake read-only [31:31] GPIO15_EDGE_HIGH read-only [30:30] GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-only [27:27] GPIO14_EDGE_HIGH read-only [26:26] GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-only [23:23] GPIO13_EDGE_HIGH read-only [22:22] GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-only [19:19] GPIO12_EDGE_HIGH read-only [18:18] GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-only [15:15] GPIO11_EDGE_HIGH read-only [14:14] GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-only [11:11] GPIO10_EDGE_HIGH read-only [10:10] GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-only [7:7] GPIO9_EDGE_HIGH read-only [6:6] GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-only [3:3] GPIO8_EDGE_HIGH read-only [2:2] GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW DORMANT_WAKE_INTS1 0x00000000 0x0188 Interrupt status after masking & forcing for dormant_wake read-only [31:31] GPIO23_EDGE_HIGH read-only [30:30] GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-only [27:27] GPIO22_EDGE_HIGH read-only [26:26] GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-only [23:23] GPIO21_EDGE_HIGH read-only [22:22] GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-only [19:19] GPIO20_EDGE_HIGH read-only [18:18] GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-only [15:15] GPIO19_EDGE_HIGH read-only [14:14] GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-only [11:11] GPIO18_EDGE_HIGH read-only [10:10] GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-only [7:7] GPIO17_EDGE_HIGH read-only [6:6] GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-only [3:3] GPIO16_EDGE_HIGH read-only [2:2] GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW DORMANT_WAKE_INTS2 0x00000000 0x018c Interrupt status after masking & forcing for dormant_wake read-only [23:23] GPIO29_EDGE_HIGH read-only [22:22] GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-only [19:19] GPIO28_EDGE_HIGH read-only [18:18] GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-only [15:15] GPIO27_EDGE_HIGH read-only [14:14] GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-only [11:11] GPIO26_EDGE_HIGH read-only [10:10] GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-only [7:7] GPIO25_EDGE_HIGH read-only [6:6] GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-only [3:3] GPIO24_EDGE_HIGH read-only [2:2] GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW DORMANT_WAKE_INTS3 0x00000000 32 1 0 0x1000 registers 0x40018000 IO_IRQ_QSPI 14 IO_QSPI 0x0000 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SCLK_STATUS 0x00000000 0x0004 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sclk 0 sio_30 5 null 31 FUNCSEL GPIO_QSPI_SCLK_CTRL 0x0000001f 0x0008 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SS_STATUS 0x00000000 0x000c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_ss_n 0 sio_31 5 null 31 FUNCSEL GPIO_QSPI_SS_CTRL 0x0000001f 0x0010 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD0_STATUS 0x00000000 0x0014 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd0 0 sio_32 5 null 31 FUNCSEL GPIO_QSPI_SD0_CTRL 0x0000001f 0x0018 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD1_STATUS 0x00000000 0x001c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd1 0 sio_33 5 null 31 FUNCSEL GPIO_QSPI_SD1_CTRL 0x0000001f 0x0020 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD2_STATUS 0x00000000 0x0024 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd2 0 sio_34 5 null 31 FUNCSEL GPIO_QSPI_SD2_CTRL 0x0000001f 0x0028 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD3_STATUS 0x00000000 0x002c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd3 0 sio_35 5 null 31 FUNCSEL GPIO_QSPI_SD3_CTRL 0x0000001f 0x0030 Raw Interrupts read-write [23:23] oneToClear GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] oneToClear GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] oneToClear GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] oneToClear GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] oneToClear GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] oneToClear GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] oneToClear GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] oneToClear GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] oneToClear GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] oneToClear GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] oneToClear GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] oneToClear GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW INTR 0x00000000 0x0034 Interrupt Enable for proc0 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC0_INTE 0x00000000 0x0038 Interrupt Force for proc0 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC0_INTF 0x00000000 0x003c Interrupt status after masking & forcing for proc0 read-only [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-only [22:22] GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-only [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-only [18:18] GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-only [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-only [14:14] GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-only [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-only [10:10] GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-only [7:7] GPIO_QSPI_SS_EDGE_HIGH read-only [6:6] GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-only [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-only [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC0_INTS 0x00000000 0x0040 Interrupt Enable for proc1 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC1_INTE 0x00000000 0x0044 Interrupt Force for proc1 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC1_INTF 0x00000000 0x0048 Interrupt status after masking & forcing for proc1 read-only [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-only [22:22] GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-only [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-only [18:18] GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-only [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-only [14:14] GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-only [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-only [10:10] GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-only [7:7] GPIO_QSPI_SS_EDGE_HIGH read-only [6:6] GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-only [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-only [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC1_INTS 0x00000000 0x004c Interrupt Enable for dormant_wake read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW DORMANT_WAKE_INTE 0x00000000 0x0050 Interrupt Force for dormant_wake read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW DORMANT_WAKE_INTF 0x00000000 0x0054 Interrupt status after masking & forcing for dormant_wake read-only [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-only [22:22] GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-only [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-only [18:18] GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-only [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-only [14:14] GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-only [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-only [10:10] GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-only [7:7] GPIO_QSPI_SS_EDGE_HIGH read-only [6:6] GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-only [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-only [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW DORMANT_WAKE_INTS 0x00000000 32 1 0 0x1000 registers 0x4001c000 PADS_BANK0 0x0000 Voltage select. Per bank control read-write [0:0] Set voltage to 3.3V (DVDD >= 2V5) 3v3 0 Set voltage to 1.8V (DVDD <= 1V8) 1v8 1 VOLTAGE_SELECT VOLTAGE_SELECT 0x00000000 0x0004 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO0 0x00000056 0x0008 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO1 0x00000056 0x000c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO2 0x00000056 0x0010 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO3 0x00000056 0x0014 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO4 0x00000056 0x0018 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO5 0x00000056 0x001c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO6 0x00000056 0x0020 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO7 0x00000056 0x0024 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO8 0x00000056 0x0028 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO9 0x00000056 0x002c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO10 0x00000056 0x0030 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO11 0x00000056 0x0034 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO12 0x00000056 0x0038 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO13 0x00000056 0x003c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO14 0x00000056 0x0040 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO15 0x00000056 0x0044 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO16 0x00000056 0x0048 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO17 0x00000056 0x004c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO18 0x00000056 0x0050 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO19 0x00000056 0x0054 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO20 0x00000056 0x0058 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO21 0x00000056 0x005c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO22 0x00000056 0x0060 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO23 0x00000056 0x0064 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO24 0x00000056 0x0068 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO25 0x00000056 0x006c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO26 0x00000056 0x0070 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO27 0x00000056 0x0074 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO28 0x00000056 0x0078 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO29 0x00000056 0x007c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST SWCLK 0x000000da 0x0080 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST SWD 0x0000005a 32 1 0 0x1000 registers 0x40020000 PADS_QSPI 0x0000 Voltage select. Per bank control read-write [0:0] Set voltage to 3.3V (DVDD >= 2V5) 3v3 0 Set voltage to 1.8V (DVDD <= 1V8) 1v8 1 VOLTAGE_SELECT VOLTAGE_SELECT 0x00000000 0x0004 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SCLK 0x00000056 0x0008 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD0 0x00000052 0x000c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD1 0x00000052 0x0010 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD2 0x00000052 0x0014 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD3 0x00000052 0x0018 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SS 0x0000005a 32 1 0 0x1000 registers 0x40024000 Controls the crystal oscillator XOSC 0x0000 Crystal Oscillator Control read-write [23:12] On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. DISABLE 3358 ENABLE 4011 ENABLE read-write [11:0] Frequency range. This resets to 0xAA0 and cannot be changed. 1_15MHZ 2720 RESERVED_1 2721 RESERVED_2 2722 RESERVED_3 2723 FREQ_RANGE CTRL 0x00000000 0x0004 Crystal Oscillator Status read-only [31:31] Oscillator is running and stable STABLE read-write [24:24] An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT oneToClear BADWRITE read-only [12:12] Oscillator is enabled but not necessarily running and stable, resets to 0 ENABLED read-only [1:0] The current frequency range setting, always reads 0 1_15MHZ 0 RESERVED_1 1 RESERVED_2 2 RESERVED_3 3 FREQ_RANGE STATUS 0x00000000 read-write 0x0008 Crystal Oscillator pause control\n This is used to save power by pausing the XOSC\n On power-up this field is initialised to WAKE\n An invalid write will also select WAKE\n WARNING: stop the PLLs before selecting dormant mode\n WARNING: setup the irq before selecting dormant mode DORMANT 0x00000000 0x000c Controls the startup delay read-write [20:20] Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. X4 read-write [13:0] in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. DELAY STARTUP 0x000000c4 0x001c A down counter running at the xosc frequency which counts to zero and stops.\n To start the counter write a non-zero value.\n Can be used for short software pauses when setting up time sensitive hardware. read-write [7:0] COUNT COUNT 0x00000000 32 1 0 0x1000 registers 0x40028000 PLL_SYS 0x0000 Control and Status\n GENERAL CONSTRAINTS:\n Reference clock frequency min=5MHz, max=800MHz\n Feedback divider min=16, max=320\n VCO frequency min=750MHz, max=1600MHz read-only [31:31] PLL is locked LOCK read-write [8:8] Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. BYPASS read-write [5:0] Divides the PLL input reference clock.\n Behaviour is undefined for div=0.\n PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. REFDIV CS 0x00000001 0x0004 Controls the PLL power modes. read-write [5:5] PLL VCO powerdown\n To save power set high when PLL output not required or bypass=1. VCOPD read-write [3:3] PLL post divider powerdown\n To save power set high when PLL output not required or bypass=1. POSTDIVPD read-write [2:2] PLL DSM powerdown\n Nothing is achieved by setting this low. DSMPD read-write [0:0] PLL powerdown\n To save power set high when PLL output not required. PD PWR 0x0000002d 0x0008 Feedback divisor\n (note: this PLL does not support fractional division) read-write [11:0] see ctrl reg description for constraints FBDIV_INT FBDIV_INT 0x00000000 0x000c Controls the PLL post dividers for the primary output\n (note: this PLL does not have a secondary output)\n the primary output is driven from VCO divided by postdiv1*postdiv2 read-write [18:16] divide by 1-7 POSTDIV1 read-write [14:12] divide by 1-7 POSTDIV2 PRIM 0x00077000 32 1 0x4002c000 PLL_USB 0 0x1000 registers 0x40030000 Register block for busfabric control signals and performance counters BUSCTRL 0x0000 Set the priority of each master for bus arbitration. read-write [12:12] 0 - low priority, 1 - high priority DMA_W read-write [8:8] 0 - low priority, 1 - high priority DMA_R read-write [4:4] 0 - low priority, 1 - high priority PROC1 read-write [0:0] 0 - low priority, 1 - high priority PROC0 BUS_PRIORITY 0x00000000 0x0004 Bus priority acknowledge read-only [0:0] Goes to 1 once all arbiters have registered the new global priority levels.\n Arbiters update their local priority when servicing a new nonsequential access.\n In normal circumstances this will happen almost immediately. BUS_PRIORITY_ACK BUS_PRIORITY_ACK 0x00000000 0x0008 Bus fabric performance counter 0 read-write [23:0] Busfabric saturating performance counter 0\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL0 oneToClear PERFCTR0 PERFCTR0 0x00000000 0x000c Bus fabric performance event select for PERFCTR0 read-write [4:0] Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 PERFSEL0 PERFSEL0 0x0000001f 0x0010 Bus fabric performance counter 1 read-write [23:0] Busfabric saturating performance counter 1\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL1 oneToClear PERFCTR1 PERFCTR1 0x00000000 0x0014 Bus fabric performance event select for PERFCTR1 read-write [4:0] Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 PERFSEL1 PERFSEL1 0x0000001f 0x0018 Bus fabric performance counter 2 read-write [23:0] Busfabric saturating performance counter 2\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL2 oneToClear PERFCTR2 PERFCTR2 0x00000000 0x001c Bus fabric performance event select for PERFCTR2 read-write [4:0] Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 PERFSEL2 PERFSEL2 0x0000001f 0x0020 Bus fabric performance counter 3 read-write [23:0] Busfabric saturating performance counter 3\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL3 oneToClear PERFCTR3 PERFCTR3 0x00000000 0x0024 Bus fabric performance event select for PERFCTR3 read-write [4:0] Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 PERFSEL3 PERFSEL3 0x0000001f 32 1 0 0x1000 registers 0x40034000 UART0_IRQ 20 UART0 0x0000 Data Register, UARTDR read-only [11:11] Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. OE read-only [10:10] Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. BE read-only [9:9] Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. PE read-only [8:8] Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. FE read-write [7:0] Receive (read) data character. Transmit (write) data character. DATA UARTDR 0x00000000 0x0004 Receive Status Register/Error Clear Register, UARTRSR/UARTECR read-write [3:3] Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. oneToClear OE read-write [2:2] Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. oneToClear BE read-write [1:1] Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. oneToClear PE read-write [0:0] Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. oneToClear FE UARTRSR 0x00000000 0x0018 Flag Register, UARTFR read-only [8:8] Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. RI read-only [7:7] Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. TXFE read-only [6:6] Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. RXFF read-only [5:5] Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. TXFF read-only [4:4] Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. RXFE read-only [3:3] UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. BUSY read-only [2:2] Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. DCD read-only [1:1] Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. DSR read-only [0:0] Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. CTS UARTFR 0x00000090 0x0020 IrDA Low-Power Counter Register, UARTILPR read-write [7:0] 8-bit low-power divisor value. These bits are cleared to 0 at reset. ILPDVSR UARTILPR 0x00000000 0x0024 Integer Baud Rate Register, UARTIBRD read-write [15:0] The integer baud rate divisor. These bits are cleared to 0 on reset. BAUD_DIVINT UARTIBRD 0x00000000 0x0028 Fractional Baud Rate Register, UARTFBRD read-write [5:0] The fractional baud rate divisor. These bits are cleared to 0 on reset. BAUD_DIVFRAC UARTFBRD 0x00000000 0x002c Line Control Register, UARTLCR_H read-write [7:7] Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. SPS read-write [6:5] Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. WLEN read-write [4:4] Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). FEN read-write [3:3] Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. STP2 read-write [2:2] Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. EPS read-write [1:1] Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. PEN read-write [0:0] Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. BRK UARTLCR_H 0x00000000 0x0030 Control Register, UARTCR read-write [15:15] CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. CTSEN read-write [14:14] RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. RTSEN read-write [13:13] This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). OUT2 read-write [12:12] This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). OUT1 read-write [11:11] Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. RTS read-write [10:10] Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. DTR read-write [9:9] Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. RXE read-write [8:8] Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. TXE read-write [7:7] Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. LBE read-write [2:2] SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. SIRLP read-write [1:1] SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. SIREN read-write [0:0] UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. UARTEN UARTCR 0x00000300 0x0034 Interrupt FIFO Level Select Register, UARTIFLS read-write [5:3] Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. RXIFLSEL read-write [2:0] Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. TXIFLSEL UARTIFLS 0x00000012 0x0038 Interrupt Mask Set/Clear Register, UARTIMSC read-write [10:10] Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. OEIM read-write [9:9] Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. BEIM read-write [8:8] Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. PEIM read-write [7:7] Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. FEIM read-write [6:6] Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. RTIM read-write [5:5] Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. TXIM read-write [4:4] Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. RXIM read-write [3:3] nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. DSRMIM read-write [2:2] nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. DCDMIM read-write [1:1] nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. CTSMIM read-write [0:0] nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. RIMIM UARTIMSC 0x00000000 0x003c Raw Interrupt Status Register, UARTRIS read-only [10:10] Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. OERIS read-only [9:9] Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. BERIS read-only [8:8] Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. PERIS read-only [7:7] Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. FERIS read-only [6:6] Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a RTRIS read-only [5:5] Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. TXRIS read-only [4:4] Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. RXRIS read-only [3:3] nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. DSRRMIS read-only [2:2] nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. DCDRMIS read-only [1:1] nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. CTSRMIS read-only [0:0] nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. RIRMIS UARTRIS 0x00000000 0x0040 Masked Interrupt Status Register, UARTMIS read-only [10:10] Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. OEMIS read-only [9:9] Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. BEMIS read-only [8:8] Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. PEMIS read-only [7:7] Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. FEMIS read-only [6:6] Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. RTMIS read-only [5:5] Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. TXMIS read-only [4:4] Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. RXMIS read-only [3:3] nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. DSRMMIS read-only [2:2] nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. DCDMMIS read-only [1:1] nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. CTSMMIS read-only [0:0] nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. RIMMIS UARTMIS 0x00000000 0x0044 Interrupt Clear Register, UARTICR read-write [10:10] Overrun error interrupt clear. Clears the UARTOEINTR interrupt. oneToClear OEIC read-write [9:9] Break error interrupt clear. Clears the UARTBEINTR interrupt. oneToClear BEIC read-write [8:8] Parity error interrupt clear. Clears the UARTPEINTR interrupt. oneToClear PEIC read-write [7:7] Framing error interrupt clear. Clears the UARTFEINTR interrupt. oneToClear FEIC read-write [6:6] Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. oneToClear RTIC read-write [5:5] Transmit interrupt clear. Clears the UARTTXINTR interrupt. oneToClear TXIC read-write [4:4] Receive interrupt clear. Clears the UARTRXINTR interrupt. oneToClear RXIC read-write [3:3] nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. oneToClear DSRMIC read-write [2:2] nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. oneToClear DCDMIC read-write [1:1] nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. oneToClear CTSMIC read-write [0:0] nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. oneToClear RIMIC UARTICR 0x00000000 0x0048 DMA Control Register, UARTDMACR read-write [2:2] DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. DMAONERR read-write [1:1] Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. TXDMAE read-write [0:0] Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. RXDMAE UARTDMACR 0x00000000 0x0fe0 UARTPeriphID0 Register read-only [7:0] These bits read back as 0x11 PARTNUMBER0 UARTPERIPHID0 0x00000011 0x0fe4 UARTPeriphID1 Register read-only [7:4] These bits read back as 0x1 DESIGNER0 read-only [3:0] These bits read back as 0x0 PARTNUMBER1 UARTPERIPHID1 0x00000010 0x0fe8 UARTPeriphID2 Register read-only [7:4] This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 REVISION read-only [3:0] These bits read back as 0x4 DESIGNER1 UARTPERIPHID2 0x00000034 0x0fec UARTPeriphID3 Register read-only [7:0] These bits read back as 0x00 CONFIGURATION UARTPERIPHID3 0x00000000 0x0ff0 UARTPCellID0 Register read-only [7:0] These bits read back as 0x0D UARTPCELLID0 UARTPCELLID0 0x0000000d 0x0ff4 UARTPCellID1 Register read-only [7:0] These bits read back as 0xF0 UARTPCELLID1 UARTPCELLID1 0x000000f0 0x0ff8 UARTPCellID2 Register read-only [7:0] These bits read back as 0x05 UARTPCELLID2 UARTPCELLID2 0x00000005 0x0ffc UARTPCellID3 Register read-only [7:0] These bits read back as 0xB1 UARTPCELLID3 UARTPCELLID3 0x000000b1 32 1 0x40038000 UART1_IRQ 21 UART1 0 0x1000 registers 0x4003c000 SPI0_IRQ 18 SPI0 0x0000 Control register 0, SSPCR0 on page 3-4 read-write [15:8] Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. SCR read-write [7:7] SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. SPH read-write [6:6] SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. SPO read-write [5:4] Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. FRF read-write [3:0] Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. DSS SSPCR0 0x00000000 0x0004 Control register 1, SSPCR1 on page 3-5 read-write [3:3] Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. SOD read-write [2:2] Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. MS read-write [1:1] Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. SSE read-write [0:0] Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. LBM SSPCR1 0x00000000 0x0008 Data register, SSPDR on page 3-6 read-write [15:0] Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. DATA SSPDR 0x00000000 0x000c Status register, SSPSR on page 3-7 read-only [4:4] PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. BSY read-only [3:3] Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. RFF read-only [2:2] Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. RNE read-only [1:1] Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. TNF read-only [0:0] Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. TFE SSPSR 0x00000003 0x0010 Clock prescale register, SSPCPSR on page 3-8 read-write [7:0] Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. CPSDVSR SSPCPSR 0x00000000 0x0014 Interrupt mask set or clear register, SSPIMSC on page 3-9 read-write [3:3] Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. TXIM read-write [2:2] Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. RXIM read-write [1:1] Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. RTIM read-write [0:0] Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. RORIM SSPIMSC 0x00000000 0x0018 Raw interrupt status register, SSPRIS on page 3-10 read-only [3:3] Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt TXRIS read-only [2:2] Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt RXRIS read-only [1:1] Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt RTRIS read-only [0:0] Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt RORRIS SSPRIS 0x00000008 0x001c Masked interrupt status register, SSPMIS on page 3-11 read-only [3:3] Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt TXMIS read-only [2:2] Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt RXMIS read-only [1:1] Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt RTMIS read-only [0:0] Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt RORMIS SSPMIS 0x00000000 0x0020 Interrupt clear register, SSPICR on page 3-11 read-write [1:1] Clears the SSPRTINTR interrupt oneToClear RTIC read-write [0:0] Clears the SSPRORINTR interrupt oneToClear RORIC SSPICR 0x00000000 0x0024 DMA control register, SSPDMACR on page 3-12 read-write [1:1] Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. TXDMAE read-write [0:0] Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. RXDMAE SSPDMACR 0x00000000 0x0fe0 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:0] These bits read back as 0x22 PARTNUMBER0 SSPPERIPHID0 0x00000022 0x0fe4 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:4] These bits read back as 0x1 DESIGNER0 read-only [3:0] These bits read back as 0x0 PARTNUMBER1 SSPPERIPHID1 0x00000010 0x0fe8 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:4] These bits return the peripheral revision REVISION read-only [3:0] These bits read back as 0x4 DESIGNER1 SSPPERIPHID2 0x00000034 0x0fec Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:0] These bits read back as 0x00 CONFIGURATION SSPPERIPHID3 0x00000000 0x0ff0 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0x0D SSPPCELLID0 SSPPCELLID0 0x0000000d 0x0ff4 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0xF0 SSPPCELLID1 SSPPCELLID1 0x000000f0 0x0ff8 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0x05 SSPPCELLID2 SSPPCELLID2 0x00000005 0x0ffc PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0xB1 SSPPCELLID3 SSPPCELLID3 0x000000b1 32 1 0x40040000 SPI1_IRQ 19 SPI1 0 0x0100 registers 0x40044000 DW_apb_i2c address block\n\n List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\n\n IC_ULTRA_FAST_MODE ................ 0x0\n IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n IC_UFM_SCL_LOW_COUNT .............. 0x0008\n IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n IC_TX_TL .......................... 0x0\n IC_TX_CMD_BLOCK ................... 0x1\n IC_HAS_DMA ........................ 0x1\n IC_HAS_ASYNC_FIFO ................. 0x0\n IC_SMBUS_ARP ...................... 0x0\n IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n IC_INTR_IO ........................ 0x1\n IC_MASTER_MODE .................... 0x1\n IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n IC_INTR_POL ....................... 0x1\n IC_OPTIONAL_SAR ................... 0x0\n IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n IC_DEFAULT_SLAVE_ADDR ............. 0x055\n IC_DEFAULT_HS_SPKLEN .............. 0x1\n IC_FS_SCL_HIGH_COUNT .............. 0x0006\n IC_HS_SCL_LOW_COUNT ............... 0x0008\n IC_DEVICE_ID_VALUE ................ 0x0\n IC_10BITADDR_MASTER ............... 0x0\n IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n IC_DEFAULT_FS_SPKLEN .............. 0x7\n IC_ADD_ENCODED_PARAMS ............. 0x0\n IC_DEFAULT_SDA_HOLD ............... 0x000001\n IC_DEFAULT_SDA_SETUP .............. 0x64\n IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n IC_CLOCK_PERIOD ................... 100\n IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n IC_RESTART_EN ..................... 0x1\n IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n IC_BUS_CLEAR_FEATURE .............. 0x0\n IC_CAP_LOADING .................... 100\n IC_FS_SCL_LOW_COUNT ............... 0x000d\n APB_DATA_WIDTH .................... 32\n IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n IC_SLV_DATA_NACK_ONLY ............. 0x1\n IC_10BITADDR_SLAVE ................ 0x0\n IC_CLK_TYPE ....................... 0x0\n IC_SMBUS_UDID_MSB ................. 0x0\n IC_SMBUS_SUSPEND_ALERT ............ 0x0\n IC_HS_SCL_HIGH_COUNT .............. 0x0006\n IC_SLV_RESTART_DET_EN ............. 0x1\n IC_SMBUS .......................... 0x0\n IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n IC_USE_COUNTS ..................... 0x0\n IC_RX_BUFFER_DEPTH ................ 16\n IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n IC_RX_FULL_HLD_BUS_EN ............. 0x1\n IC_SLAVE_DISABLE .................. 0x1\n IC_RX_TL .......................... 0x0\n IC_DEVICE_ID ...................... 0x0\n IC_HC_COUNT_VALUES ................ 0x0\n I2C_DYNAMIC_TAR_UPDATE ............ 0\n IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n IC_HS_MASTER_CODE ................. 0x1\n IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n IC_SS_SCL_HIGH_COUNT .............. 0x0028\n IC_SS_SCL_LOW_COUNT ............... 0x002f\n IC_MAX_SPEED_MODE ................. 0x2\n IC_STAT_FOR_CLK_STRETCH ........... 0x0\n IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n IC_DEFAULT_UFM_SPKLEN ............. 0x1\n IC_TX_BUFFER_DEPTH ................ 16 I2C0_IRQ 23 I2C0 0x0000 I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. read-only [10:10] Master issues the STOP_DET interrupt irrespective of whether master is active or not STOP_DET_IF_MASTER_ACTIVE read-write [9:9] This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n Reset value: 0x0. Overflow when RX_FIFO is full DISABLED 0 Hold bus when RX_FIFO is full ENABLED 1 RX_FIFO_FULL_HLD_CTRL read-write [8:8] This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0. Default behaviour of TX_EMPTY interrupt DISABLED 0 Controlled generation of TX_EMPTY interrupt ENABLED 1 TX_EMPTY_CTRL read-write [7:7] In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). slave issues STOP_DET intr always DISABLED 0 slave issues STOP_DET intr only if addressed ENABLED 1 STOP_DET_IFADDRESSED read-write [6:6] This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. Slave mode is enabled SLAVE_ENABLED 0 Slave mode is disabled SLAVE_DISABLED 1 IC_SLAVE_DISABLE read-write [5:5] Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n Reset value: ENABLED Master restart disabled DISABLED 0 Master restart enabled ENABLED 1 IC_RESTART_EN read-write [4:4] Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing Master 7Bit addressing mode ADDR_7BITS 0 Master 10Bit addressing mode ADDR_10BITS 1 IC_10BITADDR_MASTER read-write [3:3] When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. Slave 7Bit addressing ADDR_7BITS 0 Slave 10Bit addressing ADDR_10BITS 1 IC_10BITADDR_SLAVE read-write [2:1] These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n 1: standard mode (100 kbit/s)\n\n 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n 3: high speed mode (3.4 Mbit/s)\n\n Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 Standard Speed mode of operation STANDARD 1 Fast or Fast Plus mode of operation FAST 2 High Speed mode of operation HIGH 3 SPEED read-write [0:0] This bit controls whether the DW_apb_i2c master is enabled.\n\n NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. Master mode is disabled DISABLED 0 Master mode is enabled ENABLED 1 MASTER_MODE IC_CON 0x00000065 0x0004 I2C Target Address Register\n\n This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. read-write [11:11] This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 Disables programming of GENERAL_CALL or START_BYTE transmission DISABLED 0 Enables programming of GENERAL_CALL or START_BYTE transmission ENABLED 1 SPECIAL read-write [10:10] If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 GENERAL_CALL byte transmission GENERAL_CALL 0 START byte transmission START_BYTE 1 GC_OR_START read-write [9:0] This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. IC_TAR IC_TAR 0x00000055 0x0008 I2C Slave Address Register read-write [9:0] The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. IC_SAR IC_SAR 0x00000055 0x0010 I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n The size of the register changes as follows:\n\n Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. read-only [11:11] Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n Reset value : 0x0\n\n NOTE: In case of APB_DATA_WIDTH=8,\n\n 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. Sequential data byte received INACTIVE 0 Non sequential data byte received ACTIVE 1 FIRST_DATA_BYTE read-write [10:10] This bit controls whether a RESTART is issued before the byte is sent or received.\n\n 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n Reset value: 0x0 Don't Issue RESTART before this command DISABLE 0 Issue RESTART before this command ENABLE 1 clear RESTART read-write [9:9] This bit controls whether a STOP is issued after the byte is sent or received.\n\n - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 Don't Issue STOP after this command DISABLE 0 Issue STOP after this command ENABLE 1 clear STOP read-write [8:8] This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n Reset value: 0x0 Master Write Command WRITE 0 Master Read Command READ 1 clear CMD read-write [7:0] This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n Reset value: 0x0 DAT IC_DATA_CMD 0x00000000 0x0014 Standard Speed I2C Clock SCL High Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. IC_SS_SCL_HCNT IC_SS_SCL_HCNT 0x00000028 0x0018 Standard Speed I2C Clock SCL Low Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. IC_SS_SCL_LCNT IC_SS_SCL_LCNT 0x0000002f 0x001c Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. IC_FS_SCL_HCNT IC_FS_SCL_HCNT 0x00000006 0x0020 Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. IC_FS_SCL_LCNT IC_FS_SCL_LCNT 0x0000000d 0x002c I2C Interrupt Status Register\n\n Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. read-only [12:12] See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n Reset value: 0x0 R_RESTART_DET interrupt is inactive INACTIVE 0 R_RESTART_DET interrupt is active ACTIVE 1 R_RESTART_DET read-only [11:11] See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n Reset value: 0x0 R_GEN_CALL interrupt is inactive INACTIVE 0 R_GEN_CALL interrupt is active ACTIVE 1 R_GEN_CALL read-only [10:10] See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n Reset value: 0x0 R_START_DET interrupt is inactive INACTIVE 0 R_START_DET interrupt is active ACTIVE 1 R_START_DET read-only [9:9] See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n Reset value: 0x0 R_STOP_DET interrupt is inactive INACTIVE 0 R_STOP_DET interrupt is active ACTIVE 1 R_STOP_DET read-only [8:8] See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n Reset value: 0x0 R_ACTIVITY interrupt is inactive INACTIVE 0 R_ACTIVITY interrupt is active ACTIVE 1 R_ACTIVITY read-only [7:7] See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n Reset value: 0x0 R_RX_DONE interrupt is inactive INACTIVE 0 R_RX_DONE interrupt is active ACTIVE 1 R_RX_DONE read-only [6:6] See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n Reset value: 0x0 R_TX_ABRT interrupt is inactive INACTIVE 0 R_TX_ABRT interrupt is active ACTIVE 1 R_TX_ABRT read-only [5:5] See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n Reset value: 0x0 R_RD_REQ interrupt is inactive INACTIVE 0 R_RD_REQ interrupt is active ACTIVE 1 R_RD_REQ read-only [4:4] See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n Reset value: 0x0 R_TX_EMPTY interrupt is inactive INACTIVE 0 R_TX_EMPTY interrupt is active ACTIVE 1 R_TX_EMPTY read-only [3:3] See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n Reset value: 0x0 R_TX_OVER interrupt is inactive INACTIVE 0 R_TX_OVER interrupt is active ACTIVE 1 R_TX_OVER read-only [2:2] See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n Reset value: 0x0 R_RX_FULL interrupt is inactive INACTIVE 0 R_RX_FULL interrupt is active ACTIVE 1 R_RX_FULL read-only [1:1] See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n Reset value: 0x0 R_RX_OVER interrupt is inactive INACTIVE 0 R_RX_OVER interrupt is active ACTIVE 1 R_RX_OVER read-only [0:0] See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n Reset value: 0x0 RX_UNDER interrupt is inactive INACTIVE 0 RX_UNDER interrupt is active ACTIVE 1 R_RX_UNDER IC_INTR_STAT 0x00000000 0x0030 I2C Interrupt Mask Register.\n\n These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. read-write [12:12] This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 RESTART_DET interrupt is masked ENABLED 0 RESTART_DET interrupt is unmasked DISABLED 1 M_RESTART_DET read-write [11:11] This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 GEN_CALL interrupt is masked ENABLED 0 GEN_CALL interrupt is unmasked DISABLED 1 M_GEN_CALL read-write [10:10] This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 START_DET interrupt is masked ENABLED 0 START_DET interrupt is unmasked DISABLED 1 M_START_DET read-write [9:9] This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 STOP_DET interrupt is masked ENABLED 0 STOP_DET interrupt is unmasked DISABLED 1 M_STOP_DET read-write [8:8] This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 ACTIVITY interrupt is masked ENABLED 0 ACTIVITY interrupt is unmasked DISABLED 1 M_ACTIVITY read-write [7:7] This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_DONE interrupt is masked ENABLED 0 RX_DONE interrupt is unmasked DISABLED 1 M_RX_DONE read-write [6:6] This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 TX_ABORT interrupt is masked ENABLED 0 TX_ABORT interrupt is unmasked DISABLED 1 M_TX_ABRT read-write [5:5] This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RD_REQ interrupt is masked ENABLED 0 RD_REQ interrupt is unmasked DISABLED 1 M_RD_REQ read-write [4:4] This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 TX_EMPTY interrupt is masked ENABLED 0 TX_EMPTY interrupt is unmasked DISABLED 1 M_TX_EMPTY read-write [3:3] This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 TX_OVER interrupt is masked ENABLED 0 TX_OVER interrupt is unmasked DISABLED 1 M_TX_OVER read-write [2:2] This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_FULL interrupt is masked ENABLED 0 RX_FULL interrupt is unmasked DISABLED 1 M_RX_FULL read-write [1:1] This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_OVER interrupt is masked ENABLED 0 RX_OVER interrupt is unmasked DISABLED 1 M_RX_OVER read-write [0:0] This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_UNDER interrupt is masked ENABLED 0 RX_UNDER interrupt is unmasked DISABLED 1 M_RX_UNDER IC_INTR_MASK 0x000008ff 0x0034 I2C Raw Interrupt Status Register\n\n Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. read-only [12:12] Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n Reset value: 0x0 RESTART_DET interrupt is inactive INACTIVE 0 RESTART_DET interrupt is active ACTIVE 1 RESTART_DET read-only [11:11] Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n Reset value: 0x0 GEN_CALL interrupt is inactive INACTIVE 0 GEN_CALL interrupt is active ACTIVE 1 GEN_CALL read-only [10:10] Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n Reset value: 0x0 START_DET interrupt is inactive INACTIVE 0 START_DET interrupt is active ACTIVE 1 START_DET read-only [9:9] Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 STOP_DET interrupt is inactive INACTIVE 0 STOP_DET interrupt is active ACTIVE 1 STOP_DET read-only [8:8] This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n Reset value: 0x0 RAW_INTR_ACTIVITY interrupt is inactive INACTIVE 0 RAW_INTR_ACTIVITY interrupt is active ACTIVE 1 ACTIVITY read-only [7:7] When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n Reset value: 0x0 RX_DONE interrupt is inactive INACTIVE 0 RX_DONE interrupt is active ACTIVE 1 RX_DONE read-only [6:6] This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n Reset value: 0x0 TX_ABRT interrupt is inactive INACTIVE 0 TX_ABRT interrupt is active ACTIVE 1 TX_ABRT read-only [5:5] This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n Reset value: 0x0 RD_REQ interrupt is inactive INACTIVE 0 RD_REQ interrupt is active ACTIVE 1 RD_REQ read-only [4:4] The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n Reset value: 0x0. TX_EMPTY interrupt is inactive INACTIVE 0 TX_EMPTY interrupt is active ACTIVE 1 TX_EMPTY read-only [3:3] Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Reset value: 0x0 TX_OVER interrupt is inactive INACTIVE 0 TX_OVER interrupt is active ACTIVE 1 TX_OVER read-only [2:2] Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n Reset value: 0x0 RX_FULL interrupt is inactive INACTIVE 0 RX_FULL interrupt is active ACTIVE 1 RX_FULL read-only [1:1] Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n Reset value: 0x0 RX_OVER interrupt is inactive INACTIVE 0 RX_OVER interrupt is active ACTIVE 1 RX_OVER read-only [0:0] Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Reset value: 0x0 RX_UNDER interrupt is inactive INACTIVE 0 RX_UNDER interrupt is active ACTIVE 1 RX_UNDER IC_RAW_INTR_STAT 0x00000000 0x0038 I2C Receive FIFO Threshold Register read-write [7:0] Receive FIFO Threshold Level.\n\n Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. RX_TL IC_RX_TL 0x00000000 0x003c I2C Transmit FIFO Threshold Register read-write [7:0] Transmit FIFO Threshold Level.\n\n Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. TX_TL IC_TX_TL 0x00000000 0x0040 Clear Combined and Individual Interrupt Register read-only [0:0] Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n Reset value: 0x0 CLR_INTR IC_CLR_INTR 0x00000000 0x0044 Clear RX_UNDER Interrupt Register read-only [0:0] Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RX_UNDER IC_CLR_RX_UNDER 0x00000000 0x0048 Clear RX_OVER Interrupt Register read-only [0:0] Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RX_OVER IC_CLR_RX_OVER 0x00000000 0x004c Clear TX_OVER Interrupt Register read-only [0:0] Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_TX_OVER IC_CLR_TX_OVER 0x00000000 0x0050 Clear RD_REQ Interrupt Register read-only [0:0] Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RD_REQ IC_CLR_RD_REQ 0x00000000 0x0054 Clear TX_ABRT Interrupt Register read-only [0:0] Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n Reset value: 0x0 CLR_TX_ABRT IC_CLR_TX_ABRT 0x00000000 0x0058 Clear RX_DONE Interrupt Register read-only [0:0] Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RX_DONE IC_CLR_RX_DONE 0x00000000 0x005c Clear ACTIVITY Interrupt Register read-only [0:0] Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_ACTIVITY IC_CLR_ACTIVITY 0x00000000 0x0060 Clear STOP_DET Interrupt Register read-only [0:0] Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_STOP_DET IC_CLR_STOP_DET 0x00000000 0x0064 Clear START_DET Interrupt Register read-only [0:0] Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_START_DET IC_CLR_START_DET 0x00000000 0x0068 Clear GEN_CALL Interrupt Register read-only [0:0] Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_GEN_CALL IC_CLR_GEN_CALL 0x00000000 0x006c I2C Enable Register read-write [2:2] In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT Tx Command execution not blocked NOT_BLOCKED 0 Tx Command execution blocked BLOCKED 1 TX_CMD_BLOCK read-write [1:1] When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n Reset value: 0x0 ABORT operation not in progress DISABLE 0 ABORT operation in progress ENABLED 1 ABORT read-write [0:0] Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n Reset value: 0x0 I2C is disabled DISABLED 0 I2C is enabled ENABLED 1 ENABLE IC_ENABLE 0x00000000 0x0070 I2C Status Register\n\n This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 read-only [6:6] Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 Slave is idle IDLE 0 Slave not idle ACTIVE 1 SLV_ACTIVITY read-only [5:5] Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n Reset value: 0x0 Master is idle IDLE 0 Master not idle ACTIVE 1 MST_ACTIVITY read-only [4:4] Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 Rx FIFO not full NOT_FULL 0 Rx FIFO is full FULL 1 RFF read-only [3:3] Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 Rx FIFO is empty EMPTY 0 Rx FIFO not empty NOT_EMPTY 1 RFNE read-only [2:2] Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 Tx FIFO not empty NON_EMPTY 0 Tx FIFO is empty EMPTY 1 TFE read-only [1:1] Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 Tx FIFO is full FULL 0 Tx FIFO not full NOT_FULL 1 TFNF read-only [0:0] I2C Activity Status. Reset value: 0x0 I2C is idle INACTIVE 0 I2C is active ACTIVE 1 ACTIVITY IC_STATUS 0x00000006 0x0074 I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. read-only [4:0] Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n Reset value: 0x0 TXFLR IC_TXFLR 0x00000000 0x0078 I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. read-only [4:0] Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n Reset value: 0x0 RXFLR IC_RXFLR 0x00000000 0x007c I2C SDA Hold Time Length Register\n\n The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n Writes to this register succeed only when IC_ENABLE[0]=0.\n\n The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. read-write [23:16] Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n Reset value: IC_DEFAULT_SDA_HOLD[23:16]. IC_SDA_RX_HOLD read-write [15:0] Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n Reset value: IC_DEFAULT_SDA_HOLD[15:0]. IC_SDA_TX_HOLD IC_SDA_HOLD 0x00000001 0x0080 I2C Transmit Abort Source Register\n\n This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. read-only [31:23] This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter TX_FLUSH_CNT read-only [16:16] This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter Transfer abort detected by master- scenario not present ABRT_USER_ABRT_VOID 0 Transfer abort detected by master ABRT_USER_ABRT_GENERATED 1 ABRT_USER_ABRT read-only [15:15] 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter Slave trying to transmit to remote master in read mode- scenario not present ABRT_SLVRD_INTX_VOID 0 Slave trying to transmit to remote master in read mode ABRT_SLVRD_INTX_GENERATED 1 ABRT_SLVRD_INTX read-only [14:14] This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter Slave lost arbitration to remote master- scenario not present ABRT_SLV_ARBLOST_VOID 0 Slave lost arbitration to remote master ABRT_SLV_ARBLOST_GENERATED 1 ABRT_SLV_ARBLOST read-only [13:13] This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter Slave flushes existing data in TX-FIFO upon getting read command- scenario not present ABRT_SLVFLUSH_TXFIFO_VOID 0 Slave flushes existing data in TX-FIFO upon getting read command ABRT_SLVFLUSH_TXFIFO_GENERATED 1 ABRT_SLVFLUSH_TXFIFO read-only [12:12] This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter Master or Slave-Transmitter lost arbitration- scenario not present ABRT_LOST_VOID 0 Master or Slave-Transmitter lost arbitration ABRT_LOST_GENERATED 1 ARB_LOST read-only [11:11] This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver User initiating master operation when MASTER disabled- scenario not present ABRT_MASTER_DIS_VOID 0 User initiating master operation when MASTER disabled ABRT_MASTER_DIS_GENERATED 1 ABRT_MASTER_DIS read-only [10:10] This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Receiver Master not trying to read in 10Bit addressing mode when RESTART disabled ABRT_10B_RD_VOID 0 Master trying to read in 10Bit addressing mode when RESTART disabled ABRT_10B_RD_GENERATED 1 ABRT_10B_RD_NORSTRT read-only [9:9] To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master User trying to send START byte when RESTART disabled- scenario not present ABRT_SBYTE_NORSTRT_VOID 0 User trying to send START byte when RESTART disabled ABRT_SBYTE_NORSTRT_GENERATED 1 ABRT_SBYTE_NORSTRT read-only [8:8] This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver User trying to switch Master to HS mode when RESTART disabled- scenario not present ABRT_HS_NORSTRT_VOID 0 User trying to switch Master to HS mode when RESTART disabled ABRT_HS_NORSTRT_GENERATED 1 ABRT_HS_NORSTRT read-only [7:7] This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master ACK detected for START byte- scenario not present ABRT_SBYTE_ACKDET_VOID 0 ACK detected for START byte ABRT_SBYTE_ACKDET_GENERATED 1 ABRT_SBYTE_ACKDET read-only [6:6] This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master HS Master code ACKed in HS Mode- scenario not present ABRT_HS_ACK_VOID 0 HS Master code ACKed in HS Mode ABRT_HS_ACK_GENERATED 1 ABRT_HS_ACKDET read-only [5:5] This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter GCALL is followed by read from bus-scenario not present ABRT_GCALL_READ_VOID 0 GCALL is followed by read from bus ABRT_GCALL_READ_GENERATED 1 ABRT_GCALL_READ read-only [4:4] This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter GCALL not ACKed by any slave-scenario not present ABRT_GCALL_NOACK_VOID 0 GCALL not ACKed by any slave ABRT_GCALL_NOACK_GENERATED 1 ABRT_GCALL_NOACK read-only [3:3] This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter Transmitted data non-ACKed by addressed slave-scenario not present ABRT_TXDATA_NOACK_VOID 0 Transmitted data not ACKed by addressed slave ABRT_TXDATA_NOACK_GENERATED 1 ABRT_TXDATA_NOACK read-only [2:2] This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver This abort is not generated INACTIVE 0 Byte 2 of 10Bit Address not ACKed by any slave ACTIVE 1 ABRT_10ADDR2_NOACK read-only [1:1] This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver This abort is not generated INACTIVE 0 Byte 1 of 10Bit Address not ACKed by any slave ACTIVE 1 ABRT_10ADDR1_NOACK read-only [0:0] This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver This abort is not generated INACTIVE 0 This abort is generated because of NOACK for 7-bit address ACTIVE 1 ABRT_7B_ADDR_NOACK IC_TX_ABRT_SOURCE 0x00000000 0x0084 Generate Slave Data NACK Register\n\n The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. read-write [0:0] Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 Slave receiver generates NACK normally DISABLED 0 Slave receiver generates NACK upon data reception only ENABLED 1 NACK IC_SLV_DATA_NACK_ONLY 0x00000000 0x0088 DMA Control Register\n\n The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. read-write [1:1] Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 transmit FIFO DMA channel disabled DISABLED 0 Transmit FIFO DMA channel enabled ENABLED 1 TDMAE read-write [0:0] Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 Receive FIFO DMA channel disabled DISABLED 0 Receive FIFO DMA channel enabled ENABLED 1 RDMAE IC_DMA_CR 0x00000000 0x008c DMA Transmit Data Level Register read-write [3:0] Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n Reset value: 0x0 DMATDL IC_DMA_TDLR 0x00000000 0x0090 I2C Receive Data Level Register read-write [3:0] Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n Reset value: 0x0 DMARDL IC_DMA_RDLR 0x00000000 0x0094 I2C SDA Setup Register\n\n This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. read-write [7:0] SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. SDA_SETUP IC_SDA_SETUP 0x00000064 0x0098 I2C ACK General Call Register\n\n The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n This register is applicable only when the DW_apb_i2c is in slave mode. read-write [0:0] ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). Generate NACK for a General Call DISABLED 0 Generate ACK for a General Call ENABLED 1 ACK_GEN_CALL IC_ACK_GENERAL_CALL 0x00000001 0x009c I2C Enable Status Register\n\n The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. read-only [2:2] Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n Reset value: 0x0 Slave RX Data is not lost INACTIVE 0 Slave RX Data is lost ACTIVE 1 SLV_RX_DATA_LOST read-only [1:1] Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n OR,\n\n (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n Reset value: 0x0 Slave is disabled when it is idle INACTIVE 0 Slave is disabled when it is active ACTIVE 1 SLV_DISABLED_WHILE_BUSY read-only [0:0] ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n Reset value: 0x0 I2C disabled DISABLED 0 I2C enabled ENABLED 1 IC_EN IC_ENABLE_STATUS 0x00000000 0x00a0 I2C SS, FS or FM+ spike suppression limit\n\n This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. read-write [7:0] This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. IC_FS_SPKLEN IC_FS_SPKLEN 0x00000007 0x00a8 Clear RESTART_DET Interrupt Register read-only [0:0] Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RESTART_DET IC_CLR_RESTART_DET 0x00000000 0x00f4 Component Parameter Register 1\n\n Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters read-only [23:16] TX Buffer Depth = 16 TX_BUFFER_DEPTH read-only [15:8] RX Buffer Depth = 16 RX_BUFFER_DEPTH read-only [7:7] Encoded parameters not visible ADD_ENCODED_PARAMS read-only [6:6] DMA handshaking signals are enabled HAS_DMA read-only [5:5] COMBINED Interrupt outputs INTR_IO read-only [4:4] Programmable count values for each mode. HC_COUNT_VALUES read-only [3:2] MAX SPEED MODE = FAST MODE MAX_SPEED_MODE read-only [1:0] APB data bus width is 32 bits APB_DATA_WIDTH IC_COMP_PARAM_1 0x00000000 0x00f8 I2C Component Version Register read-only [31:0] IC_COMP_VERSION IC_COMP_VERSION 0x3230312a 0x00fc I2C Component Type Register read-only [31:0] Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. IC_COMP_TYPE IC_COMP_TYPE 0x44570140 32 1 0x40048000 I2C1_IRQ 24 I2C1 0 0x1000 registers 0x4004c000 Control and data interface to SAR ADC ADC_IRQ_FIFO 22 ADC 0x0000 ADC Control and Status read-write [20:16] Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n The first channel to be sampled will be the one currently indicated by AINSEL.\n AINSEL will be updated after each conversion with the newly-selected channel. RROBIN read-write [14:12] Select analog mux input. Updated automatically in round-robin mode. AINSEL read-write [10:10] Some past ADC conversion encountered an error. Write 1 to clear. oneToClear ERR_STICKY read-only [9:9] The most recent ADC conversion encountered an error; result is undefined or noisy. ERR read-only [8:8] 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n 0 whilst conversion in progress. READY read-write [3:3] Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. START_MANY read-write [2:2] Start a single conversion. Self-clearing. Ignored if start_many is asserted. clear START_ONCE read-write [1:1] Power on temperature sensor. 1 - enabled. 0 - disabled. TS_EN read-write [0:0] Power on ADC and enable its clock.\n 1 - enabled. 0 - disabled. EN CS 0x00000000 0x0004 Result of most recent ADC conversion read-only [11:0] RESULT RESULT 0x00000000 0x0008 FIFO control and status read-write [27:24] DREQ/IRQ asserted when level >= threshold THRESH read-only [19:16] The number of conversion results currently waiting in the FIFO LEVEL read-write [11:11] 1 if the FIFO has been overflowed. Write 1 to clear. oneToClear OVER read-write [10:10] 1 if the FIFO has been underflowed. Write 1 to clear. oneToClear UNDER read-only [9:9] FULL read-only [8:8] EMPTY read-write [3:3] If 1: assert DMA requests when FIFO contains data DREQ_EN read-write [2:2] If 1: conversion error bit appears in the FIFO alongside the result ERR read-write [1:1] If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. SHIFT read-write [0:0] If 1: write result to the FIFO after each conversion. EN FCS 0x00000000 0x000c Conversion result FIFO read-only [15:15] 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. ERR read-only [11:0] VAL FIFO 0x00000000 0x0010 Clock divider. If non-zero, CS_START_MANY will start conversions\n at regular intervals rather than back-to-back.\n The divider is reset when either of these fields are written.\n Total period is 1 + INT + FRAC / 256 read-write [23:8] Integer part of clock divisor. INT read-write [7:0] Fractional part of clock divisor. First-order delta-sigma. FRAC DIV 0x00000000 0x0014 Raw Interrupts read-only [0:0] Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field. FIFO INTR 0x00000000 0x0018 Interrupt Enable read-write [0:0] Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field. FIFO INTE 0x00000000 0x001c Interrupt Force read-write [0:0] Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field. FIFO INTF 0x00000000 0x0020 Interrupt status after masking & forcing read-only [0:0] Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field. FIFO INTS 0x00000000 32 2 0 0x1000 registers 0x40050000 Simple PWM PWM_IRQ_WRAP 4 PWM 0x0000 Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH0_CSR 0x00000000 0x0004 INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH0_DIV 0x00000010 0x0008 Direct access to the PWM counter read-write [15:0] CH0_CTR CH0_CTR 0x00000000 0x000c Counter compare values read-write [31:16] B read-write [15:0] A CH0_CC 0x00000000 0x0010 Counter wrap value read-write [15:0] CH0_TOP CH0_TOP 0x0000ffff 0x0014 Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH1_CSR 0x00000000 0x0018 INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH1_DIV 0x00000010 0x001c Direct access to the PWM counter read-write [15:0] CH1_CTR CH1_CTR 0x00000000 0x0020 Counter compare values read-write [31:16] B read-write [15:0] A CH1_CC 0x00000000 0x0024 Counter wrap value read-write [15:0] CH1_TOP CH1_TOP 0x0000ffff 0x0028 Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH2_CSR 0x00000000 0x002c INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH2_DIV 0x00000010 0x0030 Direct access to the PWM counter read-write [15:0] CH2_CTR CH2_CTR 0x00000000 0x0034 Counter compare values read-write [31:16] B read-write [15:0] A CH2_CC 0x00000000 0x0038 Counter wrap value read-write [15:0] CH2_TOP CH2_TOP 0x0000ffff 0x003c Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH3_CSR 0x00000000 0x0040 INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH3_DIV 0x00000010 0x0044 Direct access to the PWM counter read-write [15:0] CH3_CTR CH3_CTR 0x00000000 0x0048 Counter compare values read-write [31:16] B read-write [15:0] A CH3_CC 0x00000000 0x004c Counter wrap value read-write [15:0] CH3_TOP CH3_TOP 0x0000ffff 0x0050 Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH4_CSR 0x00000000 0x0054 INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH4_DIV 0x00000010 0x0058 Direct access to the PWM counter read-write [15:0] CH4_CTR CH4_CTR 0x00000000 0x005c Counter compare values read-write [31:16] B read-write [15:0] A CH4_CC 0x00000000 0x0060 Counter wrap value read-write [15:0] CH4_TOP CH4_TOP 0x0000ffff 0x0064 Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH5_CSR 0x00000000 0x0068 INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH5_DIV 0x00000010 0x006c Direct access to the PWM counter read-write [15:0] CH5_CTR CH5_CTR 0x00000000 0x0070 Counter compare values read-write [31:16] B read-write [15:0] A CH5_CC 0x00000000 0x0074 Counter wrap value read-write [15:0] CH5_TOP CH5_TOP 0x0000ffff 0x0078 Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH6_CSR 0x00000000 0x007c INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH6_DIV 0x00000010 0x0080 Direct access to the PWM counter read-write [15:0] CH6_CTR CH6_CTR 0x00000000 0x0084 Counter compare values read-write [31:16] B read-write [15:0] A CH6_CC 0x00000000 0x0088 Counter wrap value read-write [15:0] CH6_TOP CH6_TOP 0x0000ffff 0x008c Control and status register read-write [7:7] Advance the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running\n at less than full speed (div_int + div_frac / 16 > 1) clear PH_ADV read-write [6:6] Retard the phase of the counter by 1 count, while it is running.\n Self-clearing. Write a 1, and poll until low. Counter must be running. clear PH_RET read-write [5:4] Free-running counting at rate dictated by fractional divider div 0 Fractional divider operation is gated by the PWM B pin. level 1 Counter advances with each rising edge of the PWM B pin. rise 2 Counter advances with each falling edge of the PWM B pin. fall 3 DIVMODE read-write [3:3] Invert output B B_INV read-write [2:2] Invert output A A_INV read-write [1:1] 1: Enable phase-correct modulation. 0: Trailing-edge PH_CORRECT read-write [0:0] Enable the PWM channel. EN CH7_CSR 0x00000000 0x0090 INT and FRAC form a fixed-point fractional number.\n Counting rate is system clock frequency divided by this number.\n Fractional division uses simple 1st-order sigma-delta. read-write [11:4] INT read-write [3:0] FRAC CH7_DIV 0x00000010 0x0094 Direct access to the PWM counter read-write [15:0] CH7_CTR CH7_CTR 0x00000000 0x0098 Counter compare values read-write [31:16] B read-write [15:0] A CH7_CC 0x00000000 0x009c Counter wrap value read-write [15:0] CH7_TOP CH7_TOP 0x0000ffff 0x00a0 This register aliases the CSR_EN bits for all channels.\n Writing to this register allows multiple channels to be enabled\n or disabled simultaneously, so they can run in perfect sync.\n For each channel, there is only one physical EN register bit,\n which can be accessed through here or CHx_CSR. read-write [7:7] CH7 read-write [6:6] CH6 read-write [5:5] CH5 read-write [4:4] CH4 read-write [3:3] CH3 read-write [2:2] CH2 read-write [1:1] CH1 read-write [0:0] CH0 EN 0x00000000 0x00a4 Raw Interrupts read-write [7:7] oneToClear CH7 read-write [6:6] oneToClear CH6 read-write [5:5] oneToClear CH5 read-write [4:4] oneToClear CH4 read-write [3:3] oneToClear CH3 read-write [2:2] oneToClear CH2 read-write [1:1] oneToClear CH1 read-write [0:0] oneToClear CH0 INTR 0x00000000 0x00a8 Interrupt Enable read-write [7:7] CH7 read-write [6:6] CH6 read-write [5:5] CH5 read-write [4:4] CH4 read-write [3:3] CH3 read-write [2:2] CH2 read-write [1:1] CH1 read-write [0:0] CH0 INTE 0x00000000 0x00ac Interrupt Force read-write [7:7] CH7 read-write [6:6] CH6 read-write [5:5] CH5 read-write [4:4] CH4 read-write [3:3] CH3 read-write [2:2] CH2 read-write [1:1] CH1 read-write [0:0] CH0 INTF 0x00000000 0x00b0 Interrupt status after masking & forcing read-only [7:7] CH7 read-only [6:6] CH6 read-only [5:5] CH5 read-only [4:4] CH4 read-only [3:3] CH3 read-only [2:2] CH2 read-only [1:1] CH1 read-only [0:0] CH0 INTS 0x00000000 32 1 0 0x1000 registers 0x40054000 Controls time and alarms\n time is a 64 bit value indicating the time in usec since power-on\n timeh is the top 32 bits of time & timel is the bottom 32 bits\n to change time write to timelw before timehw\n to read time read from timelr before timehr\n An alarm is set by setting alarm_enable and writing to the corresponding alarm register\n When an alarm is pending, the corresponding alarm_running signal will be high\n An alarm can be cancelled before it has finished by clearing the alarm_enable\n When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\n To clear the interrupt write a 1 to the corresponding alarm_irq TIMER_IRQ_0 0 TIMER_IRQ_1 1 TIMER_IRQ_2 2 TIMER_IRQ_3 3 TIMER write-only 0x0000 Write to bits 63:32 of time\n always write timelw before timehw TIMEHW 0x00000000 write-only 0x0004 Write to bits 31:0 of time\n writes do not get copied to time until timehw is written TIMELW 0x00000000 read-only 0x0008 Read from bits 63:32 of time\n always read timelr before timehr TIMEHR 0x00000000 read-only 0x000c Read from bits 31:0 of time TIMELR 0x00000000 read-write 0x0010 Arm alarm 0, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register. ALARM0 0x00000000 read-write 0x0014 Arm alarm 1, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register. ALARM1 0x00000000 read-write 0x0018 Arm alarm 2, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register. ALARM2 0x00000000 read-write 0x001c Arm alarm 3, and configure the time it will fire.\n Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n The alarm will disarm itself once it fires, and can\n be disarmed early using the ARMED status register. ALARM3 0x00000000 0x0020 Indicates the armed/disarmed status of each alarm.\n A write to the corresponding ALARMx register arms the alarm.\n Alarms automatically disarm upon firing, but writing ones here\n will disarm immediately without waiting to fire. read-write [3:0] oneToClear ARMED ARMED 0x00000000 read-only 0x0024 Raw read from bits 63:32 of time (no side effects) TIMERAWH 0x00000000 read-only 0x0028 Raw read from bits 31:0 of time (no side effects) TIMERAWL 0x00000000 0x002c Set bits high to enable pause when the corresponding debug ports are active read-write [2:2] Pause when processor 1 is in debug mode DBG1 read-write [1:1] Pause when processor 0 is in debug mode DBG0 DBGPAUSE 0x00000007 0x0030 Set high to pause the timer read-write [0:0] PAUSE PAUSE 0x00000000 0x0034 Raw Interrupts read-write [3:3] oneToClear ALARM_3 read-write [2:2] oneToClear ALARM_2 read-write [1:1] oneToClear ALARM_1 read-write [0:0] oneToClear ALARM_0 INTR 0x00000000 0x0038 Interrupt Enable read-write [3:3] ALARM_3 read-write [2:2] ALARM_2 read-write [1:1] ALARM_1 read-write [0:0] ALARM_0 INTE 0x00000000 0x003c Interrupt Force read-write [3:3] ALARM_3 read-write [2:2] ALARM_2 read-write [1:1] ALARM_1 read-write [0:0] ALARM_0 INTF 0x00000000 0x0040 Interrupt status after masking & forcing read-only [3:3] ALARM_3 read-only [2:2] ALARM_2 read-only [1:1] ALARM_1 read-only [0:0] ALARM_0 INTS 0x00000000 32 1 0 0x1000 registers 0x40058000 WATCHDOG 0x0000 Watchdog control\n The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\n The watchdog can be triggered in software. read-write [31:31] Trigger a watchdog reset clear TRIGGER read-write [30:30] When not enabled the watchdog timer is paused ENABLE read-write [26:26] Pause the watchdog timer when processor 1 is in debug mode PAUSE_DBG1 read-write [25:25] Pause the watchdog timer when processor 0 is in debug mode PAUSE_DBG0 read-write [24:24] Pause the watchdog timer when JTAG is accessing the bus fabric PAUSE_JTAG read-only [23:0] Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered TIME CTRL 0x07000000 0x0004 Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). write-only [23:0] LOAD LOAD 0x00000000 0x0008 Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. read-only [1:1] FORCE read-only [0:0] TIMER REASON 0x00000000 read-write 0x000c Scratch register. Information persists through soft reset of the chip. SCRATCH0 0x00000000 read-write 0x0010 Scratch register. Information persists through soft reset of the chip. SCRATCH1 0x00000000 read-write 0x0014 Scratch register. Information persists through soft reset of the chip. SCRATCH2 0x00000000 read-write 0x0018 Scratch register. Information persists through soft reset of the chip. SCRATCH3 0x00000000 read-write 0x001c Scratch register. Information persists through soft reset of the chip. SCRATCH4 0x00000000 read-write 0x0020 Scratch register. Information persists through soft reset of the chip. SCRATCH5 0x00000000 read-write 0x0024 Scratch register. Information persists through soft reset of the chip. SCRATCH6 0x00000000 read-write 0x0028 Scratch register. Information persists through soft reset of the chip. SCRATCH7 0x00000000 0x002c Controls the tick generator read-only [19:11] Count down timer: the remaining number clk_tick cycles before the next tick is generated. COUNT read-only [10:10] Is the tick generator running? RUNNING read-write [9:9] start / stop tick generation ENABLE read-write [8:0] Total number of clk_tick cycles before the next tick. CYCLES TICK 0x00000200 32 1 0 0x1000 registers 0x4005c000 Register block to control RTC RTC_IRQ 25 RTC 0x0000 Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. read-write [15:0] CLKDIV_M1 CLKDIV_M1 0x00000000 0x0004 RTC setup register 0 read-write [23:12] Year YEAR read-write [11:8] Month (1..12) MONTH read-write [4:0] Day of the month (1..31) DAY SETUP_0 0x00000000 0x0008 RTC setup register 1 read-write [26:24] Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 DOTW read-write [20:16] Hours HOUR read-write [13:8] Minutes MIN read-write [5:0] Seconds SEC SETUP_1 0x00000000 0x000c RTC Control and status read-write [8:8] If set, leapyear is forced off.\n Useful for years divisible by 100 but not by 400 FORCE_NOTLEAPYEAR read-write [4:4] Load RTC clear LOAD read-only [1:1] RTC enabled (running) RTC_ACTIVE read-write [0:0] Enable RTC RTC_ENABLE CTRL 0x00000000 0x0010 Interrupt setup register 0 read-only [29:29] MATCH_ACTIVE read-write [28:28] Global match enable. Don't change any other value while this one is enabled MATCH_ENA read-write [26:26] Enable year matching YEAR_ENA read-write [25:25] Enable month matching MONTH_ENA read-write [24:24] Enable day matching DAY_ENA read-write [23:12] Year YEAR read-write [11:8] Month (1..12) MONTH read-write [4:0] Day of the month (1..31) DAY IRQ_SETUP_0 0x00000000 0x0014 Interrupt setup register 1 read-write [31:31] Enable day of the week matching DOTW_ENA read-write [30:30] Enable hour matching HOUR_ENA read-write [29:29] Enable minute matching MIN_ENA read-write [28:28] Enable second matching SEC_ENA read-write [26:24] Day of the week DOTW read-write [20:16] Hours HOUR read-write [13:8] Minutes MIN read-write [5:0] Seconds SEC IRQ_SETUP_1 0x00000000 0x0018 RTC register 1. read-only [23:12] Year YEAR read-only [11:8] Month (1..12) MONTH read-only [4:0] Day of the month (1..31) DAY RTC_1 0x00000000 0x001c RTC register 0\n Read this before RTC 1! read-only [26:24] Day of the week DOTW read-only [20:16] Hours HOUR read-only [13:8] Minutes MIN read-only [5:0] Seconds SEC RTC_0 0x00000000 0x0020 Raw Interrupts read-only [0:0] RTC INTR 0x00000000 0x0024 Interrupt Enable read-write [0:0] RTC INTE 0x00000000 0x0028 Interrupt Force read-write [0:0] RTC INTF 0x00000000 0x002c Interrupt status after masking & forcing read-only [0:0] RTC INTS 0x00000000 32 1 0 0x1000 registers 0x40060000 ROSC 0x0000 Ring Oscillator control read-write [23:12] On power-up this field is initialised to ENABLE\n The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\n The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. DISABLE 3358 ENABLE 4011 ENABLE read-write [11:0] Controls the number of delay stages in the ROSC ring\n LOW uses stages 0 to 7\n MEDIUM uses stages 0 to 5\n HIGH uses stages 0 to 3\n TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\n The clock output will not glitch when changing the range up one step at a time\n The clock output will glitch when changing the range down\n Note: the values here are gray coded which is why HIGH comes before TOOHIGH LOW 4004 MEDIUM 4005 HIGH 4007 TOOHIGH 4006 FREQ_RANGE CTRL 0x00000aa0 0x0004 The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\n The drive strength has 4 levels determined by the number of bits set\n Increasing the number of bits set increases the drive strength and increases the oscillation frequency\n 0 bits set is the default drive strength\n 1 bit set doubles the drive strength\n 2 bits set triples drive strength\n 3 bits set quadruples drive strength read-write [31:16] Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0 PASS 38550 PASSWD read-write [14:12] Stage 3 drive strength DS3 read-write [10:8] Stage 2 drive strength DS2 read-write [6:4] Stage 1 drive strength DS1 read-write [2:0] Stage 0 drive strength DS0 FREQA 0x00000000 0x0008 For a detailed description see freqa register read-write [31:16] Set to 0x9696 to apply the settings\n Any other value in this field will set all drive strengths to 0 PASS 38550 PASSWD read-write [14:12] Stage 7 drive strength DS7 read-write [10:8] Stage 6 drive strength DS6 read-write [6:4] Stage 5 drive strength DS5 read-write [2:0] Stage 4 drive strength DS4 FREQB 0x00000000 read-write 0x000c Ring Oscillator pause control\n This is used to save power by pausing the ROSC\n On power-up this field is initialised to WAKE\n An invalid write will also select WAKE\n Warning: setup the irq before selecting dormant mode DORMANT 0x00000000 0x0010 Controls the output divider read-write [11:0] set to 0xaa0 + div where\n div = 0 divides by 32\n div = 1-31 divides by div\n any other value sets div=31\n this register resets to div=16 PASS 2720 DIV DIV 0x00000000 0x0014 Controls the phase shifted output read-write [11:4] set to 0xaa\n any other value enables the output with shift=0 PASSWD read-write [3:3] enable the phase-shifted output\n this can be changed on-the-fly ENABLE read-write [2:2] invert the phase-shifted output\n this is ignored when div=1 FLIP read-write [1:0] phase shift the phase-shifted output by SHIFT input clocks\n this can be changed on-the-fly\n must be set to 0 before setting div=1 SHIFT PHASE 0x00000008 0x0018 Ring Oscillator Status read-only [31:31] Oscillator is running and stable STABLE read-write [24:24] An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT oneToClear BADWRITE read-only [16:16] post-divider is running\n this resets to 0 but transitions to 1 during chip startup DIV_RUNNING read-only [12:12] Oscillator is enabled but not necessarily running and stable\n this resets to 0 but transitions to 1 during chip startup ENABLED STATUS 0x00000000 0x001c This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency read-only [0:0] RANDOMBIT RANDOMBIT 0x00000001 0x0020 A down counter running at the ROSC frequency which counts to zero and stops.\n To start the counter write a non-zero value.\n Can be used for short software pauses when setting up time sensitive hardware. read-write [7:0] COUNT COUNT 0x00000000 32 1 0 0x1000 registers 0x40064000 control and status for on-chip voltage regulator and chip level reset subsystem VREG_AND_CHIP_RESET 0x0000 Voltage regulator control and status read-only [12:12] regulation status\n 0=not in regulation, 1=in regulation ROK read-write [7:4] output voltage select\n 0000 to 0101 - 0.80V\n 0110 - 0.85V\n 0111 - 0.90V\n 1000 - 0.95V\n 1001 - 1.00V\n 1010 - 1.05V\n 1011 - 1.10V (default)\n 1100 - 1.15V\n 1101 - 1.20V\n 1110 - 1.25V\n 1111 - 1.30V VSEL read-write [1:1] high impedance mode select\n 0=not in high impedance mode, 1=in high impedance mode HIZ read-write [0:0] enable\n 0=not enabled, 1=enabled EN VREG 0x000000b1 0x0004 brown-out detection control read-write [7:4] threshold select\n 0000 - 0.473V\n 0001 - 0.516V\n 0010 - 0.559V\n 0011 - 0.602V\n 0100 - 0.645V\n 0101 - 0.688V\n 0110 - 0.731V\n 0111 - 0.774V\n 1000 - 0.817V\n 1001 - 0.860V (default)\n 1010 - 0.903V\n 1011 - 0.946V\n 1100 - 0.989V\n 1101 - 1.032V\n 1110 - 1.075V\n 1111 - 1.118V VSEL read-write [0:0] enable\n 0=not enabled, 1=enabled EN BOD 0x00000091 0x0008 Chip reset control and status read-write [24:24] This is set by psm_restart from the debugger.\n Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\n In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. oneToClear PSM_RESTART_FLAG read-only [20:20] Last reset was from the debug port HAD_PSM_RESTART read-only [16:16] Last reset was from the RUN pin HAD_RUN read-only [8:8] Last reset was from the power-on reset or brown-out detection blocks HAD_POR CHIP_RESET 0x00000000 32 1 0 0x1000 registers 0x4006c000 Testbench manager. Allows the programmer to know what platform their software is running on. TBMAN 0x0000 Indicates the type of platform in use read-only [1:1] Indicates the platform is an FPGA FPGA read-only [0:0] Indicates the platform is an ASIC ASIC PLATFORM 0x00000005 32 1 0 0x1000 registers 0x50000000 DMA with separate read and write masters DMA_IRQ_0 11 DMA_IRQ_1 12 DMA read-write 0x0000 DMA Channel 0 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH0_READ_ADDR 0x00000000 read-write 0x0004 DMA Channel 0 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH0_WRITE_ADDR 0x00000000 read-write 0x0008 DMA Channel 0 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH0_TRANS_COUNT 0x00000000 0x000c DMA Channel 0 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH0_CTRL_TRIG 0x00000000 read-write 0x0010 Alias for channel 0 CTRL register CH0_AL1_CTRL 0x00000000 read-write 0x0014 Alias for channel 0 READ_ADDR register CH0_AL1_READ_ADDR 0x00000000 read-write 0x0018 Alias for channel 0 WRITE_ADDR register CH0_AL1_WRITE_ADDR 0x00000000 read-write 0x001c Alias for channel 0 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH0_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x0020 Alias for channel 0 CTRL register CH0_AL2_CTRL 0x00000000 read-write 0x0024 Alias for channel 0 TRANS_COUNT register CH0_AL2_TRANS_COUNT 0x00000000 read-write 0x0028 Alias for channel 0 READ_ADDR register CH0_AL2_READ_ADDR 0x00000000 read-write 0x002c Alias for channel 0 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH0_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x0030 Alias for channel 0 CTRL register CH0_AL3_CTRL 0x00000000 read-write 0x0034 Alias for channel 0 WRITE_ADDR register CH0_AL3_WRITE_ADDR 0x00000000 read-write 0x0038 Alias for channel 0 TRANS_COUNT register CH0_AL3_TRANS_COUNT 0x00000000 read-write 0x003c Alias for channel 0 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH0_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0040 DMA Channel 1 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH1_READ_ADDR 0x00000000 read-write 0x0044 DMA Channel 1 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH1_WRITE_ADDR 0x00000000 read-write 0x0048 DMA Channel 1 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH1_TRANS_COUNT 0x00000000 0x004c DMA Channel 1 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH1_CTRL_TRIG 0x00000000 read-write 0x0050 Alias for channel 1 CTRL register CH1_AL1_CTRL 0x00000000 read-write 0x0054 Alias for channel 1 READ_ADDR register CH1_AL1_READ_ADDR 0x00000000 read-write 0x0058 Alias for channel 1 WRITE_ADDR register CH1_AL1_WRITE_ADDR 0x00000000 read-write 0x005c Alias for channel 1 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH1_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x0060 Alias for channel 1 CTRL register CH1_AL2_CTRL 0x00000000 read-write 0x0064 Alias for channel 1 TRANS_COUNT register CH1_AL2_TRANS_COUNT 0x00000000 read-write 0x0068 Alias for channel 1 READ_ADDR register CH1_AL2_READ_ADDR 0x00000000 read-write 0x006c Alias for channel 1 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH1_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x0070 Alias for channel 1 CTRL register CH1_AL3_CTRL 0x00000000 read-write 0x0074 Alias for channel 1 WRITE_ADDR register CH1_AL3_WRITE_ADDR 0x00000000 read-write 0x0078 Alias for channel 1 TRANS_COUNT register CH1_AL3_TRANS_COUNT 0x00000000 read-write 0x007c Alias for channel 1 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH1_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0080 DMA Channel 2 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH2_READ_ADDR 0x00000000 read-write 0x0084 DMA Channel 2 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH2_WRITE_ADDR 0x00000000 read-write 0x0088 DMA Channel 2 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH2_TRANS_COUNT 0x00000000 0x008c DMA Channel 2 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH2_CTRL_TRIG 0x00000000 read-write 0x0090 Alias for channel 2 CTRL register CH2_AL1_CTRL 0x00000000 read-write 0x0094 Alias for channel 2 READ_ADDR register CH2_AL1_READ_ADDR 0x00000000 read-write 0x0098 Alias for channel 2 WRITE_ADDR register CH2_AL1_WRITE_ADDR 0x00000000 read-write 0x009c Alias for channel 2 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH2_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x00a0 Alias for channel 2 CTRL register CH2_AL2_CTRL 0x00000000 read-write 0x00a4 Alias for channel 2 TRANS_COUNT register CH2_AL2_TRANS_COUNT 0x00000000 read-write 0x00a8 Alias for channel 2 READ_ADDR register CH2_AL2_READ_ADDR 0x00000000 read-write 0x00ac Alias for channel 2 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH2_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x00b0 Alias for channel 2 CTRL register CH2_AL3_CTRL 0x00000000 read-write 0x00b4 Alias for channel 2 WRITE_ADDR register CH2_AL3_WRITE_ADDR 0x00000000 read-write 0x00b8 Alias for channel 2 TRANS_COUNT register CH2_AL3_TRANS_COUNT 0x00000000 read-write 0x00bc Alias for channel 2 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH2_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x00c0 DMA Channel 3 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH3_READ_ADDR 0x00000000 read-write 0x00c4 DMA Channel 3 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH3_WRITE_ADDR 0x00000000 read-write 0x00c8 DMA Channel 3 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH3_TRANS_COUNT 0x00000000 0x00cc DMA Channel 3 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH3_CTRL_TRIG 0x00000000 read-write 0x00d0 Alias for channel 3 CTRL register CH3_AL1_CTRL 0x00000000 read-write 0x00d4 Alias for channel 3 READ_ADDR register CH3_AL1_READ_ADDR 0x00000000 read-write 0x00d8 Alias for channel 3 WRITE_ADDR register CH3_AL1_WRITE_ADDR 0x00000000 read-write 0x00dc Alias for channel 3 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH3_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x00e0 Alias for channel 3 CTRL register CH3_AL2_CTRL 0x00000000 read-write 0x00e4 Alias for channel 3 TRANS_COUNT register CH3_AL2_TRANS_COUNT 0x00000000 read-write 0x00e8 Alias for channel 3 READ_ADDR register CH3_AL2_READ_ADDR 0x00000000 read-write 0x00ec Alias for channel 3 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH3_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x00f0 Alias for channel 3 CTRL register CH3_AL3_CTRL 0x00000000 read-write 0x00f4 Alias for channel 3 WRITE_ADDR register CH3_AL3_WRITE_ADDR 0x00000000 read-write 0x00f8 Alias for channel 3 TRANS_COUNT register CH3_AL3_TRANS_COUNT 0x00000000 read-write 0x00fc Alias for channel 3 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH3_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0100 DMA Channel 4 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH4_READ_ADDR 0x00000000 read-write 0x0104 DMA Channel 4 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH4_WRITE_ADDR 0x00000000 read-write 0x0108 DMA Channel 4 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH4_TRANS_COUNT 0x00000000 0x010c DMA Channel 4 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH4_CTRL_TRIG 0x00000000 read-write 0x0110 Alias for channel 4 CTRL register CH4_AL1_CTRL 0x00000000 read-write 0x0114 Alias for channel 4 READ_ADDR register CH4_AL1_READ_ADDR 0x00000000 read-write 0x0118 Alias for channel 4 WRITE_ADDR register CH4_AL1_WRITE_ADDR 0x00000000 read-write 0x011c Alias for channel 4 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH4_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x0120 Alias for channel 4 CTRL register CH4_AL2_CTRL 0x00000000 read-write 0x0124 Alias for channel 4 TRANS_COUNT register CH4_AL2_TRANS_COUNT 0x00000000 read-write 0x0128 Alias for channel 4 READ_ADDR register CH4_AL2_READ_ADDR 0x00000000 read-write 0x012c Alias for channel 4 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH4_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x0130 Alias for channel 4 CTRL register CH4_AL3_CTRL 0x00000000 read-write 0x0134 Alias for channel 4 WRITE_ADDR register CH4_AL3_WRITE_ADDR 0x00000000 read-write 0x0138 Alias for channel 4 TRANS_COUNT register CH4_AL3_TRANS_COUNT 0x00000000 read-write 0x013c Alias for channel 4 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH4_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0140 DMA Channel 5 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH5_READ_ADDR 0x00000000 read-write 0x0144 DMA Channel 5 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH5_WRITE_ADDR 0x00000000 read-write 0x0148 DMA Channel 5 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH5_TRANS_COUNT 0x00000000 0x014c DMA Channel 5 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH5_CTRL_TRIG 0x00000000 read-write 0x0150 Alias for channel 5 CTRL register CH5_AL1_CTRL 0x00000000 read-write 0x0154 Alias for channel 5 READ_ADDR register CH5_AL1_READ_ADDR 0x00000000 read-write 0x0158 Alias for channel 5 WRITE_ADDR register CH5_AL1_WRITE_ADDR 0x00000000 read-write 0x015c Alias for channel 5 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH5_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x0160 Alias for channel 5 CTRL register CH5_AL2_CTRL 0x00000000 read-write 0x0164 Alias for channel 5 TRANS_COUNT register CH5_AL2_TRANS_COUNT 0x00000000 read-write 0x0168 Alias for channel 5 READ_ADDR register CH5_AL2_READ_ADDR 0x00000000 read-write 0x016c Alias for channel 5 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH5_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x0170 Alias for channel 5 CTRL register CH5_AL3_CTRL 0x00000000 read-write 0x0174 Alias for channel 5 WRITE_ADDR register CH5_AL3_WRITE_ADDR 0x00000000 read-write 0x0178 Alias for channel 5 TRANS_COUNT register CH5_AL3_TRANS_COUNT 0x00000000 read-write 0x017c Alias for channel 5 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH5_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0180 DMA Channel 6 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH6_READ_ADDR 0x00000000 read-write 0x0184 DMA Channel 6 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH6_WRITE_ADDR 0x00000000 read-write 0x0188 DMA Channel 6 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH6_TRANS_COUNT 0x00000000 0x018c DMA Channel 6 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH6_CTRL_TRIG 0x00000000 read-write 0x0190 Alias for channel 6 CTRL register CH6_AL1_CTRL 0x00000000 read-write 0x0194 Alias for channel 6 READ_ADDR register CH6_AL1_READ_ADDR 0x00000000 read-write 0x0198 Alias for channel 6 WRITE_ADDR register CH6_AL1_WRITE_ADDR 0x00000000 read-write 0x019c Alias for channel 6 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH6_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x01a0 Alias for channel 6 CTRL register CH6_AL2_CTRL 0x00000000 read-write 0x01a4 Alias for channel 6 TRANS_COUNT register CH6_AL2_TRANS_COUNT 0x00000000 read-write 0x01a8 Alias for channel 6 READ_ADDR register CH6_AL2_READ_ADDR 0x00000000 read-write 0x01ac Alias for channel 6 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH6_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x01b0 Alias for channel 6 CTRL register CH6_AL3_CTRL 0x00000000 read-write 0x01b4 Alias for channel 6 WRITE_ADDR register CH6_AL3_WRITE_ADDR 0x00000000 read-write 0x01b8 Alias for channel 6 TRANS_COUNT register CH6_AL3_TRANS_COUNT 0x00000000 read-write 0x01bc Alias for channel 6 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH6_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x01c0 DMA Channel 7 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH7_READ_ADDR 0x00000000 read-write 0x01c4 DMA Channel 7 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH7_WRITE_ADDR 0x00000000 read-write 0x01c8 DMA Channel 7 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH7_TRANS_COUNT 0x00000000 0x01cc DMA Channel 7 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH7_CTRL_TRIG 0x00000000 read-write 0x01d0 Alias for channel 7 CTRL register CH7_AL1_CTRL 0x00000000 read-write 0x01d4 Alias for channel 7 READ_ADDR register CH7_AL1_READ_ADDR 0x00000000 read-write 0x01d8 Alias for channel 7 WRITE_ADDR register CH7_AL1_WRITE_ADDR 0x00000000 read-write 0x01dc Alias for channel 7 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH7_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x01e0 Alias for channel 7 CTRL register CH7_AL2_CTRL 0x00000000 read-write 0x01e4 Alias for channel 7 TRANS_COUNT register CH7_AL2_TRANS_COUNT 0x00000000 read-write 0x01e8 Alias for channel 7 READ_ADDR register CH7_AL2_READ_ADDR 0x00000000 read-write 0x01ec Alias for channel 7 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH7_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x01f0 Alias for channel 7 CTRL register CH7_AL3_CTRL 0x00000000 read-write 0x01f4 Alias for channel 7 WRITE_ADDR register CH7_AL3_WRITE_ADDR 0x00000000 read-write 0x01f8 Alias for channel 7 TRANS_COUNT register CH7_AL3_TRANS_COUNT 0x00000000 read-write 0x01fc Alias for channel 7 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH7_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0200 DMA Channel 8 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH8_READ_ADDR 0x00000000 read-write 0x0204 DMA Channel 8 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH8_WRITE_ADDR 0x00000000 read-write 0x0208 DMA Channel 8 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH8_TRANS_COUNT 0x00000000 0x020c DMA Channel 8 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH8_CTRL_TRIG 0x00000000 read-write 0x0210 Alias for channel 8 CTRL register CH8_AL1_CTRL 0x00000000 read-write 0x0214 Alias for channel 8 READ_ADDR register CH8_AL1_READ_ADDR 0x00000000 read-write 0x0218 Alias for channel 8 WRITE_ADDR register CH8_AL1_WRITE_ADDR 0x00000000 read-write 0x021c Alias for channel 8 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH8_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x0220 Alias for channel 8 CTRL register CH8_AL2_CTRL 0x00000000 read-write 0x0224 Alias for channel 8 TRANS_COUNT register CH8_AL2_TRANS_COUNT 0x00000000 read-write 0x0228 Alias for channel 8 READ_ADDR register CH8_AL2_READ_ADDR 0x00000000 read-write 0x022c Alias for channel 8 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH8_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x0230 Alias for channel 8 CTRL register CH8_AL3_CTRL 0x00000000 read-write 0x0234 Alias for channel 8 WRITE_ADDR register CH8_AL3_WRITE_ADDR 0x00000000 read-write 0x0238 Alias for channel 8 TRANS_COUNT register CH8_AL3_TRANS_COUNT 0x00000000 read-write 0x023c Alias for channel 8 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH8_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0240 DMA Channel 9 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH9_READ_ADDR 0x00000000 read-write 0x0244 DMA Channel 9 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH9_WRITE_ADDR 0x00000000 read-write 0x0248 DMA Channel 9 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH9_TRANS_COUNT 0x00000000 0x024c DMA Channel 9 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH9_CTRL_TRIG 0x00000000 read-write 0x0250 Alias for channel 9 CTRL register CH9_AL1_CTRL 0x00000000 read-write 0x0254 Alias for channel 9 READ_ADDR register CH9_AL1_READ_ADDR 0x00000000 read-write 0x0258 Alias for channel 9 WRITE_ADDR register CH9_AL1_WRITE_ADDR 0x00000000 read-write 0x025c Alias for channel 9 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH9_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x0260 Alias for channel 9 CTRL register CH9_AL2_CTRL 0x00000000 read-write 0x0264 Alias for channel 9 TRANS_COUNT register CH9_AL2_TRANS_COUNT 0x00000000 read-write 0x0268 Alias for channel 9 READ_ADDR register CH9_AL2_READ_ADDR 0x00000000 read-write 0x026c Alias for channel 9 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH9_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x0270 Alias for channel 9 CTRL register CH9_AL3_CTRL 0x00000000 read-write 0x0274 Alias for channel 9 WRITE_ADDR register CH9_AL3_WRITE_ADDR 0x00000000 read-write 0x0278 Alias for channel 9 TRANS_COUNT register CH9_AL3_TRANS_COUNT 0x00000000 read-write 0x027c Alias for channel 9 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH9_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x0280 DMA Channel 10 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH10_READ_ADDR 0x00000000 read-write 0x0284 DMA Channel 10 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH10_WRITE_ADDR 0x00000000 read-write 0x0288 DMA Channel 10 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH10_TRANS_COUNT 0x00000000 0x028c DMA Channel 10 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH10_CTRL_TRIG 0x00000000 read-write 0x0290 Alias for channel 10 CTRL register CH10_AL1_CTRL 0x00000000 read-write 0x0294 Alias for channel 10 READ_ADDR register CH10_AL1_READ_ADDR 0x00000000 read-write 0x0298 Alias for channel 10 WRITE_ADDR register CH10_AL1_WRITE_ADDR 0x00000000 read-write 0x029c Alias for channel 10 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH10_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x02a0 Alias for channel 10 CTRL register CH10_AL2_CTRL 0x00000000 read-write 0x02a4 Alias for channel 10 TRANS_COUNT register CH10_AL2_TRANS_COUNT 0x00000000 read-write 0x02a8 Alias for channel 10 READ_ADDR register CH10_AL2_READ_ADDR 0x00000000 read-write 0x02ac Alias for channel 10 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH10_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x02b0 Alias for channel 10 CTRL register CH10_AL3_CTRL 0x00000000 read-write 0x02b4 Alias for channel 10 WRITE_ADDR register CH10_AL3_WRITE_ADDR 0x00000000 read-write 0x02b8 Alias for channel 10 TRANS_COUNT register CH10_AL3_TRANS_COUNT 0x00000000 read-write 0x02bc Alias for channel 10 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH10_AL3_READ_ADDR_TRIG 0x00000000 read-write 0x02c0 DMA Channel 11 Read Address pointer\n This register updates automatically each time a read completes. The current value is the next address to be read by this channel. CH11_READ_ADDR 0x00000000 read-write 0x02c4 DMA Channel 11 Write Address pointer\n This register updates automatically each time a write completes. The current value is the next address to be written by this channel. CH11_WRITE_ADDR 0x00000000 read-write 0x02c8 DMA Channel 11 Transfer Count\n Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\n\n When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\n\n Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\n\n The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. CH11_TRANS_COUNT 0x00000000 0x02cc DMA Channel 11 Control and Status read-only [31:31] Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. AHB_ERROR read-write [30:30] If 1, the channel received a read bus error. Write one to clear.\n READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) oneToClear READ_ERROR read-write [29:29] If 1, the channel received a write bus error. Write one to clear.\n WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) oneToClear WRITE_ERROR read-only [24:24] This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\n\n To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. BUSY read-write [23:23] If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\n\n This allows checksum to be enabled or disabled on a per-control- block basis. SNIFF_EN read-write [22:22] Apply byte-swap transformation to DMA data.\n For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. BSWAP read-write [21:21] In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\n\n This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. IRQ_QUIET read-write [20:15] Select a Transfer Request signal.\n The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\n 0x0 to 0x3a -> select DREQ n as TREQ Select Timer 0 as TREQ TIMER0 59 Select Timer 1 as TREQ TIMER1 60 Select Timer 2 as TREQ (Optional) TIMER2 61 Select Timer 3 as TREQ (Optional) TIMER3 62 Permanent request, for unpaced transfers. PERMANENT 63 TREQ_SEL read-write [14:11] When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. CHAIN_TO read-write [10:10] Select whether RING_SIZE applies to read or write addresses.\n If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. RING_SEL read-write [9:6] Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\n\n Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. RING_NONE 0 RING_SIZE read-write [5:5] If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\n\n Generally this should be disabled for memory-to-peripheral transfers. INCR_WRITE read-write [4:4] If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\n\n Generally this should be disabled for peripheral-to-memory transfers. INCR_READ read-write [3:2] Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 DATA_SIZE read-write [1:1] HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\n\n This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. HIGH_PRIORITY read-write [0:0] DMA Channel Enable.\n When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) EN CH11_CTRL_TRIG 0x00000000 read-write 0x02d0 Alias for channel 11 CTRL register CH11_AL1_CTRL 0x00000000 read-write 0x02d4 Alias for channel 11 READ_ADDR register CH11_AL1_READ_ADDR 0x00000000 read-write 0x02d8 Alias for channel 11 WRITE_ADDR register CH11_AL1_WRITE_ADDR 0x00000000 read-write 0x02dc Alias for channel 11 TRANS_COUNT register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH11_AL1_TRANS_COUNT_TRIG 0x00000000 read-write 0x02e0 Alias for channel 11 CTRL register CH11_AL2_CTRL 0x00000000 read-write 0x02e4 Alias for channel 11 TRANS_COUNT register CH11_AL2_TRANS_COUNT 0x00000000 read-write 0x02e8 Alias for channel 11 READ_ADDR register CH11_AL2_READ_ADDR 0x00000000 read-write 0x02ec Alias for channel 11 WRITE_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH11_AL2_WRITE_ADDR_TRIG 0x00000000 read-write 0x02f0 Alias for channel 11 CTRL register CH11_AL3_CTRL 0x00000000 read-write 0x02f4 Alias for channel 11 WRITE_ADDR register CH11_AL3_WRITE_ADDR 0x00000000 read-write 0x02f8 Alias for channel 11 TRANS_COUNT register CH11_AL3_TRANS_COUNT 0x00000000 read-write 0x02fc Alias for channel 11 READ_ADDR register\n This is a trigger register (0xc). Writing a nonzero value will\n reload the channel counter and start the channel. CH11_AL3_READ_ADDR_TRIG 0x00000000 0x0400 Interrupt Status (raw) read-write [15:0] Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\n\n Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\n\n This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\n\n It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. oneToClear INTR INTR 0x00000000 0x0404 Interrupt Enables for IRQ 0 read-write [15:0] Set bit n to pass interrupts from channel n to DMA IRQ 0. INTE0 INTE0 0x00000000 0x0408 Force Interrupts read-write [15:0] Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. INTF0 INTF0 0x00000000 0x040c Interrupt Status for IRQ 0 read-write [15:0] Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here. oneToClear INTS0 INTS0 0x00000000 0x0414 Interrupt Enables for IRQ 1 read-write [15:0] Set bit n to pass interrupts from channel n to DMA IRQ 1. INTE1 INTE1 0x00000000 0x0418 Force Interrupts for IRQ 1 read-write [15:0] Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. INTF1 INTF1 0x00000000 0x041c Interrupt Status (masked) for IRQ 1 read-write [15:0] Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\n Channel interrupts can be cleared by writing a bit mask here. oneToClear INTS1 INTS1 0x00000000 0x0420 Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. read-write [31:16] Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. X read-write [15:0] Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. Y TIMER0 0x00000000 0x0424 Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. read-write [31:16] Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. X read-write [15:0] Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. Y TIMER1 0x00000000 0x0428 Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. read-write [31:16] Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. X read-write [15:0] Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. Y TIMER2 0x00000000 0x042c Pacing (X/Y) Fractional Timer\n The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. read-write [31:16] Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. X read-write [15:0] Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. Y TIMER3 0x00000000 0x0430 Trigger one or more channels simultaneously read-write [15:0] Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. clear MULTI_CHAN_TRIGGER MULTI_CHAN_TRIGGER 0x00000000 0x0434 Sniffer Control read-write [11:11] If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. OUT_INV read-write [10:10] If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. OUT_REV read-write [9:9] Locally perform a byte reverse on the sniffed data, before feeding into checksum.\n\n Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. BSWAP read-write [8:5] Calculate a CRC-32 (IEEE802.3 polynomial) CRC32 0 Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data CRC32R 1 Calculate a CRC-16-CCITT CRC16 2 Calculate a CRC-16-CCITT with bit reversed data CRC16R 3 XOR reduction over all data. == 1 if the total 1 population count is odd. EVEN 14 Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) SUM 15 CALC read-write [4:1] DMA channel for Sniffer to observe DMACH read-write [0:0] Enable sniffer EN SNIFF_CTRL 0x00000000 read-write 0x0438 Data accumulator for sniff hardware\n Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. SNIFF_DATA 0x00000000 0x0440 Debug RAF, WAF, TDF levels read-only [23:16] Current Read-Address-FIFO fill level RAF_LVL read-only [15:8] Current Write-Address-FIFO fill level WAF_LVL read-only [7:0] Current Transfer-Data-FIFO fill level TDF_LVL FIFO_LEVELS 0x00000000 0x0444 Abort an in-progress transfer sequence on one or more channels read-write [15:0] Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\n\n After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. clear CHAN_ABORT CHAN_ABORT 0x00000000 0x0448 The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. read-only [4:0] N_CHANNELS N_CHANNELS 0x00000000 0x0800 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH0_DBG_CTDREQ CH0_DBG_CTDREQ 0x00000000 read-only 0x0804 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH0_DBG_TCR 0x00000000 0x0840 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH1_DBG_CTDREQ CH1_DBG_CTDREQ 0x00000000 read-only 0x0844 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH1_DBG_TCR 0x00000000 0x0880 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH2_DBG_CTDREQ CH2_DBG_CTDREQ 0x00000000 read-only 0x0884 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH2_DBG_TCR 0x00000000 0x08c0 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH3_DBG_CTDREQ CH3_DBG_CTDREQ 0x00000000 read-only 0x08c4 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH3_DBG_TCR 0x00000000 0x0900 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH4_DBG_CTDREQ CH4_DBG_CTDREQ 0x00000000 read-only 0x0904 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH4_DBG_TCR 0x00000000 0x0940 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH5_DBG_CTDREQ CH5_DBG_CTDREQ 0x00000000 read-only 0x0944 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH5_DBG_TCR 0x00000000 0x0980 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH6_DBG_CTDREQ CH6_DBG_CTDREQ 0x00000000 read-only 0x0984 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH6_DBG_TCR 0x00000000 0x09c0 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH7_DBG_CTDREQ CH7_DBG_CTDREQ 0x00000000 read-only 0x09c4 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH7_DBG_TCR 0x00000000 0x0a00 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH8_DBG_CTDREQ CH8_DBG_CTDREQ 0x00000000 read-only 0x0a04 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH8_DBG_TCR 0x00000000 0x0a40 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH9_DBG_CTDREQ CH9_DBG_CTDREQ 0x00000000 read-only 0x0a44 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH9_DBG_TCR 0x00000000 0x0a80 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH10_DBG_CTDREQ CH10_DBG_CTDREQ 0x00000000 read-only 0x0a84 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH10_DBG_TCR 0x00000000 0x0ac0 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. read-write [5:0] oneToClear CH11_DBG_CTDREQ CH11_DBG_CTDREQ 0x00000000 read-only 0x0ac4 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer CH11_DBG_TCR 0x00000000 32 1 0 0x0100 registers 0x50100000 DPRAM layout for USB device. USBCTRL_DPRAM 0x0000 Bytes 0-3 of the SETUP packet from the host. read-write [31:16] WVALUE read-write [15:8] BREQUEST read-write [7:0] BMREQUESTTYPE SETUP_PACKET_LOW 0x00000000 0x0004 Bytes 4-7 of the setup packet from the host. read-write [31:16] WLENGTH read-write [15:0] WINDEX SETUP_PACKET_HIGH 0x00000000 0x0008 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP1_IN_CONTROL 0x00000000 0x000c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP1_OUT_CONTROL 0x00000000 0x0010 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP2_IN_CONTROL 0x00000000 0x0014 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP2_OUT_CONTROL 0x00000000 0x0018 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP3_IN_CONTROL 0x00000000 0x001c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP3_OUT_CONTROL 0x00000000 0x0020 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP4_IN_CONTROL 0x00000000 0x0024 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP4_OUT_CONTROL 0x00000000 0x0028 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP5_IN_CONTROL 0x00000000 0x002c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP5_OUT_CONTROL 0x00000000 0x0030 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP6_IN_CONTROL 0x00000000 0x0034 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP6_OUT_CONTROL 0x00000000 0x0038 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP7_IN_CONTROL 0x00000000 0x003c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP7_OUT_CONTROL 0x00000000 0x0040 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP8_IN_CONTROL 0x00000000 0x0044 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP8_OUT_CONTROL 0x00000000 0x0048 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP9_IN_CONTROL 0x00000000 0x004c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP9_OUT_CONTROL 0x00000000 0x0050 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP10_IN_CONTROL 0x00000000 0x0054 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP10_OUT_CONTROL 0x00000000 0x0058 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP11_IN_CONTROL 0x00000000 0x005c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP11_OUT_CONTROL 0x00000000 0x0060 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP12_IN_CONTROL 0x00000000 0x0064 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP12_OUT_CONTROL 0x00000000 0x0068 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP13_IN_CONTROL 0x00000000 0x006c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP13_OUT_CONTROL 0x00000000 0x0070 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP14_IN_CONTROL 0x00000000 0x0074 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP14_OUT_CONTROL 0x00000000 0x0078 read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP15_IN_CONTROL 0x00000000 0x007c read-write [31:31] Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. ENABLE read-write [30:30] This endpoint is double buffered. DOUBLE_BUFFERED read-write [29:29] Trigger an interrupt each time a buffer is done. INTERRUPT_PER_BUFF read-write [28:28] Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. INTERRUPT_PER_DOUBLE_BUFF read-write [27:26] Control 0 Isochronous 1 Bulk 2 Interrupt 3 ENDPOINT_TYPE read-write [17:17] Trigger an interrupt if a STALL is sent. Intended for debug only. INTERRUPT_ON_STALL read-write [16:16] Trigger an interrupt if a NAK is sent. Intended for debug only. INTERRUPT_ON_NAK read-write [15:0] 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. BUFFER_ADDRESS EP15_OUT_CONTROL 0x00000000 0x0080 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP0_IN_BUFFER_CONTROL 0x00000000 0x0084 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP0_OUT_BUFFER_CONTROL 0x00000000 0x0088 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP1_IN_BUFFER_CONTROL 0x00000000 0x008c Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP1_OUT_BUFFER_CONTROL 0x00000000 0x0090 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP2_IN_BUFFER_CONTROL 0x00000000 0x0094 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP2_OUT_BUFFER_CONTROL 0x00000000 0x0098 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP3_IN_BUFFER_CONTROL 0x00000000 0x009c Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP3_OUT_BUFFER_CONTROL 0x00000000 0x00a0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP4_IN_BUFFER_CONTROL 0x00000000 0x00a4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP4_OUT_BUFFER_CONTROL 0x00000000 0x00a8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP5_IN_BUFFER_CONTROL 0x00000000 0x00ac Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP5_OUT_BUFFER_CONTROL 0x00000000 0x00b0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP6_IN_BUFFER_CONTROL 0x00000000 0x00b4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP6_OUT_BUFFER_CONTROL 0x00000000 0x00b8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP7_IN_BUFFER_CONTROL 0x00000000 0x00bc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP7_OUT_BUFFER_CONTROL 0x00000000 0x00c0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP8_IN_BUFFER_CONTROL 0x00000000 0x00c4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP8_OUT_BUFFER_CONTROL 0x00000000 0x00c8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP9_IN_BUFFER_CONTROL 0x00000000 0x00cc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP9_OUT_BUFFER_CONTROL 0x00000000 0x00d0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP10_IN_BUFFER_CONTROL 0x00000000 0x00d4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP10_OUT_BUFFER_CONTROL 0x00000000 0x00d8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP11_IN_BUFFER_CONTROL 0x00000000 0x00dc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP11_OUT_BUFFER_CONTROL 0x00000000 0x00e0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP12_IN_BUFFER_CONTROL 0x00000000 0x00e4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP12_OUT_BUFFER_CONTROL 0x00000000 0x00e8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP13_IN_BUFFER_CONTROL 0x00000000 0x00ec Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP13_OUT_BUFFER_CONTROL 0x00000000 0x00f0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP14_IN_BUFFER_CONTROL 0x00000000 0x00f4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP14_OUT_BUFFER_CONTROL 0x00000000 0x00f8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP15_IN_BUFFER_CONTROL 0x00000000 0x00fc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. read-write [31:31] Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_1 read-write [30:30] Buffer 1 is the last buffer of the transfer. LAST_1 read-write [29:29] The data pid of buffer 1. PID_1 read-write [28:27] The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n For a non Isochronous endpoint the offset is always 64 bytes. 128 0 256 1 512 2 1024 3 DOUBLE_BUFFER_ISO_OFFSET read-write [26:26] Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_1 read-write [25:16] The length of the data in buffer 1. LENGTH_1 read-write [15:15] Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. FULL_0 read-write [14:14] Buffer 0 is the last buffer of the transfer. LAST_0 read-write [13:13] The data pid of buffer 0. PID_0 read-write [12:12] Reset the buffer selector to buffer 0. RESET read-write [11:11] Reply with a stall (valid for both buffers). STALL read-write [10:10] Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. AVAILABLE_0 read-write [9:0] The length of the data in buffer 0. LENGTH_0 EP15_OUT_BUFFER_CONTROL 0x00000000 32 1 0 0x1000 registers 0x50110000 USB FS/LS controller device registers USBCTRL_IRQ 5 USBCTRL_REGS 0x0000 Device address and endpoint control read-write [19:16] Device endpoint to send data to. Only valid for HOST mode. ENDPOINT read-write [6:0] In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. ADDRESS ADDR_ENDP 0x00000000 0x0004 Interrupt endpoint 1. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP1 0x00000000 0x0008 Interrupt endpoint 2. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP2 0x00000000 0x000c Interrupt endpoint 3. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP3 0x00000000 0x0010 Interrupt endpoint 4. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP4 0x00000000 0x0014 Interrupt endpoint 5. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP5 0x00000000 0x0018 Interrupt endpoint 6. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP6 0x00000000 0x001c Interrupt endpoint 7. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP7 0x00000000 0x0020 Interrupt endpoint 8. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP8 0x00000000 0x0024 Interrupt endpoint 9. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP9 0x00000000 0x0028 Interrupt endpoint 10. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP10 0x00000000 0x002c Interrupt endpoint 11. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP11 0x00000000 0x0030 Interrupt endpoint 12. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP12 0x00000000 0x0034 Interrupt endpoint 13. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP13 0x00000000 0x0038 Interrupt endpoint 14. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP14 0x00000000 0x003c Interrupt endpoint 15. Only valid for HOST mode. read-write [26:26] Interrupt EP requires preamble (is a low speed device on a full speed hub) INTEP_PREAMBLE read-write [25:25] Direction of the interrupt endpoint. In=0, Out=1 INTEP_DIR read-write [19:16] Endpoint number of the interrupt endpoint ENDPOINT read-write [6:0] Device address ADDRESS ADDR_ENDP15 0x00000000 0x0040 Main control register read-write [31:31] Reduced timings for simulation SIM_TIMING read-write [1:1] Device mode = 0, Host mode = 1 HOST_NDEVICE read-write [0:0] Enable controller CONTROLLER_EN MAIN_CTRL 0x00000000 0x0044 Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. write-only [10:0] COUNT SOF_WR 0x00000000 0x0048 Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. read-only [10:0] COUNT SOF_RD 0x00000000 0x004c SIE control register read-write [31:31] Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL EP0_INT_STALL read-write [30:30] Device: EP0 single buffered = 0, double buffered = 1 EP0_DOUBLE_BUF read-write [29:29] Device: Set bit in BUFF_STATUS for every buffer completed on EP0 EP0_INT_1BUF read-write [28:28] Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 EP0_INT_2BUF read-write [27:27] Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK EP0_INT_NAK read-write [26:26] Direct bus drive enable DIRECT_EN read-write [25:25] Direct control of DP DIRECT_DP read-write [24:24] Direct control of DM DIRECT_DM read-write [18:18] Power down bus transceiver TRANSCEIVER_PD read-write [17:17] Device: Pull-up strength (0=1K2, 1=2k3) RPU_OPT read-write [16:16] Device: Enable pull up resistor PULLUP_EN read-write [15:15] Host: Enable pull down resistors PULLDOWN_EN read-write [13:13] Host: Reset bus clear RESET_BUS read-write [12:12] Device: Remote wakeup. Device can initiate its own resume after suspend. clear RESUME read-write [11:11] Host: Enable VBUS VBUS_EN read-write [10:10] Host: Enable keep alive packet (for low speed bus) KEEP_ALIVE_EN read-write [9:9] Host: Enable SOF generation (for full speed bus) SOF_EN read-write [8:8] Host: Delay packet(s) until after SOF SOF_SYNC read-write [6:6] Host: Preable enable for LS device on FS hub PREAMBLE_EN read-write [4:4] Host: Stop transaction clear STOP_TRANS read-write [3:3] Host: Receive transaction (IN to host) RECEIVE_DATA read-write [2:2] Host: Send transaction (OUT from host) SEND_DATA read-write [1:1] Host: Send Setup packet SEND_SETUP read-write [0:0] Host: Start transaction clear START_TRANS SIE_CTRL 0x00000000 0x0050 SIE status register read-write [31:31] Data Sequence Error.\n\n The device can raise a sequence error in the following conditions:\n\n * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\n\n The host can raise a data sequence error in the following conditions:\n\n * An IN packet from the device has the wrong data PID oneToClear DATA_SEQ_ERROR read-write [30:30] ACK received. Raised by both host and device. oneToClear ACK_REC read-write [29:29] Host: STALL received oneToClear STALL_REC read-write [28:28] Host: NAK received oneToClear NAK_REC read-write [27:27] RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. oneToClear RX_TIMEOUT read-write [26:26] RX overflow is raised by the Serial RX engine if the incoming data is too fast. oneToClear RX_OVERFLOW read-write [25:25] Bit Stuff Error. Raised by the Serial RX engine. oneToClear BIT_STUFF_ERROR read-write [24:24] CRC Error. Raised by the Serial RX engine. oneToClear CRC_ERROR read-write [19:19] Device: bus reset received oneToClear BUS_RESET read-write [18:18] Transaction complete.\n\n Raised by device if:\n\n * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\n\n Raised by host if:\n\n * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set oneToClear TRANS_COMPLETE read-write [17:17] Device: Setup packet received oneToClear SETUP_REC read-write [16:16] Device: connected oneToClear CONNECTED read-write [11:11] Host: Device has initiated a remote resume. Device: host has initiated a resume. oneToClear RESUME read-only [10:10] VBUS over current detected VBUS_OVER_CURR read-write [9:8] Host: device speed. Disconnected = 00, LS = 01, FS = 10 oneToClear SPEED read-write [4:4] Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. oneToClear SUSPENDED read-only [3:2] USB bus line state LINE_STATE read-only [0:0] Device: VBUS Detected VBUS_DETECTED SIE_STATUS 0x00000000 0x0054 interrupt endpoint control register read-write [15:1] Host: Enable interrupt endpoint 1 -> 15 INT_EP_ACTIVE INT_EP_CTRL 0x00000000 0x0058 Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. read-write [31:31] oneToClear EP15_OUT read-write [30:30] oneToClear EP15_IN read-write [29:29] oneToClear EP14_OUT read-write [28:28] oneToClear EP14_IN read-write [27:27] oneToClear EP13_OUT read-write [26:26] oneToClear EP13_IN read-write [25:25] oneToClear EP12_OUT read-write [24:24] oneToClear EP12_IN read-write [23:23] oneToClear EP11_OUT read-write [22:22] oneToClear EP11_IN read-write [21:21] oneToClear EP10_OUT read-write [20:20] oneToClear EP10_IN read-write [19:19] oneToClear EP9_OUT read-write [18:18] oneToClear EP9_IN read-write [17:17] oneToClear EP8_OUT read-write [16:16] oneToClear EP8_IN read-write [15:15] oneToClear EP7_OUT read-write [14:14] oneToClear EP7_IN read-write [13:13] oneToClear EP6_OUT read-write [12:12] oneToClear EP6_IN read-write [11:11] oneToClear EP5_OUT read-write [10:10] oneToClear EP5_IN read-write [9:9] oneToClear EP4_OUT read-write [8:8] oneToClear EP4_IN read-write [7:7] oneToClear EP3_OUT read-write [6:6] oneToClear EP3_IN read-write [5:5] oneToClear EP2_OUT read-write [4:4] oneToClear EP2_IN read-write [3:3] oneToClear EP1_OUT read-write [2:2] oneToClear EP1_IN read-write [1:1] oneToClear EP0_OUT read-write [0:0] oneToClear EP0_IN BUFF_STATUS 0x00000000 0x005c Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. read-only [31:31] EP15_OUT read-only [30:30] EP15_IN read-only [29:29] EP14_OUT read-only [28:28] EP14_IN read-only [27:27] EP13_OUT read-only [26:26] EP13_IN read-only [25:25] EP12_OUT read-only [24:24] EP12_IN read-only [23:23] EP11_OUT read-only [22:22] EP11_IN read-only [21:21] EP10_OUT read-only [20:20] EP10_IN read-only [19:19] EP9_OUT read-only [18:18] EP9_IN read-only [17:17] EP8_OUT read-only [16:16] EP8_IN read-only [15:15] EP7_OUT read-only [14:14] EP7_IN read-only [13:13] EP6_OUT read-only [12:12] EP6_IN read-only [11:11] EP5_OUT read-only [10:10] EP5_IN read-only [9:9] EP4_OUT read-only [8:8] EP4_IN read-only [7:7] EP3_OUT read-only [6:6] EP3_IN read-only [5:5] EP2_OUT read-only [4:4] EP2_IN read-only [3:3] EP1_OUT read-only [2:2] EP1_IN read-only [1:1] EP0_OUT read-only [0:0] EP0_IN BUFF_CPU_SHOULD_HANDLE 0x00000000 0x0060 Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. read-write [31:31] EP15_OUT read-write [30:30] EP15_IN read-write [29:29] EP14_OUT read-write [28:28] EP14_IN read-write [27:27] EP13_OUT read-write [26:26] EP13_IN read-write [25:25] EP12_OUT read-write [24:24] EP12_IN read-write [23:23] EP11_OUT read-write [22:22] EP11_IN read-write [21:21] EP10_OUT read-write [20:20] EP10_IN read-write [19:19] EP9_OUT read-write [18:18] EP9_IN read-write [17:17] EP8_OUT read-write [16:16] EP8_IN read-write [15:15] EP7_OUT read-write [14:14] EP7_IN read-write [13:13] EP6_OUT read-write [12:12] EP6_IN read-write [11:11] EP5_OUT read-write [10:10] EP5_IN read-write [9:9] EP4_OUT read-write [8:8] EP4_IN read-write [7:7] EP3_OUT read-write [6:6] EP3_IN read-write [5:5] EP2_OUT read-write [4:4] EP2_IN read-write [3:3] EP1_OUT read-write [2:2] EP1_IN read-write [1:1] EP0_OUT read-write [0:0] EP0_IN EP_ABORT 0x00000000 0x0064 Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. read-write [31:31] oneToClear EP15_OUT read-write [30:30] oneToClear EP15_IN read-write [29:29] oneToClear EP14_OUT read-write [28:28] oneToClear EP14_IN read-write [27:27] oneToClear EP13_OUT read-write [26:26] oneToClear EP13_IN read-write [25:25] oneToClear EP12_OUT read-write [24:24] oneToClear EP12_IN read-write [23:23] oneToClear EP11_OUT read-write [22:22] oneToClear EP11_IN read-write [21:21] oneToClear EP10_OUT read-write [20:20] oneToClear EP10_IN read-write [19:19] oneToClear EP9_OUT read-write [18:18] oneToClear EP9_IN read-write [17:17] oneToClear EP8_OUT read-write [16:16] oneToClear EP8_IN read-write [15:15] oneToClear EP7_OUT read-write [14:14] oneToClear EP7_IN read-write [13:13] oneToClear EP6_OUT read-write [12:12] oneToClear EP6_IN read-write [11:11] oneToClear EP5_OUT read-write [10:10] oneToClear EP5_IN read-write [9:9] oneToClear EP4_OUT read-write [8:8] oneToClear EP4_IN read-write [7:7] oneToClear EP3_OUT read-write [6:6] oneToClear EP3_IN read-write [5:5] oneToClear EP2_OUT read-write [4:4] oneToClear EP2_IN read-write [3:3] oneToClear EP1_OUT read-write [2:2] oneToClear EP1_IN read-write [1:1] oneToClear EP0_OUT read-write [0:0] oneToClear EP0_IN EP_ABORT_DONE 0x00000000 0x0068 Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. read-write [1:1] EP0_OUT read-write [0:0] EP0_IN EP_STALL_ARM 0x00000000 0x006c Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. read-write [25:16] NAK polling interval for a full speed device DELAY_FS read-write [9:0] NAK polling interval for a low speed device DELAY_LS NAK_POLL 0x00100010 0x0070 Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. read-write [31:31] oneToClear EP15_OUT read-write [30:30] oneToClear EP15_IN read-write [29:29] oneToClear EP14_OUT read-write [28:28] oneToClear EP14_IN read-write [27:27] oneToClear EP13_OUT read-write [26:26] oneToClear EP13_IN read-write [25:25] oneToClear EP12_OUT read-write [24:24] oneToClear EP12_IN read-write [23:23] oneToClear EP11_OUT read-write [22:22] oneToClear EP11_IN read-write [21:21] oneToClear EP10_OUT read-write [20:20] oneToClear EP10_IN read-write [19:19] oneToClear EP9_OUT read-write [18:18] oneToClear EP9_IN read-write [17:17] oneToClear EP8_OUT read-write [16:16] oneToClear EP8_IN read-write [15:15] oneToClear EP7_OUT read-write [14:14] oneToClear EP7_IN read-write [13:13] oneToClear EP6_OUT read-write [12:12] oneToClear EP6_IN read-write [11:11] oneToClear EP5_OUT read-write [10:10] oneToClear EP5_IN read-write [9:9] oneToClear EP4_OUT read-write [8:8] oneToClear EP4_IN read-write [7:7] oneToClear EP3_OUT read-write [6:6] oneToClear EP3_IN read-write [5:5] oneToClear EP2_OUT read-write [4:4] oneToClear EP2_IN read-write [3:3] oneToClear EP1_OUT read-write [2:2] oneToClear EP1_IN read-write [1:1] oneToClear EP0_OUT read-write [0:0] oneToClear EP0_IN EP_STATUS_STALL_NAK 0x00000000 0x0074 Where to connect the USB controller. Should be to_phy by default. read-write [3:3] SOFTCON read-write [2:2] TO_DIGITAL_PAD read-write [1:1] TO_EXTPHY read-write [0:0] TO_PHY USB_MUXING 0x00000000 0x0078 Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. read-write [5:5] OVERCURR_DETECT_EN read-write [4:4] OVERCURR_DETECT read-write [3:3] VBUS_DETECT_OVERRIDE_EN read-write [2:2] VBUS_DETECT read-write [1:1] VBUS_EN_OVERRIDE_EN read-write [0:0] VBUS_EN USB_PWR 0x00000000 0x007c This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. read-only [22:22] DM over voltage DM_OVV read-only [21:21] DP over voltage DP_OVV read-only [20:20] DM overcurrent DM_OVCN read-only [19:19] DP overcurrent DP_OVCN read-only [18:18] DPM pin state RX_DM read-only [17:17] DPP pin state RX_DP read-only [16:16] Differential RX RX_DD read-write [15:15] TX_DIFFMODE=0: Single ended mode\n TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) TX_DIFFMODE read-write [14:14] TX_FSSLEW=0: Low speed slew rate\n TX_FSSLEW=1: Full speed slew rate TX_FSSLEW read-write [13:13] TX power down override (if override enable is set). 1 = powered down. TX_PD read-write [12:12] RX power down override (if override enable is set). 1 = powered down. RX_PD read-write [11:11] Output data. TX_DIFFMODE=1, Ignored\n TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM TX_DM read-write [10:10] Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\n If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP TX_DP read-write [9:9] Output enable. If TX_DIFFMODE=1, Ignored.\n If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving TX_DM_OE read-write [8:8] Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\n If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving TX_DP_OE read-write [6:6] DM pull down enable DM_PULLDN_EN read-write [5:5] DM pull up enable DM_PULLUP_EN read-write [4:4] Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 DM_PULLUP_HISEL read-write [2:2] DP pull down enable DP_PULLDN_EN read-write [1:1] DP pull up enable DP_PULLUP_EN read-write [0:0] Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 DP_PULLUP_HISEL USBPHY_DIRECT 0x00000000 0x0080 Override enable for each control in usbphy_direct read-write [15:15] TX_DIFFMODE_OVERRIDE_EN read-write [12:12] DM_PULLUP_OVERRIDE_EN read-write [11:11] TX_FSSLEW_OVERRIDE_EN read-write [10:10] TX_PD_OVERRIDE_EN read-write [9:9] RX_PD_OVERRIDE_EN read-write [8:8] TX_DM_OVERRIDE_EN read-write [7:7] TX_DP_OVERRIDE_EN read-write [6:6] TX_DM_OE_OVERRIDE_EN read-write [5:5] TX_DP_OE_OVERRIDE_EN read-write [4:4] DM_PULLDN_EN_OVERRIDE_EN read-write [3:3] DP_PULLDN_EN_OVERRIDE_EN read-write [2:2] DP_PULLUP_EN_OVERRIDE_EN read-write [1:1] DM_PULLUP_HISEL_OVERRIDE_EN read-write [0:0] DP_PULLUP_HISEL_OVERRIDE_EN USBPHY_DIRECT_OVERRIDE 0x00000000 0x0084 Used to adjust trim values of USB phy pull down resistors. read-write [12:8] Value to drive to USB PHY\n DM pulldown resistor trim control\n Experimental data suggests that the reset value will work, but this register allows adjustment if required DM_PULLDN_TRIM read-write [4:0] Value to drive to USB PHY\n DP pulldown resistor trim control\n Experimental data suggests that the reset value will work, but this register allows adjustment if required DP_PULLDN_TRIM USBPHY_TRIM 0x00001f1f 0x008c Raw Interrupts read-only [19:19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. EP_STALL_NAK read-only [18:18] Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. ABORT_DONE read-only [17:17] Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD DEV_SOF read-only [16:16] Device. Source: SIE_STATUS.SETUP_REC SETUP_REQ read-only [15:15] Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME DEV_RESUME_FROM_HOST read-only [14:14] Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED DEV_SUSPEND read-only [13:13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED DEV_CONN_DIS read-only [12:12] Source: SIE_STATUS.BUS_RESET BUS_RESET read-only [11:11] Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT read-only [10:10] Source: SIE_STATUS.STALL_REC STALL read-only [9:9] Source: SIE_STATUS.CRC_ERROR ERROR_CRC read-only [8:8] Source: SIE_STATUS.BIT_STUFF_ERROR ERROR_BIT_STUFF read-only [7:7] Source: SIE_STATUS.RX_OVERFLOW ERROR_RX_OVERFLOW read-only [6:6] Source: SIE_STATUS.RX_TIMEOUT ERROR_RX_TIMEOUT read-only [5:5] Source: SIE_STATUS.DATA_SEQ_ERROR ERROR_DATA_SEQ read-only [4:4] Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. BUFF_STATUS read-only [3:3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. TRANS_COMPLETE read-only [2:2] Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD HOST_SOF read-only [1:1] Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME HOST_RESUME read-only [0:0] Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED HOST_CONN_DIS INTR 0x00000000 0x0090 Interrupt Enable read-write [19:19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. EP_STALL_NAK read-write [18:18] Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. ABORT_DONE read-write [17:17] Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD DEV_SOF read-write [16:16] Device. Source: SIE_STATUS.SETUP_REC SETUP_REQ read-write [15:15] Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME DEV_RESUME_FROM_HOST read-write [14:14] Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED DEV_SUSPEND read-write [13:13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED DEV_CONN_DIS read-write [12:12] Source: SIE_STATUS.BUS_RESET BUS_RESET read-write [11:11] Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT read-write [10:10] Source: SIE_STATUS.STALL_REC STALL read-write [9:9] Source: SIE_STATUS.CRC_ERROR ERROR_CRC read-write [8:8] Source: SIE_STATUS.BIT_STUFF_ERROR ERROR_BIT_STUFF read-write [7:7] Source: SIE_STATUS.RX_OVERFLOW ERROR_RX_OVERFLOW read-write [6:6] Source: SIE_STATUS.RX_TIMEOUT ERROR_RX_TIMEOUT read-write [5:5] Source: SIE_STATUS.DATA_SEQ_ERROR ERROR_DATA_SEQ read-write [4:4] Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. BUFF_STATUS read-write [3:3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. TRANS_COMPLETE read-write [2:2] Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD HOST_SOF read-write [1:1] Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME HOST_RESUME read-write [0:0] Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED HOST_CONN_DIS INTE 0x00000000 0x0094 Interrupt Force read-write [19:19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. EP_STALL_NAK read-write [18:18] Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. ABORT_DONE read-write [17:17] Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD DEV_SOF read-write [16:16] Device. Source: SIE_STATUS.SETUP_REC SETUP_REQ read-write [15:15] Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME DEV_RESUME_FROM_HOST read-write [14:14] Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED DEV_SUSPEND read-write [13:13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED DEV_CONN_DIS read-write [12:12] Source: SIE_STATUS.BUS_RESET BUS_RESET read-write [11:11] Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT read-write [10:10] Source: SIE_STATUS.STALL_REC STALL read-write [9:9] Source: SIE_STATUS.CRC_ERROR ERROR_CRC read-write [8:8] Source: SIE_STATUS.BIT_STUFF_ERROR ERROR_BIT_STUFF read-write [7:7] Source: SIE_STATUS.RX_OVERFLOW ERROR_RX_OVERFLOW read-write [6:6] Source: SIE_STATUS.RX_TIMEOUT ERROR_RX_TIMEOUT read-write [5:5] Source: SIE_STATUS.DATA_SEQ_ERROR ERROR_DATA_SEQ read-write [4:4] Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. BUFF_STATUS read-write [3:3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. TRANS_COMPLETE read-write [2:2] Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD HOST_SOF read-write [1:1] Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME HOST_RESUME read-write [0:0] Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED HOST_CONN_DIS INTF 0x00000000 0x0098 Interrupt status after masking & forcing read-only [19:19] Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. EP_STALL_NAK read-only [18:18] Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. ABORT_DONE read-only [17:17] Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD DEV_SOF read-only [16:16] Device. Source: SIE_STATUS.SETUP_REC SETUP_REQ read-only [15:15] Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME DEV_RESUME_FROM_HOST read-only [14:14] Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED DEV_SUSPEND read-only [13:13] Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED DEV_CONN_DIS read-only [12:12] Source: SIE_STATUS.BUS_RESET BUS_RESET read-only [11:11] Source: SIE_STATUS.VBUS_DETECTED VBUS_DETECT read-only [10:10] Source: SIE_STATUS.STALL_REC STALL read-only [9:9] Source: SIE_STATUS.CRC_ERROR ERROR_CRC read-only [8:8] Source: SIE_STATUS.BIT_STUFF_ERROR ERROR_BIT_STUFF read-only [7:7] Source: SIE_STATUS.RX_OVERFLOW ERROR_RX_OVERFLOW read-only [6:6] Source: SIE_STATUS.RX_TIMEOUT ERROR_RX_TIMEOUT read-only [5:5] Source: SIE_STATUS.DATA_SEQ_ERROR ERROR_DATA_SEQ read-only [4:4] Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. BUFF_STATUS read-only [3:3] Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. TRANS_COMPLETE read-only [2:2] Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD HOST_SOF read-only [1:1] Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME HOST_RESUME read-only [0:0] Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED HOST_CONN_DIS INTS 0x00000000 32 1 0 0x1000 registers 0x50200000 Programmable IO block PIO0_IRQ_0 7 PIO0_IRQ_1 8 PIO0 0x0000 PIO control register read-write [11:8] Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\n\n Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. clear CLKDIV_RESTART read-write [7:4] Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\n\n Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.\n\n The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. clear SM_RESTART read-write [3:0] Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. SM_ENABLE CTRL 0x00000000 0x0004 FIFO status register read-only [27:24] State machine TX FIFO is empty TXEMPTY read-only [19:16] State machine TX FIFO is full TXFULL read-only [11:8] State machine RX FIFO is empty RXEMPTY read-only [3:0] State machine RX FIFO is full RXFULL FSTAT 0x0f000f00 0x0008 FIFO debug register read-write [27:24] State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. oneToClear TXSTALL read-write [19:16] TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. oneToClear TXOVER read-write [11:8] RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. oneToClear RXUNDER read-write [3:0] State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. oneToClear RXSTALL FDEBUG 0x00000000 0x000c FIFO levels read-only [31:28] RX3 read-only [27:24] TX3 read-only [23:20] RX2 read-only [19:16] TX2 read-only [15:12] RX1 read-only [11:8] TX1 read-only [7:4] RX0 read-only [3:0] TX0 FLEVEL 0x00000000 write-only 0x0010 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF0 0x00000000 write-only 0x0014 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF1 0x00000000 write-only 0x0018 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF2 0x00000000 write-only 0x001c Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. TXF3 0x00000000 read-only 0x0020 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF0 0x00000000 read-only 0x0024 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF1 0x00000000 read-only 0x0028 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF2 0x00000000 read-only 0x002c Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. RXF3 0x00000000 0x0030 State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\n\n Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. read-write [7:0] oneToClear IRQ IRQ 0x00000000 0x0034 Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. write-only [7:0] IRQ_FORCE IRQ_FORCE 0x00000000 read-write 0x0038 There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\n 0 -> input is synchronized (default)\n 1 -> synchronizer is bypassed\n If in doubt, leave this register as all zeroes. INPUT_SYNC_BYPASS 0x00000000 read-only 0x003c Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. DBG_PADOUT 0x00000000 read-only 0x0040 Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. DBG_PADOE 0x00000000 0x0044 The PIO hardware has some free parameters that may vary between chip products.\n These should be provided in the chip datasheet, but are also exposed here. read-only [21:16] The size of the instruction memory, measured in units of one instruction IMEM_SIZE read-only [11:8] The number of state machines this PIO instance is equipped with. SM_COUNT read-only [5:0] The depth of the state machine TX/RX FIFOs, measured in words.\n Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n this depth. FIFO_DEPTH DBG_CFGINFO 0x00000000 0x0048 Write-only access to instruction memory location 0 write-only [15:0] INSTR_MEM0 INSTR_MEM0 0x00000000 0x004c Write-only access to instruction memory location 1 write-only [15:0] INSTR_MEM1 INSTR_MEM1 0x00000000 0x0050 Write-only access to instruction memory location 2 write-only [15:0] INSTR_MEM2 INSTR_MEM2 0x00000000 0x0054 Write-only access to instruction memory location 3 write-only [15:0] INSTR_MEM3 INSTR_MEM3 0x00000000 0x0058 Write-only access to instruction memory location 4 write-only [15:0] INSTR_MEM4 INSTR_MEM4 0x00000000 0x005c Write-only access to instruction memory location 5 write-only [15:0] INSTR_MEM5 INSTR_MEM5 0x00000000 0x0060 Write-only access to instruction memory location 6 write-only [15:0] INSTR_MEM6 INSTR_MEM6 0x00000000 0x0064 Write-only access to instruction memory location 7 write-only [15:0] INSTR_MEM7 INSTR_MEM7 0x00000000 0x0068 Write-only access to instruction memory location 8 write-only [15:0] INSTR_MEM8 INSTR_MEM8 0x00000000 0x006c Write-only access to instruction memory location 9 write-only [15:0] INSTR_MEM9 INSTR_MEM9 0x00000000 0x0070 Write-only access to instruction memory location 10 write-only [15:0] INSTR_MEM10 INSTR_MEM10 0x00000000 0x0074 Write-only access to instruction memory location 11 write-only [15:0] INSTR_MEM11 INSTR_MEM11 0x00000000 0x0078 Write-only access to instruction memory location 12 write-only [15:0] INSTR_MEM12 INSTR_MEM12 0x00000000 0x007c Write-only access to instruction memory location 13 write-only [15:0] INSTR_MEM13 INSTR_MEM13 0x00000000 0x0080 Write-only access to instruction memory location 14 write-only [15:0] INSTR_MEM14 INSTR_MEM14 0x00000000 0x0084 Write-only access to instruction memory location 15 write-only [15:0] INSTR_MEM15 INSTR_MEM15 0x00000000 0x0088 Write-only access to instruction memory location 16 write-only [15:0] INSTR_MEM16 INSTR_MEM16 0x00000000 0x008c Write-only access to instruction memory location 17 write-only [15:0] INSTR_MEM17 INSTR_MEM17 0x00000000 0x0090 Write-only access to instruction memory location 18 write-only [15:0] INSTR_MEM18 INSTR_MEM18 0x00000000 0x0094 Write-only access to instruction memory location 19 write-only [15:0] INSTR_MEM19 INSTR_MEM19 0x00000000 0x0098 Write-only access to instruction memory location 20 write-only [15:0] INSTR_MEM20 INSTR_MEM20 0x00000000 0x009c Write-only access to instruction memory location 21 write-only [15:0] INSTR_MEM21 INSTR_MEM21 0x00000000 0x00a0 Write-only access to instruction memory location 22 write-only [15:0] INSTR_MEM22 INSTR_MEM22 0x00000000 0x00a4 Write-only access to instruction memory location 23 write-only [15:0] INSTR_MEM23 INSTR_MEM23 0x00000000 0x00a8 Write-only access to instruction memory location 24 write-only [15:0] INSTR_MEM24 INSTR_MEM24 0x00000000 0x00ac Write-only access to instruction memory location 25 write-only [15:0] INSTR_MEM25 INSTR_MEM25 0x00000000 0x00b0 Write-only access to instruction memory location 26 write-only [15:0] INSTR_MEM26 INSTR_MEM26 0x00000000 0x00b4 Write-only access to instruction memory location 27 write-only [15:0] INSTR_MEM27 INSTR_MEM27 0x00000000 0x00b8 Write-only access to instruction memory location 28 write-only [15:0] INSTR_MEM28 INSTR_MEM28 0x00000000 0x00bc Write-only access to instruction memory location 29 write-only [15:0] INSTR_MEM29 INSTR_MEM29 0x00000000 0x00c0 Write-only access to instruction memory location 30 write-only [15:0] INSTR_MEM30 INSTR_MEM30 0x00000000 0x00c4 Write-only access to instruction memory location 31 write-only [15:0] INSTR_MEM31 INSTR_MEM31 0x00000000 0x00c8 Clock divisor register for state machine 0\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] Fractional part of clock divisor FRAC SM0_CLKDIV 0x00010000 0x00cc Execution/behavioural settings for state machine 0 read-only [31:31] If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR read-write [28:24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. JMP_PIN read-write [23:19] Which data bit to use for inline OUT enable OUT_EN_SEL read-write [18:18] If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) INLINE_OUT_EN read-write [17:17] Continuously assert the most recent OUT/SET to the pins OUT_STICKY read-write [16:12] After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority. WRAP_TOP read-write [11:7] After reaching wrap_top, execution is wrapped to this address. WRAP_BOTTOM read-write [4:4] Comparison used for the MOV x, STATUS instruction. All-ones if TX FIFO level < N, otherwise all-zeroes TXLEVEL 0 All-ones if RX FIFO level < N, otherwise all-zeroes RXLEVEL 1 STATUS_SEL read-write [3:0] Comparison level for the MOV x, STATUS instruction STATUS_N SM0_EXECCTRL 0x0001f000 0x00d0 Control behaviour of the input/output shift registers for state machine 0 read-write [31:31] When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_RX read-write [30:30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_TX read-write [29:25] Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH read-write [19:19] 1 = shift out of output shift register to right. 0 = to left. OUT_SHIFTDIR read-write [18:18] 1 = shift input shift register to right (data enters from left). 0 = to left. IN_SHIFTDIR read-write [17:17] Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH SM0_SHIFTCTRL 0x000c0000 0x00d4 Current instruction address of state machine 0 read-only [4:0] SM0_ADDR SM0_ADDR 0x00000000 0x00d8 Read to see the instruction currently addressed by state machine 0's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. read-write [15:0] SM0_INSTR SM0_INSTR 0x00000000 0x00dc State machine pin control read-write [31:29] The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE SM0_PINCTRL 0x14000000 0x00e0 Clock divisor register for state machine 1\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] Fractional part of clock divisor FRAC SM1_CLKDIV 0x00010000 0x00e4 Execution/behavioural settings for state machine 1 read-only [31:31] If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR read-write [28:24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. JMP_PIN read-write [23:19] Which data bit to use for inline OUT enable OUT_EN_SEL read-write [18:18] If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) INLINE_OUT_EN read-write [17:17] Continuously assert the most recent OUT/SET to the pins OUT_STICKY read-write [16:12] After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority. WRAP_TOP read-write [11:7] After reaching wrap_top, execution is wrapped to this address. WRAP_BOTTOM read-write [4:4] Comparison used for the MOV x, STATUS instruction. All-ones if TX FIFO level < N, otherwise all-zeroes TXLEVEL 0 All-ones if RX FIFO level < N, otherwise all-zeroes RXLEVEL 1 STATUS_SEL read-write [3:0] Comparison level for the MOV x, STATUS instruction STATUS_N SM1_EXECCTRL 0x0001f000 0x00e8 Control behaviour of the input/output shift registers for state machine 1 read-write [31:31] When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_RX read-write [30:30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_TX read-write [29:25] Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH read-write [19:19] 1 = shift out of output shift register to right. 0 = to left. OUT_SHIFTDIR read-write [18:18] 1 = shift input shift register to right (data enters from left). 0 = to left. IN_SHIFTDIR read-write [17:17] Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH SM1_SHIFTCTRL 0x000c0000 0x00ec Current instruction address of state machine 1 read-only [4:0] SM1_ADDR SM1_ADDR 0x00000000 0x00f0 Read to see the instruction currently addressed by state machine 1's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. read-write [15:0] SM1_INSTR SM1_INSTR 0x00000000 0x00f4 State machine pin control read-write [31:29] The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE SM1_PINCTRL 0x14000000 0x00f8 Clock divisor register for state machine 2\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] Fractional part of clock divisor FRAC SM2_CLKDIV 0x00010000 0x00fc Execution/behavioural settings for state machine 2 read-only [31:31] If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR read-write [28:24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. JMP_PIN read-write [23:19] Which data bit to use for inline OUT enable OUT_EN_SEL read-write [18:18] If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) INLINE_OUT_EN read-write [17:17] Continuously assert the most recent OUT/SET to the pins OUT_STICKY read-write [16:12] After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority. WRAP_TOP read-write [11:7] After reaching wrap_top, execution is wrapped to this address. WRAP_BOTTOM read-write [4:4] Comparison used for the MOV x, STATUS instruction. All-ones if TX FIFO level < N, otherwise all-zeroes TXLEVEL 0 All-ones if RX FIFO level < N, otherwise all-zeroes RXLEVEL 1 STATUS_SEL read-write [3:0] Comparison level for the MOV x, STATUS instruction STATUS_N SM2_EXECCTRL 0x0001f000 0x0100 Control behaviour of the input/output shift registers for state machine 2 read-write [31:31] When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_RX read-write [30:30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_TX read-write [29:25] Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH read-write [19:19] 1 = shift out of output shift register to right. 0 = to left. OUT_SHIFTDIR read-write [18:18] 1 = shift input shift register to right (data enters from left). 0 = to left. IN_SHIFTDIR read-write [17:17] Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH SM2_SHIFTCTRL 0x000c0000 0x0104 Current instruction address of state machine 2 read-only [4:0] SM2_ADDR SM2_ADDR 0x00000000 0x0108 Read to see the instruction currently addressed by state machine 2's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. read-write [15:0] SM2_INSTR SM2_INSTR 0x00000000 0x010c State machine pin control read-write [31:29] The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE SM2_PINCTRL 0x14000000 0x0110 Clock divisor register for state machine 3\n Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) read-write [31:16] Effective frequency is sysclk/(int + frac/256).\n Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. INT read-write [15:8] Fractional part of clock divisor FRAC SM3_CLKDIV 0x00010000 0x0114 Execution/behavioural settings for state machine 3 read-only [31:31] If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. EXEC_STALLED read-write [30:30] If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. SIDE_EN read-write [29:29] If 1, side-set data is asserted to pin directions, instead of pin values SIDE_PINDIR read-write [28:24] The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. JMP_PIN read-write [23:19] Which data bit to use for inline OUT enable OUT_EN_SEL read-write [18:18] If 1, use a bit of OUT data as an auxiliary write enable\n When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n deassert the latest pin write. This can create useful masking/override behaviour\n due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) INLINE_OUT_EN read-write [17:17] Continuously assert the most recent OUT/SET to the pins OUT_STICKY read-write [16:12] After reaching this address, execution is wrapped to wrap_bottom.\n If the instruction is a jump, and the jump condition is true, the jump takes priority. WRAP_TOP read-write [11:7] After reaching wrap_top, execution is wrapped to this address. WRAP_BOTTOM read-write [4:4] Comparison used for the MOV x, STATUS instruction. All-ones if TX FIFO level < N, otherwise all-zeroes TXLEVEL 0 All-ones if RX FIFO level < N, otherwise all-zeroes RXLEVEL 1 STATUS_SEL read-write [3:0] Comparison level for the MOV x, STATUS instruction STATUS_N SM3_EXECCTRL 0x0001f000 0x0118 Control behaviour of the input/output shift registers for state machine 3 read-write [31:31] When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n TX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_RX read-write [30:30] When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n RX FIFO is disabled as a result (always reads as both full and empty).\n FIFOs are flushed when this bit is changed. FJOIN_TX read-write [29:25] Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\n Write 0 for value of 32. PULL_THRESH read-write [24:20] Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\n Write 0 for value of 32. PUSH_THRESH read-write [19:19] 1 = shift out of output shift register to right. 0 = to left. OUT_SHIFTDIR read-write [18:18] 1 = shift input shift register to right (data enters from left). 0 = to left. IN_SHIFTDIR read-write [17:17] Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. AUTOPULL read-write [16:16] Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. AUTOPUSH SM3_SHIFTCTRL 0x000c0000 0x011c Current instruction address of state machine 3 read-only [4:0] SM3_ADDR SM3_ADDR 0x00000000 0x0120 Read to see the instruction currently addressed by state machine 3's program counter\n Write to execute an instruction immediately (including jumps) and then resume execution. read-write [15:0] SM3_INSTR SM3_INSTR 0x00000000 0x0124 State machine pin control read-write [31:29] The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). SIDESET_COUNT read-write [28:26] The number of pins asserted by a SET. In the range 0 to 5 inclusive. SET_COUNT read-write [25:20] The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. OUT_COUNT read-write [19:15] The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. IN_BASE read-write [14:10] The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. SIDESET_BASE read-write [9:5] The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. SET_BASE read-write [4:0] The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. OUT_BASE SM3_PINCTRL 0x14000000 0x0128 Raw Interrupts read-only [11:11] SM3 read-only [10:10] SM2 read-only [9:9] SM1 read-only [8:8] SM0 read-only [7:7] SM3_TXNFULL read-only [6:6] SM2_TXNFULL read-only [5:5] SM1_TXNFULL read-only [4:4] SM0_TXNFULL read-only [3:3] SM3_RXNEMPTY read-only [2:2] SM2_RXNEMPTY read-only [1:1] SM1_RXNEMPTY read-only [0:0] SM0_RXNEMPTY INTR 0x00000000 0x012c Interrupt Enable for irq0 read-write [11:11] SM3 read-write [10:10] SM2 read-write [9:9] SM1 read-write [8:8] SM0 read-write [7:7] SM3_TXNFULL read-write [6:6] SM2_TXNFULL read-write [5:5] SM1_TXNFULL read-write [4:4] SM0_TXNFULL read-write [3:3] SM3_RXNEMPTY read-write [2:2] SM2_RXNEMPTY read-write [1:1] SM1_RXNEMPTY read-write [0:0] SM0_RXNEMPTY IRQ0_INTE 0x00000000 0x0130 Interrupt Force for irq0 read-write [11:11] SM3 read-write [10:10] SM2 read-write [9:9] SM1 read-write [8:8] SM0 read-write [7:7] SM3_TXNFULL read-write [6:6] SM2_TXNFULL read-write [5:5] SM1_TXNFULL read-write [4:4] SM0_TXNFULL read-write [3:3] SM3_RXNEMPTY read-write [2:2] SM2_RXNEMPTY read-write [1:1] SM1_RXNEMPTY read-write [0:0] SM0_RXNEMPTY IRQ0_INTF 0x00000000 0x0134 Interrupt status after masking & forcing for irq0 read-only [11:11] SM3 read-only [10:10] SM2 read-only [9:9] SM1 read-only [8:8] SM0 read-only [7:7] SM3_TXNFULL read-only [6:6] SM2_TXNFULL read-only [5:5] SM1_TXNFULL read-only [4:4] SM0_TXNFULL read-only [3:3] SM3_RXNEMPTY read-only [2:2] SM2_RXNEMPTY read-only [1:1] SM1_RXNEMPTY read-only [0:0] SM0_RXNEMPTY IRQ0_INTS 0x00000000 0x0138 Interrupt Enable for irq1 read-write [11:11] SM3 read-write [10:10] SM2 read-write [9:9] SM1 read-write [8:8] SM0 read-write [7:7] SM3_TXNFULL read-write [6:6] SM2_TXNFULL read-write [5:5] SM1_TXNFULL read-write [4:4] SM0_TXNFULL read-write [3:3] SM3_RXNEMPTY read-write [2:2] SM2_RXNEMPTY read-write [1:1] SM1_RXNEMPTY read-write [0:0] SM0_RXNEMPTY IRQ1_INTE 0x00000000 0x013c Interrupt Force for irq1 read-write [11:11] SM3 read-write [10:10] SM2 read-write [9:9] SM1 read-write [8:8] SM0 read-write [7:7] SM3_TXNFULL read-write [6:6] SM2_TXNFULL read-write [5:5] SM1_TXNFULL read-write [4:4] SM0_TXNFULL read-write [3:3] SM3_RXNEMPTY read-write [2:2] SM2_RXNEMPTY read-write [1:1] SM1_RXNEMPTY read-write [0:0] SM0_RXNEMPTY IRQ1_INTF 0x00000000 0x0140 Interrupt status after masking & forcing for irq1 read-only [11:11] SM3 read-only [10:10] SM2 read-only [9:9] SM1 read-only [8:8] SM0 read-only [7:7] SM3_TXNFULL read-only [6:6] SM2_TXNFULL read-only [5:5] SM1_TXNFULL read-only [4:4] SM0_TXNFULL read-only [3:3] SM3_RXNEMPTY read-only [2:2] SM2_RXNEMPTY read-only [1:1] SM1_RXNEMPTY read-only [0:0] SM0_RXNEMPTY IRQ1_INTS 0x00000000 32 1 0x50300000 PIO1_IRQ_0 9 PIO1_IRQ_1 10 PIO1 0 0x0200 registers 0xd0000000 Single-cycle IO block\n Provides core-local and inter-core hardware for the two processors, with single-cycle access. SIO_IRQ_PROC0 15 SIO_IRQ_PROC1 16 SIO read-only 0x0000 Processor core identifier\n Value is 0 when read from processor core 0, and 1 when read from processor core 1. CPUID 0x00000000 0x0004 Input value for GPIO pins read-only [29:0] Input value for GPIO0...29 GPIO_IN GPIO_IN 0x00000000 0x0008 Input value for QSPI pins read-only [5:0] Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 GPIO_HI_IN GPIO_HI_IN 0x00000000 0x0010 GPIO output value read-write [29:0] Set output level (1/0 -> high/low) for GPIO0...29.\n Reading back gives the last value written, NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result. GPIO_OUT GPIO_OUT 0x00000000 0x0014 GPIO output value set write-only [29:0] Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` GPIO_OUT_SET GPIO_OUT_SET 0x00000000 0x0018 GPIO output value clear write-only [29:0] Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` GPIO_OUT_CLR GPIO_OUT_CLR 0x00000000 0x001c GPIO output value XOR write-only [29:0] Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` GPIO_OUT_XOR GPIO_OUT_XOR 0x00000000 0x0020 GPIO output enable read-write [29:0] Set output enable (1/0 -> output/input) for GPIO0...29.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result. GPIO_OE GPIO_OE 0x00000000 0x0024 GPIO output enable set write-only [29:0] Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` GPIO_OE_SET GPIO_OE_SET 0x00000000 0x0028 GPIO output enable clear write-only [29:0] Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` GPIO_OE_CLR GPIO_OE_CLR 0x00000000 0x002c GPIO output enable XOR write-only [29:0] Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` GPIO_OE_XOR GPIO_OE_XOR 0x00000000 0x0030 QSPI output value read-write [5:0] Set output level (1/0 -> high/low) for QSPI IO0...5.\n Reading back gives the last value written, NOT the input value from the pins.\n If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result. GPIO_HI_OUT GPIO_HI_OUT 0x00000000 0x0034 QSPI output value set write-only [5:0] Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` GPIO_HI_OUT_SET GPIO_HI_OUT_SET 0x00000000 0x0038 QSPI output value clear write-only [5:0] Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` GPIO_HI_OUT_CLR GPIO_HI_OUT_CLR 0x00000000 0x003c QSPI output value XOR write-only [5:0] Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` GPIO_HI_OUT_XOR GPIO_HI_OUT_XOR 0x00000000 0x0040 QSPI output enable read-write [5:0] Set output enable (1/0 -> output/input) for QSPI IO0...5.\n Reading back gives the last value written.\n If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\n the result is as though the write from core 0 took place first,\n and the write from core 1 was then applied to that intermediate result. GPIO_HI_OE GPIO_HI_OE 0x00000000 0x0044 QSPI output enable set write-only [5:0] Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` GPIO_HI_OE_SET GPIO_HI_OE_SET 0x00000000 0x0048 QSPI output enable clear write-only [5:0] Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` GPIO_HI_OE_CLR GPIO_HI_OE_CLR 0x00000000 0x004c QSPI output enable XOR write-only [5:0] Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` GPIO_HI_OE_XOR GPIO_HI_OE_XOR 0x00000000 0x0050 Status register for inter-core FIFOs (mailboxes).\n There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\n Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\n Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\n The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. read-write [3:3] Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. oneToClear ROE read-write [2:2] Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. oneToClear WOF read-only [1:1] Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) RDY read-only [0:0] Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) VLD FIFO_ST 0x00000002 write-only 0x0054 Write access to this core's TX FIFO FIFO_WR 0x00000000 read-only 0x0058 Read access to this core's RX FIFO FIFO_RD 0x00000000 read-only 0x005c Spinlock state\n A bitmap containing the state of all 32 spinlocks (1=locked).\n Mainly intended for debugging. SPINLOCK_ST 0x00000000 read-write 0x0060 Divider unsigned dividend\n Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\n unsigned calculation, and the S alias starts a signed calculation. DIV_UDIVIDEND 0x00000000 read-write 0x0064 Divider unsigned divisor\n Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\n UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\n unsigned calculation, and the S alias starts a signed calculation. DIV_UDIVISOR 0x00000000 read-write 0x0068 Divider signed dividend\n The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. DIV_SDIVIDEND 0x00000000 read-write 0x006c Divider signed divisor\n The same as UDIVISOR, but starts a signed calculation, rather than unsigned. DIV_SDIVISOR 0x00000000 read-write 0x0070 Divider result quotient\n The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\n For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\n This register can be written to directly, for context save/restore purposes. This halts any\n in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\n REMAINDER, QUOTIENT if CSR_DIRTY is used. DIV_QUOTIENT 0x00000000 read-write 0x0074 Divider result remainder\n The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\n For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n This register can be written to directly, for context save/restore purposes. This halts any\n in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. DIV_REMAINDER 0x00000000 0x0078 Control and status register for divider. read-only [1:1] Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\n Software can use this flag to make save/restore more efficient (skip if not DIRTY).\n If the flag is used in this way, it's recommended to either read QUOTIENT only,\n or REMAINDER and then QUOTIENT, to prevent data loss on context switch. DIRTY read-only [0:0] Reads as 0 when a calculation is in progress, 1 otherwise.\n Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\n matter if one is already in progress.\n Writing to a result register will immediately terminate any in-progress calculation\n and set the READY and DIRTY flags. READY DIV_CSR 0x00000001 read-write 0x0080 Read/write access to accumulator 0 INTERP0_ACCUM0 0x00000000 read-write 0x0084 Read/write access to accumulator 1 INTERP0_ACCUM1 0x00000000 read-write 0x0088 Read/write access to BASE0 register. INTERP0_BASE0 0x00000000 read-write 0x008c Read/write access to BASE1 register. INTERP0_BASE1 0x00000000 read-write 0x0090 Read/write access to BASE2 register. INTERP0_BASE2 0x00000000 read-only 0x0094 Read LANE0 result, and simultaneously write lane results to both accumulators (POP). INTERP0_POP_LANE0 0x00000000 read-only 0x0098 Read LANE1 result, and simultaneously write lane results to both accumulators (POP). INTERP0_POP_LANE1 0x00000000 read-only 0x009c Read FULL result, and simultaneously write lane results to both accumulators (POP). INTERP0_POP_FULL 0x00000000 read-only 0x00a0 Read LANE0 result, without altering any internal state (PEEK). INTERP0_PEEK_LANE0 0x00000000 read-only 0x00a4 Read LANE1 result, without altering any internal state (PEEK). INTERP0_PEEK_LANE1 0x00000000 read-only 0x00a8 Read FULL result, without altering any internal state (PEEK). INTERP0_PEEK_FULL 0x00000000 0x00ac Control register for lane 0 read-only [25:25] Set if either OVERF0 or OVERF1 is set. OVERF read-only [24:24] Indicates if any masked-off MSBs in ACCUM1 are set. OVERF1 read-only [23:23] Indicates if any masked-off MSBs in ACCUM0 are set. OVERF0 read-write [21:21] Only present on INTERP0 on each core. If BLEND mode is enabled:\n - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n 0 and 255/256ths)\n - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\n - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\n LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. BLEND read-write [20:19] ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM. FORCE_MSB read-write [18:18] If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. ADD_RAW read-write [17:17] If 1, feed the opposite lane's result into this lane's accumulator on POP. CROSS_RESULT read-write [16:16] If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) CROSS_INPUT read-write [15:15] If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. SIGNED read-write [14:10] The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out MASK_MSB read-write [9:5] The least-significant bit allowed to pass by the mask (inclusive) MASK_LSB read-write [4:0] Logical right-shift applied to accumulator before masking SHIFT INTERP0_CTRL_LANE0 0x00000000 0x00b0 Control register for lane 1 read-write [20:19] ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM. FORCE_MSB read-write [18:18] If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. ADD_RAW read-write [17:17] If 1, feed the opposite lane's result into this lane's accumulator on POP. CROSS_RESULT read-write [16:16] If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) CROSS_INPUT read-write [15:15] If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. SIGNED read-write [14:10] The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out MASK_MSB read-write [9:5] The least-significant bit allowed to pass by the mask (inclusive) MASK_LSB read-write [4:0] Logical right-shift applied to accumulator before masking SHIFT INTERP0_CTRL_LANE1 0x00000000 0x00b4 Values written here are atomically added to ACCUM0\n Reading yields lane 0's raw shift and mask value (BASE0 not added). read-write [23:0] INTERP0_ACCUM0_ADD INTERP0_ACCUM0_ADD 0x00000000 0x00b8 Values written here are atomically added to ACCUM1\n Reading yields lane 1's raw shift and mask value (BASE1 not added). read-write [23:0] INTERP0_ACCUM1_ADD INTERP0_ACCUM1_ADD 0x00000000 write-only 0x00bc On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. INTERP0_BASE_1AND0 0x00000000 read-write 0x00c0 Read/write access to accumulator 0 INTERP1_ACCUM0 0x00000000 read-write 0x00c4 Read/write access to accumulator 1 INTERP1_ACCUM1 0x00000000 read-write 0x00c8 Read/write access to BASE0 register. INTERP1_BASE0 0x00000000 read-write 0x00cc Read/write access to BASE1 register. INTERP1_BASE1 0x00000000 read-write 0x00d0 Read/write access to BASE2 register. INTERP1_BASE2 0x00000000 read-only 0x00d4 Read LANE0 result, and simultaneously write lane results to both accumulators (POP). INTERP1_POP_LANE0 0x00000000 read-only 0x00d8 Read LANE1 result, and simultaneously write lane results to both accumulators (POP). INTERP1_POP_LANE1 0x00000000 read-only 0x00dc Read FULL result, and simultaneously write lane results to both accumulators (POP). INTERP1_POP_FULL 0x00000000 read-only 0x00e0 Read LANE0 result, without altering any internal state (PEEK). INTERP1_PEEK_LANE0 0x00000000 read-only 0x00e4 Read LANE1 result, without altering any internal state (PEEK). INTERP1_PEEK_LANE1 0x00000000 read-only 0x00e8 Read FULL result, without altering any internal state (PEEK). INTERP1_PEEK_FULL 0x00000000 0x00ec Control register for lane 0 read-only [25:25] Set if either OVERF0 or OVERF1 is set. OVERF read-only [24:24] Indicates if any masked-off MSBs in ACCUM1 are set. OVERF1 read-only [23:23] Indicates if any masked-off MSBs in ACCUM0 are set. OVERF0 read-write [22:22] Only present on INTERP1 on each core. If CLAMP mode is enabled:\n - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n BASE0 and an upper bound of BASE1.\n - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED CLAMP read-write [20:19] ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM. FORCE_MSB read-write [18:18] If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. ADD_RAW read-write [17:17] If 1, feed the opposite lane's result into this lane's accumulator on POP. CROSS_RESULT read-write [16:16] If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) CROSS_INPUT read-write [15:15] If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. SIGNED read-write [14:10] The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out MASK_MSB read-write [9:5] The least-significant bit allowed to pass by the mask (inclusive) MASK_LSB read-write [4:0] Logical right-shift applied to accumulator before masking SHIFT INTERP1_CTRL_LANE0 0x00000000 0x00f0 Control register for lane 1 read-write [20:19] ORed into bits 29:28 of the lane result presented to the processor on the bus.\n No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\n of pointers into flash or SRAM. FORCE_MSB read-write [18:18] If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. ADD_RAW read-write [17:17] If 1, feed the opposite lane's result into this lane's accumulator on POP. CROSS_RESULT read-write [16:16] If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\n Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) CROSS_INPUT read-write [15:15] If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\n before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. SIGNED read-write [14:10] The most-significant bit allowed to pass by the mask (inclusive)\n Setting MSB < LSB may cause chip to turn inside-out MASK_MSB read-write [9:5] The least-significant bit allowed to pass by the mask (inclusive) MASK_LSB read-write [4:0] Logical right-shift applied to accumulator before masking SHIFT INTERP1_CTRL_LANE1 0x00000000 0x00f4 Values written here are atomically added to ACCUM0\n Reading yields lane 0's raw shift and mask value (BASE0 not added). read-write [23:0] INTERP1_ACCUM0_ADD INTERP1_ACCUM0_ADD 0x00000000 0x00f8 Values written here are atomically added to ACCUM1\n Reading yields lane 1's raw shift and mask value (BASE1 not added). read-write [23:0] INTERP1_ACCUM1_ADD INTERP1_ACCUM1_ADD 0x00000000 write-only 0x00fc On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. INTERP1_BASE_1AND0 0x00000000 read-write 0x0100 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK0 0x00000000 read-write 0x0104 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK1 0x00000000 read-write 0x0108 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK2 0x00000000 read-write 0x010c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK3 0x00000000 read-write 0x0110 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK4 0x00000000 read-write 0x0114 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK5 0x00000000 read-write 0x0118 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK6 0x00000000 read-write 0x011c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK7 0x00000000 read-write 0x0120 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK8 0x00000000 read-write 0x0124 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK9 0x00000000 read-write 0x0128 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK10 0x00000000 read-write 0x012c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK11 0x00000000 read-write 0x0130 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK12 0x00000000 read-write 0x0134 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK13 0x00000000 read-write 0x0138 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK14 0x00000000 read-write 0x013c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK15 0x00000000 read-write 0x0140 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK16 0x00000000 read-write 0x0144 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK17 0x00000000 read-write 0x0148 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK18 0x00000000 read-write 0x014c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK19 0x00000000 read-write 0x0150 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK20 0x00000000 read-write 0x0154 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK21 0x00000000 read-write 0x0158 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK22 0x00000000 read-write 0x015c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK23 0x00000000 read-write 0x0160 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK24 0x00000000 read-write 0x0164 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK25 0x00000000 read-write 0x0168 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK26 0x00000000 read-write 0x016c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK27 0x00000000 read-write 0x0170 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK28 0x00000000 read-write 0x0174 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK29 0x00000000 read-write 0x0178 Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK30 0x00000000 read-write 0x017c Reading from a spinlock address will:\n - Return 0 if lock is already locked\n - Otherwise return nonzero, and simultaneously claim the lock\n\n Writing (any value) releases the lock.\n If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\n The value returned on success is 0x1 << lock number. SPINLOCK31 0x00000000 32 1 0 0x10000 registers 0xe0000000 PPB 0xe010 Use the SysTick Control and Status Register to enable the SysTick features. read-only [16:16] Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. COUNTFLAG read-write [2:2] SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n Selects the SysTick timer clock source:\n 0 = External reference clock.\n 1 = Processor clock. CLKSOURCE read-write [1:1] Enables SysTick exception request:\n 0 = Counting down to zero does not assert the SysTick exception request.\n 1 = Counting down to zero to asserts the SysTick exception request. TICKINT read-write [0:0] Enable SysTick counter:\n 0 = Counter disabled.\n 1 = Counter enabled. ENABLE SYST_CSR 0x00000000 0xe014 Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\n To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. read-write [23:0] Value to load into the SysTick Current Value Register when the counter reaches 0. RELOAD SYST_RVR 0x00000000 0xe018 Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. read-write [23:0] Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. CURRENT SYST_CVR 0x00000000 0xe01c Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. read-only [31:31] If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. NOREF read-only [30:30] If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). SKEW read-only [23:0] An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. TENMS SYST_CALIB 0x00000000 0xe100 Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\n If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. read-write [31:0] Interrupt set-enable bits.\n Write:\n 0 = No effect.\n 1 = Enable interrupt.\n Read:\n 0 = Interrupt disabled.\n 1 = Interrupt enabled. SETENA NVIC_ISER 0x00000000 0xe180 Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. read-write [31:0] Interrupt clear-enable bits.\n Write:\n 0 = No effect.\n 1 = Disable interrupt.\n Read:\n 0 = Interrupt disabled.\n 1 = Interrupt enabled. CLRENA NVIC_ICER 0x00000000 0xe200 The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. read-write [31:0] Interrupt set-pending bits.\n Write:\n 0 = No effect.\n 1 = Changes interrupt state to pending.\n Read:\n 0 = Interrupt is not pending.\n 1 = Interrupt is pending.\n Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n An interrupt that is pending has no effect.\n A disabled interrupt sets the state of that interrupt to pending. SETPEND NVIC_ISPR 0x00000000 0xe280 Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. read-write [31:0] Interrupt clear-pending bits.\n Write:\n 0 = No effect.\n 1 = Removes pending state and interrupt.\n Read:\n 0 = Interrupt is not pending.\n 1 = Interrupt is pending. CLRPEND NVIC_ICPR 0x00000000 0xe400 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\n Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\n These registers are only word-accessible read-write [31:30] Priority of interrupt 3 IP_3 read-write [23:22] Priority of interrupt 2 IP_2 read-write [15:14] Priority of interrupt 1 IP_1 read-write [7:6] Priority of interrupt 0 IP_0 NVIC_IPR0 0x00000000 0xe404 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. read-write [31:30] Priority of interrupt 7 IP_7 read-write [23:22] Priority of interrupt 6 IP_6 read-write [15:14] Priority of interrupt 5 IP_5 read-write [7:6] Priority of interrupt 4 IP_4 NVIC_IPR1 0x00000000 0xe408 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. read-write [31:30] Priority of interrupt 11 IP_11 read-write [23:22] Priority of interrupt 10 IP_10 read-write [15:14] Priority of interrupt 9 IP_9 read-write [7:6] Priority of interrupt 8 IP_8 NVIC_IPR2 0x00000000 0xe40c Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. read-write [31:30] Priority of interrupt 15 IP_15 read-write [23:22] Priority of interrupt 14 IP_14 read-write [15:14] Priority of interrupt 13 IP_13 read-write [7:6] Priority of interrupt 12 IP_12 NVIC_IPR3 0x00000000 0xe410 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. read-write [31:30] Priority of interrupt 19 IP_19 read-write [23:22] Priority of interrupt 18 IP_18 read-write [15:14] Priority of interrupt 17 IP_17 read-write [7:6] Priority of interrupt 16 IP_16 NVIC_IPR4 0x00000000 0xe414 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. read-write [31:30] Priority of interrupt 23 IP_23 read-write [23:22] Priority of interrupt 22 IP_22 read-write [15:14] Priority of interrupt 21 IP_21 read-write [7:6] Priority of interrupt 20 IP_20 NVIC_IPR5 0x00000000 0xe418 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. read-write [31:30] Priority of interrupt 27 IP_27 read-write [23:22] Priority of interrupt 26 IP_26 read-write [15:14] Priority of interrupt 25 IP_25 read-write [7:6] Priority of interrupt 24 IP_24 NVIC_IPR6 0x00000000 0xe41c Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. read-write [31:30] Priority of interrupt 31 IP_31 read-write [23:22] Priority of interrupt 30 IP_30 read-write [15:14] Priority of interrupt 29 IP_29 read-write [7:6] Priority of interrupt 28 IP_28 NVIC_IPR7 0x00000000 0xed00 Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. read-only [31:24] Implementor code: 0x41 = ARM IMPLEMENTER read-only [23:20] Major revision number n in the rnpm revision status:\n 0x0 = Revision 0. VARIANT read-only [19:16] Constant that defines the architecture of the processor:\n 0xC = ARMv6-M architecture. ARCHITECTURE read-only [15:4] Number of processor within family: 0xC60 = Cortex-M0+ PARTNO read-only [3:0] Minor revision number m in the rnpm revision status:\n 0x1 = Patch 1. REVISION CPUID 0x410cc601 0xed04 Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. read-write [31:31] Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\n NMI set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes NMI exception state to pending.\n Read:\n 0 = NMI exception is not pending.\n 1 = NMI exception is pending.\n Because NMI is the highest-priority exception, normally the processor enters the NMI\n exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\n this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\n NMI signal is reasserted while the processor is executing that handler. NMIPENDSET read-write [28:28] PendSV set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes PendSV exception state to pending.\n Read:\n 0 = PendSV exception is not pending.\n 1 = PendSV exception is pending.\n Writing 1 to this bit is the only way to set the PendSV exception state to pending. PENDSVSET read-write [27:27] PendSV clear-pending bit.\n Write:\n 0 = No effect.\n 1 = Removes the pending state from the PendSV exception. PENDSVCLR read-write [26:26] SysTick exception set-pending bit.\n Write:\n 0 = No effect.\n 1 = Changes SysTick exception state to pending.\n Read:\n 0 = SysTick exception is not pending.\n 1 = SysTick exception is pending. PENDSTSET read-write [25:25] SysTick exception clear-pending bit.\n Write:\n 0 = No effect.\n 1 = Removes the pending state from the SysTick exception.\n This bit is WO. On a register read its value is Unknown. PENDSTCLR read-only [23:23] The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. ISRPREEMPT read-only [22:22] External interrupt pending flag ISRPENDING read-only [20:12] Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. VECTPENDING read-only [8:0] Active exception number field. Reset clears the VECTACTIVE field. VECTACTIVE ICSR 0x00000000 0xed08 The VTOR holds the vector table offset address. read-write [31:8] Bits [31:8] of the indicate the vector table offset address. TBLOFF VTOR 0x00000000 0xed0c Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. read-write [31:16] Register key:\n Reads as Unknown\n On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. VECTKEY read-only [15:15] Data endianness implemented:\n 0 = Little-endian. ENDIANESS read-write [2:2] Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. SYSRESETREQ read-write [1:1] Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. VECTCLRACTIVE AIRCR 0x00000000 0xed10 System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. read-write [4:4] Send Event on Pending bit:\n 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\n 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\n When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\n processor is not waiting for an event, the event is registered and affects the next WFE.\n The processor also wakes up on execution of an SEV instruction or an external event. SEVONPEND read-write [2:2] Controls whether the processor uses sleep or deep sleep as its low power mode:\n 0 = Sleep.\n 1 = Deep sleep. SLEEPDEEP read-write [1:1] Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n 0 = Do not sleep when returning to Thread mode.\n 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. SLEEPONEXIT SCR 0x00000000 0xed14 The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. read-only [9:9] Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. STKALIGN read-only [3:3] Always reads as one, indicates that all unaligned accesses generate a HardFault. UNALIGN_TRP CCR 0x00000000 0xed1c System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. read-write [31:30] Priority of system handler 11, SVCall PRI_11 SHPR2 0x00000000 0xed20 System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. read-write [31:30] Priority of system handler 15, SysTick PRI_15 read-write [23:22] Priority of system handler 14, PendSV PRI_14 SHPR3 0x00000000 0xed24 Use the System Handler Control and State Register to determine or clear the pending status of SVCall. read-write [15:15] Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. SVCALLPENDED SHCSR 0x00000000 0xed90 Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. read-only [23:16] Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. IREGION read-only [15:8] Number of regions supported by the MPU. DREGION read-only [0:0] Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. SEPARATE MPU_TYPE 0x00000800 0xed94 Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. read-write [2:2] Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\n 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\n covered by any enabled region causes a fault.\n 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\n When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. PRIVDEFENA read-write [1:1] Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\n When the MPU is enabled:\n 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\n 1 = the MPU is enabled during HardFault and NMI handlers. HFNMIENA read-write [0:0] Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\n 0 = MPU disabled.\n 1 = MPU enabled. ENABLE MPU_CTRL 0x00000000 0xed98 Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. read-write [3:0] Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n The MPU supports 8 memory regions, so the permitted values of this field are 0-7. REGION MPU_RNR 0x00000000 0xed9c Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. read-write [31:8] Base address of the region. ADDR read-write [4:4] On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\n Write:\n 0 = MPU_RNR not changed, and the processor:\n Updates the base address for the region specified in the MPU_RNR.\n Ignores the value of the REGION field.\n 1 = The processor:\n Updates the value of the MPU_RNR to the value of the REGION field.\n Updates the base address for the region specified in the REGION field.\n Always reads as zero. VALID read-write [3:0] On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. REGION MPU_RBAR 0x00000000 0xeda0 Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. read-write [31:16] The MPU Region Attribute field. Use to define the region attribute control.\n 28 = XN: Instruction access disable bit:\n 0 = Instruction fetches enabled.\n 1 = Instruction fetches disabled.\n 26:24 = AP: Access permission field\n 18 = S: Shareable bit\n 17 = C: Cacheable bit\n 16 = B: Bufferable bit ATTRS read-write [15:8] Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. SRD read-write [5:1] Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes SIZE read-write [0:0] Enables the region. ENABLE MPU_RASR 0x00000000 32 1 SWI_IRQ Virtual Peripheral to access unused NVIC software interrupts 0 SWI_IRQ_0 26 SWI_IRQ_1 27 SWI_IRQ_2 28 SWI_IRQ_3 29 SWI_IRQ_4 30 SWI_IRQ_5 31