Raspberry Pi RP2350 RP 0.1 Dual Cortex-M33 or Hazard3 processors at 150MHz 520kB on-chip SRAM, in 10 independent banks Extended low-power sleep states with optional SRAM retention: as low as 10uA DVDD 8kB of one-time-programmable storage (OTP) Up to 16MB of external QSPI flash/PSRAM via dedicated QSPI bus Additional 16MB flash/PSRAM accessible via optional second chip-select On-chip switched-mode power supply to generate core voltage Low-quiescent-current LDO mode can be enabled for sleep states 2x on-chip PLLs for internal or external clock generation GPIOs are 5V-tolerant (powered), and 3.3V-failsafe (unpowered) Security features: Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP Protected OTP storage for optional boot decryption key Global bus filtering based on Arm or RISC-V security/privilege levels Peripherals, GPIOs and DMA channels individually assignable to security domains Hardware mitigations for fault injection attacks Hardware SHA-256 accelerator Peripherals: 2x UARTs 2x SPI controllers 2x I2C controllers 24x PWM channels USB 1.1 controller and PHY, with host and device support 12x PIO state machines 1x HSTX peripheral Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause CM33 r1p0 little true true true true 4 false 52 8 8 32 0x20 read-write 0x00000000 0xFFFFFFFF RESETS 0x40020000 0x0 0xC registers RESET 0x0 0x1FFFFFFF USBCTRL [28:28] read-write UART1 [27:27] read-write UART0 [26:26] read-write TRNG [25:25] read-write TIMER1 [24:24] read-write TIMER0 [23:23] read-write TBMAN [22:22] read-write SYSINFO [21:21] read-write SYSCFG [20:20] read-write SPI1 [19:19] read-write SPI0 [18:18] read-write SHA256 [17:17] read-write PWM [16:16] read-write PLL_USB [15:15] read-write PLL_SYS [14:14] read-write PIO2 [13:13] read-write PIO1 [12:12] read-write PIO0 [11:11] read-write PADS_QSPI [10:10] read-write PADS_BANK0 [9:9] read-write JTAG [8:8] read-write IO_QSPI [7:7] read-write IO_BANK0 [6:6] read-write I2C1 [5:5] read-write I2C0 [4:4] read-write HSTX [3:3] read-write DMA [2:2] read-write BUSCTRL [1:1] read-write ADC [0:0] read-write WDSEL 0x4 0x00000000 USBCTRL [28:28] read-write UART1 [27:27] read-write UART0 [26:26] read-write TRNG [25:25] read-write TIMER1 [24:24] read-write TIMER0 [23:23] read-write TBMAN [22:22] read-write SYSINFO [21:21] read-write SYSCFG [20:20] read-write SPI1 [19:19] read-write SPI0 [18:18] read-write SHA256 [17:17] read-write PWM [16:16] read-write PLL_USB [15:15] read-write PLL_SYS [14:14] read-write PIO2 [13:13] read-write PIO1 [12:12] read-write PIO0 [11:11] read-write PADS_QSPI [10:10] read-write PADS_BANK0 [9:9] read-write JTAG [8:8] read-write IO_QSPI [7:7] read-write IO_BANK0 [6:6] read-write I2C1 [5:5] read-write I2C0 [4:4] read-write HSTX [3:3] read-write DMA [2:2] read-write BUSCTRL [1:1] read-write ADC [0:0] read-write RESET_DONE 0x8 0x00000000 USBCTRL [28:28] read-only UART1 [27:27] read-only UART0 [26:26] read-only TRNG [25:25] read-only TIMER1 [24:24] read-only TIMER0 [23:23] read-only TBMAN [22:22] read-only SYSINFO [21:21] read-only SYSCFG [20:20] read-only SPI1 [19:19] read-only SPI0 [18:18] read-only SHA256 [17:17] read-only PWM [16:16] read-only PLL_USB [15:15] read-only PLL_SYS [14:14] read-only PIO2 [13:13] read-only PIO1 [12:12] read-only PIO0 [11:11] read-only PADS_QSPI [10:10] read-only PADS_BANK0 [9:9] read-only JTAG [8:8] read-only IO_QSPI [7:7] read-only IO_BANK0 [6:6] read-only I2C1 [5:5] read-only I2C0 [4:4] read-only HSTX [3:3] read-only DMA [2:2] read-only BUSCTRL [1:1] read-only ADC [0:0] read-only PSM 0x40018000 0x0 0x10 registers FRCE_ON Force block out of reset (i.e. power it on) 0x0 0x00000000 PROC1 [24:24] read-write PROC0 [23:23] read-write ACCESSCTRL [22:22] read-write SIO [21:21] read-write XIP [20:20] read-write SRAM9 [19:19] read-write SRAM8 [18:18] read-write SRAM7 [17:17] read-write SRAM6 [16:16] read-write SRAM5 [15:15] read-write SRAM4 [14:14] read-write SRAM3 [13:13] read-write SRAM2 [12:12] read-write SRAM1 [11:11] read-write SRAM0 [10:10] read-write BOOTRAM [9:9] read-write ROM [8:8] read-write BUSFABRIC [7:7] read-write PSM_READY [6:6] read-write CLOCKS [5:5] read-write RESETS [4:4] read-write XOSC [3:3] read-write ROSC [2:2] read-write OTP [1:1] read-write PROC_COLD [0:0] read-write FRCE_OFF Force into reset (i.e. power it off) 0x4 0x00000000 PROC1 [24:24] read-write PROC0 [23:23] read-write ACCESSCTRL [22:22] read-write SIO [21:21] read-write XIP [20:20] read-write SRAM9 [19:19] read-write SRAM8 [18:18] read-write SRAM7 [17:17] read-write SRAM6 [16:16] read-write SRAM5 [15:15] read-write SRAM4 [14:14] read-write SRAM3 [13:13] read-write SRAM2 [12:12] read-write SRAM1 [11:11] read-write SRAM0 [10:10] read-write BOOTRAM [9:9] read-write ROM [8:8] read-write BUSFABRIC [7:7] read-write PSM_READY [6:6] read-write CLOCKS [5:5] read-write RESETS [4:4] read-write XOSC [3:3] read-write ROSC [2:2] read-write OTP [1:1] read-write PROC_COLD [0:0] read-write WDSEL Set to 1 if the watchdog should reset this 0x8 0x00000000 PROC1 [24:24] read-write PROC0 [23:23] read-write ACCESSCTRL [22:22] read-write SIO [21:21] read-write XIP [20:20] read-write SRAM9 [19:19] read-write SRAM8 [18:18] read-write SRAM7 [17:17] read-write SRAM6 [16:16] read-write SRAM5 [15:15] read-write SRAM4 [14:14] read-write SRAM3 [13:13] read-write SRAM2 [12:12] read-write SRAM1 [11:11] read-write SRAM0 [10:10] read-write BOOTRAM [9:9] read-write ROM [8:8] read-write BUSFABRIC [7:7] read-write PSM_READY [6:6] read-write CLOCKS [5:5] read-write RESETS [4:4] read-write XOSC [3:3] read-write ROSC [2:2] read-write OTP [1:1] read-write PROC_COLD [0:0] read-write DONE Is the subsystem ready? 0xC 0x00000000 PROC1 [24:24] read-only PROC0 [23:23] read-only ACCESSCTRL [22:22] read-only SIO [21:21] read-only XIP [20:20] read-only SRAM9 [19:19] read-only SRAM8 [18:18] read-only SRAM7 [17:17] read-only SRAM6 [16:16] read-only SRAM5 [15:15] read-only SRAM4 [14:14] read-only SRAM3 [13:13] read-only SRAM2 [12:12] read-only SRAM1 [11:11] read-only SRAM0 [10:10] read-only BOOTRAM [9:9] read-only ROM [8:8] read-only BUSFABRIC [7:7] read-only PSM_READY [6:6] read-only CLOCKS [5:5] read-only RESETS [4:4] read-only XOSC [3:3] read-only ROSC [2:2] read-only OTP [1:1] read-only PROC_COLD [0:0] read-only CLOCKS 0x40010000 0x0 0xD4 registers CLOCKS_IRQ 30 CLK_GPOUT0_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x0 0x00000000 ENABLED clock generator is enabled [28:28] read-only NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors, can be changed on-the-fly [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 clksrc_pll_usb_primary_ref_opcg 4 rosc_clksrc 5 xosc_clksrc 6 lposc_clksrc 7 clk_sys 8 clk_usb 9 clk_adc 10 clk_ref 11 clk_peri 12 clk_hstx 13 otp_clk2fc 14 CLK_GPOUT0_DIV 0x4 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [31:16] read-write FRAC Fractional component of the divisor, can be changed on-the-fly [15:0] read-write CLK_GPOUT0_SELECTED Indicates which src is currently selected (one-hot) 0x8 0x00000001 CLK_GPOUT0_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only CLK_GPOUT1_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0xC 0x00000000 ENABLED clock generator is enabled [28:28] read-only NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors, can be changed on-the-fly [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 clksrc_pll_usb_primary_ref_opcg 4 rosc_clksrc 5 xosc_clksrc 6 lposc_clksrc 7 clk_sys 8 clk_usb 9 clk_adc 10 clk_ref 11 clk_peri 12 clk_hstx 13 otp_clk2fc 14 CLK_GPOUT1_DIV 0x10 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [31:16] read-write FRAC Fractional component of the divisor, can be changed on-the-fly [15:0] read-write CLK_GPOUT1_SELECTED Indicates which src is currently selected (one-hot) 0x14 0x00000001 CLK_GPOUT1_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only CLK_GPOUT2_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x18 0x00000000 ENABLED clock generator is enabled [28:28] read-only NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors, can be changed on-the-fly [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 clksrc_pll_usb_primary_ref_opcg 4 rosc_clksrc_ph 5 xosc_clksrc 6 lposc_clksrc 7 clk_sys 8 clk_usb 9 clk_adc 10 clk_ref 11 clk_peri 12 clk_hstx 13 otp_clk2fc 14 CLK_GPOUT2_DIV 0x1C 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [31:16] read-write FRAC Fractional component of the divisor, can be changed on-the-fly [15:0] read-write CLK_GPOUT2_SELECTED Indicates which src is currently selected (one-hot) 0x20 0x00000001 CLK_GPOUT2_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only CLK_GPOUT3_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x24 0x00000000 ENABLED clock generator is enabled [28:28] read-only NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors, can be changed on-the-fly [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 clksrc_pll_usb_primary_ref_opcg 4 rosc_clksrc_ph 5 xosc_clksrc 6 lposc_clksrc 7 clk_sys 8 clk_usb 9 clk_adc 10 clk_ref 11 clk_peri 12 clk_hstx 13 otp_clk2fc 14 CLK_GPOUT3_DIV 0x28 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [31:16] read-write FRAC Fractional component of the divisor, can be changed on-the-fly [15:0] read-write CLK_GPOUT3_SELECTED Indicates which src is currently selected (one-hot) 0x2C 0x00000001 CLK_GPOUT3_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only CLK_REF_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x30 0x00000000 AUXSRC Selects the auxiliary clock source, will glitch when switching [6:5] read-write clksrc_pll_usb 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb_primary_ref_opcg 3 SRC Selects the clock source glitchlessly, can be changed on-the-fly [1:0] read-write rosc_clksrc_ph 0 clksrc_clk_ref_aux 1 xosc_clksrc 2 lposc_clksrc 3 CLK_REF_DIV 0x34 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [23:16] read-write CLK_REF_SELECTED Indicates which src is currently selected (one-hot) 0x38 0x00000001 CLK_REF_SELECTED The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. [3:0] read-only CLK_SYS_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x3C 0x00000000 AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clksrc_pll_sys 0 clksrc_pll_usb 1 rosc_clksrc 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 SRC Selects the clock source glitchlessly, can be changed on-the-fly [0:0] read-write clk_ref 0 clksrc_clk_sys_aux 1 CLK_SYS_DIV 0x40 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [31:16] read-write FRAC Fractional component of the divisor, can be changed on-the-fly [15:0] read-write CLK_SYS_SELECTED Indicates which src is currently selected (one-hot) 0x44 0x00000001 CLK_SYS_SELECTED The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. [1:0] read-only CLK_PERI_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x48 0x00000000 ENABLED clock generator is enabled [28:28] read-only ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clk_sys 0 clksrc_pll_sys 1 clksrc_pll_usb 2 rosc_clksrc_ph 3 xosc_clksrc 4 clksrc_gpin0 5 clksrc_gpin1 6 CLK_PERI_DIV 0x4C 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [17:16] read-write CLK_PERI_SELECTED Indicates which src is currently selected (one-hot) 0x50 0x00000001 CLK_PERI_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only CLK_HSTX_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x54 0x00000000 ENABLED clock generator is enabled [28:28] read-only NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clk_sys 0 clksrc_pll_sys 1 clksrc_pll_usb 2 clksrc_gpin0 3 clksrc_gpin1 4 CLK_HSTX_DIV 0x58 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [17:16] read-write CLK_HSTX_SELECTED Indicates which src is currently selected (one-hot) 0x5C 0x00000001 CLK_HSTX_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only CLK_USB_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x60 0x00000000 ENABLED clock generator is enabled [28:28] read-only NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 CLK_USB_DIV 0x64 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [19:16] read-write CLK_USB_SELECTED Indicates which src is currently selected (one-hot) 0x68 0x00000001 CLK_USB_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only CLK_ADC_CTRL Clock control, can be changed on-the-fly (except for auxsrc) 0x6C 0x00000000 ENABLED clock generator is enabled [28:28] read-only NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator, enable must be set low before deasserting kill [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 CLK_ADC_DIV 0x70 0x00010000 INT Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly [19:16] read-write CLK_ADC_SELECTED Indicates which src is currently selected (one-hot) 0x74 0x00000001 CLK_ADC_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [0:0] read-only DFTCLK_XOSC_CTRL 0x78 0x00000000 SRC [1:0] read-write NULL 0 clksrc_pll_usb_primary 1 clksrc_gpin0 2 DFTCLK_ROSC_CTRL 0x7C 0x00000000 SRC [1:0] read-write NULL 0 clksrc_pll_sys_primary_rosc 1 clksrc_gpin1 2 DFTCLK_LPOSC_CTRL 0x80 0x00000000 SRC [1:0] read-write NULL 0 clksrc_pll_usb_primary_lposc 1 clksrc_gpin1 2 CLK_SYS_RESUS_CTRL 0x84 0x000000FF CLEAR For clearing the resus after the fault that triggered it has been corrected [16:16] read-write FRCE Force a resus, for test purposes only [12:12] read-write ENABLE Enable resus [8:8] read-write TIMEOUT This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq [7:0] read-write CLK_SYS_RESUS_STATUS 0x88 0x00000000 RESUSSED Clock has been resuscitated, correct the error then send ctrl_clear=1 [0:0] read-only FC0_REF_KHZ Reference clock frequency in kHz 0x8C 0x00000000 FC0_REF_KHZ [19:0] read-write FC0_MIN_KHZ Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags 0x90 0x00000000 FC0_MIN_KHZ [24:0] read-write FC0_MAX_KHZ Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags 0x94 0x01FFFFFF FC0_MAX_KHZ [24:0] read-write FC0_DELAY Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period 0x98 0x00000001 FC0_DELAY [2:0] read-write FC0_INTERVAL The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us 0x9C 0x00000008 FC0_INTERVAL [3:0] read-write FC0_SRC Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count 0xA0 0x00000000 FC0_SRC [7:0] read-write NULL 0 pll_sys_clksrc_primary 1 pll_usb_clksrc_primary 2 rosc_clksrc 3 rosc_clksrc_ph 4 xosc_clksrc 5 clksrc_gpin0 6 clksrc_gpin1 7 clk_ref 8 clk_sys 9 clk_peri 10 clk_usb 11 clk_adc 12 clk_hstx 13 lposc_clksrc 14 otp_clk2fc 15 pll_usb_clksrc_primary_dft 16 FC0_STATUS Frequency counter status 0xA4 0x00000000 DIED Test clock stopped during test [28:28] read-only FAST Test clock faster than expected, only valid when status_done=1 [24:24] read-only SLOW Test clock slower than expected, only valid when status_done=1 [20:20] read-only FAIL Test failed [16:16] read-only WAITING Waiting for test clock to start [12:12] read-only RUNNING Test running [8:8] read-only DONE Test complete [4:4] read-only PASS Test passed [0:0] read-only FC0_RESULT Result of frequency measurement, only valid when status_done=1 0xA8 0x00000000 KHZ [29:5] read-only FRAC [4:0] read-only WAKE_EN0 enable clock in wake mode 0xAC 0xFFFFFFFF CLK_SYS_SIO [31:31] read-write CLK_SYS_SHA256 [30:30] read-write CLK_SYS_PSM [29:29] read-write CLK_SYS_ROSC [28:28] read-write CLK_SYS_ROM [27:27] read-write CLK_SYS_RESETS [26:26] read-write CLK_SYS_PWM [25:25] read-write CLK_SYS_POWMAN [24:24] read-write CLK_REF_POWMAN [23:23] read-write CLK_SYS_PLL_USB [22:22] read-write CLK_SYS_PLL_SYS [21:21] read-write CLK_SYS_PIO2 [20:20] read-write CLK_SYS_PIO1 [19:19] read-write CLK_SYS_PIO0 [18:18] read-write CLK_SYS_PADS [17:17] read-write CLK_SYS_OTP [16:16] read-write CLK_REF_OTP [15:15] read-write CLK_SYS_JTAG [14:14] read-write CLK_SYS_IO [13:13] read-write CLK_SYS_I2C1 [12:12] read-write CLK_SYS_I2C0 [11:11] read-write CLK_SYS_HSTX [10:10] read-write CLK_HSTX [9:9] read-write CLK_SYS_GLITCH_DETECTOR [8:8] read-write CLK_SYS_DMA [7:7] read-write CLK_SYS_BUSFABRIC [6:6] read-write CLK_SYS_BUSCTRL [5:5] read-write CLK_SYS_BOOTRAM [4:4] read-write CLK_SYS_ADC [3:3] read-write CLK_ADC [2:2] read-write CLK_SYS_ACCESSCTRL [1:1] read-write CLK_SYS_CLOCKS [0:0] read-write WAKE_EN1 enable clock in wake mode 0xB0 0x7FFFFFFF CLK_SYS_XOSC [30:30] read-write CLK_SYS_XIP [29:29] read-write CLK_SYS_WATCHDOG [28:28] read-write CLK_USB [27:27] read-write CLK_SYS_USBCTRL [26:26] read-write CLK_SYS_UART1 [25:25] read-write CLK_PERI_UART1 [24:24] read-write CLK_SYS_UART0 [23:23] read-write CLK_PERI_UART0 [22:22] read-write CLK_SYS_TRNG [21:21] read-write CLK_SYS_TIMER1 [20:20] read-write CLK_SYS_TIMER0 [19:19] read-write CLK_SYS_TICKS [18:18] read-write CLK_REF_TICKS [17:17] read-write CLK_SYS_TBMAN [16:16] read-write CLK_SYS_SYSINFO [15:15] read-write CLK_SYS_SYSCFG [14:14] read-write CLK_SYS_SRAM9 [13:13] read-write CLK_SYS_SRAM8 [12:12] read-write CLK_SYS_SRAM7 [11:11] read-write CLK_SYS_SRAM6 [10:10] read-write CLK_SYS_SRAM5 [9:9] read-write CLK_SYS_SRAM4 [8:8] read-write CLK_SYS_SRAM3 [7:7] read-write CLK_SYS_SRAM2 [6:6] read-write CLK_SYS_SRAM1 [5:5] read-write CLK_SYS_SRAM0 [4:4] read-write CLK_SYS_SPI1 [3:3] read-write CLK_PERI_SPI1 [2:2] read-write CLK_SYS_SPI0 [1:1] read-write CLK_PERI_SPI0 [0:0] read-write SLEEP_EN0 enable clock in sleep mode 0xB4 0xFFFFFFFF CLK_SYS_SIO [31:31] read-write CLK_SYS_SHA256 [30:30] read-write CLK_SYS_PSM [29:29] read-write CLK_SYS_ROSC [28:28] read-write CLK_SYS_ROM [27:27] read-write CLK_SYS_RESETS [26:26] read-write CLK_SYS_PWM [25:25] read-write CLK_SYS_POWMAN [24:24] read-write CLK_REF_POWMAN [23:23] read-write CLK_SYS_PLL_USB [22:22] read-write CLK_SYS_PLL_SYS [21:21] read-write CLK_SYS_PIO2 [20:20] read-write CLK_SYS_PIO1 [19:19] read-write CLK_SYS_PIO0 [18:18] read-write CLK_SYS_PADS [17:17] read-write CLK_SYS_OTP [16:16] read-write CLK_REF_OTP [15:15] read-write CLK_SYS_JTAG [14:14] read-write CLK_SYS_IO [13:13] read-write CLK_SYS_I2C1 [12:12] read-write CLK_SYS_I2C0 [11:11] read-write CLK_SYS_HSTX [10:10] read-write CLK_HSTX [9:9] read-write CLK_SYS_GLITCH_DETECTOR [8:8] read-write CLK_SYS_DMA [7:7] read-write CLK_SYS_BUSFABRIC [6:6] read-write CLK_SYS_BUSCTRL [5:5] read-write CLK_SYS_BOOTRAM [4:4] read-write CLK_SYS_ADC [3:3] read-write CLK_ADC [2:2] read-write CLK_SYS_ACCESSCTRL [1:1] read-write CLK_SYS_CLOCKS [0:0] read-write SLEEP_EN1 enable clock in sleep mode 0xB8 0x7FFFFFFF CLK_SYS_XOSC [30:30] read-write CLK_SYS_XIP [29:29] read-write CLK_SYS_WATCHDOG [28:28] read-write CLK_USB [27:27] read-write CLK_SYS_USBCTRL [26:26] read-write CLK_SYS_UART1 [25:25] read-write CLK_PERI_UART1 [24:24] read-write CLK_SYS_UART0 [23:23] read-write CLK_PERI_UART0 [22:22] read-write CLK_SYS_TRNG [21:21] read-write CLK_SYS_TIMER1 [20:20] read-write CLK_SYS_TIMER0 [19:19] read-write CLK_SYS_TICKS [18:18] read-write CLK_REF_TICKS [17:17] read-write CLK_SYS_TBMAN [16:16] read-write CLK_SYS_SYSINFO [15:15] read-write CLK_SYS_SYSCFG [14:14] read-write CLK_SYS_SRAM9 [13:13] read-write CLK_SYS_SRAM8 [12:12] read-write CLK_SYS_SRAM7 [11:11] read-write CLK_SYS_SRAM6 [10:10] read-write CLK_SYS_SRAM5 [9:9] read-write CLK_SYS_SRAM4 [8:8] read-write CLK_SYS_SRAM3 [7:7] read-write CLK_SYS_SRAM2 [6:6] read-write CLK_SYS_SRAM1 [5:5] read-write CLK_SYS_SRAM0 [4:4] read-write CLK_SYS_SPI1 [3:3] read-write CLK_PERI_SPI1 [2:2] read-write CLK_SYS_SPI0 [1:1] read-write CLK_PERI_SPI0 [0:0] read-write ENABLED0 indicates the state of the clock enable 0xBC 0x00000000 CLK_SYS_SIO [31:31] read-only CLK_SYS_SHA256 [30:30] read-only CLK_SYS_PSM [29:29] read-only CLK_SYS_ROSC [28:28] read-only CLK_SYS_ROM [27:27] read-only CLK_SYS_RESETS [26:26] read-only CLK_SYS_PWM [25:25] read-only CLK_SYS_POWMAN [24:24] read-only CLK_REF_POWMAN [23:23] read-only CLK_SYS_PLL_USB [22:22] read-only CLK_SYS_PLL_SYS [21:21] read-only CLK_SYS_PIO2 [20:20] read-only CLK_SYS_PIO1 [19:19] read-only CLK_SYS_PIO0 [18:18] read-only CLK_SYS_PADS [17:17] read-only CLK_SYS_OTP [16:16] read-only CLK_REF_OTP [15:15] read-only CLK_SYS_JTAG [14:14] read-only CLK_SYS_IO [13:13] read-only CLK_SYS_I2C1 [12:12] read-only CLK_SYS_I2C0 [11:11] read-only CLK_SYS_HSTX [10:10] read-only CLK_HSTX [9:9] read-only CLK_SYS_GLITCH_DETECTOR [8:8] read-only CLK_SYS_DMA [7:7] read-only CLK_SYS_BUSFABRIC [6:6] read-only CLK_SYS_BUSCTRL [5:5] read-only CLK_SYS_BOOTRAM [4:4] read-only CLK_SYS_ADC [3:3] read-only CLK_ADC [2:2] read-only CLK_SYS_ACCESSCTRL [1:1] read-only CLK_SYS_CLOCKS [0:0] read-only ENABLED1 indicates the state of the clock enable 0xC0 0x00000000 CLK_SYS_XOSC [30:30] read-only CLK_SYS_XIP [29:29] read-only CLK_SYS_WATCHDOG [28:28] read-only CLK_USB [27:27] read-only CLK_SYS_USBCTRL [26:26] read-only CLK_SYS_UART1 [25:25] read-only CLK_PERI_UART1 [24:24] read-only CLK_SYS_UART0 [23:23] read-only CLK_PERI_UART0 [22:22] read-only CLK_SYS_TRNG [21:21] read-only CLK_SYS_TIMER1 [20:20] read-only CLK_SYS_TIMER0 [19:19] read-only CLK_SYS_TICKS [18:18] read-only CLK_REF_TICKS [17:17] read-only CLK_SYS_TBMAN [16:16] read-only CLK_SYS_SYSINFO [15:15] read-only CLK_SYS_SYSCFG [14:14] read-only CLK_SYS_SRAM9 [13:13] read-only CLK_SYS_SRAM8 [12:12] read-only CLK_SYS_SRAM7 [11:11] read-only CLK_SYS_SRAM6 [10:10] read-only CLK_SYS_SRAM5 [9:9] read-only CLK_SYS_SRAM4 [8:8] read-only CLK_SYS_SRAM3 [7:7] read-only CLK_SYS_SRAM2 [6:6] read-only CLK_SYS_SRAM1 [5:5] read-only CLK_SYS_SRAM0 [4:4] read-only CLK_SYS_SPI1 [3:3] read-only CLK_PERI_SPI1 [2:2] read-only CLK_SYS_SPI0 [1:1] read-only CLK_PERI_SPI0 [0:0] read-only INTR Raw Interrupts 0xC4 0x00000000 CLK_SYS_RESUS [0:0] read-only INTE Interrupt Enable 0xC8 0x00000000 CLK_SYS_RESUS [0:0] read-write INTF Interrupt Force 0xCC 0x00000000 CLK_SYS_RESUS [0:0] read-write INTS Interrupt status after masking & forcing 0xD0 0x00000000 CLK_SYS_RESUS [0:0] read-only TICKS 0x40108000 0x0 0x48 registers 6 0xC PROC0,PROC1,TIMER0,TIMER1,WATCHDOG,RISCV TICK%s Cluster TICK%s, containing *_CTRL, *_CYCLES, *_COUNT 0x0 CTRL Controls the tick generator 0x0 0x00000000 RUNNING Is the tick generator running? [1:1] read-only ENABLE start / stop tick generation [0:0] read-write CYCLES 0x4 0x00000000 PROC0_CYCLES Total number of clk_tick cycles before the next tick. [8:0] read-write COUNT 0x8 0x00000000 PROC0_COUNT Count down timer: the remaining number clk_tick cycles before the next tick is generated. [8:0] read-only PADS_BANK0 0x40038000 0x0 0xCC registers VOLTAGE_SELECT Voltage select. Per bank control 0x0 0x00000000 VOLTAGE_SELECT [0:0] read-write 3v3 Set voltage to 3.3V (DVDD >= 2V5) 0 1v8 Set voltage to 1.8V (DVDD <= 1V8) 1 48 0x4 0-47 GPIO%s 0x4 0x00000116 ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write SWCLK 0xC4 0x0000005A ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write SWD 0xC8 0x0000005A ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write PADS_QSPI 0x40040000 0x0 0x1C registers VOLTAGE_SELECT Voltage select. Per bank control 0x0 0x00000000 VOLTAGE_SELECT [0:0] read-write 3v3 Set voltage to 3.3V (DVDD >= 2V5) 0 1v8 Set voltage to 1.8V (DVDD <= 1V8) 1 GPIO_QSPI_SCLK 0x4 0x00000156 ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD0 0x8 0x00000156 ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD1 0xC 0x00000156 ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD2 0x10 0x0000015A ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD3 0x14 0x0000015A ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SS 0x18 0x0000015A ISO Pad isolation control. Remove this once the pad is configured by software. [8:8] read-write OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write IO_QSPI 0x40030000 0x0 0x240 registers IO_IRQ_QSPI 23 IO_IRQ_QSPI_NS 24 USBPHY_DP_STATUS 0x0 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only INFROMPAD input signal from pad, before filtering and override are applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only USBPHY_DP_CTRL 0x4 0x0000001F IRQOVER [29:28] read-write NORMAL don't invert the interrupt 0 INVERT invert the interrupt 1 LOW drive interrupt low 2 HIGH drive interrupt high 3 INOVER [17:16] read-write NORMAL don't invert the peri input 0 INVERT invert the peri input 1 LOW drive peri input low 2 HIGH drive peri input high 3 OEOVER [15:14] read-write NORMAL drive output enable from peripheral signal selected by funcsel 0 INVERT drive output enable from inverse of peripheral signal selected by funcsel 1 DISABLE disable output 2 ENABLE enable output 3 OUTOVER [13:12] read-write NORMAL drive output from peripheral signal selected by funcsel 0 INVERT drive output from inverse of peripheral signal selected by funcsel 1 LOW drive output low 2 HIGH drive output high 3 FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write uart1_tx 2 i2c0_sda 3 siob_proc_56 5 null 31 USBPHY_DM_STATUS 0x8 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only INFROMPAD input signal from pad, before filtering and override are applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only USBPHY_DM_CTRL 0xC 0x0000001F IRQOVER [29:28] read-write NORMAL don't invert the interrupt 0 INVERT invert the interrupt 1 LOW drive interrupt low 2 HIGH drive interrupt high 3 INOVER [17:16] read-write NORMAL don't invert the peri input 0 INVERT invert the peri input 1 LOW drive peri input low 2 HIGH drive peri input high 3 OEOVER [15:14] read-write NORMAL drive output enable from peripheral signal selected by funcsel 0 INVERT drive output enable from inverse of peripheral signal selected by funcsel 1 DISABLE disable output 2 ENABLE enable output 3 OUTOVER [13:12] read-write NORMAL drive output from peripheral signal selected by funcsel 0 INVERT drive output from inverse of peripheral signal selected by funcsel 1 LOW drive output low 2 HIGH drive output high 3 FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write uart1_rx 2 i2c0_scl 3 siob_proc_57 5 null 31 6 0x8 SCLK,SS,SD0,SD1,SD2,SD3 GPIO_QSPI%s Cluster GPIO_QSPI%s, containing GPIO_QSPI_*_STATUS, GPIO_QSPI_*_CTRL 0x10 GPIO_STATUS 0x0 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only INFROMPAD input signal from pad, before filtering and override are applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only GPIO_CTRL 0x4 0x0000001F IRQOVER [29:28] read-write NORMAL don't invert the interrupt 0 INVERT invert the interrupt 1 LOW drive interrupt low 2 HIGH drive interrupt high 3 INOVER [17:16] read-write NORMAL don't invert the peri input 0 INVERT invert the peri input 1 LOW drive peri input low 2 HIGH drive peri input high 3 OEOVER [15:14] read-write NORMAL drive output enable from peripheral signal selected by funcsel 0 INVERT drive output enable from inverse of peripheral signal selected by funcsel 1 DISABLE disable output 2 ENABLE enable output 3 OUTOVER [13:12] read-write NORMAL drive output from peripheral signal selected by funcsel 0 INVERT drive output from inverse of peripheral signal selected by funcsel 1 LOW drive output low 2 HIGH drive output high 3 FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write xip_sclk 0 uart1_cts 2 i2c1_sda 3 siob_proc_58 5 uart1_tx 11 null 31 IRQSUMMARY_PROC0_SECURE 0x200 0x00000000 GPIO_QSPI_SD3 [7:7] read-only GPIO_QSPI_SD2 [6:6] read-only GPIO_QSPI_SD1 [5:5] read-only GPIO_QSPI_SD0 [4:4] read-only GPIO_QSPI_SS [3:3] read-only GPIO_QSPI_SCLK [2:2] read-only USBPHY_DM [1:1] read-only USBPHY_DP [0:0] read-only IRQSUMMARY_PROC0_NONSECURE 0x204 0x00000000 GPIO_QSPI_SD3 [7:7] read-only GPIO_QSPI_SD2 [6:6] read-only GPIO_QSPI_SD1 [5:5] read-only GPIO_QSPI_SD0 [4:4] read-only GPIO_QSPI_SS [3:3] read-only GPIO_QSPI_SCLK [2:2] read-only USBPHY_DM [1:1] read-only USBPHY_DP [0:0] read-only IRQSUMMARY_PROC1_SECURE 0x208 0x00000000 GPIO_QSPI_SD3 [7:7] read-only GPIO_QSPI_SD2 [6:6] read-only GPIO_QSPI_SD1 [5:5] read-only GPIO_QSPI_SD0 [4:4] read-only GPIO_QSPI_SS [3:3] read-only GPIO_QSPI_SCLK [2:2] read-only USBPHY_DM [1:1] read-only USBPHY_DP [0:0] read-only IRQSUMMARY_PROC1_NONSECURE 0x20C 0x00000000 GPIO_QSPI_SD3 [7:7] read-only GPIO_QSPI_SD2 [6:6] read-only GPIO_QSPI_SD1 [5:5] read-only GPIO_QSPI_SD0 [4:4] read-only GPIO_QSPI_SS [3:3] read-only GPIO_QSPI_SCLK [2:2] read-only USBPHY_DM [1:1] read-only USBPHY_DP [0:0] read-only IRQSUMMARY_DORMANT_WAKE_SECURE 0x210 0x00000000 GPIO_QSPI_SD3 [7:7] read-only GPIO_QSPI_SD2 [6:6] read-only GPIO_QSPI_SD1 [5:5] read-only GPIO_QSPI_SD0 [4:4] read-only GPIO_QSPI_SS [3:3] read-only GPIO_QSPI_SCLK [2:2] read-only USBPHY_DM [1:1] read-only USBPHY_DP [0:0] read-only IRQSUMMARY_DORMANT_WAKE_NONSECURE 0x214 0x00000000 GPIO_QSPI_SD3 [7:7] read-only GPIO_QSPI_SD2 [6:6] read-only GPIO_QSPI_SD1 [5:5] read-only GPIO_QSPI_SD0 [4:4] read-only GPIO_QSPI_SS [3:3] read-only GPIO_QSPI_SCLK [2:2] read-only USBPHY_DM [1:1] read-only USBPHY_DP [0:0] read-only INTR Raw Interrupts 0x218 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-write oneToClear GPIO_QSPI_SD3_EDGE_LOW [30:30] read-write oneToClear GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-only GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-only GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-write oneToClear GPIO_QSPI_SD2_EDGE_LOW [26:26] read-write oneToClear GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-only GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-only GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-write oneToClear GPIO_QSPI_SD1_EDGE_LOW [22:22] read-write oneToClear GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-write oneToClear GPIO_QSPI_SD0_EDGE_LOW [18:18] read-write oneToClear GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-only GPIO_QSPI_SS_EDGE_HIGH [15:15] read-write oneToClear GPIO_QSPI_SS_EDGE_LOW [14:14] read-write oneToClear GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SS_LEVEL_LOW [12:12] read-only GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-write oneToClear GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-write oneToClear GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-only USBPHY_DM_EDGE_HIGH [7:7] read-write oneToClear USBPHY_DM_EDGE_LOW [6:6] read-write oneToClear USBPHY_DM_LEVEL_HIGH [5:5] read-only USBPHY_DM_LEVEL_LOW [4:4] read-only USBPHY_DP_EDGE_HIGH [3:3] read-write oneToClear USBPHY_DP_EDGE_LOW [2:2] read-write oneToClear USBPHY_DP_LEVEL_HIGH [1:1] read-only USBPHY_DP_LEVEL_LOW [0:0] read-only PROC0_INTE Interrupt Enable for proc0 0x21C 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-write GPIO_QSPI_SD3_EDGE_LOW [30:30] read-write GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-write GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-write GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-write GPIO_QSPI_SD2_EDGE_LOW [26:26] read-write GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-write GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-write GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD1_EDGE_LOW [22:22] read-write GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD0_EDGE_LOW [18:18] read-write GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-write GPIO_QSPI_SS_EDGE_HIGH [15:15] read-write GPIO_QSPI_SS_EDGE_LOW [14:14] read-write GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SS_LEVEL_LOW [12:12] read-write GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-write GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-write USBPHY_DM_EDGE_HIGH [7:7] read-write USBPHY_DM_EDGE_LOW [6:6] read-write USBPHY_DM_LEVEL_HIGH [5:5] read-write USBPHY_DM_LEVEL_LOW [4:4] read-write USBPHY_DP_EDGE_HIGH [3:3] read-write USBPHY_DP_EDGE_LOW [2:2] read-write USBPHY_DP_LEVEL_HIGH [1:1] read-write USBPHY_DP_LEVEL_LOW [0:0] read-write PROC0_INTF Interrupt Force for proc0 0x220 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-write GPIO_QSPI_SD3_EDGE_LOW [30:30] read-write GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-write GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-write GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-write GPIO_QSPI_SD2_EDGE_LOW [26:26] read-write GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-write GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-write GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD1_EDGE_LOW [22:22] read-write GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD0_EDGE_LOW [18:18] read-write GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-write GPIO_QSPI_SS_EDGE_HIGH [15:15] read-write GPIO_QSPI_SS_EDGE_LOW [14:14] read-write GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SS_LEVEL_LOW [12:12] read-write GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-write GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-write USBPHY_DM_EDGE_HIGH [7:7] read-write USBPHY_DM_EDGE_LOW [6:6] read-write USBPHY_DM_LEVEL_HIGH [5:5] read-write USBPHY_DM_LEVEL_LOW [4:4] read-write USBPHY_DP_EDGE_HIGH [3:3] read-write USBPHY_DP_EDGE_LOW [2:2] read-write USBPHY_DP_LEVEL_HIGH [1:1] read-write USBPHY_DP_LEVEL_LOW [0:0] read-write PROC0_INTS Interrupt status after masking & forcing for proc0 0x224 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-only GPIO_QSPI_SD3_EDGE_LOW [30:30] read-only GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-only GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-only GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-only GPIO_QSPI_SD2_EDGE_LOW [26:26] read-only GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-only GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-only GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-only GPIO_QSPI_SD1_EDGE_LOW [22:22] read-only GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-only GPIO_QSPI_SD0_EDGE_LOW [18:18] read-only GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-only GPIO_QSPI_SS_EDGE_HIGH [15:15] read-only GPIO_QSPI_SS_EDGE_LOW [14:14] read-only GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SS_LEVEL_LOW [12:12] read-only GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-only GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-only GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-only USBPHY_DM_EDGE_HIGH [7:7] read-only USBPHY_DM_EDGE_LOW [6:6] read-only USBPHY_DM_LEVEL_HIGH [5:5] read-only USBPHY_DM_LEVEL_LOW [4:4] read-only USBPHY_DP_EDGE_HIGH [3:3] read-only USBPHY_DP_EDGE_LOW [2:2] read-only USBPHY_DP_LEVEL_HIGH [1:1] read-only USBPHY_DP_LEVEL_LOW [0:0] read-only PROC1_INTE Interrupt Enable for proc1 0x228 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-write GPIO_QSPI_SD3_EDGE_LOW [30:30] read-write GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-write GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-write GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-write GPIO_QSPI_SD2_EDGE_LOW [26:26] read-write GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-write GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-write GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD1_EDGE_LOW [22:22] read-write GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD0_EDGE_LOW [18:18] read-write GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-write GPIO_QSPI_SS_EDGE_HIGH [15:15] read-write GPIO_QSPI_SS_EDGE_LOW [14:14] read-write GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SS_LEVEL_LOW [12:12] read-write GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-write GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-write USBPHY_DM_EDGE_HIGH [7:7] read-write USBPHY_DM_EDGE_LOW [6:6] read-write USBPHY_DM_LEVEL_HIGH [5:5] read-write USBPHY_DM_LEVEL_LOW [4:4] read-write USBPHY_DP_EDGE_HIGH [3:3] read-write USBPHY_DP_EDGE_LOW [2:2] read-write USBPHY_DP_LEVEL_HIGH [1:1] read-write USBPHY_DP_LEVEL_LOW [0:0] read-write PROC1_INTF Interrupt Force for proc1 0x22C 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-write GPIO_QSPI_SD3_EDGE_LOW [30:30] read-write GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-write GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-write GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-write GPIO_QSPI_SD2_EDGE_LOW [26:26] read-write GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-write GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-write GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD1_EDGE_LOW [22:22] read-write GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD0_EDGE_LOW [18:18] read-write GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-write GPIO_QSPI_SS_EDGE_HIGH [15:15] read-write GPIO_QSPI_SS_EDGE_LOW [14:14] read-write GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SS_LEVEL_LOW [12:12] read-write GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-write GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-write USBPHY_DM_EDGE_HIGH [7:7] read-write USBPHY_DM_EDGE_LOW [6:6] read-write USBPHY_DM_LEVEL_HIGH [5:5] read-write USBPHY_DM_LEVEL_LOW [4:4] read-write USBPHY_DP_EDGE_HIGH [3:3] read-write USBPHY_DP_EDGE_LOW [2:2] read-write USBPHY_DP_LEVEL_HIGH [1:1] read-write USBPHY_DP_LEVEL_LOW [0:0] read-write PROC1_INTS Interrupt status after masking & forcing for proc1 0x230 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-only GPIO_QSPI_SD3_EDGE_LOW [30:30] read-only GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-only GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-only GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-only GPIO_QSPI_SD2_EDGE_LOW [26:26] read-only GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-only GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-only GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-only GPIO_QSPI_SD1_EDGE_LOW [22:22] read-only GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-only GPIO_QSPI_SD0_EDGE_LOW [18:18] read-only GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-only GPIO_QSPI_SS_EDGE_HIGH [15:15] read-only GPIO_QSPI_SS_EDGE_LOW [14:14] read-only GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SS_LEVEL_LOW [12:12] read-only GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-only GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-only GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-only USBPHY_DM_EDGE_HIGH [7:7] read-only USBPHY_DM_EDGE_LOW [6:6] read-only USBPHY_DM_LEVEL_HIGH [5:5] read-only USBPHY_DM_LEVEL_LOW [4:4] read-only USBPHY_DP_EDGE_HIGH [3:3] read-only USBPHY_DP_EDGE_LOW [2:2] read-only USBPHY_DP_LEVEL_HIGH [1:1] read-only USBPHY_DP_LEVEL_LOW [0:0] read-only DORMANT_WAKE_INTE Interrupt Enable for dormant_wake 0x234 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-write GPIO_QSPI_SD3_EDGE_LOW [30:30] read-write GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-write GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-write GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-write GPIO_QSPI_SD2_EDGE_LOW [26:26] read-write GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-write GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-write GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD1_EDGE_LOW [22:22] read-write GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD0_EDGE_LOW [18:18] read-write GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-write GPIO_QSPI_SS_EDGE_HIGH [15:15] read-write GPIO_QSPI_SS_EDGE_LOW [14:14] read-write GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SS_LEVEL_LOW [12:12] read-write GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-write GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-write USBPHY_DM_EDGE_HIGH [7:7] read-write USBPHY_DM_EDGE_LOW [6:6] read-write USBPHY_DM_LEVEL_HIGH [5:5] read-write USBPHY_DM_LEVEL_LOW [4:4] read-write USBPHY_DP_EDGE_HIGH [3:3] read-write USBPHY_DP_EDGE_LOW [2:2] read-write USBPHY_DP_LEVEL_HIGH [1:1] read-write USBPHY_DP_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTF Interrupt Force for dormant_wake 0x238 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-write GPIO_QSPI_SD3_EDGE_LOW [30:30] read-write GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-write GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-write GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-write GPIO_QSPI_SD2_EDGE_LOW [26:26] read-write GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-write GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-write GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD1_EDGE_LOW [22:22] read-write GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD0_EDGE_LOW [18:18] read-write GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-write GPIO_QSPI_SS_EDGE_HIGH [15:15] read-write GPIO_QSPI_SS_EDGE_LOW [14:14] read-write GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SS_LEVEL_LOW [12:12] read-write GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-write GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-write USBPHY_DM_EDGE_HIGH [7:7] read-write USBPHY_DM_EDGE_LOW [6:6] read-write USBPHY_DM_LEVEL_HIGH [5:5] read-write USBPHY_DM_LEVEL_LOW [4:4] read-write USBPHY_DP_EDGE_HIGH [3:3] read-write USBPHY_DP_EDGE_LOW [2:2] read-write USBPHY_DP_LEVEL_HIGH [1:1] read-write USBPHY_DP_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTS Interrupt status after masking & forcing for dormant_wake 0x23C 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [31:31] read-only GPIO_QSPI_SD3_EDGE_LOW [30:30] read-only GPIO_QSPI_SD3_LEVEL_HIGH [29:29] read-only GPIO_QSPI_SD3_LEVEL_LOW [28:28] read-only GPIO_QSPI_SD2_EDGE_HIGH [27:27] read-only GPIO_QSPI_SD2_EDGE_LOW [26:26] read-only GPIO_QSPI_SD2_LEVEL_HIGH [25:25] read-only GPIO_QSPI_SD2_LEVEL_LOW [24:24] read-only GPIO_QSPI_SD1_EDGE_HIGH [23:23] read-only GPIO_QSPI_SD1_EDGE_LOW [22:22] read-only GPIO_QSPI_SD1_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD1_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD0_EDGE_HIGH [19:19] read-only GPIO_QSPI_SD0_EDGE_LOW [18:18] read-only GPIO_QSPI_SD0_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD0_LEVEL_LOW [16:16] read-only GPIO_QSPI_SS_EDGE_HIGH [15:15] read-only GPIO_QSPI_SS_EDGE_LOW [14:14] read-only GPIO_QSPI_SS_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SS_LEVEL_LOW [12:12] read-only GPIO_QSPI_SCLK_EDGE_HIGH [11:11] read-only GPIO_QSPI_SCLK_EDGE_LOW [10:10] read-only GPIO_QSPI_SCLK_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SCLK_LEVEL_LOW [8:8] read-only USBPHY_DM_EDGE_HIGH [7:7] read-only USBPHY_DM_EDGE_LOW [6:6] read-only USBPHY_DM_LEVEL_HIGH [5:5] read-only USBPHY_DM_LEVEL_LOW [4:4] read-only USBPHY_DP_EDGE_HIGH [3:3] read-only USBPHY_DP_EDGE_LOW [2:2] read-only USBPHY_DP_LEVEL_HIGH [1:1] read-only USBPHY_DP_LEVEL_LOW [0:0] read-only IO_BANK0 0x40028000 0x0 0x320 registers IO_IRQ_BANK0 21 IO_IRQ_BANK0_NS 22 48 0x8 0-47 GPIO%s Cluster GPIO%s, containing GPIO*_STATUS, GPIO*_CTRL 0x0 GPIO_STATUS 0x0 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only INFROMPAD input signal from pad, before filtering and override are applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only GPIO_CTRL 0x4 0x0000001F IRQOVER [29:28] read-write NORMAL don't invert the interrupt 0 INVERT invert the interrupt 1 LOW drive interrupt low 2 HIGH drive interrupt high 3 INOVER [17:16] read-write NORMAL don't invert the peri input 0 INVERT invert the peri input 1 LOW drive peri input low 2 HIGH drive peri input high 3 OEOVER [15:14] read-write NORMAL drive output enable from peripheral signal selected by funcsel 0 INVERT drive output enable from inverse of peripheral signal selected by funcsel 1 DISABLE disable output 2 ENABLE enable output 3 OUTOVER [13:12] read-write NORMAL drive output from peripheral signal selected by funcsel 0 INVERT drive output from inverse of peripheral signal selected by funcsel 1 LOW drive output low 2 HIGH drive output high 3 FUNCSEL 0-31 -> selects pin function according to the GPIO table. Not all options are valid for all GPIO pins. [4:0] read-write FUNCSEL jtag Connect to JTAG peripheral 0 spi Connect to matching SPI peripheral 1 uart Connect to matching UART peripheral 2 i2c Connect to matching I2C peripheral 3 pwm Connect to matching PWM peripheral 4 sio Use as a GPIO pin (connect to SIO peripheral) 5 pio0 Connect to PIO0 peripheral 6 pio1 Connect to PIO1 peripheral 7 pio2 Connect to PIO2 peripheral 8 gpck Connect to GPCK peripheral 9 usb Connect to USB peripheral 10 uart_aux Connect to matching UART_AUX peripheral 11 null Connect to nothing 31 IRQSUMMARY_PROC0_SECURE0 0x200 0x00000000 GPIO31 [31:31] read-only GPIO30 [30:30] read-only GPIO29 [29:29] read-only GPIO28 [28:28] read-only GPIO27 [27:27] read-only GPIO26 [26:26] read-only GPIO25 [25:25] read-only GPIO24 [24:24] read-only GPIO23 [23:23] read-only GPIO22 [22:22] read-only GPIO21 [21:21] read-only GPIO20 [20:20] read-only GPIO19 [19:19] read-only GPIO18 [18:18] read-only GPIO17 [17:17] read-only GPIO16 [16:16] read-only GPIO15 [15:15] read-only GPIO14 [14:14] read-only GPIO13 [13:13] read-only GPIO12 [12:12] read-only GPIO11 [11:11] read-only GPIO10 [10:10] read-only GPIO9 [9:9] read-only GPIO8 [8:8] read-only GPIO7 [7:7] read-only GPIO6 [6:6] read-only GPIO5 [5:5] read-only GPIO4 [4:4] read-only GPIO3 [3:3] read-only GPIO2 [2:2] read-only GPIO1 [1:1] read-only GPIO0 [0:0] read-only IRQSUMMARY_PROC0_SECURE1 0x204 0x00000000 GPIO47 [15:15] read-only GPIO46 [14:14] read-only GPIO45 [13:13] read-only GPIO44 [12:12] read-only GPIO43 [11:11] read-only GPIO42 [10:10] read-only GPIO41 [9:9] read-only GPIO40 [8:8] read-only GPIO39 [7:7] read-only GPIO38 [6:6] read-only GPIO37 [5:5] read-only GPIO36 [4:4] read-only GPIO35 [3:3] read-only GPIO34 [2:2] read-only GPIO33 [1:1] read-only GPIO32 [0:0] read-only IRQSUMMARY_PROC0_NONSECURE0 0x208 0x00000000 GPIO31 [31:31] read-only GPIO30 [30:30] read-only GPIO29 [29:29] read-only GPIO28 [28:28] read-only GPIO27 [27:27] read-only GPIO26 [26:26] read-only GPIO25 [25:25] read-only GPIO24 [24:24] read-only GPIO23 [23:23] read-only GPIO22 [22:22] read-only GPIO21 [21:21] read-only GPIO20 [20:20] read-only GPIO19 [19:19] read-only GPIO18 [18:18] read-only GPIO17 [17:17] read-only GPIO16 [16:16] read-only GPIO15 [15:15] read-only GPIO14 [14:14] read-only GPIO13 [13:13] read-only GPIO12 [12:12] read-only GPIO11 [11:11] read-only GPIO10 [10:10] read-only GPIO9 [9:9] read-only GPIO8 [8:8] read-only GPIO7 [7:7] read-only GPIO6 [6:6] read-only GPIO5 [5:5] read-only GPIO4 [4:4] read-only GPIO3 [3:3] read-only GPIO2 [2:2] read-only GPIO1 [1:1] read-only GPIO0 [0:0] read-only IRQSUMMARY_PROC0_NONSECURE1 0x20C 0x00000000 GPIO47 [15:15] read-only GPIO46 [14:14] read-only GPIO45 [13:13] read-only GPIO44 [12:12] read-only GPIO43 [11:11] read-only GPIO42 [10:10] read-only GPIO41 [9:9] read-only GPIO40 [8:8] read-only GPIO39 [7:7] read-only GPIO38 [6:6] read-only GPIO37 [5:5] read-only GPIO36 [4:4] read-only GPIO35 [3:3] read-only GPIO34 [2:2] read-only GPIO33 [1:1] read-only GPIO32 [0:0] read-only IRQSUMMARY_PROC1_SECURE0 0x210 0x00000000 GPIO31 [31:31] read-only GPIO30 [30:30] read-only GPIO29 [29:29] read-only GPIO28 [28:28] read-only GPIO27 [27:27] read-only GPIO26 [26:26] read-only GPIO25 [25:25] read-only GPIO24 [24:24] read-only GPIO23 [23:23] read-only GPIO22 [22:22] read-only GPIO21 [21:21] read-only GPIO20 [20:20] read-only GPIO19 [19:19] read-only GPIO18 [18:18] read-only GPIO17 [17:17] read-only GPIO16 [16:16] read-only GPIO15 [15:15] read-only GPIO14 [14:14] read-only GPIO13 [13:13] read-only GPIO12 [12:12] read-only GPIO11 [11:11] read-only GPIO10 [10:10] read-only GPIO9 [9:9] read-only GPIO8 [8:8] read-only GPIO7 [7:7] read-only GPIO6 [6:6] read-only GPIO5 [5:5] read-only GPIO4 [4:4] read-only GPIO3 [3:3] read-only GPIO2 [2:2] read-only GPIO1 [1:1] read-only GPIO0 [0:0] read-only IRQSUMMARY_PROC1_SECURE1 0x214 0x00000000 GPIO47 [15:15] read-only GPIO46 [14:14] read-only GPIO45 [13:13] read-only GPIO44 [12:12] read-only GPIO43 [11:11] read-only GPIO42 [10:10] read-only GPIO41 [9:9] read-only GPIO40 [8:8] read-only GPIO39 [7:7] read-only GPIO38 [6:6] read-only GPIO37 [5:5] read-only GPIO36 [4:4] read-only GPIO35 [3:3] read-only GPIO34 [2:2] read-only GPIO33 [1:1] read-only GPIO32 [0:0] read-only IRQSUMMARY_PROC1_NONSECURE0 0x218 0x00000000 GPIO31 [31:31] read-only GPIO30 [30:30] read-only GPIO29 [29:29] read-only GPIO28 [28:28] read-only GPIO27 [27:27] read-only GPIO26 [26:26] read-only GPIO25 [25:25] read-only GPIO24 [24:24] read-only GPIO23 [23:23] read-only GPIO22 [22:22] read-only GPIO21 [21:21] read-only GPIO20 [20:20] read-only GPIO19 [19:19] read-only GPIO18 [18:18] read-only GPIO17 [17:17] read-only GPIO16 [16:16] read-only GPIO15 [15:15] read-only GPIO14 [14:14] read-only GPIO13 [13:13] read-only GPIO12 [12:12] read-only GPIO11 [11:11] read-only GPIO10 [10:10] read-only GPIO9 [9:9] read-only GPIO8 [8:8] read-only GPIO7 [7:7] read-only GPIO6 [6:6] read-only GPIO5 [5:5] read-only GPIO4 [4:4] read-only GPIO3 [3:3] read-only GPIO2 [2:2] read-only GPIO1 [1:1] read-only GPIO0 [0:0] read-only IRQSUMMARY_PROC1_NONSECURE1 0x21C 0x00000000 GPIO47 [15:15] read-only GPIO46 [14:14] read-only GPIO45 [13:13] read-only GPIO44 [12:12] read-only GPIO43 [11:11] read-only GPIO42 [10:10] read-only GPIO41 [9:9] read-only GPIO40 [8:8] read-only GPIO39 [7:7] read-only GPIO38 [6:6] read-only GPIO37 [5:5] read-only GPIO36 [4:4] read-only GPIO35 [3:3] read-only GPIO34 [2:2] read-only GPIO33 [1:1] read-only GPIO32 [0:0] read-only IRQSUMMARY_DORMANT_WAKE_SECURE0 0x220 0x00000000 GPIO31 [31:31] read-only GPIO30 [30:30] read-only GPIO29 [29:29] read-only GPIO28 [28:28] read-only GPIO27 [27:27] read-only GPIO26 [26:26] read-only GPIO25 [25:25] read-only GPIO24 [24:24] read-only GPIO23 [23:23] read-only GPIO22 [22:22] read-only GPIO21 [21:21] read-only GPIO20 [20:20] read-only GPIO19 [19:19] read-only GPIO18 [18:18] read-only GPIO17 [17:17] read-only GPIO16 [16:16] read-only GPIO15 [15:15] read-only GPIO14 [14:14] read-only GPIO13 [13:13] read-only GPIO12 [12:12] read-only GPIO11 [11:11] read-only GPIO10 [10:10] read-only GPIO9 [9:9] read-only GPIO8 [8:8] read-only GPIO7 [7:7] read-only GPIO6 [6:6] read-only GPIO5 [5:5] read-only GPIO4 [4:4] read-only GPIO3 [3:3] read-only GPIO2 [2:2] read-only GPIO1 [1:1] read-only GPIO0 [0:0] read-only IRQSUMMARY_DORMANT_WAKE_SECURE1 0x224 0x00000000 GPIO47 [15:15] read-only GPIO46 [14:14] read-only GPIO45 [13:13] read-only GPIO44 [12:12] read-only GPIO43 [11:11] read-only GPIO42 [10:10] read-only GPIO41 [9:9] read-only GPIO40 [8:8] read-only GPIO39 [7:7] read-only GPIO38 [6:6] read-only GPIO37 [5:5] read-only GPIO36 [4:4] read-only GPIO35 [3:3] read-only GPIO34 [2:2] read-only GPIO33 [1:1] read-only GPIO32 [0:0] read-only IRQSUMMARY_DORMANT_WAKE_NONSECURE0 0x228 0x00000000 GPIO31 [31:31] read-only GPIO30 [30:30] read-only GPIO29 [29:29] read-only GPIO28 [28:28] read-only GPIO27 [27:27] read-only GPIO26 [26:26] read-only GPIO25 [25:25] read-only GPIO24 [24:24] read-only GPIO23 [23:23] read-only GPIO22 [22:22] read-only GPIO21 [21:21] read-only GPIO20 [20:20] read-only GPIO19 [19:19] read-only GPIO18 [18:18] read-only GPIO17 [17:17] read-only GPIO16 [16:16] read-only GPIO15 [15:15] read-only GPIO14 [14:14] read-only GPIO13 [13:13] read-only GPIO12 [12:12] read-only GPIO11 [11:11] read-only GPIO10 [10:10] read-only GPIO9 [9:9] read-only GPIO8 [8:8] read-only GPIO7 [7:7] read-only GPIO6 [6:6] read-only GPIO5 [5:5] read-only GPIO4 [4:4] read-only GPIO3 [3:3] read-only GPIO2 [2:2] read-only GPIO1 [1:1] read-only GPIO0 [0:0] read-only IRQSUMMARY_DORMANT_WAKE_NONSECURE1 0x22C 0x00000000 GPIO47 [15:15] read-only GPIO46 [14:14] read-only GPIO45 [13:13] read-only GPIO44 [12:12] read-only GPIO43 [11:11] read-only GPIO42 [10:10] read-only GPIO41 [9:9] read-only GPIO40 [8:8] read-only GPIO39 [7:7] read-only GPIO38 [6:6] read-only GPIO37 [5:5] read-only GPIO36 [4:4] read-only GPIO35 [3:3] read-only GPIO34 [2:2] read-only GPIO33 [1:1] read-only GPIO32 [0:0] read-only 6 0x4 0-5 INTR%s Raw Interrupts 0x230 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write oneToClear GPIO7_EDGE_LOW [30:30] read-write oneToClear GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-write oneToClear GPIO6_EDGE_LOW [26:26] read-write oneToClear GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-write oneToClear GPIO5_EDGE_LOW [22:22] read-write oneToClear GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-write oneToClear GPIO4_EDGE_LOW [18:18] read-write oneToClear GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-write oneToClear GPIO3_EDGE_LOW [14:14] read-write oneToClear GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-write oneToClear GPIO2_EDGE_LOW [10:10] read-write oneToClear GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-write oneToClear GPIO1_EDGE_LOW [6:6] read-write oneToClear GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-write oneToClear GPIO0_EDGE_LOW [2:2] read-write oneToClear GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only 6 0x4 0-5 PROC0_INTE%s Interrupt Enable for proc0 0x248 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write 6 0x4 0-5 PROC0_INTF%s Interrupt Force for proc0 0x260 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write 6 0x4 0-5 PROC0_INTS%s Interrupt status after masking & forcing for proc0 0x278 0x00000000 GPIO7_EDGE_HIGH [31:31] read-only GPIO7_EDGE_LOW [30:30] read-only GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-only GPIO6_EDGE_LOW [26:26] read-only GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-only GPIO5_EDGE_LOW [22:22] read-only GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-only GPIO4_EDGE_LOW [18:18] read-only GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-only GPIO3_EDGE_LOW [14:14] read-only GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-only GPIO2_EDGE_LOW [10:10] read-only GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-only GPIO1_EDGE_LOW [6:6] read-only GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-only GPIO0_EDGE_LOW [2:2] read-only GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only 6 0x4 0-5 PROC1_INTE%s Interrupt Enable for proc1 0x290 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write 6 0x4 0-5 PROC1_INTF%s Interrupt Force for proc1 0x2A8 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write 6 0x4 0-5 PROC1_INTS%s Interrupt status after masking & forcing for proc1 0x2C0 0x00000000 GPIO7_EDGE_HIGH [31:31] read-only GPIO7_EDGE_LOW [30:30] read-only GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-only GPIO6_EDGE_LOW [26:26] read-only GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-only GPIO5_EDGE_LOW [22:22] read-only GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-only GPIO4_EDGE_LOW [18:18] read-only GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-only GPIO3_EDGE_LOW [14:14] read-only GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-only GPIO2_EDGE_LOW [10:10] read-only GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-only GPIO1_EDGE_LOW [6:6] read-only GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-only GPIO0_EDGE_LOW [2:2] read-only GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only 6 0x4 0-5 DORMANT_WAKE_INTE%s Interrupt Enable for dormant_wake 0x2D8 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write 6 0x4 0-5 DORMANT_WAKE_INTF%s Interrupt Force for dormant_wake 0x2F0 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write 6 0x4 0-5 DORMANT_WAKE_INTS%s Interrupt status after masking & forcing for dormant_wake 0x308 0x00000000 GPIO7_EDGE_HIGH [31:31] read-only GPIO7_EDGE_LOW [30:30] read-only GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-only GPIO6_EDGE_LOW [26:26] read-only GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-only GPIO5_EDGE_LOW [22:22] read-only GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-only GPIO4_EDGE_LOW [18:18] read-only GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-only GPIO3_EDGE_LOW [14:14] read-only GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-only GPIO2_EDGE_LOW [10:10] read-only GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-only GPIO1_EDGE_LOW [6:6] read-only GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-only GPIO0_EDGE_LOW [2:2] read-only GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only SYSINFO 0x40000000 0x0 0x18 registers CHIP_ID JEDEC JEP-106 compliant chip identifier. 0x0 0x00000001 REVISION [31:28] read-only PART [27:12] read-only MANUFACTURER [11:1] read-only STOP_BIT [0:0] read-only PACKAGE_SEL 0x4 0x00000000 PACKAGE_SEL [0:0] read-only PLATFORM Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM. 0x8 0x00000000 GATESIM [4:4] read-only BATCHSIM [3:3] read-only HDLSIM [2:2] read-only ASIC [1:1] read-only FPGA [0:0] read-only GITREF_RP2350 Git hash of the chip source. Used to identify chip version. 0x14 0x00000000 GITREF_RP2350 [31:0] read-only SHA256 SHA-256 hash function implementation 0x400F8000 0x0 0x28 registers CSR Control and status register 0x0 0x00001206 BSWAP Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around. [12:12] read-write DMA_SIZE Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block. [9:8] read-write 8bit 0 16bit 1 32bit 2 ERR_WDATA_NOT_RDY Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear. [4:4] read-write oneToClear SUM_VLD If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed. [2:2] read-only WDATA_RDY If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest. [1:1] read-only START Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers. [0:0] write-only WDATA Write data register 0x4 0x00000000 WDATA After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. After this, WDATA_RDY will return high, and more data can be written (if any). This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block. [31:0] write-only SUM0 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0x8 0x00000000 SUM0 [31:0] read-only SUM1 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0xC 0x00000000 SUM1 [31:0] read-only SUM2 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0x10 0x00000000 SUM2 [31:0] read-only SUM3 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0x14 0x00000000 SUM3 [31:0] read-only SUM4 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0x18 0x00000000 SUM4 [31:0] read-only SUM5 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0x1C 0x00000000 SUM5 [31:0] read-only SUM6 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0x20 0x00000000 SUM6 [31:0] read-only SUM7 256-bit checksum result. Contents are undefined when CSR_SUM_VLD is 0. 0x24 0x00000000 SUM7 [31:0] read-only HSTX_FIFO FIFO status and write access for HSTX 0x50600000 0x0 0x8 registers STAT FIFO status 0x0 0x00000000 WOF FIFO was written when full. Write 1 to clear. [10:10] read-write oneToClear EMPTY [9:9] read-only FULL [8:8] read-only LEVEL [7:0] read-only FIFO Write access to FIFO 0x4 0x00000000 FIFO [31:0] write-only HSTX_CTRL Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. 0x400C0000 0x0 0x2C registers CSR 0x0 0x10050600 CLKDIV Clock period of the generated clock, measured in HSTX clock cycles. Can be odd or even. The generated clock advances only on cycles where the shift register shifts. For example, a clkdiv of 5 would generate a complete output clock period for every 5 HSTX clocks (or every 10 half-clocks). A CLKDIV value of 0 is mapped to a period of 16 HSTX clock cycles. [31:28] read-write CLKPHASE Set the initial phase of the generated clock. A CLKPHASE of 0 means the clock is initially low, and the first rising edge occurs after one half period of the generated clock (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1 will advance the initial clock phase by one half clk_hstx period. For example, if CLKDIV=2 and CLKPHASE=1: * The clock will be initially low * The first rising edge will be 0.5 clk_hstx cycles after asserting first data * The first falling edge will be 1.5 clk_hstx cycles after asserting first data This configuration would be suitable for serialising at a bit rate of clk_hstx with a centre-aligned DDR clock. When the HSTX is halted by clearing CSR_EN, the clock generator will return to its initial phase as configured by the CLKPHASE field. Note CLKPHASE must be strictly less than double the value of CLKDIV (one full period), else its operation is undefined. [27:24] read-write N_SHIFTS Number of times to shift the shift register before refilling it from the FIFO. (A count of how many times it has been shifted, *not* the total shift distance.) A register value of 0 means shift 32 times. [20:16] read-write SHIFT How many bits to right-rotate the shift register by each cycle. The use of a rotate rather than a shift allows left shifts to be emulated, by subtracting the left-shift amount from 32. It also allows data to be repeated, when the product of SHIFT and N_SHIFTS is greater than 32. [12:8] read-write COUPLED_SEL Select which PIO to use for coupled mode operation. [6:5] read-write COUPLED_MODE Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked *directly* from the system clock (not just from some other clock source of the same frequency) for this synchronous interface to function correctly. When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24 through 31 will select bits from the 8-bit PIO-to-HSTX path, rather than shifter bits. Indices of 0 through 23 will still index the shift register as normal. The PIO outputs connected to the PIO-to-HSTX bus are those same outputs that would appear on the HSTX-capable pins if those pins' FUNCSELs were set to PIO instead of HSTX. For example, if HSTX is on GPIOs 12 through 19, then PIO outputs 12 through 19 are connected to the HSTX when coupled mode is engaged. [4:4] read-write EXPAND_EN Enable the command expander. When 0, raw FIFO data is passed directly to the output shift register. When 1, the command expander can perform simple operations such as run length decoding on data between the FIFO and the shift register. Do not change CXPD_EN whilst EN is set. It's safe to set CXPD_EN simultaneously with setting EN. [1:1] read-write EN When EN is 1, the HSTX will shift out data as it appears in the FIFO. As long as there is data, the HSTX shift register will shift once per clock cycle, and the frequency of popping from the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH. When EN is 0, the FIFO is not popped. The shift counter and clock generator are also reset to their initial state for as long as EN is low. Note the initial phase of the clock generator can be configured by the CLKPHASE field. Once the HSTX is enabled again, and data is pushed to the FIFO, the generated clock's first rising edge will be one half-period after the first data is launched. [0:0] read-write BIT0 Data control register for output bit 0 0x4 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write BIT1 Data control register for output bit 1 0x8 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write BIT2 Data control register for output bit 2 0xC 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write BIT3 Data control register for output bit 3 0x10 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write BIT4 Data control register for output bit 4 0x14 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write BIT5 Data control register for output bit 5 0x18 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write BIT6 Data control register for output bit 6 0x1C 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write BIT7 Data control register for output bit 7 0x20 0x00000000 CLK Connect this output to the generated clock, rather than the data shift register. SEL_P and SEL_N are ignored if this bit is set, but INV can still be set to generate an antiphase clock. [17:17] read-write INV Invert this data output (logical NOT) [16:16] read-write SEL_N Shift register data bit select for the second half of the HSTX clock cycle [12:8] read-write SEL_P Shift register data bit select for the first half of the HSTX clock cycle [4:0] read-write EXPAND_SHIFT Configure the optional shifter inside the command expander 0x24 0x01000100 ENC_N_SHIFTS Number of times to consume from the shift register before refilling it from the FIFO, when the current command is an encoded data command (e.g. TMDS). A register value of 0 means shift 32 times. [28:24] read-write ENC_SHIFT How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is an encoded data command (e.g. TMDS). [20:16] read-write RAW_N_SHIFTS Number of times to consume from the shift register before refilling it from the FIFO, when the current command is a raw data command. A register value of 0 means shift 32 times. [12:8] read-write RAW_SHIFT How many bits to right-rotate the shift register by each time data is pushed to the output shifter, when the current command is a raw data command. [4:0] read-write EXPAND_TMDS Configure the optional TMDS encoder inside the command expander 0x28 0x00000000 L2_NBITS Number of valid data bits for the lane 2 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. [23:21] read-write L2_ROT Right-rotate applied to the current shifter data before the lane 2 TMDS encoder. [20:16] read-write L1_NBITS Number of valid data bits for the lane 1 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. [15:13] read-write L1_ROT Right-rotate applied to the current shifter data before the lane 1 TMDS encoder. [12:8] read-write L0_NBITS Number of valid data bits for the lane 0 TMDS encoder, starting from bit 7 of the rotated data. Field values of 0 -> 7 encode counts of 1 -> 8 bits. [7:5] read-write L0_ROT Right-rotate applied to the current shifter data before the lane 0 TMDS encoder. [4:0] read-write EPPB Cortex-M33 EPPB vendor register block for RP2350 0xE0080000 0x0 0xC registers NMI_MASK0 NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset. 0x0 0x00000000 NMI_MASK0 [31:0] read-write NMI_MASK1 NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset. 0x4 0x00000000 NMI_MASK1 [19:0] read-write SLEEPCTRL Nonstandard sleep control register 0x8 0x00000002 WICENACK Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK. [2:2] read-only WICENREQ Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change. [1:1] read-write LIGHT_SLEEP By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request. [0:0] read-write PPB TEAL registers accessible through the debug interface 0xE0000000 0x0 0x43000 registers ITM_STIM0 Provides the interface for generating Instrumentation packets 0x0 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM1 Provides the interface for generating Instrumentation packets 0x4 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM2 Provides the interface for generating Instrumentation packets 0x8 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM3 Provides the interface for generating Instrumentation packets 0xC 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM4 Provides the interface for generating Instrumentation packets 0x10 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM5 Provides the interface for generating Instrumentation packets 0x14 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM6 Provides the interface for generating Instrumentation packets 0x18 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM7 Provides the interface for generating Instrumentation packets 0x1C 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM8 Provides the interface for generating Instrumentation packets 0x20 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM9 Provides the interface for generating Instrumentation packets 0x24 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM10 Provides the interface for generating Instrumentation packets 0x28 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM11 Provides the interface for generating Instrumentation packets 0x2C 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM12 Provides the interface for generating Instrumentation packets 0x30 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM13 Provides the interface for generating Instrumentation packets 0x34 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM14 Provides the interface for generating Instrumentation packets 0x38 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM15 Provides the interface for generating Instrumentation packets 0x3C 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM16 Provides the interface for generating Instrumentation packets 0x40 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM17 Provides the interface for generating Instrumentation packets 0x44 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM18 Provides the interface for generating Instrumentation packets 0x48 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM19 Provides the interface for generating Instrumentation packets 0x4C 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM20 Provides the interface for generating Instrumentation packets 0x50 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM21 Provides the interface for generating Instrumentation packets 0x54 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM22 Provides the interface for generating Instrumentation packets 0x58 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM23 Provides the interface for generating Instrumentation packets 0x5C 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM24 Provides the interface for generating Instrumentation packets 0x60 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM25 Provides the interface for generating Instrumentation packets 0x64 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM26 Provides the interface for generating Instrumentation packets 0x68 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM27 Provides the interface for generating Instrumentation packets 0x6C 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM28 Provides the interface for generating Instrumentation packets 0x70 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM29 Provides the interface for generating Instrumentation packets 0x74 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM30 Provides the interface for generating Instrumentation packets 0x78 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_STIM31 Provides the interface for generating Instrumentation packets 0x7C 0x00000000 STIMULUS Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated. [31:0] read-write ITM_TER0 Provide an individual enable bit for each ITM_STIM register 0xE00 0x00000000 STIMENA For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled [31:0] read-write ITM_TPR Controls which stimulus ports can be accessed by unprivileged code 0xE40 0x00000000 PRIVMASK Bit mask to enable tracing on ITM stimulus ports [3:0] read-write ITM_TCR Configures and controls transfers through the ITM interface 0xE80 0x00000000 BUSY Indicates whether the ITM is currently processing events [23:23] read-only TRACEBUSID Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field [22:16] read-write GTSFREQ Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps [11:10] read-write TSPRESCALE Local timestamp prescaler, used with the trace packet reference clock [9:8] read-write STALLENA Stall the PE to guarantee delivery of Data Trace packets. [5:5] read-write SWOENA Enables asynchronous clocking of the timestamp counter [4:4] read-write TXENA Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU [3:3] read-write SYNCENA Enables Synchronization packet transmission for a synchronous TPIU [2:2] read-write TSENA Enables Local timestamp generation [1:1] read-write ITMENA Enables the ITM [0:0] read-write INT_ATREADY Integration Mode: Read ATB Ready 0xEF0 0x00000000 AFVALID A read of this bit returns the value of AFVALID [1:1] read-only ATREADY A read of this bit returns the value of ATREADY [0:0] read-only INT_ATVALID Integration Mode: Write ATB Valid 0xEF8 0x00000000 AFREADY A write to this bit gives the value of AFREADY [1:1] read-write ATREADY A write to this bit gives the value of ATVALID [0:0] read-write ITM_ITCTRL Integration Mode Control Register 0xF00 0x00000000 IME Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing. [0:0] read-write ITM_DEVARCH Provides CoreSight discovery information for the ITM 0xFBC 0x47701A01 ARCHITECT Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. [31:21] read-only PRESENT Defines that the DEVARCH register is present [20:20] read-only REVISION Defines the architecture revision of the component [19:16] read-only ARCHVER Defines the architecture version of the component [15:12] read-only ARCHPART Defines the architecture of the component [11:0] read-only ITM_DEVTYPE Provides CoreSight discovery information for the ITM 0xFCC 0x00000043 SUB Component sub-type [7:4] read-only MAJOR Component major type [3:0] read-only ITM_PIDR4 Provides CoreSight discovery information for the ITM 0xFD0 0x00000004 SIZE See CoreSight Architecture Specification [7:4] read-only DES_2 See CoreSight Architecture Specification [3:0] read-only ITM_PIDR5 Provides CoreSight discovery information for the ITM 0xFD4 0x00000000 ITM_PIDR5 [31:0] read-write ITM_PIDR6 Provides CoreSight discovery information for the ITM 0xFD8 0x00000000 ITM_PIDR6 [31:0] read-write ITM_PIDR7 Provides CoreSight discovery information for the ITM 0xFDC 0x00000000 ITM_PIDR7 [31:0] read-write ITM_PIDR0 Provides CoreSight discovery information for the ITM 0xFE0 0x00000021 PART_0 See CoreSight Architecture Specification [7:0] read-only ITM_PIDR1 Provides CoreSight discovery information for the ITM 0xFE4 0x000000BD DES_0 See CoreSight Architecture Specification [7:4] read-only PART_1 See CoreSight Architecture Specification [3:0] read-only ITM_PIDR2 Provides CoreSight discovery information for the ITM 0xFE8 0x0000000B REVISION See CoreSight Architecture Specification [7:4] read-only JEDEC See CoreSight Architecture Specification [3:3] read-only DES_1 See CoreSight Architecture Specification [2:0] read-only ITM_PIDR3 Provides CoreSight discovery information for the ITM 0xFEC 0x00000000 REVAND See CoreSight Architecture Specification [7:4] read-only CMOD See CoreSight Architecture Specification [3:0] read-only ITM_CIDR0 Provides CoreSight discovery information for the ITM 0xFF0 0x0000000D PRMBL_0 See CoreSight Architecture Specification [7:0] read-only ITM_CIDR1 Provides CoreSight discovery information for the ITM 0xFF4 0x00000090 CLASS See CoreSight Architecture Specification [7:4] read-only PRMBL_1 See CoreSight Architecture Specification [3:0] read-only ITM_CIDR2 Provides CoreSight discovery information for the ITM 0xFF8 0x00000005 PRMBL_2 See CoreSight Architecture Specification [7:0] read-only ITM_CIDR3 Provides CoreSight discovery information for the ITM 0xFFC 0x000000B1 PRMBL_3 See CoreSight Architecture Specification [7:0] read-only DWT_CTRL Provides configuration and status information for the DWT unit, and used to control features of the unit 0x1000 0x73741824 NUMCOMP Number of DWT comparators implemented [31:28] read-only NOTRCPKT Indicates whether the implementation does not support trace [27:27] read-only NOEXTTRIG Reserved, RAZ [26:26] read-only NOCYCCNT Indicates whether the implementation does not include a cycle counter [25:25] read-only NOPRFCNT Indicates whether the implementation does not include the profiling counters [24:24] read-only CYCDISS Controls whether the cycle counter is disabled in Secure state [23:23] read-write CYCEVTENA Enables Event Counter packet generation on POSTCNT underflow [22:22] read-write FOLDEVTENA Enables DWT_FOLDCNT counter [21:21] read-write LSUEVTENA Enables DWT_LSUCNT counter [20:20] read-write SLEEPEVTENA Enable DWT_SLEEPCNT counter [19:19] read-write EXCEVTENA Enables DWT_EXCCNT counter [18:18] read-write CPIEVTENA Enables DWT_CPICNT counter [17:17] read-write EXTTRCENA Enables generation of Exception Trace packets [16:16] read-write PCSAMPLENA Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation [12:12] read-write SYNCTAP Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate [11:10] read-write CYCTAP Selects the position of the POSTCNT tap on the CYCCNT counter [9:9] read-write POSTINIT Initial value for the POSTCNT counter [8:5] read-write POSTPRESET Reload value for the POSTCNT counter [4:1] read-write CYCCNTENA Enables CYCCNT [0:0] read-write DWT_CYCCNT Shows or sets the value of the processor cycle counter, CYCCNT 0x1004 0x00000000 CYCCNT Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero [31:0] read-write DWT_EXCCNT Counts the total cycles spent in exception processing 0x100C 0x00000000 EXCCNT Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. [7:0] read-write DWT_LSUCNT Increments on the additional cycles required to execute all load or store instructions 0x1014 0x00000000 LSUCNT Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. [7:0] read-write DWT_FOLDCNT Increments on the additional cycles required to execute all load or store instructions 0x1018 0x00000000 FOLDCNT Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one [7:0] read-write DWT_COMP0 Provides a reference value for use by watchpoint comparator 0 0x1020 0x00000000 DWT_COMP0 [31:0] read-write DWT_FUNCTION0 Controls the operation of watchpoint comparator 0 0x1028 0x58000000 ID Identifies the capabilities for MATCH for comparator *n [31:27] read-only MATCHED Set to 1 when the comparator matches [24:24] read-only DATAVSIZE Defines the size of the object being watched for by Data Value and Data Address comparators [11:10] read-write ACTION Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH [5:4] read-write MATCH Controls the type of match generated by this comparator [3:0] read-write DWT_COMP1 Provides a reference value for use by watchpoint comparator 1 0x1030 0x00000000 DWT_COMP1 [31:0] read-write DWT_FUNCTION1 Controls the operation of watchpoint comparator 1 0x1038 0x89000828 ID Identifies the capabilities for MATCH for comparator *n [31:27] read-only MATCHED Set to 1 when the comparator matches [24:24] read-only DATAVSIZE Defines the size of the object being watched for by Data Value and Data Address comparators [11:10] read-write ACTION Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH [5:4] read-write MATCH Controls the type of match generated by this comparator [3:0] read-write DWT_COMP2 Provides a reference value for use by watchpoint comparator 2 0x1040 0x00000000 DWT_COMP2 [31:0] read-write DWT_FUNCTION2 Controls the operation of watchpoint comparator 2 0x1048 0x50000000 ID Identifies the capabilities for MATCH for comparator *n [31:27] read-only MATCHED Set to 1 when the comparator matches [24:24] read-only DATAVSIZE Defines the size of the object being watched for by Data Value and Data Address comparators [11:10] read-write ACTION Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH [5:4] read-write MATCH Controls the type of match generated by this comparator [3:0] read-write DWT_COMP3 Provides a reference value for use by watchpoint comparator 3 0x1050 0x00000000 DWT_COMP3 [31:0] read-write DWT_FUNCTION3 Controls the operation of watchpoint comparator 3 0x1058 0x20000800 ID Identifies the capabilities for MATCH for comparator *n [31:27] read-only MATCHED Set to 1 when the comparator matches [24:24] read-only DATAVSIZE Defines the size of the object being watched for by Data Value and Data Address comparators [11:10] read-write ACTION Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH [5:4] read-write MATCH Controls the type of match generated by this comparator [3:0] read-write DWT_DEVARCH Provides CoreSight discovery information for the DWT 0x1FBC 0x47701A02 ARCHITECT Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. [31:21] read-only PRESENT Defines that the DEVARCH register is present [20:20] read-only REVISION Defines the architecture revision of the component [19:16] read-only ARCHVER Defines the architecture version of the component [15:12] read-only ARCHPART Defines the architecture of the component [11:0] read-only DWT_DEVTYPE Provides CoreSight discovery information for the DWT 0x1FCC 0x00000000 SUB Component sub-type [7:4] read-only MAJOR Component major type [3:0] read-only DWT_PIDR4 Provides CoreSight discovery information for the DWT 0x1FD0 0x00000004 SIZE See CoreSight Architecture Specification [7:4] read-only DES_2 See CoreSight Architecture Specification [3:0] read-only DWT_PIDR5 Provides CoreSight discovery information for the DWT 0x1FD4 0x00000000 DWT_PIDR5 [31:0] read-write DWT_PIDR6 Provides CoreSight discovery information for the DWT 0x1FD8 0x00000000 DWT_PIDR6 [31:0] read-write DWT_PIDR7 Provides CoreSight discovery information for the DWT 0x1FDC 0x00000000 DWT_PIDR7 [31:0] read-write DWT_PIDR0 Provides CoreSight discovery information for the DWT 0x1FE0 0x00000021 PART_0 See CoreSight Architecture Specification [7:0] read-only DWT_PIDR1 Provides CoreSight discovery information for the DWT 0x1FE4 0x000000BD DES_0 See CoreSight Architecture Specification [7:4] read-only PART_1 See CoreSight Architecture Specification [3:0] read-only DWT_PIDR2 Provides CoreSight discovery information for the DWT 0x1FE8 0x0000000B REVISION See CoreSight Architecture Specification [7:4] read-only JEDEC See CoreSight Architecture Specification [3:3] read-only DES_1 See CoreSight Architecture Specification [2:0] read-only DWT_PIDR3 Provides CoreSight discovery information for the DWT 0x1FEC 0x00000000 REVAND See CoreSight Architecture Specification [7:4] read-only CMOD See CoreSight Architecture Specification [3:0] read-only DWT_CIDR0 Provides CoreSight discovery information for the DWT 0x1FF0 0x0000000D PRMBL_0 See CoreSight Architecture Specification [7:0] read-only DWT_CIDR1 Provides CoreSight discovery information for the DWT 0x1FF4 0x00000090 CLASS See CoreSight Architecture Specification [7:4] read-only PRMBL_1 See CoreSight Architecture Specification [3:0] read-only DWT_CIDR2 Provides CoreSight discovery information for the DWT 0x1FF8 0x00000005 PRMBL_2 See CoreSight Architecture Specification [7:0] read-only DWT_CIDR3 Provides CoreSight discovery information for the DWT 0x1FFC 0x000000B1 PRMBL_3 See CoreSight Architecture Specification [7:0] read-only FP_CTRL Provides FPB implementation information, and the global enable for the FPB unit 0x2000 0x60005580 REV Flash Patch and Breakpoint Unit architecture revision [31:28] read-only NUM_CODE_14_12_ Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 [14:12] read-only NUM_LIT Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 [11:8] read-only NUM_CODE_7_4_ Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 [7:4] read-only KEY Writes to the FP_CTRL are ignored unless KEY is concurrently written to one [1:1] read-write ENABLE Enables the FPB [0:0] read-write FP_REMAP Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap 0x2004 0x00000000 RMPSPT Indicates whether the FPB unit supports the Flash Patch remap function [29:29] read-only REMAP Holds the bits[28:5] of the Flash Patch remap address [28:5] read-only FP_COMP0 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x2008 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_COMP1 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x200C 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_COMP2 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x2010 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_COMP3 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x2014 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_COMP4 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x2018 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_COMP5 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x201C 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_COMP6 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x2020 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_COMP7 Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator 0x2024 0x00000000 BE Selects between flashpatch and breakpoint functionality [0:0] read-write FP_DEVARCH Provides CoreSight discovery information for the FPB 0x2FBC 0x47701A03 ARCHITECT Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. [31:21] read-only PRESENT Defines that the DEVARCH register is present [20:20] read-only REVISION Defines the architecture revision of the component [19:16] read-only ARCHVER Defines the architecture version of the component [15:12] read-only ARCHPART Defines the architecture of the component [11:0] read-only FP_DEVTYPE Provides CoreSight discovery information for the FPB 0x2FCC 0x00000000 SUB Component sub-type [7:4] read-only MAJOR Component major type [3:0] read-only FP_PIDR4 Provides CoreSight discovery information for the FP 0x2FD0 0x00000004 SIZE See CoreSight Architecture Specification [7:4] read-only DES_2 See CoreSight Architecture Specification [3:0] read-only FP_PIDR5 Provides CoreSight discovery information for the FP 0x2FD4 0x00000000 FP_PIDR5 [31:0] read-write FP_PIDR6 Provides CoreSight discovery information for the FP 0x2FD8 0x00000000 FP_PIDR6 [31:0] read-write FP_PIDR7 Provides CoreSight discovery information for the FP 0x2FDC 0x00000000 FP_PIDR7 [31:0] read-write FP_PIDR0 Provides CoreSight discovery information for the FP 0x2FE0 0x00000021 PART_0 See CoreSight Architecture Specification [7:0] read-only FP_PIDR1 Provides CoreSight discovery information for the FP 0x2FE4 0x000000BD DES_0 See CoreSight Architecture Specification [7:4] read-only PART_1 See CoreSight Architecture Specification [3:0] read-only FP_PIDR2 Provides CoreSight discovery information for the FP 0x2FE8 0x0000000B REVISION See CoreSight Architecture Specification [7:4] read-only JEDEC See CoreSight Architecture Specification [3:3] read-only DES_1 See CoreSight Architecture Specification [2:0] read-only FP_PIDR3 Provides CoreSight discovery information for the FP 0x2FEC 0x00000000 REVAND See CoreSight Architecture Specification [7:4] read-only CMOD See CoreSight Architecture Specification [3:0] read-only FP_CIDR0 Provides CoreSight discovery information for the FP 0x2FF0 0x0000000D PRMBL_0 See CoreSight Architecture Specification [7:0] read-only FP_CIDR1 Provides CoreSight discovery information for the FP 0x2FF4 0x00000090 CLASS See CoreSight Architecture Specification [7:4] read-only PRMBL_1 See CoreSight Architecture Specification [3:0] read-only FP_CIDR2 Provides CoreSight discovery information for the FP 0x2FF8 0x00000005 PRMBL_2 See CoreSight Architecture Specification [7:0] read-only FP_CIDR3 Provides CoreSight discovery information for the FP 0x2FFC 0x000000B1 PRMBL_3 See CoreSight Architecture Specification [7:0] read-only ICTR Provides information about the interrupt controller 0xE004 0x00000001 INTLINESNUM Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM [3:0] read-only ACTLR Provides IMPLEMENTATION DEFINED configuration and control options 0xE008 0x00000000 EXTEXCLALL External Exclusives Allowed with no MPU [29:29] read-write DISITMATBFLUSH Disable ATB Flush [12:12] read-write FPEXCODIS Disable FPU exception outputs [10:10] read-write DISOOFP Disable out-of-order FP instruction completion [9:9] read-write DISFOLD Disable dual-issue. [2:2] read-write DISMCYCINT Disable dual-issue. [0:0] read-write SYST_CSR Use the SysTick Control and Status Register to enable the SysTick features. 0xE010 0x00000000 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. [16:16] read-only CLKSOURCE SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock. [2:2] read-write TICKINT Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request. [1:1] read-write ENABLE Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled. [0:0] read-write SYST_RVR Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. 0xE014 0x00000000 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0. [23:0] read-write SYST_CVR Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. 0xE018 0x00000000 CURRENT Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. [23:0] read-write SYST_CALIB Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. 0xE01C 0x00000000 NOREF If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. [31:31] read-only SKEW If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). [30:30] read-only TENMS An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. [23:0] read-only NVIC_ISER0 Enables or reads the enabled state of each group of 32 interrupts 0xE100 0x00000000 SETENA For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled [31:0] read-write NVIC_ISER1 Enables or reads the enabled state of each group of 32 interrupts 0xE104 0x00000000 SETENA For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled [31:0] read-write NVIC_ICER0 Clears or reads the enabled state of each group of 32 interrupts 0xE180 0x00000000 CLRENA For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled [31:0] read-write NVIC_ICER1 Clears or reads the enabled state of each group of 32 interrupts 0xE184 0x00000000 CLRENA For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled [31:0] read-write NVIC_ISPR0 Enables or reads the pending state of each group of 32 interrupts 0xE200 0x00000000 SETPEND For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending [31:0] read-write NVIC_ISPR1 Enables or reads the pending state of each group of 32 interrupts 0xE204 0x00000000 SETPEND For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending [31:0] read-write NVIC_ICPR0 Clears or reads the pending state of each group of 32 interrupts 0xE280 0x00000000 CLRPEND For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending [31:0] read-write NVIC_ICPR1 Clears or reads the pending state of each group of 32 interrupts 0xE284 0x00000000 CLRPEND For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending [31:0] read-write NVIC_IABR0 For each group of 32 interrupts, shows the active state of each interrupt 0xE300 0x00000000 ACTIVE For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m [31:0] read-write NVIC_IABR1 For each group of 32 interrupts, shows the active state of each interrupt 0xE304 0x00000000 ACTIVE For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m [31:0] read-write NVIC_ITNS0 For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state 0xE380 0x00000000 ITNS For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m [31:0] read-write NVIC_ITNS1 For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state 0xE384 0x00000000 ITNS For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m [31:0] read-write NVIC_IPR0 Sets or reads interrupt priorities 0xE400 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR1 Sets or reads interrupt priorities 0xE404 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR2 Sets or reads interrupt priorities 0xE408 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR3 Sets or reads interrupt priorities 0xE40C 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR4 Sets or reads interrupt priorities 0xE410 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR5 Sets or reads interrupt priorities 0xE414 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR6 Sets or reads interrupt priorities 0xE418 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR7 Sets or reads interrupt priorities 0xE41C 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR8 Sets or reads interrupt priorities 0xE420 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR9 Sets or reads interrupt priorities 0xE424 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR10 Sets or reads interrupt priorities 0xE428 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR11 Sets or reads interrupt priorities 0xE42C 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR12 Sets or reads interrupt priorities 0xE430 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR13 Sets or reads interrupt priorities 0xE434 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR14 Sets or reads interrupt priorities 0xE438 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write NVIC_IPR15 Sets or reads interrupt priorities 0xE43C 0x00000000 PRI_N3 For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt [31:28] read-write PRI_N2 For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt [23:20] read-write PRI_N1 For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt [15:12] read-write PRI_N0 For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt [7:4] read-write CPUID Provides identification information for the PE, including an implementer code for the device and a device ID number 0xED00 0x411FD210 IMPLEMENTER This field must hold an implementer code that has been assigned by ARM [31:24] read-only VARIANT IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product [23:20] read-only ARCHITECTURE Defines the Architecture implemented by the PE [19:16] read-only PARTNO IMPLEMENTATION DEFINED primary part number for the device [15:4] read-only REVISION IMPLEMENTATION DEFINED revision number for the device [3:0] read-only ICSR Controls and provides status information for NMI, PendSV, SysTick and interrupts 0xED04 0x00000000 PENDNMISET Indicates whether the NMI exception is pending [31:31] read-only PENDNMICLR Allows the NMI exception pend state to be cleared [30:30] read-write PENDSVSET Indicates whether the PendSV `FTSSS exception is pending [28:28] read-only PENDSVCLR Allows the PendSV exception pend state to be cleared `FTSSS [27:27] read-write PENDSTSET Indicates whether the SysTick `FTSSS exception is pending [26:26] read-only PENDSTCLR Allows the SysTick exception pend state to be cleared `FTSSS [25:25] read-write STTNS Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure [24:24] read-write ISRPREEMPT Indicates whether a pending exception will be serviced on exit from debug halt state [23:23] read-only ISRPENDING Indicates whether an external interrupt, generated by the NVIC, is pending [22:22] read-only VECTPENDING The exception number of the highest priority pending and enabled interrupt [20:12] read-only RETTOBASE In Handler mode, indicates whether there is more than one active exception [11:11] read-only VECTACTIVE The exception number of the current executing exception [8:0] read-only VTOR The VTOR indicates the offset of the vector table base address from memory address 0x00000000. 0xED08 0x00000000 TBLOFF Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map. [31:7] read-write AIRCR Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. 0xED0C 0x00000000 VECTKEY Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. [31:16] read-write ENDIANESS Data endianness implemented: 0 = Little-endian. [15:15] read-only PRIS Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled. 0 Priority ranges of Secure and Non-secure exceptions are identical. 1 Non-secure exceptions are de-prioritized. [14:14] read-write BFHFNMINS BusFault, HardFault, and NMI Non-secure enable. 0 BusFault, HardFault, and NMI are Secure. 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault. [13:13] read-write PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en [10:8] read-write SYSRESETREQS System reset request, Secure state only. 0 SYSRESETREQ functionality is available to both Security states. 1 SYSRESETREQ functionality is only available to Secure state. [3:3] read-write SYSRESETREQ Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. [2:2] read-write VECTCLRACTIVE Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. [1:1] read-write SCR System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. 0xED10 0x00000000 SEVONPEND Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. [4:4] read-write SLEEPDEEPS 0 SLEEPDEEP is available to both security states 1 SLEEPDEEP is only available to Secure state [3:3] read-write SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep. [2:2] read-write SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. [1:1] read-write CCR Sets or returns configuration and control data 0xED14 0x00000201 BP Enables program flow prediction `FTSSS [18:18] read-only IC This is a global enable bit for instruction caches in the selected Security state [17:17] read-only DC Enables data caching of all data accesses to Normal memory `FTSSS [16:16] read-only STKOFHFNMIGN Controls the effect of a stack limit violation while executing at a requested priority less than 0 [10:10] read-write RES1 Reserved, RES1 [9:9] read-only BFHFNMIGN Determines the effect of precise BusFaults on handlers running at a requested priority less than 0 [8:8] read-write DIV_0_TRP Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero [4:4] read-write UNALIGN_TRP Controls the trapping of unaligned word or halfword accesses [3:3] read-write USERSETMPEND Determines whether unprivileged accesses are permitted to pend interrupts via the STIR [1:1] read-write RES1_1 Reserved, RES1 [0:0] read-only SHPR1 Sets or returns priority for system handlers 4 - 7 0xED18 0x00000000 PRI_7_3 Priority of system handler 7, SecureFault [31:29] read-write PRI_6_3 Priority of system handler 6, SecureFault [23:21] read-write PRI_5_3 Priority of system handler 5, SecureFault [15:13] read-write PRI_4_3 Priority of system handler 4, SecureFault [7:5] read-write SHPR2 Sets or returns priority for system handlers 8 - 11 0xED1C 0x00000000 PRI_11_3 Priority of system handler 11, SecureFault [31:29] read-write PRI_10 Reserved, RES0 [23:16] read-only PRI_9 Reserved, RES0 [15:8] read-only PRI_8 Reserved, RES0 [7:0] read-only SHPR3 Sets or returns priority for system handlers 12 - 15 0xED20 0x00000000 PRI_15_3 Priority of system handler 15, SecureFault [31:29] read-write PRI_14_3 Priority of system handler 14, SecureFault [23:21] read-write PRI_13 Reserved, RES0 [15:8] read-only PRI_12_3 Priority of system handler 12, SecureFault [7:5] read-write SHCSR Provides access to the active and pending status of system exceptions 0xED24 0x00000000 HARDFAULTPENDED `IAAMO the pending state of the HardFault exception `CTTSSS [21:21] read-write SECUREFAULTPENDED `IAAMO the pending state of the SecureFault exception [20:20] read-write SECUREFAULTENA `DW the SecureFault exception is enabled [19:19] read-write USGFAULTENA `DW the UsageFault exception is enabled `FTSSS [18:18] read-write BUSFAULTENA `DW the BusFault exception is enabled [17:17] read-write MEMFAULTENA `DW the MemManage exception is enabled `FTSSS [16:16] read-write SVCALLPENDED `IAAMO the pending state of the SVCall exception `FTSSS [15:15] read-write BUSFAULTPENDED `IAAMO the pending state of the BusFault exception [14:14] read-write MEMFAULTPENDED `IAAMO the pending state of the MemManage exception `FTSSS [13:13] read-write USGFAULTPENDED The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS [12:12] read-write SYSTICKACT `IAAMO the active state of the SysTick exception `FTSSS [11:11] read-write PENDSVACT `IAAMO the active state of the PendSV exception `FTSSS [10:10] read-write MONITORACT `IAAMO the active state of the DebugMonitor exception [8:8] read-write SVCALLACT `IAAMO the active state of the SVCall exception `FTSSS [7:7] read-write NMIACT `IAAMO the active state of the NMI exception [5:5] read-write SECUREFAULTACT `IAAMO the active state of the SecureFault exception [4:4] read-write USGFAULTACT `IAAMO the active state of the UsageFault exception `FTSSS [3:3] read-write HARDFAULTACT Indicates and allows limited modification of the active state of the HardFault exception `FTSSS [2:2] read-write BUSFAULTACT `IAAMO the active state of the BusFault exception [1:1] read-write MEMFAULTACT `IAAMO the active state of the MemManage exception `FTSSS [0:0] read-write CFSR Contains the three Configurable Fault Status Registers. 31:16 UFSR: Provides information on UsageFault exceptions 15:8 BFSR: Provides information on BusFault exceptions 7:0 MMFSR: Provides information on MemManage exceptions 0xED28 0x00000000 UFSR_DIVBYZERO Sticky flag indicating whether an integer division by zero error has occurred [25:25] read-write UFSR_UNALIGNED Sticky flag indicating whether an unaligned access error has occurred [24:24] read-write UFSR_STKOF Sticky flag indicating whether a stack overflow error has occurred [20:20] read-write UFSR_NOCP Sticky flag indicating whether a coprocessor disabled or not present error has occurred [19:19] read-write UFSR_INVPC Sticky flag indicating whether an integrity check error has occurred [18:18] read-write UFSR_INVSTATE Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred [17:17] read-write UFSR_UNDEFINSTR Sticky flag indicating whether an undefined instruction error has occurred [16:16] read-write BFSR_BFARVALID Indicates validity of the contents of the BFAR register [15:15] read-write BFSR_LSPERR Records whether a BusFault occurred during FP lazy state preservation [13:13] read-write BFSR_STKERR Records whether a derived BusFault occurred during exception entry stacking [12:12] read-write BFSR_UNSTKERR Records whether a derived BusFault occurred during exception return unstacking [11:11] read-write BFSR_IMPRECISERR Records whether an imprecise data access error has occurred [10:10] read-write BFSR_PRECISERR Records whether a precise data access error has occurred [9:9] read-write BFSR_IBUSERR Records whether a BusFault on an instruction prefetch has occurred [8:8] read-write MMFSR Provides information on MemManage exceptions [7:0] read-write HFSR Shows the cause of any HardFaults 0xED2C 0x00000000 DEBUGEVT Indicates when a Debug event has occurred [31:31] read-write FORCED Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled [30:30] read-write VECTTBL Indicates when a fault has occurred because of a vector table read error on exception processing [1:1] read-write DFSR Shows which debug event occurred 0xED30 0x00000000 EXTERNAL Sticky flag indicating whether an External debug request debug event has occurred [4:4] read-write VCATCH Sticky flag indicating whether a Vector catch debug event has occurred [3:3] read-write DWTTRAP Sticky flag indicating whether a Watchpoint debug event has occurred [2:2] read-write BKPT Sticky flag indicating whether a Breakpoint debug event has occurred [1:1] read-write HALTED Sticky flag indicating that a Halt request debug event or Step debug event has occurred [0:0] read-write MMFAR Shows the address of the memory location that caused an MPU fault 0xED34 0x00000000 ADDRESS This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN [31:0] read-write BFAR Shows the address associated with a precise data access BusFault 0xED38 0x00000000 ADDRESS This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN [31:0] read-write ID_PFR0 Gives top-level information about the instruction set supported by the PE 0xED40 0x00000030 STATE1 T32 instruction set support [7:4] read-only STATE0 A32 instruction set support [3:0] read-only ID_PFR1 Gives information about the programmers' model and Extensions support 0xED44 0x00000520 MPROGMOD Identifies support for the M-Profile programmers' model support [11:8] read-only SECURITY Identifies whether the Security Extension is implemented [7:4] read-only ID_DFR0 Provides top level information about the debug system 0xED48 0x00200000 MPROFDBG Indicates the supported M-profile debug architecture [23:20] read-only ID_AFR0 Provides information about the IMPLEMENTATION DEFINED features of the PE 0xED4C 0x00000000 IMPDEF3 IMPLEMENTATION DEFINED meaning [15:12] read-only IMPDEF2 IMPLEMENTATION DEFINED meaning [11:8] read-only IMPDEF1 IMPLEMENTATION DEFINED meaning [7:4] read-only IMPDEF0 IMPLEMENTATION DEFINED meaning [3:0] read-only ID_MMFR0 Provides information about the implemented memory model and memory management support 0xED50 0x00101F40 AUXREG Indicates support for Auxiliary Control Registers [23:20] read-only TCM Indicates support for tightly coupled memories (TCMs) [19:16] read-only SHARELVL Indicates the number of shareability levels implemented [15:12] read-only OUTERSHR Indicates the outermost shareability domain implemented [11:8] read-only PMSA Indicates support for the protected memory system architecture (PMSA) [7:4] read-only ID_MMFR1 Provides information about the implemented memory model and memory management support 0xED54 0x00000000 ID_MMFR1 [31:0] read-write ID_MMFR2 Provides information about the implemented memory model and memory management support 0xED58 0x01000000 WFISTALL Indicates the support for Wait For Interrupt (WFI) stalling [27:24] read-only ID_MMFR3 Provides information about the implemented memory model and memory management support 0xED5C 0x00000000 BPMAINT Indicates the supported branch predictor maintenance [11:8] read-only CMAINTSW Indicates the supported cache maintenance operations by set/way [7:4] read-only CMAINTVA Indicates the supported cache maintenance operations by address [3:0] read-only ID_ISAR0 Provides information about the instruction set implemented by the PE 0xED60 0x08092300 DIVIDE Indicates the supported Divide instructions [27:24] read-only DEBUG Indicates the implemented Debug instructions [23:20] read-only COPROC Indicates the supported Coprocessor instructions [19:16] read-only CMPBRANCH Indicates the supported combined Compare and Branch instructions [15:12] read-only BITFIELD Indicates the supported bit field instructions [11:8] read-only BITCOUNT Indicates the supported bit count instructions [7:4] read-only ID_ISAR1 Provides information about the instruction set implemented by the PE 0xED64 0x05725000 INTERWORK Indicates the implemented Interworking instructions [27:24] read-only IMMEDIATE Indicates the implemented for data-processing instructions with long immediates [23:20] read-only IFTHEN Indicates the implemented If-Then instructions [19:16] read-only EXTEND Indicates the implemented Extend instructions [15:12] read-only ID_ISAR2 Provides information about the instruction set implemented by the PE 0xED68 0x30173426 REVERSAL Indicates the implemented Reversal instructions [31:28] read-only MULTU Indicates the implemented advanced unsigned Multiply instructions [23:20] read-only MULTS Indicates the implemented advanced signed Multiply instructions [19:16] read-only MULT Indicates the implemented additional Multiply instructions [15:12] read-only MULTIACCESSINT Indicates the support for interruptible multi-access instructions [11:8] read-only MEMHINT Indicates the implemented Memory Hint instructions [7:4] read-only LOADSTORE Indicates the implemented additional load/store instructions [3:0] read-only ID_ISAR3 Provides information about the instruction set implemented by the PE 0xED6C 0x07895729 TRUENOP Indicates the implemented true NOP instructions [27:24] read-only T32COPY Indicates the support for T32 non flag-setting MOV instructions [23:20] read-only TABBRANCH Indicates the implemented Table Branch instructions [19:16] read-only SYNCHPRIM Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions [15:12] read-only SVC Indicates the implemented SVC instructions [11:8] read-only SIMD Indicates the implemented SIMD instructions [7:4] read-only SATURATE Indicates the implemented saturating instructions [3:0] read-only ID_ISAR4 Provides information about the instruction set implemented by the PE 0xED70 0x01310132 PSR_M Indicates the implemented M profile instructions to modify the PSRs [27:24] read-only SYNCPRIM_FRAC Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions [23:20] read-only BARRIER Indicates the implemented Barrier instructions [19:16] read-only WRITEBACK Indicates the support for writeback addressing modes [11:8] read-only WITHSHIFTS Indicates the support for writeback addressing modes [7:4] read-only UNPRIV Indicates the implemented unprivileged instructions [3:0] read-only ID_ISAR5 Provides information about the instruction set implemented by the PE 0xED74 0x00000000 ID_ISAR5 [31:0] read-write CTR Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero. 0xED7C 0x8000C000 RES1 Reserved, RES1 [31:31] read-only CWG Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified [27:24] read-only ERG Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions [23:20] read-only DMINLINE Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE [19:16] read-only RES1_1 Reserved, RES1 [15:14] read-only IMINLINE Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE [3:0] read-only CPACR Specifies the access privileges for coprocessors and the FP Extension 0xED88 0x00000000 CP11 The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN [23:22] read-write CP10 Defines the access rights for the floating-point functionality [21:20] read-write CP7 Controls access privileges for coprocessor 7 [15:14] read-write CP6 Controls access privileges for coprocessor 6 [13:12] read-write CP5 Controls access privileges for coprocessor 5 [11:10] read-write CP4 Controls access privileges for coprocessor 4 [9:8] read-write CP3 Controls access privileges for coprocessor 3 [7:6] read-write CP2 Controls access privileges for coprocessor 2 [5:4] read-write CP1 Controls access privileges for coprocessor 1 [3:2] read-write CP0 Controls access privileges for coprocessor 0 [1:0] read-write NSACR Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7 0xED8C 0x00000000 CP11 Enables Non-secure access to the Floating-point Extension [11:11] read-write CP10 Enables Non-secure access to the Floating-point Extension [10:10] read-write CP7 Enables Non-secure access to coprocessor CP7 [7:7] read-write CP6 Enables Non-secure access to coprocessor CP6 [6:6] read-write CP5 Enables Non-secure access to coprocessor CP5 [5:5] read-write CP4 Enables Non-secure access to coprocessor CP4 [4:4] read-write CP3 Enables Non-secure access to coprocessor CP3 [3:3] read-write CP2 Enables Non-secure access to coprocessor CP2 [2:2] read-write CP1 Enables Non-secure access to coprocessor CP1 [1:1] read-write CP0 Enables Non-secure access to coprocessor CP0 [0:0] read-write MPU_TYPE The MPU Type Register indicates how many regions the MPU `FTSSS supports 0xED90 0x00000800 DREGION Number of regions supported by the MPU [15:8] read-only SEPARATE Indicates support for separate instructions and data address regions [0:0] read-only MPU_CTRL Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 0xED94 0x00000000 PRIVDEFENA Controls whether the default memory map is enabled for privileged software [2:2] read-write HFNMIENA Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1 [1:1] read-write ENABLE Enables the MPU [0:0] read-write MPU_RNR Selects the region currently accessed by MPU_RBAR and MPU_RLAR 0xED98 0x00000000 REGION Indicates the memory region accessed by MPU_RBAR and MPU_RLAR [2:0] read-write MPU_RBAR Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS 0xED9C 0x00000000 BASE Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against [31:5] read-write SH Defines the Shareability domain of this region for Normal memory [4:3] read-write AP Defines the access permissions for this region [2:1] read-write XN Defines whether code can be executed from this region [0:0] read-write MPU_RLAR Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS 0xEDA0 0x00000000 LIMIT Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against [31:5] read-write ATTRINDX Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields [3:1] read-write EN Region enable [0:0] read-write MPU_RBAR_A1 Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS 0xEDA4 0x00000000 BASE Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against [31:5] read-write SH Defines the Shareability domain of this region for Normal memory [4:3] read-write AP Defines the access permissions for this region [2:1] read-write XN Defines whether code can be executed from this region [0:0] read-write MPU_RLAR_A1 Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS 0xEDA8 0x00000000 LIMIT Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against [31:5] read-write ATTRINDX Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields [3:1] read-write EN Region enable [0:0] read-write MPU_RBAR_A2 Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS 0xEDAC 0x00000000 BASE Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against [31:5] read-write SH Defines the Shareability domain of this region for Normal memory [4:3] read-write AP Defines the access permissions for this region [2:1] read-write XN Defines whether code can be executed from this region [0:0] read-write MPU_RLAR_A2 Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS 0xEDB0 0x00000000 LIMIT Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against [31:5] read-write ATTRINDX Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields [3:1] read-write EN Region enable [0:0] read-write MPU_RBAR_A3 Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS 0xEDB4 0x00000000 BASE Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against [31:5] read-write SH Defines the Shareability domain of this region for Normal memory [4:3] read-write AP Defines the access permissions for this region [2:1] read-write XN Defines whether code can be executed from this region [0:0] read-write MPU_RLAR_A3 Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS 0xEDB8 0x00000000 LIMIT Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against [31:5] read-write ATTRINDX Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields [3:1] read-write EN Region enable [0:0] read-write MPU_MAIR0 Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values 0xEDC0 0x00000000 ATTR3 Memory attribute encoding for MPU regions with an AttrIndex of 3 [31:24] read-write ATTR2 Memory attribute encoding for MPU regions with an AttrIndex of 2 [23:16] read-write ATTR1 Memory attribute encoding for MPU regions with an AttrIndex of 1 [15:8] read-write ATTR0 Memory attribute encoding for MPU regions with an AttrIndex of 0 [7:0] read-write MPU_MAIR1 Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values 0xEDC4 0x00000000 ATTR7 Memory attribute encoding for MPU regions with an AttrIndex of 7 [31:24] read-write ATTR6 Memory attribute encoding for MPU regions with an AttrIndex of 6 [23:16] read-write ATTR5 Memory attribute encoding for MPU regions with an AttrIndex of 5 [15:8] read-write ATTR4 Memory attribute encoding for MPU regions with an AttrIndex of 4 [7:0] read-write SAU_CTRL Allows enabling of the Security Attribution Unit 0xEDD0 0x00000000 ALLNS When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure [1:1] read-write ENABLE Enables the SAU [0:0] read-write SAU_TYPE Indicates the number of regions implemented by the Security Attribution Unit 0xEDD4 0x00000008 SREGION The number of implemented SAU regions [7:0] read-only SAU_RNR Selects the region currently accessed by SAU_RBAR and SAU_RLAR 0xEDD8 0x00000000 REGION Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR [7:0] read-write SAU_RBAR Provides indirect read and write access to the base address of the currently selected SAU region 0xEDDC 0x00000000 BADDR Holds bits [31:5] of the base address for the selected SAU region [31:5] read-write SAU_RLAR Provides indirect read and write access to the limit address of the currently selected SAU region 0xEDE0 0x00000000 LADDR Holds bits [31:5] of the limit address for the selected SAU region [31:5] read-write NSC Controls whether Non-secure state is permitted to execute an SG instruction from this region [1:1] read-write ENABLE SAU region enable [0:0] read-write SFSR Provides information about any security related faults 0xEDE4 0x00000000 LSERR Sticky flag indicating that an error occurred during lazy state activation or deactivation [7:7] read-write SFARVALID This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault [6:6] read-write LSPERR Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state [5:5] read-write INVTRAN Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory [4:4] read-write AUVIOL Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR [3:3] read-write INVER This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state [2:2] read-write INVIS This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation [1:1] read-write INVEP This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set [0:0] read-write SFAR Shows the address of the memory location that caused a Security violation 0xEDE8 0x00000000 ADDRESS The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state [31:0] read-write DHCSR Controls halting debug 0xEDF0 0x00000000 S_RESTART_ST Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request [26:26] read-only S_RESET_ST Indicates whether the PE has been reset since the last read of the DHCSR [25:25] read-only S_RETIRE_ST Set to 1 every time the PE retires one of more instructions [24:24] read-only S_SDE Indicates whether Secure invasive debug is allowed [20:20] read-only S_LOCKUP Indicates whether the PE is in Lockup state [19:19] read-only S_SLEEP Indicates whether the PE is sleeping [18:18] read-only S_HALT Indicates whether the PE is in Debug state [17:17] read-only S_REGRDY Handshake flag to transfers through the DCRDR [16:16] read-only C_SNAPSTALL Allow imprecise entry to Debug state [5:5] read-write C_MASKINTS When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts [3:3] read-write C_STEP Enable single instruction step [2:2] read-write C_HALT PE enter Debug state halt request [1:1] read-write C_DEBUGEN Enable Halting debug [0:0] read-write DCRSR With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer 0xEDF4 0x00000000 REGWNR Specifies the access type for the transfer [16:16] read-write REGSEL Specifies the general-purpose register, special-purpose register, or FP register to transfer [6:0] read-write DCRDR With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE 0xEDF8 0x00000000 DBGTMP Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers [31:0] read-write DEMCR Manages vector catch behavior and DebugMonitor handling when debugging 0xEDFC 0x00000000 TRCENA Global enable for all DWT and ITM features [24:24] read-write SDME Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state [20:20] read-only MON_REQ DebugMonitor semaphore bit [19:19] read-write MON_STEP Enable DebugMonitor stepping [18:18] read-write MON_PEND Sets or clears the pending state of the DebugMonitor exception [17:17] read-write MON_EN Enable the DebugMonitor exception [16:16] read-write VC_SFERR SecureFault exception halting debug vector catch enable [11:11] read-write VC_HARDERR HardFault exception halting debug vector catch enable [10:10] read-write VC_INTERR Enable halting debug vector catch for faults during exception entry and return [9:9] read-write VC_BUSERR BusFault exception halting debug vector catch enable [8:8] read-write VC_STATERR Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception [7:7] read-write VC_CHKERR Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error [6:6] read-write VC_NOCPERR Enable halting debug trap on a UsageFault caused by an access to a coprocessor [5:5] read-write VC_MMERR Enable halting debug trap on a MemManage exception [4:4] read-write VC_CORERESET Enable Reset Vector Catch. This causes a warm reset to halt a running system [0:0] read-write DSCSR Provides control and status information for Secure debug 0xEE08 0x00000000 CDSKEY Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero [17:17] read-write CDS This field indicates the current Security state of the processor [16:16] read-write SBRSEL If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger [1:1] read-write SBRSELEN Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger [0:0] read-write STIR Provides a mechanism for software to generate an interrupt 0xEF00 0x00000000 INTID Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16) [8:0] read-write FPCCR Holds control data for the Floating-point extension 0xEF34 0x20000472 ASPEN When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 [31:31] read-write LSPEN Enables lazy context save of floating-point state [30:30] read-write LSPENS This bit controls whether the LSPEN bit is writeable from the Non-secure state [29:29] read-write CLRONRET Clear floating-point caller saved registers on exception return [28:28] read-write CLRONRETS This bit controls whether the CLRONRET bit is writeable from the Non-secure state [27:27] read-write TS Treat floating-point registers as Secure enable [26:26] read-write UFRDY Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending [10:10] read-write SPLIMVIOL This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior [9:9] read-write MONRDY Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending [8:8] read-write SFRDY Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state [7:7] read-write BFRDY Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending [6:6] read-write MMRDY Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending [5:5] read-write HFRDY Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending [4:4] read-write THREAD Indicates the PE mode when it allocated the floating-point stack frame [3:3] read-write S Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed [2:2] read-write USER Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame [1:1] read-write LSPACT Indicates whether lazy preservation of the floating-point state is active [0:0] read-write FPCAR Holds the location of the unpopulated floating-point register space allocated on an exception stack frame 0xEF38 0x00000000 ADDRESS The location of the unpopulated floating-point register space allocated on an exception stack frame [31:3] read-write FPDSCR Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context 0xEF3C 0x00000000 AHP Default value for FPSCR.AHP [26:26] read-write DN Default value for FPSCR.DN [25:25] read-write FZ Default value for FPSCR.FZ [24:24] read-write RMODE Default value for FPSCR.RMode [23:22] read-write MVFR0 Describes the features provided by the Floating-point Extension 0xEF40 0x60540601 FPROUND Indicates the rounding modes supported by the FP Extension [31:28] read-only FPSQRT Indicates the support for FP square root operations [23:20] read-only FPDIVIDE Indicates the support for FP divide operations [19:16] read-only FPDP Indicates support for FP double-precision operations [11:8] read-only FPSP Indicates support for FP single-precision operations [7:4] read-only SIMDREG Indicates size of FP register file [3:0] read-only MVFR1 Describes the features provided by the Floating-point Extension 0xEF44 0x85000089 FMAC Indicates whether the FP Extension implements the fused multiply accumulate instructions [31:28] read-only FPHP Indicates whether the FP Extension implements half-precision FP conversion instructions [27:24] read-only FPDNAN Indicates whether the FP hardware implementation supports NaN propagation [7:4] read-only FPFTZ Indicates whether subnormals are always flushed-to-zero [3:0] read-only MVFR2 Describes the features provided by the Floating-point Extension 0xEF48 0x00000060 FPMISC Indicates support for miscellaneous FP features [7:4] read-only DDEVARCH Provides CoreSight discovery information for the SCS 0xEFBC 0x47702A04 ARCHITECT Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. [31:21] read-only PRESENT Defines that the DEVARCH register is present [20:20] read-only REVISION Defines the architecture revision of the component [19:16] read-only ARCHVER Defines the architecture version of the component [15:12] read-only ARCHPART Defines the architecture of the component [11:0] read-only DDEVTYPE Provides CoreSight discovery information for the SCS 0xEFCC 0x00000000 SUB Component sub-type [7:4] read-only MAJOR CoreSight major type [3:0] read-only DPIDR4 Provides CoreSight discovery information for the SCS 0xEFD0 0x00000004 SIZE See CoreSight Architecture Specification [7:4] read-only DES_2 See CoreSight Architecture Specification [3:0] read-only DPIDR5 Provides CoreSight discovery information for the SCS 0xEFD4 0x00000000 DPIDR5 [31:0] read-write DPIDR6 Provides CoreSight discovery information for the SCS 0xEFD8 0x00000000 DPIDR6 [31:0] read-write DPIDR7 Provides CoreSight discovery information for the SCS 0xEFDC 0x00000000 DPIDR7 [31:0] read-write DPIDR0 Provides CoreSight discovery information for the SCS 0xEFE0 0x00000021 PART_0 See CoreSight Architecture Specification [7:0] read-only DPIDR1 Provides CoreSight discovery information for the SCS 0xEFE4 0x000000BD DES_0 See CoreSight Architecture Specification [7:4] read-only PART_1 See CoreSight Architecture Specification [3:0] read-only DPIDR2 Provides CoreSight discovery information for the SCS 0xEFE8 0x0000000B REVISION See CoreSight Architecture Specification [7:4] read-only JEDEC See CoreSight Architecture Specification [3:3] read-only DES_1 See CoreSight Architecture Specification [2:0] read-only DPIDR3 Provides CoreSight discovery information for the SCS 0xEFEC 0x00000000 REVAND See CoreSight Architecture Specification [7:4] read-only CMOD See CoreSight Architecture Specification [3:0] read-only DCIDR0 Provides CoreSight discovery information for the SCS 0xEFF0 0x0000000D PRMBL_0 See CoreSight Architecture Specification [7:0] read-only DCIDR1 Provides CoreSight discovery information for the SCS 0xEFF4 0x00000090 CLASS See CoreSight Architecture Specification [7:4] read-only PRMBL_1 See CoreSight Architecture Specification [3:0] read-only DCIDR2 Provides CoreSight discovery information for the SCS 0xEFF8 0x00000005 PRMBL_2 See CoreSight Architecture Specification [7:0] read-only DCIDR3 Provides CoreSight discovery information for the SCS 0xEFFC 0x000000B1 PRMBL_3 See CoreSight Architecture Specification [7:0] read-only TRCPRGCTLR Programming Control Register 0x41004 0x00000000 EN Trace Unit Enable [0:0] read-write TRCSTATR The TRCSTATR indicates the ETM-Teal status 0x4100C 0x00000000 PMSTABLE Indicates whether the ETM-Teal registers are stable and can be read [1:1] read-only IDLE Indicates that the trace unit is inactive [0:0] read-only TRCCONFIGR The TRCCONFIGR sets the basic tracing options for the trace unit 0x41010 0x00000000 RS Return stack enable [12:12] read-write TS Global timestamp tracing [11:11] read-write COND Conditional instruction tracing [10:5] read-write CCI Cycle counting in instruction trace [4:4] read-write BB Branch broadcast mode [3:3] read-write TRCEVENTCTL0R The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs. 0x41020 0x00000000 TYPE1 Selects the resource type for event 1 [15:15] read-write SEL1 Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0] [10:8] read-write TYPE0 Selects the resource type for event 0 [7:7] read-write SEL0 Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] [2:0] read-write TRCEVENTCTL1R The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave 0x41024 0x00000000 LPOVERRIDE Low power state behavior override [12:12] read-write ATB ATB enabled [11:11] read-write INSTEN1 One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs [1:1] read-write INSTEN0 One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs [0:0] read-write TRCSTALLCTLR The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow 0x4102C 0x00000000 INSTPRIORITY Reserved, RES0 [10:10] read-only ISTALL Stall processor based on instruction trace buffer space [8:8] read-write LEVEL Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow [3:2] read-write TRCTSCTLR The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream 0x41030 0x00000000 TYPE0 Selects the resource type for event 0 [7:7] read-write SEL0 Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] [1:0] read-write TRCSYNCPR The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two 0x41034 0x0000000A PERIOD Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes [4:0] read-only TRCCCCTLR The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets 0x41038 0x00000000 THRESHOLD Instruction trace cycle count threshold [11:0] read-write TRCVICTLR The TRCVICTLR controls instruction trace filtering 0x41080 0x00000000 EXLEVEL_S3 In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level [19:19] read-write EXLEVEL_S0 In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level [16:16] read-write TRCERR Selects whether a system error exception must always be traced [11:11] read-write TRCRESET Selects whether a reset exception must always be traced [10:10] read-write SSSTATUS Indicates the current status of the start/stop logic [9:9] read-write TYPE0 Selects the resource type for event 0 [7:7] read-write SEL0 Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0] [1:0] read-write TRCCNTRLDVR0 The TRCCNTRLDVR defines the reload value for the reduced function counter 0x41140 0x00000000 VALUE Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs [15:0] read-write TRCIDR8 TRCIDR8 0x41180 0x00000000 MAXSPEC reads as `ImpDef [31:0] read-only TRCIDR9 TRCIDR9 0x41184 0x00000000 NUMP0KEY reads as `ImpDef [31:0] read-only TRCIDR10 TRCIDR10 0x41188 0x00000000 NUMP1KEY reads as `ImpDef [31:0] read-only TRCIDR11 TRCIDR11 0x4118C 0x00000000 NUMP1SPC reads as `ImpDef [31:0] read-only TRCIDR12 TRCIDR12 0x41190 0x00000001 NUMCONDKEY reads as `ImpDef [31:0] read-only TRCIDR13 TRCIDR13 0x41194 0x00000000 NUMCONDSPC reads as `ImpDef [31:0] read-only TRCIMSPEC The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided 0x411C0 0x00000000 SUPPORT Reserved, RES0 [3:0] read-only TRCIDR0 TRCIDR0 0x411E0 0x280006E1 COMMOPT reads as `ImpDef [29:29] read-only TSSIZE reads as `ImpDef [28:24] read-only TRCEXDATA reads as `ImpDef [17:17] read-only QSUPP reads as `ImpDef [16:15] read-only QFILT reads as `ImpDef [14:14] read-only CONDTYPE reads as `ImpDef [13:12] read-only NUMEVENT reads as `ImpDef [11:10] read-only RETSTACK reads as `ImpDef [9:9] read-only TRCCCI reads as `ImpDef [7:7] read-only TRCCOND reads as `ImpDef [6:6] read-only TRCBB reads as `ImpDef [5:5] read-only TRCDATA reads as `ImpDef [4:3] read-only INSTP0 reads as `ImpDef [2:1] read-only RES1 Reserved, RES1 [0:0] read-only TRCIDR1 TRCIDR1 0x411E4 0x4100F421 DESIGNER reads as `ImpDef [31:24] read-only RES1 Reserved, RES1 [15:12] read-only TRCARCHMAJ reads as 0b0100 [11:8] read-only TRCARCHMIN reads as 0b0000 [7:4] read-only REVISION reads as `ImpDef [3:0] read-only TRCIDR2 TRCIDR2 0x411E8 0x00000004 CCSIZE reads as `ImpDef [28:25] read-only DVSIZE reads as `ImpDef [24:20] read-only DASIZE reads as `ImpDef [19:15] read-only VMIDSIZE reads as `ImpDef [14:10] read-only CIDSIZE reads as `ImpDef [9:5] read-only IASIZE reads as `ImpDef [4:0] read-only TRCIDR3 TRCIDR3 0x411EC 0x0F090004 NOOVERFLOW reads as `ImpDef [31:31] read-only NUMPROC reads as `ImpDef [30:28] read-only SYSSTALL reads as `ImpDef [27:27] read-only STALLCTL reads as `ImpDef [26:26] read-only SYNCPR reads as `ImpDef [25:25] read-only TRCERR reads as `ImpDef [24:24] read-only EXLEVEL_NS reads as `ImpDef [23:20] read-only EXLEVEL_S reads as `ImpDef [19:16] read-only CCITMIN reads as `ImpDef [11:0] read-only TRCIDR4 TRCIDR4 0x411F0 0x00114000 NUMVMIDC reads as `ImpDef [31:28] read-only NUMCIDC reads as `ImpDef [27:24] read-only NUMSSCC reads as `ImpDef [23:20] read-only NUMRSPAIR reads as `ImpDef [19:16] read-only NUMPC reads as `ImpDef [15:12] read-only SUPPDAC reads as `ImpDef [8:8] read-only NUMDVC reads as `ImpDef [7:4] read-only NUMACPAIRS reads as `ImpDef [3:0] read-only TRCIDR5 TRCIDR5 0x411F4 0x90C70004 REDFUNCNTR reads as `ImpDef [31:31] read-only NUMCNTR reads as `ImpDef [30:28] read-only NUMSEQSTATE reads as `ImpDef [27:25] read-only LPOVERRIDE reads as `ImpDef [23:23] read-only ATBTRIG reads as `ImpDef [22:22] read-only TRACEIDSIZE reads as 0x07 [21:16] read-only NUMEXTINSEL reads as `ImpDef [11:9] read-only NUMEXTIN reads as `ImpDef [8:0] read-only TRCIDR6 TRCIDR6 0x411F8 0x00000000 TRCIDR6 [31:0] read-write TRCIDR7 TRCIDR7 0x411FC 0x00000000 TRCIDR7 [31:0] read-write TRCRSCTLR2 The TRCRSCTLR controls the trace resources 0x41208 0x00000000 PAIRINV Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors [21:21] read-write INV Inverts the selected resources [20:20] read-write GROUP Selects a group of resource [18:16] read-write SELECT Selects one or more resources from the wanted group. One bit is provided per resource from the group [7:0] read-write TRCRSCTLR3 The TRCRSCTLR controls the trace resources 0x4120C 0x00000000 PAIRINV Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors [21:21] read-write INV Inverts the selected resources [20:20] read-write GROUP Selects a group of resource [18:16] read-write SELECT Selects one or more resources from the wanted group. One bit is provided per resource from the group [7:0] read-write TRCSSCSR Controls the corresponding single-shot comparator resource 0x412A0 0x00000000 STATUS Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched [31:31] read-write PC Reserved, RES1 [3:3] read-only DV Reserved, RES0 [2:2] read-only DA Reserved, RES0 [1:1] read-only INST Reserved, RES0 [0:0] read-only TRCSSPCICR Selects the PE comparator inputs for Single-shot control 0x412C0 0x00000000 PC Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control [3:0] read-write TRCPDCR Requests the system to provide power to the trace unit 0x41310 0x00000000 PU Powerup request bit: [3:3] read-write TRCPDSR Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status 0x41314 0x00000003 OSLK OS Lock status bit: [5:5] read-only STICKYPD Sticky powerdown status bit. Indicates whether the trace register state is valid: [1:1] read-only POWER Power status bit: [0:0] read-only TRCITATBIDR Trace Integration ATB Identification Register 0x41EE4 0x00000000 ID Trace ID [6:0] read-write TRCITIATBINR Trace Integration Instruction ATB In Register 0x41EF4 0x00000000 AFVALIDM Integration Mode instruction AFVALIDM in [1:1] read-write ATREADYM Integration Mode instruction ATREADYM in [0:0] read-write TRCITIATBOUTR Trace Integration Instruction ATB Out Register 0x41EFC 0x00000000 AFREADY Integration Mode instruction AFREADY out [1:1] read-write ATVALID Integration Mode instruction ATVALID out [0:0] read-write TRCCLAIMSET Claim Tag Set Register 0x41FA0 0x0000000F SET3 When a write to one of these bits occurs, with the value: [3:3] read-write SET2 When a write to one of these bits occurs, with the value: [2:2] read-write SET1 When a write to one of these bits occurs, with the value: [1:1] read-write SET0 When a write to one of these bits occurs, with the value: [0:0] read-write TRCCLAIMCLR Claim Tag Clear Register 0x41FA4 0x00000000 CLR3 When a write to one of these bits occurs, with the value: [3:3] read-write CLR2 When a write to one of these bits occurs, with the value: [2:2] read-write CLR1 When a write to one of these bits occurs, with the value: [1:1] read-write CLR0 When a write to one of these bits occurs, with the value: [0:0] read-write TRCAUTHSTATUS Returns the level of tracing that the trace unit can support 0x41FB8 0x00000000 SNID Indicates whether the system enables the trace unit to support Secure non-invasive debug: [7:6] read-only SID Indicates whether the trace unit supports Secure invasive debug: [5:4] read-only NSNID Indicates whether the system enables the trace unit to support Non-secure non-invasive debug: [3:2] read-only NSID Indicates whether the trace unit supports Non-secure invasive debug: [1:0] read-only TRCDEVARCH TRCDEVARCH 0x41FBC 0x47724A13 ARCHITECT reads as 0b01000111011 [31:21] read-only PRESENT reads as 0b1 [20:20] read-only REVISION reads as 0b0000 [19:16] read-only ARCHID reads as 0b0100101000010011 [15:0] read-only TRCDEVID TRCDEVID 0x41FC8 0x00000000 TRCDEVID [31:0] read-write TRCDEVTYPE TRCDEVTYPE 0x41FCC 0x00000013 SUB reads as 0b0001 [7:4] read-only MAJOR reads as 0b0011 [3:0] read-only TRCPIDR4 TRCPIDR4 0x41FD0 0x00000004 SIZE reads as `ImpDef [7:4] read-only DES_2 reads as `ImpDef [3:0] read-only TRCPIDR5 TRCPIDR5 0x41FD4 0x00000000 TRCPIDR5 [31:0] read-write TRCPIDR6 TRCPIDR6 0x41FD8 0x00000000 TRCPIDR6 [31:0] read-write TRCPIDR7 TRCPIDR7 0x41FDC 0x00000000 TRCPIDR7 [31:0] read-write TRCPIDR0 TRCPIDR0 0x41FE0 0x00000021 PART_0 reads as `ImpDef [7:0] read-only TRCPIDR1 TRCPIDR1 0x41FE4 0x000000BD DES_0 reads as `ImpDef [7:4] read-only PART_0 reads as `ImpDef [3:0] read-only TRCPIDR2 TRCPIDR2 0x41FE8 0x0000002B REVISION reads as `ImpDef [7:4] read-only JEDEC reads as 0b1 [3:3] read-only DES_0 reads as `ImpDef [2:0] read-only TRCPIDR3 TRCPIDR3 0x41FEC 0x00000000 REVAND reads as `ImpDef [7:4] read-only CMOD reads as `ImpDef [3:0] read-only TRCCIDR0 TRCCIDR0 0x41FF0 0x0000000D PRMBL_0 reads as 0b00001101 [7:0] read-only TRCCIDR1 TRCCIDR1 0x41FF4 0x00000090 CLASS reads as 0b1001 [7:4] read-only PRMBL_1 reads as 0b0000 [3:0] read-only TRCCIDR2 TRCCIDR2 0x41FF8 0x00000005 PRMBL_2 reads as 0b00000101 [7:0] read-only TRCCIDR3 TRCCIDR3 0x41FFC 0x000000B1 PRMBL_3 reads as 0b10110001 [7:0] read-only CTICONTROL CTI Control Register 0x42000 0x00000000 GLBEN Enables or disables the CTI [0:0] read-write CTIINTACK CTI Interrupt Acknowledge Register 0x42010 0x00000000 INTACK Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared. [7:0] read-write CTIAPPSET CTI Application Trigger Set Register 0x42014 0x00000000 APPSET Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel [3:0] read-write CTIAPPCLEAR CTI Application Trigger Clear Register 0x42018 0x00000000 APPCLEAR Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel. [3:0] read-write CTIAPPPULSE CTI Application Pulse Register 0x4201C 0x00000000 APPULSE Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel. [3:0] read-write CTIINEN0 CTI Trigger to Channel Enable Registers 0x42020 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIINEN1 CTI Trigger to Channel Enable Registers 0x42024 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIINEN2 CTI Trigger to Channel Enable Registers 0x42028 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIINEN3 CTI Trigger to Channel Enable Registers 0x4202C 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIINEN4 CTI Trigger to Channel Enable Registers 0x42030 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIINEN5 CTI Trigger to Channel Enable Registers 0x42034 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIINEN6 CTI Trigger to Channel Enable Registers 0x42038 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIINEN7 CTI Trigger to Channel Enable Registers 0x4203C 0x00000000 TRIGINEN Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels [3:0] read-write CTIOUTEN0 CTI Trigger to Channel Enable Registers 0x420A0 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTIOUTEN1 CTI Trigger to Channel Enable Registers 0x420A4 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTIOUTEN2 CTI Trigger to Channel Enable Registers 0x420A8 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTIOUTEN3 CTI Trigger to Channel Enable Registers 0x420AC 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTIOUTEN4 CTI Trigger to Channel Enable Registers 0x420B0 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTIOUTEN5 CTI Trigger to Channel Enable Registers 0x420B4 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTIOUTEN6 CTI Trigger to Channel Enable Registers 0x420B8 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTIOUTEN7 CTI Trigger to Channel Enable Registers 0x420BC 0x00000000 TRIGOUTEN Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels. [3:0] read-write CTITRIGINSTATUS CTI Trigger to Channel Enable Registers 0x42130 0x00000000 TRIGINSTATUS Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN. [7:0] read-only CTITRIGOUTSTATUS CTI Trigger In Status Register 0x42134 0x00000000 TRIGOUTSTATUS Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output. [7:0] read-only CTICHINSTATUS CTI Channel In Status Register 0x42138 0x00000000 CTICHOUTSTATUS Shows the status of the ctichout outputs. There is one bit of the field for each channel output [3:0] read-only CTIGATE Enable CTI Channel Gate register 0x42140 0x0000000F CTIGATEEN3 Enable ctichout3. Set to 0 to disable channel propagation. [3:3] read-write CTIGATEEN2 Enable ctichout2. Set to 0 to disable channel propagation. [2:2] read-write CTIGATEEN1 Enable ctichout1. Set to 0 to disable channel propagation. [1:1] read-write CTIGATEEN0 Enable ctichout0. Set to 0 to disable channel propagation. [0:0] read-write ASICCTL External Multiplexer Control register 0x42144 0x00000000 ASICCTL [31:0] read-write ITCHOUT Integration Test Channel Output register 0x42EE4 0x00000000 CTCHOUT Sets the value of the ctichout outputs [3:0] read-write ITTRIGOUT Integration Test Trigger Output register 0x42EE8 0x00000000 CTTRIGOUT Sets the value of the ctitrigout outputs [7:0] read-write ITCHIN Integration Test Channel Input register 0x42EF4 0x00000000 CTCHIN Reads the value of the ctichin inputs. [3:0] read-only ITCTRL Integration Mode Control register 0x42F00 0x00000000 IME Integration Mode Enable [0:0] read-write DEVARCH Device Architecture register 0x42FBC 0x47701A14 ARCHITECT Indicates the component architect [31:21] read-only PRESENT Indicates whether the DEVARCH register is present [20:20] read-only REVISION Indicates the architecture revision [19:16] read-only ARCHID Indicates the component [15:0] read-only DEVID Device Configuration register 0x42FC8 0x00040800 NUMCH Number of ECT channels available [19:16] read-only NUMTRIG Number of ECT triggers available. [15:8] read-only EXTMUXNUM Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly. [4:0] read-only DEVTYPE Device Type Identifier register 0x42FCC 0x00000014 SUB Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field. [7:4] read-only MAJOR Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component. [3:0] read-only PIDR4 CoreSight Peripheral ID4 0x42FD0 0x00000004 SIZE Always 0b0000. Indicates that the device only occupies 4KB of memory [7:4] read-only DES_2 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. [3:0] read-only PIDR5 CoreSight Peripheral ID5 0x42FD4 0x00000000 PIDR5 [31:0] read-write PIDR6 CoreSight Peripheral ID6 0x42FD8 0x00000000 PIDR6 [31:0] read-write PIDR7 CoreSight Peripheral ID7 0x42FDC 0x00000000 PIDR7 [31:0] read-write PIDR0 CoreSight Peripheral ID0 0x42FE0 0x00000021 PART_0 Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number. [7:0] read-only PIDR1 CoreSight Peripheral ID1 0x42FE4 0x000000BD DES_0 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. [7:4] read-only PART_1 Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number. [3:0] read-only PIDR2 CoreSight Peripheral ID2 0x42FE8 0x0000000B REVISION This device is at r1p0 [7:4] read-only JEDEC Always 1. Indicates that the JEDEC-assigned designer ID is used. [3:3] read-only DES_1 Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component. [2:0] read-only PIDR3 CoreSight Peripheral ID3 0x42FEC 0x00000000 REVAND Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000. [7:4] read-only CMOD Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component. [3:0] read-only CIDR0 CoreSight Component ID0 0x42FF0 0x0000000D PRMBL_0 Preamble[0]. Contains bits[7:0] of the component identification code [7:0] read-only CIDR1 CoreSight Component ID1 0x42FF4 0x00000090 CLASS Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code. [7:4] read-only PRMBL_1 Preamble[1]. Contains bits[11:8] of the component identification code. [3:0] read-only CIDR2 CoreSight Component ID2 0x42FF8 0x00000005 PRMBL_2 Preamble[2]. Contains bits[23:16] of the component identification code. [7:0] read-only CIDR3 CoreSight Component ID3 0x42FFC 0x000000B1 PRMBL_3 Preamble[3]. Contains bits[31:24] of the component identification code. [7:0] read-only PPB_NS 0xE0020000 QMI QSPI Memory Interface. Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. 0x400D0000 0x0 0x54 registers DIRECT_CSR Control and status for direct serial mode Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. 0x0 0x01800000 RXDELAY Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) [31:30] read-write CLKDIV Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0. The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte. [29:22] read-write RXLEVEL Current level of DIRECT_RX FIFO [20:18] read-only RXFULL When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped; the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full. [17:17] read-only RXEMPTY When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined. [16:16] read-only TXLEVEL Current level of DIRECT_TX FIFO [14:12] read-only TXEMPTY When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes. [11:11] read-only TXFULL When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored. [10:10] read-only AUTO_CS1N When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set. [7:7] read-write AUTO_CS0N When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set. [6:6] read-write ASSERT_CS1N When 1, assert (i.e. drive low) the CS1n chip select line. Note that this applies even when DIRECT_CSR_EN is 0. [3:3] read-write ASSERT_CS0N When 1, assert (i.e. drive low) the CS0n chip select line. Note that this applies even when DIRECT_CSR_EN is 0. [2:2] read-write BUSY Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted. The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select. (In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.) [1:1] read-only EN Enable direct mode. In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO. Memory-mapped accesses will generate bus errors when direct serial mode is enabled. [0:0] read-write DIRECT_TX Transmit FIFO for direct mode 0x4 0x00000000 NOPUSH Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. [20:20] write-only OE Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. [19:19] write-only DWIDTH Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. [18:18] write-only IWIDTH Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. [17:16] write-only S Single width 0 D Dual width 1 Q Quad width 2 DATA Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first. [15:0] write-only DIRECT_RX Receive FIFO for direct mode 0x8 0x00000000 DIRECT_RX With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. [15:0] read-only modify M0_TIMING Timing configuration register for memory address window 0. 0xC 0x40000004 COOLDOWN Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. [31:30] read-write PAGEBREAK When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled. [29:28] read-write NONE No page boundary is enforced 0 256 Break bursts crossing a 256-byte page boundary 1 1024 Break bursts crossing a 1024-byte quad-page boundary 2 4096 Break bursts crossing a 4096-byte sector boundary 3 SELECT_SETUP Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. [25:25] read-write SELECT_HOLD Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. [24:23] read-write MAX_SELECT Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. [22:17] read-write MIN_DESELECT After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. [16:12] read-write RXDELAY Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. [10:8] read-write CLKDIV Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. [7:0] read-write M0_RFMT Read transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. 0x10 0x00001000 DTR Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. [28:28] read-write DUMMY_LEN Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) [18:16] read-write NONE No dummy phase 0 4 4 dummy bits 1 8 8 dummy bits 2 12 12 dummy bits 3 16 16 dummy bits 4 20 20 dummy bits 5 24 24 dummy bits 6 28 28 dummy bits 7 SUFFIX_LEN Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. [15:14] read-write NONE No suffix 0 8 8-bit suffix 2 PREFIX_LEN Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) [12:12] read-write NONE No prefix 0 8 8-bit prefix 1 DATA_WIDTH The width used for the data transfer [9:8] read-write S Single width 0 D Dual width 1 Q Quad width 2 DUMMY_WIDTH The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. [7:6] read-write S Single width 0 D Dual width 1 Q Quad width 2 SUFFIX_WIDTH The width used for the post-address command suffix, if any [5:4] read-write S Single width 0 D Dual width 1 Q Quad width 2 ADDR_WIDTH The transfer width used for the address. The address phase always transfers 24 bits in total. [3:2] read-write S Single width 0 D Dual width 1 Q Quad width 2 PREFIX_WIDTH The transfer width used for the command prefix, if any [1:0] read-write S Single width 0 D Dual width 1 Q Quad width 2 M0_RCMD Command constants used for reads from memory address window 0. The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. 0x14 0x0000A003 SUFFIX The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. [15:8] read-write PREFIX The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. [7:0] read-write M0_WFMT Write transfer format configuration for memory address window 0. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default. 0x18 0x00001000 DTR Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. [28:28] read-write DUMMY_LEN Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) [18:16] read-write NONE No dummy phase 0 4 4 dummy bits 1 8 8 dummy bits 2 12 12 dummy bits 3 16 16 dummy bits 4 20 20 dummy bits 5 24 24 dummy bits 6 28 28 dummy bits 7 SUFFIX_LEN Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. [15:14] read-write NONE No suffix 0 8 8-bit suffix 2 PREFIX_LEN Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) [12:12] read-write NONE No prefix 0 8 8-bit prefix 1 DATA_WIDTH The width used for the data transfer [9:8] read-write S Single width 0 D Dual width 1 Q Quad width 2 DUMMY_WIDTH The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. [7:6] read-write S Single width 0 D Dual width 1 Q Quad width 2 SUFFIX_WIDTH The width used for the post-address command suffix, if any [5:4] read-write S Single width 0 D Dual width 1 Q Quad width 2 ADDR_WIDTH The transfer width used for the address. The address phase always transfers 24 bits in total. [3:2] read-write S Single width 0 D Dual width 1 Q Quad width 2 PREFIX_WIDTH The transfer width used for the command prefix, if any [1:0] read-write S Single width 0 D Dual width 1 Q Quad width 2 M0_WCMD Command constants used for writes to memory address window 0. The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. 0x1C 0x0000A002 SUFFIX The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. [15:8] read-write PREFIX The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. [7:0] read-write M1_TIMING Timing configuration register for memory address window 1. 0x20 0x40000004 COOLDOWN Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power. If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput. Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer. If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes. [31:30] read-write PAGEBREAK When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary. Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices. This field has no effect when COOLDOWN is disabled. [29:28] read-write NONE No page boundary is enforced 0 256 Break bursts crossing a 256-byte page boundary 1 1024 Break bursts crossing a 1024-byte quad-page boundary 2 4096 Break bursts crossing a 4096-byte sector boundary 3 SELECT_SETUP Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK. The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices. [25:25] read-write SELECT_HOLD Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select. The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe. Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point. Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked. [24:23] read-write MAX_SELECT Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN). This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time. If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line. [22:17] read-write MIN_DESELECT After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin. Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected. [16:12] read-write RXDELAY Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register. At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device. [10:8] read-write CLKDIV Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0. The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle. If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed. [7:0] read-write M1_RFMT Read transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration. 0x24 0x00001000 DTR Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. [28:28] read-write DUMMY_LEN Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) [18:16] read-write NONE No dummy phase 0 4 4 dummy bits 1 8 8 dummy bits 2 12 12 dummy bits 3 16 16 dummy bits 4 20 20 dummy bits 5 24 24 dummy bits 6 28 28 dummy bits 7 SUFFIX_LEN Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. [15:14] read-write NONE No suffix 0 8 8-bit suffix 2 PREFIX_LEN Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) [12:12] read-write NONE No prefix 0 8 8-bit prefix 1 DATA_WIDTH The width used for the data transfer [9:8] read-write S Single width 0 D Dual width 1 Q Quad width 2 DUMMY_WIDTH The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. [7:6] read-write S Single width 0 D Dual width 1 Q Quad width 2 SUFFIX_WIDTH The width used for the post-address command suffix, if any [5:4] read-write S Single width 0 D Dual width 1 Q Quad width 2 ADDR_WIDTH The transfer width used for the address. The address phase always transfers 24 bits in total. [3:2] read-write S Single width 0 D Dual width 1 Q Quad width 2 PREFIX_WIDTH The transfer width used for the command prefix, if any [1:0] read-write S Single width 0 D Dual width 1 Q Quad width 2 M1_RCMD Command constants used for reads from memory address window 1. The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration. 0x28 0x0000A003 SUFFIX The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero. [15:8] read-write PREFIX The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero. [7:0] read-write M1_WFMT Write transfer format configuration for memory address window 1. Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported. The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default. 0x2C 0x00001000 DTR Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. [28:28] read-write DUMMY_LEN Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) [18:16] read-write NONE No dummy phase 0 4 4 dummy bits 1 8 8 dummy bits 2 12 12 dummy bits 3 16 16 dummy bits 4 20 20 dummy bits 5 24 24 dummy bits 6 28 28 dummy bits 7 SUFFIX_LEN Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. [15:14] read-write NONE No suffix 0 8 8-bit suffix 2 PREFIX_LEN Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) [12:12] read-write NONE No prefix 0 8 8-bit prefix 1 DATA_WIDTH The width used for the data transfer [9:8] read-write S Single width 0 D Dual width 1 Q Quad width 2 DUMMY_WIDTH The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. [7:6] read-write S Single width 0 D Dual width 1 Q Quad width 2 SUFFIX_WIDTH The width used for the post-address command suffix, if any [5:4] read-write S Single width 0 D Dual width 1 Q Quad width 2 ADDR_WIDTH The transfer width used for the address. The address phase always transfers 24 bits in total. [3:2] read-write S Single width 0 D Dual width 1 Q Quad width 2 PREFIX_WIDTH The transfer width used for the command prefix, if any [1:0] read-write S Single width 0 D Dual width 1 Q Quad width 2 M1_WCMD Command constants used for writes to memory address window 1. The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration. 0x30 0x0000A002 SUFFIX The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero. [15:8] read-write PREFIX The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero. [7:0] read-write ATRANS0 Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x34 0x04000000 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write ATRANS1 Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x38 0x04000400 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write ATRANS2 Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x3C 0x04000800 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write ATRANS3 Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x40 0x04000C00 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write ATRANS4 Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x44 0x04000000 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write ATRANS5 Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x48 0x04000400 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write ATRANS6 Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x4C 0x04000800 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write ATRANS7 Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB). Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code. At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required. Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation. 0x50 0x04000C00 SIZE Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector). Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access. [26:16] read-write BASE Physical address base for this virtual address range, in units of 4 kiB (one flash sector). Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary. [11:0] read-write XIP_CTRL QSPI flash execute-in-place block 0x400C8000 0x0 0x20 registers CTRL Cache control register. Read-only from a Non-secure context. 0x0 0x00000083 WRITABLE_M1 If 1, enable writes to XIP memory window 1 (addresses 0x11000000 through 0x11ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 1. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. [11:11] read-write WRITABLE_M0 If 1, enable writes to XIP memory window 0 (addresses 0x10000000 through 0x10ffffff, and their uncached mirrors). If 0, this region is read-only. XIP memory is *read-only by default*. This bit must be set to enable writes if a RAM device is attached on QSPI chip select 0. The default read-only behaviour avoids two issues with writing to a read-only QSPI device (e.g. flash). First, a write will initially appear to succeed due to caching, but the data will eventually be lost when the written line is evicted, causing unpredictable behaviour. Second, when a written line is evicted, it will cause a write command to be issued to the flash, which can break the flash out of its continuous read mode. After this point, flash reads will return garbage. This is a security concern, as it allows Non-secure software to break Secure flash reads if it has permission to write to any flash address. Note the read-only behaviour is implemented by downgrading writes to reads, so writes will still cause allocation of an address, but have no other effect. [10:10] read-write SPLIT_WAYS When 1, route all cached+Secure accesses to way 0 of the cache, and route all cached+Non-secure accesses to way 1 of the cache. This partitions the cache into two half-sized direct-mapped regions, such that Non-secure code can not observe cache line state changes caused by Secure execution. A full cache flush is required when changing the value of SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is 0, so that both cache ways are accessible for invalidation. [9:9] read-write MAINT_NONSEC When 0, Non-secure accesses to the cache maintenance address window (addr[27] == 1, addr[26] == 0) will generate a bus error. When 1, Non-secure accesses can perform cache maintenance operations by writing to the cache maintenance address window. Cache maintenance operations may be used to corrupt Secure data by invalidating cache lines inappropriately, or map Secure content into a Non-secure region by pinning cache lines. Therefore this bit should generally be set to 0, unless Secure code is not using the cache. Care should also be taken to clear the cache data memory and tag memory before granting maintenance operations to Non-secure code. [8:8] read-write NO_UNTRANSLATED_NONSEC When 1, Non-secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. [7:7] read-write NO_UNTRANSLATED_SEC When 1, Secure accesses to the uncached, untranslated window (addr[27:26] == 3) will generate a bus error. [6:6] read-write NO_UNCACHED_NONSEC When 1, Non-secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. [5:5] read-write NO_UNCACHED_SEC When 1, Secure accesses to the uncached window (addr[27:26] == 1) will generate a bus error. This may reduce the number of SAU/MPU/PMP regions required to protect flash contents. Note this does not disable access to the uncached, untranslated window -- see NO_UNTRANSLATED_SEC. [4:4] read-write POWER_DOWN When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN_SECURE and CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when powered down. [3:3] read-write EN_NONSECURE When 1, enable the cache for Non-secure accesses. When enabled, Non-secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. [1:1] read-write EN_SECURE When 1, enable the cache for Secure accesses. When enabled, Secure XIP accesses to the cached (addr[26] == 0) window will query the cache, and QSPI accesses are performed only if the requested data is not present. When disabled, Secure access ignore the cache contents, and always access the QSPI interface. Accesses to the uncached (addr[26] == 1) window will never query the cache, irrespective of this bit. There is no cache-as-SRAM address window. Cache lines are allocated for SRAM-like use by individually pinning them, and keeping the cache enabled. [0:0] read-write STAT 0x8 0x00000002 FIFO_FULL When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained. [2:2] read-only FIFO_EMPTY When 1, indicates the XIP streaming FIFO is completely empty. [1:1] read-only CTR_HIT Cache Hit counter 0xC 0x00000000 CTR_HIT A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear. [31:0] read-write oneToClear CTR_ACC Cache Access counter 0x10 0x00000000 CTR_ACC A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear. [31:0] read-write oneToClear STREAM_ADDR FIFO stream address 0x14 0x00000000 STREAM_ADDR The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read. [31:2] read-write STREAM_CTR FIFO stream control 0x18 0x00000000 STREAM_CTR Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR) [21:0] read-write STREAM_FIFO FIFO stream data 0x1C 0x00000000 STREAM_FIFO Streamed data is buffered here, for retrieval by the system DMA. This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic. [31:0] read-only modify XIP_AUX Auxiliary DMA access to XIP FIFOs, via fast AHB bus access 0x50500000 0x0 0xC registers STREAM Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) 0x0 0x00000000 STREAM [31:0] read-only modify QMI_DIRECT_TX Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) 0x4 0x00000000 NOPUSH Inhibit the RX FIFO push that would correspond to this TX FIFO entry. Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer. [20:20] write-only OE Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input. For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer. [19:19] write-only DWIDTH Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely. [18:18] write-only IWIDTH Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely. [17:16] write-only S Single width 0 D Dual width 1 Q Quad width 2 DATA Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO. For 16-bit data, the least-significant byte is transmitted first. [15:0] write-only QMI_DIRECT_RX Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) 0x8 0x00000000 QMI_DIRECT_RX With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data. When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received. [15:0] read-only modify SYSCFG Register block for various chip control signals 0x40008000 0x0 0x18 registers PROC_CONFIG Configuration for processors 0x0 0x00000000 PROC1_HALTED Indication that proc1 has halted [1:1] read-only PROC0_HALTED Indication that proc0 has halted [0:0] read-only PROC_IN_SYNC_BYPASS For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31. 0x4 0x00000000 GPIO [31:0] read-write PROC_IN_SYNC_BYPASS_HI For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63 0x8 0x00000000 QSPI_SD [31:28] read-write QSPI_CSN [27:27] read-write QSPI_SCK [26:26] read-write USB_DM [25:25] read-write USB_DP [24:24] read-write GPIO [15:0] read-write DBGFORCE Directly control the chip SWD debug port 0xC 0x00000006 ATTACH Attach chip debug port to syscfg controls, and disconnect it from external SWD pads. [3:3] read-write SWCLK Directly drive SWCLK, if ATTACH is set [2:2] read-write SWDI Directly drive SWDIO input, if ATTACH is set [1:1] read-write SWDO Observe the value of SWDIO output. [0:0] read-only MEMPOWERDOWN Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution 0x10 0x00000000 BOOTRAM [12:12] read-write ROM [11:11] read-write USB [10:10] read-write SRAM9 [9:9] read-write SRAM8 [8:8] read-write SRAM7 [7:7] read-write SRAM6 [6:6] read-write SRAM5 [5:5] read-write SRAM4 [4:4] read-write SRAM3 [3:3] read-write SRAM2 [2:2] read-write SRAM1 [1:1] read-write SRAM0 [0:0] read-write AUXCTRL Auxiliary system control register 0x14 0x00000000 AUXCTRL * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state. [7:0] read-write XOSC Controls the crystal oscillator 0x40048000 0x0 0x14 registers CTRL Crystal Oscillator Control 0x0 0x00000000 ENABLE On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED [23:12] read-write DISABLE 3358 ENABLE 4011 FREQ_RANGE The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE [11:0] read-write 1_15MHZ 2720 10_30MHZ 2721 25_60MHZ 2722 40_100MHZ 2723 STATUS Crystal Oscillator Status 0x4 0x00000000 STABLE Oscillator is running and stable [31:31] read-only BADWRITE An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT [24:24] read-write oneToClear ENABLED Oscillator is enabled but not necessarily running and stable, resets to 0 [12:12] read-only FREQ_RANGE The current frequency range setting [1:0] read-only 1_15MHZ 0 10_30MHZ 1 25_60MHZ 2 40_100MHZ 3 DORMANT Crystal Oscillator pause control 0x8 0x00000000 DORMANT This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode [31:0] read-write dormant 1668246881 WAKE 2002873189 STARTUP Controls the startup delay 0xC 0x00000000 X4 Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0. [20:20] read-write DELAY in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. [13:0] read-write COUNT A down counter running at the xosc frequency which counts to zero and stops. Can be used for short software pauses when setting up time sensitive hardware. To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished. Minimum count value is 4. Count values <4 will be treated as count value =4. Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that. 0x10 0x00000000 COUNT [15:0] read-write PLL_SYS 0x40050000 0x0 0x20 registers PLL_SYS_IRQ 42 CS Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz 0x0 0x00000001 LOCK PLL is locked [31:31] read-only LOCK_N PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set [30:30] read-write oneToClear BYPASS Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. [8:8] read-write REFDIV Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. [5:0] read-write PWR Controls the PLL power modes. 0x4 0x0000002D VCOPD PLL VCO powerdown To save power set high when PLL output not required or bypass=1. [5:5] read-write POSTDIVPD PLL post divider powerdown To save power set high when PLL output not required or bypass=1. [3:3] read-write DSMPD PLL DSM powerdown Nothing is achieved by setting this low. [2:2] read-write PD PLL powerdown To save power set high when PLL output not required. [0:0] read-write FBDIV_INT Feedback divisor (note: this PLL does not support fractional division) 0x8 0x00000000 FBDIV_INT see ctrl reg description for constraints [11:0] read-write PRIM Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 0xC 0x00077000 POSTDIV1 divide by 1-7 [18:16] read-write POSTDIV2 divide by 1-7 [14:12] read-write INTR Raw Interrupts 0x10 0x00000000 LOCK_N_STICKY [0:0] read-write oneToClear INTE Interrupt Enable 0x14 0x00000000 LOCK_N_STICKY [0:0] read-write INTF Interrupt Force 0x18 0x00000000 LOCK_N_STICKY [0:0] read-write INTS Interrupt status after masking & forcing 0x1C 0x00000000 LOCK_N_STICKY [0:0] read-only PLL_USB 0x40058000 PLL_USB_IRQ 43 ACCESSCTRL Hardware access control registers 0x40060000 0x0 0xEC registers LOCK Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to. 0x0 0x00000004 DEBUG [3:3] read-write DMA [2:2] read-only CORE1 [1:1] read-write CORE0 [0:0] read-write FORCE_CORE_NS Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID. 0x4 0x00000000 CORE1 [1:1] read-write CFGRESET Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents. 0x8 0x00000000 CFGRESET [0:0] write-only GPIO_NSMASK0 Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access 0xC 0x00000000 GPIO_NSMASK0 [31:0] read-write GPIO_NSMASK1 Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger. 0x10 0x00000000 QSPI_SD [31:28] read-write QSPI_CSN [27:27] read-write QSPI_SCK [26:26] read-write USB_DM [25:25] read-write USB_DP [24:24] read-write GPIO [15:0] read-write ROM Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x14 0x000000FF DBG If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, ROM can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, ROM can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write XIP_MAIN Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x18 0x000000FF DBG If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, XIP_MAIN can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM0 Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x1C 0x000000FF DBG If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM1 Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x20 0x000000FF DBG If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM1 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM1 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM2 Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x24 0x000000FF DBG If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM2 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM2 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM3 Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x28 0x000000FF DBG If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM3 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM3 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM4 Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x2C 0x000000FF DBG If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM4 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM4 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM5 Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x30 0x000000FF DBG If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM5 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM5 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM6 Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x34 0x000000FF DBG If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM6 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM6 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM7 Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x38 0x000000FF DBG If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM7 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM7 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM8 Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x3C 0x000000FF DBG If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM8 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM8 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SRAM9 Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x40 0x000000FF DBG If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SRAM9 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SRAM9 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write DMA Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x44 0x000000FC DBG If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, DMA can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, DMA can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write USBCTRL Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x48 0x000000FC DBG If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, USBCTRL can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, USBCTRL can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PIO0 Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x4C 0x000000FC DBG If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PIO0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PIO0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PIO1 Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x50 0x000000FC DBG If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PIO1 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PIO1 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PIO2 Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x54 0x000000FC DBG If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PIO2 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PIO2 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write CORESIGHT_TRACE Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x58 0x000000B8 DBG If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write CORESIGHT_PERIPH Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x5C 0x000000B8 DBG If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SYSINFO Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x60 0x000000FF DBG If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SYSINFO can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SYSINFO can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write RESETS Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x64 0x000000FC DBG If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, RESETS can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, RESETS can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write IO_BANK0 Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x68 0x000000FC DBG If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, IO_BANK0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write IO_BANK1 Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x6C 0x000000FC DBG If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, IO_BANK1 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PADS_BANK0 Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x70 0x000000FC DBG If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PADS_BANK0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PADS_QSPI Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x74 0x000000FC DBG If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PADS_QSPI can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write BUSCTRL Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x78 0x000000FC DBG If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, BUSCTRL can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, BUSCTRL can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write ADC0 Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x7C 0x000000FC DBG If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, ADC0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, ADC0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write HSTX Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x80 0x000000FC DBG If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, HSTX can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, HSTX can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write I2C0 Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x84 0x000000FC DBG If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, I2C0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, I2C0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write I2C1 Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x88 0x000000FC DBG If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, I2C1 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, I2C1 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PWM Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x8C 0x000000FC DBG If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PWM can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PWM can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SPI0 Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x90 0x000000FC DBG If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SPI0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SPI0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SPI1 Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x94 0x000000FC DBG If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SPI1 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SPI1 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write TIMER0 Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x98 0x000000FC DBG If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, TIMER0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, TIMER0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write TIMER1 Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0x9C 0x000000FC DBG If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, TIMER1 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, TIMER1 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write UART0 Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xA0 0x000000FC DBG If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, UART0 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, UART0 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write UART1 Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xA4 0x000000FC DBG If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, UART1 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, UART1 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write OTP Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xA8 0x000000FC DBG If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, OTP can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, OTP can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write TBMAN Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xAC 0x000000FC DBG If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, TBMAN can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, TBMAN can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write POWMAN Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xB0 0x000000B8 DBG If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, POWMAN can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, POWMAN can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write TRNG Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xB4 0x000000B8 DBG If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, TRNG can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, TRNG can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SHA256 Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xB8 0x000000F8 DBG If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SHA256 can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SHA256 can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write SYSCFG Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xBC 0x000000B8 DBG If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, SYSCFG can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, SYSCFG can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write CLOCKS Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xC0 0x000000B8 DBG If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, CLOCKS can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, CLOCKS can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write XOSC Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xC4 0x000000B8 DBG If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, XOSC can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, XOSC can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write ROSC Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xC8 0x000000B8 DBG If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, ROSC can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, ROSC can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PLL_SYS Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xCC 0x000000B8 DBG If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PLL_SYS can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PLL_SYS can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write PLL_USB Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xD0 0x000000B8 DBG If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, PLL_USB can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, PLL_USB can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write TICKS Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xD4 0x000000B8 DBG If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, TICKS can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, TICKS can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write WATCHDOG Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xD8 0x000000B8 DBG If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, WATCHDOG can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, WATCHDOG can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write RSM Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xDC 0x000000B8 DBG If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, RSM can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, RSM can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write XIP_CTRL Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xE0 0x000000B8 DBG If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, XIP_CTRL can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write XIP_QMI Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xE4 0x000000B8 DBG If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, XIP_QMI can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, XIP_QMI can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write XIP_AUX Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set. 0xE8 0x000000F8 DBG If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [7:7] read-write DMA If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [6:6] read-write CORE1 If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [5:5] read-write CORE0 If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. [4:4] read-write SP If 1, XIP_AUX can be accessed from a Secure, Privileged context. [3:3] read-write SU If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context. [2:2] read-write NSP If 1, XIP_AUX can be accessed from a Non-secure, Privileged context. [1:1] read-write NSU If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. [0:0] read-write UART0 0x40070000 0x0 0x1000 registers UART0_IRQ 33 UARTDR Data Register, UARTDR 0x0 0x00000000 OE Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. [11:11] read-only BE Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. [10:10] read-only PE Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. [9:9] read-only FE Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. [8:8] read-only DATA Receive (read) data character. Transmit (write) data character. [7:0] read-write modify UARTRSR Receive Status Register/Error Clear Register, UARTRSR/UARTECR 0x4 0x00000000 OE Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. [3:3] read-write oneToClear BE Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. [2:2] read-write oneToClear PE Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. [1:1] read-write oneToClear FE Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. [0:0] read-write oneToClear UARTFR Flag Register, UARTFR 0x18 0x00000090 RI Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. [8:8] read-only TXFE Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. [7:7] read-only RXFF Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. [6:6] read-only TXFF Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. [5:5] read-only RXFE Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. [4:4] read-only BUSY UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. [3:3] read-only DCD Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. [2:2] read-only DSR Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. [1:1] read-only CTS Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. [0:0] read-only UARTILPR IrDA Low-Power Counter Register, UARTILPR 0x20 0x00000000 ILPDVSR 8-bit low-power divisor value. These bits are cleared to 0 at reset. [7:0] read-write UARTIBRD Integer Baud Rate Register, UARTIBRD 0x24 0x00000000 BAUD_DIVINT The integer baud rate divisor. These bits are cleared to 0 on reset. [15:0] read-write UARTFBRD Fractional Baud Rate Register, UARTFBRD 0x28 0x00000000 BAUD_DIVFRAC The fractional baud rate divisor. These bits are cleared to 0 on reset. [5:0] read-write UARTLCR_H Line Control Register, UARTLCR_H 0x2C 0x00000000 SPS Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. [7:7] read-write WLEN Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. [6:5] read-write FEN Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). [4:4] read-write STP2 Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. [3:3] read-write EPS Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. [2:2] read-write PEN Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. [1:1] read-write BRK Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. [0:0] read-write UARTCR Control Register, UARTCR 0x30 0x00000300 CTSEN CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. [15:15] read-write RTSEN RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. [14:14] read-write OUT2 This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). [13:13] read-write OUT1 This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). [12:12] read-write RTS Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. [11:11] read-write DTR Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. [10:10] read-write RXE Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. [9:9] read-write TXE Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. [8:8] read-write LBE Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. [7:7] read-write SIRLP SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. [2:2] read-write SIREN SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. [1:1] read-write UARTEN UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. [0:0] read-write UARTIFLS Interrupt FIFO Level Select Register, UARTIFLS 0x34 0x00000012 RXIFLSEL Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. [5:3] read-write TXIFLSEL Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. [2:0] read-write UARTIMSC Interrupt Mask Set/Clear Register, UARTIMSC 0x38 0x00000000 OEIM Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. [10:10] read-write BEIM Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. [9:9] read-write PEIM Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. [8:8] read-write FEIM Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. [7:7] read-write RTIM Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. [6:6] read-write TXIM Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. [5:5] read-write RXIM Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. [4:4] read-write DSRMIM nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. [3:3] read-write DCDMIM nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. [2:2] read-write CTSMIM nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. [1:1] read-write RIMIM nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. [0:0] read-write UARTRIS Raw Interrupt Status Register, UARTRIS 0x3C 0x00000000 OERIS Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. [10:10] read-only BERIS Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. [9:9] read-only PERIS Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. [8:8] read-only FERIS Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. [7:7] read-only RTRIS Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a [6:6] read-only TXRIS Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. [5:5] read-only RXRIS Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. [4:4] read-only DSRRMIS nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. [3:3] read-only DCDRMIS nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. [2:2] read-only CTSRMIS nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. [1:1] read-only RIRMIS nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. [0:0] read-only UARTMIS Masked Interrupt Status Register, UARTMIS 0x40 0x00000000 OEMIS Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. [10:10] read-only BEMIS Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. [9:9] read-only PEMIS Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. [8:8] read-only FEMIS Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. [7:7] read-only RTMIS Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. [6:6] read-only TXMIS Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. [5:5] read-only RXMIS Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. [4:4] read-only DSRMMIS nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. [3:3] read-only DCDMMIS nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. [2:2] read-only CTSMMIS nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. [1:1] read-only RIMMIS nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. [0:0] read-only UARTICR Interrupt Clear Register, UARTICR 0x44 0x00000000 OEIC Overrun error interrupt clear. Clears the UARTOEINTR interrupt. [10:10] read-write oneToClear BEIC Break error interrupt clear. Clears the UARTBEINTR interrupt. [9:9] read-write oneToClear PEIC Parity error interrupt clear. Clears the UARTPEINTR interrupt. [8:8] read-write oneToClear FEIC Framing error interrupt clear. Clears the UARTFEINTR interrupt. [7:7] read-write oneToClear RTIC Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. [6:6] read-write oneToClear TXIC Transmit interrupt clear. Clears the UARTTXINTR interrupt. [5:5] read-write oneToClear RXIC Receive interrupt clear. Clears the UARTRXINTR interrupt. [4:4] read-write oneToClear DSRMIC nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. [3:3] read-write oneToClear DCDMIC nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. [2:2] read-write oneToClear CTSMIC nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. [1:1] read-write oneToClear RIMIC nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. [0:0] read-write oneToClear UARTDMACR DMA Control Register, UARTDMACR 0x48 0x00000000 DMAONERR DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. [2:2] read-write TXDMAE Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write RXDMAE Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write UARTPERIPHID0 UARTPeriphID0 Register 0xFE0 0x00000011 PARTNUMBER0 These bits read back as 0x11 [7:0] read-only UARTPERIPHID1 UARTPeriphID1 Register 0xFE4 0x00000010 DESIGNER0 These bits read back as 0x1 [7:4] read-only PARTNUMBER1 These bits read back as 0x0 [3:0] read-only UARTPERIPHID2 UARTPeriphID2 Register 0xFE8 0x00000034 REVISION This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 [7:4] read-only DESIGNER1 These bits read back as 0x4 [3:0] read-only UARTPERIPHID3 UARTPeriphID3 Register 0xFEC 0x00000000 CONFIGURATION These bits read back as 0x00 [7:0] read-only UARTPCELLID0 UARTPCellID0 Register 0xFF0 0x0000000D UARTPCELLID0 These bits read back as 0x0D [7:0] read-only UARTPCELLID1 UARTPCellID1 Register 0xFF4 0x000000F0 UARTPCELLID1 These bits read back as 0xF0 [7:0] read-only UARTPCELLID2 UARTPCellID2 Register 0xFF8 0x00000005 UARTPCELLID2 These bits read back as 0x05 [7:0] read-only UARTPCELLID3 UARTPCellID3 Register 0xFFC 0x000000B1 UARTPCELLID3 These bits read back as 0xB1 [7:0] read-only UART1 0x40078000 UART1_IRQ 34 ROSC 0x400E8000 0x0 0x28 registers CTRL Ring Oscillator control 0x0 0x00000AA0 ENABLE On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. [23:12] read-write DISABLE 3358 ENABLE 4011 FREQ_RANGE Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH [11:0] read-write LOW 4004 MEDIUM 4005 HIGH 4007 TOOHIGH 4006 FREQA The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength For frequency randomisation set both DS0_RANDOM=1 & DS1_RANDOM=1 0x4 0x00000000 PASSWD Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 [31:16] read-write PASS 38550 DS3 Stage 3 drive strength [14:12] read-write DS2 Stage 2 drive strength [10:8] read-write DS1_RANDOM Randomises the stage 1 drive strength [7:7] read-write DS1 Stage 1 drive strength [6:4] read-write DS0_RANDOM Randomises the stage 0 drive strength [3:3] read-write DS0 Stage 0 drive strength [2:0] read-write FREQB For a detailed description see freqa register 0x8 0x00000000 PASSWD Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 [31:16] read-write PASS 38550 DS7 Stage 7 drive strength [14:12] read-write DS6 Stage 6 drive strength [10:8] read-write DS5 Stage 5 drive strength [6:4] read-write DS4 Stage 4 drive strength [2:0] read-write RANDOM Loads a value to the LFSR randomiser 0xC 0x3F04B16D SEED [31:0] read-write DORMANT Ring Oscillator pause control 0x10 0x00000000 DORMANT This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode [31:0] read-write dormant 1668246881 WAKE 2002873189 DIV Controls the output divider 0x14 0x00000000 DIV set to 0xaa00 + div where div = 0 divides by 128 div = 1-127 divides by div any other value sets div=128 this register resets to div=32 [15:0] read-write PASS 43520 PHASE Controls the phase shifted output 0x18 0x00000008 PASSWD set to 0xaa any other value enables the output with shift=0 [11:4] read-write ENABLE enable the phase-shifted output this can be changed on-the-fly [3:3] read-write FLIP invert the phase-shifted output this is ignored when div=1 [2:2] read-write SHIFT phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1 [1:0] read-write STATUS Ring Oscillator Status 0x1C 0x00000000 STABLE Oscillator is running and stable [31:31] read-only BADWRITE An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT [24:24] read-write oneToClear DIV_RUNNING post-divider is running this resets to 0 but transitions to 1 during chip startup [16:16] read-only ENABLED Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup [12:12] read-only RANDOMBIT This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency 0x20 0x00000001 RANDOMBIT [0:0] read-only COUNT A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. 0x24 0x00000000 COUNT [15:0] read-write POWMAN Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use 0x40100000 0x0 0xF0 registers POWMAN_IRQ_POW 44 POWMAN_IRQ_TIMER 45 BADPASSWD Indicates a bad password has been used 0x0 0x00000000 BADPASSWD [0:0] read-write oneToClear VREG_CTRL Voltage Regulator Control 0x4 0x00008050 RST_N returns the regulator to its startup settings 0 - reset 1 - not reset (default) [15:15] read-write UNLOCK unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked. [13:13] read-write ISOLATE isolates the VREG control interface 0 - not isolated (default) 1 - isolated [12:12] read-write DISABLE_VOLTAGE_LIMIT 0=not disabled, 1=enabled [8:8] read-write HT_TH high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C [6:4] read-write VREG_STS Voltage Regulator Status 0x8 0x00000000 VOUT_OK output regulation status 0=not in regulation, 1=in regulation [4:4] read-only STARTUP startup status 0=startup complete, 1=starting up [0:0] read-only VREG Voltage Regulator Settings 0xC 0x000000B0 UPDATE_IN_PROGRESS regulator state is being updated writes to the vreg register will be ignored when this field is set [15:15] read-only VSEL output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V [8:4] read-write HIZ high impedance mode select 0=not in high impedance mode, 1=in high impedance mode [1:1] read-write VREG_LP_ENTRY Voltage Regulator Low Power Entry Settings 0x10 0x000000B4 VSEL output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V [8:4] read-write MODE selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear) [2:2] read-write HIZ high impedance mode select 0=not in high impedance mode, 1=in high impedance mode [1:1] read-write VREG_LP_EXIT Voltage Regulator Low Power Exit Settings 0x14 0x000000B0 VSEL output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V [8:4] read-write MODE selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear) [2:2] read-write HIZ high impedance mode select 0=not in high impedance mode, 1=in high impedance mode [1:1] read-write BOD_CTRL Brown-out Detection Control 0x18 0x00000000 ISOLATE isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated [12:12] read-write BOD Brown-out Detection Settings 0x1C 0x000000B1 VSEL threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V [8:4] read-write EN enable brown-out detection 0=not enabled, 1=enabled [0:0] read-write BOD_LP_ENTRY Brown-out Detection Low Power Entry Settings 0x20 0x000000B0 VSEL threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V [8:4] read-write EN enable brown-out detection 0=not enabled, 1=enabled [0:0] read-write BOD_LP_EXIT Brown-out Detection Low Power Exit Settings 0x24 0x000000B1 VSEL threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V [8:4] read-write EN enable brown-out detection 0=not enabled, 1=enabled [0:0] read-write LPOSC Low power oscillator control register. 0x28 0x00000203 TRIM Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3% [9:4] read-write MODE This feature has been removed [1:0] read-write CHIP_RESET Chip reset control and status 0x2C 0x00000000 HAD_WATCHDOG_RESET_RSM Last reset was a watchdog timeout which was configured to reset the power-on state machine This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state [28:28] read-only HAD_HZD_SYS_RESET_REQ Last reset was a system reset from the hazard debugger This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state [27:27] read-only HAD_GLITCH_DETECT Last reset was due to a power supply glitch This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state [26:26] read-only HAD_SWCORE_PD Last reset was a switched core powerdown This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer [25:25] read-only HAD_WATCHDOG_RESET_SWCORE Last reset was a watchdog timeout which was configured to reset the switched-core This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer [24:24] read-only HAD_WATCHDOG_RESET_POWMAN Last reset was a watchdog timeout which was configured to reset the power manager This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer [23:23] read-only HAD_WATCHDOG_RESET_POWMAN_ASYNC Last reset was a watchdog timeout which was configured to reset the power manager asynchronously This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer [22:22] read-only HAD_RESCUE Last reset was a rescue reset from the debugger This resets: double_tap flag no DP no RPAP no rescue_flag no, it sets this flag timer yes powman yes swcore yes psm yes then starts the power sequencer [21:21] read-only HAD_DP_RESET_REQ Last reset was an reset request from the arm debugger This resets: double_tap flag no DP no RPAP no rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer [19:19] read-only HAD_RUN_LOW Last reset was from the RUN pin This resets: double_tap flag no DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer [18:18] read-only HAD_BOR Last reset was from the brown-out detection block This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer [17:17] read-only HAD_POR Last reset was from the power-on reset This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer [16:16] read-only RESCUE_FLAG This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up. [4:4] read-write oneToClear DOUBLE_TAP This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader. [0:0] read-write WDSEL Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect. 0x30 0x00000000 RESET_RSM If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector [12:12] read-write RESET_SWCORE If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain [8:8] read-write RESET_POWMAN If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true [4:4] read-write RESET_POWMAN_ASYNC If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running [0:0] read-write SEQ_CFG For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1 0x34 0x001011F0 USING_FAST_POWCK 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) 1 indicates the POWMAN clock is running from the reference clock (2-50MHz) [20:20] read-only USING_BOD_LP Indicates the brown-out detector (BOD) mode 0 = BOD high power mode which is the default 1 = BOD low power mode [17:17] read-only USING_VREG_LP Indicates the voltage regulator (VREG) mode 0 = VREG high power mode which is the default 1 = VREG low power mode [16:16] read-only USE_FAST_POWCK selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run [12:12] read-write RUN_LPOSC_IN_LP Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down [8:8] read-write USE_BOD_HP Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up [7:7] read-write USE_BOD_LP Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down [6:6] read-write USE_VREG_HP Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up [5:5] read-write USE_VREG_LP Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down [4:4] read-write HW_PWRUP_SRAM0 Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change [1:1] read-write HW_PWRUP_SRAM1 Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change [0:0] read-write STATE This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes. 0x38 0x0000000F CHANGING [13:13] read-only WAITING [12:12] read-only BAD_HW_REQ Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up) [11:11] read-only BAD_SW_REQ Bad software initiated state request. No action taken. [10:10] read-only PWRUP_WHILE_WAITING Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down. [9:9] read-write oneToClear REQ_IGNORED [8:8] read-write oneToClear REQ [7:4] read-write CURRENT [3:0] read-only POW_FASTDIV 0x3C 0x00000040 POW_FASTDIV divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div [10:0] read-write POW_DELAY power state machine delays 0x40 0x00002011 SRAM_STEP timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit [15:8] read-write XIP_STEP timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit [7:4] read-write SWCORE_STEP timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit [3:0] read-write EXT_CTRL0 Configures a gpio as a power mode aware control output 0x44 0x0000003F LP_EXIT_STATE output level when exiting the low power state [14:14] read-write LP_ENTRY_STATE output level when entering the low power state [13:13] read-write INIT_STATE [12:12] read-write INIT [8:8] read-write GPIO_SELECT selects from gpio 0->30 set to 31 to disable this feature [5:0] read-write EXT_CTRL1 Configures a gpio as a power mode aware control output 0x48 0x0000003F LP_EXIT_STATE output level when exiting the low power state [14:14] read-write LP_ENTRY_STATE output level when entering the low power state [13:13] read-write INIT_STATE [12:12] read-write INIT [8:8] read-write GPIO_SELECT selects from gpio 0->30 set to 31 to disable this feature [5:0] read-write EXT_TIME_REF Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register. 0x4C 0x00000000 DRIVE_LPCK Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0 [4:4] read-write SOURCE_SEL 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22 [1:0] read-write LPOSC_FREQ_KHZ_INT Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC. 0x50 0x00000020 LPOSC_FREQ_KHZ_INT Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 [5:0] read-write LPOSC_FREQ_KHZ_FRAC Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC. 0x54 0x0000C49C LPOSC_FREQ_KHZ_FRAC Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1 [15:0] read-write XOSC_FREQ_KHZ_INT Informs the AON Timer of the integer component of the clock frequency when running off the XOSC. 0x58 0x00002EE0 XOSC_FREQ_KHZ_INT Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 [15:0] read-write XOSC_FREQ_KHZ_FRAC Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC. 0x5C 0x00000000 XOSC_FREQ_KHZ_FRAC Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0 [15:0] read-write SET_TIME_63TO48 0x60 0x00000000 SET_TIME_63TO48 For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 [15:0] read-write SET_TIME_47TO32 0x64 0x00000000 SET_TIME_47TO32 For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 [15:0] read-write SET_TIME_31TO16 0x68 0x00000000 SET_TIME_31TO16 For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 [15:0] read-write SET_TIME_15TO0 0x6C 0x00000000 SET_TIME_15TO0 For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0 [15:0] read-write READ_TIME_UPPER 0x70 0x00000000 READ_TIME_UPPER For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER. [31:0] read-only READ_TIME_LOWER 0x74 0x00000000 READ_TIME_LOWER For reading bits 31:0 of the timer. [31:0] read-only ALARM_TIME_63TO48 0x78 0x00000000 ALARM_TIME_63TO48 This field must only be written when POWMAN_ALARM_ENAB=0 [15:0] read-write ALARM_TIME_47TO32 0x7C 0x00000000 ALARM_TIME_47TO32 This field must only be written when POWMAN_ALARM_ENAB=0 [15:0] read-write ALARM_TIME_31TO16 0x80 0x00000000 ALARM_TIME_31TO16 This field must only be written when POWMAN_ALARM_ENAB=0 [15:0] read-write ALARM_TIME_15TO0 0x84 0x00000000 ALARM_TIME_15TO0 This field must only be written when POWMAN_ALARM_ENAB=0 [15:0] read-write TIMER 0x88 0x00000000 USING_GPIO_1HZ Timer is synchronised to a 1hz gpio source [19:19] read-only USING_GPIO_1KHZ Timer is running from a 1khz gpio source [18:18] read-only USING_LPOSC Timer is running from lposc [17:17] read-only USING_XOSC Timer is running from xosc [16:16] read-only USE_GPIO_1HZ Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference. [13:13] read-write USE_GPIO_1KHZ switch to gpio as the source of the 1kHz timer tick [10:10] write-only USE_XOSC switch to xosc as the source of the 1kHz timer tick [9:9] write-only USE_LPOSC Switch to lposc as the source of the 1kHz timer tick [8:8] write-only ALARM Alarm has fired. Write to 1 to clear the alarm. [6:6] read-write oneToClear PWRUP_ON_ALARM Alarm wakes the chip from low power mode [5:5] read-write ALARM_ENAB Enables the alarm. The alarm must be disabled while writing the alarm time. [4:4] read-write CLEAR Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time. [2:2] write-only RUN Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1 [1:1] read-write NONSEC_WRITE Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure. [0:0] read-write PWRUP0 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high 0x8C 0x0000003F RAW_STATUS Value of selected gpio pin (only if enable == 1) [10:10] read-only STATUS Status of gpio wakeup. Write to 1 to clear a latched edge detect. [9:9] read-write oneToClear MODE Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. [8:8] read-write level 0 edge 1 DIRECTION [7:7] read-write low_falling 0 high_rising 1 ENABLE Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. [6:6] read-write SOURCE [5:0] read-write PWRUP1 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high 0x90 0x0000003F RAW_STATUS Value of selected gpio pin (only if enable == 1) [10:10] read-only STATUS Status of gpio wakeup. Write to 1 to clear a latched edge detect. [9:9] read-write oneToClear MODE Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. [8:8] read-write level 0 edge 1 DIRECTION [7:7] read-write low_falling 0 high_rising 1 ENABLE Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. [6:6] read-write SOURCE [5:0] read-write PWRUP2 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high 0x94 0x0000003F RAW_STATUS Value of selected gpio pin (only if enable == 1) [10:10] read-only STATUS Status of gpio wakeup. Write to 1 to clear a latched edge detect. [9:9] read-write oneToClear MODE Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. [8:8] read-write level 0 edge 1 DIRECTION [7:7] read-write low_falling 0 high_rising 1 ENABLE Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. [6:6] read-write SOURCE [5:0] read-write PWRUP3 4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high 0x98 0x0000003F RAW_STATUS Value of selected gpio pin (only if enable == 1) [10:10] read-only STATUS Status of gpio wakeup. Write to 1 to clear a latched edge detect. [9:9] read-write oneToClear MODE Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register. [8:8] read-write level 0 edge 1 DIRECTION [7:7] read-write low_falling 0 high_rising 1 ENABLE Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also. [6:6] read-write SOURCE [5:0] read-write CURRENT_PWRUP_REQ Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup 0x9C 0x00000000 CURRENT_PWRUP_REQ [6:0] read-only LAST_SWCORE_PWRUP Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup 0xA0 0x00000000 LAST_SWCORE_PWRUP [6:0] read-only DBG_PWRCFG 0xA4 0x00000000 IGNORE Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req [0:0] read-write BOOTDIS Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register. 0xA8 0x00000000 NEXT This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling. [1:1] read-write NOW When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. [0:0] read-write oneToClear DBGCONFIG 0xAC 0x00000000 DP_INSTID Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment [3:0] read-write SCRATCH0 Scratch register. Information persists in low power mode 0xB0 0x00000000 SCRATCH0 [31:0] read-write SCRATCH1 Scratch register. Information persists in low power mode 0xB4 0x00000000 SCRATCH1 [31:0] read-write SCRATCH2 Scratch register. Information persists in low power mode 0xB8 0x00000000 SCRATCH2 [31:0] read-write SCRATCH3 Scratch register. Information persists in low power mode 0xBC 0x00000000 SCRATCH3 [31:0] read-write SCRATCH4 Scratch register. Information persists in low power mode 0xC0 0x00000000 SCRATCH4 [31:0] read-write SCRATCH5 Scratch register. Information persists in low power mode 0xC4 0x00000000 SCRATCH5 [31:0] read-write SCRATCH6 Scratch register. Information persists in low power mode 0xC8 0x00000000 SCRATCH6 [31:0] read-write SCRATCH7 Scratch register. Information persists in low power mode 0xCC 0x00000000 SCRATCH7 [31:0] read-write BOOT0 Scratch register. Information persists in low power mode 0xD0 0x00000000 BOOT0 [31:0] read-write BOOT1 Scratch register. Information persists in low power mode 0xD4 0x00000000 BOOT1 [31:0] read-write BOOT2 Scratch register. Information persists in low power mode 0xD8 0x00000000 BOOT2 [31:0] read-write BOOT3 Scratch register. Information persists in low power mode 0xDC 0x00000000 BOOT3 [31:0] read-write INTR Raw Interrupts 0xE0 0x00000000 PWRUP_WHILE_WAITING Source is state.pwrup_while_waiting [3:3] read-only STATE_REQ_IGNORED Source is state.req_ignored [2:2] read-only TIMER [1:1] read-only VREG_OUTPUT_LOW [0:0] read-write oneToClear INTE Interrupt Enable 0xE4 0x00000000 PWRUP_WHILE_WAITING Source is state.pwrup_while_waiting [3:3] read-write STATE_REQ_IGNORED Source is state.req_ignored [2:2] read-write TIMER [1:1] read-write VREG_OUTPUT_LOW [0:0] read-write INTF Interrupt Force 0xE8 0x00000000 PWRUP_WHILE_WAITING Source is state.pwrup_while_waiting [3:3] read-write STATE_REQ_IGNORED Source is state.req_ignored [2:2] read-write TIMER [1:1] read-write VREG_OUTPUT_LOW [0:0] read-write INTS Interrupt status after masking & forcing 0xEC 0x00000000 PWRUP_WHILE_WAITING Source is state.pwrup_while_waiting [3:3] read-only STATE_REQ_IGNORED Source is state.req_ignored [2:2] read-only TIMER [1:1] read-only VREG_OUTPUT_LOW [0:0] read-only WATCHDOG 0x400D8000 0x0 0x2C registers CTRL Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. 0x0 0x07000000 TRIGGER Trigger a watchdog reset [31:31] write-only ENABLE When not enabled the watchdog timer is paused [30:30] read-write PAUSE_DBG1 Pause the watchdog timer when processor 1 is in debug mode [26:26] read-write PAUSE_DBG0 Pause the watchdog timer when processor 0 is in debug mode [25:25] read-write PAUSE_JTAG Pause the watchdog timer when JTAG is accessing the bus fabric [24:24] read-write TIME Indicates the time in usec before a watchdog reset will be triggered [23:0] read-only LOAD Load the watchdog timer. The maximum setting is 0xffffff which corresponds to approximately 16 seconds. 0x4 0x00000000 LOAD [23:0] write-only REASON Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. Additionally, as of RP2350, a debugger warm reset of either core (SYSRESETREQ or hartreset) will also clear the watchdog reason register, so that software loaded under the debugger following a watchdog timeout will not continue to see the timeout condition. 0x8 0x00000000 FORCE [1:1] read-only TIMER [0:0] read-only SCRATCH0 Scratch register. Information persists through soft reset of the chip. 0xC 0x00000000 SCRATCH0 [31:0] read-write SCRATCH1 Scratch register. Information persists through soft reset of the chip. 0x10 0x00000000 SCRATCH1 [31:0] read-write SCRATCH2 Scratch register. Information persists through soft reset of the chip. 0x14 0x00000000 SCRATCH2 [31:0] read-write SCRATCH3 Scratch register. Information persists through soft reset of the chip. 0x18 0x00000000 SCRATCH3 [31:0] read-write SCRATCH4 Scratch register. Information persists through soft reset of the chip. 0x1C 0x00000000 SCRATCH4 [31:0] read-write SCRATCH5 Scratch register. Information persists through soft reset of the chip. 0x20 0x00000000 SCRATCH5 [31:0] read-write SCRATCH6 Scratch register. Information persists through soft reset of the chip. 0x24 0x00000000 SCRATCH6 [31:0] read-write SCRATCH7 Scratch register. Information persists through soft reset of the chip. 0x28 0x00000000 SCRATCH7 [31:0] read-write DMA DMA with separate read and write masters 0x50000000 0x0 0xBC8 registers DMA_IRQ_0 10 DMA_IRQ_1 11 DMA_IRQ_2 12 DMA_IRQ_3 13 16 0x40 0-15 CH%s Cluster CH%s, containing CH?_READ_ADDR,CH??_READ_ADDR, CH?_WRITE_ADDR,CH??_WRITE_ADDR, CH?_TRANS_COUNT,CH??_TRANS_COUNT, CH?_CTRL_TRIG,CH??_CTRL_TRIG, CH?_AL1_CTRL,CH??_AL1_CTRL, CH?_AL1_READ_ADDR,CH??_AL1_READ_ADDR, CH?_AL1_WRITE_ADDR,CH??_AL1_WRITE_ADDR, CH?_AL1_TRANS_COUNT_TRIG,CH??_AL1_TRANS_COUNT_TRIG, CH?_AL2_CTRL,CH??_AL2_CTRL, CH?_AL2_TRANS_COUNT,CH??_AL2_TRANS_COUNT, CH?_AL2_READ_ADDR,CH??_AL2_READ_ADDR, CH?_AL2_WRITE_ADDR_TRIG,CH??_AL2_WRITE_ADDR_TRIG, CH?_AL3_CTRL,CH??_AL3_CTRL, CH?_AL3_WRITE_ADDR,CH??_AL3_WRITE_ADDR, CH?_AL3_TRANS_COUNT,CH??_AL3_TRANS_COUNT, CH?_AL3_READ_ADDR_TRIG,CH??_AL3_READ_ADDR_TRIG 0x0 CH_READ_ADDR DMA Channel 0 Read Address pointer 0x0 0x00000000 CH0_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH_WRITE_ADDR DMA Channel 0 Write Address pointer 0x4 0x00000000 CH0_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH_TRANS_COUNT DMA Channel 0 Transfer Count 0x8 0x00000000 MODE When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO. When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts. When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised. All other values are reserved. [31:28] read-write NORMAL 0 TRIGGER_SELF 1 ENDLESS 15 COUNT 28-bit transfer count (256 million transfers maximum). Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [27:0] read-write CH_CTRL_TRIG DMA Channel 0 Control and Status 0xC 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [26:26] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [25:25] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [24:24] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [23:23] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [22:17] read-write TREQ_SEL PIO0_TX0 Select PIO0's TX FIFO 0 as TREQ 0 PIO0_TX1 Select PIO0's TX FIFO 1 as TREQ 1 PIO0_TX2 Select PIO0's TX FIFO 2 as TREQ 2 PIO0_TX3 Select PIO0's TX FIFO 3 as TREQ 3 PIO0_RX0 Select PIO0's RX FIFO 0 as TREQ 4 PIO0_RX1 Select PIO0's RX FIFO 1 as TREQ 5 PIO0_RX2 Select PIO0's RX FIFO 2 as TREQ 6 PIO0_RX3 Select PIO0's RX FIFO 3 as TREQ 7 PIO1_TX0 Select PIO1's TX FIFO 0 as TREQ 8 PIO1_TX1 Select PIO1's TX FIFO 1 as TREQ 9 PIO1_TX2 Select PIO1's TX FIFO 2 as TREQ 10 PIO1_TX3 Select PIO1's TX FIFO 3 as TREQ 11 PIO1_RX0 Select PIO1's RX FIFO 0 as TREQ 12 PIO1_RX1 Select PIO1's RX FIFO 1 as TREQ 13 PIO1_RX2 Select PIO1's RX FIFO 2 as TREQ 14 PIO1_RX3 Select PIO1's RX FIFO 3 as TREQ 15 PIO2_TX0 Select PIO2's TX FIFO 0 as TREQ 16 PIO2_TX1 Select PIO2's TX FIFO 1 as TREQ 17 PIO2_TX2 Select PIO2's TX FIFO 2 as TREQ 18 PIO2_TX3 Select PIO2's TX FIFO 3 as TREQ 19 PIO2_RX0 Select PIO2's RX FIFO 0 as TREQ 20 PIO2_RX1 Select PIO2's RX FIFO 1 as TREQ 21 PIO2_RX2 Select PIO2's RX FIFO 2 as TREQ 22 PIO2_RX3 Select PIO2's RX FIFO 3 as TREQ 23 SPI0_TX Select SPI0's TX FIFO as TREQ 24 SPI0_RX Select SPI0's RX FIFO as TREQ 25 SPI1_TX Select SPI1's TX FIFO as TREQ 26 SPI1_RX Select SPI1's RX FIFO as TREQ 27 UART0_TX Select UART0's TX FIFO as TREQ 28 UART0_RX Select UART0's RX FIFO as TREQ 29 UART1_TX Select UART1's TX FIFO as TREQ 30 UART1_RX Select UART1's RX FIFO as TREQ 31 PWM_WRAP0 Select PWM Counter 0's Wrap Value as TREQ 32 PWM_WRAP1 Select PWM Counter 1's Wrap Value as TREQ 33 PWM_WRAP2 Select PWM Counter 2's Wrap Value as TREQ 34 PWM_WRAP3 Select PWM Counter 3's Wrap Value as TREQ 35 PWM_WRAP4 Select PWM Counter 4's Wrap Value as TREQ 36 PWM_WRAP5 Select PWM Counter 5's Wrap Value as TREQ 37 PWM_WRAP6 Select PWM Counter 6's Wrap Value as TREQ 38 PWM_WRAP7 Select PWM Counter 7's Wrap Value as TREQ 39 PWM_WRAP8 Select PWM Counter 8's Wrap Value as TREQ 40 PWM_WRAP9 Select PWM Counter 9's Wrap Value as TREQ 41 PWM_WRAP10 Select PWM Counter 10's Wrap Value as TREQ 42 PWM_WRAP11 Select PWM Counter 11's Wrap Value as TREQ 43 I2C0_TX Select I2C0's TX FIFO as TREQ 44 I2C0_RX Select I2C0's RX FIFO as TREQ 45 I2C1_TX Select I2C1's TX FIFO as TREQ 46 I2C1_RX Select I2C1's RX FIFO as TREQ 47 ADC Select ADC as TREQ 48 XIP_STREAM Select XIP_STREAM as TREQ 49 XIP_QMITX Select XIP_QMI's TX FIFO as TREQ 50 XIP_QMIRX Select XIP_QMI's RX FIFO as TREQ 51 HSTX Select HSTX as TREQ 52 CORESIGHT Select CORESIGHT as TREQ 53 SHA256 Select SHA256 as TREQ 54 TIMER0 Select Timer 0 as TREQ 59 TIMER1 Select Timer 1 as TREQ 60 TIMER2 Select Timer 2 as TREQ (Optional) 61 TIMER3 Select Timer 3 as TREQ (Optional) 62 PERMANENT Permanent request, for unpaced transfers. 63 CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. [16:13] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [12:12] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [11:8] read-write RING_NONE 0 INCR_WRITE_REV If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [7:7] read-write INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [6:6] read-write INCR_READ_REV If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH_AL1_CTRL DMA Channel 0 Control and Status 0x10 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [26:26] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [25:25] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [24:24] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [23:23] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [22:17] read-write TREQ_SEL PIO0_TX0 Select PIO0's TX FIFO 0 as TREQ 0 PIO0_TX1 Select PIO0's TX FIFO 1 as TREQ 1 PIO0_TX2 Select PIO0's TX FIFO 2 as TREQ 2 PIO0_TX3 Select PIO0's TX FIFO 3 as TREQ 3 PIO0_RX0 Select PIO0's RX FIFO 0 as TREQ 4 PIO0_RX1 Select PIO0's RX FIFO 1 as TREQ 5 PIO0_RX2 Select PIO0's RX FIFO 2 as TREQ 6 PIO0_RX3 Select PIO0's RX FIFO 3 as TREQ 7 PIO1_TX0 Select PIO1's TX FIFO 0 as TREQ 8 PIO1_TX1 Select PIO1's TX FIFO 1 as TREQ 9 PIO1_TX2 Select PIO1's TX FIFO 2 as TREQ 10 PIO1_TX3 Select PIO1's TX FIFO 3 as TREQ 11 PIO1_RX0 Select PIO1's RX FIFO 0 as TREQ 12 PIO1_RX1 Select PIO1's RX FIFO 1 as TREQ 13 PIO1_RX2 Select PIO1's RX FIFO 2 as TREQ 14 PIO1_RX3 Select PIO1's RX FIFO 3 as TREQ 15 PIO2_TX0 Select PIO2's TX FIFO 0 as TREQ 16 PIO2_TX1 Select PIO2's TX FIFO 1 as TREQ 17 PIO2_TX2 Select PIO2's TX FIFO 2 as TREQ 18 PIO2_TX3 Select PIO2's TX FIFO 3 as TREQ 19 PIO2_RX0 Select PIO2's RX FIFO 0 as TREQ 20 PIO2_RX1 Select PIO2's RX FIFO 1 as TREQ 21 PIO2_RX2 Select PIO2's RX FIFO 2 as TREQ 22 PIO2_RX3 Select PIO2's RX FIFO 3 as TREQ 23 SPI0_TX Select SPI0's TX FIFO as TREQ 24 SPI0_RX Select SPI0's RX FIFO as TREQ 25 SPI1_TX Select SPI1's TX FIFO as TREQ 26 SPI1_RX Select SPI1's RX FIFO as TREQ 27 UART0_TX Select UART0's TX FIFO as TREQ 28 UART0_RX Select UART0's RX FIFO as TREQ 29 UART1_TX Select UART1's TX FIFO as TREQ 30 UART1_RX Select UART1's RX FIFO as TREQ 31 PWM_WRAP0 Select PWM Counter 0's Wrap Value as TREQ 32 PWM_WRAP1 Select PWM Counter 1's Wrap Value as TREQ 33 PWM_WRAP2 Select PWM Counter 2's Wrap Value as TREQ 34 PWM_WRAP3 Select PWM Counter 3's Wrap Value as TREQ 35 PWM_WRAP4 Select PWM Counter 4's Wrap Value as TREQ 36 PWM_WRAP5 Select PWM Counter 5's Wrap Value as TREQ 37 PWM_WRAP6 Select PWM Counter 6's Wrap Value as TREQ 38 PWM_WRAP7 Select PWM Counter 7's Wrap Value as TREQ 39 PWM_WRAP8 Select PWM Counter 8's Wrap Value as TREQ 40 PWM_WRAP9 Select PWM Counter 9's Wrap Value as TREQ 41 PWM_WRAP10 Select PWM Counter 10's Wrap Value as TREQ 42 PWM_WRAP11 Select PWM Counter 11's Wrap Value as TREQ 43 I2C0_TX Select I2C0's TX FIFO as TREQ 44 I2C0_RX Select I2C0's RX FIFO as TREQ 45 I2C1_TX Select I2C1's TX FIFO as TREQ 46 I2C1_RX Select I2C1's RX FIFO as TREQ 47 ADC Select ADC as TREQ 48 XIP_STREAM Select XIP_STREAM as TREQ 49 XIP_QMITX Select XIP_QMI's TX FIFO as TREQ 50 XIP_QMIRX Select XIP_QMI's RX FIFO as TREQ 51 HSTX Select HSTX as TREQ 52 CORESIGHT Select CORESIGHT as TREQ 53 SHA256 Select SHA256 as TREQ 54 TIMER0 Select Timer 0 as TREQ 59 TIMER1 Select Timer 1 as TREQ 60 TIMER2 Select Timer 2 as TREQ (Optional) 61 TIMER3 Select Timer 3 as TREQ (Optional) 62 PERMANENT Permanent request, for unpaced transfers. 63 CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. [16:13] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [12:12] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [11:8] read-write RING_NONE 0 INCR_WRITE_REV If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [7:7] read-write INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [6:6] read-write INCR_READ_REV If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH_AL1_READ_ADDR Alias for channel 0 READ_ADDR register 0x14 0x00000000 CH0_AL1_READ_ADDR [31:0] read-write CH_AL1_WRITE_ADDR Alias for channel 0 WRITE_ADDR register 0x18 0x00000000 CH0_AL1_WRITE_ADDR [31:0] read-write CH_AL1_TRANS_COUNT_TRIG Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x1C 0x00000000 CH0_AL1_TRANS_COUNT_TRIG [31:0] read-write CH_AL2_CTRL DMA Channel 0 Control and Status 0x20 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [26:26] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [25:25] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [24:24] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [23:23] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [22:17] read-write TREQ_SEL PIO0_TX0 Select PIO0's TX FIFO 0 as TREQ 0 PIO0_TX1 Select PIO0's TX FIFO 1 as TREQ 1 PIO0_TX2 Select PIO0's TX FIFO 2 as TREQ 2 PIO0_TX3 Select PIO0's TX FIFO 3 as TREQ 3 PIO0_RX0 Select PIO0's RX FIFO 0 as TREQ 4 PIO0_RX1 Select PIO0's RX FIFO 1 as TREQ 5 PIO0_RX2 Select PIO0's RX FIFO 2 as TREQ 6 PIO0_RX3 Select PIO0's RX FIFO 3 as TREQ 7 PIO1_TX0 Select PIO1's TX FIFO 0 as TREQ 8 PIO1_TX1 Select PIO1's TX FIFO 1 as TREQ 9 PIO1_TX2 Select PIO1's TX FIFO 2 as TREQ 10 PIO1_TX3 Select PIO1's TX FIFO 3 as TREQ 11 PIO1_RX0 Select PIO1's RX FIFO 0 as TREQ 12 PIO1_RX1 Select PIO1's RX FIFO 1 as TREQ 13 PIO1_RX2 Select PIO1's RX FIFO 2 as TREQ 14 PIO1_RX3 Select PIO1's RX FIFO 3 as TREQ 15 PIO2_TX0 Select PIO2's TX FIFO 0 as TREQ 16 PIO2_TX1 Select PIO2's TX FIFO 1 as TREQ 17 PIO2_TX2 Select PIO2's TX FIFO 2 as TREQ 18 PIO2_TX3 Select PIO2's TX FIFO 3 as TREQ 19 PIO2_RX0 Select PIO2's RX FIFO 0 as TREQ 20 PIO2_RX1 Select PIO2's RX FIFO 1 as TREQ 21 PIO2_RX2 Select PIO2's RX FIFO 2 as TREQ 22 PIO2_RX3 Select PIO2's RX FIFO 3 as TREQ 23 SPI0_TX Select SPI0's TX FIFO as TREQ 24 SPI0_RX Select SPI0's RX FIFO as TREQ 25 SPI1_TX Select SPI1's TX FIFO as TREQ 26 SPI1_RX Select SPI1's RX FIFO as TREQ 27 UART0_TX Select UART0's TX FIFO as TREQ 28 UART0_RX Select UART0's RX FIFO as TREQ 29 UART1_TX Select UART1's TX FIFO as TREQ 30 UART1_RX Select UART1's RX FIFO as TREQ 31 PWM_WRAP0 Select PWM Counter 0's Wrap Value as TREQ 32 PWM_WRAP1 Select PWM Counter 1's Wrap Value as TREQ 33 PWM_WRAP2 Select PWM Counter 2's Wrap Value as TREQ 34 PWM_WRAP3 Select PWM Counter 3's Wrap Value as TREQ 35 PWM_WRAP4 Select PWM Counter 4's Wrap Value as TREQ 36 PWM_WRAP5 Select PWM Counter 5's Wrap Value as TREQ 37 PWM_WRAP6 Select PWM Counter 6's Wrap Value as TREQ 38 PWM_WRAP7 Select PWM Counter 7's Wrap Value as TREQ 39 PWM_WRAP8 Select PWM Counter 8's Wrap Value as TREQ 40 PWM_WRAP9 Select PWM Counter 9's Wrap Value as TREQ 41 PWM_WRAP10 Select PWM Counter 10's Wrap Value as TREQ 42 PWM_WRAP11 Select PWM Counter 11's Wrap Value as TREQ 43 I2C0_TX Select I2C0's TX FIFO as TREQ 44 I2C0_RX Select I2C0's RX FIFO as TREQ 45 I2C1_TX Select I2C1's TX FIFO as TREQ 46 I2C1_RX Select I2C1's RX FIFO as TREQ 47 ADC Select ADC as TREQ 48 XIP_STREAM Select XIP_STREAM as TREQ 49 XIP_QMITX Select XIP_QMI's TX FIFO as TREQ 50 XIP_QMIRX Select XIP_QMI's RX FIFO as TREQ 51 HSTX Select HSTX as TREQ 52 CORESIGHT Select CORESIGHT as TREQ 53 SHA256 Select SHA256 as TREQ 54 TIMER0 Select Timer 0 as TREQ 59 TIMER1 Select Timer 1 as TREQ 60 TIMER2 Select Timer 2 as TREQ (Optional) 61 TIMER3 Select Timer 3 as TREQ (Optional) 62 PERMANENT Permanent request, for unpaced transfers. 63 CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. [16:13] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [12:12] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [11:8] read-write RING_NONE 0 INCR_WRITE_REV If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [7:7] read-write INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [6:6] read-write INCR_READ_REV If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH_AL2_TRANS_COUNT Alias for channel 0 TRANS_COUNT register 0x24 0x00000000 CH0_AL2_TRANS_COUNT [31:0] read-write CH_AL2_READ_ADDR Alias for channel 0 READ_ADDR register 0x28 0x00000000 CH0_AL2_READ_ADDR [31:0] read-write CH_AL2_WRITE_ADDR_TRIG Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x2C 0x00000000 CH0_AL2_WRITE_ADDR_TRIG [31:0] read-write CH_AL3_CTRL DMA Channel 0 Control and Status 0x30 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [26:26] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [25:25] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [24:24] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [23:23] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [22:17] read-write TREQ_SEL PIO0_TX0 Select PIO0's TX FIFO 0 as TREQ 0 PIO0_TX1 Select PIO0's TX FIFO 1 as TREQ 1 PIO0_TX2 Select PIO0's TX FIFO 2 as TREQ 2 PIO0_TX3 Select PIO0's TX FIFO 3 as TREQ 3 PIO0_RX0 Select PIO0's RX FIFO 0 as TREQ 4 PIO0_RX1 Select PIO0's RX FIFO 1 as TREQ 5 PIO0_RX2 Select PIO0's RX FIFO 2 as TREQ 6 PIO0_RX3 Select PIO0's RX FIFO 3 as TREQ 7 PIO1_TX0 Select PIO1's TX FIFO 0 as TREQ 8 PIO1_TX1 Select PIO1's TX FIFO 1 as TREQ 9 PIO1_TX2 Select PIO1's TX FIFO 2 as TREQ 10 PIO1_TX3 Select PIO1's TX FIFO 3 as TREQ 11 PIO1_RX0 Select PIO1's RX FIFO 0 as TREQ 12 PIO1_RX1 Select PIO1's RX FIFO 1 as TREQ 13 PIO1_RX2 Select PIO1's RX FIFO 2 as TREQ 14 PIO1_RX3 Select PIO1's RX FIFO 3 as TREQ 15 PIO2_TX0 Select PIO2's TX FIFO 0 as TREQ 16 PIO2_TX1 Select PIO2's TX FIFO 1 as TREQ 17 PIO2_TX2 Select PIO2's TX FIFO 2 as TREQ 18 PIO2_TX3 Select PIO2's TX FIFO 3 as TREQ 19 PIO2_RX0 Select PIO2's RX FIFO 0 as TREQ 20 PIO2_RX1 Select PIO2's RX FIFO 1 as TREQ 21 PIO2_RX2 Select PIO2's RX FIFO 2 as TREQ 22 PIO2_RX3 Select PIO2's RX FIFO 3 as TREQ 23 SPI0_TX Select SPI0's TX FIFO as TREQ 24 SPI0_RX Select SPI0's RX FIFO as TREQ 25 SPI1_TX Select SPI1's TX FIFO as TREQ 26 SPI1_RX Select SPI1's RX FIFO as TREQ 27 UART0_TX Select UART0's TX FIFO as TREQ 28 UART0_RX Select UART0's RX FIFO as TREQ 29 UART1_TX Select UART1's TX FIFO as TREQ 30 UART1_RX Select UART1's RX FIFO as TREQ 31 PWM_WRAP0 Select PWM Counter 0's Wrap Value as TREQ 32 PWM_WRAP1 Select PWM Counter 1's Wrap Value as TREQ 33 PWM_WRAP2 Select PWM Counter 2's Wrap Value as TREQ 34 PWM_WRAP3 Select PWM Counter 3's Wrap Value as TREQ 35 PWM_WRAP4 Select PWM Counter 4's Wrap Value as TREQ 36 PWM_WRAP5 Select PWM Counter 5's Wrap Value as TREQ 37 PWM_WRAP6 Select PWM Counter 6's Wrap Value as TREQ 38 PWM_WRAP7 Select PWM Counter 7's Wrap Value as TREQ 39 PWM_WRAP8 Select PWM Counter 8's Wrap Value as TREQ 40 PWM_WRAP9 Select PWM Counter 9's Wrap Value as TREQ 41 PWM_WRAP10 Select PWM Counter 10's Wrap Value as TREQ 42 PWM_WRAP11 Select PWM Counter 11's Wrap Value as TREQ 43 I2C0_TX Select I2C0's TX FIFO as TREQ 44 I2C0_RX Select I2C0's RX FIFO as TREQ 45 I2C1_TX Select I2C1's TX FIFO as TREQ 46 I2C1_RX Select I2C1's RX FIFO as TREQ 47 ADC Select ADC as TREQ 48 XIP_STREAM Select XIP_STREAM as TREQ 49 XIP_QMITX Select XIP_QMI's TX FIFO as TREQ 50 XIP_QMIRX Select XIP_QMI's RX FIFO as TREQ 51 HSTX Select HSTX as TREQ 52 CORESIGHT Select CORESIGHT as TREQ 53 SHA256 Select SHA256 as TREQ 54 TIMER0 Select Timer 0 as TREQ 59 TIMER1 Select Timer 1 as TREQ 60 TIMER2 Select Timer 2 as TREQ (Optional) 61 TIMER3 Select Timer 3 as TREQ (Optional) 62 PERMANENT Permanent request, for unpaced transfers. 63 CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. \n Reset value is 0, which means for channels 1 and above the default will be to chain to channel 0 - set this field to avoid this behaviour. [16:13] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [12:12] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [11:8] read-write RING_NONE 0 INCR_WRITE_REV If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer. If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [7:7] read-write INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [6:6] read-write INCR_READ_REV If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer. If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH_AL3_WRITE_ADDR Alias for channel 0 WRITE_ADDR register 0x34 0x00000000 CH0_AL3_WRITE_ADDR [31:0] read-write CH_AL3_TRANS_COUNT Alias for channel 0 TRANS_COUNT register 0x38 0x00000000 CH0_AL3_TRANS_COUNT [31:0] read-write CH_AL3_READ_ADDR_TRIG Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x3C 0x00000000 CH0_AL3_READ_ADDR_TRIG [31:0] read-write INTR Interrupt Status (raw) 0x400 0x00000000 INTR Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. [15:0] read-write oneToClear INTE0 Interrupt Enables for IRQ 0 0x404 0x00000000 INTE0 Set bit n to pass interrupts from channel n to DMA IRQ 0. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0. [15:0] read-write INTF0 Force Interrupts 0x408 0x00000000 INTF0 Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared. [15:0] read-write INTS0 Interrupt Status for IRQ 0 0x40C 0x00000000 INTS0 Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes. [15:0] read-write oneToClear INTR1 Interrupt Status (raw) 0x410 0x00000000 INTR1 Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. [15:0] read-write oneToClear INTE1 Interrupt Enables for IRQ 1 0x414 0x00000000 INTE1 Set bit n to pass interrupts from channel n to DMA IRQ 1. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1. [15:0] read-write INTF1 Force Interrupts 0x418 0x00000000 INTF1 Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared. [15:0] read-write INTS1 Interrupt Status for IRQ 1 0x41C 0x00000000 INTS1 Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes. [15:0] read-write oneToClear INTR2 Interrupt Status (raw) 0x420 0x00000000 INTR2 Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. [15:0] read-write oneToClear INTE2 Interrupt Enables for IRQ 2 0x424 0x00000000 INTE2 Set bit n to pass interrupts from channel n to DMA IRQ 2. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2. [15:0] read-write INTF2 Force Interrupts 0x428 0x00000000 INTF2 Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared. [15:0] read-write INTS2 Interrupt Status for IRQ 2 0x42C 0x00000000 INTS2 Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes. [15:0] read-write oneToClear INTR3 Interrupt Status (raw) 0x430 0x00000000 INTR3 Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3. Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3. The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains. It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0. If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes. [15:0] read-write oneToClear INTE3 Interrupt Enables for IRQ 3 0x434 0x00000000 INTE3 Set bit n to pass interrupts from channel n to DMA IRQ 3. Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3. [15:0] read-write INTF3 Force Interrupts 0x438 0x00000000 INTF3 Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared. [15:0] read-write INTS3 Interrupt Status for IRQ 3 0x43C 0x00000000 INTS3 Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted. Channel interrupts can be cleared by writing a bit mask here. Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes. [15:0] read-write oneToClear TIMER0 Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x440 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write TIMER1 Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x444 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write TIMER2 Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x448 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write TIMER3 Pacing (X/Y) fractional timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x44C 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write MULTI_CHAN_TRIGGER Trigger one or more channels simultaneously 0x450 0x00000000 MULTI_CHAN_TRIGGER Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. [15:0] write-only SNIFF_CTRL Sniffer Control 0x454 0x00000000 OUT_INV If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. [11:11] read-write OUT_REV If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. [10:10] read-write BSWAP Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. [9:9] read-write CALC [8:5] read-write CRC32 Calculate a CRC-32 (IEEE802.3 polynomial) 0 CRC32R Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data 1 CRC16 Calculate a CRC-16-CCITT 2 CRC16R Calculate a CRC-16-CCITT with bit reversed data 3 EVEN XOR reduction over all data. == 1 if the total 1 population count is odd. 14 SUM Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) 15 DMACH DMA channel for Sniffer to observe [4:1] read-write EN Enable sniffer [0:0] read-write SNIFF_DATA Data accumulator for sniff hardware 0x458 0x00000000 SNIFF_DATA Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. [31:0] read-write FIFO_LEVELS Debug RAF, WAF, TDF levels 0x460 0x00000000 RAF_LVL Current Read-Address-FIFO fill level [23:16] read-only WAF_LVL Current Write-Address-FIFO fill level [15:8] read-only TDF_LVL Current Transfer-Data-FIFO fill level [7:0] read-only CHAN_ABORT Abort an in-progress transfer sequence on one or more channels 0x464 0x00000000 CHAN_ABORT Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. [15:0] write-only N_CHANNELS The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. 0x468 0x00000000 N_CHANNELS [4:0] read-only SECCFG_CH0 Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x480 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH1 Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x484 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH2 Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x488 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH3 Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x48C 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH4 Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x490 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH5 Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x494 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH6 Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x498 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH7 Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x49C 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH8 Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4A0 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH9 Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4A4 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH10 Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4A8 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH11 Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4AC 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH12 Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4B0 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH13 Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4B4 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH14 Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4B8 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_CH15 Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses. If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel. This register automatically locks down (becomes read-only) once software starts to configure the channel. This register is world-readable, but is writable only from a Secure, Privileged context. 0x4BC 0x00000003 LOCK LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases. Once its LOCK bit is set, this register becomes read-only. A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit. [2:2] read-write S Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses. If 1, this channel is controllable only from a Secure context. [1:1] read-write P Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses. If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level. [0:0] read-write SECCFG_IRQ0 Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. 0x4C0 0x00000003 S Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. [1:1] read-write P Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. [0:0] read-write SECCFG_IRQ1 Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. 0x4C4 0x00000003 S Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. [1:1] read-write P Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. [0:0] read-write SECCFG_IRQ2 Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. 0x4C8 0x00000003 S Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. [1:1] read-write P Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. [0:0] read-write SECCFG_IRQ3 Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags. 0x4CC 0x00000003 S Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context. If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels. [1:1] read-write P Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context. If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels. [0:0] read-write SECCFG_MISC Miscellaneous security configuration 0x4D0 0x000003FF TIMER3_S If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels. [9:9] read-write TIMER3_P If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels. [8:8] read-write TIMER2_S If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels. [7:7] read-write TIMER2_P If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels. [6:6] read-write TIMER1_S If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels. [5:5] read-write TIMER1_P If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels. [4:4] read-write TIMER0_S If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels. [3:3] read-write TIMER0_P If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels. [2:2] read-write SNIFF_S If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context. If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels. [1:1] read-write SNIFF_P If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0. If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels. [0:0] read-write MPU_CTRL Control register for DMA MPU. Accessible only from a Privileged context. 0x500 0x00000000 NS_HIDE_ADDR By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map. [3:3] read-write S Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0) [2:2] read-write P Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0) [1:1] read-write MPU_BAR0 Base address register for MPU region 0. Writable only from a Secure, Privileged context. 0x504 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR0 Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x508 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write MPU_BAR1 Base address register for MPU region 1. Writable only from a Secure, Privileged context. 0x50C 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR1 Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x510 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write MPU_BAR2 Base address register for MPU region 2. Writable only from a Secure, Privileged context. 0x514 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR2 Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x518 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write MPU_BAR3 Base address register for MPU region 3. Writable only from a Secure, Privileged context. 0x51C 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR3 Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x520 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write MPU_BAR4 Base address register for MPU region 4. Writable only from a Secure, Privileged context. 0x524 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR4 Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x528 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write MPU_BAR5 Base address register for MPU region 5. Writable only from a Secure, Privileged context. 0x52C 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR5 Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x530 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write MPU_BAR6 Base address register for MPU region 6. Writable only from a Secure, Privileged context. 0x534 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR6 Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x538 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write MPU_BAR7 Base address register for MPU region 7. Writable only from a Secure, Privileged context. 0x53C 0x00000000 ADDR This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write MPU_LAR7 Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit. 0x540 0x00000000 ADDR Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context. [31:5] read-write S Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled. [2:2] read-write P Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context. [1:1] read-write EN Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P. [0:0] read-write CH0_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x800 0x00000000 CH0_DBG_CTDREQ [5:0] read-write oneToClear CH0_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x804 0x00000000 CH0_DBG_TCR [31:0] read-only CH1_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x840 0x00000000 CH1_DBG_CTDREQ [5:0] read-write oneToClear CH1_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x844 0x00000000 CH1_DBG_TCR [31:0] read-only CH2_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x880 0x00000000 CH2_DBG_CTDREQ [5:0] read-write oneToClear CH2_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x884 0x00000000 CH2_DBG_TCR [31:0] read-only CH3_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x8C0 0x00000000 CH3_DBG_CTDREQ [5:0] read-write oneToClear CH3_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x8C4 0x00000000 CH3_DBG_TCR [31:0] read-only CH4_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x900 0x00000000 CH4_DBG_CTDREQ [5:0] read-write oneToClear CH4_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x904 0x00000000 CH4_DBG_TCR [31:0] read-only CH5_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x940 0x00000000 CH5_DBG_CTDREQ [5:0] read-write oneToClear CH5_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x944 0x00000000 CH5_DBG_TCR [31:0] read-only CH6_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x980 0x00000000 CH6_DBG_CTDREQ [5:0] read-write oneToClear CH6_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x984 0x00000000 CH6_DBG_TCR [31:0] read-only CH7_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x9C0 0x00000000 CH7_DBG_CTDREQ [5:0] read-write oneToClear CH7_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x9C4 0x00000000 CH7_DBG_TCR [31:0] read-only CH8_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xA00 0x00000000 CH8_DBG_CTDREQ [5:0] read-write oneToClear CH8_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xA04 0x00000000 CH8_DBG_TCR [31:0] read-only CH9_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xA40 0x00000000 CH9_DBG_CTDREQ [5:0] read-write oneToClear CH9_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xA44 0x00000000 CH9_DBG_TCR [31:0] read-only CH10_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xA80 0x00000000 CH10_DBG_CTDREQ [5:0] read-write oneToClear CH10_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xA84 0x00000000 CH10_DBG_TCR [31:0] read-only CH11_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xAC0 0x00000000 CH11_DBG_CTDREQ [5:0] read-write oneToClear CH11_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xAC4 0x00000000 CH11_DBG_TCR [31:0] read-only CH12_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xB00 0x00000000 CH12_DBG_CTDREQ [5:0] read-write oneToClear CH12_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xB04 0x00000000 CH12_DBG_TCR [31:0] read-only CH13_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xB40 0x00000000 CH13_DBG_CTDREQ [5:0] read-write oneToClear CH13_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xB44 0x00000000 CH13_DBG_TCR [31:0] read-only CH14_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xB80 0x00000000 CH14_DBG_CTDREQ [5:0] read-write oneToClear CH14_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xB84 0x00000000 CH14_DBG_TCR [31:0] read-only CH15_DBG_CTDREQ Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0xBC0 0x00000000 CH15_DBG_CTDREQ [5:0] read-write oneToClear CH15_DBG_TCR Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0xBC4 0x00000000 CH15_DBG_TCR [31:0] read-only TIMER0 Controls time and alarms time is a 64 bit value indicating the time since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing 0x400B0000 0x0 0x4C registers TIMER0_IRQ_0 0 TIMER0_IRQ_1 1 TIMER0_IRQ_2 2 TIMER0_IRQ_3 3 TIMEHW Write to bits 63:32 of time always write timelw before timehw 0x0 0x00000000 TIMEHW [31:0] write-only TIMELW Write to bits 31:0 of time writes do not get copied to time until timehw is written 0x4 0x00000000 TIMELW [31:0] write-only TIMEHR Read from bits 63:32 of time always read timelr before timehr 0x8 0x00000000 TIMEHR [31:0] read-only TIMELR Read from bits 31:0 of time 0xC 0x00000000 TIMELR [31:0] read-only modify ALARM0 Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x10 0x00000000 ALARM0 [31:0] read-write ALARM1 Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x14 0x00000000 ALARM1 [31:0] read-write ALARM2 Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x18 0x00000000 ALARM2 [31:0] read-write ALARM3 Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x1C 0x00000000 ALARM3 [31:0] read-write ARMED Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. 0x20 0x00000000 ARMED [3:0] read-write oneToClear TIMERAWH Raw read from bits 63:32 of time (no side effects) 0x24 0x00000000 TIMERAWH [31:0] read-only TIMERAWL Raw read from bits 31:0 of time (no side effects) 0x28 0x00000000 TIMERAWL [31:0] read-only DBGPAUSE Set bits high to enable pause when the corresponding debug ports are active 0x2C 0x00000007 DBG1 Pause when processor 1 is in debug mode [2:2] read-write DBG0 Pause when processor 0 is in debug mode [1:1] read-write PAUSE Set high to pause the timer 0x30 0x00000000 PAUSE [0:0] read-write LOCKED Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset) 0x34 0x00000000 LOCKED [0:0] read-write SOURCE Selects the source for the timer. Defaults to the normal tick configured in the ticks block (typically configured to 1 microsecond). Writing to 1 will ignore the tick and count clk_sys cycles instead. 0x38 0x00000000 CLK_SYS [0:0] read-write TICK 0 CLK_SYS 1 INTR Raw Interrupts 0x3C 0x00000000 ALARM_3 [3:3] read-write oneToClear ALARM_2 [2:2] read-write oneToClear ALARM_1 [1:1] read-write oneToClear ALARM_0 [0:0] read-write oneToClear INTE Interrupt Enable 0x40 0x00000000 ALARM_3 [3:3] read-write ALARM_2 [2:2] read-write ALARM_1 [1:1] read-write ALARM_0 [0:0] read-write INTF Interrupt Force 0x44 0x00000000 ALARM_3 [3:3] read-write ALARM_2 [2:2] read-write ALARM_1 [1:1] read-write ALARM_0 [0:0] read-write INTS Interrupt status after masking & forcing 0x48 0x00000000 ALARM_3 [3:3] read-only ALARM_2 [2:2] read-only ALARM_1 [1:1] read-only ALARM_0 [0:0] read-only TIMER1 0x400B8000 TIMER1_IRQ_0 4 TIMER1_IRQ_1 5 TIMER1_IRQ_2 6 TIMER1_IRQ_3 7 PWM Simple PWM 0x400A8000 0x0 0x110 registers PWM_IRQ_WRAP_0 8 PWM_IRQ_WRAP_1 9 12 0x14 0-11 CH%s Cluster CH%s, containing CH*_CC, CH*_CSR, CH*_CTR, CH*_DIV, CH*_TOP 0x0 CC Counter compare values 0xC 0x00000000 B [31:16] read-write A [15:0] read-write CSR Control and status register 0x0 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div Free-running counting at rate dictated by fractional divider 0 level Fractional divider operation is gated by the PWM B pin. 1 rise Counter advances with each rising edge of the PWM B pin. 2 fall Counter advances with each falling edge of the PWM B pin. 3 B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CTR Direct access to the PWM counter 0x8 0x00000000 CTR [15:0] read-write DIV INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x4 0x00000010 INT [11:4] read-write FRAC [3:0] read-write TOP Counter wrap value 0x10 0x0000FFFF TOP [15:0] read-write EN This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. 0xF0 0x00000000 CH11 [11:11] read-write CH10 [10:10] read-write CH9 [9:9] read-write CH8 [8:8] read-write CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write INTR Raw Interrupts 0xF4 0x00000000 CH11 [11:11] read-write oneToClear CH10 [10:10] read-write oneToClear CH9 [9:9] read-write oneToClear CH8 [8:8] read-write oneToClear CH7 [7:7] read-write oneToClear CH6 [6:6] read-write oneToClear CH5 [5:5] read-write oneToClear CH4 [4:4] read-write oneToClear CH3 [3:3] read-write oneToClear CH2 [2:2] read-write oneToClear CH1 [1:1] read-write oneToClear CH0 [0:0] read-write oneToClear IRQ0_INTE Interrupt Enable for irq0 0xF8 0x00000000 CH11 [11:11] read-write CH10 [10:10] read-write CH9 [9:9] read-write CH8 [8:8] read-write CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write IRQ0_INTF Interrupt Force for irq0 0xFC 0x00000000 CH11 [11:11] read-write CH10 [10:10] read-write CH9 [9:9] read-write CH8 [8:8] read-write CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write IRQ0_INTS Interrupt status after masking & forcing for irq0 0x100 0x00000000 CH11 [11:11] read-only CH10 [10:10] read-only CH9 [9:9] read-only CH8 [8:8] read-only CH7 [7:7] read-only CH6 [6:6] read-only CH5 [5:5] read-only CH4 [4:4] read-only CH3 [3:3] read-only CH2 [2:2] read-only CH1 [1:1] read-only CH0 [0:0] read-only IRQ1_INTE Interrupt Enable for irq1 0x104 0x00000000 CH11 [11:11] read-write CH10 [10:10] read-write CH9 [9:9] read-write CH8 [8:8] read-write CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write IRQ1_INTF Interrupt Force for irq1 0x108 0x00000000 CH11 [11:11] read-write CH10 [10:10] read-write CH9 [9:9] read-write CH8 [8:8] read-write CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write IRQ1_INTS Interrupt status after masking & forcing for irq1 0x10C 0x00000000 CH11 [11:11] read-only CH10 [10:10] read-only CH9 [9:9] read-only CH8 [8:8] read-only CH7 [7:7] read-only CH6 [6:6] read-only CH5 [5:5] read-only CH4 [4:4] read-only CH3 [3:3] read-only CH2 [2:2] read-only CH1 [1:1] read-only CH0 [0:0] read-only ADC Control and data interface to SAR ADC 0x400A0000 0x0 0x24 registers ADC_IRQ_FIFO 35 CS ADC Control and Status 0x0 0x00000000 RROBIN Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel. [24:16] read-write AINSEL Select analog mux input. Updated automatically in round-robin mode. This is corrected for the package option so only ADC channels which are bonded are available, and in the correct order [15:12] read-write ERR_STICKY Some past ADC conversion encountered an error. Write 1 to clear. [10:10] read-write oneToClear ERR The most recent ADC conversion encountered an error; result is undefined or noisy. [9:9] read-only READY 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress. [8:8] read-only START_MANY Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. [3:3] read-write START_ONCE Start a single conversion. Self-clearing. Ignored if start_many is asserted. [2:2] write-only TS_EN Power on temperature sensor. 1 - enabled. 0 - disabled. [1:1] read-write EN Power on ADC and enable its clock. 1 - enabled. 0 - disabled. [0:0] read-write RESULT Result of most recent ADC conversion 0x4 0x00000000 RESULT [11:0] read-only FCS FIFO control and status 0x8 0x00000000 THRESH DREQ/IRQ asserted when level >= threshold [27:24] read-write LEVEL The number of conversion results currently waiting in the FIFO [19:16] read-only OVER 1 if the FIFO has been overflowed. Write 1 to clear. [11:11] read-write oneToClear UNDER 1 if the FIFO has been underflowed. Write 1 to clear. [10:10] read-write oneToClear FULL [9:9] read-only EMPTY [8:8] read-only DREQ_EN If 1: assert DMA requests when FIFO contains data [3:3] read-write ERR If 1: conversion error bit appears in the FIFO alongside the result [2:2] read-write SHIFT If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. [1:1] read-write EN If 1: write result to the FIFO after each conversion. [0:0] read-write FIFO Conversion result FIFO 0xC 0x00000000 ERR 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. [15:15] read-only modify VAL [11:0] read-only modify DIV Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 0x10 0x00000000 INT Integer part of clock divisor. [23:8] read-write FRAC Fractional part of clock divisor. First-order delta-sigma. [7:0] read-write INTR Raw Interrupts 0x14 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-only INTE Interrupt Enable 0x18 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-write INTF Interrupt Force 0x1C 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-write INTS Interrupt status after masking & forcing 0x20 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-only I2C0 DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16 0x40090000 0x0 0x100 registers I2C0_IRQ 36 IC_CON I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. 0x0 0x00000065 STOP_DET_IF_MASTER_ACTIVE Master issues the STOP_DET interrupt irrespective of whether master is active or not [10:10] read-only RX_FIFO_FULL_HLD_CTRL This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. [9:9] read-write DISABLED Overflow when RX_FIFO is full 0 ENABLED Hold bus when RX_FIFO is full 1 TX_EMPTY_CTRL This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. [8:8] read-write DISABLED Default behaviour of TX_EMPTY interrupt 0 ENABLED Controlled generation of TX_EMPTY interrupt 1 STOP_DET_IFADDRESSED In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). [7:7] read-write DISABLED slave issues STOP_DET intr always 0 ENABLED slave issues STOP_DET intr only if addressed 1 IC_SLAVE_DISABLE This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. [6:6] read-write SLAVE_ENABLED Slave mode is enabled 0 SLAVE_DISABLED Slave mode is disabled 1 IC_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED [5:5] read-write DISABLED Master restart disabled 0 ENABLED Master restart enabled 1 IC_10BITADDR_MASTER Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing [4:4] read-write ADDR_7BITS Master 7Bit addressing mode 0 ADDR_10BITS Master 10Bit addressing mode 1 IC_10BITADDR_SLAVE When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. [3:3] read-write ADDR_7BITS Slave 7Bit addressing 0 ADDR_10BITS Slave 10Bit addressing 1 SPEED These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 [2:1] read-write STANDARD Standard Speed mode of operation 1 FAST Fast or Fast Plus mode of operation 2 HIGH High Speed mode of operation 3 MASTER_MODE This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. [0:0] read-write DISABLED Master mode is disabled 0 ENABLED Master mode is enabled 1 IC_TAR I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. 0x4 0x00000055 SPECIAL This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 [11:11] read-write DISABLED Disables programming of GENERAL_CALL or START_BYTE transmission 0 ENABLED Enables programming of GENERAL_CALL or START_BYTE transmission 1 GC_OR_START If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 [10:10] read-write GENERAL_CALL GENERAL_CALL byte transmission 0 START_BYTE START byte transmission 1 IC_TAR This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. [9:0] read-write IC_SAR I2C Slave Address Register 0x8 0x00000055 IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. [9:0] read-write IC_DATA_CMD I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. 0x10 0x00000000 FIRST_DATA_BYTE Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. [11:11] read-only INACTIVE Sequential data byte received 0 ACTIVE Non sequential data byte received 1 RESTART This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0 [10:10] write-only DISABLE Don't Issue RESTART before this command 0 ENABLE Issue RESTART before this command 1 STOP This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 [9:9] write-only DISABLE Don't Issue STOP after this command 0 ENABLE Issue STOP after this command 1 CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0 [8:8] write-only WRITE Master Write Command 0 READ Master Read Command 1 DAT This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0 [7:0] read-write IC_SS_SCL_HCNT Standard Speed I2C Clock SCL High Count Register 0x14 0x00000028 IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. [15:0] read-write IC_SS_SCL_LCNT Standard Speed I2C Clock SCL Low Count Register 0x18 0x0000002F IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. [15:0] read-write IC_FS_SCL_HCNT Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register 0x1C 0x00000006 IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. [15:0] read-write IC_FS_SCL_LCNT Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register 0x20 0x0000000D IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. [15:0] read-write IC_INTR_STAT I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. 0x2C 0x00000000 R_RESTART_DET See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0 [12:12] read-only INACTIVE R_RESTART_DET interrupt is inactive 0 ACTIVE R_RESTART_DET interrupt is active 1 R_GEN_CALL See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0 [11:11] read-only INACTIVE R_GEN_CALL interrupt is inactive 0 ACTIVE R_GEN_CALL interrupt is active 1 R_START_DET See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0 [10:10] read-only INACTIVE R_START_DET interrupt is inactive 0 ACTIVE R_START_DET interrupt is active 1 R_STOP_DET See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0 [9:9] read-only INACTIVE R_STOP_DET interrupt is inactive 0 ACTIVE R_STOP_DET interrupt is active 1 R_ACTIVITY See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0 [8:8] read-only INACTIVE R_ACTIVITY interrupt is inactive 0 ACTIVE R_ACTIVITY interrupt is active 1 R_RX_DONE See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0 [7:7] read-only INACTIVE R_RX_DONE interrupt is inactive 0 ACTIVE R_RX_DONE interrupt is active 1 R_TX_ABRT See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0 [6:6] read-only INACTIVE R_TX_ABRT interrupt is inactive 0 ACTIVE R_TX_ABRT interrupt is active 1 R_RD_REQ See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0 [5:5] read-only INACTIVE R_RD_REQ interrupt is inactive 0 ACTIVE R_RD_REQ interrupt is active 1 R_TX_EMPTY See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0 [4:4] read-only INACTIVE R_TX_EMPTY interrupt is inactive 0 ACTIVE R_TX_EMPTY interrupt is active 1 R_TX_OVER See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0 [3:3] read-only INACTIVE R_TX_OVER interrupt is inactive 0 ACTIVE R_TX_OVER interrupt is active 1 R_RX_FULL See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0 [2:2] read-only INACTIVE R_RX_FULL interrupt is inactive 0 ACTIVE R_RX_FULL interrupt is active 1 R_RX_OVER See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 [1:1] read-only INACTIVE R_RX_OVER interrupt is inactive 0 ACTIVE R_RX_OVER interrupt is active 1 R_RX_UNDER See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0 [0:0] read-only INACTIVE RX_UNDER interrupt is inactive 0 ACTIVE RX_UNDER interrupt is active 1 IC_INTR_MASK I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. 0x30 0x000008FF M_RESTART_DET This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 [12:12] read-write ENABLED RESTART_DET interrupt is masked 0 DISABLED RESTART_DET interrupt is unmasked 1 M_GEN_CALL This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 [11:11] read-write ENABLED GEN_CALL interrupt is masked 0 DISABLED GEN_CALL interrupt is unmasked 1 M_START_DET This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 [10:10] read-write ENABLED START_DET interrupt is masked 0 DISABLED START_DET interrupt is unmasked 1 M_STOP_DET This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 [9:9] read-write ENABLED STOP_DET interrupt is masked 0 DISABLED STOP_DET interrupt is unmasked 1 M_ACTIVITY This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 [8:8] read-write ENABLED ACTIVITY interrupt is masked 0 DISABLED ACTIVITY interrupt is unmasked 1 M_RX_DONE This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 [7:7] read-write ENABLED RX_DONE interrupt is masked 0 DISABLED RX_DONE interrupt is unmasked 1 M_TX_ABRT This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 [6:6] read-write ENABLED TX_ABORT interrupt is masked 0 DISABLED TX_ABORT interrupt is unmasked 1 M_RD_REQ This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 [5:5] read-write ENABLED RD_REQ interrupt is masked 0 DISABLED RD_REQ interrupt is unmasked 1 M_TX_EMPTY This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 [4:4] read-write ENABLED TX_EMPTY interrupt is masked 0 DISABLED TX_EMPTY interrupt is unmasked 1 M_TX_OVER This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 [3:3] read-write ENABLED TX_OVER interrupt is masked 0 DISABLED TX_OVER interrupt is unmasked 1 M_RX_FULL This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 [2:2] read-write ENABLED RX_FULL interrupt is masked 0 DISABLED RX_FULL interrupt is unmasked 1 M_RX_OVER This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 [1:1] read-write ENABLED RX_OVER interrupt is masked 0 DISABLED RX_OVER interrupt is unmasked 1 M_RX_UNDER This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 [0:0] read-write ENABLED RX_UNDER interrupt is masked 0 DISABLED RX_UNDER interrupt is unmasked 1 IC_RAW_INTR_STAT I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. 0x34 0x00000000 RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0 [12:12] read-only INACTIVE RESTART_DET interrupt is inactive 0 ACTIVE RESTART_DET interrupt is active 1 GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0 [11:11] read-only INACTIVE GEN_CALL interrupt is inactive 0 ACTIVE GEN_CALL interrupt is active 1 START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 [10:10] read-only INACTIVE START_DET interrupt is inactive 0 ACTIVE START_DET interrupt is active 1 STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 [9:9] read-only INACTIVE STOP_DET interrupt is inactive 0 ACTIVE STOP_DET interrupt is active 1 ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0 [8:8] read-only INACTIVE RAW_INTR_ACTIVITY interrupt is inactive 0 ACTIVE RAW_INTR_ACTIVITY interrupt is active 1 RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0 [7:7] read-only INACTIVE RX_DONE interrupt is inactive 0 ACTIVE RX_DONE interrupt is active 1 TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0 [6:6] read-only INACTIVE TX_ABRT interrupt is inactive 0 ACTIVE TX_ABRT interrupt is active 1 RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0 [5:5] read-only INACTIVE RD_REQ interrupt is inactive 0 ACTIVE RD_REQ interrupt is active 1 TX_EMPTY The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0. [4:4] read-only INACTIVE TX_EMPTY interrupt is inactive 0 ACTIVE TX_EMPTY interrupt is active 1 TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 [3:3] read-only INACTIVE TX_OVER interrupt is inactive 0 ACTIVE TX_OVER interrupt is active 1 RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0 [2:2] read-only INACTIVE RX_FULL interrupt is inactive 0 ACTIVE RX_FULL interrupt is active 1 RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0 [1:1] read-only INACTIVE RX_OVER interrupt is inactive 0 ACTIVE RX_OVER interrupt is active 1 RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 [0:0] read-only INACTIVE RX_UNDER interrupt is inactive 0 ACTIVE RX_UNDER interrupt is active 1 IC_RX_TL I2C Receive FIFO Threshold Register 0x38 0x00000000 RX_TL Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. [7:0] read-write IC_TX_TL I2C Transmit FIFO Threshold Register 0x3C 0x00000000 TX_TL Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. [7:0] read-write IC_CLR_INTR Clear Combined and Individual Interrupt Register 0x40 0x00000000 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0 [0:0] read-only IC_CLR_RX_UNDER Clear RX_UNDER Interrupt Register 0x44 0x00000000 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_RX_OVER Clear RX_OVER Interrupt Register 0x48 0x00000000 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_TX_OVER Clear TX_OVER Interrupt Register 0x4C 0x00000000 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_RD_REQ Clear RD_REQ Interrupt Register 0x50 0x00000000 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_TX_ABRT Clear TX_ABRT Interrupt Register 0x54 0x00000000 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0 [0:0] read-only IC_CLR_RX_DONE Clear RX_DONE Interrupt Register 0x58 0x00000000 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_ACTIVITY Clear ACTIVITY Interrupt Register 0x5C 0x00000000 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_STOP_DET Clear STOP_DET Interrupt Register 0x60 0x00000000 CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_START_DET Clear START_DET Interrupt Register 0x64 0x00000000 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_GEN_CALL Clear GEN_CALL Interrupt Register 0x68 0x00000000 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_ENABLE I2C Enable Register 0x6C 0x00000000 TX_CMD_BLOCK In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT [2:2] read-write NOT_BLOCKED Tx Command execution not blocked 0 BLOCKED Tx Command execution blocked 1 ABORT When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0 [1:1] read-write DISABLE ABORT operation not in progress 0 ENABLED ABORT operation in progress 1 ENABLE Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0 [0:0] read-write DISABLED I2C is disabled 0 ENABLED I2C is enabled 1 IC_STATUS I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 0x70 0x00000006 SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 [6:6] read-only IDLE Slave is idle 0 ACTIVE Slave not idle 1 MST_ACTIVITY Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0 [5:5] read-only IDLE Master is idle 0 ACTIVE Master not idle 1 RFF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 [4:4] read-only NOT_FULL Rx FIFO not full 0 FULL Rx FIFO is full 1 RFNE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 [3:3] read-only EMPTY Rx FIFO is empty 0 NOT_EMPTY Rx FIFO not empty 1 TFE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 [2:2] read-only NON_EMPTY Tx FIFO not empty 0 EMPTY Tx FIFO is empty 1 TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 [1:1] read-only FULL Tx FIFO is full 0 NOT_FULL Tx FIFO not full 1 ACTIVITY I2C Activity Status. Reset value: 0x0 [0:0] read-only INACTIVE I2C is idle 0 ACTIVE I2C is active 1 IC_TXFLR I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. 0x74 0x00000000 TXFLR Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0 [4:0] read-only IC_RXFLR I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. 0x78 0x00000000 RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0 [4:0] read-only IC_SDA_HOLD I2C SDA Hold Time Length Register The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE[0]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. 0x7C 0x00000001 IC_SDA_RX_HOLD Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD[23:16]. [23:16] read-write IC_SDA_TX_HOLD Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD[15:0]. [15:0] read-write IC_TX_ABRT_SOURCE I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. 0x80 0x00000000 TX_FLUSH_CNT This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter [31:23] read-only ABRT_USER_ABRT This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [16:16] read-only ABRT_USER_ABRT_VOID Transfer abort detected by master- scenario not present 0 ABRT_USER_ABRT_GENERATED Transfer abort detected by master 1 ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter [15:15] read-only ABRT_SLVRD_INTX_VOID Slave trying to transmit to remote master in read mode- scenario not present 0 ABRT_SLVRD_INTX_GENERATED Slave trying to transmit to remote master in read mode 1 ABRT_SLV_ARBLOST This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter [14:14] read-only ABRT_SLV_ARBLOST_VOID Slave lost arbitration to remote master- scenario not present 0 ABRT_SLV_ARBLOST_GENERATED Slave lost arbitration to remote master 1 ABRT_SLVFLUSH_TXFIFO This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter [13:13] read-only ABRT_SLVFLUSH_TXFIFO_VOID Slave flushes existing data in TX-FIFO upon getting read command- scenario not present 0 ABRT_SLVFLUSH_TXFIFO_GENERATED Slave flushes existing data in TX-FIFO upon getting read command 1 ARB_LOST This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter [12:12] read-only ABRT_LOST_VOID Master or Slave-Transmitter lost arbitration- scenario not present 0 ABRT_LOST_GENERATED Master or Slave-Transmitter lost arbitration 1 ABRT_MASTER_DIS This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [11:11] read-only ABRT_MASTER_DIS_VOID User initiating master operation when MASTER disabled- scenario not present 0 ABRT_MASTER_DIS_GENERATED User initiating master operation when MASTER disabled 1 ABRT_10B_RD_NORSTRT This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver [10:10] read-only ABRT_10B_RD_VOID Master not trying to read in 10Bit addressing mode when RESTART disabled 0 ABRT_10B_RD_GENERATED Master trying to read in 10Bit addressing mode when RESTART disabled 1 ABRT_SBYTE_NORSTRT To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master [9:9] read-only ABRT_SBYTE_NORSTRT_VOID User trying to send START byte when RESTART disabled- scenario not present 0 ABRT_SBYTE_NORSTRT_GENERATED User trying to send START byte when RESTART disabled 1 ABRT_HS_NORSTRT This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [8:8] read-only ABRT_HS_NORSTRT_VOID User trying to switch Master to HS mode when RESTART disabled- scenario not present 0 ABRT_HS_NORSTRT_GENERATED User trying to switch Master to HS mode when RESTART disabled 1 ABRT_SBYTE_ACKDET This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master [7:7] read-only ABRT_SBYTE_ACKDET_VOID ACK detected for START byte- scenario not present 0 ABRT_SBYTE_ACKDET_GENERATED ACK detected for START byte 1 ABRT_HS_ACKDET This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master [6:6] read-only ABRT_HS_ACK_VOID HS Master code ACKed in HS Mode- scenario not present 0 ABRT_HS_ACK_GENERATED HS Master code ACKed in HS Mode 1 ABRT_GCALL_READ This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [5:5] read-only ABRT_GCALL_READ_VOID GCALL is followed by read from bus-scenario not present 0 ABRT_GCALL_READ_GENERATED GCALL is followed by read from bus 1 ABRT_GCALL_NOACK This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [4:4] read-only ABRT_GCALL_NOACK_VOID GCALL not ACKed by any slave-scenario not present 0 ABRT_GCALL_NOACK_GENERATED GCALL not ACKed by any slave 1 ABRT_TXDATA_NOACK This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [3:3] read-only ABRT_TXDATA_NOACK_VOID Transmitted data non-ACKed by addressed slave-scenario not present 0 ABRT_TXDATA_NOACK_GENERATED Transmitted data not ACKed by addressed slave 1 ABRT_10ADDR2_NOACK This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [2:2] read-only INACTIVE This abort is not generated 0 ACTIVE Byte 2 of 10Bit Address not ACKed by any slave 1 ABRT_10ADDR1_NOACK This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [1:1] read-only INACTIVE This abort is not generated 0 ACTIVE Byte 1 of 10Bit Address not ACKed by any slave 1 ABRT_7B_ADDR_NOACK This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [0:0] read-only INACTIVE This abort is not generated 0 ACTIVE This abort is generated because of NOACK for 7-bit address 1 IC_SLV_DATA_NACK_ONLY Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. 0x84 0x00000000 NACK Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 [0:0] read-write DISABLED Slave receiver generates NACK normally 0 ENABLED Slave receiver generates NACK upon data reception only 1 IC_DMA_CR DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. 0x88 0x00000000 TDMAE Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 [1:1] read-write DISABLED transmit FIFO DMA channel disabled 0 ENABLED Transmit FIFO DMA channel enabled 1 RDMAE Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 [0:0] read-write DISABLED Receive FIFO DMA channel disabled 0 ENABLED Receive FIFO DMA channel enabled 1 IC_DMA_TDLR DMA Transmit Data Level Register 0x8C 0x00000000 DMATDL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0 [3:0] read-write IC_DMA_RDLR I2C Receive Data Level Register 0x90 0x00000000 DMARDL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0 [3:0] read-write IC_SDA_SETUP I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE[0] = 0. Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. 0x94 0x00000064 SDA_SETUP SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. [7:0] read-write IC_ACK_GENERAL_CALL I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode. 0x98 0x00000001 ACK_GEN_CALL ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). [0:0] read-write DISABLED Generate NACK for a General Call 0 ENABLED Generate ACK for a General Call 1 IC_ENABLE_STATUS I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. 0x9C 0x00000000 SLV_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 [2:2] read-only INACTIVE Slave RX Data is not lost 0 ACTIVE Slave RX Data is lost 1 SLV_DISABLED_WHILE_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 [1:1] read-only INACTIVE Slave is disabled when it is idle 0 ACTIVE Slave is disabled when it is active 1 IC_EN ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0 [0:0] read-only DISABLED I2C disabled 0 ENABLED I2C enabled 1 IC_FS_SPKLEN I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. 0xA0 0x00000007 IC_FS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. [7:0] read-write IC_CLR_RESTART_DET Clear RESTART_DET Interrupt Register 0xA8 0x00000000 CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_COMP_PARAM_1 Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters 0xF4 0x00000000 TX_BUFFER_DEPTH TX Buffer Depth = 16 [23:16] read-only RX_BUFFER_DEPTH RX Buffer Depth = 16 [15:8] read-only ADD_ENCODED_PARAMS Encoded parameters not visible [7:7] read-only HAS_DMA DMA handshaking signals are enabled [6:6] read-only INTR_IO COMBINED Interrupt outputs [5:5] read-only HC_COUNT_VALUES Programmable count values for each mode. [4:4] read-only MAX_SPEED_MODE MAX SPEED MODE = FAST MODE [3:2] read-only APB_DATA_WIDTH APB data bus width is 32 bits [1:0] read-only IC_COMP_VERSION I2C Component Version Register 0xF8 0x3230312A IC_COMP_VERSION [31:0] read-only IC_COMP_TYPE I2C Component Type Register 0xFC 0x44570140 IC_COMP_TYPE Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. [31:0] read-only I2C1 0x40098000 I2C1_IRQ 37 SPI0 0x40080000 0x0 0x1000 registers SPI0_IRQ 31 SSPCR0 Control register 0, SSPCR0 on page 3-4 0x0 0x00000000 SCR Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. [15:8] read-write SPH SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. [7:7] read-write SPO SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. [6:6] read-write FRF Frame format. [5:4] read-write FRF Motorola Motorola SPI frame format 0 Texas_Instruments Texas Instruments synchronous serial frame format 1 National_Semiconductor_Microwire National Semiconductor Microwire frame format 2 DSS Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. [3:0] read-write SSPCR1 Control register 1, SSPCR1 on page 3-5 0x4 0x00000000 SOD Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. [3:3] read-write MS Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. [2:2] read-write SSE Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. [1:1] read-write LBM Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. [0:0] read-write SSPDR Data register, SSPDR on page 3-6 0x8 0x00000000 DATA Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write modify SSPSR Status register, SSPSR on page 3-7 0xC 0x00000003 BSY PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only RFF Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. [3:3] read-only RNE Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. [2:2] read-only TNF Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. [1:1] read-only TFE Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. [0:0] read-only SSPCPSR Clock prescale register, SSPCPSR on page 3-8 0x10 0x00000000 CPSDVSR Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write SSPIMSC Interrupt mask set or clear register, SSPIMSC on page 3-9 0x14 0x00000000 TXIM Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. [3:3] read-write RXIM Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. [2:2] read-write RTIM Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. [1:1] read-write RORIM Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. [0:0] read-write SSPRIS Raw interrupt status register, SSPRIS on page 3-10 0x18 0x00000008 TXRIS Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only RXRIS Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only RTRIS Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only RORRIS Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only SSPMIS Masked interrupt status register, SSPMIS on page 3-11 0x1C 0x00000000 TXMIS Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only RXMIS Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only RTMIS Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only RORMIS Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only SSPICR Interrupt clear register, SSPICR on page 3-11 0x20 0x00000000 RTIC Clears the SSPRTINTR interrupt [1:1] read-write oneToClear RORIC Clears the SSPRORINTR interrupt [0:0] read-write oneToClear SSPDMACR DMA control register, SSPDMACR on page 3-12 0x24 0x00000000 TXDMAE Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write RXDMAE Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write SSPPERIPHID0 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0xFE0 0x00000022 PARTNUMBER0 These bits read back as 0x22 [7:0] read-only SSPPERIPHID1 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0xFE4 0x00000010 DESIGNER0 These bits read back as 0x1 [7:4] read-only PARTNUMBER1 These bits read back as 0x0 [3:0] read-only SSPPERIPHID2 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0xFE8 0x00000034 REVISION These bits return the peripheral revision [7:4] read-only DESIGNER1 These bits read back as 0x4 [3:0] read-only SSPPERIPHID3 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0xFEC 0x00000000 CONFIGURATION These bits read back as 0x00 [7:0] read-only SSPPCELLID0 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0xFF0 0x0000000D SSPPCELLID0 These bits read back as 0x0D [7:0] read-only SSPPCELLID1 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0xFF4 0x000000F0 SSPPCELLID1 These bits read back as 0xF0 [7:0] read-only SSPPCELLID2 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0xFF8 0x00000005 SSPPCELLID2 These bits read back as 0x05 [7:0] read-only SSPPCELLID3 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0xFFC 0x000000B1 SSPPCELLID3 These bits read back as 0xB1 [7:0] read-only SPI1 0x40088000 SPI1_IRQ 32 PIO0 Programmable IO block 0x50200000 0x0 0x188 registers PIO0_IRQ_0 15 PIO0_IRQ_1 16 CTRL PIO control register 0x0 0x00000000 NEXTPREV_CLKDIV_RESTART Write 1 to restart the clock dividers of state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to writing 1 to the corresponding CLKDIV_RESTART bits in those PIOs' CTRL registers. [26:26] write-only NEXTPREV_SM_DISABLE Write 1 to disable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to clearing the corresponding SM_ENABLE bits in those PIOs' CTRL registers. [25:25] write-only NEXTPREV_SM_ENABLE Write 1 to enable state machines in neighbouring PIO blocks, as specified by NEXT_PIO_MASK and PREV_PIO_MASK in the same write. This is equivalent to setting the corresponding SM_ENABLE bits in those PIOs' CTRL registers. If both OTHERS_SM_ENABLE and OTHERS_SM_DISABLE are set, the disable takes precedence. [24:24] write-only NEXT_PIO_MASK A mask of state machines in the neighbouring higher-numbered PIO block in the system (or PIO block 0 if this is the highest-numbered PIO block) to which to apply the operations specified by NEXTPREV_CLKDIV_RESTART, NEXTPREV_SM_ENABLE, and NEXTPREV_SM_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Note that in a system with two PIOs, NEXT_PIO_MASK and PREV_PIO_MASK actually indicate the same PIO block. In this case the effects are applied cumulatively (as though the masks were OR'd together). Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. [23:20] write-only PREV_PIO_MASK A mask of state machines in the neighbouring lower-numbered PIO block in the system (or the highest-numbered PIO block if this is PIO block 0) to which to apply the operations specified by OP_CLKDIV_RESTART, OP_ENABLE, OP_DISABLE in the same write. This allows state machines in a neighbouring PIO block to be started/stopped/clock-synced exactly simultaneously with a write to this PIO block's CTRL register. Neighbouring PIO blocks are disconnected (status signals tied to 0 and control signals ignored) if one block is accessible to NonSecure code, and one is not. [19:16] write-only CLKDIV_RESTART Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. [11:8] write-only SM_RESTART Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The contents of the output shift register and the X/Y scratch registers are not affected. [7:4] write-only SM_ENABLE Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. [3:0] read-write FSTAT FIFO status register 0x4 0x0F000F00 TXEMPTY State machine TX FIFO is empty [27:24] read-only TXFULL State machine TX FIFO is full [19:16] read-only RXEMPTY State machine RX FIFO is empty [11:8] read-only RXFULL State machine RX FIFO is full [3:0] read-only FDEBUG FIFO debug register 0x8 0x00000000 TXSTALL State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. [27:24] read-write oneToClear TXOVER TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. [19:16] read-write oneToClear RXUNDER RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. [11:8] read-write oneToClear RXSTALL State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. [3:0] read-write oneToClear FLEVEL FIFO levels 0xC 0x00000000 RX3 [31:28] read-only TX3 [27:24] read-only RX2 [23:20] read-only TX2 [19:16] read-only RX1 [15:12] read-only TX1 [11:8] read-only RX0 [7:4] read-only TX0 [3:0] read-only 4 0x4 0-3 TXF%s Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. 0x10 0x00000000 TXF0 [31:0] write-only 4 0x4 0-3 RXF%s Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. 0x20 0x00000000 RXF0 [31:0] read-only modify IRQ State machine IRQ flags register. Write 1 to clear. There are eight state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the eight flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. Any combination of the eight flags can also routed out to either of the two system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. 0x30 0x00000000 IRQ [7:0] read-write oneToClear IRQ_FORCE Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. 0x34 0x00000000 IRQ_FORCE [7:0] write-only INPUT_SYNC_BYPASS There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. 0x38 0x00000000 INPUT_SYNC_BYPASS [31:0] read-write DBG_PADOUT Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. 0x3C 0x00000000 DBG_PADOUT [31:0] read-only DBG_PADOE Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. 0x40 0x00000000 DBG_PADOE [31:0] read-only DBG_CFGINFO The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. 0x44 0x10000000 VERSION Version of the core PIO hardware. [31:28] read-only v0 Version 0 (RP2040) 0 v1 Version 1 (RP2350) 1 IMEM_SIZE The size of the instruction memory, measured in units of one instruction [21:16] read-only SM_COUNT The number of state machines this PIO instance is equipped with. [11:8] read-only FIFO_DEPTH The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth. [5:0] read-only 32 0x4 0-31 INSTR_MEM%s Write-only access to instruction memory location %s 0x48 0x00000000 INSTR_MEM0 [15:0] write-only 4 0x18 0-3 SM%s Cluster SM%s, containing SM*_CLKDIV, SM*_EXECCTRL, SM*_SHIFTCTRL, SM*_ADDR, SM*_INSTR, SM*_PINCTRL 0xC8 SM_CLKDIV Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 0x0 0x00010000 INT Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. [31:16] read-write FRAC Fractional part of clock divisor [15:8] read-write SM_EXECCTRL Execution/behavioural settings for state machine 0 0x4 0x0001F000 EXEC_STALLED If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. [31:31] read-only SIDE_EN If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. [30:30] read-write SIDE_PINDIR If 1, side-set data is asserted to pin directions, instead of pin values [29:29] read-write JMP_PIN The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. [28:24] read-write OUT_EN_SEL Which data bit to use for inline OUT enable [23:19] read-write INLINE_OUT_EN If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) [18:18] read-write OUT_STICKY Continuously assert the most recent OUT/SET to the pins [17:17] read-write WRAP_TOP After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. [16:12] read-write WRAP_BOTTOM After reaching wrap_top, execution is wrapped to this address. [11:7] read-write STATUS_SEL Comparison used for the MOV x, STATUS instruction. [6:5] read-write TXLEVEL All-ones if TX FIFO level < N, otherwise all-zeroes 0 RXLEVEL All-ones if RX FIFO level < N, otherwise all-zeroes 1 IRQ All-ones if the indexed IRQ flag is raised, otherwise all-zeroes 2 STATUS_N Comparison level or IRQ index for the MOV x, STATUS instruction. If STATUS_SEL is TXLEVEL or RXLEVEL, then values of STATUS_N greater than the current FIFO depth are reserved, and have undefined behaviour. [4:0] read-write IRQ Index 0-7 of an IRQ flag in this PIO block 0 IRQ_PREVPIO Index 0-7 of an IRQ flag in the next lower-numbered PIO block 8 IRQ_NEXTPIO Index 0-7 of an IRQ flag in the next higher-numbered PIO block 16 SM_SHIFTCTRL Control behaviour of the input/output shift registers for state machine 0 0x8 0x000C0000 FJOIN_RX When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [31:31] read-write FJOIN_TX When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [30:30] read-write PULL_THRESH Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. [29:25] read-write PUSH_THRESH Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. [24:20] read-write OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. [19:19] read-write IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). 0 = to left. [18:18] read-write AUTOPULL Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. [17:17] read-write AUTOPUSH Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. [16:16] read-write FJOIN_RX_PUT If 1, disable this state machine's RX FIFO, make its storage available for random write access by the state machine (using the `put` instruction) and, unless FJOIN_RX_GET is also set, random read access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. [15:15] read-write FJOIN_RX_GET If 1, disable this state machine's RX FIFO, make its storage available for random read access by the state machine (using the `get` instruction) and, unless FJOIN_RX_PUT is also set, random write access by the processor (through the RXFx_PUTGETy registers). If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO's registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. [14:14] read-write IN_COUNT Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. [4:0] read-write SM_ADDR Current instruction address of state machine 0 0xC 0x00000000 SM0_ADDR [4:0] read-only SM_INSTR Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. 0x10 0x00000000 SM0_INSTR [15:0] read-write SM_PINCTRL State machine pin control 0x14 0x14000000 SIDESET_COUNT The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). [31:29] read-write SET_COUNT The number of pins asserted by a SET. In the range 0 to 5 inclusive. [28:26] read-write OUT_COUNT The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. [25:20] read-write IN_BASE The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. [19:15] read-write SIDESET_BASE The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. [14:10] read-write SET_BASE The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. [9:5] read-write OUT_BASE The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. [4:0] read-write 4 0x4 0-3 RXF0_PUTGET%s Direct read/write access to entry %s of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. 0x128 0x00000000 RXF0_PUTGET0 [31:0] read-write 4 0x4 0-3 RXF1_PUTGET%s Direct read/write access to entry %s of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. 0x138 0x00000000 RXF1_PUTGET0 [31:0] read-write 4 0x4 0-3 RXF2_PUTGET%s Direct read/write access to entry %s of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. 0x148 0x00000000 RXF2_PUTGET0 [31:0] read-write 4 0x4 0-3 RXF3_PUTGET%s Direct read/write access to entry %s of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set. 0x158 0x00000000 RXF3_PUTGET0 [31:0] read-write GPIOBASE Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32 GPIOs from PIO. Only the values 0 and 16 are supported (only bit 4 is writable). 0x168 0x00000000 GPIOBASE [4:4] read-write INTR Raw Interrupts 0x16C 0x00000000 SM7 [15:15] read-only SM6 [14:14] read-only SM5 [13:13] read-only SM4 [12:12] read-only SM3 [11:11] read-only SM2 [10:10] read-only SM1 [9:9] read-only SM0 [8:8] read-only SM3_TXNFULL [7:7] read-only SM2_TXNFULL [6:6] read-only SM1_TXNFULL [5:5] read-only SM0_TXNFULL [4:4] read-only SM3_RXNEMPTY [3:3] read-only SM2_RXNEMPTY [2:2] read-only SM1_RXNEMPTY [1:1] read-only SM0_RXNEMPTY [0:0] read-only 2 0xC 0-1 SM_IRQ%s Cluster SM_IRQ%s, containing IRQ*_INTE, IRQ*_INTF, IRQ*_INTS 0x170 IRQ_INTE Interrupt Enable for irq0 0x0 0x00000000 SM7 [15:15] read-write SM6 [14:14] read-write SM5 [13:13] read-write SM4 [12:12] read-write SM3 [11:11] read-write SM2 [10:10] read-write SM1 [9:9] read-write SM0 [8:8] read-write SM3_TXNFULL [7:7] read-write SM2_TXNFULL [6:6] read-write SM1_TXNFULL [5:5] read-write SM0_TXNFULL [4:4] read-write SM3_RXNEMPTY [3:3] read-write SM2_RXNEMPTY [2:2] read-write SM1_RXNEMPTY [1:1] read-write SM0_RXNEMPTY [0:0] read-write IRQ_INTF Interrupt Force for irq0 0x4 0x00000000 SM7 [15:15] read-write SM6 [14:14] read-write SM5 [13:13] read-write SM4 [12:12] read-write SM3 [11:11] read-write SM2 [10:10] read-write SM1 [9:9] read-write SM0 [8:8] read-write SM3_TXNFULL [7:7] read-write SM2_TXNFULL [6:6] read-write SM1_TXNFULL [5:5] read-write SM0_TXNFULL [4:4] read-write SM3_RXNEMPTY [3:3] read-write SM2_RXNEMPTY [2:2] read-write SM1_RXNEMPTY [1:1] read-write SM0_RXNEMPTY [0:0] read-write IRQ_INTS Interrupt status after masking & forcing for irq0 0x8 0x00000000 SM7 [15:15] read-only SM6 [14:14] read-only SM5 [13:13] read-only SM4 [12:12] read-only SM3 [11:11] read-only SM2 [10:10] read-only SM1 [9:9] read-only SM0 [8:8] read-only SM3_TXNFULL [7:7] read-only SM2_TXNFULL [6:6] read-only SM1_TXNFULL [5:5] read-only SM0_TXNFULL [4:4] read-only SM3_RXNEMPTY [3:3] read-only SM2_RXNEMPTY [2:2] read-only SM1_RXNEMPTY [1:1] read-only SM0_RXNEMPTY [0:0] read-only PIO1 0x50300000 PIO1_IRQ_0 17 PIO1_IRQ_1 18 PIO2 0x50400000 PIO2_IRQ_0 19 PIO2_IRQ_1 20 BUSCTRL Register block for busfabric control signals and performance counters 0x40068000 0x0 0x2C registers BUS_PRIORITY Set the priority of each master for bus arbitration. 0x0 0x00000000 DMA_W 0 - low priority, 1 - high priority [12:12] read-write DMA_R 0 - low priority, 1 - high priority [8:8] read-write PROC1 0 - low priority, 1 - high priority [4:4] read-write PROC0 0 - low priority, 1 - high priority [0:0] read-write BUS_PRIORITY_ACK Bus priority acknowledge 0x4 0x00000000 BUS_PRIORITY_ACK Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately. [0:0] read-only PERFCTR_EN Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code. The performance counters are initially disabled, to save energy. 0x8 0x00000000 PERFCTR_EN [0:0] read-write PERFCTR0 Bus fabric performance counter 0 0xC 0x00000000 PERFCTR0 Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL0 [23:0] read-write oneToClear PERFSEL0 Bus fabric performance event select for PERFCTR0 0x10 0x0000001F PERFSEL0 Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. [6:0] read-write siob_proc1_stall_upstream 0 siob_proc1_stall_downstream 1 siob_proc1_access_contested 2 siob_proc1_access 3 siob_proc0_stall_upstream 4 siob_proc0_stall_downstream 5 siob_proc0_access_contested 6 siob_proc0_access 7 apb_stall_upstream 8 apb_stall_downstream 9 apb_access_contested 10 apb_access 11 fastperi_stall_upstream 12 fastperi_stall_downstream 13 fastperi_access_contested 14 fastperi_access 15 sram9_stall_upstream 16 sram9_stall_downstream 17 sram9_access_contested 18 sram9_access 19 sram8_stall_upstream 20 sram8_stall_downstream 21 sram8_access_contested 22 sram8_access 23 sram7_stall_upstream 24 sram7_stall_downstream 25 sram7_access_contested 26 sram7_access 27 sram6_stall_upstream 28 sram6_stall_downstream 29 sram6_access_contested 30 sram6_access 31 sram5_stall_upstream 32 sram5_stall_downstream 33 sram5_access_contested 34 sram5_access 35 sram4_stall_upstream 36 sram4_stall_downstream 37 sram4_access_contested 38 sram4_access 39 sram3_stall_upstream 40 sram3_stall_downstream 41 sram3_access_contested 42 sram3_access 43 sram2_stall_upstream 44 sram2_stall_downstream 45 sram2_access_contested 46 sram2_access 47 sram1_stall_upstream 48 sram1_stall_downstream 49 sram1_access_contested 50 sram1_access 51 sram0_stall_upstream 52 sram0_stall_downstream 53 sram0_access_contested 54 sram0_access 55 xip_main1_stall_upstream 56 xip_main1_stall_downstream 57 xip_main1_access_contested 58 xip_main1_access 59 xip_main0_stall_upstream 60 xip_main0_stall_downstream 61 xip_main0_access_contested 62 xip_main0_access 63 rom_stall_upstream 64 rom_stall_downstream 65 rom_access_contested 66 rom_access 67 PERFCTR1 Bus fabric performance counter 1 0x14 0x00000000 PERFCTR1 Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL1 [23:0] read-write oneToClear PERFSEL1 Bus fabric performance event select for PERFCTR1 0x18 0x0000001F PERFSEL1 Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. [6:0] read-write siob_proc1_stall_upstream 0 siob_proc1_stall_downstream 1 siob_proc1_access_contested 2 siob_proc1_access 3 siob_proc0_stall_upstream 4 siob_proc0_stall_downstream 5 siob_proc0_access_contested 6 siob_proc0_access 7 apb_stall_upstream 8 apb_stall_downstream 9 apb_access_contested 10 apb_access 11 fastperi_stall_upstream 12 fastperi_stall_downstream 13 fastperi_access_contested 14 fastperi_access 15 sram9_stall_upstream 16 sram9_stall_downstream 17 sram9_access_contested 18 sram9_access 19 sram8_stall_upstream 20 sram8_stall_downstream 21 sram8_access_contested 22 sram8_access 23 sram7_stall_upstream 24 sram7_stall_downstream 25 sram7_access_contested 26 sram7_access 27 sram6_stall_upstream 28 sram6_stall_downstream 29 sram6_access_contested 30 sram6_access 31 sram5_stall_upstream 32 sram5_stall_downstream 33 sram5_access_contested 34 sram5_access 35 sram4_stall_upstream 36 sram4_stall_downstream 37 sram4_access_contested 38 sram4_access 39 sram3_stall_upstream 40 sram3_stall_downstream 41 sram3_access_contested 42 sram3_access 43 sram2_stall_upstream 44 sram2_stall_downstream 45 sram2_access_contested 46 sram2_access 47 sram1_stall_upstream 48 sram1_stall_downstream 49 sram1_access_contested 50 sram1_access 51 sram0_stall_upstream 52 sram0_stall_downstream 53 sram0_access_contested 54 sram0_access 55 xip_main1_stall_upstream 56 xip_main1_stall_downstream 57 xip_main1_access_contested 58 xip_main1_access 59 xip_main0_stall_upstream 60 xip_main0_stall_downstream 61 xip_main0_access_contested 62 xip_main0_access 63 rom_stall_upstream 64 rom_stall_downstream 65 rom_access_contested 66 rom_access 67 PERFCTR2 Bus fabric performance counter 2 0x1C 0x00000000 PERFCTR2 Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL2 [23:0] read-write oneToClear PERFSEL2 Bus fabric performance event select for PERFCTR2 0x20 0x0000001F PERFSEL2 Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. [6:0] read-write siob_proc1_stall_upstream 0 siob_proc1_stall_downstream 1 siob_proc1_access_contested 2 siob_proc1_access 3 siob_proc0_stall_upstream 4 siob_proc0_stall_downstream 5 siob_proc0_access_contested 6 siob_proc0_access 7 apb_stall_upstream 8 apb_stall_downstream 9 apb_access_contested 10 apb_access 11 fastperi_stall_upstream 12 fastperi_stall_downstream 13 fastperi_access_contested 14 fastperi_access 15 sram9_stall_upstream 16 sram9_stall_downstream 17 sram9_access_contested 18 sram9_access 19 sram8_stall_upstream 20 sram8_stall_downstream 21 sram8_access_contested 22 sram8_access 23 sram7_stall_upstream 24 sram7_stall_downstream 25 sram7_access_contested 26 sram7_access 27 sram6_stall_upstream 28 sram6_stall_downstream 29 sram6_access_contested 30 sram6_access 31 sram5_stall_upstream 32 sram5_stall_downstream 33 sram5_access_contested 34 sram5_access 35 sram4_stall_upstream 36 sram4_stall_downstream 37 sram4_access_contested 38 sram4_access 39 sram3_stall_upstream 40 sram3_stall_downstream 41 sram3_access_contested 42 sram3_access 43 sram2_stall_upstream 44 sram2_stall_downstream 45 sram2_access_contested 46 sram2_access 47 sram1_stall_upstream 48 sram1_stall_downstream 49 sram1_access_contested 50 sram1_access 51 sram0_stall_upstream 52 sram0_stall_downstream 53 sram0_access_contested 54 sram0_access 55 xip_main1_stall_upstream 56 xip_main1_stall_downstream 57 xip_main1_access_contested 58 xip_main1_access 59 xip_main0_stall_upstream 60 xip_main0_stall_downstream 61 xip_main0_access_contested 62 xip_main0_access 63 rom_stall_upstream 64 rom_stall_downstream 65 rom_access_contested 66 rom_access 67 PERFCTR3 Bus fabric performance counter 3 0x24 0x00000000 PERFCTR3 Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters, if PERFCTR_EN is set. Write any value to clear. Select an event to count using PERFSEL3 [23:0] read-write oneToClear PERFSEL3 Bus fabric performance event select for PERFCTR3 0x28 0x0000001F PERFSEL3 Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place; ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters; STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus; STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters. [6:0] read-write siob_proc1_stall_upstream 0 siob_proc1_stall_downstream 1 siob_proc1_access_contested 2 siob_proc1_access 3 siob_proc0_stall_upstream 4 siob_proc0_stall_downstream 5 siob_proc0_access_contested 6 siob_proc0_access 7 apb_stall_upstream 8 apb_stall_downstream 9 apb_access_contested 10 apb_access 11 fastperi_stall_upstream 12 fastperi_stall_downstream 13 fastperi_access_contested 14 fastperi_access 15 sram9_stall_upstream 16 sram9_stall_downstream 17 sram9_access_contested 18 sram9_access 19 sram8_stall_upstream 20 sram8_stall_downstream 21 sram8_access_contested 22 sram8_access 23 sram7_stall_upstream 24 sram7_stall_downstream 25 sram7_access_contested 26 sram7_access 27 sram6_stall_upstream 28 sram6_stall_downstream 29 sram6_access_contested 30 sram6_access 31 sram5_stall_upstream 32 sram5_stall_downstream 33 sram5_access_contested 34 sram5_access 35 sram4_stall_upstream 36 sram4_stall_downstream 37 sram4_access_contested 38 sram4_access 39 sram3_stall_upstream 40 sram3_stall_downstream 41 sram3_access_contested 42 sram3_access 43 sram2_stall_upstream 44 sram2_stall_downstream 45 sram2_access_contested 46 sram2_access 47 sram1_stall_upstream 48 sram1_stall_downstream 49 sram1_access_contested 50 sram1_access 51 sram0_stall_upstream 52 sram0_stall_downstream 53 sram0_access_contested 54 sram0_access 55 xip_main1_stall_upstream 56 xip_main1_stall_downstream 57 xip_main1_access_contested 58 xip_main1_access 59 xip_main0_stall_upstream 60 xip_main0_stall_downstream 61 xip_main0_access_contested 62 xip_main0_access 63 rom_stall_upstream 64 rom_stall_downstream 65 rom_access_contested 66 rom_access 67 SIO Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access. 0xD0000000 0x0 0x1E8 registers SIO_IRQ_FIFO 25 SIO_IRQ_BELL 26 SIO_IRQ_FIFO_NS 27 SIO_IRQ_BELL_NS 28 SIO_IRQ_MTIMECMP 29 CPUID Processor core identifier 0x0 0x00000000 CPUID Value is 0 when read from processor core 0, and 1 when read from processor core 1. [31:0] read-only GPIO_IN Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. 0x4 0x00000000 GPIO_IN [31:0] read-only GPIO_HI_IN Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. 0x8 0x00000000 QSPI_SD Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins [31:28] read-only QSPI_CSN Input value on QSPI CSn pin [27:27] read-only QSPI_SCK Input value on QSPI SCK pin [26:26] read-only USB_DM Input value on USB D- pin [25:25] read-only USB_DP Input value on USB D+ pin [24:24] read-only GPIO Input value on GPIO32...47 [15:0] read-only GPIO_OUT GPIO0...31 output value 0x10 0x00000000 GPIO_OUT Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. [31:0] read-write GPIO_HI_OUT Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. 0x14 0x00000000 QSPI_SD Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins [31:28] read-write QSPI_CSN Output value for QSPI CSn pin [27:27] read-write QSPI_SCK Output value for QSPI SCK pin [26:26] read-write USB_DM Output value for USB D- pin [25:25] read-write USB_DP Output value for USB D+ pin [24:24] read-write GPIO Output value for GPIO32...47 [15:0] read-write GPIO_OUT_SET GPIO0...31 output value set 0x18 0x00000000 GPIO_OUT_SET Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` [31:0] write-only GPIO_HI_OUT_SET Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` 0x1C 0x00000000 QSPI_SD [31:28] write-only QSPI_CSN [27:27] write-only QSPI_SCK [26:26] write-only USB_DM [25:25] write-only USB_DP [24:24] write-only GPIO [15:0] write-only GPIO_OUT_CLR GPIO0...31 output value clear 0x20 0x00000000 GPIO_OUT_CLR Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` [31:0] write-only GPIO_HI_OUT_CLR Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` 0x24 0x00000000 QSPI_SD [31:28] write-only QSPI_CSN [27:27] write-only QSPI_SCK [26:26] write-only USB_DM [25:25] write-only USB_DP [24:24] write-only GPIO [15:0] write-only GPIO_OUT_XOR GPIO0...31 output value XOR 0x28 0x00000000 GPIO_OUT_XOR Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` [31:0] write-only GPIO_HI_OUT_XOR Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` 0x2C 0x00000000 QSPI_SD [31:28] write-only QSPI_CSN [27:27] write-only QSPI_SCK [26:26] write-only USB_DM [25:25] write-only USB_DP [24:24] write-only GPIO [15:0] write-only GPIO_OE GPIO0...31 output enable 0x30 0x00000000 GPIO_OE Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. [31:0] read-write GPIO_HI_OE Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register. 0x34 0x00000000 QSPI_SD Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins [31:28] read-write QSPI_CSN Output enable value for QSPI CSn pin [27:27] read-write QSPI_SCK Output enable value for QSPI SCK pin [26:26] read-write USB_DM Output enable value for USB D- pin [25:25] read-write USB_DP Output enable value for USB D+ pin [24:24] read-write GPIO Output enable value for GPIO32...47 [15:0] read-write GPIO_OE_SET GPIO0...31 output enable set 0x38 0x00000000 GPIO_OE_SET Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` [31:0] write-only GPIO_HI_OE_SET Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` 0x3C 0x00000000 QSPI_SD [31:28] write-only QSPI_CSN [27:27] write-only QSPI_SCK [26:26] write-only USB_DM [25:25] write-only USB_DP [24:24] write-only GPIO [15:0] write-only GPIO_OE_CLR GPIO0...31 output enable clear 0x40 0x00000000 GPIO_OE_CLR Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` [31:0] write-only GPIO_HI_OE_CLR Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` 0x44 0x00000000 QSPI_SD [31:28] write-only QSPI_CSN [27:27] write-only QSPI_SCK [26:26] write-only USB_DM [25:25] write-only USB_DP [24:24] write-only GPIO [15:0] write-only GPIO_OE_XOR GPIO0...31 output enable XOR 0x48 0x00000000 GPIO_OE_XOR Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` [31:0] write-only GPIO_HI_OE_XOR Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` 0x4C 0x00000000 QSPI_SD [31:28] write-only QSPI_CSN [27:27] write-only QSPI_SCK [26:26] write-only USB_DM [25:25] write-only USB_DP [24:24] write-only GPIO [15:0] write-only FIFO_ST Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. 0x50 0x00000002 ROE Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. [3:3] read-write oneToClear WOF Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. [2:2] read-write oneToClear RDY Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) [1:1] read-only VLD Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) [0:0] read-only FIFO_WR Write access to this core's TX FIFO 0x54 0x00000000 FIFO_WR [31:0] write-only FIFO_RD Read access to this core's RX FIFO 0x58 0x00000000 FIFO_RD [31:0] read-only modify SPINLOCK_ST Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. 0x5C 0x00000000 SPINLOCK_ST [31:0] read-only INTERP0_ACCUM0 Read/write access to accumulator 0 0x80 0x00000000 INTERP0_ACCUM0 [31:0] read-write INTERP0_ACCUM1 Read/write access to accumulator 1 0x84 0x00000000 INTERP0_ACCUM1 [31:0] read-write INTERP0_BASE0 Read/write access to BASE0 register. 0x88 0x00000000 INTERP0_BASE0 [31:0] read-write INTERP0_BASE1 Read/write access to BASE1 register. 0x8C 0x00000000 INTERP0_BASE1 [31:0] read-write INTERP0_BASE2 Read/write access to BASE2 register. 0x90 0x00000000 INTERP0_BASE2 [31:0] read-write INTERP0_POP_LANE0 Read LANE0 result, and simultaneously write lane results to both accumulators (POP). 0x94 0x00000000 INTERP0_POP_LANE0 [31:0] read-only INTERP0_POP_LANE1 Read LANE1 result, and simultaneously write lane results to both accumulators (POP). 0x98 0x00000000 INTERP0_POP_LANE1 [31:0] read-only INTERP0_POP_FULL Read FULL result, and simultaneously write lane results to both accumulators (POP). 0x9C 0x00000000 INTERP0_POP_FULL [31:0] read-only INTERP0_PEEK_LANE0 Read LANE0 result, without altering any internal state (PEEK). 0xA0 0x00000000 INTERP0_PEEK_LANE0 [31:0] read-only INTERP0_PEEK_LANE1 Read LANE1 result, without altering any internal state (PEEK). 0xA4 0x00000000 INTERP0_PEEK_LANE1 [31:0] read-only INTERP0_PEEK_FULL Read FULL result, without altering any internal state (PEEK). 0xA8 0x00000000 INTERP0_PEEK_FULL [31:0] read-only INTERP0_CTRL_LANE0 Control register for lane 0 0xAC 0x00000000 OVERF Set if either OVERF0 or OVERF1 is set. [25:25] read-only OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set. [24:24] read-only OVERF0 Indicates if any masked-off MSBs in ACCUM0 are set. [23:23] read-only BLEND Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. [21:21] read-write FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. [4:0] read-write INTERP0_CTRL_LANE1 Control register for lane 1 0xB0 0x00000000 FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. [4:0] read-write INTERP0_ACCUM0_ADD Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). 0xB4 0x00000000 INTERP0_ACCUM0_ADD [23:0] read-write INTERP0_ACCUM1_ADD Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). 0xB8 0x00000000 INTERP0_ACCUM1_ADD [23:0] read-write INTERP0_BASE_1AND0 On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. 0xBC 0x00000000 INTERP0_BASE_1AND0 [31:0] write-only INTERP1_ACCUM0 Read/write access to accumulator 0 0xC0 0x00000000 INTERP1_ACCUM0 [31:0] read-write INTERP1_ACCUM1 Read/write access to accumulator 1 0xC4 0x00000000 INTERP1_ACCUM1 [31:0] read-write INTERP1_BASE0 Read/write access to BASE0 register. 0xC8 0x00000000 INTERP1_BASE0 [31:0] read-write INTERP1_BASE1 Read/write access to BASE1 register. 0xCC 0x00000000 INTERP1_BASE1 [31:0] read-write INTERP1_BASE2 Read/write access to BASE2 register. 0xD0 0x00000000 INTERP1_BASE2 [31:0] read-write INTERP1_POP_LANE0 Read LANE0 result, and simultaneously write lane results to both accumulators (POP). 0xD4 0x00000000 INTERP1_POP_LANE0 [31:0] read-only INTERP1_POP_LANE1 Read LANE1 result, and simultaneously write lane results to both accumulators (POP). 0xD8 0x00000000 INTERP1_POP_LANE1 [31:0] read-only INTERP1_POP_FULL Read FULL result, and simultaneously write lane results to both accumulators (POP). 0xDC 0x00000000 INTERP1_POP_FULL [31:0] read-only INTERP1_PEEK_LANE0 Read LANE0 result, without altering any internal state (PEEK). 0xE0 0x00000000 INTERP1_PEEK_LANE0 [31:0] read-only INTERP1_PEEK_LANE1 Read LANE1 result, without altering any internal state (PEEK). 0xE4 0x00000000 INTERP1_PEEK_LANE1 [31:0] read-only INTERP1_PEEK_FULL Read FULL result, without altering any internal state (PEEK). 0xE8 0x00000000 INTERP1_PEEK_FULL [31:0] read-only INTERP1_CTRL_LANE0 Control register for lane 0 0xEC 0x00000000 OVERF Set if either OVERF0 or OVERF1 is set. [25:25] read-only OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set. [24:24] read-only OVERF0 Indicates if any masked-off MSBs in ACCUM0 are set. [23:23] read-only CLAMP Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED [22:22] read-write FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. [4:0] read-write INTERP1_CTRL_LANE1 Control register for lane 1 0xF0 0x00000000 FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised. [4:0] read-write INTERP1_ACCUM0_ADD Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). 0xF4 0x00000000 INTERP1_ACCUM0_ADD [23:0] read-write INTERP1_ACCUM1_ADD Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). 0xF8 0x00000000 INTERP1_ACCUM1_ADD [23:0] read-write INTERP1_BASE_1AND0 On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. 0xFC 0x00000000 INTERP1_BASE_1AND0 [31:0] write-only 32 0x4 0-31 SPINLOCK%s Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x100 read-write 0x00000000 SPINLOCK0 [31:0] read-write modify DOORBELL_OUT_SET Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status. 0x180 0x00000000 DOORBELL_OUT_SET [7:0] read-write DOORBELL_OUT_CLR Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status. 0x184 0x00000000 DOORBELL_OUT_CLR [7:0] read-write oneToClear DOORBELL_IN_SET Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core. 0x188 0x00000000 DOORBELL_IN_SET [7:0] read-write DOORBELL_IN_CLR Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core. 0x18C 0x00000000 DOORBELL_IN_CLR [7:0] read-write oneToClear PERI_NONSEC Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register. 0x190 0x00000000 TMDS IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO. [5:5] read-write INTERP1 If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO. [1:1] read-write INTERP0 If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO. [0:0] read-write RISCV_SOFTIRQ Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect. 0x1A0 0x00000000 CORE1_CLR Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag. [9:9] read-write CORE0_CLR Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag. [8:8] read-write CORE1_SET Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag. [1:1] read-write CORE0_SET Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag. [0:0] read-write MTIME_CTRL Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores. 0x1A4 0x0000000D DBGPAUSE_CORE1 If 1, the timer pauses when core 1 is in the debug halt state. [3:3] read-write DBGPAUSE_CORE0 If 1, the timer pauses when core 0 is in the debug halt state. [2:2] read-write FULLSPEED If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input. [1:1] read-write EN Timer enable bit. When 0, the timer will not increment automatically. [0:0] read-write MTIME Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. 0x1B0 0x00000000 MTIME [31:0] read-write MTIMEH Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence. 0x1B4 0x00000000 MTIMEH [31:0] read-write MTIMECMP Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. 0x1B8 0xFFFFFFFF MTIMECMP [31:0] read-write MTIMECMPH High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values. 0x1BC 0xFFFFFFFF MTIMECMPH [31:0] read-write TMDS_CTRL Control register for TMDS encoder. 0x1C0 0x00000000 CLEAR_BALANCE Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline. [28:28] write-only PIX2_NOSHIFT When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling. [27:27] read-write PIX_SHIFT Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.) [26:24] read-write 0 Do not shift the colour data register. 0 1 Shift the colour data register by 1 bit 1 2 Shift the colour data register by 2 bits 2 4 Shift the colour data register by 4 bits 3 8 Shift the colour data register by 8 bits 4 16 Shift the colour data register by 16 bits 5 INTERLEAVE Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant. [23:23] read-write L2_NBITS Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. [20:18] read-write L1_NBITS Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. [17:15] read-write L0_NBITS Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate. [14:12] read-write L2_ROT Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input. [11:8] read-write L1_ROT Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input. [7:4] read-write L0_ROT Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input. [3:0] read-write TMDS_WDATA Write-only access to the TMDS colour data register. 0x1C4 0x00000000 TMDS_WDATA [31:0] write-only TMDS_PEEK_SINGLE Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling. 0x1C8 0x00000000 TMDS_PEEK_SINGLE [31:0] read-only modify TMDS_POP_SINGLE Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder. 0x1CC 0x00000000 TMDS_POP_SINGLE [31:0] read-only modify TMDS_PEEK_DOUBLE_L0 Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. 0x1D0 0x00000000 TMDS_PEEK_DOUBLE_L0 [31:0] read-only modify TMDS_POP_DOUBLE_L0 Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. 0x1D4 0x00000000 TMDS_POP_DOUBLE_L0 [31:0] read-only modify TMDS_PEEK_DOUBLE_L1 Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. 0x1D8 0x00000000 TMDS_PEEK_DOUBLE_L1 [31:0] read-only modify TMDS_POP_DOUBLE_L1 Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. 0x1DC 0x00000000 TMDS_POP_DOUBLE_L1 [31:0] read-only modify TMDS_PEEK_DOUBLE_L2 Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane. 0x1E0 0x00000000 TMDS_PEEK_DOUBLE_L2 [31:0] read-only modify TMDS_POP_DOUBLE_L2 Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT. 0x1E4 0x00000000 TMDS_POP_DOUBLE_L2 [31:0] read-only modify SIO_NS 0xD0020000 BOOTRAM Additional registers mapped adjacent to the bootram, for use by the bootrom. 0x400E0000 0x0 0x82C registers WRITE_ONCE0 This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. 0x800 0x00000000 WRITE_ONCE0 [31:0] read-write WRITE_ONCE1 This registers always ORs writes into its current contents. Once a bit is set, it can only be cleared by a reset. 0x804 0x00000000 WRITE_ONCE1 [31:0] read-write BOOTLOCK_STAT Bootlock status register. 1=unclaimed, 0=claimed. These locks function identically to the SIO spinlocks, but are reserved for bootrom use. 0x808 0x000000FF BOOTLOCK_STAT [7:0] read-write BOOTLOCK0 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x80C 0x00000000 BOOTLOCK0 [31:0] read-write BOOTLOCK1 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x810 0x00000000 BOOTLOCK1 [31:0] read-write BOOTLOCK2 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x814 0x00000000 BOOTLOCK2 [31:0] read-write BOOTLOCK3 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x818 0x00000000 BOOTLOCK3 [31:0] read-write BOOTLOCK4 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x81C 0x00000000 BOOTLOCK4 [31:0] read-write BOOTLOCK5 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x820 0x00000000 BOOTLOCK5 [31:0] read-write BOOTLOCK6 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x824 0x00000000 BOOTLOCK6 [31:0] read-write BOOTLOCK7 Read to claim and check. Write to unclaim. The value returned on successful claim is 1 << n, and on failed claim is zero. 0x828 0x00000000 BOOTLOCK7 [31:0] read-write CORESIGHT_TRACE Coresight block - RP specific registers 0x50700000 0x0 0x8 registers CTRL_STATUS Control and status register 0x0 0x00000001 TRACE_CAPTURE_FIFO_OVERFLOW This status flag is set high when trace data has been dropped due to the FIFO being full at the point trace data was sampled. Write 1 to acknowledge and clear the bit. [1:1] read-write TRACE_CAPTURE_FIFO_FLUSH Set to 1 to continuously hold the trace FIFO in a flushed state and prevent overflow. Before clearing this flag, configure and start a DMA channel with the correct DREQ for the TRACE_CAPTURE_FIFO register. Clear this flag to begin sampling trace data, and set once again once the trace capture buffer is full. You must configure the TPIU in order to generate trace packets to be captured, as well as components like the ETM further upstream to generate the event stream propagated to the TPIU. [0:0] read-write TRACE_CAPTURE_FIFO FIFO for trace data captured from the TPIU 0x4 0x00000000 RDATA Read from an 8 x 32-bit FIFO containing trace data captured from the TPIU. Hardware pushes to the FIFO on rising edges of clk_sys, when either of the following is true: * TPIU TRACECTL output is low (normal trace data) * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and TRACEDATA1 are both low (trigger packet) These conditions are in accordance with Arm Coresight Architecture Spec v3.0 section D3.3.3: Decoding requirements for Trace Capture Devices The data captured into the FIFO is the full 32-bit TRACEDATA bus output by the TPIU. Note that the TPIU is a DDR output at half of clk_sys, therefore this interface can capture the full 32-bit TPIU DDR output bandwidth as it samples once per active edge of the TPIU output clock. [31:0] read-only modify USB USB FS/LS controller device registers 0x50110000 0x0 0x118 registers USBCTRL_IRQ 14 ADDR_ENDP Device address and endpoint control 0x0 0x00000000 ENDPOINT Device endpoint to send data to. Only valid for HOST mode. [19:16] read-write ADDRESS In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. [6:0] read-write 15 0x4 1-15 HOST_ADDR_ENDP%s Interrupt endpoints. Only valid in HOST mode. 0x4 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write MAIN_CTRL Main control register 0x40 0x00000004 SIM_TIMING Reduced timings for simulation [31:31] read-write PHY_ISO Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1 [2:2] read-write HOST_NDEVICE Device mode = 0, Host mode = 1 [1:1] read-write CONTROLLER_EN Enable controller [0:0] read-write SOF_WR Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. 0x44 0x00000000 COUNT [10:0] write-only SOF_RD Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. 0x48 0x00000000 COUNT [10:0] read-only SIE_CTRL SIE control register 0x4C 0x00008000 EP0_INT_STALL Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL [31:31] read-write EP0_DOUBLE_BUF Device: EP0 single buffered = 0, double buffered = 1 [30:30] read-write EP0_INT_1BUF Device: Set bit in BUFF_STATUS for every buffer completed on EP0 [29:29] read-write EP0_INT_2BUF Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 [28:28] read-write EP0_INT_NAK Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK [27:27] read-write DIRECT_EN Direct bus drive enable [26:26] read-write DIRECT_DP Direct control of DP [25:25] read-write DIRECT_DM Direct control of DM [24:24] read-write EP0_STOP_ON_SHORT_PACKET Device: Stop EP0 on a short packet. [19:19] read-write TRANSCEIVER_PD Power down bus transceiver [18:18] read-write RPU_OPT Device: Pull-up strength (0=1K2, 1=2k3) [17:17] read-write PULLUP_EN Device: Enable pull up resistor [16:16] read-write PULLDOWN_EN Host: Enable pull down resistors [15:15] read-write RESET_BUS Host: Reset bus [13:13] write-only RESUME Device: Remote wakeup. Device can initiate its own resume after suspend. [12:12] write-only VBUS_EN Host: Enable VBUS [11:11] read-write KEEP_ALIVE_EN Host: Enable keep alive packet (for low speed bus) [10:10] read-write SOF_EN Host: Enable SOF generation (for full speed bus) [9:9] read-write SOF_SYNC Host: Delay packet(s) until after SOF [8:8] read-write PREAMBLE_EN Host: Preable enable for LS device on FS hub [6:6] read-write STOP_TRANS Host: Stop transaction [4:4] write-only RECEIVE_DATA Host: Receive transaction (IN to host) [3:3] read-write SEND_DATA Host: Send transaction (OUT from host) [2:2] read-write SEND_SETUP Host: Send Setup packet [1:1] read-write START_TRANS Host: Start transaction [0:0] write-only SIE_STATUS SIE status register 0x50 0x00000000 DATA_SEQ_ERROR Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID [31:31] read-write oneToClear ACK_REC ACK received. Raised by both host and device. [30:30] read-write oneToClear STALL_REC Host: STALL received [29:29] read-write oneToClear NAK_REC Host: NAK received [28:28] read-write oneToClear RX_TIMEOUT RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. [27:27] read-write oneToClear RX_OVERFLOW RX overflow is raised by the Serial RX engine if the incoming data is too fast. [26:26] read-write oneToClear BIT_STUFF_ERROR Bit Stuff Error. Raised by the Serial RX engine. [25:25] read-write oneToClear CRC_ERROR CRC Error. Raised by the Serial RX engine. [24:24] read-write oneToClear ENDPOINT_ERROR An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error. [23:23] read-write oneToClear BUS_RESET Device: bus reset received [19:19] read-write oneToClear TRANS_COMPLETE Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set [18:18] read-write oneToClear SETUP_REC Device: Setup packet received [17:17] read-write oneToClear CONNECTED Device: connected [16:16] read-only RX_SHORT_PACKET Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early. [12:12] read-write oneToClear RESUME Host: Device has initiated a remote resume. Device: host has initiated a resume. [11:11] read-write oneToClear VBUS_OVER_CURR VBUS over current detected [10:10] read-only SPEED Host: device speed. Disconnected = 00, LS = 01, FS = 10 [9:8] read-only SUSPENDED Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled. [4:4] read-write oneToClear LINE_STATE USB bus line state [3:2] read-only LINE_STATE SE0 SE0 0 J J 1 K K 2 SE1 SE1 3 VBUS_DETECTED Device: VBUS Detected [0:0] read-only INT_EP_CTRL interrupt endpoint control register 0x54 0x00000000 INT_EP_ACTIVE Host: Enable interrupt endpoint 1 -> 15 [15:1] read-write BUFF_STATUS Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. 0x58 0x00000000 EP15_OUT [31:31] read-write oneToClear EP15_IN [30:30] read-write oneToClear EP14_OUT [29:29] read-write oneToClear EP14_IN [28:28] read-write oneToClear EP13_OUT [27:27] read-write oneToClear EP13_IN [26:26] read-write oneToClear EP12_OUT [25:25] read-write oneToClear EP12_IN [24:24] read-write oneToClear EP11_OUT [23:23] read-write oneToClear EP11_IN [22:22] read-write oneToClear EP10_OUT [21:21] read-write oneToClear EP10_IN [20:20] read-write oneToClear EP9_OUT [19:19] read-write oneToClear EP9_IN [18:18] read-write oneToClear EP8_OUT [17:17] read-write oneToClear EP8_IN [16:16] read-write oneToClear EP7_OUT [15:15] read-write oneToClear EP7_IN [14:14] read-write oneToClear EP6_OUT [13:13] read-write oneToClear EP6_IN [12:12] read-write oneToClear EP5_OUT [11:11] read-write oneToClear EP5_IN [10:10] read-write oneToClear EP4_OUT [9:9] read-write oneToClear EP4_IN [8:8] read-write oneToClear EP3_OUT [7:7] read-write oneToClear EP3_IN [6:6] read-write oneToClear EP2_OUT [5:5] read-write oneToClear EP2_IN [4:4] read-write oneToClear EP1_OUT [3:3] read-write oneToClear EP1_IN [2:2] read-write oneToClear EP0_OUT [1:1] read-write oneToClear EP0_IN [0:0] read-write oneToClear BUFF_CPU_SHOULD_HANDLE Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. 0x5C 0x00000000 EP15_OUT [31:31] read-only EP15_IN [30:30] read-only EP14_OUT [29:29] read-only EP14_IN [28:28] read-only EP13_OUT [27:27] read-only EP13_IN [26:26] read-only EP12_OUT [25:25] read-only EP12_IN [24:24] read-only EP11_OUT [23:23] read-only EP11_IN [22:22] read-only EP10_OUT [21:21] read-only EP10_IN [20:20] read-only EP9_OUT [19:19] read-only EP9_IN [18:18] read-only EP8_OUT [17:17] read-only EP8_IN [16:16] read-only EP7_OUT [15:15] read-only EP7_IN [14:14] read-only EP6_OUT [13:13] read-only EP6_IN [12:12] read-only EP5_OUT [11:11] read-only EP5_IN [10:10] read-only EP4_OUT [9:9] read-only EP4_IN [8:8] read-only EP3_OUT [7:7] read-only EP3_IN [6:6] read-only EP2_OUT [5:5] read-only EP2_IN [4:4] read-only EP1_OUT [3:3] read-only EP1_IN [2:2] read-only EP0_OUT [1:1] read-only EP0_IN [0:0] read-only EP_ABORT Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. 0x60 0x00000000 EP15_OUT [31:31] read-write EP15_IN [30:30] read-write EP14_OUT [29:29] read-write EP14_IN [28:28] read-write EP13_OUT [27:27] read-write EP13_IN [26:26] read-write EP12_OUT [25:25] read-write EP12_IN [24:24] read-write EP11_OUT [23:23] read-write EP11_IN [22:22] read-write EP10_OUT [21:21] read-write EP10_IN [20:20] read-write EP9_OUT [19:19] read-write EP9_IN [18:18] read-write EP8_OUT [17:17] read-write EP8_IN [16:16] read-write EP7_OUT [15:15] read-write EP7_IN [14:14] read-write EP6_OUT [13:13] read-write EP6_IN [12:12] read-write EP5_OUT [11:11] read-write EP5_IN [10:10] read-write EP4_OUT [9:9] read-write EP4_IN [8:8] read-write EP3_OUT [7:7] read-write EP3_IN [6:6] read-write EP2_OUT [5:5] read-write EP2_IN [4:4] read-write EP1_OUT [3:3] read-write EP1_IN [2:2] read-write EP0_OUT [1:1] read-write EP0_IN [0:0] read-write EP_ABORT_DONE Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. 0x64 0x00000000 EP15_OUT [31:31] read-write oneToClear EP15_IN [30:30] read-write oneToClear EP14_OUT [29:29] read-write oneToClear EP14_IN [28:28] read-write oneToClear EP13_OUT [27:27] read-write oneToClear EP13_IN [26:26] read-write oneToClear EP12_OUT [25:25] read-write oneToClear EP12_IN [24:24] read-write oneToClear EP11_OUT [23:23] read-write oneToClear EP11_IN [22:22] read-write oneToClear EP10_OUT [21:21] read-write oneToClear EP10_IN [20:20] read-write oneToClear EP9_OUT [19:19] read-write oneToClear EP9_IN [18:18] read-write oneToClear EP8_OUT [17:17] read-write oneToClear EP8_IN [16:16] read-write oneToClear EP7_OUT [15:15] read-write oneToClear EP7_IN [14:14] read-write oneToClear EP6_OUT [13:13] read-write oneToClear EP6_IN [12:12] read-write oneToClear EP5_OUT [11:11] read-write oneToClear EP5_IN [10:10] read-write oneToClear EP4_OUT [9:9] read-write oneToClear EP4_IN [8:8] read-write oneToClear EP3_OUT [7:7] read-write oneToClear EP3_IN [6:6] read-write oneToClear EP2_OUT [5:5] read-write oneToClear EP2_IN [4:4] read-write oneToClear EP1_OUT [3:3] read-write oneToClear EP1_IN [2:2] read-write oneToClear EP0_OUT [1:1] read-write oneToClear EP0_IN [0:0] read-write oneToClear EP_STALL_ARM Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. 0x68 0x00000000 EP0_OUT [1:1] read-write EP0_IN [0:0] read-write NAK_POLL Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. 0x6C 0x00100010 RETRY_COUNT_HI Bits 9:6 of nak_retry count [31:28] read-only EPX_STOPPED_ON_NAK EPX polling has stopped because a nak was received [27:27] read-write oneToClear STOP_EPX_ON_NAK Stop polling epx when a nak is received [26:26] read-write DELAY_FS NAK polling interval for a full speed device [25:16] read-write RETRY_COUNT_LO Bits 5:0 of nak_retry_count [15:10] read-only DELAY_LS NAK polling interval for a low speed device [9:0] read-write EP_STATUS_STALL_NAK Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. 0x70 0x00000000 EP15_OUT [31:31] read-write oneToClear EP15_IN [30:30] read-write oneToClear EP14_OUT [29:29] read-write oneToClear EP14_IN [28:28] read-write oneToClear EP13_OUT [27:27] read-write oneToClear EP13_IN [26:26] read-write oneToClear EP12_OUT [25:25] read-write oneToClear EP12_IN [24:24] read-write oneToClear EP11_OUT [23:23] read-write oneToClear EP11_IN [22:22] read-write oneToClear EP10_OUT [21:21] read-write oneToClear EP10_IN [20:20] read-write oneToClear EP9_OUT [19:19] read-write oneToClear EP9_IN [18:18] read-write oneToClear EP8_OUT [17:17] read-write oneToClear EP8_IN [16:16] read-write oneToClear EP7_OUT [15:15] read-write oneToClear EP7_IN [14:14] read-write oneToClear EP6_OUT [13:13] read-write oneToClear EP6_IN [12:12] read-write oneToClear EP5_OUT [11:11] read-write oneToClear EP5_IN [10:10] read-write oneToClear EP4_OUT [9:9] read-write oneToClear EP4_IN [8:8] read-write oneToClear EP3_OUT [7:7] read-write oneToClear EP3_IN [6:6] read-write oneToClear EP2_OUT [5:5] read-write oneToClear EP2_IN [4:4] read-write oneToClear EP1_OUT [3:3] read-write oneToClear EP1_IN [2:2] read-write oneToClear EP0_OUT [1:1] read-write oneToClear EP0_IN [0:0] read-write oneToClear USB_MUXING Where to connect the USB controller. Should be to_phy by default. 0x74 0x00000001 SWAP_DPDM Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls. [31:31] read-write USBPHY_AS_GPIO Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller. [4:4] read-write SOFTCON [3:3] read-write TO_DIGITAL_PAD [2:2] read-write TO_EXTPHY [1:1] read-write TO_PHY [0:0] read-write USB_PWR Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value. 0x78 0x00000000 OVERCURR_DETECT_EN [5:5] read-write OVERCURR_DETECT [4:4] read-write VBUS_DETECT_OVERRIDE_EN [3:3] read-write VBUS_DETECT [2:2] read-write VBUS_EN_OVERRIDE_EN [1:1] read-write VBUS_EN [0:0] read-write USBPHY_DIRECT This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit. 0x7C 0x00000000 RX_DM_OVERRIDE Override rx_dm value into controller [25:25] read-write RX_DP_OVERRIDE Override rx_dp value into controller [24:24] read-write RX_DD_OVERRIDE Override rx_dd value into controller [23:23] read-write DM_OVV DM over voltage [22:22] read-only DP_OVV DP over voltage [21:21] read-only DM_OVCN DM overcurrent [20:20] read-only DP_OVCN DP overcurrent [19:19] read-only RX_DM DPM pin state [18:18] read-only RX_DP DPP pin state [17:17] read-only RX_DD Differential RX [16:16] read-only TX_DIFFMODE TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) [15:15] read-write TX_FSSLEW TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate [14:14] read-write TX_PD TX power down override (if override enable is set). 1 = powered down. [13:13] read-write RX_PD RX power down override (if override enable is set). 1 = powered down. [12:12] read-write TX_DM Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM [11:11] read-write TX_DP Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP [10:10] read-write TX_DM_OE Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving [9:9] read-write TX_DP_OE Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving [8:8] read-write DM_PULLDN_EN DM pull down enable [6:6] read-write DM_PULLUP_EN DM pull up enable [5:5] read-write DM_PULLUP_HISEL Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 [4:4] read-write DP_PULLDN_EN DP pull down enable [2:2] read-write DP_PULLUP_EN DP pull up enable [1:1] read-write DP_PULLUP_HISEL Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 [0:0] read-write USBPHY_DIRECT_OVERRIDE Override enable for each control in usbphy_direct 0x80 0x00000000 RX_DM_OVERRIDE_EN [18:18] read-write RX_DP_OVERRIDE_EN [17:17] read-write RX_DD_OVERRIDE_EN [16:16] read-write TX_DIFFMODE_OVERRIDE_EN [15:15] read-write DM_PULLUP_OVERRIDE_EN [12:12] read-write TX_FSSLEW_OVERRIDE_EN [11:11] read-write TX_PD_OVERRIDE_EN [10:10] read-write RX_PD_OVERRIDE_EN [9:9] read-write TX_DM_OVERRIDE_EN [8:8] read-write TX_DP_OVERRIDE_EN [7:7] read-write TX_DM_OE_OVERRIDE_EN [6:6] read-write TX_DP_OE_OVERRIDE_EN [5:5] read-write DM_PULLDN_EN_OVERRIDE_EN [4:4] read-write DP_PULLDN_EN_OVERRIDE_EN [3:3] read-write DP_PULLUP_EN_OVERRIDE_EN [2:2] read-write DM_PULLUP_HISEL_OVERRIDE_EN [1:1] read-write DP_PULLUP_HISEL_OVERRIDE_EN [0:0] read-write USBPHY_TRIM Used to adjust trim values of USB phy pull down resistors. 0x84 0x00001F1F DM_PULLDN_TRIM Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required [12:8] read-write DP_PULLDN_TRIM Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required [4:0] read-write LINESTATE_TUNING Used for debug only. 0x88 0x000000F8 SPARE_FIX [11:8] read-write DEV_LS_WAKE_FIX Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer [7:7] read-write DEV_RX_ERR_QUIESCE Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet. [6:6] read-write SIE_RX_CHATTER_SE0_FIX RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits. [5:5] read-write SIE_RX_BITSTUFF_FIX RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases. [4:4] read-write DEV_BUFF_CONTROL_DOUBLE_READ_FIX Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match. [3:3] read-write MULTI_HUB_FIX Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays. [2:2] read-write LINESTATE_DELAY Device/Host - add an extra 1-bit debounce of linestate sampling. [1:1] read-write RCV_DELAY Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs. [0:0] read-write INTR Raw Interrupts 0x8C 0x00000000 EPX_STOPPED_ON_NAK Source: NAK_POLL.EPX_STOPPED_ON_NAK [23:23] read-only DEV_SM_WATCHDOG_FIRED Source: DEV_SM_WATCHDOG.FIRED [22:22] read-only ENDPOINT_ERROR Source: SIE_STATUS.ENDPOINT_ERROR [21:21] read-only RX_SHORT_PACKET Source: SIE_STATUS.RX_SHORT_PACKET [20:20] read-only EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-only ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-only DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-only SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-only DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME [15:15] read-only DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-only DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-only BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-only VBUS_DETECT Source: SIE_STATUS.VBUS_DETECTED [11:11] read-only STALL Source: SIE_STATUS.STALL_REC [10:10] read-only ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-only ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-only ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-only ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-only ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-only BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-only TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-only HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-only HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME [1:1] read-only HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-only INTE Interrupt Enable 0x90 0x00000000 EPX_STOPPED_ON_NAK Source: NAK_POLL.EPX_STOPPED_ON_NAK [23:23] read-write DEV_SM_WATCHDOG_FIRED Source: DEV_SM_WATCHDOG.FIRED [22:22] read-write ENDPOINT_ERROR Source: SIE_STATUS.ENDPOINT_ERROR [21:21] read-write RX_SHORT_PACKET Source: SIE_STATUS.RX_SHORT_PACKET [20:20] read-write EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-write ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-write DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-write SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-write DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME [15:15] read-write DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-write DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-write BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-write VBUS_DETECT Source: SIE_STATUS.VBUS_DETECTED [11:11] read-write STALL Source: SIE_STATUS.STALL_REC [10:10] read-write ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-write ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-write ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-write ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-write ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-write BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-write TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-write HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-write HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME [1:1] read-write HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-write INTF Interrupt Force 0x94 0x00000000 EPX_STOPPED_ON_NAK Source: NAK_POLL.EPX_STOPPED_ON_NAK [23:23] read-write DEV_SM_WATCHDOG_FIRED Source: DEV_SM_WATCHDOG.FIRED [22:22] read-write ENDPOINT_ERROR Source: SIE_STATUS.ENDPOINT_ERROR [21:21] read-write RX_SHORT_PACKET Source: SIE_STATUS.RX_SHORT_PACKET [20:20] read-write EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-write ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-write DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-write SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-write DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME [15:15] read-write DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-write DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-write BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-write VBUS_DETECT Source: SIE_STATUS.VBUS_DETECTED [11:11] read-write STALL Source: SIE_STATUS.STALL_REC [10:10] read-write ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-write ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-write ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-write ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-write ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-write BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-write TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-write HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-write HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME [1:1] read-write HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-write INTS Interrupt status after masking & forcing 0x98 0x00000000 EPX_STOPPED_ON_NAK Source: NAK_POLL.EPX_STOPPED_ON_NAK [23:23] read-only DEV_SM_WATCHDOG_FIRED Source: DEV_SM_WATCHDOG.FIRED [22:22] read-only ENDPOINT_ERROR Source: SIE_STATUS.ENDPOINT_ERROR [21:21] read-only RX_SHORT_PACKET Source: SIE_STATUS.RX_SHORT_PACKET [20:20] read-only EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-only ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-only DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-only SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-only DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME [15:15] read-only DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-only DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-only BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-only VBUS_DETECT Source: SIE_STATUS.VBUS_DETECTED [11:11] read-only STALL Source: SIE_STATUS.STALL_REC [10:10] read-only ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-only ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-only ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-only ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-only ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-only BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-only TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-only HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-only HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME [1:1] read-only HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-only SOF_TIMESTAMP_RAW Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events. 0x100 0x00000000 SOF_TIMESTAMP_RAW [20:0] read-only SOF_TIMESTAMP_LAST Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred. 0x104 0x00000000 SOF_TIMESTAMP_LAST [20:0] read-only SM_STATE 0x108 0x00000000 RX_DASM [11:8] read-only BC_STATE [7:5] read-only STATE [4:0] read-only EP_TX_ERROR TX error count for each endpoint. Write to each field to reset the counter to 0. 0x10C 0x00000000 EP15 [31:30] read-write oneToClear EP14 [29:28] read-write oneToClear EP13 [27:26] read-write oneToClear EP12 [25:24] read-write oneToClear EP11 [23:22] read-write oneToClear EP10 [21:20] read-write oneToClear EP9 [19:18] read-write oneToClear EP8 [17:16] read-write oneToClear EP7 [15:14] read-write oneToClear EP6 [13:12] read-write oneToClear EP5 [11:10] read-write oneToClear EP4 [9:8] read-write oneToClear EP3 [7:6] read-write oneToClear EP2 [5:4] read-write oneToClear EP1 [3:2] read-write oneToClear EP0 [1:0] read-write oneToClear EP_RX_ERROR RX error count for each endpoint. Write to each field to reset the counter to 0. 0x110 0x00000000 EP15_SEQ [31:31] read-write oneToClear EP15_TRANSACTION [30:30] read-write oneToClear EP14_SEQ [29:29] read-write oneToClear EP14_TRANSACTION [28:28] read-write oneToClear EP13_SEQ [27:27] read-write oneToClear EP13_TRANSACTION [26:26] read-write oneToClear EP12_SEQ [25:25] read-write oneToClear EP12_TRANSACTION [24:24] read-write oneToClear EP11_SEQ [23:23] read-write oneToClear EP11_TRANSACTION [22:22] read-write oneToClear EP10_SEQ [21:21] read-write oneToClear EP10_TRANSACTION [20:20] read-write oneToClear EP9_SEQ [19:19] read-write oneToClear EP9_TRANSACTION [18:18] read-write oneToClear EP8_SEQ [17:17] read-write oneToClear EP8_TRANSACTION [16:16] read-write oneToClear EP7_SEQ [15:15] read-write oneToClear EP7_TRANSACTION [14:14] read-write oneToClear EP6_SEQ [13:13] read-write oneToClear EP6_TRANSACTION [12:12] read-write oneToClear EP5_SEQ [11:11] read-write oneToClear EP5_TRANSACTION [10:10] read-write oneToClear EP4_SEQ [9:9] read-write oneToClear EP4_TRANSACTION [8:8] read-write oneToClear EP3_SEQ [7:7] read-write oneToClear EP3_TRANSACTION [6:6] read-write oneToClear EP2_SEQ [5:5] read-write oneToClear EP2_TRANSACTION [4:4] read-write oneToClear EP1_SEQ [3:3] read-write oneToClear EP1_TRANSACTION [2:2] read-write oneToClear EP0_SEQ [1:1] read-write oneToClear EP0_TRANSACTION [0:0] read-write oneToClear DEV_SM_WATCHDOG Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable. 0x114 0x00000000 FIRED [20:20] read-write oneToClear RESET Set to 1 to forcibly reset the device state machine on watchdog expiry [19:19] read-write ENABLE [18:18] read-write LIMIT [17:0] read-write TRNG ARM TrustZone RNG register block 0x400F0000 0x0 0x1EC registers TRNG_IRQ 39 RNG_IMR Interrupt masking. 0x100 0x0000000F RESERVED RESERVED [31:4] read-only VN_ERR_INT_MASK 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. [3:3] read-write CRNGT_ERR_INT_MASK 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. [2:2] read-write AUTOCORR_ERR_INT_MASK 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. [1:1] read-write EHR_VALID_INT_MASK 1'b1-mask interrupt, no interrupt will be generated. See RNG_ISR for an explanation on this interrupt. [0:0] read-write RNG_ISR RNG status register. If corresponding RNG_IMR bit is unmasked, an interrupt will be generated. 0x104 0x00000000 RESERVED RESERVED [31:4] read-only VN_ERR 1'b1 indicates Von Neuman error. Error in von Neuman occurs if 32 consecutive collected bits are identical, ZERO or ONE. [3:3] read-only CRNGT_ERR 1'b1 indicates CRNGT in the RNG test failed. Failure occurs when two consecutive blocks of 16 collected bits are equal. [2:2] read-only AUTOCORR_ERR 1'b1 indicates Autocorrelation test failed four times in a row. When set, RNG cease from functioning until next reset. [1:1] read-only EHR_VALID 1'b1 indicates that 192 bits have been collected in the RNG, and are ready to be read. [0:0] read-only RNG_ICR Interrupt/status bit clear Register. 0x108 0x00000000 RESERVED RESERVED [31:4] read-only VN_ERR Write 1'b1 - clear corresponding bit in RNG_ISR. [3:3] read-write CRNGT_ERR Write 1'b1 - clear corresponding bit in RNG_ISR. [2:2] read-write AUTOCORR_ERR Cannot be cleared by SW! Only RNG reset clears this bit. [1:1] read-write EHR_VALID Write 1'b1 - clear corresponding bit in RNG_ISR. [0:0] read-write TRNG_CONFIG Selecting the inverter-chain length. 0x10C 0x00000000 RESERVED RESERVED [31:2] read-only RND_SRC_SEL Selects the number of inverters (out of four possible selections) in the ring oscillator (the entropy source). [1:0] read-write TRNG_VALID 192 bit collection indication. 0x110 0x00000000 RESERVED RESERVED [31:1] read-only EHR_VALID 1'b1 indicates that collection of bits in the RNG is completed, and data can be read from EHR_DATA register. [0:0] read-only EHR_DATA0 RNG collected bits. 0x114 0x00000000 EHR_DATA0 Bits [31:0] of Entropy Holding Register (EHR) - RNG output register [31:0] read-only EHR_DATA1 RNG collected bits. 0x118 0x00000000 EHR_DATA1 Bits [63:32] of Entropy Holding Register (EHR) - RNG output register [31:0] read-only EHR_DATA2 RNG collected bits. 0x11C 0x00000000 EHR_DATA2 Bits [95:64] of Entropy Holding Register (EHR) - RNG output register [31:0] read-only EHR_DATA3 RNG collected bits. 0x120 0x00000000 EHR_DATA3 Bits [127:96] of Entropy Holding Register (EHR) - RNG output register [31:0] read-only EHR_DATA4 RNG collected bits. 0x124 0x00000000 EHR_DATA4 Bits [159:128] of Entropy Holding Register (EHR) - RNG output register [31:0] read-only EHR_DATA5 RNG collected bits. 0x128 0x00000000 EHR_DATA5 Bits [191:160] of Entropy Holding Register (EHR) - RNG output register [31:0] read-only RND_SOURCE_ENABLE Enable signal for the random source. 0x12C 0x00000000 RESERVED RESERVED [31:1] read-only RND_SRC_EN * 1'b1 - entropy source is enabled. *1'b0 - entropy source is disabled [0:0] read-write SAMPLE_CNT1 Counts clocks between sampling of random bit. 0x130 0x0000FFFF SAMPLE_CNTR1 Sets the number of rng_clk cycles between two consecutive ring oscillator samples. Note! If the Von-Neuman is bypassed, the minimum value for sample counter must not be less then decimal seventeen [31:0] read-write AUTOCORR_STATISTIC Statistic about Autocorrelation test activations. 0x134 0x00000000 RESERVED RESERVED [31:22] read-only AUTOCORR_FAILS Count each time an autocorrelation test fails. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. [21:14] read-write AUTOCORR_TRYS Count each time an autocorrelation test starts. Any write to the register reset the counter. Stop collecting statistic if one of the counters reached the limit. [13:0] read-write TRNG_DEBUG_CONTROL Debug register. 0x138 0x00000000 AUTO_CORRELATE_BYPASS When set, the autocorrelation test in the TRNG module is bypassed. [3:3] read-write TRNG_CRNGT_BYPASS When set, the CRNGT test in the RNG is bypassed. [2:2] read-write VNC_BYPASS When set, the Von-Neuman balancer is bypassed (including the 32 consecutive bits test). [1:1] read-write RESERVED N/A [0:0] read-only TRNG_SW_RESET Generate internal SW reset within the RNG block. 0x140 0x00000000 RESERVED RESERVED [31:1] read-only TRNG_SW_RESET Writing 1'b1 to this register causes an internal RNG reset. [0:0] read-write RNG_DEBUG_EN_INPUT Enable the RNG debug mode 0x1B4 0x00000000 RESERVED RESERVED [31:1] read-only RNG_DEBUG_EN * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled [0:0] read-write TRNG_BUSY RNG Busy indication. 0x1B8 0x00000000 RESERVED RESERVED [31:1] read-only TRNG_BUSY Reflects rng_busy status. [0:0] read-only RST_BITS_COUNTER Reset the counter of collected bits in the RNG. 0x1BC 0x00000000 RESERVED RESERVED [31:1] read-only RST_BITS_COUNTER Writing any value to this address will reset the bits counter and RNG valid registers. RND_SORCE_ENABLE register must be unset in order for the reset to take place. [0:0] read-write RNG_VERSION Displays the version settings of the TRNG. 0x1C0 0x00000000 RESERVED RESERVED [31:8] read-only RNG_USE_5_SBOXES * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES [7:7] read-only RESEEDING_EXISTS * 1'b1 - Exists. *1'b0 - Does not exist [6:6] read-only KAT_EXISTS * 1'b1 - Exists. *1'b0 - Does not exist [5:5] read-only PRNG_EXISTS * 1'b1 - Exists. *1'b0 - Does not exist [4:4] read-only TRNG_TESTS_BYPASS_EN * 1'b1 - Exists. *1'b0 - Does not exist [3:3] read-only AUTOCORR_EXISTS * 1'b1 - Exists. *1'b0 - Does not exist [2:2] read-only CRNGT_EXISTS * 1'b1 - Exists. *1'b0 - Does not exist [1:1] read-only EHR_WIDTH_192 * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR [0:0] read-only RNG_BIST_CNTR_0 Collected BIST results. 0x1E0 0x00000000 RESERVED RESERVED [31:22] read-only ROSC_CNTR_VAL Reflects the results of RNG BIST counter. [21:0] read-only RNG_BIST_CNTR_1 Collected BIST results. 0x1E4 0x00000000 RESERVED RESERVED [31:22] read-only ROSC_CNTR_VAL Reflects the results of RNG BIST counter. [21:0] read-only RNG_BIST_CNTR_2 Collected BIST results. 0x1E8 0x00000000 RESERVED RESERVED [31:22] read-only ROSC_CNTR_VAL Reflects the results of RNG BIST counter. [21:0] read-only GLITCH_DETECTOR Glitch detector controls 0x40158000 0x0 0x18 registers ARM Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only. 0x0 0x00005BAD ARM [15:0] read-write no Do not force the glitch detectors to be armed 23469 yes Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES) 0 DISARM 0x4 0x00000000 DISARM Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only. [15:0] read-write no Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO) 0 yes Disarm the glitch detectors 56495 SENSITIVITY Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only. 0x8 0x00000000 DEFAULT [31:24] read-write yes Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES) 0 no Do not use the default sensitivity configured in OTP. Instead use the value from this register. 222 DET3_INV Must be the inverse of DET3, else the default value is used. [15:14] read-write DET2_INV Must be the inverse of DET2, else the default value is used. [13:12] read-write DET1_INV Must be the inverse of DET1, else the default value is used. [11:10] read-write DET0_INV Must be the inverse of DET0, else the default value is used. [9:8] read-write DET3 Set sensitivity for detector 3. Higher values are more sensitive. [7:6] read-write DET2 Set sensitivity for detector 2. Higher values are more sensitive. [5:4] read-write DET1 Set sensitivity for detector 1. Higher values are more sensitive. [3:2] read-write DET0 Set sensitivity for detector 0. Higher values are more sensitive. [1:0] read-write LOCK 0xC 0x00000000 LOCK Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only. [7:0] read-write TRIG_STATUS Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only. 0x10 0x00000000 DET3 [3:3] read-write oneToClear DET2 [2:2] read-write oneToClear DET1 [1:1] read-write oneToClear DET0 [0:0] read-write oneToClear TRIG_FORCE Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only. 0x14 0x00000000 TRIG_FORCE [3:0] write-only OTP SNPS OTP control IF (SBPI and RPi wrapper control) 0x40120000 0x0 0x174 registers OTP_IRQ 38 SW_LOCK0 Software lock register for page 0. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x0 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK1 Software lock register for page 1. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x4 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK2 Software lock register for page 2. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x8 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK3 Software lock register for page 3. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xC 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK4 Software lock register for page 4. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x10 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK5 Software lock register for page 5. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x14 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK6 Software lock register for page 6. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x18 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK7 Software lock register for page 7. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x1C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK8 Software lock register for page 8. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x20 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK9 Software lock register for page 9. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x24 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK10 Software lock register for page 10. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x28 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK11 Software lock register for page 11. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x2C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK12 Software lock register for page 12. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x30 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK13 Software lock register for page 13. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x34 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK14 Software lock register for page 14. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x38 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK15 Software lock register for page 15. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x3C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK16 Software lock register for page 16. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x40 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK17 Software lock register for page 17. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x44 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK18 Software lock register for page 18. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x48 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK19 Software lock register for page 19. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x4C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK20 Software lock register for page 20. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x50 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK21 Software lock register for page 21. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x54 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK22 Software lock register for page 22. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x58 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK23 Software lock register for page 23. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x5C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK24 Software lock register for page 24. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x60 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK25 Software lock register for page 25. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x64 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK26 Software lock register for page 26. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x68 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK27 Software lock register for page 27. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x6C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK28 Software lock register for page 28. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x70 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK29 Software lock register for page 29. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x74 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK30 Software lock register for page 30. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x78 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK31 Software lock register for page 31. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x7C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK32 Software lock register for page 32. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x80 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK33 Software lock register for page 33. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x84 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK34 Software lock register for page 34. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x88 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK35 Software lock register for page 35. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x8C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK36 Software lock register for page 36. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x90 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK37 Software lock register for page 37. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x94 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK38 Software lock register for page 38. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x98 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK39 Software lock register for page 39. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0x9C 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK40 Software lock register for page 40. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xA0 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK41 Software lock register for page 41. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xA4 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK42 Software lock register for page 42. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xA8 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK43 Software lock register for page 43. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xAC 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK44 Software lock register for page 44. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xB0 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK45 Software lock register for page 45. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xB4 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK46 Software lock register for page 46. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xB8 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK47 Software lock register for page 47. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xBC 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK48 Software lock register for page 48. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xC0 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK49 Software lock register for page 49. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xC4 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK50 Software lock register for page 50. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xC8 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK51 Software lock register for page 51. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xCC 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK52 Software lock register for page 52. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xD0 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK53 Software lock register for page 53. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xD4 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK54 Software lock register for page 54. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xD8 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK55 Software lock register for page 55. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xDC 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK56 Software lock register for page 56. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xE0 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK57 Software lock register for page 57. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xE4 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK58 Software lock register for page 58. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xE8 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK59 Software lock register for page 59. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xEC 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK60 Software lock register for page 60. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xF0 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK61 Software lock register for page 61. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xF4 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK62 Software lock register for page 62. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xF8 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SW_LOCK63 Software lock register for page 63. Locks are initialised from the OTP lock pages at reset. This register can be written to further advance the lock state of each page (until next reset), and read to check the current lock state of a page. 0xFC 0x00000000 NSEC Non-secure lock status. Writes are OR'd with the current value. [3:2] read-write read_write 0 read_only 1 inaccessible 3 SEC Secure lock status. Writes are OR'd with the current value. This field is read-only to Non-secure code. [1:0] read-write read_write 0 read_only 1 inaccessible 3 SBPI_INSTR Dispatch instructions to the SBPI interface, used for programming the OTP fuses. 0x100 0x00000000 EXEC Execute instruction [30:30] write-only IS_WR Payload type is write [29:29] read-write HAS_PAYLOAD Instruction has payload (data to be written or to be read) [28:28] read-write PAYLOAD_SIZE_M1 Instruction payload size in bytes minus 1 [27:24] read-write TARGET Instruction target, it can be PMC (0x3a) or DAP (0x02) [23:16] read-write CMD [15:8] read-write SHORT_WDATA wdata to be used only when payload_size_m1=0 [7:0] read-write SBPI_WDATA_0 SBPI write payload bytes 3..0 0x104 0x00000000 SBPI_WDATA_0 [31:0] read-write SBPI_WDATA_1 SBPI write payload bytes 7..4 0x108 0x00000000 SBPI_WDATA_1 [31:0] read-write SBPI_WDATA_2 SBPI write payload bytes 11..8 0x10C 0x00000000 SBPI_WDATA_2 [31:0] read-write SBPI_WDATA_3 SBPI write payload bytes 15..12 0x110 0x00000000 SBPI_WDATA_3 [31:0] read-write SBPI_RDATA_0 Read payload bytes 3..0. Once read, the data in the register will automatically clear to 0. 0x114 0x00000000 SBPI_RDATA_0 [31:0] read-only modify SBPI_RDATA_1 Read payload bytes 7..4. Once read, the data in the register will automatically clear to 0. 0x118 0x00000000 SBPI_RDATA_1 [31:0] read-only modify SBPI_RDATA_2 Read payload bytes 11..8. Once read, the data in the register will automatically clear to 0. 0x11C 0x00000000 SBPI_RDATA_2 [31:0] read-only modify SBPI_RDATA_3 Read payload bytes 15..12. Once read, the data in the register will automatically clear to 0. 0x120 0x00000000 SBPI_RDATA_3 [31:0] read-only modify SBPI_STATUS 0x124 0x00000000 MISO SBPI MISO (master in - slave out): response from SBPI [23:16] read-only FLAG SBPI flag [12:12] read-only INSTR_MISS Last instruction missed (dropped), as the previous has not finished running [8:8] read-write oneToClear INSTR_DONE Last instruction done [4:4] read-write oneToClear RDATA_VLD Read command has returned data [0:0] read-write oneToClear USR Controls for APB data read interface (USER interface) 0x128 0x00000001 PD Power-down; 1 disables current reference. Must be 0 to read data from the OTP. [4:4] read-write DCTRL 1 enables USER interface; 0 disables USER interface (enables SBPI). This bit must be cleared before performing any SBPI access, such as when programming the OTP. The APB data read interface (USER interface) will be inaccessible during this time, and will return a bus error if any read is attempted. [0:0] read-write DBG Debug for OTP power-on state machine 0x12C 0x00000000 CUSTOMER_RMA_FLAG The chip is in RMA mode [12:12] read-only PSM_STATE Monitor the PSM FSM's state [7:4] read-only ROSC_UP Ring oscillator is up and running [3:3] read-only ROSC_UP_SEEN Ring oscillator was seen up and running [2:2] read-write oneToClear BOOT_DONE PSM boot done status flag [1:1] read-only PSM_DONE PSM done status flag [0:0] read-only BIST During BIST, count address locations that have at least one leaky bit 0x134 0x0FFF0000 CNT_FAIL Flag if the count of address locations with at least one leaky bit exceeds cnt_max [30:30] read-only CNT_CLR Clear counter before use [29:29] write-only CNT_ENA Enable the counter before the BIST function is initiated [28:28] read-write CNT_MAX The cnt_fail flag will be set if the number of leaky locations exceeds this number [27:16] read-write CNT Number of locations that have at least one leaky bit. Note: This count is true only if the BIST was initiated without the fix option. [12:0] read-only CRT_KEY_W0 Word 0 (bits 31..0) of the key. Write only, read returns 0x0 0x138 0x00000000 CRT_KEY_W0 [31:0] write-only CRT_KEY_W1 Word 1 (bits 63..32) of the key. Write only, read returns 0x0 0x13C 0x00000000 CRT_KEY_W1 [31:0] write-only CRT_KEY_W2 Word 2 (bits 95..64) of the key. Write only, read returns 0x0 0x140 0x00000000 CRT_KEY_W2 [31:0] write-only CRT_KEY_W3 Word 3 (bits 127..96) of the key. Write only, read returns 0x0 0x144 0x00000000 CRT_KEY_W3 [31:0] write-only CRITICAL Quickly check values of critical flags read during boot up 0x148 0x00000000 RISCV_DISABLE [17:17] read-only ARM_DISABLE [16:16] read-only GLITCH_DETECTOR_SENS [6:5] read-only GLITCH_DETECTOR_ENABLE [4:4] read-only DEFAULT_ARCHSEL [3:3] read-only DEBUG_DISABLE [2:2] read-only SECURE_DEBUG_DISABLE [1:1] read-only SECURE_BOOT_ENABLE [0:0] read-only KEY_VALID Which keys were valid (enrolled) at boot time 0x14C 0x00000000 KEY_VALID [7:0] read-only DEBUGEN Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD. Specifically: - The DEBUG_DISABLE flag disables all debug features. This can be fully overridden by setting all bits of this register. - The SECURE_DEBUG_DISABLE flag disables secure processor debug. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If a single debug key has been registered, and no matching key value has been supplied over SWD, then all debug features are disabled. This can be fully overridden by setting all bits of this register. - If both debug keys have been registered, and the Non-secure key's value (key 6) has been supplied over SWD, secure processor debug is disabled. This can be fully overridden by setting the PROC0_SECURE and PROC1_SECURE bits of this register. - If both debug keys have been registered, and the Secure key's value (key 5) has been supplied over SWD, then no debug features are disabled by the key mechanism. However, note that in this case debug features may still be disabled by the critical boot flags. 0x150 0x00000000 MISC Enable other debug components. Specifically, the CTI, and the APB-AP used to access the RISC-V Debug Module. These components are disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. [8:8] read-write PROC1_SECURE Permit core 1's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 1 (SPIDEN and SPNIDEN). Secure debug of core 1 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. [3:3] read-write PROC1 Enable core 1's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. [2:2] read-write PROC0_SECURE Permit core 0's Mem-AP to generate Secure accesses, assuming it is enabled at all. Also enable secure debug of core 0 (SPIDEN and SPNIDEN). Secure debug of core 0 is disabled by default if the secure debug disable critical flag is set, or if at least one debug key has been enrolled and the most secure of these enrolled key values not yet provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). [1:1] read-write PROC0 Enable core 0's Mem-AP if it is currently disabled. The Mem-AP is disabled by default if either of the debug disable critical flags is set, or if at least one debug key has been enrolled and the least secure of these enrolled key values has not been provided over SWD. Note also that core Mem-APs are unconditionally disabled when a core is switched to RISC-V mode (by setting the ARCHSEL bit and performing a warm reset of the core). [0:0] read-write DEBUGEN_LOCK Write 1s to lock corresponding bits in DEBUGEN. This register is reset by the processor cold reset. 0x154 0x00000000 MISC Write 1 to lock the MISC bit of DEBUGEN. Can't be cleared once set. [8:8] read-write PROC1_SECURE Write 1 to lock the PROC1_SECURE bit of DEBUGEN. Can't be cleared once set. [3:3] read-write PROC1 Write 1 to lock the PROC1 bit of DEBUGEN. Can't be cleared once set. [2:2] read-write PROC0_SECURE Write 1 to lock the PROC0_SECURE bit of DEBUGEN. Can't be cleared once set. [1:1] read-write PROC0 Write 1 to lock the PROC0 bit of DEBUGEN. Can't be cleared once set. [0:0] read-write ARCHSEL Architecture select (Arm/RISC-V). The default and allowable values of this register are constrained by the critical boot flags. This register is reset by the earliest reset in the switched core power domain (before a processor cold reset). Cores sample their architecture select signal on a warm reset. The source of the warm reset could be the system power-up state machine, the watchdog timer, Arm SYSRESETREQ or from RISC-V hartresetreq. Note that when an Arm core is deselected, its cold reset domain is also held in reset, since in particular the SYSRESETREQ bit becomes inaccessible once the core is deselected. Note also the RISC-V cores do not have a cold reset domain, since their corresponding controls are located in the Debug Module. 0x158 0x00000000 CORE1 Select architecture for core 1. [1:1] read-write arm Switch core 1 to Arm (Cortex-M33) 0 riscv Switch core 1 to RISC-V (Hazard3) 1 CORE0 Select architecture for core 0. [0:0] read-write arm Switch core 0 to Arm (Cortex-M33) 0 riscv Switch core 0 to RISC-V (Hazard3) 1 ARCHSEL_STATUS Get the current architecture select state of each core. Cores sample the current value of the ARCHSEL register when their warm reset is released, at which point the corresponding bit in this register will also update. 0x15C 0x00000000 CORE1 Current architecture for core 0. Updated on processor warm reset. [1:1] read-only arm Core 1 is currently Arm (Cortex-M33) 0 riscv Core 1 is currently RISC-V (Hazard3) 1 CORE0 Current architecture for core 0. Updated on processor warm reset. [0:0] read-only arm Core 0 is currently Arm (Cortex-M33) 0 riscv Core 0 is currently RISC-V (Hazard3) 1 BOOTDIS Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up. If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by performing a watchdog reset that resets the OTP. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the power manager BOOTDIS register. 0x160 0x00000000 NEXT This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the boot scratch registers will be ignored following the next core power down. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it via watchdog reset. [1:1] read-write NOW When the core is powered down, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the boot scratch registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data. [0:0] read-write oneToClear INTR Raw Interrupts 0x164 0x00000000 APB_RD_NSEC_FAIL [4:4] read-write oneToClear APB_RD_SEC_FAIL [3:3] read-write oneToClear APB_DCTRL_FAIL [2:2] read-write oneToClear SBPI_WR_FAIL [1:1] read-write oneToClear SBPI_FLAG_N [0:0] read-only INTE Interrupt Enable 0x168 0x00000000 APB_RD_NSEC_FAIL [4:4] read-write APB_RD_SEC_FAIL [3:3] read-write APB_DCTRL_FAIL [2:2] read-write SBPI_WR_FAIL [1:1] read-write SBPI_FLAG_N [0:0] read-write INTF Interrupt Force 0x16C 0x00000000 APB_RD_NSEC_FAIL [4:4] read-write APB_RD_SEC_FAIL [3:3] read-write APB_DCTRL_FAIL [2:2] read-write SBPI_WR_FAIL [1:1] read-write SBPI_FLAG_N [0:0] read-write INTS Interrupt status after masking & forcing 0x170 0x00000000 APB_RD_NSEC_FAIL [4:4] read-only APB_RD_SEC_FAIL [3:3] read-only APB_DCTRL_FAIL [2:2] read-only SBPI_WR_FAIL [1:1] read-only SBPI_FLAG_N [0:0] read-only OTP_DATA Predefined OTP data layout for RP2350 0x40130000 0x0 0x1EF0 registers CHIPID0 Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. 0x0 0x10 0x00000000 CHIPID0 [15:0] read-only CHIPID1 Bits 31:16 of public device ID (ECC) 0x2 0x10 0x00000000 CHIPID1 [15:0] read-only CHIPID2 Bits 47:32 of public device ID (ECC) 0x4 0x10 0x00000000 CHIPID2 [15:0] read-only CHIPID3 Bits 63:48 of public device ID (ECC) 0x6 0x10 0x00000000 CHIPID3 [15:0] read-only RANDID0 Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. 0x8 0x10 0x00000000 RANDID0 [15:0] read-only RANDID1 Bits 31:16 of private per-device random number (ECC) 0xA 0x10 0x00000000 RANDID1 [15:0] read-only RANDID2 Bits 47:32 of private per-device random number (ECC) 0xC 0x10 0x00000000 RANDID2 [15:0] read-only RANDID3 Bits 63:48 of private per-device random number (ECC) 0xE 0x10 0x00000000 RANDID3 [15:0] read-only RANDID4 Bits 79:64 of private per-device random number (ECC) 0x10 0x10 0x00000000 RANDID4 [15:0] read-only RANDID5 Bits 95:80 of private per-device random number (ECC) 0x12 0x10 0x00000000 RANDID5 [15:0] read-only RANDID6 Bits 111:96 of private per-device random number (ECC) 0x14 0x10 0x00000000 RANDID6 [15:0] read-only RANDID7 Bits 127:112 of private per-device random number (ECC) 0x16 0x10 0x00000000 RANDID7 [15:0] read-only ROSC_CALIB Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. 0x20 0x10 0x00000000 ROSC_CALIB [15:0] read-only LPOSC_CALIB Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. 0x22 0x10 0x00000000 LPOSC_CALIB [15:0] read-only NUM_GPIOS The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) 0x30 0x10 0x00000000 NUM_GPIOS [7:0] read-only INFO_CRC0 Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) 0x6C 0x10 0x00000000 INFO_CRC0 [15:0] read-only INFO_CRC1 Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) 0x6E 0x10 0x00000000 INFO_CRC1 [15:0] read-only FLASH_DEVINFO Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. 0xA8 0x10 0x00000000 CS1_SIZE The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. [15:12] read-only NONE 0 8K 1 16K 2 32K 3 64k 4 128K 5 256K 6 512K 7 1M 8 2M 9 4M 10 8M 11 16M 12 CS0_SIZE The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. [11:8] read-only NONE 0 8K 1 16K 2 32K 3 64k 4 128K 5 256K 6 512K 7 1M 8 2M 9 4M 10 8M 11 16M 12 D8H_ERASE_SUPPORTED If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. [7:7] read-only CS1_GPIO Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). [5:0] read-only FLASH_PARTITION_SLOT_SIZE Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) 0xAA 0x10 0x00000000 FLASH_PARTITION_SLOT_SIZE [15:0] read-only BOOTSEL_LED_CFG Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. 0xAC 0x10 0x00000000 ACTIVELOW LED is active-low. (Default: active-high.) [8:8] read-only PIN GPIO index to use for bootloader activity LED. [5:0] read-only BOOTSEL_PLL_CFG Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. 0xAE 0x10 0x00000000 REFDIV PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) [15:15] read-only POSTDIV2 PLL post-divide 2 divisor, in the range 1..7 inclusive. [14:12] read-only POSTDIV1 PLL post-divide 1 divisor, in the range 1..7 inclusive. [11:9] read-only FBDIV PLL feedback divisor, in the range 16..320 inclusive. [8:0] read-only BOOTSEL_XOSC_CFG Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. 0xB0 0x10 0x00000000 RANGE Value of the XOSC_CTRL_FREQ_RANGE register. [15:14] read-only 1_15MHZ 0 10_30MHZ 1 25_60MHZ 2 40_100MHZ 3 STARTUP Value of the XOSC_STARTUP register [13:0] read-only USB_WHITE_LABEL_ADDR Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): 0xB8 0x10 0x00000000 USB_WHITE_LABEL_ADDR [15:0] read-only INDEX_USB_DEVICE_VID_VALUE 0 INDEX_USB_DEVICE_PID_VALUE 1 INDEX_USB_DEVICE_BCD_DEVICE_VALUE 2 INDEX_USB_DEVICE_LANG_ID_VALUE 3 INDEX_USB_DEVICE_MANUFACTURER_STRDEF 4 INDEX_USB_DEVICE_PRODUCT_STRDEF 5 INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF 6 INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES 7 INDEX_VOLUME_LABEL_STRDEF 8 INDEX_SCSI_INQUIRY_VENDOR_STRDEF 9 INDEX_SCSI_INQUIRY_PRODUCT_STRDEF 10 INDEX_SCSI_INQUIRY_VERSION_STRDEF 11 INDEX_INDEX_HTM_REDIRECT_URL_STRDEF 12 INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF 13 INDEX_INFO_UF2_TXT_MODEL_STRDEF 14 INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF 15 OTPBOOT_SRC OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. 0xBC 0x10 0x00000000 OTPBOOT_SRC [15:0] read-only OTPBOOT_LEN Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). 0xBE 0x10 0x00000000 OTPBOOT_LEN [15:0] read-only OTPBOOT_DST0 Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. 0xC0 0x10 0x00000000 OTPBOOT_DST0 [15:0] read-only OTPBOOT_DST1 Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. 0xC2 0x10 0x00000000 OTPBOOT_DST1 [15:0] read-only BOOTKEY0_0 Bits 15:0 of SHA-256 hash of boot key 0 (ECC) 0x100 0x10 0x00000000 BOOTKEY0_0 [15:0] read-only BOOTKEY0_1 Bits 31:16 of SHA-256 hash of boot key 0 (ECC) 0x102 0x10 0x00000000 BOOTKEY0_1 [15:0] read-only BOOTKEY0_2 Bits 47:32 of SHA-256 hash of boot key 0 (ECC) 0x104 0x10 0x00000000 BOOTKEY0_2 [15:0] read-only BOOTKEY0_3 Bits 63:48 of SHA-256 hash of boot key 0 (ECC) 0x106 0x10 0x00000000 BOOTKEY0_3 [15:0] read-only BOOTKEY0_4 Bits 79:64 of SHA-256 hash of boot key 0 (ECC) 0x108 0x10 0x00000000 BOOTKEY0_4 [15:0] read-only BOOTKEY0_5 Bits 95:80 of SHA-256 hash of boot key 0 (ECC) 0x10A 0x10 0x00000000 BOOTKEY0_5 [15:0] read-only BOOTKEY0_6 Bits 111:96 of SHA-256 hash of boot key 0 (ECC) 0x10C 0x10 0x00000000 BOOTKEY0_6 [15:0] read-only BOOTKEY0_7 Bits 127:112 of SHA-256 hash of boot key 0 (ECC) 0x10E 0x10 0x00000000 BOOTKEY0_7 [15:0] read-only BOOTKEY0_8 Bits 143:128 of SHA-256 hash of boot key 0 (ECC) 0x110 0x10 0x00000000 BOOTKEY0_8 [15:0] read-only BOOTKEY0_9 Bits 159:144 of SHA-256 hash of boot key 0 (ECC) 0x112 0x10 0x00000000 BOOTKEY0_9 [15:0] read-only BOOTKEY0_10 Bits 175:160 of SHA-256 hash of boot key 0 (ECC) 0x114 0x10 0x00000000 BOOTKEY0_10 [15:0] read-only BOOTKEY0_11 Bits 191:176 of SHA-256 hash of boot key 0 (ECC) 0x116 0x10 0x00000000 BOOTKEY0_11 [15:0] read-only BOOTKEY0_12 Bits 207:192 of SHA-256 hash of boot key 0 (ECC) 0x118 0x10 0x00000000 BOOTKEY0_12 [15:0] read-only BOOTKEY0_13 Bits 223:208 of SHA-256 hash of boot key 0 (ECC) 0x11A 0x10 0x00000000 BOOTKEY0_13 [15:0] read-only BOOTKEY0_14 Bits 239:224 of SHA-256 hash of boot key 0 (ECC) 0x11C 0x10 0x00000000 BOOTKEY0_14 [15:0] read-only BOOTKEY0_15 Bits 255:240 of SHA-256 hash of boot key 0 (ECC) 0x11E 0x10 0x00000000 BOOTKEY0_15 [15:0] read-only BOOTKEY1_0 Bits 15:0 of SHA-256 hash of boot key 1 (ECC) 0x120 0x10 0x00000000 BOOTKEY1_0 [15:0] read-only BOOTKEY1_1 Bits 31:16 of SHA-256 hash of boot key 1 (ECC) 0x122 0x10 0x00000000 BOOTKEY1_1 [15:0] read-only BOOTKEY1_2 Bits 47:32 of SHA-256 hash of boot key 1 (ECC) 0x124 0x10 0x00000000 BOOTKEY1_2 [15:0] read-only BOOTKEY1_3 Bits 63:48 of SHA-256 hash of boot key 1 (ECC) 0x126 0x10 0x00000000 BOOTKEY1_3 [15:0] read-only BOOTKEY1_4 Bits 79:64 of SHA-256 hash of boot key 1 (ECC) 0x128 0x10 0x00000000 BOOTKEY1_4 [15:0] read-only BOOTKEY1_5 Bits 95:80 of SHA-256 hash of boot key 1 (ECC) 0x12A 0x10 0x00000000 BOOTKEY1_5 [15:0] read-only BOOTKEY1_6 Bits 111:96 of SHA-256 hash of boot key 1 (ECC) 0x12C 0x10 0x00000000 BOOTKEY1_6 [15:0] read-only BOOTKEY1_7 Bits 127:112 of SHA-256 hash of boot key 1 (ECC) 0x12E 0x10 0x00000000 BOOTKEY1_7 [15:0] read-only BOOTKEY1_8 Bits 143:128 of SHA-256 hash of boot key 1 (ECC) 0x130 0x10 0x00000000 BOOTKEY1_8 [15:0] read-only BOOTKEY1_9 Bits 159:144 of SHA-256 hash of boot key 1 (ECC) 0x132 0x10 0x00000000 BOOTKEY1_9 [15:0] read-only BOOTKEY1_10 Bits 175:160 of SHA-256 hash of boot key 1 (ECC) 0x134 0x10 0x00000000 BOOTKEY1_10 [15:0] read-only BOOTKEY1_11 Bits 191:176 of SHA-256 hash of boot key 1 (ECC) 0x136 0x10 0x00000000 BOOTKEY1_11 [15:0] read-only BOOTKEY1_12 Bits 207:192 of SHA-256 hash of boot key 1 (ECC) 0x138 0x10 0x00000000 BOOTKEY1_12 [15:0] read-only BOOTKEY1_13 Bits 223:208 of SHA-256 hash of boot key 1 (ECC) 0x13A 0x10 0x00000000 BOOTKEY1_13 [15:0] read-only BOOTKEY1_14 Bits 239:224 of SHA-256 hash of boot key 1 (ECC) 0x13C 0x10 0x00000000 BOOTKEY1_14 [15:0] read-only BOOTKEY1_15 Bits 255:240 of SHA-256 hash of boot key 1 (ECC) 0x13E 0x10 0x00000000 BOOTKEY1_15 [15:0] read-only BOOTKEY2_0 Bits 15:0 of SHA-256 hash of boot key 2 (ECC) 0x140 0x10 0x00000000 BOOTKEY2_0 [15:0] read-only BOOTKEY2_1 Bits 31:16 of SHA-256 hash of boot key 2 (ECC) 0x142 0x10 0x00000000 BOOTKEY2_1 [15:0] read-only BOOTKEY2_2 Bits 47:32 of SHA-256 hash of boot key 2 (ECC) 0x144 0x10 0x00000000 BOOTKEY2_2 [15:0] read-only BOOTKEY2_3 Bits 63:48 of SHA-256 hash of boot key 2 (ECC) 0x146 0x10 0x00000000 BOOTKEY2_3 [15:0] read-only BOOTKEY2_4 Bits 79:64 of SHA-256 hash of boot key 2 (ECC) 0x148 0x10 0x00000000 BOOTKEY2_4 [15:0] read-only BOOTKEY2_5 Bits 95:80 of SHA-256 hash of boot key 2 (ECC) 0x14A 0x10 0x00000000 BOOTKEY2_5 [15:0] read-only BOOTKEY2_6 Bits 111:96 of SHA-256 hash of boot key 2 (ECC) 0x14C 0x10 0x00000000 BOOTKEY2_6 [15:0] read-only BOOTKEY2_7 Bits 127:112 of SHA-256 hash of boot key 2 (ECC) 0x14E 0x10 0x00000000 BOOTKEY2_7 [15:0] read-only BOOTKEY2_8 Bits 143:128 of SHA-256 hash of boot key 2 (ECC) 0x150 0x10 0x00000000 BOOTKEY2_8 [15:0] read-only BOOTKEY2_9 Bits 159:144 of SHA-256 hash of boot key 2 (ECC) 0x152 0x10 0x00000000 BOOTKEY2_9 [15:0] read-only BOOTKEY2_10 Bits 175:160 of SHA-256 hash of boot key 2 (ECC) 0x154 0x10 0x00000000 BOOTKEY2_10 [15:0] read-only BOOTKEY2_11 Bits 191:176 of SHA-256 hash of boot key 2 (ECC) 0x156 0x10 0x00000000 BOOTKEY2_11 [15:0] read-only BOOTKEY2_12 Bits 207:192 of SHA-256 hash of boot key 2 (ECC) 0x158 0x10 0x00000000 BOOTKEY2_12 [15:0] read-only BOOTKEY2_13 Bits 223:208 of SHA-256 hash of boot key 2 (ECC) 0x15A 0x10 0x00000000 BOOTKEY2_13 [15:0] read-only BOOTKEY2_14 Bits 239:224 of SHA-256 hash of boot key 2 (ECC) 0x15C 0x10 0x00000000 BOOTKEY2_14 [15:0] read-only BOOTKEY2_15 Bits 255:240 of SHA-256 hash of boot key 2 (ECC) 0x15E 0x10 0x00000000 BOOTKEY2_15 [15:0] read-only BOOTKEY3_0 Bits 15:0 of SHA-256 hash of boot key 3 (ECC) 0x160 0x10 0x00000000 BOOTKEY3_0 [15:0] read-only BOOTKEY3_1 Bits 31:16 of SHA-256 hash of boot key 3 (ECC) 0x162 0x10 0x00000000 BOOTKEY3_1 [15:0] read-only BOOTKEY3_2 Bits 47:32 of SHA-256 hash of boot key 3 (ECC) 0x164 0x10 0x00000000 BOOTKEY3_2 [15:0] read-only BOOTKEY3_3 Bits 63:48 of SHA-256 hash of boot key 3 (ECC) 0x166 0x10 0x00000000 BOOTKEY3_3 [15:0] read-only BOOTKEY3_4 Bits 79:64 of SHA-256 hash of boot key 3 (ECC) 0x168 0x10 0x00000000 BOOTKEY3_4 [15:0] read-only BOOTKEY3_5 Bits 95:80 of SHA-256 hash of boot key 3 (ECC) 0x16A 0x10 0x00000000 BOOTKEY3_5 [15:0] read-only BOOTKEY3_6 Bits 111:96 of SHA-256 hash of boot key 3 (ECC) 0x16C 0x10 0x00000000 BOOTKEY3_6 [15:0] read-only BOOTKEY3_7 Bits 127:112 of SHA-256 hash of boot key 3 (ECC) 0x16E 0x10 0x00000000 BOOTKEY3_7 [15:0] read-only BOOTKEY3_8 Bits 143:128 of SHA-256 hash of boot key 3 (ECC) 0x170 0x10 0x00000000 BOOTKEY3_8 [15:0] read-only BOOTKEY3_9 Bits 159:144 of SHA-256 hash of boot key 3 (ECC) 0x172 0x10 0x00000000 BOOTKEY3_9 [15:0] read-only BOOTKEY3_10 Bits 175:160 of SHA-256 hash of boot key 3 (ECC) 0x174 0x10 0x00000000 BOOTKEY3_10 [15:0] read-only BOOTKEY3_11 Bits 191:176 of SHA-256 hash of boot key 3 (ECC) 0x176 0x10 0x00000000 BOOTKEY3_11 [15:0] read-only BOOTKEY3_12 Bits 207:192 of SHA-256 hash of boot key 3 (ECC) 0x178 0x10 0x00000000 BOOTKEY3_12 [15:0] read-only BOOTKEY3_13 Bits 223:208 of SHA-256 hash of boot key 3 (ECC) 0x17A 0x10 0x00000000 BOOTKEY3_13 [15:0] read-only BOOTKEY3_14 Bits 239:224 of SHA-256 hash of boot key 3 (ECC) 0x17C 0x10 0x00000000 BOOTKEY3_14 [15:0] read-only BOOTKEY3_15 Bits 255:240 of SHA-256 hash of boot key 3 (ECC) 0x17E 0x10 0x00000000 BOOTKEY3_15 [15:0] read-only KEY1_0 Bits 15:0 of OTP access key 1 (ECC) 0x1E90 0x10 0x00000000 KEY1_0 [15:0] read-only KEY1_1 Bits 31:16 of OTP access key 1 (ECC) 0x1E92 0x10 0x00000000 KEY1_1 [15:0] read-only KEY1_2 Bits 47:32 of OTP access key 1 (ECC) 0x1E94 0x10 0x00000000 KEY1_2 [15:0] read-only KEY1_3 Bits 63:48 of OTP access key 1 (ECC) 0x1E96 0x10 0x00000000 KEY1_3 [15:0] read-only KEY1_4 Bits 79:64 of OTP access key 1 (ECC) 0x1E98 0x10 0x00000000 KEY1_4 [15:0] read-only KEY1_5 Bits 95:80 of OTP access key 1 (ECC) 0x1E9A 0x10 0x00000000 KEY1_5 [15:0] read-only KEY1_6 Bits 111:96 of OTP access key 1 (ECC) 0x1E9C 0x10 0x00000000 KEY1_6 [15:0] read-only KEY1_7 Bits 127:112 of OTP access key 1 (ECC) 0x1E9E 0x10 0x00000000 KEY1_7 [15:0] read-only KEY2_0 Bits 15:0 of OTP access key 2 (ECC) 0x1EA0 0x10 0x00000000 KEY2_0 [15:0] read-only KEY2_1 Bits 31:16 of OTP access key 2 (ECC) 0x1EA2 0x10 0x00000000 KEY2_1 [15:0] read-only KEY2_2 Bits 47:32 of OTP access key 2 (ECC) 0x1EA4 0x10 0x00000000 KEY2_2 [15:0] read-only KEY2_3 Bits 63:48 of OTP access key 2 (ECC) 0x1EA6 0x10 0x00000000 KEY2_3 [15:0] read-only KEY2_4 Bits 79:64 of OTP access key 2 (ECC) 0x1EA8 0x10 0x00000000 KEY2_4 [15:0] read-only KEY2_5 Bits 95:80 of OTP access key 2 (ECC) 0x1EAA 0x10 0x00000000 KEY2_5 [15:0] read-only KEY2_6 Bits 111:96 of OTP access key 2 (ECC) 0x1EAC 0x10 0x00000000 KEY2_6 [15:0] read-only KEY2_7 Bits 127:112 of OTP access key 2 (ECC) 0x1EAE 0x10 0x00000000 KEY2_7 [15:0] read-only KEY3_0 Bits 15:0 of OTP access key 3 (ECC) 0x1EB0 0x10 0x00000000 KEY3_0 [15:0] read-only KEY3_1 Bits 31:16 of OTP access key 3 (ECC) 0x1EB2 0x10 0x00000000 KEY3_1 [15:0] read-only KEY3_2 Bits 47:32 of OTP access key 3 (ECC) 0x1EB4 0x10 0x00000000 KEY3_2 [15:0] read-only KEY3_3 Bits 63:48 of OTP access key 3 (ECC) 0x1EB6 0x10 0x00000000 KEY3_3 [15:0] read-only KEY3_4 Bits 79:64 of OTP access key 3 (ECC) 0x1EB8 0x10 0x00000000 KEY3_4 [15:0] read-only KEY3_5 Bits 95:80 of OTP access key 3 (ECC) 0x1EBA 0x10 0x00000000 KEY3_5 [15:0] read-only KEY3_6 Bits 111:96 of OTP access key 3 (ECC) 0x1EBC 0x10 0x00000000 KEY3_6 [15:0] read-only KEY3_7 Bits 127:112 of OTP access key 3 (ECC) 0x1EBE 0x10 0x00000000 KEY3_7 [15:0] read-only KEY4_0 Bits 15:0 of OTP access key 4 (ECC) 0x1EC0 0x10 0x00000000 KEY4_0 [15:0] read-only KEY4_1 Bits 31:16 of OTP access key 4 (ECC) 0x1EC2 0x10 0x00000000 KEY4_1 [15:0] read-only KEY4_2 Bits 47:32 of OTP access key 4 (ECC) 0x1EC4 0x10 0x00000000 KEY4_2 [15:0] read-only KEY4_3 Bits 63:48 of OTP access key 4 (ECC) 0x1EC6 0x10 0x00000000 KEY4_3 [15:0] read-only KEY4_4 Bits 79:64 of OTP access key 4 (ECC) 0x1EC8 0x10 0x00000000 KEY4_4 [15:0] read-only KEY4_5 Bits 95:80 of OTP access key 4 (ECC) 0x1ECA 0x10 0x00000000 KEY4_5 [15:0] read-only KEY4_6 Bits 111:96 of OTP access key 4 (ECC) 0x1ECC 0x10 0x00000000 KEY4_6 [15:0] read-only KEY4_7 Bits 127:112 of OTP access key 4 (ECC) 0x1ECE 0x10 0x00000000 KEY4_7 [15:0] read-only KEY5_0 Bits 15:0 of OTP access key 5 (ECC) 0x1ED0 0x10 0x00000000 KEY5_0 [15:0] read-only KEY5_1 Bits 31:16 of OTP access key 5 (ECC) 0x1ED2 0x10 0x00000000 KEY5_1 [15:0] read-only KEY5_2 Bits 47:32 of OTP access key 5 (ECC) 0x1ED4 0x10 0x00000000 KEY5_2 [15:0] read-only KEY5_3 Bits 63:48 of OTP access key 5 (ECC) 0x1ED6 0x10 0x00000000 KEY5_3 [15:0] read-only KEY5_4 Bits 79:64 of OTP access key 5 (ECC) 0x1ED8 0x10 0x00000000 KEY5_4 [15:0] read-only KEY5_5 Bits 95:80 of OTP access key 5 (ECC) 0x1EDA 0x10 0x00000000 KEY5_5 [15:0] read-only KEY5_6 Bits 111:96 of OTP access key 5 (ECC) 0x1EDC 0x10 0x00000000 KEY5_6 [15:0] read-only KEY5_7 Bits 127:112 of OTP access key 5 (ECC) 0x1EDE 0x10 0x00000000 KEY5_7 [15:0] read-only KEY6_0 Bits 15:0 of OTP access key 6 (ECC) 0x1EE0 0x10 0x00000000 KEY6_0 [15:0] read-only KEY6_1 Bits 31:16 of OTP access key 6 (ECC) 0x1EE2 0x10 0x00000000 KEY6_1 [15:0] read-only KEY6_2 Bits 47:32 of OTP access key 6 (ECC) 0x1EE4 0x10 0x00000000 KEY6_2 [15:0] read-only KEY6_3 Bits 63:48 of OTP access key 6 (ECC) 0x1EE6 0x10 0x00000000 KEY6_3 [15:0] read-only KEY6_4 Bits 79:64 of OTP access key 6 (ECC) 0x1EE8 0x10 0x00000000 KEY6_4 [15:0] read-only KEY6_5 Bits 95:80 of OTP access key 6 (ECC) 0x1EEA 0x10 0x00000000 KEY6_5 [15:0] read-only KEY6_6 Bits 111:96 of OTP access key 6 (ECC) 0x1EEC 0x10 0x00000000 KEY6_6 [15:0] read-only KEY6_7 Bits 127:112 of OTP access key 6 (ECC) 0x1EEE 0x10 0x00000000 KEY6_7 [15:0] read-only OTP_DATA_RAW Predefined OTP data layout for RP2350 0x40134000 0x0 0x4000 registers CHIPID0 Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API. The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique. 0x0 0x00000000 CHIPID0 [15:0] read-only CHIPID1 Bits 31:16 of public device ID (ECC) 0x4 0x00000000 CHIPID1 [15:0] read-only CHIPID2 Bits 47:32 of public device ID (ECC) 0x8 0x00000000 CHIPID2 [15:0] read-only CHIPID3 Bits 63:48 of public device ID (ECC) 0xC 0x00000000 CHIPID3 [15:0] read-only RANDID0 Bits 15:0 of private per-device random number (ECC) The RANDID0..7 rows form a 128-bit random number generated during device test. This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0. 0x10 0x00000000 RANDID0 [15:0] read-only RANDID1 Bits 31:16 of private per-device random number (ECC) 0x14 0x00000000 RANDID1 [15:0] read-only RANDID2 Bits 47:32 of private per-device random number (ECC) 0x18 0x00000000 RANDID2 [15:0] read-only RANDID3 Bits 63:48 of private per-device random number (ECC) 0x1C 0x00000000 RANDID3 [15:0] read-only RANDID4 Bits 79:64 of private per-device random number (ECC) 0x20 0x00000000 RANDID4 [15:0] read-only RANDID5 Bits 95:80 of private per-device random number (ECC) 0x24 0x00000000 RANDID5 [15:0] read-only RANDID6 Bits 111:96 of private per-device random number (ECC) 0x28 0x00000000 RANDID6 [15:0] read-only RANDID7 Bits 127:112 of private per-device random number (ECC) 0x2C 0x00000000 RANDID7 [15:0] read-only ROSC_CALIB Ring oscillator frequency in kHz, measured during manufacturing (ECC) This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state. 0x40 0x00000000 ROSC_CALIB [15:0] read-only LPOSC_CALIB Low-power oscillator frequency in Hz, measured during manufacturing (ECC) This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state. 0x44 0x00000000 LPOSC_CALIB [15:0] read-only NUM_GPIOS The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC) 0x60 0x00000000 NUM_GPIOS [7:0] read-only INFO_CRC0 Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC) 0xD8 0x00000000 INFO_CRC0 [15:0] read-only INFO_CRC1 Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) 0xDC 0x00000000 INFO_CRC1 [15:0] read-only CRIT0 Page 0 critical boot flags (RBIT-8) 0xE0 0x00000000 RISCV_DISABLE Permanently disable RISC-V processors (Hazard3) [1:1] read-only ARM_DISABLE Permanently disable ARM processors (Cortex-M33) [0:0] read-only CRIT0_R1 Redundant copy of CRIT0 0xE4 0x00000000 CRIT0_R1 [23:0] read-only CRIT0_R2 Redundant copy of CRIT0 0xE8 0x00000000 CRIT0_R2 [23:0] read-only CRIT0_R3 Redundant copy of CRIT0 0xEC 0x00000000 CRIT0_R3 [23:0] read-only CRIT0_R4 Redundant copy of CRIT0 0xF0 0x00000000 CRIT0_R4 [23:0] read-only CRIT0_R5 Redundant copy of CRIT0 0xF4 0x00000000 CRIT0_R5 [23:0] read-only CRIT0_R6 Redundant copy of CRIT0 0xF8 0x00000000 CRIT0_R6 [23:0] read-only CRIT0_R7 Redundant copy of CRIT0 0xFC 0x00000000 CRIT0_R7 [23:0] read-only CRIT1 Page 1 critical boot flags (RBIT-8) 0x100 0x00000000 GLITCH_DETECTOR_SENS Increase the sensitivity of the glitch detectors from their default. [6:5] read-only GLITCH_DETECTOR_ENABLE Arm the glitch detectors to reset the system if an abnormal clock/power event is observed. [4:4] read-only BOOT_ARCH Set the default boot architecture, 0=ARM 1=RISC-V. Ignored if ARM_DISABLE, RISCV_DISABLE or SECURE_BOOT_ENABLE is set. [3:3] read-only DEBUG_DISABLE Disable all debug access [2:2] read-only SECURE_DEBUG_DISABLE Disable Secure debug access [1:1] read-only SECURE_BOOT_ENABLE Enable boot signature enforcement, and permanently disable the RISC-V cores. [0:0] read-only CRIT1_R1 Redundant copy of CRIT1 0x104 0x00000000 CRIT1_R1 [23:0] read-only CRIT1_R2 Redundant copy of CRIT1 0x108 0x00000000 CRIT1_R2 [23:0] read-only CRIT1_R3 Redundant copy of CRIT1 0x10C 0x00000000 CRIT1_R3 [23:0] read-only CRIT1_R4 Redundant copy of CRIT1 0x110 0x00000000 CRIT1_R4 [23:0] read-only CRIT1_R5 Redundant copy of CRIT1 0x114 0x00000000 CRIT1_R5 [23:0] read-only CRIT1_R6 Redundant copy of CRIT1 0x118 0x00000000 CRIT1_R6 [23:0] read-only CRIT1_R7 Redundant copy of CRIT1 0x11C 0x00000000 CRIT1_R7 [23:0] read-only BOOT_FLAGS0 Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) 0x120 0x00000000 DISABLE_SRAM_WINDOW_BOOT [21:21] read-only DISABLE_XIP_ACCESS_ON_SRAM_ENTRY Disable all access to XIP after entering an SRAM binary. Note that this will cause bootrom APIs that access XIP to fail, including APIs that interact with the partition table. [20:20] read-only DISABLE_BOOTSEL_UART_BOOT [19:19] read-only DISABLE_BOOTSEL_USB_PICOBOOT_IFC [18:18] read-only DISABLE_BOOTSEL_USB_MSD_IFC [17:17] read-only DISABLE_WATCHDOG_SCRATCH [16:16] read-only DISABLE_POWER_SCRATCH [15:15] read-only ENABLE_OTP_BOOT Enable OTP boot. A number of OTP rows specified by OTPBOOT_LEN will be loaded, starting from OTPBOOT_SRC, into the SRAM location specified by OTPBOOT_DST1 and OTPBOOT_DST0. The loaded program image is stored with ECC, 16 bits per row, and must contain a valid IMAGE_DEF. Do not set this bit without first programming an image into OTP and configuring OTPBOOT_LEN, OTPBOOT_SRC, OTPBOOT_DST0 and OTPBOOT_DST1. Note that OTPBOOT_LEN and OTPBOOT_SRC must be even numbers of OTP rows. Equivalently, the image must be a multiple of 32 bits in size, and must start at a 32-bit-aligned address in the ECC read data address window. [14:14] read-only DISABLE_OTP_BOOT Takes precedence over ENABLE_OTP_BOOT. [13:13] read-only DISABLE_FLASH_BOOT [12:12] read-only ROLLBACK_REQUIRED Require binaries to have a rollback version. Set automatically the first time a binary with a rollback version is booted. [11:11] read-only HASHED_PARTITION_TABLE Require a partition table to be hashed (if not signed) [10:10] read-only SECURE_PARTITION_TABLE Require a partition table to be signed [9:9] read-only DISABLE_AUTO_SWITCH_ARCH Disable auto-switch of CPU architecture on boot when the (only) binary to be booted is for the other Arm/RISC-V architecture and both architectures are enabled [8:8] read-only SINGLE_FLASH_BINARY Restrict flash boot path to use of a single binary at the start of flash [7:7] read-only OVERRIDE_FLASH_PARTITION_SLOT_SIZE Override the limit for default flash metadata scanning. The value is specified in FLASH_PARTITION_SLOT_SIZE. Make sure FLASH_PARTITION_SLOT_SIZE is valid before setting this bit [6:6] read-only FLASH_DEVINFO_ENABLE Mark FLASH_DEVINFO as containing valid, ECC'd data which describes external flash devices. [5:5] read-only FAST_SIGCHECK_ROSC_DIV Enable quartering of ROSC divisor during signature check, to reduce secure boot time [4:4] read-only FLASH_IO_VOLTAGE_1V8 If 1, configure the QSPI pads for 1.8 V operation when accessing flash for the first time from the bootrom, using the VOLTAGE_SELECT register for the QSPI pads bank. This slightly improves the input timing of the pads at low voltages, but does not affect their output characteristics. If 0, leave VOLTAGE_SELECT in its reset state (suitable for operation at and above 2.5 V) [3:3] read-only ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG Enable loading of the non-default XOSC and PLL configuration before entering BOOTSEL mode. Ensure that BOOTSEL_XOSC_CFG and BOOTSEL_PLL_CFG are correctly programmed before setting this bit. If this bit is set, user software may use the contents of BOOTSEL_PLL_CFG to calculated the expected XOSC frequency based on the fixed USB boot frequency of 48 MHz. [2:2] read-only ENABLE_BOOTSEL_LED Enable bootloader activity LED. If set, bootsel_led_cfg is assumed to be valid [1:1] read-only DISABLE_BOOTSEL_EXEC2 [0:0] read-only BOOT_FLAGS0_R1 Redundant copy of BOOT_FLAGS0 0x124 0x00000000 BOOT_FLAGS0_R1 [23:0] read-only BOOT_FLAGS0_R2 Redundant copy of BOOT_FLAGS0 0x128 0x00000000 BOOT_FLAGS0_R2 [23:0] read-only BOOT_FLAGS1 Disable/Enable boot paths/features in the RP2350 mask ROM. Disables always supersede enables. Enables are provided where there are other configurations in OTP that must be valid. (RBIT-3) 0x12C 0x00000000 DOUBLE_TAP Enable entering BOOTSEL mode via double-tap of the RUN/RSTn pin. Adds a significant delay to boot time, as configured by DOUBLE_TAP_DELAY. This functions by waiting at startup (i.e. following a reset) to see if a second reset is applied soon afterward. The second reset is detected by the bootrom with help of the POWMAN_CHIP_RESET_DOUBLE_TAP flag, which is not reset by the external reset pin, and the bootrom enters BOOTSEL mode (NSBOOT) to await further instruction over USB or UART. [19:19] read-only DOUBLE_TAP_DELAY Adjust how long to wait for a second reset when double tap BOOTSEL mode is enabled via DOUBLE_TAP. The minimum is 50 milliseconds, and each unit of this field adds an additional 50 milliseconds. For example, settings this field to its maximum value of 7 will cause the chip to wait for 400 milliseconds at boot to check for a second reset which requests entry to BOOTSEL mode. 200 milliseconds (DOUBLE_TAP_DELAY=3) is a good intermediate value. [18:16] read-only KEY_INVALID Mark a boot key as invalid, or prevent it from ever becoming valid. The bootrom will ignore any boot key marked as invalid during secure boot signature checks. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. When provisioning boot keys, it's recommended to mark any boot key slots you don't intend to use as KEY_INVALID, so that spurious keys can not be installed at a later time. [11:8] read-only KEY_VALID Mark each of the possible boot keys as valid. The bootrom will check signatures against all valid boot keys, and ignore invalid boot keys. Each bit in this field corresponds to one of the four 256-bit boot key hashes that may be stored in page 2 of the OTP. A KEY_VALID bit is ignored if the corresponding KEY_INVALID bit is set. Boot keys are considered valid only when KEY_VALID is set and KEY_INVALID is clear. Do not mark a boot key as KEY_VALID if it does not contain a valid SHA-256 hash of your secp256k1 public key. Verify keys after programming, before setting the KEY_VALID bits -- a boot key with uncorrectable ECC faults will render your device unbootable if secure boot is enabled. Do not enable secure boot without first installing a valid key. This will render your device unbootable. [3:0] read-only BOOT_FLAGS1_R1 Redundant copy of BOOT_FLAGS1 0x130 0x00000000 BOOT_FLAGS1_R1 [23:0] read-only BOOT_FLAGS1_R2 Redundant copy of BOOT_FLAGS1 0x134 0x00000000 BOOT_FLAGS1_R2 [23:0] read-only DEFAULT_BOOT_VERSION0 Default boot version thermometer counter, bits 23:0 (RBIT-3) 0x138 0x00000000 DEFAULT_BOOT_VERSION0 [23:0] read-only DEFAULT_BOOT_VERSION0_R1 Redundant copy of DEFAULT_BOOT_VERSION0 0x13C 0x00000000 DEFAULT_BOOT_VERSION0_R1 [23:0] read-only DEFAULT_BOOT_VERSION0_R2 Redundant copy of DEFAULT_BOOT_VERSION0 0x140 0x00000000 DEFAULT_BOOT_VERSION0_R2 [23:0] read-only DEFAULT_BOOT_VERSION1 Default boot version thermometer counter, bits 47:24 (RBIT-3) 0x144 0x00000000 DEFAULT_BOOT_VERSION1 [23:0] read-only DEFAULT_BOOT_VERSION1_R1 Redundant copy of DEFAULT_BOOT_VERSION1 0x148 0x00000000 DEFAULT_BOOT_VERSION1_R1 [23:0] read-only DEFAULT_BOOT_VERSION1_R2 Redundant copy of DEFAULT_BOOT_VERSION1 0x14C 0x00000000 DEFAULT_BOOT_VERSION1_R2 [23:0] read-only FLASH_DEVINFO Stores information about external flash device(s). (ECC) Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. 0x150 0x00000000 CS1_SIZE The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used. [15:12] read-only NONE 0 8K 1 16K 2 32K 3 64k 4 128K 5 256K 6 512K 7 1M 8 2M 9 4M 10 8M 11 16M 12 CS0_SIZE The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff). A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used. [11:8] read-only NONE 0 8K 1 16K 2 32K 3 64k 4 128K 5 256K 6 512K 7 1M 8 2M 9 4M 10 8M 11 16M 12 D8H_ERASE_SUPPORTED If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command. If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster. When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false. [7:7] read-only CS1_GPIO Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin. On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47. Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot). [5:0] read-only FLASH_PARTITION_SLOT_SIZE Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1) 0x154 0x00000000 FLASH_PARTITION_SLOT_SIZE [15:0] read-only BOOTSEL_LED_CFG Pin configuration for LED status, used by USB bootloader. (ECC) Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. 0x158 0x00000000 ACTIVELOW LED is active-low. (Default: active-high.) [8:8] read-only PIN GPIO index to use for bootloader activity LED. [5:0] read-only BOOTSEL_PLL_CFG Optional PLL configuration for BOOTSEL mode. (ECC) This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output. If no configuration is given, the crystal is assumed to be 12 MHz. The PLL frequency can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal frequency can be calculated as: XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.) Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed. 0x15C 0x00000000 REFDIV PLL reference divisor, minus one. Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs) [15:15] read-only POSTDIV2 PLL post-divide 2 divisor, in the range 1..7 inclusive. [14:12] read-only POSTDIV1 PLL post-divide 1 divisor, in the range 1..7 inclusive. [11:9] read-only FBDIV PLL feedback divisor, in the range 16..320 inclusive. [8:0] read-only BOOTSEL_XOSC_CFG Non-default crystal oscillator configuration for the USB bootloader. (ECC) These values may also be used by user code configuring the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed. 0x160 0x00000000 RANGE Value of the XOSC_CTRL_FREQ_RANGE register. [15:14] read-only 1_15MHZ 0 10_30MHZ 1 25_60MHZ 2 40_100MHZ 3 STARTUP Value of the XOSC_STARTUP register [13:0] read-only USB_BOOT_FLAGS USB boot specific feature flags (RBIT-3) 0x164 0x00000000 DP_DM_SWAP Swap DM/DP during USB boot, to support board layouts with mirrored USB routing (deliberate or accidental). [23:23] read-only WHITE_LABEL_ADDR_VALID valid flag for INFO_UF2_TXT_BOARD_ID_STRDEF entry of the USB_WHITE_LABEL struct (index 15) [22:22] read-only WL_INFO_UF2_TXT_BOARD_ID_STRDEF_VALID valid flag for the USB_WHITE_LABEL_ADDR field [15:15] read-only WL_INFO_UF2_TXT_MODEL_STRDEF_VALID valid flag for INFO_UF2_TXT_MODEL_STRDEF entry of the USB_WHITE_LABEL struct (index 14) [14:14] read-only WL_INDEX_HTM_REDIRECT_NAME_STRDEF_VALID valid flag for INDEX_HTM_REDIRECT_NAME_STRDEF entry of the USB_WHITE_LABEL struct (index 13) [13:13] read-only WL_INDEX_HTM_REDIRECT_URL_STRDEF_VALID valid flag for INDEX_HTM_REDIRECT_URL_STRDEF entry of the USB_WHITE_LABEL struct (index 12) [12:12] read-only WL_SCSI_INQUIRY_VERSION_STRDEF_VALID valid flag for SCSI_INQUIRY_VERSION_STRDEF entry of the USB_WHITE_LABEL struct (index 11) [11:11] read-only WL_SCSI_INQUIRY_PRODUCT_STRDEF_VALID valid flag for SCSI_INQUIRY_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 10) [10:10] read-only WL_SCSI_INQUIRY_VENDOR_STRDEF_VALID valid flag for SCSI_INQUIRY_VENDOR_STRDEF entry of the USB_WHITE_LABEL struct (index 9) [9:9] read-only WL_VOLUME_LABEL_STRDEF_VALID valid flag for VOLUME_LABEL_STRDEF entry of the USB_WHITE_LABEL struct (index 8) [8:8] read-only WL_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES_VALID valid flag for USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES entry of the USB_WHITE_LABEL struct (index 7) [7:7] read-only WL_USB_DEVICE_SERIAL_NUMBER_STRDEF_VALID valid flag for USB_DEVICE_SERIAL_NUMBER_STRDEF entry of the USB_WHITE_LABEL struct (index 6) [6:6] read-only WL_USB_DEVICE_PRODUCT_STRDEF_VALID valid flag for USB_DEVICE_PRODUCT_STRDEF entry of the USB_WHITE_LABEL struct (index 5) [5:5] read-only WL_USB_DEVICE_MANUFACTURER_STRDEF_VALID valid flag for USB_DEVICE_MANUFACTURER_STRDEF entry of the USB_WHITE_LABEL struct (index 4) [4:4] read-only WL_USB_DEVICE_LANG_ID_VALUE_VALID valid flag for USB_DEVICE_LANG_ID_VALUE entry of the USB_WHITE_LABEL struct (index 3) [3:3] read-only WL_USB_DEVICE_SERIAL_NUMBER_VALUE_VALID valid flag for USB_DEVICE_BCD_DEVICEVALUE entry of the USB_WHITE_LABEL struct (index 2) [2:2] read-only WL_USB_DEVICE_PID_VALUE_VALID valid flag for USB_DEVICE_PID_VALUE entry of the USB_WHITE_LABEL struct (index 1) [1:1] read-only WL_USB_DEVICE_VID_VALUE_VALID valid flag for USB_DEVICE_VID_VALUE entry of the USB_WHITE_LABEL struct (index 0) [0:0] read-only USB_BOOT_FLAGS_R1 Redundant copy of USB_BOOT_FLAGS 0x168 0x00000000 USB_BOOT_FLAGS_R1 [23:0] read-only USB_BOOT_FLAGS_R2 Redundant copy of USB_BOOT_FLAGS 0x16C 0x00000000 USB_BOOT_FLAGS_R2 [23:0] read-only USB_WHITE_LABEL_ADDR Row index of the USB_WHITE_LABEL structure within OTP (ECC) The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC). The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value. The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte. In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom. Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero. Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used. The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index): 0x170 0x00000000 USB_WHITE_LABEL_ADDR [15:0] read-only INDEX_USB_DEVICE_VID_VALUE 0 INDEX_USB_DEVICE_PID_VALUE 1 INDEX_USB_DEVICE_BCD_DEVICE_VALUE 2 INDEX_USB_DEVICE_LANG_ID_VALUE 3 INDEX_USB_DEVICE_MANUFACTURER_STRDEF 4 INDEX_USB_DEVICE_PRODUCT_STRDEF 5 INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF 6 INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES 7 INDEX_VOLUME_LABEL_STRDEF 8 INDEX_SCSI_INQUIRY_VENDOR_STRDEF 9 INDEX_SCSI_INQUIRY_PRODUCT_STRDEF 10 INDEX_SCSI_INQUIRY_VERSION_STRDEF 11 INDEX_INDEX_HTM_REDIRECT_URL_STRDEF 12 INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF 13 INDEX_INFO_UF2_TXT_MODEL_STRDEF 14 INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF 15 OTPBOOT_SRC OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected. This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window. 0x178 0x00000000 OTPBOOT_SRC [15:0] read-only OTPBOOT_LEN Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits). 0x17C 0x00000000 OTPBOOT_LEN [15:0] read-only OTPBOOT_DST0 Bits 15:0 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. 0x180 0x00000000 OTPBOOT_DST0 [15:0] read-only OTPBOOT_DST1 Bits 31:16 of the OTP boot image load destination (and entry point). (ECC) This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned. 0x184 0x00000000 OTPBOOT_DST1 [15:0] read-only BOOTKEY0_0 Bits 15:0 of SHA-256 hash of boot key 0 (ECC) 0x200 0x00000000 BOOTKEY0_0 [15:0] read-only BOOTKEY0_1 Bits 31:16 of SHA-256 hash of boot key 0 (ECC) 0x204 0x00000000 BOOTKEY0_1 [15:0] read-only BOOTKEY0_2 Bits 47:32 of SHA-256 hash of boot key 0 (ECC) 0x208 0x00000000 BOOTKEY0_2 [15:0] read-only BOOTKEY0_3 Bits 63:48 of SHA-256 hash of boot key 0 (ECC) 0x20C 0x00000000 BOOTKEY0_3 [15:0] read-only BOOTKEY0_4 Bits 79:64 of SHA-256 hash of boot key 0 (ECC) 0x210 0x00000000 BOOTKEY0_4 [15:0] read-only BOOTKEY0_5 Bits 95:80 of SHA-256 hash of boot key 0 (ECC) 0x214 0x00000000 BOOTKEY0_5 [15:0] read-only BOOTKEY0_6 Bits 111:96 of SHA-256 hash of boot key 0 (ECC) 0x218 0x00000000 BOOTKEY0_6 [15:0] read-only BOOTKEY0_7 Bits 127:112 of SHA-256 hash of boot key 0 (ECC) 0x21C 0x00000000 BOOTKEY0_7 [15:0] read-only BOOTKEY0_8 Bits 143:128 of SHA-256 hash of boot key 0 (ECC) 0x220 0x00000000 BOOTKEY0_8 [15:0] read-only BOOTKEY0_9 Bits 159:144 of SHA-256 hash of boot key 0 (ECC) 0x224 0x00000000 BOOTKEY0_9 [15:0] read-only BOOTKEY0_10 Bits 175:160 of SHA-256 hash of boot key 0 (ECC) 0x228 0x00000000 BOOTKEY0_10 [15:0] read-only BOOTKEY0_11 Bits 191:176 of SHA-256 hash of boot key 0 (ECC) 0x22C 0x00000000 BOOTKEY0_11 [15:0] read-only BOOTKEY0_12 Bits 207:192 of SHA-256 hash of boot key 0 (ECC) 0x230 0x00000000 BOOTKEY0_12 [15:0] read-only BOOTKEY0_13 Bits 223:208 of SHA-256 hash of boot key 0 (ECC) 0x234 0x00000000 BOOTKEY0_13 [15:0] read-only BOOTKEY0_14 Bits 239:224 of SHA-256 hash of boot key 0 (ECC) 0x238 0x00000000 BOOTKEY0_14 [15:0] read-only BOOTKEY0_15 Bits 255:240 of SHA-256 hash of boot key 0 (ECC) 0x23C 0x00000000 BOOTKEY0_15 [15:0] read-only BOOTKEY1_0 Bits 15:0 of SHA-256 hash of boot key 1 (ECC) 0x240 0x00000000 BOOTKEY1_0 [15:0] read-only BOOTKEY1_1 Bits 31:16 of SHA-256 hash of boot key 1 (ECC) 0x244 0x00000000 BOOTKEY1_1 [15:0] read-only BOOTKEY1_2 Bits 47:32 of SHA-256 hash of boot key 1 (ECC) 0x248 0x00000000 BOOTKEY1_2 [15:0] read-only BOOTKEY1_3 Bits 63:48 of SHA-256 hash of boot key 1 (ECC) 0x24C 0x00000000 BOOTKEY1_3 [15:0] read-only BOOTKEY1_4 Bits 79:64 of SHA-256 hash of boot key 1 (ECC) 0x250 0x00000000 BOOTKEY1_4 [15:0] read-only BOOTKEY1_5 Bits 95:80 of SHA-256 hash of boot key 1 (ECC) 0x254 0x00000000 BOOTKEY1_5 [15:0] read-only BOOTKEY1_6 Bits 111:96 of SHA-256 hash of boot key 1 (ECC) 0x258 0x00000000 BOOTKEY1_6 [15:0] read-only BOOTKEY1_7 Bits 127:112 of SHA-256 hash of boot key 1 (ECC) 0x25C 0x00000000 BOOTKEY1_7 [15:0] read-only BOOTKEY1_8 Bits 143:128 of SHA-256 hash of boot key 1 (ECC) 0x260 0x00000000 BOOTKEY1_8 [15:0] read-only BOOTKEY1_9 Bits 159:144 of SHA-256 hash of boot key 1 (ECC) 0x264 0x00000000 BOOTKEY1_9 [15:0] read-only BOOTKEY1_10 Bits 175:160 of SHA-256 hash of boot key 1 (ECC) 0x268 0x00000000 BOOTKEY1_10 [15:0] read-only BOOTKEY1_11 Bits 191:176 of SHA-256 hash of boot key 1 (ECC) 0x26C 0x00000000 BOOTKEY1_11 [15:0] read-only BOOTKEY1_12 Bits 207:192 of SHA-256 hash of boot key 1 (ECC) 0x270 0x00000000 BOOTKEY1_12 [15:0] read-only BOOTKEY1_13 Bits 223:208 of SHA-256 hash of boot key 1 (ECC) 0x274 0x00000000 BOOTKEY1_13 [15:0] read-only BOOTKEY1_14 Bits 239:224 of SHA-256 hash of boot key 1 (ECC) 0x278 0x00000000 BOOTKEY1_14 [15:0] read-only BOOTKEY1_15 Bits 255:240 of SHA-256 hash of boot key 1 (ECC) 0x27C 0x00000000 BOOTKEY1_15 [15:0] read-only BOOTKEY2_0 Bits 15:0 of SHA-256 hash of boot key 2 (ECC) 0x280 0x00000000 BOOTKEY2_0 [15:0] read-only BOOTKEY2_1 Bits 31:16 of SHA-256 hash of boot key 2 (ECC) 0x284 0x00000000 BOOTKEY2_1 [15:0] read-only BOOTKEY2_2 Bits 47:32 of SHA-256 hash of boot key 2 (ECC) 0x288 0x00000000 BOOTKEY2_2 [15:0] read-only BOOTKEY2_3 Bits 63:48 of SHA-256 hash of boot key 2 (ECC) 0x28C 0x00000000 BOOTKEY2_3 [15:0] read-only BOOTKEY2_4 Bits 79:64 of SHA-256 hash of boot key 2 (ECC) 0x290 0x00000000 BOOTKEY2_4 [15:0] read-only BOOTKEY2_5 Bits 95:80 of SHA-256 hash of boot key 2 (ECC) 0x294 0x00000000 BOOTKEY2_5 [15:0] read-only BOOTKEY2_6 Bits 111:96 of SHA-256 hash of boot key 2 (ECC) 0x298 0x00000000 BOOTKEY2_6 [15:0] read-only BOOTKEY2_7 Bits 127:112 of SHA-256 hash of boot key 2 (ECC) 0x29C 0x00000000 BOOTKEY2_7 [15:0] read-only BOOTKEY2_8 Bits 143:128 of SHA-256 hash of boot key 2 (ECC) 0x2A0 0x00000000 BOOTKEY2_8 [15:0] read-only BOOTKEY2_9 Bits 159:144 of SHA-256 hash of boot key 2 (ECC) 0x2A4 0x00000000 BOOTKEY2_9 [15:0] read-only BOOTKEY2_10 Bits 175:160 of SHA-256 hash of boot key 2 (ECC) 0x2A8 0x00000000 BOOTKEY2_10 [15:0] read-only BOOTKEY2_11 Bits 191:176 of SHA-256 hash of boot key 2 (ECC) 0x2AC 0x00000000 BOOTKEY2_11 [15:0] read-only BOOTKEY2_12 Bits 207:192 of SHA-256 hash of boot key 2 (ECC) 0x2B0 0x00000000 BOOTKEY2_12 [15:0] read-only BOOTKEY2_13 Bits 223:208 of SHA-256 hash of boot key 2 (ECC) 0x2B4 0x00000000 BOOTKEY2_13 [15:0] read-only BOOTKEY2_14 Bits 239:224 of SHA-256 hash of boot key 2 (ECC) 0x2B8 0x00000000 BOOTKEY2_14 [15:0] read-only BOOTKEY2_15 Bits 255:240 of SHA-256 hash of boot key 2 (ECC) 0x2BC 0x00000000 BOOTKEY2_15 [15:0] read-only BOOTKEY3_0 Bits 15:0 of SHA-256 hash of boot key 3 (ECC) 0x2C0 0x00000000 BOOTKEY3_0 [15:0] read-only BOOTKEY3_1 Bits 31:16 of SHA-256 hash of boot key 3 (ECC) 0x2C4 0x00000000 BOOTKEY3_1 [15:0] read-only BOOTKEY3_2 Bits 47:32 of SHA-256 hash of boot key 3 (ECC) 0x2C8 0x00000000 BOOTKEY3_2 [15:0] read-only BOOTKEY3_3 Bits 63:48 of SHA-256 hash of boot key 3 (ECC) 0x2CC 0x00000000 BOOTKEY3_3 [15:0] read-only BOOTKEY3_4 Bits 79:64 of SHA-256 hash of boot key 3 (ECC) 0x2D0 0x00000000 BOOTKEY3_4 [15:0] read-only BOOTKEY3_5 Bits 95:80 of SHA-256 hash of boot key 3 (ECC) 0x2D4 0x00000000 BOOTKEY3_5 [15:0] read-only BOOTKEY3_6 Bits 111:96 of SHA-256 hash of boot key 3 (ECC) 0x2D8 0x00000000 BOOTKEY3_6 [15:0] read-only BOOTKEY3_7 Bits 127:112 of SHA-256 hash of boot key 3 (ECC) 0x2DC 0x00000000 BOOTKEY3_7 [15:0] read-only BOOTKEY3_8 Bits 143:128 of SHA-256 hash of boot key 3 (ECC) 0x2E0 0x00000000 BOOTKEY3_8 [15:0] read-only BOOTKEY3_9 Bits 159:144 of SHA-256 hash of boot key 3 (ECC) 0x2E4 0x00000000 BOOTKEY3_9 [15:0] read-only BOOTKEY3_10 Bits 175:160 of SHA-256 hash of boot key 3 (ECC) 0x2E8 0x00000000 BOOTKEY3_10 [15:0] read-only BOOTKEY3_11 Bits 191:176 of SHA-256 hash of boot key 3 (ECC) 0x2EC 0x00000000 BOOTKEY3_11 [15:0] read-only BOOTKEY3_12 Bits 207:192 of SHA-256 hash of boot key 3 (ECC) 0x2F0 0x00000000 BOOTKEY3_12 [15:0] read-only BOOTKEY3_13 Bits 223:208 of SHA-256 hash of boot key 3 (ECC) 0x2F4 0x00000000 BOOTKEY3_13 [15:0] read-only BOOTKEY3_14 Bits 239:224 of SHA-256 hash of boot key 3 (ECC) 0x2F8 0x00000000 BOOTKEY3_14 [15:0] read-only BOOTKEY3_15 Bits 255:240 of SHA-256 hash of boot key 3 (ECC) 0x2FC 0x00000000 BOOTKEY3_15 [15:0] read-only KEY1_0 Bits 15:0 of OTP access key 1 (ECC) 0x3D20 0x00000000 KEY1_0 [15:0] read-only KEY1_1 Bits 31:16 of OTP access key 1 (ECC) 0x3D24 0x00000000 KEY1_1 [15:0] read-only KEY1_2 Bits 47:32 of OTP access key 1 (ECC) 0x3D28 0x00000000 KEY1_2 [15:0] read-only KEY1_3 Bits 63:48 of OTP access key 1 (ECC) 0x3D2C 0x00000000 KEY1_3 [15:0] read-only KEY1_4 Bits 79:64 of OTP access key 1 (ECC) 0x3D30 0x00000000 KEY1_4 [15:0] read-only KEY1_5 Bits 95:80 of OTP access key 1 (ECC) 0x3D34 0x00000000 KEY1_5 [15:0] read-only KEY1_6 Bits 111:96 of OTP access key 1 (ECC) 0x3D38 0x00000000 KEY1_6 [15:0] read-only KEY1_7 Bits 127:112 of OTP access key 1 (ECC) 0x3D3C 0x00000000 KEY1_7 [15:0] read-only KEY2_0 Bits 15:0 of OTP access key 2 (ECC) 0x3D40 0x00000000 KEY2_0 [15:0] read-only KEY2_1 Bits 31:16 of OTP access key 2 (ECC) 0x3D44 0x00000000 KEY2_1 [15:0] read-only KEY2_2 Bits 47:32 of OTP access key 2 (ECC) 0x3D48 0x00000000 KEY2_2 [15:0] read-only KEY2_3 Bits 63:48 of OTP access key 2 (ECC) 0x3D4C 0x00000000 KEY2_3 [15:0] read-only KEY2_4 Bits 79:64 of OTP access key 2 (ECC) 0x3D50 0x00000000 KEY2_4 [15:0] read-only KEY2_5 Bits 95:80 of OTP access key 2 (ECC) 0x3D54 0x00000000 KEY2_5 [15:0] read-only KEY2_6 Bits 111:96 of OTP access key 2 (ECC) 0x3D58 0x00000000 KEY2_6 [15:0] read-only KEY2_7 Bits 127:112 of OTP access key 2 (ECC) 0x3D5C 0x00000000 KEY2_7 [15:0] read-only KEY3_0 Bits 15:0 of OTP access key 3 (ECC) 0x3D60 0x00000000 KEY3_0 [15:0] read-only KEY3_1 Bits 31:16 of OTP access key 3 (ECC) 0x3D64 0x00000000 KEY3_1 [15:0] read-only KEY3_2 Bits 47:32 of OTP access key 3 (ECC) 0x3D68 0x00000000 KEY3_2 [15:0] read-only KEY3_3 Bits 63:48 of OTP access key 3 (ECC) 0x3D6C 0x00000000 KEY3_3 [15:0] read-only KEY3_4 Bits 79:64 of OTP access key 3 (ECC) 0x3D70 0x00000000 KEY3_4 [15:0] read-only KEY3_5 Bits 95:80 of OTP access key 3 (ECC) 0x3D74 0x00000000 KEY3_5 [15:0] read-only KEY3_6 Bits 111:96 of OTP access key 3 (ECC) 0x3D78 0x00000000 KEY3_6 [15:0] read-only KEY3_7 Bits 127:112 of OTP access key 3 (ECC) 0x3D7C 0x00000000 KEY3_7 [15:0] read-only KEY4_0 Bits 15:0 of OTP access key 4 (ECC) 0x3D80 0x00000000 KEY4_0 [15:0] read-only KEY4_1 Bits 31:16 of OTP access key 4 (ECC) 0x3D84 0x00000000 KEY4_1 [15:0] read-only KEY4_2 Bits 47:32 of OTP access key 4 (ECC) 0x3D88 0x00000000 KEY4_2 [15:0] read-only KEY4_3 Bits 63:48 of OTP access key 4 (ECC) 0x3D8C 0x00000000 KEY4_3 [15:0] read-only KEY4_4 Bits 79:64 of OTP access key 4 (ECC) 0x3D90 0x00000000 KEY4_4 [15:0] read-only KEY4_5 Bits 95:80 of OTP access key 4 (ECC) 0x3D94 0x00000000 KEY4_5 [15:0] read-only KEY4_6 Bits 111:96 of OTP access key 4 (ECC) 0x3D98 0x00000000 KEY4_6 [15:0] read-only KEY4_7 Bits 127:112 of OTP access key 4 (ECC) 0x3D9C 0x00000000 KEY4_7 [15:0] read-only KEY5_0 Bits 15:0 of OTP access key 5 (ECC) 0x3DA0 0x00000000 KEY5_0 [15:0] read-only KEY5_1 Bits 31:16 of OTP access key 5 (ECC) 0x3DA4 0x00000000 KEY5_1 [15:0] read-only KEY5_2 Bits 47:32 of OTP access key 5 (ECC) 0x3DA8 0x00000000 KEY5_2 [15:0] read-only KEY5_3 Bits 63:48 of OTP access key 5 (ECC) 0x3DAC 0x00000000 KEY5_3 [15:0] read-only KEY5_4 Bits 79:64 of OTP access key 5 (ECC) 0x3DB0 0x00000000 KEY5_4 [15:0] read-only KEY5_5 Bits 95:80 of OTP access key 5 (ECC) 0x3DB4 0x00000000 KEY5_5 [15:0] read-only KEY5_6 Bits 111:96 of OTP access key 5 (ECC) 0x3DB8 0x00000000 KEY5_6 [15:0] read-only KEY5_7 Bits 127:112 of OTP access key 5 (ECC) 0x3DBC 0x00000000 KEY5_7 [15:0] read-only KEY6_0 Bits 15:0 of OTP access key 6 (ECC) 0x3DC0 0x00000000 KEY6_0 [15:0] read-only KEY6_1 Bits 31:16 of OTP access key 6 (ECC) 0x3DC4 0x00000000 KEY6_1 [15:0] read-only KEY6_2 Bits 47:32 of OTP access key 6 (ECC) 0x3DC8 0x00000000 KEY6_2 [15:0] read-only KEY6_3 Bits 63:48 of OTP access key 6 (ECC) 0x3DCC 0x00000000 KEY6_3 [15:0] read-only KEY6_4 Bits 79:64 of OTP access key 6 (ECC) 0x3DD0 0x00000000 KEY6_4 [15:0] read-only KEY6_5 Bits 95:80 of OTP access key 6 (ECC) 0x3DD4 0x00000000 KEY6_5 [15:0] read-only KEY6_6 Bits 111:96 of OTP access key 6 (ECC) 0x3DD8 0x00000000 KEY6_6 [15:0] read-only KEY6_7 Bits 127:112 of OTP access key 6 (ECC) 0x3DDC 0x00000000 KEY6_7 [15:0] read-only KEY1_VALID Valid flag for key 1. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DE4 0x00000000 VALID_R2 Redundant copy of VALID, with 3-way majority vote [16:16] read-only VALID_R1 Redundant copy of VALID, with 3-way majority vote [8:8] read-only VALID [0:0] read-only KEY2_VALID Valid flag for key 2. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DE8 0x00000000 VALID_R2 Redundant copy of VALID, with 3-way majority vote [16:16] read-only VALID_R1 Redundant copy of VALID, with 3-way majority vote [8:8] read-only VALID [0:0] read-only KEY3_VALID Valid flag for key 3. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DEC 0x00000000 VALID_R2 Redundant copy of VALID, with 3-way majority vote [16:16] read-only VALID_R1 Redundant copy of VALID, with 3-way majority vote [8:8] read-only VALID [0:0] read-only KEY4_VALID Valid flag for key 4. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DF0 0x00000000 VALID_R2 Redundant copy of VALID, with 3-way majority vote [16:16] read-only VALID_R1 Redundant copy of VALID, with 3-way majority vote [8:8] read-only VALID [0:0] read-only KEY5_VALID Valid flag for key 5. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DF4 0x00000000 VALID_R2 Redundant copy of VALID, with 3-way majority vote [16:16] read-only VALID_R1 Redundant copy of VALID, with 3-way majority vote [8:8] read-only VALID [0:0] read-only KEY6_VALID Valid flag for key 6. Once the valid flag is set, the key can no longer be read or written, and becomes a valid fixed key for protecting OTP pages. 0x3DF8 0x00000000 VALID_R2 Redundant copy of VALID, with 3-way majority vote [16:16] read-only VALID_R1 Redundant copy of VALID, with 3-way majority vote [8:8] read-only VALID [0:0] read-only PAGE0_LOCK0 Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E00 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE0_LOCK1 Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E04 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE1_LOCK0 Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E08 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE1_LOCK1 Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E0C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE2_LOCK0 Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E10 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE2_LOCK1 Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E14 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE3_LOCK0 Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E18 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE3_LOCK1 Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E1C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE4_LOCK0 Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E20 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE4_LOCK1 Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E24 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE5_LOCK0 Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E28 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE5_LOCK1 Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E2C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE6_LOCK0 Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E30 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE6_LOCK1 Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E34 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE7_LOCK0 Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E38 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE7_LOCK1 Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E3C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE8_LOCK0 Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E40 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE8_LOCK1 Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E44 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE9_LOCK0 Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E48 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE9_LOCK1 Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E4C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE10_LOCK0 Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E50 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE10_LOCK1 Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E54 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE11_LOCK0 Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E58 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE11_LOCK1 Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E5C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE12_LOCK0 Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E60 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE12_LOCK1 Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E64 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE13_LOCK0 Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E68 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE13_LOCK1 Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E6C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE14_LOCK0 Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E70 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE14_LOCK1 Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E74 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE15_LOCK0 Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E78 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE15_LOCK1 Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E7C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE16_LOCK0 Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E80 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE16_LOCK1 Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E84 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE17_LOCK0 Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E88 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE17_LOCK1 Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E8C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE18_LOCK0 Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E90 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE18_LOCK1 Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E94 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE19_LOCK0 Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E98 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE19_LOCK1 Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3E9C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE20_LOCK0 Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EA0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE20_LOCK1 Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EA4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE21_LOCK0 Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EA8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE21_LOCK1 Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EAC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE22_LOCK0 Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EB0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE22_LOCK1 Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EB4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE23_LOCK0 Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EB8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE23_LOCK1 Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EBC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE24_LOCK0 Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EC0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE24_LOCK1 Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EC4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE25_LOCK0 Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EC8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE25_LOCK1 Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3ECC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE26_LOCK0 Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3ED0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE26_LOCK1 Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3ED4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE27_LOCK0 Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3ED8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE27_LOCK1 Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EDC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE28_LOCK0 Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EE0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE28_LOCK1 Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EE4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE29_LOCK0 Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EE8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE29_LOCK1 Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EEC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE30_LOCK0 Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EF0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE30_LOCK1 Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EF4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE31_LOCK0 Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EF8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE31_LOCK1 Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3EFC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE32_LOCK0 Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F00 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE32_LOCK1 Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F04 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE33_LOCK0 Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F08 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE33_LOCK1 Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F0C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE34_LOCK0 Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F10 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE34_LOCK1 Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F14 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE35_LOCK0 Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F18 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE35_LOCK1 Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F1C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE36_LOCK0 Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F20 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE36_LOCK1 Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F24 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE37_LOCK0 Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F28 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE37_LOCK1 Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F2C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE38_LOCK0 Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F30 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE38_LOCK1 Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F34 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE39_LOCK0 Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F38 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE39_LOCK1 Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F3C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE40_LOCK0 Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F40 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE40_LOCK1 Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F44 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE41_LOCK0 Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F48 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE41_LOCK1 Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F4C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE42_LOCK0 Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F50 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE42_LOCK1 Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F54 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE43_LOCK0 Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F58 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE43_LOCK1 Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F5C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE44_LOCK0 Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F60 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE44_LOCK1 Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F64 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE45_LOCK0 Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F68 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE45_LOCK1 Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F6C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE46_LOCK0 Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F70 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE46_LOCK1 Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F74 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE47_LOCK0 Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F78 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE47_LOCK1 Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F7C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE48_LOCK0 Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F80 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE48_LOCK1 Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F84 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE49_LOCK0 Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F88 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE49_LOCK1 Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F8C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE50_LOCK0 Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F90 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE50_LOCK1 Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F94 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE51_LOCK0 Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F98 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE51_LOCK1 Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3F9C 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE52_LOCK0 Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FA0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE52_LOCK1 Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FA4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE53_LOCK0 Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FA8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE53_LOCK1 Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FAC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE54_LOCK0 Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FB0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE54_LOCK1 Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FB4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE55_LOCK0 Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FB8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE55_LOCK1 Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FBC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE56_LOCK0 Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FC0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE56_LOCK1 Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FC4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE57_LOCK0 Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FC8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE57_LOCK1 Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FCC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE58_LOCK0 Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FD0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE58_LOCK1 Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FD4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE59_LOCK0 Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FD8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE59_LOCK1 Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FDC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE60_LOCK0 Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FE0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE60_LOCK1 Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FE4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE61_LOCK0 Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FE8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE61_LOCK1 Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FEC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE62_LOCK0 Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FF0 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE62_LOCK1 Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FF4 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 PAGE63_LOCK0 Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FF8 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only RMA Decommission for RMA of a suspected faulty device. This re-enables the factory test JTAG interface, and makes pages 3 through 61 of the OTP permanently inaccessible. [7:7] read-only NO_KEY_STATE State when at least one key is registered for this page and no matching key has been entered. [6:6] read-only read_only 0 inaccessible 1 KEY_R Index 1-6 of a hardware key which must be entered to grant read access, or 0 if no such key is required. [5:3] read-only KEY_W Index 1-6 of a hardware key which must be entered to grant write access, or 0 if no such key is required. [2:0] read-only PAGE63_LOCK1 Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). Locks are stored with 3-way majority vote encoding, so that bits can be set independently. This OTP location is always readable, and is write-protected by its own permissions. 0x3FFC 0x00000000 R2 Redundant copy of bits 7:0 [23:16] read-only R1 Redundant copy of bits 7:0 [15:8] read-only LOCK_BL Dummy lock bits reserved for bootloaders (including the RP2350 USB bootloader) to store their own OTP access permissions. No hardware effect, and no corresponding SW_LOCKx registers. [5:4] read-only read_write Bootloader permits user reads and writes to this page 0 read_only Bootloader permits user reads of this page 1 reserved Do not use. Behaves the same as INACCESSIBLE 2 inaccessible Bootloader does not permit user access to this page 3 LOCK_NS Lock state for Non-secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. Note that READ_WRITE and READ_ONLY are equivalent in hardware, as the SBPI programming interface is not accessible to Non-secure software. However, Secure software may check these bits to apply write permissions to a Non-secure OTP programming API. [3:2] read-only read_write Page can be read by Non-secure software, and Secure software may permit Non-secure writes. 0 read_only Page can be read by Non-secure software 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Non-secure software. 3 LOCK_S Lock state for Secure accesses to this page. Thermometer-coded, so lock state can be advanced permanently from any state to any less-permissive state by programming OTP. Software can also advance the lock state temporarily (until next OTP reset) using the SW_LOCKx registers. [1:0] read-only read_write Page is fully accessible by Secure software. 0 read_only Page can be read by Secure software, but can not be written. 1 reserved Do not use. Behaves the same as INACCESSIBLE. 2 inaccessible Page can not be accessed by Secure software. 3 TBMAN For managing simulation testbenches 0x40160000 0x0 0x4 registers PLATFORM Indicates the type of platform in use 0x0 0x00000001 HDLSIM Indicates the platform is a simulation [2:2] read-only FPGA Indicates the platform is an FPGA [1:1] read-only ASIC Indicates the platform is an ASIC [0:0] read-only USB_DPRAM DPRAM layout for USB device. 0x50100000 0x0 0x100 registers SETUP_PACKET_LOW Bytes 0-3 of the SETUP packet from the host. 0x0 0x00000000 WVALUE [31:16] read-write BREQUEST [15:8] read-write BMREQUESTTYPE [7:0] read-write SETUP_PACKET_HIGH Bytes 4-7 of the setup packet from the host. 0x4 0x00000000 WLENGTH [31:16] read-write WINDEX [15:0] read-write 30 0x4 0-29 EP_CONTROL%s TODO 0x8 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write 32 0x4 0-31 EP_BUFFER_CONTROL%s TODO 0x80 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 1. [9:0] read-write