# RISC-V

`rt` requires the A extension (both Zalrsc and Zaamo) as well as the Zicsr
extension. The M and Zbb extensions improve performance in several places but
are not required.

`rt_trap_handler` must be used to handle the top-level trap (mcause.Interrupt
== 0), and it will invoke a handler from `rt_trap_vector`, which must be
provided by the application. The environment call handler fields in
`rt_trap_vector` must be set to `rt_ecall_handler`. Declarations for these
symbols are provided in [`<rt/arch/trap.h>`](include/rt/arch/trap.h).

If vectored asynchronous interrupts are not enabled, then `mtvec` may be set
directly to `rt_trap_handler`, otherwise, the instruction located at the
`mtvec.BASE` address must be a jump to `rt_trap_handler`, and other
instructions at `mtvec.BASE + 4*cause` should be jumps to the appropriate
handler for each interrupt type.

`rt_msi_handler` is provided for handling the machine software interrupt, which
is used for asynchronous system calls made by other interrupts. An `msi.h`
header must be on the include path and define a function `msi_pend` for
triggering the MSI, as well as an `MSIP_BASE` constant for clearing the MSI
from assembly. An implementation of this header for the Espressif ESP32 RISC-V
cores is provided in [`esp32/msi.h`](esp32/msi.h). When using one of these
cores, add `arch/riscv/esp32` to your include path.