# rtlicious

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[Nom](https://crates.io/crates/nom)-based parser for [Yosys](https://yosyshq.readthedocs.io/projects/yosys/en/manual-rewrite/index.html) RTLIL [text representation](https://yosyshq.readthedocs.io/projects/yosys/en/manual-rewrite/yosys_internals/formats/rtlil_text.html).

## Usage:

```rust
    use rtlicious;
    let src =
    r#"module \test
    wire $a
    end
    "#;
    let design = rtlicious::parse(src).unwrap();
    assert_eq!(design.modules().len(), 1);
    dbg!({:?}, design);
```
```text
> Design {
    autoidx: None,
    modules: {
        "test": Module {
            attributes: {},
            parameters: {},
            wires: {
                "a": Wire {
                    width: 1,
                    offset: 0,
                    input: false,
                    output: false,
                    inout: false,
                    upto: false,
                    signed: false,
                    attributes: {},
                },
            },
            memories: {},
            cells: {},
            processes: {},
            connections: [],
        },
    },
}
```