[package]
name = "rust-hdl"
version = "0.46.0"
edition = "2021"
license = "MIT"
description = "Write firmware for FPGAs in Rust"
homepage = "https://rust-hdl.org"
repository = "https://github.com/samitbasu/rust-hdl"
keywords = ["fpga", "verilog", "hardware"]
authors = ["Samit Basu <basu.samit@gmail.com>"]

[dependencies]
rust-hdl-macros = { version = "0.46.0", path = "../rust-hdl-macros" }
rust-hdl-core = { version = "0.46.0", path = "../rust-hdl-core" }
rust-hdl-sim = { version = "0.46.0", path = "../rust-hdl-sim" }
rust-hdl-hls = { version = "0.46.0", path = "../rust-hdl-hls" }
rust-hdl-widgets = { version = "0.46.0", path = "../rust-hdl-widgets" }
rust-hdl-fpga-support = { version = "0.46.0", path = "../rust-hdl-fpga-support", optional = true }
crossbeam = "0.8.1"
num-bigint = "0.4.0"
num-traits = "0.2.14"
vcd = "0.6.1"
evalexpr = "6.3.0"
regex = "1.5.4"
array-init = "2.0.0"
rand = "0.8"
petgraph = "0.6.0"
embed-doc-image = "0.1.4"
svg = "0.10.0"
substring = "^1"
anyhow = "^1"

seq-macro = "0.3.1"

[features]
fpga = ["dep:rust-hdl-fpga-support"]