* Safe - have Rust check the validity of your firmware with
 strongly typed interfaces at **compile** time, as well as at
 run time, synthesis, and on the device.
 * Fast - Run simulations of your designs straight from your
 Rust code, with pretty good simulation performance.
 * Readable - RustHDL outputs Verilog code for synthesis and
 implementation, and goes through some effort to make sure that
 code is readable and understandable, in case you need to resolve
 timing issues or other conflicts.
 * Reusable - RustHDL supports templated firmware for parametric
 use, as well as a simple composition model based on structs.
 * Batteries Included - RustHDL includes a set of basic firmware
 widgets that provide FIFOs, RAMs and ROMs, Flip flops, SPI components,
 PWMs etc, so you can get started quickly.
 * Free - Although you can use RustHDL to wrap existing IP cores,
 all of the RustHDL code and firmware is open source and free to use
(as in speech and beer).