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[package]
edition = "2021"
name = "rust-hdl-ok-core"
version = "0.46.0"
authors = ["Samit Basu <sbasu.samit@gmail.com>"]
description = "Generic support code for OpalKelly based FPGA modules that use the FrontPanel HDL interface"
homepage = "https://rust-hdl.org"
keywords = [
    "fpga",
    "verilog",
    "hardware",
]
license = "MIT"
repository = "https://github.com/samitbasu/rust-hdl"
resolver = "1"

[dependencies.rand]
version = "0.8.5"

[dependencies.regex]
version = "1.5.4"

[dependencies.rust-hdl-core]
version = "0.46.0"

[dependencies.rust-hdl-hls]
version = "0.46.0"

[dependencies.rust-hdl-ok-frontpanel-sys]
version = "0.46.0"

[dependencies.rust-hdl-sim]
version = "0.46.0"

[dependencies.rust-hdl-widgets]
version = "0.46.0"