[package]
name = "rust-hdl-ok-core"
version = "0.46.0"
edition = "2021"
license = "MIT"
description = "Generic support code for OpalKelly based FPGA modules that use the FrontPanel HDL interface"
homepage = "https://rust-hdl.org"
repository = "https://github.com/samitbasu/rust-hdl"
keywords = ["fpga", "verilog", "hardware"]
authors = ["Samit Basu <sbasu.samit@gmail.com>"]

# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html

[dependencies]
rust-hdl-core = { version = "0.46.0", path = "../rust-hdl-core" }
rust-hdl-hls = { version = "0.46.0", path = "../rust-hdl-hls" }
rust-hdl-sim = { version = "0.46.0", path = "../rust-hdl-sim" }
rust-hdl-widgets = { version = "0.46.0", path = "../rust-hdl-widgets" }
rust-hdl-ok-frontpanel-sys = { version = "0.46.0", path = "../rust-hdl-ok-frontpanel-sys" }
regex = "1.5.4"
rand = "0.8.5"