[package]
name = "rust-hdl-test-core"
version = "0.1.0"
edition = "2018"
license = "MIT"
description = "Test infrastructure for the RustHDL crate."
homepage = "https://rusthdl.org"
repository = "https://github.com/SmithsDigitalForge/rust-hdl"
keywords = ["fpga", "verilog", "hardware"]
authors = ["Samit Basu <samit.basu@smiths.com>"]


[dependencies]
rust-hdl-core = "^0.1"
rust-hdl-macros = "^0.1"
rust-hdl-widgets = "^0.1"
rust-hdl-yosys-synth = "^0.1"
rust-hdl-sim-chips = "^0.1"
num-bigint = "0.4.0"
rand = "0.8.4"
array-init = "2.0.0"
regex = "^1"