[package]
name = "rust-hdl-test-ok-common"
version = "0.1.0"
edition = "2018"
license = "MIT"
description = "OpalKelly FrontPanel test support components of the RustHDL crate."
homepage = "https://rusthdl.org"
repository = "https://github.com/SmithsDigitalForge/rust-hdl"
keywords = ["fpga", "verilog", "hardware"]
authors = ["Samit Basu <samit.basu@smiths.com>"]

[dependencies]
rust-hdl-core = "^0.1"
rust-hdl-widgets = "^0.1"
rust-hdl-ok-frontpanel-sys = "^0.1"
rust-hdl-sim-chips = "^0.1"
rust-hdl-yosys-synth = "^0.1"
rust-hdl-ok-core = "^0.1"
rust-hdl-test-core = "^0.1"
regex = "1.5.4"
rand = "0.8.4"