[package]
name = "rust-hdl-yosys-synth"
version = "0.1.0"
edition = "2018"
license = "MIT"
description = "Yosys synthesis support for RustHDL crate."
homepage = "https://rusthdl.org"
repository = "https://github.com/SmithsDigitalForge/rust-hdl"
keywords = ["fpga", "verilog", "hardware"]
authors = ["Samit Basu <samit.basu@smiths.com>"]

[dependencies]
regex = "1.5.4"
rust-hdl-core = "^0.1"