digraph {
    0 [ label = "\"NetType\"" ]
    1 [ label = "\"Statement\"" ]
    2 [ label = "\"Assign\"" ]
    3 [ label = "\"Always\"" ]
    4 [ label = "\"Expression\"" ]
    5 [ label = "\"UnaryOp\"" ]
    6 [ label = "\"BinaryOp\"" ]
    7 [ label = "\"Port\"" ]
    8 [ label = "\"If\"" ]
    9 [ label = "\"Case\"" ]
    10 [ label = "\"Input\"" ]
    11 [ label = "\"Inout\"" ]
    12 [ label = "\"RegNetType\"" ]
    13 [ label = "\"Output\"" ]
    14 [ label = "\"OperationType\"" ]
    15 [ label = "\"Assignment\"" ]
    16 [ label = "\"Module\"" ]
    17 [ label = "\"Wire\"" ]
    18 [ label = "\"Register\"" ]
    19 [ label = "\"LocalParam\"" ]
    20 [ label = "\"Number\"" ]
    1 -> 17 [ ]
    1 -> 18 [ ]
    1 -> 2 [ ]
    1 -> 3 [ ]
    1 -> 19 [ ]
    1 -> 8 [ ]
    1 -> 9 [ ]
    1 -> 15 [ ]
    2 -> 4 [ ]
    3 -> 1 [ ]
    4 -> 5 [ ]
    4 -> 4 [ ]
    4 -> 4 [ ]
    4 -> 6 [ ]
    4 -> 4 [ ]
    4 -> 20 [ ]
    7 -> 10 [ ]
    7 -> 13 [ ]
    7 -> 11 [ ]
    8 -> 4 [ ]
    8 -> 1 [ ]
    8 -> 1 [ ]
    9 -> 4 [ ]
    10 -> 0 [ ]
    11 -> 0 [ ]
    12 -> 0 [ ]
    13 -> 12 [ ]
    15 -> 14 [ ]
    15 -> 4 [ ]
    16 -> 1 [ ]
    16 -> 7 [ ]
    19 -> 20 [ ]
}