/dts-v1/;

/ {
	compatible = "starfive,visionfive2";
	model = "RustSBI JH7110";
	#address-cells = <0x01>;
	#size-cells = <0x01>;

	// Memory layout of the firmware:
	//
	// "header": VisionFive2 SPL header (may work on other JH71xx-based boards)
	//
	// "bootloader": Up to ~2 MiB of initial boot code, equivalent to SPL (Secondary Program Loader) from U-Boot
	//     The bootloader region can be reconfigured, however the stripped example bootloader is ~30 KiB.
	//     If reconfigured, "bootloader" region should be 2 KiB offset from a 4 KiB page boundary.
	//     The bootloader binary must smaller than the total SRAM size (2 MiB).
	//        2 KiB for the SPL header + DTB blob
	//        5 * 'HART_STACK_LEN' KiB for HART stacks ('HART_STACK_LEN' KiB per HART stack)
	//
	// "board_dtb": Flattened DeviceTree Blob of the initial board memory layout (this file compiled to .dtb, in SRAM/Flash)
	//     Previously, the DTB was located at a fixed offset.
	//     Now, it just follows the "bootloader" code.
	memory@8000000 {
		device_type = "sram";

		reg = <0x00 0x400 0x400 0x1ffc00>;
		reg-names = "header", "bootloader";
	};
	// "flash": up to 128 MiB of boot code, equivalent to TPL (Tertiary Program Loader) from U-Boot
	//      This can be:
	//      - bare-metal code
	//      - small kernels
	//      - trampoline into a larger kernel loaded from external media
	flash@21000000 {
		device_type = "xspi-nor";

		reg = <0x00 0x8000000>;
		reg-names = "flash";
	};
	// "ram": up to 2 GiB of code (by default, actual RAM length can be read from I2C EEPROM)
	//      This can be any code loaded from "flash" or external media:
	//      - bare-metal code
	//      - small kernels
	//      - larger kernel loaded from external media
	ram@40000000 {
		device_type = "dram";

		reg = <0x00 0x80000000>;
		reg-names = "ram";
	};
};