WCH Ltd. WCH CH32V103xx 1.0 CH32V103xx View File 8 32 0x20 0x0 0xFFFFFFFF PWR Power control PWR 0x40007000 0x0 0x400 registers PVD PVD through EXTI line detection interrupt 17 CTLR CTLR Power control register (PWR_CTRL) 0x0 0x20 read-write 0x00000000 LPDS Low Power Deep Sleep 0 1 PDDS Power Down Deep Sleep 1 1 CWUF Clear Wake-up Flag 2 1 CSBF Clear STANDBY Flag 3 1 PVDE Power Voltage Detector Enable 4 1 PLS PVD Level Selection 5 3 DBP Disable Backup Domain write protection 8 1 CSR CSR Power control register (PWR_CSR) 0x04 0x20 0x00000000 WUF Wake-Up Flag 0 1 read-only SBF STANDBY Flag 1 1 read-only PVDO PVD Output 2 1 read-only EWUP Enable WKUP pin 8 1 read-write RCC Reset and clock control RCC 0x40021000 0x00 0x400 registers RCC RCC global interrupt 5 CTLR CTLR Clock control register 0x00 0x20 0x00000083 HSION Internal High Speed clock enable 0 1 read-write HSIRDY Internal High Speed clock ready flag 1 1 read-only HSITRIM Internal High Speed clock trimming 3 5 read-write HSICAL Internal High Speed clock Calibration 8 8 read-only HSEON External High Speed clock enable 16 1 read-write HSERDY External High Speed clock ready flag 17 1 read-only HSEBYP External High Speed clock Bypass 18 1 read-write CSSON Clock Security System enable 19 1 read-write PLLON PLL enable 24 1 read-write PLLRDY PLL clock ready flag 25 1 read-only CFGR0 CFGR0 Clock configuration register(RCC_CFGR0) 0x04 0x20 0x00000000 SW System clock Switch 0 2 read-write SWS System Clock Switch Status 2 2 read-only HPRE AHB prescaler 4 4 read-write PPRE1 APB Low speed prescaler(APB1) 8 3 read-write PPRE2 APB High speed prescaler(APB2) 11 3 read-write ADCPRE ADC prescaler 14 2 read-write PLLSRC PLL entry clock source 16 1 read-write PLLXTPRE HSE divider for PLL entry 17 1 read-write PLLMUL PLL Multiplication Factor 18 4 read-write USBPRE USB prescaler 22 1 read-write MCO Microcontroller clock output 24 3 read-write INTR INTR Clock interrupt register(RCC_INTR) 0x08 0x20 0x00000000 LSIRDYF LSI Ready Interrupt flag 0 1 read-only LSERDYF LSE Ready Interrupt flag 1 1 read-only HSIRDYF HSI Ready Interrupt flag 2 1 read-only HSERDYF HSE Ready Interrupt flag 3 1 read-only PLLRDYF PLL Ready Interrupt flag 4 1 read-only CSSF Clock Security System Interrupt flag 7 1 read-only LSIRDYIE LSI Ready Interrupt Enable 8 1 read-write LSERDYIE LSE Ready Interrupt Enable 9 1 read-write HSIRDYIE HSI Ready Interrupt Enable 10 1 read-write HSERDYIE HSE Ready Interrupt Enable 11 1 read-write PLLRDYIE PLL Ready Interrupt Enable 12 1 read-write LSIRDYC LSI Ready Interrupt Clear 16 1 write-only LSERDYC LSE Ready Interrupt Clear 17 1 write-only HSIRDYC HSI Ready Interrupt Clear 18 1 write-only HSERDYC HSE Ready Interrupt Clear 19 1 write-only PLLRDYC PLL Ready Interrupt Clear 20 1 write-only CSSC Clock security system interrupt clear 23 1 write-only APB2PRSTR APB2PRSTR APB2 peripheral reset register(RCC_APB2PRSTR) 0x0C 0x20 read-write 0x000000000 AFIORST Alternate function I/O reset 0 1 IOPARST IO port A reset 2 1 IOPBRST IO port B reset 3 1 IOPCRST IO port C reset 4 1 IOPDRST IO port D reset 5 1 ADCRST ADC interface reset 9 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI 1 reset 12 1 USART1RST USART1 reset 14 1 APB1PRSTR APB1PRSTR APB1 peripheral reset register(RCC_APB1PRSTR) 0x10 0x20 read-write 0x00000000 TIM2RST Timer 2 reset 0 1 TIM3RST Timer 3 reset 1 1 TIM4RST Timer 4 reset 2 1 WWDGRST Window watchdog reset 11 1 SPI2RST SPI2 reset 14 1 USART2RST USART 2 reset 17 1 USART3RST USART 3 reset 18 1 I2C1RST I2C1 reset 21 1 I2C2RST I2C2 reset 22 1 USBDRST USBD reset 23 1 CANRST CAN reset 25 1 BKPRST Backup interface reset 27 1 PWRRST Power interface reset 28 1 DACRST DAC interface reset 29 1 AHBPCENR AHBPCENR AHB Peripheral Clock enable register(RCC_AHBPCENR) 0x14 0x20 read-write 0x00000014 DMAEN DMA clock enable 0 1 SRAMEN SRAM interface clock enable 2 1 FLITFEN FLITF clock enable 4 1 CRCEN CRC clock enable 6 1 USBHDEN USBHD clock enable 12 1 APB2PCENR APB2PCENR APB2 peripheral clock enable register (RCC_APB2PCENR) 0x18 0x20 read-write 0x00000000 AFIOEN Alternate function I/O clock enable 0 1 IOPAEN I/O port A clock enable 2 1 IOPBEN I/O port B clock enable 3 1 IOPCEN I/O port C clock enable 4 1 IOPDEN I/O port D clock enable 5 1 ADCEN ADC interface clock enable 9 1 TIM1EN TIM1 Timer clock enable 11 1 SPI1EN SPI 1 clock enable 12 1 USART1EN USART1 clock enable 14 1 APB1PCENR APB1PCENR APB1 peripheral clock enable register (RCC_APB1PCENR) 0x1C 0x20 read-write 0x00000000 TIM2EN Timer 2 clock enable 0 1 TIM3EN Timer 3 clock enable 1 1 TIM4EN Timer 4 clock enable 2 1 WWDGEN Window watchdog clock enable 11 1 SPI2EN SPI 2 clock enable 14 1 USART2EN USART 2 clock enable 17 1 USART3EN USART 3 clock enable 18 1 I2C1EN I2C 1 clock enable 21 1 I2C2EN I2C 2 clock enable 22 1 USBDEN USBD clock enable 23 1 CANEN CAN clock enable 25 1 BKPEN Backup interface clock enable 27 1 PWREN Power interface clock enable 28 1 DACEN DAC interface clock enable 29 1 BDCTLR BDCTLR Backup domain control register(RCC_BDCTLR) 0x20 0x20 0x00000000 LSEON External Low Speed oscillator enable 0 1 read-write LSERDY External Low Speed oscillator ready 1 1 read-only LSEBYP External Low Speed oscillator bypass 2 1 read-write RTCSEL RTC clock source selection 8 2 read-write RTCEN RTC clock enable 15 1 read-write BDRST Backup domain software reset 16 1 read-write RSTSCKR RSTSCKR Control/status register(RCC_RSTSCKR) 0x24 0x20 0x0C000000 LSION Internal low speed oscillator enable 0 1 read-write LSIRDY Internal low speed oscillator ready 1 1 read-only RMVF Remove reset flag 24 1 read-write PINRSTF PIN reset flag 26 1 read-write PORRSTF POR/PDR reset flag 27 1 read-write SFTRSTF Software reset flag 28 1 read-write IWDGRSTF Independent watchdog reset flag 29 1 read-write WWDGRSTF Window watchdog reset flag 30 1 read-write LPWRRSTF Low-power reset flag 31 1 read-write AHBRSTR AHBRSTR AHB reset register(RCC_APHBRSTR) 0x28 0x20 0x00000000 USBHDRST USBHD reset 12 1 read-write EXTEND extension configuration EXTEND 0x40023800 0x00 0x800 registers EXTEND_CTR EXTEND_CTR EXTEND register 0X00 0x20 0x00000020 USBDLS USBD Lowspeed Enable 0 1 read-write USBDPU USBD pullup Enable 1 1 read-write USBHDIO USBHD IO(PB6/PB7) Enable 2 1 read-write USB5VSEL USB 5V Enable 3 1 read-write HSIPRE Whether HSI is divided 4 1 read-write LKUPEN LOCKUP 6 1 read-write LKUPRESET LOCKUP RESET 7 1 read-write ULLDOTRIM ULLDOTRIM 8 2 read-write LDOTRIM LDOTRIM 10 1 read-write GPIOA General purpose I/O GPIO 0x40010800 0x00 0x400 registers CFGLR CFGLR Port configuration register low(GPIOn_CFGLR) 0x00 0x20 read-write 0x44444444 MODE0 Port n.0 mode bits 0 2 CNF0 Port n.0 configuration bits 2 2 MODE1 Port n.1 mode bits 4 2 CNF1 Port n.1 configuration bits 6 2 MODE2 Port n.2 mode bits 8 2 CNF2 Port n.2 configuration bits 10 2 MODE3 Port n.3 mode bits 12 2 CNF3 Port n.3 configuration bits 14 2 MODE4 Port n.4 mode bits 16 2 CNF4 Port n.4 configuration bits 18 2 MODE5 Port n.5 mode bits 20 2 CNF5 Port n.5 configuration bits 22 2 MODE6 Port n.6 mode bits 24 2 CNF6 Port n.6 configuration bits 26 2 MODE7 Port n.7 mode bits 28 2 CNF7 Port n.7 configuration bits 30 2 CFGHR CFGHR Port configuration register high (GPIOn_CFGHR) 0x04 0x20 read-write 0x44444444 MODE8 Port n.8 mode bits 0 2 CNF8 Port n.8 configuration bits 2 2 MODE9 Port n.9 mode bits 4 2 CNF9 Port n.9 configuration bits 6 2 MODE10 Port n.10 mode bits 8 2 CNF10 Port n.10 configuration bits 10 2 MODE11 Port n.11 mode bits 12 2 CNF11 Port n.11 configuration bits 14 2 MODE12 Port n.12 mode bits 16 2 CNF12 Port n.12 configuration bits 18 2 MODE13 Port n.13 mode bits 20 2 CNF13 Port n.13 configuration bits 22 2 MODE14 Port n.14 mode bits 24 2 CNF14 Port n.14 configuration bits 26 2 MODE15 Port n.15 mode bits 28 2 CNF15 Port n.15 configuration bits 30 2 INDR INDR Port input data register (GPIOn_INDR) 0x08 0x20 read-only 0x00000000 IDR0 Port input data 0 1 IDR1 Port input data 1 1 IDR2 Port input data 2 1 IDR3 Port input data 3 1 IDR4 Port input data 4 1 IDR5 Port input data 5 1 IDR6 Port input data 6 1 IDR7 Port input data 7 1 IDR8 Port input data 8 1 IDR9 Port input data 9 1 IDR10 Port input data 10 1 IDR11 Port input data 11 1 IDR12 Port input data 12 1 IDR13 Port input data 13 1 IDR14 Port input data 14 1 IDR15 Port input data 15 1 OUTDR OUTDR Port output data register (GPIOn_OUTDR) 0x0C 0x20 read-write 0x00000000 ODR0 Port output data 0 1 ODR1 Port output data 1 1 ODR2 Port output data 2 1 ODR3 Port output data 3 1 ODR4 Port output data 4 1 ODR5 Port output data 5 1 ODR6 Port output data 6 1 ODR7 Port output data 7 1 ODR8 Port output data 8 1 ODR9 Port output data 9 1 ODR10 Port output data 10 1 ODR11 Port output data 11 1 ODR12 Port output data 12 1 ODR13 Port output data 13 1 ODR14 Port output data 14 1 ODR15 Port output data 15 1 BSHR BSHR Port bit set/reset register (GPIOn_BSHR) 0x10 0x20 write-only 0x00000000 BS0 Set bit 0 0 1 BS1 Set bit 1 1 1 BS2 Set bit 1 2 1 BS3 Set bit 3 3 1 BS4 Set bit 4 4 1 BS5 Set bit 5 5 1 BS6 Set bit 6 6 1 BS7 Set bit 7 7 1 BS8 Set bit 8 8 1 BS9 Set bit 9 9 1 BS10 Set bit 10 10 1 BS11 Set bit 11 11 1 BS12 Set bit 12 12 1 BS13 Set bit 13 13 1 BS14 Set bit 14 14 1 BS15 Set bit 15 15 1 BR0 Reset bit 0 16 1 BR1 Reset bit 1 17 1 BR2 Reset bit 2 18 1 BR3 Reset bit 3 19 1 BR4 Reset bit 4 20 1 BR5 Reset bit 5 21 1 BR6 Reset bit 6 22 1 BR7 Reset bit 7 23 1 BR8 Reset bit 8 24 1 BR9 Reset bit 9 25 1 BR10 Reset bit 10 26 1 BR11 Reset bit 11 27 1 BR12 Reset bit 12 28 1 BR13 Reset bit 13 29 1 BR14 Reset bit 14 30 1 BR15 Reset bit 15 31 1 BCR BCR Port bit reset register (GPIOn_BCR) 0x14 0x20 write-only 0x00000000 BR0 Reset bit 0 0 1 BR1 Reset bit 1 1 1 BR2 Reset bit 1 2 1 BR3 Reset bit 3 3 1 BR4 Reset bit 4 4 1 BR5 Reset bit 5 5 1 BR6 Reset bit 6 6 1 BR7 Reset bit 7 7 1 BR8 Reset bit 8 8 1 BR9 Reset bit 9 9 1 BR10 Reset bit 10 10 1 BR11 Reset bit 11 11 1 BR12 Reset bit 12 12 1 BR13 Reset bit 13 13 1 BR14 Reset bit 14 14 1 BR15 Reset bit 15 15 1 LCKR LCKR Port configuration lock register 0x18 0x20 read-write 0x00000000 LCK0 Port A Lock bit 0 0 1 LCK1 Port A Lock bit 1 1 1 LCK2 Port A Lock bit 2 2 1 LCK3 Port A Lock bit 3 3 1 LCK4 Port A Lock bit 4 4 1 LCK5 Port A Lock bit 5 5 1 LCK6 Port A Lock bit 6 6 1 LCK7 Port A Lock bit 7 7 1 LCK8 Port A Lock bit 8 8 1 LCK9 Port A Lock bit 9 9 1 LCK10 Port A Lock bit 10 10 1 LCK11 Port A Lock bit 11 11 1 LCK12 Port A Lock bit 12 12 1 LCK13 Port A Lock bit 13 13 1 LCK14 Port A Lock bit 14 14 1 LCK15 Port A Lock bit 15 15 1 LCKK Lock key 16 1 GPIOB 0x40010C00 GPIOC 0x40011000 GPIOD 0x40011400 AFIO Alternate function I/O AFIO 0x40010000 0x0 0x400 registers ECR ECR Event Control Register (AFIO_ECR) 0x0 0x20 read-write 0x00000000 PIN Pin selection 0 4 PORT Port selection 4 3 EVOE Event Output Enable 7 1 PCFR1 PCFR1 AF remap and debug I/O configuration register (AFIO_PCFR1) 0x4 0x20 0x00000000 SPI1_REMAP SPI1 remapping 0 1 read-write I2C1_REMAP I2C1 remapping 1 1 read-write USART1_REMAP USART1 remapping 2 1 read-write USART2_REMAP USART2 remapping 3 1 read-write USART3_REMAP USART3 remapping 4 2 read-write TIM1_REMAP TIM1 remapping 6 2 read-write TIM2_REMAP TIM2 remapping 8 2 read-write TIM3_REMAP TIM3 remapping 10 2 read-write TIM4_REMAP TIM4 remapping 12 1 read-write CAN_REMAP CAN1 remapping 13 2 read-write PD01_REMAP Port D0/Port D1 mapping on OSCIN/OSCOUT 15 1 read-write TIM5CH4_IREMAP Set and cleared by software 16 1 read-write ADC1_ETRGINJ_REMAP ADC 1 External trigger injected conversion remapping 17 1 read-write ADC1_ETRGREG_REMAP ADC 1 external trigger regular conversion remapping 18 1 read-write ADC2_ETRGINJ_REMAP ADC 2 external trigger injected conversion remapping 19 1 read-write ADC2_ETRGREG_REMAP ADC 2 external trigger regular conversion remapping 20 1 read-write SWJ_CFG Serial wire JTAG configuration 24 3 write-only EXTICR1 EXTICR1 External interrupt configuration register 1 (AFIO_EXTICR1) 0x8 0x20 read-write 0x00000000 EXTI0 EXTI0 configuration 0 4 EXTI1 EXTI1 configuration 4 4 EXTI2 EXTI2 configuration 8 4 EXTI3 EXTI3 configuration 12 4 EXTICR2 EXTICR2 External interrupt configuration register 2 (AFIO_EXTICR2) 0xC 0x20 read-write 0x00000000 EXTI4 EXTI4 configuration 0 4 EXTI5 EXTI5 configuration 4 4 EXTI6 EXTI6 configuration 8 4 EXTI7 EXTI7 configuration 12 4 EXTICR3 EXTICR3 External interrupt configuration register 3 (AFIO_EXTICR3) 0x10 0x20 read-write 0x00000000 EXTI8 EXTI8 configuration 0 4 EXTI9 EXTI9 configuration 4 4 EXTI10 EXTI10 configuration 8 4 EXTI11 EXTI11 configuration 12 4 EXTICR4 EXTICR4 External interrupt configuration register 4 (AFIO_EXTICR4) 0x14 0x20 read-write 0x00000000 EXTI12 EXTI12 configuration 0 4 EXTI13 EXTI13 configuration 4 4 EXTI14 EXTI14 configuration 8 4 EXTI15 EXTI15 configuration 12 4 PCFR2 PCFR2 AF remap and debug I/O configuration register 0x1C 0x20 read-write 0x00000000 TIM9_REMAP TIM9 remapping 5 1 TIM10_REMAP TIM10 remapping 6 1 TIM11_REMAP TIM11 remapping 7 1 TIM13_REMAP TIM13 remapping 8 1 TIM14_REMAP TIM14 remapping 9 1 FSMC_NADV NADV connect/disconnect 10 1 EXTI EXTI EXTI 0x40010400 0x00 0x400 registers TAMPER Tamper interrupt 18 EXTI0 EXTI Line0 interrupt 22 EXTI1 EXTI Line1 interrupt 23 EXTI2 EXTI Line2 interrupt 24 EXTI3 EXTI Line3 interrupt 25 EXTI4 EXTI Line4 interrupt 26 EXTI9_5 EXTI Line[9:5] interrupts 39 EXTI15_10 EXTI Line[15:10] interrupts 56 INTENR INTENR Interrupt mask register(EXTI_INTENR) 0x00 0x20 read-write 0x00000000 MR0 Interrupt Mask on line 0 0 1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 MR10 Interrupt Mask on line 10 10 1 MR11 Interrupt Mask on line 11 11 1 MR12 Interrupt Mask on line 12 12 1 MR13 Interrupt Mask on line 13 13 1 MR14 Interrupt Mask on line 14 14 1 MR15 Interrupt Mask on line 15 15 1 MR16 Interrupt Mask on line 16 16 1 MR17 Interrupt Mask on line 17 17 1 MR18 Interrupt Mask on line 18 18 1 EVENR EVENR Event mask register (EXTI_EVENR) 0x04 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 MR10 Event Mask on line 10 10 1 MR11 Event Mask on line 11 11 1 MR12 Event Mask on line 12 12 1 MR13 Event Mask on line 13 13 1 MR14 Event Mask on line 14 14 1 MR15 Event Mask on line 15 15 1 MR16 Event Mask on line 16 16 1 MR17 Event Mask on line 17 17 1 MR18 Event Mask on line 18 18 1 RTENR RTENR Rising Trigger selection register(EXTI_RTENR) 0x08 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 TR10 Rising trigger event configuration of line 10 10 1 TR11 Rising trigger event configuration of line 11 11 1 TR12 Rising trigger event configuration of line 12 12 1 TR13 Rising trigger event configuration of line 13 13 1 TR14 Rising trigger event configuration of line 14 14 1 TR15 Rising trigger event configuration of line 15 15 1 TR16 Rising trigger event configuration of line 16 16 1 TR17 Rising trigger event configuration of line 17 17 1 TR18 Rising trigger event configuration of line 18 18 1 FTENR FTENR Falling Trigger selection register(EXTI_FTENR) 0x0C 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 TR10 Falling trigger event configuration of line 10 10 1 TR11 Falling trigger event configuration of line 11 11 1 TR12 Falling trigger event configuration of line 12 12 1 TR13 Falling trigger event configuration of line 13 13 1 TR14 Falling trigger event configuration of line 14 14 1 TR15 Falling trigger event configuration of line 15 15 1 TR16 Falling trigger event configuration of line 16 16 1 TR17 Falling trigger event configuration of line 17 17 1 TR18 Falling trigger event configuration of line 18 18 1 SWIEVR SWIEVR Software interrupt event register(EXTI_SWIEVR) 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 SWIER10 Software Interrupt on line 10 10 1 SWIER11 Software Interrupt on line 11 11 1 SWIER12 Software Interrupt on line 12 12 1 SWIER13 Software Interrupt on line 13 13 1 SWIER14 Software Interrupt on line 14 14 1 SWIER15 Software Interrupt on line 15 15 1 SWIER16 Software Interrupt on line 16 16 1 SWIER17 Software Interrupt on line 17 17 1 SWIER18 Software Interrupt on line 18 18 1 INTFR INTFR Pending register (EXTI_INTFR) 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 PR1 Pending bit 1 1 1 PR2 Pending bit 2 2 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 PR10 Pending bit 10 10 1 PR11 Pending bit 11 11 1 PR12 Pending bit 12 12 1 PR13 Pending bit 13 13 1 PR14 Pending bit 14 14 1 PR15 Pending bit 15 15 1 PR16 Pending bit 16 16 1 PR17 Pending bit 17 17 1 PR18 Pending bit 18 18 1 DMA DMA controller DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 27 DMA1_Channel2 DMA1 Channel2 global interrupt 28 DMA1_Channel3 DMA1 Channel3 global interrupt 29 DMA1_Channel4 DMA1 Channel4 global interrupt 30 DMA1_Channel5 DMA1 Channel5 global interrupt 31 DMA1_Channel6 DMA1 Channel6 global interrupt 32 DMA1_Channel7 DMA1 Channel7 global interrupt 33 INTFR INTFR DMA interrupt status register (DMA_INTFR) 0x0 0x20 read-only 0x00000000 GIF1 Channel 1 Global interrupt flag 0 1 TCIF1 Channel 1 Transfer Complete flag 1 1 HTIF1 Channel 1 Half Transfer Complete flag 2 1 TEIF1 Channel 1 Transfer Error flag 3 1 GIF2 Channel 2 Global interrupt flag 4 1 TCIF2 Channel 2 Transfer Complete flag 5 1 HTIF2 Channel 2 Half Transfer Complete flag 6 1 TEIF2 Channel 2 Transfer Error flag 7 1 GIF3 Channel 3 Global interrupt flag 8 1 TCIF3 Channel 3 Transfer Complete flag 9 1 HTIF3 Channel 3 Half Transfer Complete flag 10 1 TEIF3 Channel 3 Transfer Error flag 11 1 GIF4 Channel 4 Global interrupt flag 12 1 TCIF4 Channel 4 Transfer Complete flag 13 1 HTIF4 Channel 4 Half Transfer Complete flag 14 1 TEIF4 Channel 4 Transfer Error flag 15 1 GIF5 Channel 5 Global interrupt flag 16 1 TCIF5 Channel 5 Transfer Complete flag 17 1 HTIF5 Channel 5 Half Transfer Complete flag 18 1 TEIF5 Channel 5 Transfer Error flag 19 1 GIF6 Channel 6 Global interrupt flag 20 1 TCIF6 Channel 6 Transfer Complete flag 21 1 HTIF6 Channel 6 Half Transfer Complete flag 22 1 TEIF6 Channel 6 Transfer Error flag 23 1 GIF7 Channel 7 Global interrupt flag 24 1 TCIF7 Channel 7 Transfer Complete flag 25 1 HTIF7 Channel 7 Half Transfer Complete flag 26 1 TEIF7 Channel 7 Transfer Error flag 27 1 INTFCR INTFCR DMA interrupt flag clear register (DMA_INTFCR) 0x4 0x20 write-only 0x00000000 CGIF1 Channel 1 Global interrupt clear 0 1 CGIF2 Channel 2 Global interrupt clear 4 1 CGIF3 Channel 3 Global interrupt clear 8 1 CGIF4 Channel 4 Global interrupt clear 12 1 CGIF5 Channel 5 Global interrupt clear 16 1 CGIF6 Channel 6 Global interrupt clear 20 1 CGIF7 Channel 7 Global interrupt clear 24 1 CTCIF1 Channel 1 Transfer Complete clear 1 1 CTCIF2 Channel 2 Transfer Complete clear 5 1 CTCIF3 Channel 3 Transfer Complete clear 9 1 CTCIF4 Channel 4 Transfer Complete clear 13 1 CTCIF5 Channel 5 Transfer Complete clear 17 1 CTCIF6 Channel 6 Transfer Complete clear 21 1 CTCIF7 Channel 7 Transfer Complete clear 25 1 CHTIF1 Channel 1 Half Transfer clear 2 1 CHTIF2 Channel 2 Half Transfer clear 6 1 CHTIF3 Channel 3 Half Transfer clear 10 1 CHTIF4 Channel 4 Half Transfer clear 14 1 CHTIF5 Channel 5 Half Transfer clear 18 1 CHTIF6 Channel 6 Half Transfer clear 22 1 CHTIF7 Channel 7 Half Transfer clear 26 1 CTEIF1 Channel 1 Transfer Error clear 3 1 CTEIF2 Channel 2 Transfer Error clear 7 1 CTEIF3 Channel 3 Transfer Error clear 11 1 CTEIF4 Channel 4 Transfer Error clear 15 1 CTEIF5 Channel 5 Transfer Error clear 19 1 CTEIF6 Channel 6 Transfer Error clear 23 1 CTEIF7 Channel 7 Transfer Error clear 27 1 CFGR1 CFGR1 DMA channel configuration register (DMA_CFGR) 0x8 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR1 CNTR1 DMA channel 1 number of data register 0xC 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR1 PADDR1 DMA channel 1 peripheral address register 0x10 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR1 MADDR1 DMA channel 1 memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR2 CFGR2 DMA channel configuration register (DMA_CFGR) 0x1C 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR2 CNTR2 DMA channel 2 number of data register 0x20 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR2 PADDR2 DMA channel 2 peripheral address register 0x24 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR2 MADDR2 DMA channel 2 memory address register 0x28 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR3 CFGR3 DMA channel configuration register (DMA_CFGR) 0x30 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR3 CNTR3 DMA channel 3 number of data register 0x34 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR3 PADDR3 DMA channel 3 peripheral address register 0x38 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR3 MADDR3 DMA channel 3 memory address register 0x3C 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR4 CFGR4 DMA channel configuration register (DMA_CFGR) 0x44 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR4 CNTR4 DMA channel 4 number of data register 0x48 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR4 PADDR4 DMA channel 4 peripheral address register 0x4C 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR4 MADDR4 DMA channel 4 memory address register 0x50 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR5 CFGR5 DMA channel configuration register (DMA_CFGR) 0x58 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR5 CNTR5 DMA channel 5 number of data register 0x5C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR5 PADDR5 DMA channel 5 peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR5 MADDR5 DMA channel 5 memory address register 0x64 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR6 CFGR6 DMA channel configuration register (DMA_CFGR) 0x6C 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR6 CNTR6 DMA channel 6 number of data register 0x70 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR6 PADDR6 DMA channel 6 peripheral address register 0x74 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR6 MADDR6 DMA channel 6 memory address register 0x78 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR7 CFGR7 DMA channel configuration register (DMA_CFGR) 0x80 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR7 CNTR7 DMA channel 7 number of data register 0x84 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR7 PADDR7 DMA channel 7 peripheral address register 0x88 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR7 MADDR7 DMA channel 7 memory address register 0x8C 0x20 read-write 0x00000000 MA Memory address 0 32 RTC Real time clock RTC 0x40002800 0x0 0x400 registers RTC RTC global interrupt 19 RTCAlarm RTC Alarms through EXTI line interrupt 57 CTLRH CTLRH RTC Control Register High 0x0 0x20 read-write 0x0000 SECIE Second interrupt Enable 0 1 ALRIE Alarm interrupt Enable 1 1 OWIE Overflow interrupt Enable 2 1 CTLRL CTLRL RTC Control Register Low 0x4 0x20 0x0020 SECF Second Flag 0 1 read-write ALRF Alarm Flag 1 1 read-write OWF Overflow Flag 2 1 read-write RSF Registers Synchronized Flag 3 1 read-write CNF Configuration Flag 4 1 read-write RTOFF RTC operation OFF 5 1 read-only PSCRH PSCRH RTC Prescaler Load Register High 0x8 0x20 write-only 0x0000 PRLH RTC Prescaler Load Register High 0 4 PSCRL PSCRL RTC Prescaler Load Register Low 0xC 0x20 write-only 0x8000 PRLL RTC Prescaler Divider Register Low 0 16 DIVH DIVH RTC Prescaler Divider Register High 0x10 0x20 read-only 0x0000 DIVH RTC prescaler divider register high 0 4 DIVL DIVL RTC Prescaler Divider Register Low 0x14 0x20 read-only 0x8000 DIVL RTC prescaler divider register Low 0 16 CNTH CNTH RTC Counter Register High 0x18 0x20 read-write 0x0000 CNTH RTC counter register high 0 16 CNTL CNTL RTC Counter Register Low 0x1C 0x20 read-write 0x0000 CNTL RTC counter register Low 0 16 ALRMH ALRMH RTC Alarm Register High 0x20 0x20 write-only 0xFFFF ALRMH RTC alarm register high 0 16 ALRML ALRML RTC Alarm Register Low 0x24 0x20 write-only 0xFFFF ALRML RTC alarm register low 0 16 BKP Backup registers BKP 0x40006C00 0x0 0x400 registers DATAR1 DATAR1 Backup data register (BKP_DR) 0x4 0x20 read-write 0x00000000 D1 Backup data 0 16 DATAR2 DATAR2 Backup data register (BKP_DR) 0x8 0x20 read-write 0x00000000 D2 Backup data 0 16 DATAR3 DATAR3 Backup data register (BKP_DR) 0xC 0x20 read-write 0x00000000 D3 Backup data 0 16 DATAR4 DATAR4 Backup data register (BKP_DR) 0x10 0x20 read-write 0x00000000 D4 Backup data 0 16 DATAR5 DATAR5 Backup data register (BKP_DR) 0x14 0x20 read-write 0x00000000 D5 Backup data 0 16 DATAR6 DATAR6 Backup data register (BKP_DR) 0x18 0x20 read-write 0x00000000 D6 Backup data 0 16 DATAR7 DATAR7 Backup data register (BKP_DR) 0x1C 0x20 read-write 0x00000000 D7 Backup data 0 16 DATAR8 DATAR8 Backup data register (BKP_DR) 0x20 0x20 read-write 0x00000000 D8 Backup data 0 16 DATAR9 DATAR9 Backup data register (BKP_DR) 0x24 0x20 read-write 0x00000000 D9 Backup data 0 16 DATAR10 DATAR10 Backup data register (BKP_DR) 0x28 0x20 read-write 0x00000000 D10 Backup data 0 16 OCTLR OCTLR RTC clock calibration register (BKP_OCTLR) 0x2C 0x20 read-write 0x00000000 CAL Calibration value 0 7 CCO Calibration Clock Output 7 1 ASOE Alarm or second output enable 8 1 ASOS Alarm or second output selection 9 1 TPCTLR TPCTLR Backup control register (BKP_TPCTLR) 0x30 0x20 read-write 0x00000000 TPE Tamper pin enable 0 1 TPAL Tamper pin active level 1 1 TPCSR TPCSR BKP_TPCSR control/status register (BKP_CSR) 0x34 0x20 0x00000000 CTE Clear Tamper event 0 1 write-only CTI Clear Tamper Interrupt 1 1 write-only TPIE Tamper Pin interrupt enable 2 1 read-write TEF Tamper Event Flag 8 1 read-only TIF Tamper Interrupt Flag 9 1 read-only IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers CTLR CTLR Key register (IWDG_CTLR) 0x0 0x20 write-only 0x0000 KEY Key value 0 16 PSCR PSCR Prescaler register (IWDG_PSCR) 0x4 0x20 read-write 0x0000 PR Prescaler divider 0 3 RLDR RLDR Reload register (IWDG_RLDR) 0x8 0x20 read-write 0x0FFF RL Watchdog counter reload value 0 12 STATR STATR Status register (IWDG_SR) 0xC 0x20 read-only 0x0000 PVU Watchdog prescaler value update 0 1 RVU Watchdog counter reload value update 1 1 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 16 CTLR CTLR Control register (WWDG_CR) 0x0 0x20 read-write 0x007F T 7-bit counter (MSB to LSB) 0 7 WDGA Activation bit 7 1 CFGR CFGR Configuration register (WWDG_CFR) 0x4 0x20 read-write 0x007F W 7-bit window value 0 7 WDGTB Timer Base 7 2 EWI Early Wakeup Interrupt 9 1 STATR STATR Status register (WWDG_SR) 0x8 0x20 read-write 0x0000 WEIF Early Wakeup Interrupt Flag 0 1 TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_TIM9 TIM1 Break interrupt and TIM9 global interrupt 40 TIM1_UP_TIM10 TIM1 Update interrupt and TIM10 global interrupt 41 TIM1_TRG_COM_TIM11 TIM1 Trigger and Commutation interrupts and TIM11 global interrupt 42 TIM1_CC TIM1 Capture Compare interrupt 43 CTLR1 CTLR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CTLR2 CTLR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCFGR SMCFGR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 BIE Break interrupt enable 7 1 COMIE COM interrupt enable 5 1 INTFR INTFR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 SWEVGR SWEVGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CHCTLR1_Output CHCTLR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x0000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 0x20 read-write 0x0000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register (output mode) 0x1C 0x20 read-write 0x0000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 0x20 read-write 0x00000000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x00000000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ATRLR ATRLR auto-reload register 0x2C 0x20 read-write 0x00000000 ARR Auto-reload value 0 16 CH1CVR CH1CVR capture/compare register 1 0x34 0x20 read-write 0x00000000 CCR1 Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 0x20 read-write 0x00000000 CCR2 Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 0x20 read-write 0x00000000 CCR3 Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 0x20 read-write 0x00000000 CCR4 Capture/Compare value 0 16 DMACFGR DMACFGR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 RPTCR RPTCR repetition counter register 0x30 0x20 read-write 0x0000 REP Repetition counter value 0 8 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 TIM2 General purpose timer TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 44 CTLR1 CTLR1 control register 1 0x0 0x20 read-write 0x0000 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CTLR2 CTLR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCFGR SMCFGR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 0x20 write-only 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 SWEVGR SWEVGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CHCTLR1_Output CHCTLR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x0000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 0x20 read-write 0x0000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x0000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 0x20 read-write 0x0000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x0000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ATRLR ATRLR auto-reload register 0x2C 0x20 read-write 0x0000 ARR Auto-reload value 0 16 CH1CVR CH1CVR capture/compare register 1 0x34 0x20 read-write 0x0000 CCR1 Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 0x20 read-write 0x0000 CCR2 Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 0x20 read-write 0x0000 CCR3 Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 0x20 read-write 0x0000 CCR4 Capture/Compare value 0 16 DMACFGR DMACFGR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAR DMAR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAB DMA register for burst accesses 0 16 TIM3 0x40000400 TIM3 TIM3 global interrupt 45 TIM4 0x40000800 TIM4 TIM4 global interrupt 46 I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 47 I2C1_ER I2C1 error interrupt 48 CTLR1 CTLR1 Control register 1 0x0 0x20 read-write 0x0000 SWRST Software reset 15 1 ALERT SMBus alert 13 1 PEC Packet error checking 12 1 POS Acknowledge/PEC Position (for data reception) 11 1 ACK Acknowledge enable 10 1 STOP Stop generation 9 1 START Start generation 8 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 ENGC General call enable 6 1 ENPEC PEC enable 5 1 ENARP ARP enable 4 1 SMBTYPE SMBus type 3 1 SMBUS SMBus mode 1 1 PE Peripheral enable 0 1 CTLR2 CTLR2 Control register 2 0x4 0x20 read-write 0x0000 LAST DMA last transfer 12 1 DMAEN DMA requests enable 11 1 ITBUFEN Buffer interrupt enable 10 1 ITEVTEN Event interrupt enable 9 1 ITERREN Error interrupt enable 8 1 FREQ Peripheral clock frequency 0 6 OADDR1 OADDR1 Own address register 1 0x8 0x20 read-write 0x0000 ADDMODE Addressing mode (slave mode) 15 1 MUST1 must set 1 bit 14 1 ADD9_8 Interface address 8 2 ADD7_1 Interface address 1 7 ADD0 Interface address 0 1 OADDR2 OADDR2 Own address register 2 0xC 0x20 read-write 0x0000 ADD2 Interface address 1 7 ENDUAL Dual addressing mode enable 0 1 DATAR DATAR Data register 0x10 0x20 read-write 0x0000 DR 8-bit data register 0 8 STAR1 STAR1 Status register 1 0x14 0x20 0x0000 SMBALERT SMBus alert 15 1 read-write TIMEOUT Timeout or Tlow error 14 1 read-write PECERR PEC Error in reception 12 1 read-write OVR Overrun/Underrun 11 1 read-write AF Acknowledge failure 10 1 read-write ARLO Arbitration lost (master mode) 9 1 read-write BERR Bus error 8 1 read-write TxE Data register empty (transmitters) 7 1 read-only RxNE Data register not empty (receivers) 6 1 read-only STOPF Stop detection (slave mode) 4 1 read-only ADD10 10-bit header sent (Master mode) 3 1 read-only BTF Byte transfer finished 2 1 read-only ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only SB Start bit (Master mode) 0 1 read-only STAR2 STAR2 Status register 2 0x18 0x20 read-only 0x0000 PEC acket error checking register 8 8 DUALF Dual flag (Slave mode) 7 1 SMBHOST SMBus host header (Slave mode) 6 1 SMBDEFAULT SMBus device default address (Slave mode) 5 1 GENCALL General call address (Slave mode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CKCFGR CKCFGR Clock control register 0x1C 0x20 read-write 0x0000 F_S I2C master mode selection 15 1 DUTY Fast mode duty cycle 14 1 CCR Clock control register in Fast/Standard mode (Master mode) 0 12 RTR RTR RTR register 0x20 0x20 read-write 0x0002 TRISE Maximum rise time in Fast/Standard mode (Master mode) 0 6 I2C2 0x40005800 I2C2_EV I2C2 event interrupt 49 I2C2_ER I2C2 error interrupt 50 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 51 CTLR1 CTLR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CTLR2 CTLR2 control register 2 0x4 0x20 read-write 0x0000 TXEIE Tx buffer empty interrupt enable 7 1 RXNEIE RX buffer not empty interrupt enable 6 1 ERRIE Error interrupt enable 5 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 RXDMAEN Rx buffer DMA enable 0 1 STATR STATR status register 0x8 0x20 0x0002 BSY Busy flag 7 1 read-only OVR Overrun flag 6 1 read-only MODF Mode fault 5 1 read-only CRCERR CRC error flag 4 1 read-write TXE Transmit buffer empty 1 1 read-only RXNE Receive buffer not empty 0 1 read-only DATAR DATAR data register 0xC 0x20 read-write 0x0000 DATAR Data register 0 16 CRCR CRCR CRCR polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RCRCR RCRCR RX CRC register 0x14 0x20 read-only 0x0000 RxCRC Rx CRC register 0 16 TCRCR TCRCR TX CRC register 0x18 0x20 read-only 0x0000 TxCRC Tx CRC register 0 16 I2SCFGR I2SCFGR I2S configuration register 0x1C 0x20 read-write 0x0000 I2SMOD I2S mode selection 11 1 I2SE I2S Enable 10 1 I2SCFG I2S configuration mode 8 2 PCMSYNC PCM frame synchronization 7 1 I2SSTD I2S standard selection 4 2 CKPOL Steady state clock polarity 3 1 DATLEN Data length to be transferred 1 2 CHLEN Channel length (number of bits per audio channel) 0 1 I2SPR I2SPR I2S prescaler register 0x20 0x20 read-write 00000010 MCKOE Master clock output enable 9 1 ODD Odd factor for the prescaler 8 1 I2SDIV I2S Linear prescaler 0 8 SPI2 0x40003800 SPI2 SPI2 global interrupt 52 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 53 STATR STATR Status register 0x0 0x20 read-write 0x000000C0 CTS CTS flag 9 1 read-write LBD LIN break detection flag 8 1 read-write TXE Transmit data register empty 7 1 read-only TC Transmission complete 6 1 read-write RXNE Read data register not empty 5 1 read-write IDLE IDLE line detected 4 1 read-only ORE Overrun error 3 1 read-only NE Noise error flag 2 1 read-only FE Framing error 1 1 read-only PE Parity error 0 1 read-only DATAR DATAR Data register 0x4 0x20 read-write 0x00000000 DR Data value 0 9 BRR BRR Baud rate register 0x8 0x20 read-write 0x00000000 DIV_Mantissa mantissa of USARTDIV 4 12 DIV_Fraction fraction of USARTDIV 0 4 CTLR1 CTLR1 Control register 1 0xC 0x20 read-write 0x00000000 UE USART enable 13 1 M Word length 12 1 WAKE Wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE TXE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 SBK Send break 0 1 CTLR2 CTLR2 Control register 2 0x10 0x20 read-write 0x00000000 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 ADD Address of the USART node 0 4 CTLR3 CTLR3 Control register 3 0x14 0x20 read-write 0x00000000 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 EIE Error interrupt enable 0 1 GPR GPR Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GT Guard time value 8 8 PSC Prescaler value 0 8 USART2 0x40004400 USART2 USART2 global interrupt 54 USART3 0x40004800 USART3 USART3 global interrupt 55 ADC Analog to digital converter ADC 0x40012400 0x0 0x400 registers ADC ADC1 global interrupt 34 STATR STATR status register 0x0 0x20 read-write 0x00000000 STRT Regular channel start flag 4 1 JSTRT Injected channel start flag 3 1 JEOC Injected channel end of conversion 2 1 EOC Regular channel end of conversion 1 1 AWD Analog watchdog flag 0 1 CTLR1 CTLR1 control register 1 0x4 0x20 read-write 0x00000000 TKENABLE Touch key enable, including TKEY_F and TKEY_V 24 1 AWDEN Analog watchdog enable on regular channels 23 1 JAWDEN Analog watchdog enable on injected channels 22 1 DUALMOD Dual mode selection 16 4 DISCNUM Discontinuous mode channel count 13 3 JDISCEN Discontinuous mode on injected channels 12 1 DISCEN Discontinuous mode on regular channels 11 1 JAUTO Automatic injected group conversion 10 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 SCAN Scan mode 8 1 JEOCIE Interrupt enable for injected channels 7 1 AWDIE Analog watchdog interrupt enable 6 1 EOCIE Interrupt enable for EOC 5 1 AWDCH Analog watchdog channel select bits 0 5 CTLR2 CTLR2 control register 2 0x8 0x20 read-write 0x00000000 TSVREFE Temperature sensor and VREFINT enable 23 1 SWSTART Start conversion of regular channels 22 1 JSWSTART Start conversion of injected channels 21 1 EXTTRIG External trigger conversion mode for regular channels 20 1 EXTSEL External event select for regular group 17 3 JEXTTRIG External trigger conversion mode for injected channels 15 1 JEXTSEL External event select for injected group 12 3 ALIGN Data alignment 11 1 DMA Direct memory access mode 8 1 RSTCAL Reset calibration 3 1 CAL A/D calibration 2 1 CONT Continuous conversion 1 1 ADON A/D converter ON / OFF 0 1 SAMPTR1 SAMPTR1 sample time register 1 0xC 0x20 read-write 0x00000000 SMP10 Channel 10 sample time selection 0 3 SMP11 Channel 11 sample time selection 3 3 SMP12 Channel 12 sample time selection 6 3 SMP13 Channel 13 sample time selection 9 3 SMP14 Channel 14 sample time selection 12 3 SMP15 Channel 15 sample time selection 15 3 SMP16 Channel 16 sample time selection 18 3 SMP17 Channel 17 sample time selection 21 3 SAMPTR2 SAMPTR2 sample time register 2 0x10 0x20 read-write 0x00000000 SMP0 Channel 0 sample time selection 0 3 SMP1 Channel 1 sample time selection 3 3 SMP2 Channel 2 sample time selection 6 3 SMP3 Channel 3 sample time selection 9 3 SMP4 Channel 4 sample time selection 12 3 SMP5 Channel 5 sample time selection 15 3 SMP6 Channel 6 sample time selection 18 3 SMP7 Channel 7 sample time selection 21 3 SMP8 Channel 8 sample time selection 24 3 SMP9 Channel 9 sample time selection 27 3 IOFR1 IOFR1 injected channel data offset register x 0x14 0x20 read-write 0x00000000 JOFFSET1 Data offset for injected channel x 0 12 IOFR2 IOFR2 injected channel data offset register x 0x18 0x20 read-write 0x00000000 JOFFSET2 Data offset for injected channel x 0 12 IOFR3 IOFR3 injected channel data offset register x 0x1C 0x20 read-write 0x00000000 JOFFSET3 Data offset for injected channel x 0 12 IOFR4 IOFR4 injected channel data offset register x 0x20 0x20 read-write 0x00000000 JOFFSET4 Data offset for injected channel x 0 12 WDHTR WDHTR watchdog higher threshold register 0x24 0x20 read-write 0x00000000 HT Analog watchdog higher threshold 0 12 WDLTR WDLTR watchdog lower threshold register 0x28 0x20 read-write 0x00000000 LT Analog watchdog lower threshold 0 12 RSQR1 RSQR1 regular sequence register 1 0x2C 0x20 read-write 0x00000000 L Regular channel sequence length 20 4 SQ16 16th conversion in regular sequence 15 5 SQ15 15th conversion in regular sequence 10 5 SQ14 14th conversion in regular sequence 5 5 SQ13 13th conversion in regular sequence 0 5 RSQR2 RSQR2 regular sequence register 2 0x30 0x20 read-write 0x00000000 SQ12 12th conversion in regular sequence 25 5 SQ11 11th conversion in regular sequence 20 5 SQ10 10th conversion in regular sequence 15 5 SQ9 9th conversion in regular sequence 10 5 SQ8 8th conversion in regular sequence 5 5 SQ7 7th conversion in regular sequence 0 5 RSQR3 RSQR3 regular sequence register 3 0x34 0x20 read-write 0x00000000 SQ6 6th conversion in regular sequence 25 5 SQ5 5th conversion in regular sequence 20 5 SQ4 4th conversion in regular sequence 15 5 SQ3 3rd conversion in regular sequence 10 5 SQ2 2nd conversion in regular sequence 5 5 SQ1 1st conversion in regular sequence 0 5 ISQR ISQR injected sequence register 0x38 0x20 read-write 0x00000000 JL Injected sequence length 20 2 JSQ4 4th conversion in injected sequence 15 5 JSQ3 3rd conversion in injected sequence 10 5 JSQ2 2nd conversion in injected sequence 5 5 JSQ1 1st conversion in injected sequence 0 5 IDATAR1 IDATAR1 injected data register x 0x3C 0x20 read-only 0x00000000 JDATA Injected data 0 16 IDATAR2 IDATAR2 injected data register x 0x40 0x20 read-only 0x00000000 JDATA Injected data 0 16 IDATAR3 IDATAR3 injected data register x 0x44 0x20 read-only 0x00000000 JDATA Injected data 0 16 IDATAR4 IDATAR4 injected data register x 0x48 0x20 read-only 0x00000000 JDATA Injected data 0 16 RDATAR RDATAR regular data register 0x4C 0x20 read-only 0x00000000 DATA Regular data 0 16 ADC2DATA ADC2 data 16 16 DAC1 Digital to analog converter DAC 0x40007400 0x0 0x400 registers CTLR CTLR Control register (DAC_CTLR) 0x0 0x20 read-write 0x00000000 EN1 DAC channel1 enable 0 1 BOFF1 DAC channel1 output buffer disable 1 1 TEN1 DAC channel1 trigger enable 2 1 TSEL1 DAC channel1 trigger selection 3 3 WAVE1 DAC channel1 noise/triangle wave generation enable 6 2 MAMP1 DAC channel1 mask/amplitude selector 8 4 DMAEN1 DAC channel1 DMA enable 12 1 EN2 DAC channel2 enable 16 1 BOFF2 DAC channel2 output buffer disable 17 1 TEN2 DAC channel2 trigger enable 18 1 TSEL2 DAC channel2 trigger selection 19 3 WAVE2 DAC channel2 noise/triangle wave generation enable 22 2 MAMP2 DAC channel2 mask/amplitude selector 24 4 DMAEN2 DAC channel2 DMA enable 28 1 SWTR SWTR DAC software trigger register (DAC_SWTR) 0x4 0x20 write-only 0x00000000 SWTRIG1 DAC channel1 software trigger 0 1 SWTRIG2 DAC channel2 software trigger 1 1 R12BDHR1 R12BDHR1 DAC channel1 12-bit right-aligned data holding register(DAC_R12BDHR1) 0x8 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit right-aligned data 0 12 L12BDHR1 L12BDHR1 DAC channel1 12-bit left aligned data holding register (DAC_L12BDHR1) 0xC 0x20 read-write 0x00000000 DACC1DHR DAC channel1 12-bit left-aligned data 4 12 R12BDHR2 R12BDHR2 DAC channel2 12-bit right aligned data holding register (DAC_R12BDHR2) 0x14 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit right-aligned data 0 12 L12BDHR2 L12BDHR2 DAC channel2 12-bit left aligned data holding register (DAC_L12BDHR2) 0x18 0x20 read-write 0x00000000 DACC2DHR DAC channel2 12-bit left-aligned data 4 12 DOR1 DOR1 DAC channel1 data output register (DAC_DOR1) 0x2C 0x20 read-only 0x00000000 DACC1DOR DAC channel1 data output 0 12 DOR2 DOR2 DAC channel2 data output register (DAC_DOR2) 0x30 0x20 read-only 0x00000000 DACC2DOR DAC channel2 data output 0 12 DBG Debug support DBG 0xE0042000 0x0 0x400 registers IDCODE IDCODE DBGMCU_IDCODE 0x0 0x20 read-only 0x0 DEV_ID DEV_ID 0 12 REV_ID REV_ID 16 16 CFGR CFGR DBGMCU_CFGR 0x4 0x20 read-write 0x0 DBG_SLEEP DBG_SLEEP 0 1 DBG_STOP DBG_STOP 1 1 DBG_STANDBY DBG_STANDBY 2 1 TRACE_IOEN TRACE_IOEN 5 1 TRACE_MODE TRACE_MODE 6 2 DBG_IWDG_STOP DBG_IWDG_STOP 8 1 DBG_WWDG_STOP DBG_WWDG_STOP 9 1 DBG_TIM1_STOP DBG_TIM1_STOP 10 1 DBG_TIM2_STOP DBG_TIM2_STOP 11 1 DBG_TIM3_STOP DBG_TIM3_STOP 12 1 DBG_TIM4_STOP DBG_TIM4_STOP 13 1 DBG_CAN1_STOP DBG_CAN1_STOP 14 1 DBG_I2C1_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT 15 1 DBG_I2C2_SMBUS_TIMEOUT DBG_I2C2_SMBUS_TIMEOUT 16 1 DBG_TIM8_STOP DBG_TIM8_STOP 17 1 DBG_TIM5_STOP DBG_TIM5_STOP 18 1 DBG_TIM6_STOP DBG_TIM6_STOP 19 1 DBG_TIM7_STOP DBG_TIM7_STOP 20 1 DBG_CAN2_STOP DBG_CAN2_STOP 21 1 USBHD USB register USB 0x40023400 0x00 0x400 registers USBHD USBHD_IRQHandler 59 R8_USB_CTRL USB base control 0x00 0X08 read-write RB_UC_DMA_EN DMA enable and DMA interrupt enable for USB [0:0] RB_UC_CLR_ALL force clear FIFO and count of USB [1:1] RB_UC_RESET_SIE force reset USB SIE, need software clear [2:2] RB_UC_INT_BUSY enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid [3:3] MASK_UC_SYS_CTRL bit mask of USB system control [5:4] RB_UC_LOW_SPEED enable USB low speed: 0=12Mbps, 1=1.5Mbps [6:6] RB_UC_HOST_MODE enable USB host mode: 0=device mode, 1=host mode [7:7] R8_UDEV_CTRL__R8_UHOST_CTRL USB device physical prot control 0x01 8 RB_UD_PORT_EN__RB_UH_PORT_EN enable USB physical port I/O: 0=disable, 1=enable;enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached [0:0] read-write RB_UD_GP_BIT__RB_UH_BUS_RESET general purpose bit;control USB bus reset: 0=normal, 1=force bus reset [1:1] read-write RB_UD_LOW_SPEED__RB_UH_LOW_SPEED enable USB physical port low speed: 0=full speed, 1=low speed;enable USB port low speed: 0=full speed, 1=low speed [2:2] read-write RB_UD_DM_PIN__RB_UH_DM_PIN ReadOnly: indicate current UDM pin level [4:4] read-only RB_UD_DP_PIN__RB_UH_DP_PIN ReadOnly: indicate current UDP pin level [5:5] read-only RB_UD_PD_DIS__RB_UH_PD_DIS disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable [7:7] read-only R8_USB_INT_EN USB interrupt enable 0x02 8 read-write RB_UIE_BUS_RST__RB_UIE_DETECT enable interrupt for USB bus reset event for USB device mode;enable interrupt for USB device detected event for USB host mode [0:0] RB_UIE_TRANSFER enable interrupt for USB transfer completion [1:1] RB_UIE_SUSPEND enable interrupt for USB suspend or resume event [2:2] RB_UIE_HST_SOF enable interrupt for host SOF timer action for USB host mode [3:3] RB_UIE_FIFO_OV enable interrupt for FIFO overflow [4:4] RB_UIE_DEV_NAK enable interrupt for NAK responded for USB device mode [6:6] RB_UIE_DEV_SOF enable interrupt for SOF received for USB device mode [7:7] R8_USB_DEV_AD USB device address 0x03 8 read-write MASK_USB_ADDR bit mask for USB device address [6:0] RB_UDA_GP_BIT general purpose bit [7:7] R8_USB_MIS_ST USB miscellaneous status 0x05 8 read-only RB_UMS_DEV_ATTACH RO, indicate device attached status on USB host [0:0] RB_UMS_DM_LEVEL RO, indicate UDM level saved at device attached to USB host [1:1] RB_UMS_SUSPEND RO, indicate USB suspend status [2:2] RB_UMS_BUS_RESET RO, indicate USB bus reset status [3:3] RB_UMS_R_FIFO_RDY RO, indicate USB receiving FIFO ready status (not empty) [4:4] RB_UMS_SIE_FREE RO, indicate USB SIE free status [5:5] RB_UMS_SOF_ACT RO, indicate host SOF timer action status for USB host [6:6] RB_UMS_SOF_PRES RO, indicate host SOF timer presage status [7:7] R8_USB_INT_FG USB interrupt flag 0x06 8 read-write RB_UIF_BUS_RST__RB_UIF_DETECT bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear;device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear [0:0] RB_UIF_TRANSFER USB transfer completion interrupt flag, direct bit address clear or write 1 to clear [1:1] RB_UIF_SUSPEND USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear [2:2] RB_UIF_HST_SOF host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear [3:3] RB_UIF_FIFO_OV FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear [4:4] RB_U_SIE_FREE RO, indicate USB SIE free status [5:5] read-only RB_U_TOG_OK RO, indicate current USB transfer toggle is OK [6:6] read-only RB_U_IS_NAK RO, indicate current USB transfer is NAK received [7:7] read-only R8_USB_INT_ST USB interrupt status 0x07 8 read-only MASK_UIS_H_RES__MASK_UIS_ENDP RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received;RO, bit mask of current transfer endpoint number for USB device mode [3:0] MASK_UIS_TOKEN RO, bit mask of current token PID code received for USB device mode [5:4] RB_UIS_TOG_OK RO, indicate current USB transfer toggle is OK [6:6] RB_UIS_IS_NAK RO, indicate current USB transfer is NAK received for USB device mode [7:7] R8_USB_RX_LEN USB receiving length 0x08 8 read-only R8_UEP4_1_MOD endpoint 4/1 mode 0x0C 8 read-write RB_UEP4_TX_EN enable USB endpoint 4 transmittal (IN) [2:2] RB_UEP4_RX_EN enable USB endpoint 4 receiving (OUT) [3:3] RB_UEP1_BUF_MOD buffer mode of USB endpoint 1 [4:4] RB_UEP1_TX_EN enable USB endpoint 1 transmittal (IN) [6:6] RB_UEP1_RX_EN enable USB endpoint 1 receiving (OUT) [7:7] R8_UEP2_3_MOD__R8_UH_EP_MOD endpoint 2/3 mode;host endpoint mode 0x0D 8 read-write RB_UEP2_BUF_MOD__RB_UH_EP_RBUF_MOD buffer mode of USB endpoint 2;buffer mode of USB host IN endpoint [0:0] RB_UEP2_TX_EN enable USB endpoint 2 transmittal (IN) [2:2] RB_UEP2_RX_EN__RB_UH_EP_RX_EN enable USB endpoint 2 receiving (OUT);enable USB host IN endpoint receiving [3:3] RB_UEP3_BUF_MOD__RB_UH_EP_TBUF_MOD buffer mode of USB endpoint 3;buffer mode of USB host OUT endpoint [4:4] RB_UEP3_TX_EN__RB_UH_EP_TX_EN enable USB endpoint 3 transmittal (IN);enable USB host OUT endpoint transmittal [6:6] RB_UEP3_RX_EN enable USB endpoint 3 receiving (OUT) [7:7] R16_UEP0_DMA endpoint 0 DMA buffer address 0x10 16 read-write R16_UEP1_DMA endpoint 1 DMA buffer address 0x14 16 read-write R16_UEP2_DMA__R16_UH_RX_DMA endpoint 2 DMA buffer address;host rx endpoint buffer high address 0x18 16 read-write R16_UEP3_DMA__R16_UH_TX_DMA endpoint 3 DMA buffer address;host tx endpoint buffer high address 0x1C 16 read-write R8_UEP0_T_LEN endpoint 0 transmittal length 0x20 8 read-write R8_UEP0_CTRL endpoint 0 control 0x22 8 read-write MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) [1:0] MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) [3:2] RB_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle [4:4] RB_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 [6:6] RB_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 [7:7] R8_UEP1_T_LEN endpoint 1 transmittal length 0x24 8 read-write R8_UEP1_CTRL__R8_UH_SETUP endpoint 1 control;host aux setup 0x26 8 read-write MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) [1:0] MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) [3:2] RB_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle [4:4] RB_UEP_T_TOG__RB_UH_SOF_EN prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1;USB host automatic SOF enable [6:6] RB_UEP_R_TOG__RB_UH_PRE_PID_EN expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;RB_UH_PRE_PID_EN;USB host PRE PID enable for low speed device via hub [7:7] R8_UEP2_T_LEN__R8_UH_EP_PID endpoint 2 transmittal length;host endpoint and PID 0x28 8 read-write MASK_UH_ENDP bit mask of endpoint number for USB host transfer [3:0] MASK_UH_TOKEN bit mask of token PID for USB host transfer [7:4] R8_UEP2_CTRL__R8_UH_RX_CTRL endpoint 2 control;host receiver endpoint control 0x2A 8 read-write MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) [1:0] MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) [3:2] RB_UEP_AUTO_TOG__RB_UH_R_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle;enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle [4:4] RB_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 [6:6] RB_UEP_R_TOG__RB_UH_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1;expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 [7:7] R8_UEP3_T_LEN__R8_UH_TX_LEN endpoint 3 transmittal length;host transmittal endpoint transmittal length 0x2C 8 read-write R8_UEP3_CTRL__R8_UH_TX_CTRL endpoint 3 control;host transmittal endpoint control 0x2E 8 read-write MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) [1:0] MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) [3:2] RB_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle [4:4] RB_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 [6:6] RB_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 [7:7] R8_UEP4_T_LEN endpoint 4 transmittal length 0x30 8 read-write R8_UEP4_CTRL endpoint 4 control 0x32 8 read-write MASK_UEP_T_RES bit mask of handshake response type for USB endpoint X transmittal (IN) [1:0] MASK_UEP_R_RES bit mask of handshake response type for USB endpoint X receiving (OUT) [3:2] RB_UEP_AUTO_TOG enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle [4:4] RB_UEP_T_TOG prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 [6:6] RB_UEP_R_TOG expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 [7:7] R8_USB_TYPE_C_CTRL USB type-C control 0x38 8 read-write RB_UCC1_PU_EN USB CC1 pullup resistance control [1:0] RB_UCC1_PD_EN USB CC1 5.1K pulldown resistance: 0=disable, 1=enable pulldown [2:2] RB_VBUS_PD_EN USB VBUS 10K pulldown resistance: 0=disable, 1=enable pullup [3:3] RB_UCC2_PU_EN USB CC2 pullup resistance control [5:4] RB_UCC2_PD_EN USB CC2 5.1K pulldown resistance: 0=disable, 1=enable pulldown [6:6] RB_UTCC_GP_BIT USB general purpose bit [7:7] CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DATAR DATAR Data register 0x0 0x20 read-write 0xFFFFFFFF DATA Data Register 0 32 IDATAR IDATAR Independent Data register 0x4 0x20 read-write 0x00000000 IDATA Independent Data register 0 8 CTLR CTLR Control register 0x8 0x20 write-only 0x00000000 RST Reset bit 0 1 FLASH FLASH FLASH 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 20 ACTLR ACTLR Flash access control register 0x0 0x20 0x00000030 LATENCY Latency 0 3 read-write PRFTBE Prefetch buffer enable 4 1 read-write PRFTBS Prefetch buffer status 5 1 read-only KEYR KEYR Flash key register 0x4 0x20 write-only 0x00000000 KEYR FPEC key 0 32 OBKEYR OBKEYR Flash option key register 0x8 0x20 write-only 0x00000000 OBKEYR Option byte key 0 32 STATR STATR Status register 0xC 0x20 0x00000000 EOP End of operation 5 1 read-write WRPRTERR Write protection error 4 1 read-write PGERR Programming error 2 1 read-write BSY Busy 0 1 read-only CTLR CTLR Control register 0x10 0x20 read-write 0x00000080 PG Programming 0 1 PER Page Erase 1 1 MER Mass Erase 2 1 OBPG Option byte programming 4 1 OBER Option byte erase 5 1 STRT Start 6 1 LOCK Lock 7 1 OBWRE Option bytes write enable 9 1 ERRIE Error interrupt enable 10 1 EOPIE End of operation interrupt enable 12 1 FLOCK FAST programming lock 15 1 FTPG execute fast programming 16 1 FTER execute fast 128byte erase 17 1 BUFLOAD execute data load inner buffer 18 1 BUFRST execute inner buffer reset 19 1 ADDR ADDR Flash address register 0x14 0x20 write-only 0x00000000 FAR Flash Address 0 32 OBR OBR Option byte register 0x1C 0x20 read-only 0x03FFFFFC OPTERR Option byte error 0 1 RDPRT Read protection 1 1 IWDG_SW IWDG_SW 2 1 nRST_STOP nRST_STOP 3 1 nRST_STDBY nRST_STDBY 4 1 USBD_MODE USBD compatible speed mode configure 5 1 USBD_PU USBD compatible inner pull up resistance configure 6 1 POR_CTR Power on reset time 7 1 Data0 Data0 10 8 Data1 Data1 18 8 WPR WPR Write protection register 0x20 0x20 read-only 0xFFFFFFFF WRP Write protect 0 32 MODEKEYR MODEKEYR Extension key register 0x24 0x20 write-only 0x00000000 MODEKEYR high speed write /erase mode ENABLE 0 32 PFIC Programmable Fast Interrupt Controller PFIC 0xE000E000 0x00 0x1100 registers ISR1 ISR1 Interrupt Status Register 0x00 0x20 read-only 0x00000000 INTENSTA2_3 Interrupt ID Status 2 2 INTENSTA12_31 Interrupt ID Status 12 20 ISR2 ISR2 Interrupt Status Register 0x04 0x20 read-only 0x00000000 INTENSTA Interrupt ID Status 0 28 IPR1 IPR1 Interrupt Pending Register 0x20 0x20 read-only 0x00000000 PENDSTA2_3 PENDSTA 2 2 PENDSTA12_31 PENDSTA 12 20 IPR2 IPR2 Interrupt Pending Register 0x24 0x20 read-only 0x00000000 PENDSTA PENDSTA 0 28 ITHRESDR ITHRESDR Interrupt Priority Register 0x40 0x20 read-write 0x00000000 THRESHOLD THRESHOLD 0 8 FIBADDRR FIBADDRR Interrupt Fast Address Register 0x44 0x20 read-write 0x00000000 BASEADDR BASEADDR 28 4 CFGR CFGR Interrupt Config Register 0x48 0x20 0x00000000 HWSTKCTRL HWSTKCTRL read-write 0 1 NESTCTRL NESTCTRL read-write 1 1 NMISET NMISET write-only 2 1 NMIRESET NMIRESET write-only 3 1 EXCSET EXCSET write-only 4 1 EXCRESET EXCRESET write-only 5 1 PFICRSET PFICRSET write-only 6 1 SYSRESET SYSRESET write-only 7 1 KEYCODE KEYCODE write-only 16 16 GISR GISR Interrupt Global Register 0x4C 0x20 read-only 0x00000000 NESTSTA NESTSTA 0 8 GACTSTA GACTSTA 8 1 GPENDSTA GPENDSTA 9 1 FIFOADDRR0 FIFOADDRR0 Interrupt 0 address Register 0x60 0x20 read-write 0x00000000 OFFADDR0 OFFADDR0 0 24 IRQID0 IRQID0 24 8 FIFOADDRR1 FIFOADDRR1 Interrupt 1 address Register 0x64 0x20 read-write 0x00000000 OFFADDR1 OFFADDR1 0 24 IRQID1 IRQID1 24 8 FIFOADDRR2 FIFOADDRR2 Interrupt 2 address Register 0x68 0x20 read-write 0x00000000 OFFADDR2 OFFADDR2 0 24 IRQID2 IRQID2 24 8 FIFOADDRR3 FIFOADDRR3 Interrupt 3 address Register 0x6C 0x20 read-write 0x00000000 OFFADDR3 OFFADDR3 0 24 IRQID3 IRQID3 24 8 IENR1 IENR1 Interrupt Setting Register 0x100 0x20 read-write 0x00000000 INTEN INTEN 12 20 IENR2 IENR2 Interrupt Setting Register 0x104 0x20 read-write 0x00000000 INTEN INTEN 0 28 IRER1 IRER1 Interrupt Clear Register 0x180 0x20 read-write 0x00000000 INTRSET INTRSET 12 20 IRER2 IRER2 Interrupt Clear Register 0x184 0x20 read-write 0x00000000 INTRSET INTRSET 0 28 IPSR1 IPSR1 Interrupt Pending Register 0x200 0x20 read-write 0x00000000 PENDSET2_3 PENDSET 2 2 PENDSET12_31 PENDSET 12 20 IPSR2 IPSR2 Interrupt Pending Register 0x204 0x20 read-write 0x00000000 PENDSET PENDSET 0 28 IPRR1 IPRR1 Interrupt Pending Clear Register 0x280 0x20 read-write 0x00000000 PENDRESET2_3 PENDRESET 2 2 PENDRESET12_31 PENDRESET 12 20 IPRR2 IPRR2 Interrupt Pending Clear Register 0x284 0x20 read-write 0x00000000 PENDRESET PENDRESET 0 28 IACTR1 IACTR1 Interrupt ACTIVE Register 0x300 0x20 read-write 0x00000000 IACTS IACTS 12 20 IACTR2 IACTR2 Interrupt ACTIVE Register 0x304 0x20 read-write 0x00000000 IACTS IACTS 0 28 SCTLR SCTLR System Control Register 0xD10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 WFITOWFE WFITOWFE 3 1 SEVONPEND SEVONPEND 4 1 SETEVENT SETEVENT 5 1 STK_CTLR STK_CTLR STK_CTLR Register 0x1000 0x20 0x00000000 STE STE read-write 0 28 USBD Universal serial bus full-speed device interface USB 0x40005C00 0x00 0x400 registers USB_FS_WKUP USB Device FS Wakeup through EXTI line interrupt 58 EP0R EP0R endpoint 0 register 0x00 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP1R EP1R endpoint 1 register 0x04 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP2R EP2R endpoint 2 register 0x08 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP3R EP3R endpoint 3 register 0x0C 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP4R EP4R endpoint 4 register 0x10 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP5R EP5R endpoint 5 register 0x14 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP6R EP6R endpoint 6 register 0x18 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 EP7R EP7R endpoint 7 register 0x1C 0x10 read-write 0x0000 EA Endpoint address 0 4 STAT_TX Status bits, for transmission transfers 4 2 DTOG_TX Data Toggle, for transmission transfers 6 1 CTR_TX Correct Transfer for transmission 7 1 EP_KIND Endpoint kind 8 1 EP_TYPE Endpoint type 9 2 SETUP Setup transaction completed 11 1 STAT_RX Status bits, for reception transfers 12 2 DTOG_RX Data Toggle, for reception transfers 14 1 CTR_RX Correct transfer for reception 15 1 CNTR USB_CNTR control register 0x40 0x10 read-write 0x0003 FRES Force USB Reset 0 1 PDWN Power down 1 1 LPMODE Low-power mode 2 1 FSUSP Force suspend 3 1 RESUME Resume request 4 1 ESOFM Expected start of frame interrupt mask 8 1 SOFM Start of frame interrupt mask 9 1 RESETM USB reset interrupt mask 10 1 SUSPM Suspend mode interrupt mask 11 1 WKUPM Wakeup interrupt mask 12 1 ERRM Error interrupt mask 13 1 PMAOVRM Packet memory area over / underrun interrupt mask 14 1 CTRM Correct transfer interrupt mask 15 1 ISTR ISTR interrupt status register 0x44 0x10 read-write 0x0000 EP_ID Endpoint Identifier 0 4 DIR Direction of transaction 4 1 ESOF Expected start frame 8 1 SOF start of frame 9 1 RESET reset request 10 1 SUSP Suspend mode request 11 1 WKUP Wakeup 12 1 ERR Error 13 1 PMAOVR Packet memory area over / underrun 14 1 CTR Correct transfer 15 1 FNR FNR frame number register 0x48 0x10 read-only 0x0000 FN Frame number 0 11 LSOF Lost SOF 11 2 LCK Locked 13 1 RXDM Receive data - line status 14 1 RXDP Receive data + line status 15 1 DADDR DADDR device address 0x4C 0x10 read-write 0x0000 ADD Device address 0 7 EF Enable function 7 1 BTABLE BTABLE Buffer table address 0x50 0x10 read-write 0x0000 BTABLE Buffer table 3 13